drivers/gpu/drm/exynos/exynos_drm_scaler.c

   1 /*
   2  * Copyright (C) 2017 Samsung Electronics Co.Ltd
   3  * Author:
   4  *      Andrzej Pietrasiewicz <andrzejtp2010@gmail.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundationr
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/component.h>
  13 #include <linux/err.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/io.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/clk.h>
  18 #include <linux/of_device.h>
  19 #include <linux/pm_runtime.h>
  20
  21 #include <drm/drmP.h>
  22 #include <drm/exynos_drm.h>
  23 #include "regs-scaler.h"
  24 #include "exynos_drm_fb.h"
  25 #include "exynos_drm_drv.h"
  26 #include "exynos_drm_ipp.h"
  27
  28 #define scaler_read(offset)             readl(scaler->regs + (offset))
  29 #define scaler_write(cfg, offset)       writel(cfg, scaler->regs + (offset))
  30 #define SCALER_MAX_CLK                  4
  31 #define SCALER_AUTOSUSPEND_DELAY        2000
  32 #define SCALER_RESET_WAIT_RETRIES       100
  33
  34 struct scaler_data {
  35         const char      *clk_name[SCALER_MAX_CLK];
  36         unsigned int    num_clk;
  37         const struct exynos_drm_ipp_formats *formats;
  38         unsigned int    num_formats;
  39 };
  40
  41 struct scaler_context {
  42         struct exynos_drm_ipp           ipp;
  43         struct drm_device               *drm_dev;
  44         struct device                   *dev;
  45         void __iomem                    *regs;
  46         struct clk                      *clock[SCALER_MAX_CLK];
  47         struct exynos_drm_ipp_task      *task;
  48         const struct scaler_data        *scaler_data;
  49 };
  50
  51 struct scaler_format {
  52         u32     drm_fmt;
  53         u32     internal_fmt;
  54         u32     chroma_tile_w;
  55         u32     chroma_tile_h;
  56 };
  57
  58 static const struct scaler_format scaler_formats[] = {
  59         { DRM_FORMAT_NV12, SCALER_YUV420_2P_UV, 8, 8 },
  60         { DRM_FORMAT_NV21, SCALER_YUV420_2P_VU, 8, 8 },
  61         { DRM_FORMAT_YUV420, SCALER_YUV420_3P, 8, 8 },
  62         { DRM_FORMAT_YUYV, SCALER_YUV422_1P_YUYV, 16, 16 },
  63         { DRM_FORMAT_UYVY, SCALER_YUV422_1P_UYVY, 16, 16 },
  64         { DRM_FORMAT_YVYU, SCALER_YUV422_1P_YVYU, 16, 16 },
  65         { DRM_FORMAT_NV16, SCALER_YUV422_2P_UV, 8, 16 },
  66         { DRM_FORMAT_NV61, SCALER_YUV422_2P_VU, 8, 16 },
  67         { DRM_FORMAT_YUV422, SCALER_YUV422_3P, 8, 16 },
  68         { DRM_FORMAT_NV24, SCALER_YUV444_2P_UV, 16, 16 },
  69         { DRM_FORMAT_NV42, SCALER_YUV444_2P_VU, 16, 16 },
  70         { DRM_FORMAT_YUV444, SCALER_YUV444_3P, 16, 16 },
  71         { DRM_FORMAT_RGB565, SCALER_RGB_565, 0, 0 },
  72         { DRM_FORMAT_XRGB1555, SCALER_ARGB1555, 0, 0 },
  73         { DRM_FORMAT_ARGB1555, SCALER_ARGB1555, 0, 0 },
  74         { DRM_FORMAT_XRGB4444, SCALER_ARGB4444, 0, 0 },
  75         { DRM_FORMAT_ARGB4444, SCALER_ARGB4444, 0, 0 },
  76         { DRM_FORMAT_XRGB8888, SCALER_ARGB8888, 0, 0 },
  77         { DRM_FORMAT_ARGB8888, SCALER_ARGB8888, 0, 0 },
  78         { DRM_FORMAT_RGBX8888, SCALER_RGBA8888, 0, 0 },
  79         { DRM_FORMAT_RGBA8888, SCALER_RGBA8888, 0, 0 },
  80 };
  81
  82 static const struct scaler_format *scaler_get_format(u32 drm_fmt)
  83 {
  84         int i;
  85
  86         for (i = 0; i < ARRAY_SIZE(scaler_formats); i++)
  87                 if (scaler_formats[i].drm_fmt == drm_fmt)
  88                         return &scaler_formats[i];
  89
  90         return NULL;
  91 }
  92
  93 static inline int scaler_reset(struct scaler_context *scaler)
  94 {
  95         int retry = SCALER_RESET_WAIT_RETRIES;
  96
  97         scaler_write(SCALER_CFG_SOFT_RESET, SCALER_CFG);
  98         do {
  99                 cpu_relax();
 100         } while (retry > 1 &&
 101                  scaler_read(SCALER_CFG) & SCALER_CFG_SOFT_RESET);
 102         do {
 103                 cpu_relax();
 104                 scaler_write(1, SCALER_INT_EN);
 105         } while (retry > 0 && scaler_read(SCALER_INT_EN) != 1);
 106
 107         return retry ? 0 : -EIO;
 108 }
 109
 110 static inline void scaler_enable_int(struct scaler_context *scaler)
 111 {
 112         u32 val;
 113
 114         val = SCALER_INT_EN_TIMEOUT |
 115                 SCALER_INT_EN_ILLEGAL_BLEND |
 116                 SCALER_INT_EN_ILLEGAL_RATIO |
 117                 SCALER_INT_EN_ILLEGAL_DST_HEIGHT |
 118                 SCALER_INT_EN_ILLEGAL_DST_WIDTH |
 119                 SCALER_INT_EN_ILLEGAL_DST_V_POS |
 120                 SCALER_INT_EN_ILLEGAL_DST_H_POS |
 121                 SCALER_INT_EN_ILLEGAL_DST_C_SPAN |
 122                 SCALER_INT_EN_ILLEGAL_DST_Y_SPAN |
 123                 SCALER_INT_EN_ILLEGAL_DST_CR_BASE |
 124                 SCALER_INT_EN_ILLEGAL_DST_CB_BASE |
 125                 SCALER_INT_EN_ILLEGAL_DST_Y_BASE |
 126                 SCALER_INT_EN_ILLEGAL_DST_COLOR |
 127                 SCALER_INT_EN_ILLEGAL_SRC_HEIGHT |
 128                 SCALER_INT_EN_ILLEGAL_SRC_WIDTH |
 129                 SCALER_INT_EN_ILLEGAL_SRC_CV_POS |
 130                 SCALER_INT_EN_ILLEGAL_SRC_CH_POS |
 131                 SCALER_INT_EN_ILLEGAL_SRC_YV_POS |
 132                 SCALER_INT_EN_ILLEGAL_SRC_YH_POS |
 133                 SCALER_INT_EN_ILLEGAL_DST_SPAN |
 134                 SCALER_INT_EN_ILLEGAL_SRC_Y_SPAN |
 135                 SCALER_INT_EN_ILLEGAL_SRC_CR_BASE |
 136                 SCALER_INT_EN_ILLEGAL_SRC_CB_BASE |
 137                 SCALER_INT_EN_ILLEGAL_SRC_Y_BASE |
 138                 SCALER_INT_EN_ILLEGAL_SRC_COLOR |
 139                 SCALER_INT_EN_FRAME_END;
 140         scaler_write(val, SCALER_INT_EN);
 141 }
 142
 143 static inline void scaler_set_src_fmt(struct scaler_context *scaler,
 144         u32 src_fmt, u32 tile)
 145 {
 146         u32 val;
 147
 148         val = SCALER_SRC_CFG_SET_COLOR_FORMAT(src_fmt) | (tile << 10);
 149         scaler_write(val, SCALER_SRC_CFG);
 150 }
 151
 152 static inline void scaler_set_src_base(struct scaler_context *scaler,
 153         struct exynos_drm_ipp_buffer *src_buf)
 154 {
 155         static unsigned int bases[] = {
 156                 SCALER_SRC_Y_BASE,
 157                 SCALER_SRC_CB_BASE,
 158                 SCALER_SRC_CR_BASE,
 159         };
 160         int i;
 161
 162         for (i = 0; i < src_buf->format->num_planes; ++i)
 163                 scaler_write(src_buf->dma_addr[i], bases[i]);
 164 }
 165
 166 static inline void scaler_set_src_span(struct scaler_context *scaler,
 167         struct exynos_drm_ipp_buffer *src_buf)
 168 {
 169         u32 val;
 170
 171         val = SCALER_SRC_SPAN_SET_Y_SPAN(src_buf->buf.pitch[0] /
 172                 src_buf->format->cpp[0]);
 173
 174         if (src_buf->format->num_planes > 1)
 175                 val |= SCALER_SRC_SPAN_SET_C_SPAN(src_buf->buf.pitch[1]);
 176
 177         scaler_write(val, SCALER_SRC_SPAN);
 178 }
 179
 180 static inline void scaler_set_src_luma_chroma_pos(struct scaler_context *scaler,
 181                         struct drm_exynos_ipp_task_rect *src_pos,
 182                         const struct scaler_format *fmt)
 183 {
 184         u32 val;
 185
 186         val = SCALER_SRC_Y_POS_SET_YH_POS(src_pos->x << 2);
 187         val |=  SCALER_SRC_Y_POS_SET_YV_POS(src_pos->y << 2);
 188         scaler_write(val, SCALER_SRC_Y_POS);
 189         val = SCALER_SRC_C_POS_SET_CH_POS(
 190                 (src_pos->x * fmt->chroma_tile_w / 16) << 2);
 191         val |=  SCALER_SRC_C_POS_SET_CV_POS(
 192                 (src_pos->y * fmt->chroma_tile_h / 16) << 2);
 193         scaler_write(val, SCALER_SRC_C_POS);
 194 }
 195
 196 static inline void scaler_set_src_wh(struct scaler_context *scaler,
 197         struct drm_exynos_ipp_task_rect *src_pos)
 198 {
 199         u32 val;
 200
 201         val = SCALER_SRC_WH_SET_WIDTH(src_pos->w);
 202         val |= SCALER_SRC_WH_SET_HEIGHT(src_pos->h);
 203         scaler_write(val, SCALER_SRC_WH);
 204 }
 205
 206 static inline void scaler_set_dst_fmt(struct scaler_context *scaler,
 207         u32 dst_fmt)
 208 {
 209         u32 val;
 210
 211         val = SCALER_DST_CFG_SET_COLOR_FORMAT(dst_fmt);
 212         scaler_write(val, SCALER_DST_CFG);
 213 }
 214
 215 static inline void scaler_set_dst_base(struct scaler_context *scaler,
 216         struct exynos_drm_ipp_buffer *dst_buf)
 217 {
 218         static unsigned int bases[] = {
 219                 SCALER_DST_Y_BASE,
 220                 SCALER_DST_CB_BASE,
 221                 SCALER_DST_CR_BASE,
 222         };
 223         int i;
 224
 225         for (i = 0; i < dst_buf->format->num_planes; ++i)
 226                 scaler_write(dst_buf->dma_addr[i], bases[i]);
 227 }
 228
 229 static inline void scaler_set_dst_span(struct scaler_context *scaler,
 230         struct exynos_drm_ipp_buffer *dst_buf)
 231 {
 232         u32 val;
 233
 234         val = SCALER_DST_SPAN_SET_Y_SPAN(dst_buf->buf.pitch[0] /
 235                 dst_buf->format->cpp[0]);
 236
 237         if (dst_buf->format->num_planes > 1)
 238                 val |= SCALER_DST_SPAN_SET_C_SPAN(dst_buf->buf.pitch[1]);
 239
 240         scaler_write(val, SCALER_DST_SPAN);
 241 }
 242
 243 static inline void scaler_set_dst_luma_pos(struct scaler_context *scaler,
 244         struct drm_exynos_ipp_task_rect *dst_pos)
 245 {
 246         u32 val;
 247
 248         val = SCALER_DST_WH_SET_WIDTH(dst_pos->w);
 249         val |= SCALER_DST_WH_SET_HEIGHT(dst_pos->h);
 250         scaler_write(val, SCALER_DST_WH);
 251 }
 252
 253 static inline void scaler_set_dst_wh(struct scaler_context *scaler,
 254         struct drm_exynos_ipp_task_rect *dst_pos)
 255 {
 256         u32 val;
 257
 258         val = SCALER_DST_POS_SET_H_POS(dst_pos->x);
 259         val |= SCALER_DST_POS_SET_V_POS(dst_pos->y);
 260         scaler_write(val, SCALER_DST_POS);
 261 }
 262
 263 static inline void scaler_set_hv_ratio(struct scaler_context *scaler,
 264         unsigned int rotation,
 265         struct drm_exynos_ipp_task_rect *src_pos,
 266         struct drm_exynos_ipp_task_rect *dst_pos)
 267 {
 268         u32 val, h_ratio, v_ratio;
 269
 270         if (drm_rotation_90_or_270(rotation)) {
 271                 h_ratio = (src_pos->h << 16) / dst_pos->w;
 272                 v_ratio = (src_pos->w << 16) / dst_pos->h;
 273         } else {
 274                 h_ratio = (src_pos->w << 16) / dst_pos->w;
 275                 v_ratio = (src_pos->h << 16) / dst_pos->h;
 276         }
 277
 278         val = SCALER_H_RATIO_SET(h_ratio);
 279         scaler_write(val, SCALER_H_RATIO);
 280
 281         val = SCALER_V_RATIO_SET(v_ratio);
 282         scaler_write(val, SCALER_V_RATIO);
 283 }
 284
 285 static inline void scaler_set_rotation(struct scaler_context *scaler,
 286         unsigned int rotation)
 287 {
 288         u32 val = 0;
 289
 290         if (rotation & DRM_MODE_ROTATE_90)
 291                 val |= SCALER_ROT_CFG_SET_ROTMODE(SCALER_ROT_MODE_90);
 292         else if (rotation & DRM_MODE_ROTATE_180)
 293                 val |= SCALER_ROT_CFG_SET_ROTMODE(SCALER_ROT_MODE_180);
 294         else if (rotation & DRM_MODE_ROTATE_270)
 295                 val |= SCALER_ROT_CFG_SET_ROTMODE(SCALER_ROT_MODE_270);
 296         if (rotation & DRM_MODE_REFLECT_X)
 297                 val |= SCALER_ROT_CFG_FLIP_X_EN;
 298         if (rotation & DRM_MODE_REFLECT_Y)
 299                 val |= SCALER_ROT_CFG_FLIP_Y_EN;
 300         scaler_write(val, SCALER_ROT_CFG);
 301 }
 302
 303 static inline void scaler_set_csc(struct scaler_context *scaler,
 304         const struct drm_format_info *fmt)
 305 {
 306         static const u32 csc_mtx[2][3][3] = {
 307                 { /* YCbCr to RGB */
 308                         {0x254, 0x000, 0x331},
 309                         {0x254, 0xf38, 0xe60},
 310                         {0x254, 0x409, 0x000},
 311                 },
 312                 { /* RGB to YCbCr */
 313                         {0x084, 0x102, 0x032},
 314                         {0xfb4, 0xf6b, 0x0e1},
 315                         {0x0e1, 0xf44, 0xfdc},
 316                 },
 317         };
 318         int i, j, dir;
 319
 320         switch (fmt->format) {
 321         case DRM_FORMAT_RGB565:
 322         case DRM_FORMAT_XRGB1555:
 323         case DRM_FORMAT_ARGB1555:
 324         case DRM_FORMAT_XRGB4444:
 325         case DRM_FORMAT_ARGB4444:
 326         case DRM_FORMAT_XRGB8888:
 327         case DRM_FORMAT_ARGB8888:
 328         case DRM_FORMAT_RGBX8888:
 329         case DRM_FORMAT_RGBA8888:
 330                 dir = 1;
 331                 break;
 332         default:
 333                 dir = 0;
 334         }
 335
 336         for (i = 0; i < 3; i++)
 337                 for (j = 0; j < 3; j++)
 338                         scaler_write(csc_mtx[dir][i][j], SCALER_CSC_COEF(j, i));
 339 }
 340
 341 static inline void scaler_set_timer(struct scaler_context *scaler,
 342         unsigned int timer, unsigned int divider)
 343 {
 344         u32 val;
 345
 346         val = SCALER_TIMEOUT_CTRL_TIMER_ENABLE;
 347         val |= SCALER_TIMEOUT_CTRL_SET_TIMER_VALUE(timer);
 348         val |= SCALER_TIMEOUT_CTRL_SET_TIMER_DIV(divider);
 349         scaler_write(val, SCALER_TIMEOUT_CTRL);
 350 }
 351
 352 static inline void scaler_start_hw(struct scaler_context *scaler)
 353 {
 354         scaler_write(SCALER_CFG_START_CMD, SCALER_CFG);
 355 }
 356
 357 static int scaler_commit(struct exynos_drm_ipp *ipp,
 358                           struct exynos_drm_ipp_task *task)
 359 {
 360         struct scaler_context *scaler =
 361                         container_of(ipp, struct scaler_context, ipp);
 362
 363         struct drm_exynos_ipp_task_rect *src_pos = &task->src.rect;
 364         struct drm_exynos_ipp_task_rect *dst_pos = &task->dst.rect;
 365         const struct scaler_format *src_fmt, *dst_fmt;
 366
 367         src_fmt = scaler_get_format(task->src.buf.fourcc);
 368         dst_fmt = scaler_get_format(task->dst.buf.fourcc);
 369
 370         pm_runtime_get_sync(scaler->dev);
 371         if (scaler_reset(scaler)) {
 372                 pm_runtime_put(scaler->dev);
 373                 return -EIO;
 374         }
 375
 376         scaler->task = task;
 377
 378         scaler_set_src_fmt(
 379                 scaler, src_fmt->internal_fmt, task->src.buf.modifier != 0);
 380         scaler_set_src_base(scaler, &task->src);
 381         scaler_set_src_span(scaler, &task->src);
 382         scaler_set_src_luma_chroma_pos(scaler, src_pos, src_fmt);
 383         scaler_set_src_wh(scaler, src_pos);
 384
 385         scaler_set_dst_fmt(scaler, dst_fmt->internal_fmt);
 386         scaler_set_dst_base(scaler, &task->dst);
 387         scaler_set_dst_span(scaler, &task->dst);
 388         scaler_set_dst_luma_pos(scaler, dst_pos);
 389         scaler_set_dst_wh(scaler, dst_pos);
 390
 391         scaler_set_hv_ratio(scaler, task->transform.rotation, src_pos, dst_pos);
 392         scaler_set_rotation(scaler, task->transform.rotation);
 393
 394         scaler_set_csc(scaler, task->src.format);
 395
 396         scaler_set_timer(scaler, 0xffff, 0xf);
 397
 398         scaler_enable_int(scaler);
 399         scaler_start_hw(scaler);
 400
 401         return 0;
 402 }
 403
 404 static struct exynos_drm_ipp_funcs ipp_funcs = {
 405         .commit = scaler_commit,
 406 };
 407
 408 static inline void scaler_disable_int(struct scaler_context *scaler)
 409 {
 410         scaler_write(0, SCALER_INT_EN);
 411 }
 412
 413 static inline u32 scaler_get_int_status(struct scaler_context *scaler)
 414 {
 415         u32 val = scaler_read(SCALER_INT_STATUS);
 416
 417         scaler_write(val, SCALER_INT_STATUS);
 418
 419         return val;
 420 }
 421
 422 static inline int scaler_task_done(u32 val)
 423 {
 424         return val & SCALER_INT_STATUS_FRAME_END ? 0 : -EINVAL;
 425 }
 426
 427 static irqreturn_t scaler_irq_handler(int irq, void *arg)
 428 {
 429         struct scaler_context *scaler = arg;
 430
 431         u32 val = scaler_get_int_status(scaler);
 432
 433         scaler_disable_int(scaler);
 434
 435         if (scaler->task) {
 436                 struct exynos_drm_ipp_task *task = scaler->task;
 437
 438                 scaler->task = NULL;
 439                 pm_runtime_mark_last_busy(scaler->dev);
 440                 pm_runtime_put_autosuspend(scaler->dev);
 441                 exynos_drm_ipp_task_done(task, scaler_task_done(val));
 442         }
 443
 444         return IRQ_HANDLED;
 445 }
 446
 447 static int scaler_bind(struct device *dev, struct device *master, void *data)
 448 {
 449         struct scaler_context *scaler = dev_get_drvdata(dev);
 450         struct drm_device *drm_dev = data;
 451         struct exynos_drm_ipp *ipp = &scaler->ipp;
 452
 453         scaler->drm_dev = drm_dev;
 454         exynos_drm_register_dma(drm_dev, dev);
 455
 456         exynos_drm_ipp_register(drm_dev, ipp, &ipp_funcs,
 457                         DRM_EXYNOS_IPP_CAP_CROP | DRM_EXYNOS_IPP_CAP_ROTATE |
 458                         DRM_EXYNOS_IPP_CAP_SCALE | DRM_EXYNOS_IPP_CAP_CONVERT,
 459                         scaler->scaler_data->formats,
 460                         scaler->scaler_data->num_formats, "scaler");
 461
 462         dev_info(dev, "The exynos scaler has been probed successfully\n");
 463
 464         return 0;
 465 }
 466
 467 static void scaler_unbind(struct device *dev, struct device *master,
 468                         void *data)
 469 {
 470         struct scaler_context *scaler = dev_get_drvdata(dev);
 471         struct drm_device *drm_dev = data;
 472         struct exynos_drm_ipp *ipp = &scaler->ipp;
 473
 474         exynos_drm_ipp_unregister(drm_dev, ipp);
 475         exynos_drm_unregister_dma(scaler->drm_dev, scaler->dev);
 476 }
 477
 478 static const struct component_ops scaler_component_ops = {
 479         .bind   = scaler_bind,
 480         .unbind = scaler_unbind,
 481 };
 482
 483 static int scaler_probe(struct platform_device *pdev)
 484 {
 485         struct device *dev = &pdev->dev;
 486         struct resource *regs_res;
 487         struct scaler_context *scaler;
 488         int irq;
 489         int ret, i;
 490
 491         scaler = devm_kzalloc(dev, sizeof(*scaler), GFP_KERNEL);
 492         if (!scaler)
 493                 return -ENOMEM;
 494
 495         scaler->scaler_data =
 496                 (struct scaler_data *)of_device_get_match_data(dev);
 497
 498         scaler->dev = dev;
 499         regs_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 500         scaler->regs = devm_ioremap_resource(dev, regs_res);
 501         if (IS_ERR(scaler->regs))
 502                 return PTR_ERR(scaler->regs);
 503
 504         irq = platform_get_irq(pdev, 0);
 505         if (irq < 0) {
 506                 dev_err(dev, "failed to get irq\n");
 507                 return irq;
 508         }
 509
 510         ret = devm_request_threaded_irq(dev, irq, NULL, scaler_irq_handler,
 511                                         IRQF_ONESHOT, "drm_scaler", scaler);
 512         if (ret < 0) {
 513                 dev_err(dev, "failed to request irq\n");
 514                 return ret;
 515         }
 516
 517         for (i = 0; i < scaler->scaler_data->num_clk; ++i) {
 518                 scaler->clock[i] = devm_clk_get(dev,
 519                                               scaler->scaler_data->clk_name[i]);
 520                 if (IS_ERR(scaler->clock[i])) {
 521                         dev_err(dev, "failed to get clock\n");
 522                         return PTR_ERR(scaler->clock[i]);
 523                 }
 524         }
 525
 526         pm_runtime_use_autosuspend(dev);
 527         pm_runtime_set_autosuspend_delay(dev, SCALER_AUTOSUSPEND_DELAY);
 528         pm_runtime_enable(dev);
 529         platform_set_drvdata(pdev, scaler);
 530
 531         ret = component_add(dev, &scaler_component_ops);
 532         if (ret)
 533                 goto err_ippdrv_register;
 534
 535         return 0;
 536
 537 err_ippdrv_register:
 538         pm_runtime_dont_use_autosuspend(dev);
 539         pm_runtime_disable(dev);
 540         return ret;
 541 }
 542
 543 static int scaler_remove(struct platform_device *pdev)
 544 {
 545         struct device *dev = &pdev->dev;
 546
 547         component_del(dev, &scaler_component_ops);
 548         pm_runtime_dont_use_autosuspend(dev);
 549         pm_runtime_disable(dev);
 550
 551         return 0;
 552 }
 553
 554 #ifdef CONFIG_PM
 555
 556 static int clk_disable_unprepare_wrapper(struct clk *clk)
 557 {
 558         clk_disable_unprepare(clk);
 559
 560         return 0;
 561 }
 562
 563 static int scaler_clk_ctrl(struct scaler_context *scaler, bool enable)
 564 {
 565         int (*clk_fun)(struct clk *clk), i;
 566
 567         clk_fun = enable ? clk_prepare_enable : clk_disable_unprepare_wrapper;
 568
 569         for (i = 0; i < scaler->scaler_data->num_clk; ++i)
 570                 clk_fun(scaler->clock[i]);
 571
 572         return 0;
 573 }
 574
 575 static int scaler_runtime_suspend(struct device *dev)
 576 {
 577         struct scaler_context *scaler = dev_get_drvdata(dev);
 578
 579         return  scaler_clk_ctrl(scaler, false);
 580 }
 581
 582 static int scaler_runtime_resume(struct device *dev)
 583 {
 584         struct scaler_context *scaler = dev_get_drvdata(dev);
 585
 586         return  scaler_clk_ctrl(scaler, true);
 587 }
 588 #endif
 589
 590 static const struct dev_pm_ops scaler_pm_ops = {
 591         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
 592                                 pm_runtime_force_resume)
 593         SET_RUNTIME_PM_OPS(scaler_runtime_suspend, scaler_runtime_resume, NULL)
 594 };
 595
 596 static const struct drm_exynos_ipp_limit scaler_5420_two_pixel_hv_limits[] = {
 597         { IPP_SIZE_LIMIT(BUFFER, .h = { 16, SZ_8K }, .v = { 16, SZ_8K }) },
 598         { IPP_SIZE_LIMIT(AREA, .h.align = 2, .v.align = 2) },
 599         { IPP_SCALE_LIMIT(.h = { 65536 * 1 / 4, 65536 * 16 },
 600                           .v = { 65536 * 1 / 4, 65536 * 16 }) },
 601 };
 602
 603 static const struct drm_exynos_ipp_limit scaler_5420_two_pixel_h_limits[] = {
 604         { IPP_SIZE_LIMIT(BUFFER, .h = { 16, SZ_8K }, .v = { 16, SZ_8K }) },
 605         { IPP_SIZE_LIMIT(AREA, .h.align = 2, .v.align = 1) },
 606         { IPP_SCALE_LIMIT(.h = { 65536 * 1 / 4, 65536 * 16 },
 607                           .v = { 65536 * 1 / 4, 65536 * 16 }) },
 608 };
 609
 610 static const struct drm_exynos_ipp_limit scaler_5420_one_pixel_limits[] = {
 611         { IPP_SIZE_LIMIT(BUFFER, .h = { 16, SZ_8K }, .v = { 16, SZ_8K }) },
 612         { IPP_SCALE_LIMIT(.h = { 65536 * 1 / 4, 65536 * 16 },
 613                           .v = { 65536 * 1 / 4, 65536 * 16 }) },
 614 };
 615
 616 static const struct drm_exynos_ipp_limit scaler_5420_tile_limits[] = {
 617         { IPP_SIZE_LIMIT(BUFFER, .h = { 16, SZ_8K }, .v = { 16, SZ_8K })},
 618         { IPP_SIZE_LIMIT(AREA, .h.align = 16, .v.align = 16) },
 619         { IPP_SCALE_LIMIT(.h = {1, 1}, .v = {1, 1})},
 620         { }
 621 };
 622
 623 #define IPP_SRCDST_TILE_FORMAT(f, l)    \
 624         IPP_SRCDST_MFORMAT(f, DRM_FORMAT_MOD_SAMSUNG_16_16_TILE, (l))
 625
 626 static const struct exynos_drm_ipp_formats exynos5420_formats[] = {
 627         /* SCALER_YUV420_2P_UV */
 628         { IPP_SRCDST_FORMAT(NV21, scaler_5420_two_pixel_hv_limits) },
 629
 630         /* SCALER_YUV420_2P_VU */
 631         { IPP_SRCDST_FORMAT(NV12, scaler_5420_two_pixel_hv_limits) },
 632
 633         /* SCALER_YUV420_3P */
 634         { IPP_SRCDST_FORMAT(YUV420, scaler_5420_two_pixel_hv_limits) },
 635
 636         /* SCALER_YUV422_1P_YUYV */
 637         { IPP_SRCDST_FORMAT(YUYV, scaler_5420_two_pixel_h_limits) },
 638
 639         /* SCALER_YUV422_1P_UYVY */
 640         { IPP_SRCDST_FORMAT(UYVY, scaler_5420_two_pixel_h_limits) },
 641
 642         /* SCALER_YUV422_1P_YVYU */
 643         { IPP_SRCDST_FORMAT(YVYU, scaler_5420_two_pixel_h_limits) },
 644
 645         /* SCALER_YUV422_2P_UV */
 646         { IPP_SRCDST_FORMAT(NV61, scaler_5420_two_pixel_h_limits) },
 647
 648         /* SCALER_YUV422_2P_VU */
 649         { IPP_SRCDST_FORMAT(NV16, scaler_5420_two_pixel_h_limits) },
 650
 651         /* SCALER_YUV422_3P */
 652         { IPP_SRCDST_FORMAT(YUV422, scaler_5420_two_pixel_h_limits) },
 653
 654         /* SCALER_YUV444_2P_UV */
 655         { IPP_SRCDST_FORMAT(NV42, scaler_5420_one_pixel_limits) },
 656
 657         /* SCALER_YUV444_2P_VU */
 658         { IPP_SRCDST_FORMAT(NV24, scaler_5420_one_pixel_limits) },
 659
 660         /* SCALER_YUV444_3P */
 661         { IPP_SRCDST_FORMAT(YUV444, scaler_5420_one_pixel_limits) },
 662
 663         /* SCALER_RGB_565 */
 664         { IPP_SRCDST_FORMAT(RGB565, scaler_5420_one_pixel_limits) },
 665
 666         /* SCALER_ARGB1555 */
 667         { IPP_SRCDST_FORMAT(XRGB1555, scaler_5420_one_pixel_limits) },
 668
 669         /* SCALER_ARGB1555 */
 670         { IPP_SRCDST_FORMAT(ARGB1555, scaler_5420_one_pixel_limits) },
 671
 672         /* SCALER_ARGB4444 */
 673         { IPP_SRCDST_FORMAT(XRGB4444, scaler_5420_one_pixel_limits) },
 674
 675         /* SCALER_ARGB4444 */
 676         { IPP_SRCDST_FORMAT(ARGB4444, scaler_5420_one_pixel_limits) },
 677
 678         /* SCALER_ARGB8888 */
 679         { IPP_SRCDST_FORMAT(XRGB8888, scaler_5420_one_pixel_limits) },
 680
 681         /* SCALER_ARGB8888 */
 682         { IPP_SRCDST_FORMAT(ARGB8888, scaler_5420_one_pixel_limits) },
 683
 684         /* SCALER_RGBA8888 */
 685         { IPP_SRCDST_FORMAT(RGBX8888, scaler_5420_one_pixel_limits) },
 686
 687         /* SCALER_RGBA8888 */
 688         { IPP_SRCDST_FORMAT(RGBA8888, scaler_5420_one_pixel_limits) },
 689
 690         /* SCALER_YUV420_2P_UV TILE */
 691         { IPP_SRCDST_TILE_FORMAT(NV21, scaler_5420_tile_limits) },
 692
 693         /* SCALER_YUV420_2P_VU TILE */
 694         { IPP_SRCDST_TILE_FORMAT(NV12, scaler_5420_tile_limits) },
 695
 696         /* SCALER_YUV420_3P TILE */
 697         { IPP_SRCDST_TILE_FORMAT(YUV420, scaler_5420_tile_limits) },
 698
 699         /* SCALER_YUV422_1P_YUYV TILE */
 700         { IPP_SRCDST_TILE_FORMAT(YUYV, scaler_5420_tile_limits) },
 701 };
 702
 703 static const struct scaler_data exynos5420_data = {
 704         .clk_name       = {"mscl"},
 705         .num_clk        = 1,
 706         .formats        = exynos5420_formats,
 707         .num_formats    = ARRAY_SIZE(exynos5420_formats),
 708 };
 709
 710 static const struct scaler_data exynos5433_data = {
 711         .clk_name       = {"pclk", "aclk", "aclk_xiu"},
 712         .num_clk        = 3,
 713         .formats        = exynos5420_formats, /* intentional */
 714         .num_formats    = ARRAY_SIZE(exynos5420_formats),
 715 };
 716
 717 static const struct of_device_id exynos_scaler_match[] = {
 718         {
 719                 .compatible = "samsung,exynos5420-scaler",
 720                 .data = &exynos5420_data,
 721         }, {
 722                 .compatible = "samsung,exynos5433-scaler",
 723                 .data = &exynos5433_data,
 724         }, {
 725         },
 726 };
 727 MODULE_DEVICE_TABLE(of, exynos_scaler_match);
 728
 729 struct platform_driver scaler_driver = {
 730         .probe          = scaler_probe,
 731         .remove         = scaler_remove,
 732         .driver         = {
 733                 .name   = "exynos-scaler",
 734                 .owner  = THIS_MODULE,
 735                 .pm     = &scaler_pm_ops,
 736                 .of_match_table = exynos_scaler_match,
 737         },
 738 };