2 * Copyright © 2018 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Madhav Chauhan <madhav.chauhan@intel.com>
25 * Jani Nikula <jani.nikula@intel.com>
28 #include <drm/display/drm_dsc_helper.h>
29 #include <drm/drm_atomic_helper.h>
30 #include <drm/drm_mipi_dsi.h>
34 #include "icl_dsi_regs.h"
35 #include "intel_atomic.h"
36 #include "intel_backlight.h"
37 #include "intel_backlight_regs.h"
38 #include "intel_combo_phy.h"
39 #include "intel_combo_phy_regs.h"
40 #include "intel_connector.h"
41 #include "intel_crtc.h"
42 #include "intel_ddi.h"
44 #include "intel_dsi.h"
45 #include "intel_dsi_vbt.h"
46 #include "intel_panel.h"
47 #include "intel_vdsc.h"
48 #include "intel_vdsc_regs.h"
49 #include "skl_scaler.h"
50 #include "skl_universal_plane.h"
52 static int header_credits_available(struct drm_i915_private
*dev_priv
,
53 enum transcoder dsi_trans
)
55 return (intel_de_read(dev_priv
, DSI_CMD_TXCTL(dsi_trans
)) & FREE_HEADER_CREDIT_MASK
)
56 >> FREE_HEADER_CREDIT_SHIFT
;
59 static int payload_credits_available(struct drm_i915_private
*dev_priv
,
60 enum transcoder dsi_trans
)
62 return (intel_de_read(dev_priv
, DSI_CMD_TXCTL(dsi_trans
)) & FREE_PLOAD_CREDIT_MASK
)
63 >> FREE_PLOAD_CREDIT_SHIFT
;
66 static bool wait_for_header_credits(struct drm_i915_private
*dev_priv
,
67 enum transcoder dsi_trans
, int hdr_credit
)
69 if (wait_for_us(header_credits_available(dev_priv
, dsi_trans
) >=
71 drm_err(&dev_priv
->drm
, "DSI header credits not released\n");
78 static bool wait_for_payload_credits(struct drm_i915_private
*dev_priv
,
79 enum transcoder dsi_trans
, int payld_credit
)
81 if (wait_for_us(payload_credits_available(dev_priv
, dsi_trans
) >=
83 drm_err(&dev_priv
->drm
, "DSI payload credits not released\n");
90 static enum transcoder
dsi_port_to_transcoder(enum port port
)
93 return TRANSCODER_DSI_0
;
95 return TRANSCODER_DSI_1
;
98 static void wait_for_cmds_dispatched_to_panel(struct intel_encoder
*encoder
)
100 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
101 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(encoder
);
102 struct mipi_dsi_device
*dsi
;
104 enum transcoder dsi_trans
;
107 /* wait for header/payload credits to be released */
108 for_each_dsi_port(port
, intel_dsi
->ports
) {
109 dsi_trans
= dsi_port_to_transcoder(port
);
110 wait_for_header_credits(dev_priv
, dsi_trans
, MAX_HEADER_CREDIT
);
111 wait_for_payload_credits(dev_priv
, dsi_trans
, MAX_PLOAD_CREDIT
);
114 /* send nop DCS command */
115 for_each_dsi_port(port
, intel_dsi
->ports
) {
116 dsi
= intel_dsi
->dsi_hosts
[port
]->device
;
117 dsi
->mode_flags
|= MIPI_DSI_MODE_LPM
;
119 ret
= mipi_dsi_dcs_nop(dsi
);
121 drm_err(&dev_priv
->drm
,
122 "error sending DCS NOP command\n");
125 /* wait for header credits to be released */
126 for_each_dsi_port(port
, intel_dsi
->ports
) {
127 dsi_trans
= dsi_port_to_transcoder(port
);
128 wait_for_header_credits(dev_priv
, dsi_trans
, MAX_HEADER_CREDIT
);
131 /* wait for LP TX in progress bit to be cleared */
132 for_each_dsi_port(port
, intel_dsi
->ports
) {
133 dsi_trans
= dsi_port_to_transcoder(port
);
134 if (wait_for_us(!(intel_de_read(dev_priv
, DSI_LP_MSG(dsi_trans
)) &
135 LPTX_IN_PROGRESS
), 20))
136 drm_err(&dev_priv
->drm
, "LPTX bit not cleared\n");
140 static int dsi_send_pkt_payld(struct intel_dsi_host
*host
,
141 const struct mipi_dsi_packet
*packet
)
143 struct intel_dsi
*intel_dsi
= host
->intel_dsi
;
144 struct drm_i915_private
*i915
= to_i915(intel_dsi
->base
.base
.dev
);
145 enum transcoder dsi_trans
= dsi_port_to_transcoder(host
->port
);
146 const u8
*data
= packet
->payload
;
147 u32 len
= packet
->payload_length
;
150 /* payload queue can accept *256 bytes*, check limit */
151 if (len
> MAX_PLOAD_CREDIT
* 4) {
152 drm_err(&i915
->drm
, "payload size exceeds max queue limit\n");
156 for (i
= 0; i
< len
; i
+= 4) {
159 if (!wait_for_payload_credits(i915
, dsi_trans
, 1))
162 for (j
= 0; j
< min_t(u32
, len
- i
, 4); j
++)
163 tmp
|= *data
++ << 8 * j
;
165 intel_de_write(i915
, DSI_CMD_TXPYLD(dsi_trans
), tmp
);
171 static int dsi_send_pkt_hdr(struct intel_dsi_host
*host
,
172 const struct mipi_dsi_packet
*packet
,
175 struct intel_dsi
*intel_dsi
= host
->intel_dsi
;
176 struct drm_i915_private
*dev_priv
= to_i915(intel_dsi
->base
.base
.dev
);
177 enum transcoder dsi_trans
= dsi_port_to_transcoder(host
->port
);
180 if (!wait_for_header_credits(dev_priv
, dsi_trans
, 1))
183 tmp
= intel_de_read(dev_priv
, DSI_CMD_TXHDR(dsi_trans
));
186 tmp
|= PAYLOAD_PRESENT
;
188 tmp
&= ~PAYLOAD_PRESENT
;
190 tmp
&= ~VBLANK_FENCE
;
193 tmp
|= LP_DATA_TRANSFER
;
195 tmp
&= ~LP_DATA_TRANSFER
;
197 tmp
&= ~(PARAM_WC_MASK
| VC_MASK
| DT_MASK
);
198 tmp
|= ((packet
->header
[0] & VC_MASK
) << VC_SHIFT
);
199 tmp
|= ((packet
->header
[0] & DT_MASK
) << DT_SHIFT
);
200 tmp
|= (packet
->header
[1] << PARAM_WC_LOWER_SHIFT
);
201 tmp
|= (packet
->header
[2] << PARAM_WC_UPPER_SHIFT
);
202 intel_de_write(dev_priv
, DSI_CMD_TXHDR(dsi_trans
), tmp
);
207 void icl_dsi_frame_update(struct intel_crtc_state
*crtc_state
)
209 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
210 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
214 mode_flags
= crtc_state
->mode_flags
;
217 * case 1 also covers dual link
218 * In case of dual link, frame update should be set on
221 if (mode_flags
& I915_MODE_FLAG_DSI_USE_TE0
)
223 else if (mode_flags
& I915_MODE_FLAG_DSI_USE_TE1
)
228 intel_de_rmw(dev_priv
, DSI_CMD_FRMCTL(port
), 0, DSI_FRAME_UPDATE_REQUEST
);
231 static void dsi_program_swing_and_deemphasis(struct intel_encoder
*encoder
)
233 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
234 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(encoder
);
239 for_each_dsi_phy(phy
, intel_dsi
->phys
) {
241 * Program voltage swing and pre-emphasis level values as per
242 * table in BSPEC under DDI buffer programing
244 mask
= SCALING_MODE_SEL_MASK
| RTERM_SELECT_MASK
;
245 val
= SCALING_MODE_SEL(0x2) | TAP2_DISABLE
| TAP3_DISABLE
|
247 tmp
= intel_de_read(dev_priv
, ICL_PORT_TX_DW5_LN(0, phy
));
250 intel_de_write(dev_priv
, ICL_PORT_TX_DW5_GRP(phy
), tmp
);
251 intel_de_rmw(dev_priv
, ICL_PORT_TX_DW5_AUX(phy
), mask
, val
);
253 mask
= SWING_SEL_LOWER_MASK
| SWING_SEL_UPPER_MASK
|
255 val
= SWING_SEL_UPPER(0x2) | SWING_SEL_LOWER(0x2) |
257 tmp
= intel_de_read(dev_priv
, ICL_PORT_TX_DW2_LN(0, phy
));
260 intel_de_write(dev_priv
, ICL_PORT_TX_DW2_GRP(phy
), tmp
);
261 intel_de_rmw(dev_priv
, ICL_PORT_TX_DW2_AUX(phy
), mask
, val
);
263 mask
= POST_CURSOR_1_MASK
| POST_CURSOR_2_MASK
|
265 val
= POST_CURSOR_1(0x0) | POST_CURSOR_2(0x0) |
267 intel_de_rmw(dev_priv
, ICL_PORT_TX_DW4_AUX(phy
), mask
, val
);
269 /* Bspec: must not use GRP register for write */
270 for (lane
= 0; lane
<= 3; lane
++)
271 intel_de_rmw(dev_priv
, ICL_PORT_TX_DW4_LN(lane
, phy
),
276 static void configure_dual_link_mode(struct intel_encoder
*encoder
,
277 const struct intel_crtc_state
*pipe_config
)
279 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
280 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(encoder
);
281 i915_reg_t dss_ctl1_reg
, dss_ctl2_reg
;
284 /* FIXME: Move all DSS handling to intel_vdsc.c */
285 if (DISPLAY_VER(dev_priv
) >= 12) {
286 struct intel_crtc
*crtc
= to_intel_crtc(pipe_config
->uapi
.crtc
);
288 dss_ctl1_reg
= ICL_PIPE_DSS_CTL1(crtc
->pipe
);
289 dss_ctl2_reg
= ICL_PIPE_DSS_CTL2(crtc
->pipe
);
291 dss_ctl1_reg
= DSS_CTL1
;
292 dss_ctl2_reg
= DSS_CTL2
;
295 dss_ctl1
= intel_de_read(dev_priv
, dss_ctl1_reg
);
296 dss_ctl1
|= SPLITTER_ENABLE
;
297 dss_ctl1
&= ~OVERLAP_PIXELS_MASK
;
298 dss_ctl1
|= OVERLAP_PIXELS(intel_dsi
->pixel_overlap
);
300 if (intel_dsi
->dual_link
== DSI_DUAL_LINK_FRONT_BACK
) {
301 const struct drm_display_mode
*adjusted_mode
=
302 &pipe_config
->hw
.adjusted_mode
;
303 u16 hactive
= adjusted_mode
->crtc_hdisplay
;
306 dss_ctl1
&= ~DUAL_LINK_MODE_INTERLEAVE
;
307 dl_buffer_depth
= hactive
/ 2 + intel_dsi
->pixel_overlap
;
309 if (dl_buffer_depth
> MAX_DL_BUFFER_TARGET_DEPTH
)
310 drm_err(&dev_priv
->drm
,
311 "DL buffer depth exceed max value\n");
313 dss_ctl1
&= ~LEFT_DL_BUF_TARGET_DEPTH_MASK
;
314 dss_ctl1
|= LEFT_DL_BUF_TARGET_DEPTH(dl_buffer_depth
);
315 intel_de_rmw(dev_priv
, dss_ctl2_reg
, RIGHT_DL_BUF_TARGET_DEPTH_MASK
,
316 RIGHT_DL_BUF_TARGET_DEPTH(dl_buffer_depth
));
319 dss_ctl1
|= DUAL_LINK_MODE_INTERLEAVE
;
322 intel_de_write(dev_priv
, dss_ctl1_reg
, dss_ctl1
);
325 /* aka DSI 8X clock */
326 static int afe_clk(struct intel_encoder
*encoder
,
327 const struct intel_crtc_state
*crtc_state
)
329 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(encoder
);
332 if (crtc_state
->dsc
.compression_enable
)
333 bpp
= crtc_state
->dsc
.compressed_bpp
;
335 bpp
= mipi_dsi_pixel_format_to_bpp(intel_dsi
->pixel_format
);
337 return DIV_ROUND_CLOSEST(intel_dsi
->pclk
* bpp
, intel_dsi
->lane_count
);
340 static void gen11_dsi_program_esc_clk_div(struct intel_encoder
*encoder
,
341 const struct intel_crtc_state
*crtc_state
)
343 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
344 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(encoder
);
347 int theo_word_clk
, act_word_clk
;
348 u32 esc_clk_div_m
, esc_clk_div_m_phy
;
350 afe_clk_khz
= afe_clk(encoder
, crtc_state
);
352 if (IS_ALDERLAKE_S(dev_priv
) || IS_ALDERLAKE_P(dev_priv
)) {
353 theo_word_clk
= DIV_ROUND_UP(afe_clk_khz
, 8 * DSI_MAX_ESC_CLK
);
354 act_word_clk
= max(3, theo_word_clk
+ (theo_word_clk
+ 1) % 2);
355 esc_clk_div_m
= act_word_clk
* 8;
356 esc_clk_div_m_phy
= (act_word_clk
- 1) / 2;
358 esc_clk_div_m
= DIV_ROUND_UP(afe_clk_khz
, DSI_MAX_ESC_CLK
);
361 for_each_dsi_port(port
, intel_dsi
->ports
) {
362 intel_de_write(dev_priv
, ICL_DSI_ESC_CLK_DIV(port
),
363 esc_clk_div_m
& ICL_ESC_CLK_DIV_MASK
);
364 intel_de_posting_read(dev_priv
, ICL_DSI_ESC_CLK_DIV(port
));
367 for_each_dsi_port(port
, intel_dsi
->ports
) {
368 intel_de_write(dev_priv
, ICL_DPHY_ESC_CLK_DIV(port
),
369 esc_clk_div_m
& ICL_ESC_CLK_DIV_MASK
);
370 intel_de_posting_read(dev_priv
, ICL_DPHY_ESC_CLK_DIV(port
));
373 if (IS_ALDERLAKE_S(dev_priv
) || IS_ALDERLAKE_P(dev_priv
)) {
374 for_each_dsi_port(port
, intel_dsi
->ports
) {
375 intel_de_write(dev_priv
, ADL_MIPIO_DW(port
, 8),
376 esc_clk_div_m_phy
& TX_ESC_CLK_DIV_PHY
);
377 intel_de_posting_read(dev_priv
, ADL_MIPIO_DW(port
, 8));
382 static void get_dsi_io_power_domains(struct drm_i915_private
*dev_priv
,
383 struct intel_dsi
*intel_dsi
)
387 for_each_dsi_port(port
, intel_dsi
->ports
) {
388 drm_WARN_ON(&dev_priv
->drm
, intel_dsi
->io_wakeref
[port
]);
389 intel_dsi
->io_wakeref
[port
] =
390 intel_display_power_get(dev_priv
,
392 POWER_DOMAIN_PORT_DDI_IO_A
:
393 POWER_DOMAIN_PORT_DDI_IO_B
);
397 static void gen11_dsi_enable_io_power(struct intel_encoder
*encoder
)
399 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
400 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(encoder
);
403 for_each_dsi_port(port
, intel_dsi
->ports
)
404 intel_de_rmw(dev_priv
, ICL_DSI_IO_MODECTL(port
),
405 0, COMBO_PHY_MODE_DSI
);
407 get_dsi_io_power_domains(dev_priv
, intel_dsi
);
410 static void gen11_dsi_power_up_lanes(struct intel_encoder
*encoder
)
412 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
413 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(encoder
);
416 for_each_dsi_phy(phy
, intel_dsi
->phys
)
417 intel_combo_phy_power_up_lanes(dev_priv
, phy
, true,
418 intel_dsi
->lane_count
, false);
421 static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder
*encoder
)
423 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
424 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(encoder
);
429 /* Step 4b(i) set loadgen select for transmit and aux lanes */
430 for_each_dsi_phy(phy
, intel_dsi
->phys
) {
431 intel_de_rmw(dev_priv
, ICL_PORT_TX_DW4_AUX(phy
), LOADGEN_SELECT
, 0);
432 for (lane
= 0; lane
<= 3; lane
++)
433 intel_de_rmw(dev_priv
, ICL_PORT_TX_DW4_LN(lane
, phy
),
434 LOADGEN_SELECT
, lane
!= 2 ? LOADGEN_SELECT
: 0);
437 /* Step 4b(ii) set latency optimization for transmit and aux lanes */
438 for_each_dsi_phy(phy
, intel_dsi
->phys
) {
439 intel_de_rmw(dev_priv
, ICL_PORT_TX_DW2_AUX(phy
),
440 FRC_LATENCY_OPTIM_MASK
, FRC_LATENCY_OPTIM_VAL(0x5));
441 tmp
= intel_de_read(dev_priv
, ICL_PORT_TX_DW2_LN(0, phy
));
442 tmp
&= ~FRC_LATENCY_OPTIM_MASK
;
443 tmp
|= FRC_LATENCY_OPTIM_VAL(0x5);
444 intel_de_write(dev_priv
, ICL_PORT_TX_DW2_GRP(phy
), tmp
);
446 /* For EHL, TGL, set latency optimization for PCS_DW1 lanes */
447 if (IS_JASPERLAKE(dev_priv
) || IS_ELKHARTLAKE(dev_priv
) ||
448 (DISPLAY_VER(dev_priv
) >= 12)) {
449 intel_de_rmw(dev_priv
, ICL_PORT_PCS_DW1_AUX(phy
),
450 LATENCY_OPTIM_MASK
, LATENCY_OPTIM_VAL(0));
452 tmp
= intel_de_read(dev_priv
,
453 ICL_PORT_PCS_DW1_LN(0, phy
));
454 tmp
&= ~LATENCY_OPTIM_MASK
;
455 tmp
|= LATENCY_OPTIM_VAL(0x1);
456 intel_de_write(dev_priv
, ICL_PORT_PCS_DW1_GRP(phy
),
463 static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder
*encoder
)
465 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
466 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(encoder
);
470 /* clear common keeper enable bit */
471 for_each_dsi_phy(phy
, intel_dsi
->phys
) {
472 tmp
= intel_de_read(dev_priv
, ICL_PORT_PCS_DW1_LN(0, phy
));
473 tmp
&= ~COMMON_KEEPER_EN
;
474 intel_de_write(dev_priv
, ICL_PORT_PCS_DW1_GRP(phy
), tmp
);
475 intel_de_rmw(dev_priv
, ICL_PORT_PCS_DW1_AUX(phy
), COMMON_KEEPER_EN
, 0);
479 * Set SUS Clock Config bitfield to 11b
480 * Note: loadgen select program is done
481 * as part of lane phy sequence configuration
483 for_each_dsi_phy(phy
, intel_dsi
->phys
)
484 intel_de_rmw(dev_priv
, ICL_PORT_CL_DW5(phy
), 0, SUS_CLOCK_CONFIG
);
486 /* Clear training enable to change swing values */
487 for_each_dsi_phy(phy
, intel_dsi
->phys
) {
488 tmp
= intel_de_read(dev_priv
, ICL_PORT_TX_DW5_LN(0, phy
));
489 tmp
&= ~TX_TRAINING_EN
;
490 intel_de_write(dev_priv
, ICL_PORT_TX_DW5_GRP(phy
), tmp
);
491 intel_de_rmw(dev_priv
, ICL_PORT_TX_DW5_AUX(phy
), TX_TRAINING_EN
, 0);
494 /* Program swing and de-emphasis */
495 dsi_program_swing_and_deemphasis(encoder
);
497 /* Set training enable to trigger update */
498 for_each_dsi_phy(phy
, intel_dsi
->phys
) {
499 tmp
= intel_de_read(dev_priv
, ICL_PORT_TX_DW5_LN(0, phy
));
500 tmp
|= TX_TRAINING_EN
;
501 intel_de_write(dev_priv
, ICL_PORT_TX_DW5_GRP(phy
), tmp
);
502 intel_de_rmw(dev_priv
, ICL_PORT_TX_DW5_AUX(phy
), 0, TX_TRAINING_EN
);
506 static void gen11_dsi_enable_ddi_buffer(struct intel_encoder
*encoder
)
508 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
509 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(encoder
);
512 for_each_dsi_port(port
, intel_dsi
->ports
) {
513 intel_de_rmw(dev_priv
, DDI_BUF_CTL(port
), 0, DDI_BUF_CTL_ENABLE
);
515 if (wait_for_us(!(intel_de_read(dev_priv
, DDI_BUF_CTL(port
)) &
518 drm_err(&dev_priv
->drm
, "DDI port:%c buffer idle\n",
524 gen11_dsi_setup_dphy_timings(struct intel_encoder
*encoder
,
525 const struct intel_crtc_state
*crtc_state
)
527 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
528 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(encoder
);
532 /* Program DPHY clock lanes timings */
533 for_each_dsi_port(port
, intel_dsi
->ports
)
534 intel_de_write(dev_priv
, DPHY_CLK_TIMING_PARAM(port
),
535 intel_dsi
->dphy_reg
);
537 /* Program DPHY data lanes timings */
538 for_each_dsi_port(port
, intel_dsi
->ports
)
539 intel_de_write(dev_priv
, DPHY_DATA_TIMING_PARAM(port
),
540 intel_dsi
->dphy_data_lane_reg
);
543 * If DSI link operating at or below an 800 MHz,
544 * TA_SURE should be override and programmed to
545 * a value '0' inside TA_PARAM_REGISTERS otherwise
546 * leave all fields at HW default values.
548 if (DISPLAY_VER(dev_priv
) == 11) {
549 if (afe_clk(encoder
, crtc_state
) <= 800000) {
550 for_each_dsi_port(port
, intel_dsi
->ports
)
551 intel_de_rmw(dev_priv
, DPHY_TA_TIMING_PARAM(port
),
553 TA_SURE_OVERRIDE
| TA_SURE(0));
557 if (IS_JASPERLAKE(dev_priv
) || IS_ELKHARTLAKE(dev_priv
)) {
558 for_each_dsi_phy(phy
, intel_dsi
->phys
)
559 intel_de_rmw(dev_priv
, ICL_DPHY_CHKN(phy
),
560 0, ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP
);
565 gen11_dsi_setup_timings(struct intel_encoder
*encoder
,
566 const struct intel_crtc_state
*crtc_state
)
568 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
569 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(encoder
);
572 /* Program T-INIT master registers */
573 for_each_dsi_port(port
, intel_dsi
->ports
)
574 intel_de_rmw(dev_priv
, ICL_DSI_T_INIT_MASTER(port
),
575 DSI_T_INIT_MASTER_MASK
, intel_dsi
->init_count
);
577 /* shadow register inside display core */
578 for_each_dsi_port(port
, intel_dsi
->ports
)
579 intel_de_write(dev_priv
, DSI_CLK_TIMING_PARAM(port
),
580 intel_dsi
->dphy_reg
);
582 /* shadow register inside display core */
583 for_each_dsi_port(port
, intel_dsi
->ports
)
584 intel_de_write(dev_priv
, DSI_DATA_TIMING_PARAM(port
),
585 intel_dsi
->dphy_data_lane_reg
);
587 /* shadow register inside display core */
588 if (DISPLAY_VER(dev_priv
) == 11) {
589 if (afe_clk(encoder
, crtc_state
) <= 800000) {
590 for_each_dsi_port(port
, intel_dsi
->ports
) {
591 intel_de_rmw(dev_priv
, DSI_TA_TIMING_PARAM(port
),
593 TA_SURE_OVERRIDE
| TA_SURE(0));
599 static void gen11_dsi_gate_clocks(struct intel_encoder
*encoder
)
601 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
602 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(encoder
);
606 mutex_lock(&dev_priv
->display
.dpll
.lock
);
607 tmp
= intel_de_read(dev_priv
, ICL_DPCLKA_CFGCR0
);
608 for_each_dsi_phy(phy
, intel_dsi
->phys
)
609 tmp
|= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy
);
611 intel_de_write(dev_priv
, ICL_DPCLKA_CFGCR0
, tmp
);
612 mutex_unlock(&dev_priv
->display
.dpll
.lock
);
615 static void gen11_dsi_ungate_clocks(struct intel_encoder
*encoder
)
617 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
618 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(encoder
);
622 mutex_lock(&dev_priv
->display
.dpll
.lock
);
623 tmp
= intel_de_read(dev_priv
, ICL_DPCLKA_CFGCR0
);
624 for_each_dsi_phy(phy
, intel_dsi
->phys
)
625 tmp
&= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy
);
627 intel_de_write(dev_priv
, ICL_DPCLKA_CFGCR0
, tmp
);
628 mutex_unlock(&dev_priv
->display
.dpll
.lock
);
631 static bool gen11_dsi_is_clock_enabled(struct intel_encoder
*encoder
)
633 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
634 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(encoder
);
635 bool clock_enabled
= false;
639 tmp
= intel_de_read(dev_priv
, ICL_DPCLKA_CFGCR0
);
641 for_each_dsi_phy(phy
, intel_dsi
->phys
) {
642 if (!(tmp
& ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy
)))
643 clock_enabled
= true;
646 return clock_enabled
;
649 static void gen11_dsi_map_pll(struct intel_encoder
*encoder
,
650 const struct intel_crtc_state
*crtc_state
)
652 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
653 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(encoder
);
654 struct intel_shared_dpll
*pll
= crtc_state
->shared_dpll
;
658 mutex_lock(&dev_priv
->display
.dpll
.lock
);
660 val
= intel_de_read(dev_priv
, ICL_DPCLKA_CFGCR0
);
661 for_each_dsi_phy(phy
, intel_dsi
->phys
) {
662 val
&= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy
);
663 val
|= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll
->info
->id
, phy
);
665 intel_de_write(dev_priv
, ICL_DPCLKA_CFGCR0
, val
);
667 for_each_dsi_phy(phy
, intel_dsi
->phys
) {
668 val
&= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy
);
670 intel_de_write(dev_priv
, ICL_DPCLKA_CFGCR0
, val
);
672 intel_de_posting_read(dev_priv
, ICL_DPCLKA_CFGCR0
);
674 mutex_unlock(&dev_priv
->display
.dpll
.lock
);
678 gen11_dsi_configure_transcoder(struct intel_encoder
*encoder
,
679 const struct intel_crtc_state
*pipe_config
)
681 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
682 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(encoder
);
683 struct intel_crtc
*crtc
= to_intel_crtc(pipe_config
->uapi
.crtc
);
684 enum pipe pipe
= crtc
->pipe
;
687 enum transcoder dsi_trans
;
689 for_each_dsi_port(port
, intel_dsi
->ports
) {
690 dsi_trans
= dsi_port_to_transcoder(port
);
691 tmp
= intel_de_read(dev_priv
, DSI_TRANS_FUNC_CONF(dsi_trans
));
693 if (intel_dsi
->eotp_pkt
)
694 tmp
&= ~EOTP_DISABLED
;
696 tmp
|= EOTP_DISABLED
;
698 /* enable link calibration if freq > 1.5Gbps */
699 if (afe_clk(encoder
, pipe_config
) >= 1500 * 1000) {
700 tmp
&= ~LINK_CALIBRATION_MASK
;
701 tmp
|= CALIBRATION_ENABLED_INITIAL_ONLY
;
704 /* configure continuous clock */
705 tmp
&= ~CONTINUOUS_CLK_MASK
;
706 if (intel_dsi
->clock_stop
)
707 tmp
|= CLK_ENTER_LP_AFTER_DATA
;
709 tmp
|= CLK_HS_CONTINUOUS
;
711 /* configure buffer threshold limit to minimum */
712 tmp
&= ~PIX_BUF_THRESHOLD_MASK
;
713 tmp
|= PIX_BUF_THRESHOLD_1_4
;
715 /* set virtual channel to '0' */
716 tmp
&= ~PIX_VIRT_CHAN_MASK
;
717 tmp
|= PIX_VIRT_CHAN(0);
719 /* program BGR transmission */
720 if (intel_dsi
->bgr_enabled
)
721 tmp
|= BGR_TRANSMISSION
;
723 /* select pixel format */
724 tmp
&= ~PIX_FMT_MASK
;
725 if (pipe_config
->dsc
.compression_enable
) {
726 tmp
|= PIX_FMT_COMPRESSED
;
728 switch (intel_dsi
->pixel_format
) {
730 MISSING_CASE(intel_dsi
->pixel_format
);
732 case MIPI_DSI_FMT_RGB565
:
733 tmp
|= PIX_FMT_RGB565
;
735 case MIPI_DSI_FMT_RGB666_PACKED
:
736 tmp
|= PIX_FMT_RGB666_PACKED
;
738 case MIPI_DSI_FMT_RGB666
:
739 tmp
|= PIX_FMT_RGB666_LOOSE
;
741 case MIPI_DSI_FMT_RGB888
:
742 tmp
|= PIX_FMT_RGB888
;
747 if (DISPLAY_VER(dev_priv
) >= 12) {
748 if (is_vid_mode(intel_dsi
))
749 tmp
|= BLANKING_PACKET_ENABLE
;
752 /* program DSI operation mode */
753 if (is_vid_mode(intel_dsi
)) {
754 tmp
&= ~OP_MODE_MASK
;
755 switch (intel_dsi
->video_mode
) {
757 MISSING_CASE(intel_dsi
->video_mode
);
759 case NON_BURST_SYNC_EVENTS
:
760 tmp
|= VIDEO_MODE_SYNC_EVENT
;
762 case NON_BURST_SYNC_PULSE
:
763 tmp
|= VIDEO_MODE_SYNC_PULSE
;
768 * FIXME: Retrieve this info from VBT.
769 * As per the spec when dsi transcoder is operating
770 * in TE GATE mode, TE comes from GPIO
771 * which is UTIL PIN for DSI 0.
772 * Also this GPIO would not be used for other
773 * purposes is an assumption.
775 tmp
&= ~OP_MODE_MASK
;
776 tmp
|= CMD_MODE_TE_GATE
;
777 tmp
|= TE_SOURCE_GPIO
;
780 intel_de_write(dev_priv
, DSI_TRANS_FUNC_CONF(dsi_trans
), tmp
);
783 /* enable port sync mode if dual link */
784 if (intel_dsi
->dual_link
) {
785 for_each_dsi_port(port
, intel_dsi
->ports
) {
786 dsi_trans
= dsi_port_to_transcoder(port
);
787 intel_de_rmw(dev_priv
, TRANS_DDI_FUNC_CTL2(dsi_trans
),
788 0, PORT_SYNC_MODE_ENABLE
);
791 /* configure stream splitting */
792 configure_dual_link_mode(encoder
, pipe_config
);
795 for_each_dsi_port(port
, intel_dsi
->ports
) {
796 dsi_trans
= dsi_port_to_transcoder(port
);
798 /* select data lane width */
799 tmp
= intel_de_read(dev_priv
, TRANS_DDI_FUNC_CTL(dsi_trans
));
800 tmp
&= ~DDI_PORT_WIDTH_MASK
;
801 tmp
|= DDI_PORT_WIDTH(intel_dsi
->lane_count
);
803 /* select input pipe */
804 tmp
&= ~TRANS_DDI_EDP_INPUT_MASK
;
810 tmp
|= TRANS_DDI_EDP_INPUT_A_ON
;
813 tmp
|= TRANS_DDI_EDP_INPUT_B_ONOFF
;
816 tmp
|= TRANS_DDI_EDP_INPUT_C_ONOFF
;
819 tmp
|= TRANS_DDI_EDP_INPUT_D_ONOFF
;
823 /* enable DDI buffer */
824 tmp
|= TRANS_DDI_FUNC_ENABLE
;
825 intel_de_write(dev_priv
, TRANS_DDI_FUNC_CTL(dsi_trans
), tmp
);
828 /* wait for link ready */
829 for_each_dsi_port(port
, intel_dsi
->ports
) {
830 dsi_trans
= dsi_port_to_transcoder(port
);
831 if (wait_for_us((intel_de_read(dev_priv
, DSI_TRANS_FUNC_CONF(dsi_trans
)) &
833 drm_err(&dev_priv
->drm
, "DSI link not ready\n");
838 gen11_dsi_set_transcoder_timings(struct intel_encoder
*encoder
,
839 const struct intel_crtc_state
*crtc_state
)
841 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
842 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(encoder
);
843 const struct drm_display_mode
*adjusted_mode
=
844 &crtc_state
->hw
.adjusted_mode
;
846 enum transcoder dsi_trans
;
847 /* horizontal timings */
848 u16 htotal
, hactive
, hsync_start
, hsync_end
, hsync_size
;
850 /* vertical timings */
851 u16 vtotal
, vactive
, vsync_start
, vsync_end
, vsync_shift
;
852 int mul
= 1, div
= 1;
855 * Adjust horizontal timings (htotal, hsync_start, hsync_end) to account
856 * for slower link speed if DSC is enabled.
858 * The compression frequency ratio is the ratio between compressed and
859 * non-compressed link speeds, and simplifies down to the ratio between
860 * compressed and non-compressed bpp.
862 if (crtc_state
->dsc
.compression_enable
) {
863 mul
= crtc_state
->dsc
.compressed_bpp
;
864 div
= mipi_dsi_pixel_format_to_bpp(intel_dsi
->pixel_format
);
867 hactive
= adjusted_mode
->crtc_hdisplay
;
869 if (is_vid_mode(intel_dsi
))
870 htotal
= DIV_ROUND_UP(adjusted_mode
->crtc_htotal
* mul
, div
);
872 htotal
= DIV_ROUND_UP((hactive
+ 160) * mul
, div
);
874 hsync_start
= DIV_ROUND_UP(adjusted_mode
->crtc_hsync_start
* mul
, div
);
875 hsync_end
= DIV_ROUND_UP(adjusted_mode
->crtc_hsync_end
* mul
, div
);
876 hsync_size
= hsync_end
- hsync_start
;
877 hback_porch
= (adjusted_mode
->crtc_htotal
-
878 adjusted_mode
->crtc_hsync_end
);
879 vactive
= adjusted_mode
->crtc_vdisplay
;
881 if (is_vid_mode(intel_dsi
)) {
882 vtotal
= adjusted_mode
->crtc_vtotal
;
884 int bpp
, line_time_us
, byte_clk_period_ns
;
886 if (crtc_state
->dsc
.compression_enable
)
887 bpp
= crtc_state
->dsc
.compressed_bpp
;
889 bpp
= mipi_dsi_pixel_format_to_bpp(intel_dsi
->pixel_format
);
891 byte_clk_period_ns
= 1000000 / afe_clk(encoder
, crtc_state
);
892 line_time_us
= (htotal
* (bpp
/ 8) * byte_clk_period_ns
) / (1000 * intel_dsi
->lane_count
);
893 vtotal
= vactive
+ DIV_ROUND_UP(400, line_time_us
);
895 vsync_start
= adjusted_mode
->crtc_vsync_start
;
896 vsync_end
= adjusted_mode
->crtc_vsync_end
;
897 vsync_shift
= hsync_start
- htotal
/ 2;
899 if (intel_dsi
->dual_link
) {
901 if (intel_dsi
->dual_link
== DSI_DUAL_LINK_FRONT_BACK
)
902 hactive
+= intel_dsi
->pixel_overlap
;
906 /* minimum hactive as per bspec: 256 pixels */
907 if (adjusted_mode
->crtc_hdisplay
< 256)
908 drm_err(&dev_priv
->drm
, "hactive is less then 256 pixels\n");
910 /* if RGB666 format, then hactive must be multiple of 4 pixels */
911 if (intel_dsi
->pixel_format
== MIPI_DSI_FMT_RGB666
&& hactive
% 4 != 0)
912 drm_err(&dev_priv
->drm
,
913 "hactive pixels are not multiple of 4\n");
915 /* program TRANS_HTOTAL register */
916 for_each_dsi_port(port
, intel_dsi
->ports
) {
917 dsi_trans
= dsi_port_to_transcoder(port
);
918 intel_de_write(dev_priv
, TRANS_HTOTAL(dsi_trans
),
919 HACTIVE(hactive
- 1) | HTOTAL(htotal
- 1));
922 /* TRANS_HSYNC register to be programmed only for video mode */
923 if (is_vid_mode(intel_dsi
)) {
924 if (intel_dsi
->video_mode
== NON_BURST_SYNC_PULSE
) {
925 /* BSPEC: hsync size should be atleast 16 pixels */
927 drm_err(&dev_priv
->drm
,
928 "hsync size < 16 pixels\n");
931 if (hback_porch
< 16)
932 drm_err(&dev_priv
->drm
, "hback porch < 16 pixels\n");
934 if (intel_dsi
->dual_link
) {
939 for_each_dsi_port(port
, intel_dsi
->ports
) {
940 dsi_trans
= dsi_port_to_transcoder(port
);
941 intel_de_write(dev_priv
, TRANS_HSYNC(dsi_trans
),
942 HSYNC_START(hsync_start
- 1) | HSYNC_END(hsync_end
- 1));
946 /* program TRANS_VTOTAL register */
947 for_each_dsi_port(port
, intel_dsi
->ports
) {
948 dsi_trans
= dsi_port_to_transcoder(port
);
950 * FIXME: Programing this by assuming progressive mode, since
951 * non-interlaced info from VBT is not saved inside
952 * struct drm_display_mode.
953 * For interlace mode: program required pixel minus 2
955 intel_de_write(dev_priv
, TRANS_VTOTAL(dsi_trans
),
956 VACTIVE(vactive
- 1) | VTOTAL(vtotal
- 1));
959 if (vsync_end
< vsync_start
|| vsync_end
> vtotal
)
960 drm_err(&dev_priv
->drm
, "Invalid vsync_end value\n");
962 if (vsync_start
< vactive
)
963 drm_err(&dev_priv
->drm
, "vsync_start less than vactive\n");
965 /* program TRANS_VSYNC register for video mode only */
966 if (is_vid_mode(intel_dsi
)) {
967 for_each_dsi_port(port
, intel_dsi
->ports
) {
968 dsi_trans
= dsi_port_to_transcoder(port
);
969 intel_de_write(dev_priv
, TRANS_VSYNC(dsi_trans
),
970 VSYNC_START(vsync_start
- 1) | VSYNC_END(vsync_end
- 1));
975 * FIXME: It has to be programmed only for video modes and interlaced
976 * modes. Put the check condition here once interlaced
977 * info available as described above.
978 * program TRANS_VSYNCSHIFT register
980 if (is_vid_mode(intel_dsi
)) {
981 for_each_dsi_port(port
, intel_dsi
->ports
) {
982 dsi_trans
= dsi_port_to_transcoder(port
);
983 intel_de_write(dev_priv
, TRANS_VSYNCSHIFT(dsi_trans
),
989 * program TRANS_VBLANK register, should be same as vtotal programmed
991 * FIXME get rid of these local hacks and do it right,
992 * this will not handle eg. delayed vblank correctly.
994 if (DISPLAY_VER(dev_priv
) >= 12) {
995 for_each_dsi_port(port
, intel_dsi
->ports
) {
996 dsi_trans
= dsi_port_to_transcoder(port
);
997 intel_de_write(dev_priv
, TRANS_VBLANK(dsi_trans
),
998 VBLANK_START(vactive
- 1) | VBLANK_END(vtotal
- 1));
1003 static void gen11_dsi_enable_transcoder(struct intel_encoder
*encoder
)
1005 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
1006 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(encoder
);
1008 enum transcoder dsi_trans
;
1010 for_each_dsi_port(port
, intel_dsi
->ports
) {
1011 dsi_trans
= dsi_port_to_transcoder(port
);
1012 intel_de_rmw(dev_priv
, TRANSCONF(dsi_trans
), 0, TRANSCONF_ENABLE
);
1014 /* wait for transcoder to be enabled */
1015 if (intel_de_wait_for_set(dev_priv
, TRANSCONF(dsi_trans
),
1016 TRANSCONF_STATE_ENABLE
, 10))
1017 drm_err(&dev_priv
->drm
,
1018 "DSI transcoder not enabled\n");
1022 static void gen11_dsi_setup_timeouts(struct intel_encoder
*encoder
,
1023 const struct intel_crtc_state
*crtc_state
)
1025 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
1026 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(encoder
);
1028 enum transcoder dsi_trans
;
1029 u32 hs_tx_timeout
, lp_rx_timeout
, ta_timeout
, divisor
, mul
;
1032 * escape clock count calculation:
1033 * BYTE_CLK_COUNT = TIME_NS/(8 * UI)
1034 * UI (nsec) = (10^6)/Bitrate
1035 * TIME_NS = (BYTE_CLK_COUNT * 8 * 10^6)/ Bitrate
1036 * ESCAPE_CLK_COUNT = TIME_NS/ESC_CLK_NS
1038 divisor
= intel_dsi_tlpx_ns(intel_dsi
) * afe_clk(encoder
, crtc_state
) * 1000;
1040 hs_tx_timeout
= DIV_ROUND_UP(intel_dsi
->hs_tx_timeout
* mul
,
1042 lp_rx_timeout
= DIV_ROUND_UP(intel_dsi
->lp_rx_timeout
* mul
, divisor
);
1043 ta_timeout
= DIV_ROUND_UP(intel_dsi
->turn_arnd_val
* mul
, divisor
);
1045 for_each_dsi_port(port
, intel_dsi
->ports
) {
1046 dsi_trans
= dsi_port_to_transcoder(port
);
1048 /* program hst_tx_timeout */
1049 intel_de_rmw(dev_priv
, DSI_HSTX_TO(dsi_trans
),
1050 HSTX_TIMEOUT_VALUE_MASK
,
1051 HSTX_TIMEOUT_VALUE(hs_tx_timeout
));
1053 /* FIXME: DSI_CALIB_TO */
1055 /* program lp_rx_host timeout */
1056 intel_de_rmw(dev_priv
, DSI_LPRX_HOST_TO(dsi_trans
),
1057 LPRX_TIMEOUT_VALUE_MASK
,
1058 LPRX_TIMEOUT_VALUE(lp_rx_timeout
));
1060 /* FIXME: DSI_PWAIT_TO */
1062 /* program turn around timeout */
1063 intel_de_rmw(dev_priv
, DSI_TA_TO(dsi_trans
),
1064 TA_TIMEOUT_VALUE_MASK
,
1065 TA_TIMEOUT_VALUE(ta_timeout
));
1069 static void gen11_dsi_config_util_pin(struct intel_encoder
*encoder
,
1072 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
1073 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(encoder
);
1077 * used as TE i/p for DSI0,
1078 * for dual link/DSI1 TE is from slave DSI1
1081 if (is_vid_mode(intel_dsi
) || (intel_dsi
->ports
& BIT(PORT_B
)))
1084 tmp
= intel_de_read(dev_priv
, UTIL_PIN_CTL
);
1087 tmp
|= UTIL_PIN_DIRECTION_INPUT
;
1088 tmp
|= UTIL_PIN_ENABLE
;
1090 tmp
&= ~UTIL_PIN_ENABLE
;
1092 intel_de_write(dev_priv
, UTIL_PIN_CTL
, tmp
);
1096 gen11_dsi_enable_port_and_phy(struct intel_encoder
*encoder
,
1097 const struct intel_crtc_state
*crtc_state
)
1099 /* step 4a: power up all lanes of the DDI used by DSI */
1100 gen11_dsi_power_up_lanes(encoder
);
1102 /* step 4b: configure lane sequencing of the Combo-PHY transmitters */
1103 gen11_dsi_config_phy_lanes_sequence(encoder
);
1105 /* step 4c: configure voltage swing and skew */
1106 gen11_dsi_voltage_swing_program_seq(encoder
);
1108 /* setup D-PHY timings */
1109 gen11_dsi_setup_dphy_timings(encoder
, crtc_state
);
1111 /* enable DDI buffer */
1112 gen11_dsi_enable_ddi_buffer(encoder
);
1114 gen11_dsi_gate_clocks(encoder
);
1116 gen11_dsi_setup_timings(encoder
, crtc_state
);
1118 /* Since transcoder is configured to take events from GPIO */
1119 gen11_dsi_config_util_pin(encoder
, true);
1121 /* step 4h: setup DSI protocol timeouts */
1122 gen11_dsi_setup_timeouts(encoder
, crtc_state
);
1124 /* Step (4h, 4i, 4j, 4k): Configure transcoder */
1125 gen11_dsi_configure_transcoder(encoder
, crtc_state
);
1128 static void gen11_dsi_powerup_panel(struct intel_encoder
*encoder
)
1130 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
1131 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(encoder
);
1132 struct mipi_dsi_device
*dsi
;
1134 enum transcoder dsi_trans
;
1138 /* set maximum return packet size */
1139 for_each_dsi_port(port
, intel_dsi
->ports
) {
1140 dsi_trans
= dsi_port_to_transcoder(port
);
1143 * FIXME: This uses the number of DW's currently in the payload
1144 * receive queue. This is probably not what we want here.
1146 tmp
= intel_de_read(dev_priv
, DSI_CMD_RXCTL(dsi_trans
));
1147 tmp
&= NUMBER_RX_PLOAD_DW_MASK
;
1148 /* multiply "Number Rx Payload DW" by 4 to get max value */
1150 dsi
= intel_dsi
->dsi_hosts
[port
]->device
;
1151 ret
= mipi_dsi_set_maximum_return_packet_size(dsi
, tmp
);
1153 drm_err(&dev_priv
->drm
,
1154 "error setting max return pkt size%d\n", tmp
);
1157 intel_dsi_vbt_exec_sequence(intel_dsi
, MIPI_SEQ_INIT_OTP
);
1159 /* ensure all panel commands dispatched before enabling transcoder */
1160 wait_for_cmds_dispatched_to_panel(encoder
);
1163 static void gen11_dsi_pre_pll_enable(struct intel_atomic_state
*state
,
1164 struct intel_encoder
*encoder
,
1165 const struct intel_crtc_state
*crtc_state
,
1166 const struct drm_connector_state
*conn_state
)
1168 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(encoder
);
1170 intel_dsi_wait_panel_power_cycle(intel_dsi
);
1172 intel_dsi_vbt_exec_sequence(intel_dsi
, MIPI_SEQ_POWER_ON
);
1173 msleep(intel_dsi
->panel_on_delay
);
1174 intel_dsi_vbt_exec_sequence(intel_dsi
, MIPI_SEQ_DEASSERT_RESET
);
1176 /* step2: enable IO power */
1177 gen11_dsi_enable_io_power(encoder
);
1179 /* step3: enable DSI PLL */
1180 gen11_dsi_program_esc_clk_div(encoder
, crtc_state
);
1183 static void gen11_dsi_pre_enable(struct intel_atomic_state
*state
,
1184 struct intel_encoder
*encoder
,
1185 const struct intel_crtc_state
*pipe_config
,
1186 const struct drm_connector_state
*conn_state
)
1189 gen11_dsi_map_pll(encoder
, pipe_config
);
1191 /* step4: enable DSI port and DPHY */
1192 gen11_dsi_enable_port_and_phy(encoder
, pipe_config
);
1194 /* step5: program and powerup panel */
1195 gen11_dsi_powerup_panel(encoder
);
1197 intel_dsc_dsi_pps_write(encoder
, pipe_config
);
1199 /* step6c: configure transcoder timings */
1200 gen11_dsi_set_transcoder_timings(encoder
, pipe_config
);
1204 * Wa_1409054076:icl,jsl,ehl
1205 * When pipe A is disabled and MIPI DSI is enabled on pipe B,
1206 * the AMT KVMR feature will incorrectly see pipe A as enabled.
1207 * Set 0x42080 bit 23=1 before enabling DSI on pipe B and leave
1208 * it set while DSI is enabled on pipe B
1210 static void icl_apply_kvmr_pipe_a_wa(struct intel_encoder
*encoder
,
1211 enum pipe pipe
, bool enable
)
1213 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
1215 if (DISPLAY_VER(dev_priv
) == 11 && pipe
== PIPE_B
)
1216 intel_de_rmw(dev_priv
, CHICKEN_PAR1_1
,
1218 enable
? IGNORE_KVMR_PIPE_A
: 0);
1222 * Wa_16012360555:adl-p
1223 * SW will have to program the "LP to HS Wakeup Guardband"
1224 * to account for the repeaters on the HS Request/Ready
1225 * PPI signaling between the Display engine and the DPHY.
1227 static void adlp_set_lp_hs_wakeup_gb(struct intel_encoder
*encoder
)
1229 struct drm_i915_private
*i915
= to_i915(encoder
->base
.dev
);
1230 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(encoder
);
1233 if (DISPLAY_VER(i915
) == 13) {
1234 for_each_dsi_port(port
, intel_dsi
->ports
)
1235 intel_de_rmw(i915
, TGL_DSI_CHKN_REG(port
),
1236 TGL_DSI_CHKN_LSHS_GB_MASK
,
1237 TGL_DSI_CHKN_LSHS_GB(4));
1241 static void gen11_dsi_enable(struct intel_atomic_state
*state
,
1242 struct intel_encoder
*encoder
,
1243 const struct intel_crtc_state
*crtc_state
,
1244 const struct drm_connector_state
*conn_state
)
1246 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(encoder
);
1247 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
1249 /* Wa_1409054076:icl,jsl,ehl */
1250 icl_apply_kvmr_pipe_a_wa(encoder
, crtc
->pipe
, true);
1252 /* Wa_16012360555:adl-p */
1253 adlp_set_lp_hs_wakeup_gb(encoder
);
1255 /* step6d: enable dsi transcoder */
1256 gen11_dsi_enable_transcoder(encoder
);
1258 intel_dsi_vbt_exec_sequence(intel_dsi
, MIPI_SEQ_DISPLAY_ON
);
1260 /* step7: enable backlight */
1261 intel_backlight_enable(crtc_state
, conn_state
);
1262 intel_dsi_vbt_exec_sequence(intel_dsi
, MIPI_SEQ_BACKLIGHT_ON
);
1264 intel_crtc_vblank_on(crtc_state
);
1267 static void gen11_dsi_disable_transcoder(struct intel_encoder
*encoder
)
1269 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
1270 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(encoder
);
1272 enum transcoder dsi_trans
;
1274 for_each_dsi_port(port
, intel_dsi
->ports
) {
1275 dsi_trans
= dsi_port_to_transcoder(port
);
1277 /* disable transcoder */
1278 intel_de_rmw(dev_priv
, TRANSCONF(dsi_trans
), TRANSCONF_ENABLE
, 0);
1280 /* wait for transcoder to be disabled */
1281 if (intel_de_wait_for_clear(dev_priv
, TRANSCONF(dsi_trans
),
1282 TRANSCONF_STATE_ENABLE
, 50))
1283 drm_err(&dev_priv
->drm
,
1284 "DSI trancoder not disabled\n");
1288 static void gen11_dsi_powerdown_panel(struct intel_encoder
*encoder
)
1290 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(encoder
);
1292 intel_dsi_vbt_exec_sequence(intel_dsi
, MIPI_SEQ_DISPLAY_OFF
);
1294 /* ensure cmds dispatched to panel */
1295 wait_for_cmds_dispatched_to_panel(encoder
);
1298 static void gen11_dsi_deconfigure_trancoder(struct intel_encoder
*encoder
)
1300 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
1301 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(encoder
);
1303 enum transcoder dsi_trans
;
1306 /* disable periodic update mode */
1307 if (is_cmd_mode(intel_dsi
)) {
1308 for_each_dsi_port(port
, intel_dsi
->ports
)
1309 intel_de_rmw(dev_priv
, DSI_CMD_FRMCTL(port
),
1310 DSI_PERIODIC_FRAME_UPDATE_ENABLE
, 0);
1313 /* put dsi link in ULPS */
1314 for_each_dsi_port(port
, intel_dsi
->ports
) {
1315 dsi_trans
= dsi_port_to_transcoder(port
);
1316 tmp
= intel_de_read(dev_priv
, DSI_LP_MSG(dsi_trans
));
1317 tmp
|= LINK_ENTER_ULPS
;
1318 tmp
&= ~LINK_ULPS_TYPE_LP11
;
1319 intel_de_write(dev_priv
, DSI_LP_MSG(dsi_trans
), tmp
);
1321 if (wait_for_us((intel_de_read(dev_priv
, DSI_LP_MSG(dsi_trans
)) &
1324 drm_err(&dev_priv
->drm
, "DSI link not in ULPS\n");
1327 /* disable ddi function */
1328 for_each_dsi_port(port
, intel_dsi
->ports
) {
1329 dsi_trans
= dsi_port_to_transcoder(port
);
1330 intel_de_rmw(dev_priv
, TRANS_DDI_FUNC_CTL(dsi_trans
),
1331 TRANS_DDI_FUNC_ENABLE
, 0);
1334 /* disable port sync mode if dual link */
1335 if (intel_dsi
->dual_link
) {
1336 for_each_dsi_port(port
, intel_dsi
->ports
) {
1337 dsi_trans
= dsi_port_to_transcoder(port
);
1338 intel_de_rmw(dev_priv
, TRANS_DDI_FUNC_CTL2(dsi_trans
),
1339 PORT_SYNC_MODE_ENABLE
, 0);
1344 static void gen11_dsi_disable_port(struct intel_encoder
*encoder
)
1346 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
1347 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(encoder
);
1350 gen11_dsi_ungate_clocks(encoder
);
1351 for_each_dsi_port(port
, intel_dsi
->ports
) {
1352 intel_de_rmw(dev_priv
, DDI_BUF_CTL(port
), DDI_BUF_CTL_ENABLE
, 0);
1354 if (wait_for_us((intel_de_read(dev_priv
, DDI_BUF_CTL(port
)) &
1357 drm_err(&dev_priv
->drm
,
1358 "DDI port:%c buffer not idle\n",
1361 gen11_dsi_gate_clocks(encoder
);
1364 static void gen11_dsi_disable_io_power(struct intel_encoder
*encoder
)
1366 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
1367 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(encoder
);
1370 for_each_dsi_port(port
, intel_dsi
->ports
) {
1371 intel_wakeref_t wakeref
;
1373 wakeref
= fetch_and_zero(&intel_dsi
->io_wakeref
[port
]);
1374 intel_display_power_put(dev_priv
,
1376 POWER_DOMAIN_PORT_DDI_IO_A
:
1377 POWER_DOMAIN_PORT_DDI_IO_B
,
1381 /* set mode to DDI */
1382 for_each_dsi_port(port
, intel_dsi
->ports
)
1383 intel_de_rmw(dev_priv
, ICL_DSI_IO_MODECTL(port
),
1384 COMBO_PHY_MODE_DSI
, 0);
1387 static void gen11_dsi_disable(struct intel_atomic_state
*state
,
1388 struct intel_encoder
*encoder
,
1389 const struct intel_crtc_state
*old_crtc_state
,
1390 const struct drm_connector_state
*old_conn_state
)
1392 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(encoder
);
1394 /* step1: turn off backlight */
1395 intel_dsi_vbt_exec_sequence(intel_dsi
, MIPI_SEQ_BACKLIGHT_OFF
);
1396 intel_backlight_disable(old_conn_state
);
1399 static void gen11_dsi_post_disable(struct intel_atomic_state
*state
,
1400 struct intel_encoder
*encoder
,
1401 const struct intel_crtc_state
*old_crtc_state
,
1402 const struct drm_connector_state
*old_conn_state
)
1404 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(encoder
);
1405 struct intel_crtc
*crtc
= to_intel_crtc(old_crtc_state
->uapi
.crtc
);
1407 intel_crtc_vblank_off(old_crtc_state
);
1409 /* step2d,e: disable transcoder and wait */
1410 gen11_dsi_disable_transcoder(encoder
);
1412 /* Wa_1409054076:icl,jsl,ehl */
1413 icl_apply_kvmr_pipe_a_wa(encoder
, crtc
->pipe
, false);
1415 /* step2f,g: powerdown panel */
1416 gen11_dsi_powerdown_panel(encoder
);
1418 /* step2h,i,j: deconfig trancoder */
1419 gen11_dsi_deconfigure_trancoder(encoder
);
1421 intel_dsc_disable(old_crtc_state
);
1422 skl_scaler_disable(old_crtc_state
);
1424 /* step3: disable port */
1425 gen11_dsi_disable_port(encoder
);
1427 gen11_dsi_config_util_pin(encoder
, false);
1429 /* step4: disable IO power */
1430 gen11_dsi_disable_io_power(encoder
);
1432 intel_dsi_vbt_exec_sequence(intel_dsi
, MIPI_SEQ_ASSERT_RESET
);
1434 msleep(intel_dsi
->panel_off_delay
);
1435 intel_dsi_vbt_exec_sequence(intel_dsi
, MIPI_SEQ_POWER_OFF
);
1437 intel_dsi
->panel_power_off_time
= ktime_get_boottime();
1440 static enum drm_mode_status
gen11_dsi_mode_valid(struct drm_connector
*connector
,
1441 struct drm_display_mode
*mode
)
1444 return intel_dsi_mode_valid(connector
, mode
);
1447 static void gen11_dsi_get_timings(struct intel_encoder
*encoder
,
1448 struct intel_crtc_state
*pipe_config
)
1450 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(encoder
);
1451 struct drm_display_mode
*adjusted_mode
=
1452 &pipe_config
->hw
.adjusted_mode
;
1454 if (pipe_config
->dsc
.compressed_bpp
) {
1455 int div
= pipe_config
->dsc
.compressed_bpp
;
1456 int mul
= mipi_dsi_pixel_format_to_bpp(intel_dsi
->pixel_format
);
1458 adjusted_mode
->crtc_htotal
=
1459 DIV_ROUND_UP(adjusted_mode
->crtc_htotal
* mul
, div
);
1460 adjusted_mode
->crtc_hsync_start
=
1461 DIV_ROUND_UP(adjusted_mode
->crtc_hsync_start
* mul
, div
);
1462 adjusted_mode
->crtc_hsync_end
=
1463 DIV_ROUND_UP(adjusted_mode
->crtc_hsync_end
* mul
, div
);
1466 if (intel_dsi
->dual_link
) {
1467 adjusted_mode
->crtc_hdisplay
*= 2;
1468 if (intel_dsi
->dual_link
== DSI_DUAL_LINK_FRONT_BACK
)
1469 adjusted_mode
->crtc_hdisplay
-=
1470 intel_dsi
->pixel_overlap
;
1471 adjusted_mode
->crtc_htotal
*= 2;
1473 adjusted_mode
->crtc_hblank_start
= adjusted_mode
->crtc_hdisplay
;
1474 adjusted_mode
->crtc_hblank_end
= adjusted_mode
->crtc_htotal
;
1476 if (intel_dsi
->operation_mode
== INTEL_DSI_VIDEO_MODE
) {
1477 if (intel_dsi
->dual_link
) {
1478 adjusted_mode
->crtc_hsync_start
*= 2;
1479 adjusted_mode
->crtc_hsync_end
*= 2;
1482 adjusted_mode
->crtc_vblank_start
= adjusted_mode
->crtc_vdisplay
;
1483 adjusted_mode
->crtc_vblank_end
= adjusted_mode
->crtc_vtotal
;
1486 static bool gen11_dsi_is_periodic_cmd_mode(struct intel_dsi
*intel_dsi
)
1488 struct drm_device
*dev
= intel_dsi
->base
.base
.dev
;
1489 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1490 enum transcoder dsi_trans
;
1493 if (intel_dsi
->ports
== BIT(PORT_B
))
1494 dsi_trans
= TRANSCODER_DSI_1
;
1496 dsi_trans
= TRANSCODER_DSI_0
;
1498 val
= intel_de_read(dev_priv
, DSI_TRANS_FUNC_CONF(dsi_trans
));
1499 return (val
& DSI_PERIODIC_FRAME_UPDATE_ENABLE
);
1502 static void gen11_dsi_get_cmd_mode_config(struct intel_dsi
*intel_dsi
,
1503 struct intel_crtc_state
*pipe_config
)
1505 if (intel_dsi
->ports
== (BIT(PORT_B
) | BIT(PORT_A
)))
1506 pipe_config
->mode_flags
|= I915_MODE_FLAG_DSI_USE_TE1
|
1507 I915_MODE_FLAG_DSI_USE_TE0
;
1508 else if (intel_dsi
->ports
== BIT(PORT_B
))
1509 pipe_config
->mode_flags
|= I915_MODE_FLAG_DSI_USE_TE1
;
1511 pipe_config
->mode_flags
|= I915_MODE_FLAG_DSI_USE_TE0
;
1514 static void gen11_dsi_get_config(struct intel_encoder
*encoder
,
1515 struct intel_crtc_state
*pipe_config
)
1517 struct intel_crtc
*crtc
= to_intel_crtc(pipe_config
->uapi
.crtc
);
1518 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(encoder
);
1520 intel_ddi_get_clock(encoder
, pipe_config
, icl_ddi_combo_get_pll(encoder
));
1522 pipe_config
->hw
.adjusted_mode
.crtc_clock
= intel_dsi
->pclk
;
1523 if (intel_dsi
->dual_link
)
1524 pipe_config
->hw
.adjusted_mode
.crtc_clock
*= 2;
1526 gen11_dsi_get_timings(encoder
, pipe_config
);
1527 pipe_config
->output_types
|= BIT(INTEL_OUTPUT_DSI
);
1528 pipe_config
->pipe_bpp
= bdw_get_pipe_misc_bpp(crtc
);
1530 /* Get the details on which TE should be enabled */
1531 if (is_cmd_mode(intel_dsi
))
1532 gen11_dsi_get_cmd_mode_config(intel_dsi
, pipe_config
);
1534 if (gen11_dsi_is_periodic_cmd_mode(intel_dsi
))
1535 pipe_config
->mode_flags
|= I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE
;
1538 static void gen11_dsi_sync_state(struct intel_encoder
*encoder
,
1539 const struct intel_crtc_state
*crtc_state
)
1541 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
1542 struct intel_crtc
*intel_crtc
;
1548 intel_crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
1549 pipe
= intel_crtc
->pipe
;
1551 /* wa verify 1409054076:icl,jsl,ehl */
1552 if (DISPLAY_VER(dev_priv
) == 11 && pipe
== PIPE_B
&&
1553 !(intel_de_read(dev_priv
, CHICKEN_PAR1_1
) & IGNORE_KVMR_PIPE_A
))
1554 drm_dbg_kms(&dev_priv
->drm
,
1555 "[ENCODER:%d:%s] BIOS left IGNORE_KVMR_PIPE_A cleared with pipe B enabled\n",
1556 encoder
->base
.base
.id
,
1557 encoder
->base
.name
);
1560 static int gen11_dsi_dsc_compute_config(struct intel_encoder
*encoder
,
1561 struct intel_crtc_state
*crtc_state
)
1563 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
1564 struct drm_dsc_config
*vdsc_cfg
= &crtc_state
->dsc
.config
;
1565 int dsc_max_bpc
= DISPLAY_VER(dev_priv
) >= 12 ? 12 : 10;
1569 use_dsc
= intel_bios_get_dsc_params(encoder
, crtc_state
, dsc_max_bpc
);
1573 if (crtc_state
->pipe_bpp
< 8 * 3)
1576 /* FIXME: split only when necessary */
1577 if (crtc_state
->dsc
.slice_count
> 1)
1578 crtc_state
->dsc
.dsc_split
= true;
1580 /* FIXME: initialize from VBT */
1581 vdsc_cfg
->rc_model_size
= DSC_RC_MODEL_SIZE_CONST
;
1583 vdsc_cfg
->pic_height
= crtc_state
->hw
.adjusted_mode
.crtc_vdisplay
;
1585 ret
= intel_dsc_compute_params(crtc_state
);
1589 /* DSI specific sanity checks on the common code */
1590 drm_WARN_ON(&dev_priv
->drm
, vdsc_cfg
->vbr_enable
);
1591 drm_WARN_ON(&dev_priv
->drm
, vdsc_cfg
->simple_422
);
1592 drm_WARN_ON(&dev_priv
->drm
,
1593 vdsc_cfg
->pic_width
% vdsc_cfg
->slice_width
);
1594 drm_WARN_ON(&dev_priv
->drm
, vdsc_cfg
->slice_height
< 8);
1595 drm_WARN_ON(&dev_priv
->drm
,
1596 vdsc_cfg
->pic_height
% vdsc_cfg
->slice_height
);
1598 ret
= drm_dsc_compute_rc_parameters(vdsc_cfg
);
1602 crtc_state
->dsc
.compression_enable
= true;
1607 static int gen11_dsi_compute_config(struct intel_encoder
*encoder
,
1608 struct intel_crtc_state
*pipe_config
,
1609 struct drm_connector_state
*conn_state
)
1611 struct drm_i915_private
*i915
= to_i915(encoder
->base
.dev
);
1612 struct intel_dsi
*intel_dsi
= container_of(encoder
, struct intel_dsi
,
1614 struct intel_connector
*intel_connector
= intel_dsi
->attached_connector
;
1615 struct drm_display_mode
*adjusted_mode
=
1616 &pipe_config
->hw
.adjusted_mode
;
1619 pipe_config
->sink_format
= INTEL_OUTPUT_FORMAT_RGB
;
1620 pipe_config
->output_format
= INTEL_OUTPUT_FORMAT_RGB
;
1622 ret
= intel_panel_compute_config(intel_connector
, adjusted_mode
);
1626 ret
= intel_panel_fitting(pipe_config
, conn_state
);
1630 adjusted_mode
->flags
= 0;
1632 /* Dual link goes to trancoder DSI'0' */
1633 if (intel_dsi
->ports
== BIT(PORT_B
))
1634 pipe_config
->cpu_transcoder
= TRANSCODER_DSI_1
;
1636 pipe_config
->cpu_transcoder
= TRANSCODER_DSI_0
;
1638 if (intel_dsi
->pixel_format
== MIPI_DSI_FMT_RGB888
)
1639 pipe_config
->pipe_bpp
= 24;
1641 pipe_config
->pipe_bpp
= 18;
1643 pipe_config
->clock_set
= true;
1645 if (gen11_dsi_dsc_compute_config(encoder
, pipe_config
))
1646 drm_dbg_kms(&i915
->drm
, "Attempting to use DSC failed\n");
1648 pipe_config
->port_clock
= afe_clk(encoder
, pipe_config
) / 5;
1651 * In case of TE GATE cmd mode, we
1652 * receive TE from the slave if
1653 * dual link is enabled
1655 if (is_cmd_mode(intel_dsi
))
1656 gen11_dsi_get_cmd_mode_config(intel_dsi
, pipe_config
);
1661 static void gen11_dsi_get_power_domains(struct intel_encoder
*encoder
,
1662 struct intel_crtc_state
*crtc_state
)
1664 struct drm_i915_private
*i915
= to_i915(encoder
->base
.dev
);
1666 get_dsi_io_power_domains(i915
,
1667 enc_to_intel_dsi(encoder
));
1670 static bool gen11_dsi_get_hw_state(struct intel_encoder
*encoder
,
1673 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
1674 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(encoder
);
1675 enum transcoder dsi_trans
;
1676 intel_wakeref_t wakeref
;
1681 wakeref
= intel_display_power_get_if_enabled(dev_priv
,
1682 encoder
->power_domain
);
1686 for_each_dsi_port(port
, intel_dsi
->ports
) {
1687 dsi_trans
= dsi_port_to_transcoder(port
);
1688 tmp
= intel_de_read(dev_priv
, TRANS_DDI_FUNC_CTL(dsi_trans
));
1689 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
1690 case TRANS_DDI_EDP_INPUT_A_ON
:
1693 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
1696 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
1699 case TRANS_DDI_EDP_INPUT_D_ONOFF
:
1703 drm_err(&dev_priv
->drm
, "Invalid PIPE input\n");
1707 tmp
= intel_de_read(dev_priv
, TRANSCONF(dsi_trans
));
1708 ret
= tmp
& TRANSCONF_ENABLE
;
1711 intel_display_power_put(dev_priv
, encoder
->power_domain
, wakeref
);
1715 static bool gen11_dsi_initial_fastset_check(struct intel_encoder
*encoder
,
1716 struct intel_crtc_state
*crtc_state
)
1718 if (crtc_state
->dsc
.compression_enable
) {
1719 drm_dbg_kms(encoder
->base
.dev
, "Forcing full modeset due to DSC being enabled\n");
1720 crtc_state
->uapi
.mode_changed
= true;
1728 static void gen11_dsi_encoder_destroy(struct drm_encoder
*encoder
)
1730 intel_encoder_destroy(encoder
);
1733 static const struct drm_encoder_funcs gen11_dsi_encoder_funcs
= {
1734 .destroy
= gen11_dsi_encoder_destroy
,
1737 static const struct drm_connector_funcs gen11_dsi_connector_funcs
= {
1738 .detect
= intel_panel_detect
,
1739 .late_register
= intel_connector_register
,
1740 .early_unregister
= intel_connector_unregister
,
1741 .destroy
= intel_connector_destroy
,
1742 .fill_modes
= drm_helper_probe_single_connector_modes
,
1743 .atomic_get_property
= intel_digital_connector_atomic_get_property
,
1744 .atomic_set_property
= intel_digital_connector_atomic_set_property
,
1745 .atomic_destroy_state
= drm_atomic_helper_connector_destroy_state
,
1746 .atomic_duplicate_state
= intel_digital_connector_duplicate_state
,
1749 static const struct drm_connector_helper_funcs gen11_dsi_connector_helper_funcs
= {
1750 .get_modes
= intel_dsi_get_modes
,
1751 .mode_valid
= gen11_dsi_mode_valid
,
1752 .atomic_check
= intel_digital_connector_atomic_check
,
1755 static int gen11_dsi_host_attach(struct mipi_dsi_host
*host
,
1756 struct mipi_dsi_device
*dsi
)
1761 static int gen11_dsi_host_detach(struct mipi_dsi_host
*host
,
1762 struct mipi_dsi_device
*dsi
)
1767 static ssize_t
gen11_dsi_host_transfer(struct mipi_dsi_host
*host
,
1768 const struct mipi_dsi_msg
*msg
)
1770 struct intel_dsi_host
*intel_dsi_host
= to_intel_dsi_host(host
);
1771 struct mipi_dsi_packet dsi_pkt
;
1773 bool enable_lpdt
= false;
1775 ret
= mipi_dsi_create_packet(&dsi_pkt
, msg
);
1779 if (msg
->flags
& MIPI_DSI_MSG_USE_LPM
)
1782 /* only long packet contains payload */
1783 if (mipi_dsi_packet_format_is_long(msg
->type
)) {
1784 ret
= dsi_send_pkt_payld(intel_dsi_host
, &dsi_pkt
);
1789 /* send packet header */
1790 ret
= dsi_send_pkt_hdr(intel_dsi_host
, &dsi_pkt
, enable_lpdt
);
1794 //TODO: add payload receive code if needed
1796 ret
= sizeof(dsi_pkt
.header
) + dsi_pkt
.payload_length
;
1801 static const struct mipi_dsi_host_ops gen11_dsi_host_ops
= {
1802 .attach
= gen11_dsi_host_attach
,
1803 .detach
= gen11_dsi_host_detach
,
1804 .transfer
= gen11_dsi_host_transfer
,
1807 #define ICL_PREPARE_CNT_MAX 0x7
1808 #define ICL_CLK_ZERO_CNT_MAX 0xf
1809 #define ICL_TRAIL_CNT_MAX 0x7
1810 #define ICL_TCLK_PRE_CNT_MAX 0x3
1811 #define ICL_TCLK_POST_CNT_MAX 0x7
1812 #define ICL_HS_ZERO_CNT_MAX 0xf
1813 #define ICL_EXIT_ZERO_CNT_MAX 0x7
1815 static void icl_dphy_param_init(struct intel_dsi
*intel_dsi
)
1817 struct drm_device
*dev
= intel_dsi
->base
.base
.dev
;
1818 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1819 struct intel_connector
*connector
= intel_dsi
->attached_connector
;
1820 struct mipi_config
*mipi_config
= connector
->panel
.vbt
.dsi
.config
;
1822 u32 prepare_cnt
, exit_zero_cnt
, clk_zero_cnt
, trail_cnt
;
1823 u32 ths_prepare_ns
, tclk_trail_ns
;
1827 tlpx_ns
= intel_dsi_tlpx_ns(intel_dsi
);
1829 tclk_trail_ns
= max(mipi_config
->tclk_trail
, mipi_config
->ths_trail
);
1830 ths_prepare_ns
= max(mipi_config
->ths_prepare
,
1831 mipi_config
->tclk_prepare
);
1834 * prepare cnt in escape clocks
1835 * this field represents a hexadecimal value with a precision
1836 * of 1.2 – i.e. the most significant bit is the integer
1837 * and the least significant 2 bits are fraction bits.
1838 * so, the field can represent a range of 0.25 to 1.75
1840 prepare_cnt
= DIV_ROUND_UP(ths_prepare_ns
* 4, tlpx_ns
);
1841 if (prepare_cnt
> ICL_PREPARE_CNT_MAX
) {
1842 drm_dbg_kms(&dev_priv
->drm
, "prepare_cnt out of range (%d)\n",
1844 prepare_cnt
= ICL_PREPARE_CNT_MAX
;
1847 /* clk zero count in escape clocks */
1848 clk_zero_cnt
= DIV_ROUND_UP(mipi_config
->tclk_prepare_clkzero
-
1849 ths_prepare_ns
, tlpx_ns
);
1850 if (clk_zero_cnt
> ICL_CLK_ZERO_CNT_MAX
) {
1851 drm_dbg_kms(&dev_priv
->drm
,
1852 "clk_zero_cnt out of range (%d)\n", clk_zero_cnt
);
1853 clk_zero_cnt
= ICL_CLK_ZERO_CNT_MAX
;
1856 /* trail cnt in escape clocks*/
1857 trail_cnt
= DIV_ROUND_UP(tclk_trail_ns
, tlpx_ns
);
1858 if (trail_cnt
> ICL_TRAIL_CNT_MAX
) {
1859 drm_dbg_kms(&dev_priv
->drm
, "trail_cnt out of range (%d)\n",
1861 trail_cnt
= ICL_TRAIL_CNT_MAX
;
1864 /* tclk pre count in escape clocks */
1865 tclk_pre_cnt
= DIV_ROUND_UP(mipi_config
->tclk_pre
, tlpx_ns
);
1866 if (tclk_pre_cnt
> ICL_TCLK_PRE_CNT_MAX
) {
1867 drm_dbg_kms(&dev_priv
->drm
,
1868 "tclk_pre_cnt out of range (%d)\n", tclk_pre_cnt
);
1869 tclk_pre_cnt
= ICL_TCLK_PRE_CNT_MAX
;
1872 /* hs zero cnt in escape clocks */
1873 hs_zero_cnt
= DIV_ROUND_UP(mipi_config
->ths_prepare_hszero
-
1874 ths_prepare_ns
, tlpx_ns
);
1875 if (hs_zero_cnt
> ICL_HS_ZERO_CNT_MAX
) {
1876 drm_dbg_kms(&dev_priv
->drm
, "hs_zero_cnt out of range (%d)\n",
1878 hs_zero_cnt
= ICL_HS_ZERO_CNT_MAX
;
1881 /* hs exit zero cnt in escape clocks */
1882 exit_zero_cnt
= DIV_ROUND_UP(mipi_config
->ths_exit
, tlpx_ns
);
1883 if (exit_zero_cnt
> ICL_EXIT_ZERO_CNT_MAX
) {
1884 drm_dbg_kms(&dev_priv
->drm
,
1885 "exit_zero_cnt out of range (%d)\n",
1887 exit_zero_cnt
= ICL_EXIT_ZERO_CNT_MAX
;
1890 /* clock lane dphy timings */
1891 intel_dsi
->dphy_reg
= (CLK_PREPARE_OVERRIDE
|
1892 CLK_PREPARE(prepare_cnt
) |
1894 CLK_ZERO(clk_zero_cnt
) |
1896 CLK_PRE(tclk_pre_cnt
) |
1897 CLK_TRAIL_OVERRIDE
|
1898 CLK_TRAIL(trail_cnt
));
1900 /* data lanes dphy timings */
1901 intel_dsi
->dphy_data_lane_reg
= (HS_PREPARE_OVERRIDE
|
1902 HS_PREPARE(prepare_cnt
) |
1904 HS_ZERO(hs_zero_cnt
) |
1906 HS_TRAIL(trail_cnt
) |
1908 HS_EXIT(exit_zero_cnt
));
1910 intel_dsi_log_params(intel_dsi
);
1913 static void icl_dsi_add_properties(struct intel_connector
*connector
)
1915 const struct drm_display_mode
*fixed_mode
=
1916 intel_panel_preferred_fixed_mode(connector
);
1918 intel_attach_scaling_mode_property(&connector
->base
);
1920 drm_connector_set_panel_orientation_with_quirk(&connector
->base
,
1921 intel_dsi_get_panel_orientation(connector
),
1922 fixed_mode
->hdisplay
,
1923 fixed_mode
->vdisplay
);
1926 void icl_dsi_init(struct drm_i915_private
*dev_priv
,
1927 const struct intel_bios_encoder_data
*devdata
)
1929 struct intel_dsi
*intel_dsi
;
1930 struct intel_encoder
*encoder
;
1931 struct intel_connector
*intel_connector
;
1932 struct drm_connector
*connector
;
1935 port
= intel_bios_encoder_port(devdata
);
1936 if (port
== PORT_NONE
)
1939 intel_dsi
= kzalloc(sizeof(*intel_dsi
), GFP_KERNEL
);
1943 intel_connector
= intel_connector_alloc();
1944 if (!intel_connector
) {
1949 encoder
= &intel_dsi
->base
;
1950 intel_dsi
->attached_connector
= intel_connector
;
1951 connector
= &intel_connector
->base
;
1953 encoder
->devdata
= devdata
;
1955 /* register DSI encoder with DRM subsystem */
1956 drm_encoder_init(&dev_priv
->drm
, &encoder
->base
, &gen11_dsi_encoder_funcs
,
1957 DRM_MODE_ENCODER_DSI
, "DSI %c", port_name(port
));
1959 encoder
->pre_pll_enable
= gen11_dsi_pre_pll_enable
;
1960 encoder
->pre_enable
= gen11_dsi_pre_enable
;
1961 encoder
->enable
= gen11_dsi_enable
;
1962 encoder
->disable
= gen11_dsi_disable
;
1963 encoder
->post_disable
= gen11_dsi_post_disable
;
1964 encoder
->port
= port
;
1965 encoder
->get_config
= gen11_dsi_get_config
;
1966 encoder
->sync_state
= gen11_dsi_sync_state
;
1967 encoder
->update_pipe
= intel_backlight_update
;
1968 encoder
->compute_config
= gen11_dsi_compute_config
;
1969 encoder
->get_hw_state
= gen11_dsi_get_hw_state
;
1970 encoder
->initial_fastset_check
= gen11_dsi_initial_fastset_check
;
1971 encoder
->type
= INTEL_OUTPUT_DSI
;
1972 encoder
->cloneable
= 0;
1973 encoder
->pipe_mask
= ~0;
1974 encoder
->power_domain
= POWER_DOMAIN_PORT_DSI
;
1975 encoder
->get_power_domains
= gen11_dsi_get_power_domains
;
1976 encoder
->disable_clock
= gen11_dsi_gate_clocks
;
1977 encoder
->is_clock_enabled
= gen11_dsi_is_clock_enabled
;
1978 encoder
->shutdown
= intel_dsi_shutdown
;
1980 /* register DSI connector with DRM subsystem */
1981 drm_connector_init(&dev_priv
->drm
, connector
, &gen11_dsi_connector_funcs
,
1982 DRM_MODE_CONNECTOR_DSI
);
1983 drm_connector_helper_add(connector
, &gen11_dsi_connector_helper_funcs
);
1984 connector
->display_info
.subpixel_order
= SubPixelHorizontalRGB
;
1985 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
1987 /* attach connector to encoder */
1988 intel_connector_attach_encoder(intel_connector
, encoder
);
1990 intel_dsi
->panel_power_off_time
= ktime_get_boottime();
1992 intel_bios_init_panel_late(dev_priv
, &intel_connector
->panel
, encoder
->devdata
, NULL
);
1994 mutex_lock(&dev_priv
->drm
.mode_config
.mutex
);
1995 intel_panel_add_vbt_lfp_fixed_mode(intel_connector
);
1996 mutex_unlock(&dev_priv
->drm
.mode_config
.mutex
);
1998 if (!intel_panel_preferred_fixed_mode(intel_connector
)) {
1999 drm_err(&dev_priv
->drm
, "DSI fixed mode info missing\n");
2003 intel_panel_init(intel_connector
, NULL
);
2005 intel_backlight_setup(intel_connector
, INVALID_PIPE
);
2007 if (intel_connector
->panel
.vbt
.dsi
.config
->dual_link
)
2008 intel_dsi
->ports
= BIT(PORT_A
) | BIT(PORT_B
);
2010 intel_dsi
->ports
= BIT(port
);
2012 if (drm_WARN_ON(&dev_priv
->drm
, intel_connector
->panel
.vbt
.dsi
.bl_ports
& ~intel_dsi
->ports
))
2013 intel_connector
->panel
.vbt
.dsi
.bl_ports
&= intel_dsi
->ports
;
2015 if (drm_WARN_ON(&dev_priv
->drm
, intel_connector
->panel
.vbt
.dsi
.cabc_ports
& ~intel_dsi
->ports
))
2016 intel_connector
->panel
.vbt
.dsi
.cabc_ports
&= intel_dsi
->ports
;
2018 for_each_dsi_port(port
, intel_dsi
->ports
) {
2019 struct intel_dsi_host
*host
;
2021 host
= intel_dsi_host_init(intel_dsi
, &gen11_dsi_host_ops
, port
);
2025 intel_dsi
->dsi_hosts
[port
] = host
;
2028 if (!intel_dsi_vbt_init(intel_dsi
, MIPI_DSI_GENERIC_PANEL_ID
)) {
2029 drm_dbg_kms(&dev_priv
->drm
, "no device found\n");
2033 icl_dphy_param_init(intel_dsi
);
2035 icl_dsi_add_properties(intel_connector
);
2039 drm_connector_cleanup(connector
);
2040 drm_encoder_cleanup(&encoder
->base
);
2042 kfree(intel_connector
);