2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dma-resv.h>
28 #include <linux/i2c.h>
29 #include <linux/input.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/slab.h>
33 #include <linux/string_helpers.h>
35 #include <drm/display/drm_dp_helper.h>
36 #include <drm/drm_atomic.h>
37 #include <drm/drm_atomic_helper.h>
38 #include <drm/drm_atomic_uapi.h>
39 #include <drm/drm_damage_helper.h>
40 #include <drm/drm_edid.h>
41 #include <drm/drm_fourcc.h>
42 #include <drm/drm_probe_helper.h>
43 #include <drm/drm_rect.h>
45 #include "gem/i915_gem_lmem.h"
46 #include "gem/i915_gem_object.h"
51 #include "i915_config.h"
54 #include "i915_utils.h"
55 #include "i9xx_plane.h"
57 #include "intel_atomic.h"
58 #include "intel_atomic_plane.h"
59 #include "intel_audio.h"
61 #include "intel_cdclk.h"
62 #include "intel_clock_gating.h"
63 #include "intel_color.h"
64 #include "intel_crt.h"
65 #include "intel_crtc.h"
66 #include "intel_crtc_state_dump.h"
67 #include "intel_ddi.h"
69 #include "intel_display_driver.h"
70 #include "intel_display_power.h"
71 #include "intel_display_types.h"
72 #include "intel_dmc.h"
74 #include "intel_dp_link_training.h"
75 #include "intel_dp_mst.h"
76 #include "intel_dpll.h"
77 #include "intel_dpll_mgr.h"
78 #include "intel_dpt.h"
79 #include "intel_dpt_common.h"
80 #include "intel_drrs.h"
81 #include "intel_dsb.h"
82 #include "intel_dsi.h"
83 #include "intel_dvo.h"
85 #include "intel_fbc.h"
86 #include "intel_fbdev.h"
87 #include "intel_fdi.h"
88 #include "intel_fifo_underrun.h"
89 #include "intel_frontbuffer.h"
90 #include "intel_hdmi.h"
91 #include "intel_hotplug.h"
92 #include "intel_link_bw.h"
93 #include "intel_lvds.h"
94 #include "intel_lvds_regs.h"
95 #include "intel_modeset_setup.h"
96 #include "intel_modeset_verify.h"
97 #include "intel_overlay.h"
98 #include "intel_panel.h"
99 #include "intel_pch_display.h"
100 #include "intel_pch_refclk.h"
101 #include "intel_pcode.h"
102 #include "intel_pipe_crc.h"
103 #include "intel_plane_initial.h"
104 #include "intel_pmdemand.h"
105 #include "intel_pps.h"
106 #include "intel_psr.h"
107 #include "intel_psr_regs.h"
108 #include "intel_sdvo.h"
109 #include "intel_snps_phy.h"
110 #include "intel_tc.h"
111 #include "intel_tv.h"
112 #include "intel_vblank.h"
113 #include "intel_vdsc.h"
114 #include "intel_vdsc_regs.h"
115 #include "intel_vga.h"
116 #include "intel_vrr.h"
117 #include "intel_wm.h"
118 #include "skl_scaler.h"
119 #include "skl_universal_plane.h"
120 #include "skl_watermark.h"
122 #include "vlv_dsi_pll.h"
123 #include "vlv_dsi_regs.h"
124 #include "vlv_sideband.h"
126 static void intel_set_transcoder_timings(const struct intel_crtc_state
*crtc_state
);
127 static void intel_set_pipe_src_size(const struct intel_crtc_state
*crtc_state
);
128 static void hsw_set_transconf(const struct intel_crtc_state
*crtc_state
);
129 static void bdw_set_pipe_misc(const struct intel_crtc_state
*crtc_state
);
131 /* returns HPLL frequency in kHz */
132 int vlv_get_hpll_vco(struct drm_i915_private
*dev_priv
)
134 int hpll_freq
, vco_freq
[] = { 800, 1600, 2000, 2400 };
136 /* Obtain SKU information */
137 hpll_freq
= vlv_cck_read(dev_priv
, CCK_FUSE_REG
) &
138 CCK_FUSE_HPLL_FREQ_MASK
;
140 return vco_freq
[hpll_freq
] * 1000;
143 int vlv_get_cck_clock(struct drm_i915_private
*dev_priv
,
144 const char *name
, u32 reg
, int ref_freq
)
149 val
= vlv_cck_read(dev_priv
, reg
);
150 divider
= val
& CCK_FREQUENCY_VALUES
;
152 drm_WARN(&dev_priv
->drm
, (val
& CCK_FREQUENCY_STATUS
) !=
153 (divider
<< CCK_FREQUENCY_STATUS_SHIFT
),
154 "%s change in progress\n", name
);
156 return DIV_ROUND_CLOSEST(ref_freq
<< 1, divider
+ 1);
159 int vlv_get_cck_clock_hpll(struct drm_i915_private
*dev_priv
,
160 const char *name
, u32 reg
)
164 vlv_cck_get(dev_priv
);
166 if (dev_priv
->hpll_freq
== 0)
167 dev_priv
->hpll_freq
= vlv_get_hpll_vco(dev_priv
);
169 hpll
= vlv_get_cck_clock(dev_priv
, name
, reg
, dev_priv
->hpll_freq
);
171 vlv_cck_put(dev_priv
);
176 void intel_update_czclk(struct drm_i915_private
*dev_priv
)
178 if (!(IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)))
181 dev_priv
->czclk_freq
= vlv_get_cck_clock_hpll(dev_priv
, "czclk",
182 CCK_CZ_CLOCK_CONTROL
);
184 drm_dbg(&dev_priv
->drm
, "CZ clock rate: %d kHz\n",
185 dev_priv
->czclk_freq
);
188 static bool is_hdr_mode(const struct intel_crtc_state
*crtc_state
)
190 return (crtc_state
->active_planes
&
191 ~(icl_hdr_plane_mask() | BIT(PLANE_CURSOR
))) == 0;
194 /* WA Display #0827: Gen9:all */
196 skl_wa_827(struct drm_i915_private
*dev_priv
, enum pipe pipe
, bool enable
)
198 intel_de_rmw(dev_priv
, CLKGATE_DIS_PSL(pipe
),
199 DUPS1_GATING_DIS
| DUPS2_GATING_DIS
,
200 enable
? DUPS1_GATING_DIS
| DUPS2_GATING_DIS
: 0);
203 /* Wa_2006604312:icl,ehl */
205 icl_wa_scalerclkgating(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
208 intel_de_rmw(dev_priv
, CLKGATE_DIS_PSL(pipe
),
210 enable
? DPFR_GATING_DIS
: 0);
213 /* Wa_1604331009:icl,jsl,ehl */
215 icl_wa_cursorclkgating(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
218 intel_de_rmw(dev_priv
, CLKGATE_DIS_PSL(pipe
),
220 enable
? CURSOR_GATING_DIS
: 0);
224 is_trans_port_sync_slave(const struct intel_crtc_state
*crtc_state
)
226 return crtc_state
->master_transcoder
!= INVALID_TRANSCODER
;
230 is_trans_port_sync_master(const struct intel_crtc_state
*crtc_state
)
232 return crtc_state
->sync_mode_slaves_mask
!= 0;
236 is_trans_port_sync_mode(const struct intel_crtc_state
*crtc_state
)
238 return is_trans_port_sync_master(crtc_state
) ||
239 is_trans_port_sync_slave(crtc_state
);
242 static enum pipe
bigjoiner_master_pipe(const struct intel_crtc_state
*crtc_state
)
244 return ffs(crtc_state
->bigjoiner_pipes
) - 1;
247 u8
intel_crtc_bigjoiner_slave_pipes(const struct intel_crtc_state
*crtc_state
)
249 if (crtc_state
->bigjoiner_pipes
)
250 return crtc_state
->bigjoiner_pipes
& ~BIT(bigjoiner_master_pipe(crtc_state
));
255 bool intel_crtc_is_bigjoiner_slave(const struct intel_crtc_state
*crtc_state
)
257 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
259 return crtc_state
->bigjoiner_pipes
&&
260 crtc
->pipe
!= bigjoiner_master_pipe(crtc_state
);
263 bool intel_crtc_is_bigjoiner_master(const struct intel_crtc_state
*crtc_state
)
265 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
267 return crtc_state
->bigjoiner_pipes
&&
268 crtc
->pipe
== bigjoiner_master_pipe(crtc_state
);
271 static int intel_bigjoiner_num_pipes(const struct intel_crtc_state
*crtc_state
)
273 return hweight8(crtc_state
->bigjoiner_pipes
);
276 struct intel_crtc
*intel_master_crtc(const struct intel_crtc_state
*crtc_state
)
278 struct drm_i915_private
*i915
= to_i915(crtc_state
->uapi
.crtc
->dev
);
280 if (intel_crtc_is_bigjoiner_slave(crtc_state
))
281 return intel_crtc_for_pipe(i915
, bigjoiner_master_pipe(crtc_state
));
283 return to_intel_crtc(crtc_state
->uapi
.crtc
);
287 intel_wait_for_pipe_off(const struct intel_crtc_state
*old_crtc_state
)
289 struct intel_crtc
*crtc
= to_intel_crtc(old_crtc_state
->uapi
.crtc
);
290 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
292 if (DISPLAY_VER(dev_priv
) >= 4) {
293 enum transcoder cpu_transcoder
= old_crtc_state
->cpu_transcoder
;
295 /* Wait for the Pipe State to go off */
296 if (intel_de_wait_for_clear(dev_priv
, TRANSCONF(cpu_transcoder
),
297 TRANSCONF_STATE_ENABLE
, 100))
298 drm_WARN(&dev_priv
->drm
, 1, "pipe_off wait timed out\n");
300 intel_wait_for_pipe_scanline_stopped(crtc
);
304 void assert_transcoder(struct drm_i915_private
*dev_priv
,
305 enum transcoder cpu_transcoder
, bool state
)
308 enum intel_display_power_domain power_domain
;
309 intel_wakeref_t wakeref
;
311 /* we keep both pipes enabled on 830 */
312 if (IS_I830(dev_priv
))
315 power_domain
= POWER_DOMAIN_TRANSCODER(cpu_transcoder
);
316 wakeref
= intel_display_power_get_if_enabled(dev_priv
, power_domain
);
318 u32 val
= intel_de_read(dev_priv
, TRANSCONF(cpu_transcoder
));
319 cur_state
= !!(val
& TRANSCONF_ENABLE
);
321 intel_display_power_put(dev_priv
, power_domain
, wakeref
);
326 I915_STATE_WARN(dev_priv
, cur_state
!= state
,
327 "transcoder %s assertion failure (expected %s, current %s)\n",
328 transcoder_name(cpu_transcoder
), str_on_off(state
),
329 str_on_off(cur_state
));
332 static void assert_plane(struct intel_plane
*plane
, bool state
)
334 struct drm_i915_private
*i915
= to_i915(plane
->base
.dev
);
338 cur_state
= plane
->get_hw_state(plane
, &pipe
);
340 I915_STATE_WARN(i915
, cur_state
!= state
,
341 "%s assertion failure (expected %s, current %s)\n",
342 plane
->base
.name
, str_on_off(state
),
343 str_on_off(cur_state
));
346 #define assert_plane_enabled(p) assert_plane(p, true)
347 #define assert_plane_disabled(p) assert_plane(p, false)
349 static void assert_planes_disabled(struct intel_crtc
*crtc
)
351 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
352 struct intel_plane
*plane
;
354 for_each_intel_plane_on_crtc(&dev_priv
->drm
, crtc
, plane
)
355 assert_plane_disabled(plane
);
358 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
,
359 struct intel_digital_port
*dig_port
,
360 unsigned int expected_mask
)
365 switch (dig_port
->base
.port
) {
367 MISSING_CASE(dig_port
->base
.port
);
370 port_mask
= DPLL_PORTB_READY_MASK
;
374 port_mask
= DPLL_PORTC_READY_MASK
;
379 port_mask
= DPLL_PORTD_READY_MASK
;
380 dpll_reg
= DPIO_PHY_STATUS
;
384 if (intel_de_wait_for_register(dev_priv
, dpll_reg
,
385 port_mask
, expected_mask
, 1000))
386 drm_WARN(&dev_priv
->drm
, 1,
387 "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n",
388 dig_port
->base
.base
.base
.id
, dig_port
->base
.base
.name
,
389 intel_de_read(dev_priv
, dpll_reg
) & port_mask
,
393 void intel_enable_transcoder(const struct intel_crtc_state
*new_crtc_state
)
395 struct intel_crtc
*crtc
= to_intel_crtc(new_crtc_state
->uapi
.crtc
);
396 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
397 enum transcoder cpu_transcoder
= new_crtc_state
->cpu_transcoder
;
398 enum pipe pipe
= crtc
->pipe
;
401 drm_dbg_kms(&dev_priv
->drm
, "enabling pipe %c\n", pipe_name(pipe
));
403 assert_planes_disabled(crtc
);
406 * A pipe without a PLL won't actually be able to drive bits from
407 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
410 if (HAS_GMCH(dev_priv
)) {
411 if (intel_crtc_has_type(new_crtc_state
, INTEL_OUTPUT_DSI
))
412 assert_dsi_pll_enabled(dev_priv
);
414 assert_pll_enabled(dev_priv
, pipe
);
416 if (new_crtc_state
->has_pch_encoder
) {
417 /* if driving the PCH, we need FDI enabled */
418 assert_fdi_rx_pll_enabled(dev_priv
,
419 intel_crtc_pch_transcoder(crtc
));
420 assert_fdi_tx_pll_enabled(dev_priv
,
421 (enum pipe
) cpu_transcoder
);
423 /* FIXME: assert CPU port conditions for SNB+ */
426 /* Wa_22012358565:adl-p */
427 if (DISPLAY_VER(dev_priv
) == 13)
428 intel_de_rmw(dev_priv
, PIPE_ARB_CTL(pipe
),
429 0, PIPE_ARB_USE_PROG_SLOTS
);
431 val
= intel_de_read(dev_priv
, TRANSCONF(cpu_transcoder
));
432 if (val
& TRANSCONF_ENABLE
) {
433 /* we keep both pipes enabled on 830 */
434 drm_WARN_ON(&dev_priv
->drm
, !IS_I830(dev_priv
));
438 intel_de_write(dev_priv
, TRANSCONF(cpu_transcoder
),
439 val
| TRANSCONF_ENABLE
);
440 intel_de_posting_read(dev_priv
, TRANSCONF(cpu_transcoder
));
443 * Until the pipe starts PIPEDSL reads will return a stale value,
444 * which causes an apparent vblank timestamp jump when PIPEDSL
445 * resets to its proper value. That also messes up the frame count
446 * when it's derived from the timestamps. So let's wait for the
447 * pipe to start properly before we call drm_crtc_vblank_on()
449 if (intel_crtc_max_vblank_count(new_crtc_state
) == 0)
450 intel_wait_for_pipe_scanline_moving(crtc
);
453 void intel_disable_transcoder(const struct intel_crtc_state
*old_crtc_state
)
455 struct intel_crtc
*crtc
= to_intel_crtc(old_crtc_state
->uapi
.crtc
);
456 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
457 enum transcoder cpu_transcoder
= old_crtc_state
->cpu_transcoder
;
458 enum pipe pipe
= crtc
->pipe
;
461 drm_dbg_kms(&dev_priv
->drm
, "disabling pipe %c\n", pipe_name(pipe
));
464 * Make sure planes won't keep trying to pump pixels to us,
465 * or we might hang the display.
467 assert_planes_disabled(crtc
);
469 val
= intel_de_read(dev_priv
, TRANSCONF(cpu_transcoder
));
470 if ((val
& TRANSCONF_ENABLE
) == 0)
474 * Double wide has implications for planes
475 * so best keep it disabled when not needed.
477 if (old_crtc_state
->double_wide
)
478 val
&= ~TRANSCONF_DOUBLE_WIDE
;
480 /* Don't disable pipe or pipe PLLs if needed */
481 if (!IS_I830(dev_priv
))
482 val
&= ~TRANSCONF_ENABLE
;
484 intel_de_write(dev_priv
, TRANSCONF(cpu_transcoder
), val
);
486 if (DISPLAY_VER(dev_priv
) >= 12)
487 intel_de_rmw(dev_priv
, hsw_chicken_trans_reg(dev_priv
, cpu_transcoder
),
488 FECSTALL_DIS_DPTSTREAM_DPTTG
, 0);
490 if ((val
& TRANSCONF_ENABLE
) == 0)
491 intel_wait_for_pipe_off(old_crtc_state
);
494 unsigned int intel_rotation_info_size(const struct intel_rotation_info
*rot_info
)
496 unsigned int size
= 0;
499 for (i
= 0 ; i
< ARRAY_SIZE(rot_info
->plane
); i
++)
500 size
+= rot_info
->plane
[i
].dst_stride
* rot_info
->plane
[i
].width
;
505 unsigned int intel_remapped_info_size(const struct intel_remapped_info
*rem_info
)
507 unsigned int size
= 0;
510 for (i
= 0 ; i
< ARRAY_SIZE(rem_info
->plane
); i
++) {
511 unsigned int plane_size
;
513 if (rem_info
->plane
[i
].linear
)
514 plane_size
= rem_info
->plane
[i
].size
;
516 plane_size
= rem_info
->plane
[i
].dst_stride
* rem_info
->plane
[i
].height
;
521 if (rem_info
->plane_alignment
)
522 size
= ALIGN(size
, rem_info
->plane_alignment
);
530 bool intel_plane_uses_fence(const struct intel_plane_state
*plane_state
)
532 struct intel_plane
*plane
= to_intel_plane(plane_state
->uapi
.plane
);
533 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
535 return DISPLAY_VER(dev_priv
) < 4 ||
537 plane_state
->view
.gtt
.type
== I915_GTT_VIEW_NORMAL
);
541 * Convert the x/y offsets into a linear offset.
542 * Only valid with 0/180 degree rotation, which is fine since linear
543 * offset is only used with linear buffers on pre-hsw and tiled buffers
544 * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
546 u32
intel_fb_xy_to_linear(int x
, int y
,
547 const struct intel_plane_state
*state
,
550 const struct drm_framebuffer
*fb
= state
->hw
.fb
;
551 unsigned int cpp
= fb
->format
->cpp
[color_plane
];
552 unsigned int pitch
= state
->view
.color_plane
[color_plane
].mapping_stride
;
554 return y
* pitch
+ x
* cpp
;
558 * Add the x/y offsets derived from fb->offsets[] to the user
559 * specified plane src x/y offsets. The resulting x/y offsets
560 * specify the start of scanout from the beginning of the gtt mapping.
562 void intel_add_fb_offsets(int *x
, int *y
,
563 const struct intel_plane_state
*state
,
567 *x
+= state
->view
.color_plane
[color_plane
].x
;
568 *y
+= state
->view
.color_plane
[color_plane
].y
;
571 u32
intel_plane_fb_max_stride(struct drm_i915_private
*dev_priv
,
572 u32 pixel_format
, u64 modifier
)
574 struct intel_crtc
*crtc
;
575 struct intel_plane
*plane
;
577 if (!HAS_DISPLAY(dev_priv
))
581 * We assume the primary plane for pipe A has
582 * the highest stride limits of them all,
583 * if in case pipe A is disabled, use the first pipe from pipe_mask.
585 crtc
= intel_first_crtc(dev_priv
);
589 plane
= to_intel_plane(crtc
->base
.primary
);
591 return plane
->max_stride(plane
, pixel_format
, modifier
,
595 void intel_set_plane_visible(struct intel_crtc_state
*crtc_state
,
596 struct intel_plane_state
*plane_state
,
599 struct intel_plane
*plane
= to_intel_plane(plane_state
->uapi
.plane
);
601 plane_state
->uapi
.visible
= visible
;
604 crtc_state
->uapi
.plane_mask
|= drm_plane_mask(&plane
->base
);
606 crtc_state
->uapi
.plane_mask
&= ~drm_plane_mask(&plane
->base
);
609 void intel_plane_fixup_bitmasks(struct intel_crtc_state
*crtc_state
)
611 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->uapi
.crtc
->dev
);
612 struct drm_plane
*plane
;
615 * Active_planes aliases if multiple "primary" or cursor planes
616 * have been used on the same (or wrong) pipe. plane_mask uses
617 * unique ids, hence we can use that to reconstruct active_planes.
619 crtc_state
->enabled_planes
= 0;
620 crtc_state
->active_planes
= 0;
622 drm_for_each_plane_mask(plane
, &dev_priv
->drm
,
623 crtc_state
->uapi
.plane_mask
) {
624 crtc_state
->enabled_planes
|= BIT(to_intel_plane(plane
)->id
);
625 crtc_state
->active_planes
|= BIT(to_intel_plane(plane
)->id
);
629 void intel_plane_disable_noatomic(struct intel_crtc
*crtc
,
630 struct intel_plane
*plane
)
632 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
633 struct intel_crtc_state
*crtc_state
=
634 to_intel_crtc_state(crtc
->base
.state
);
635 struct intel_plane_state
*plane_state
=
636 to_intel_plane_state(plane
->base
.state
);
638 drm_dbg_kms(&dev_priv
->drm
,
639 "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n",
640 plane
->base
.base
.id
, plane
->base
.name
,
641 crtc
->base
.base
.id
, crtc
->base
.name
);
643 intel_set_plane_visible(crtc_state
, plane_state
, false);
644 intel_plane_fixup_bitmasks(crtc_state
);
645 crtc_state
->data_rate
[plane
->id
] = 0;
646 crtc_state
->data_rate_y
[plane
->id
] = 0;
647 crtc_state
->rel_data_rate
[plane
->id
] = 0;
648 crtc_state
->rel_data_rate_y
[plane
->id
] = 0;
649 crtc_state
->min_cdclk
[plane
->id
] = 0;
651 if ((crtc_state
->active_planes
& ~BIT(PLANE_CURSOR
)) == 0 &&
652 hsw_ips_disable(crtc_state
)) {
653 crtc_state
->ips_enabled
= false;
654 intel_crtc_wait_for_next_vblank(crtc
);
658 * Vblank time updates from the shadow to live plane control register
659 * are blocked if the memory self-refresh mode is active at that
660 * moment. So to make sure the plane gets truly disabled, disable
661 * first the self-refresh mode. The self-refresh enable bit in turn
662 * will be checked/applied by the HW only at the next frame start
663 * event which is after the vblank start event, so we need to have a
664 * wait-for-vblank between disabling the plane and the pipe.
666 if (HAS_GMCH(dev_priv
) &&
667 intel_set_memory_cxsr(dev_priv
, false))
668 intel_crtc_wait_for_next_vblank(crtc
);
671 * Gen2 reports pipe underruns whenever all planes are disabled.
672 * So disable underrun reporting before all the planes get disabled.
674 if (DISPLAY_VER(dev_priv
) == 2 && !crtc_state
->active_planes
)
675 intel_set_cpu_fifo_underrun_reporting(dev_priv
, crtc
->pipe
, false);
677 intel_plane_disable_arm(plane
, crtc_state
);
678 intel_crtc_wait_for_next_vblank(crtc
);
682 intel_plane_fence_y_offset(const struct intel_plane_state
*plane_state
)
686 intel_plane_adjust_aligned_offset(&x
, &y
, plane_state
, 0,
687 plane_state
->view
.color_plane
[0].offset
, 0);
692 static void icl_set_pipe_chicken(const struct intel_crtc_state
*crtc_state
)
694 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
695 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
696 enum pipe pipe
= crtc
->pipe
;
699 tmp
= intel_de_read(dev_priv
, PIPE_CHICKEN(pipe
));
702 * Display WA #1153: icl
703 * enable hardware to bypass the alpha math
704 * and rounding for per-pixel values 00 and 0xff
706 tmp
|= PER_PIXEL_ALPHA_BYPASS_EN
;
708 * Display WA # 1605353570: icl
709 * Set the pixel rounding bit to 1 for allowing
710 * passthrough of Frame buffer pixels unmodified
713 tmp
|= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU
;
716 * Underrun recovery must always be disabled on display 13+.
717 * DG2 chicken bit meaning is inverted compared to other platforms.
719 if (IS_DG2(dev_priv
))
720 tmp
&= ~UNDERRUN_RECOVERY_ENABLE_DG2
;
721 else if (DISPLAY_VER(dev_priv
) >= 13)
722 tmp
|= UNDERRUN_RECOVERY_DISABLE_ADLP
;
724 /* Wa_14010547955:dg2 */
725 if (IS_DG2(dev_priv
))
726 tmp
|= DG2_RENDER_CCSTAG_4_3_EN
;
728 intel_de_write(dev_priv
, PIPE_CHICKEN(pipe
), tmp
);
731 bool intel_has_pending_fb_unpin(struct drm_i915_private
*dev_priv
)
733 struct drm_crtc
*crtc
;
736 drm_for_each_crtc(crtc
, &dev_priv
->drm
) {
737 struct drm_crtc_commit
*commit
;
738 spin_lock(&crtc
->commit_lock
);
739 commit
= list_first_entry_or_null(&crtc
->commit_list
,
740 struct drm_crtc_commit
, commit_entry
);
741 cleanup_done
= commit
?
742 try_wait_for_completion(&commit
->cleanup_done
) : true;
743 spin_unlock(&crtc
->commit_lock
);
748 intel_crtc_wait_for_next_vblank(to_intel_crtc(crtc
));
757 * Finds the encoder associated with the given CRTC. This can only be
758 * used when we know that the CRTC isn't feeding multiple encoders!
760 struct intel_encoder
*
761 intel_get_crtc_new_encoder(const struct intel_atomic_state
*state
,
762 const struct intel_crtc_state
*crtc_state
)
764 const struct drm_connector_state
*connector_state
;
765 const struct drm_connector
*connector
;
766 struct intel_encoder
*encoder
= NULL
;
767 struct intel_crtc
*master_crtc
;
768 int num_encoders
= 0;
771 master_crtc
= intel_master_crtc(crtc_state
);
773 for_each_new_connector_in_state(&state
->base
, connector
, connector_state
, i
) {
774 if (connector_state
->crtc
!= &master_crtc
->base
)
777 encoder
= to_intel_encoder(connector_state
->best_encoder
);
781 drm_WARN(state
->base
.dev
, num_encoders
!= 1,
782 "%d encoders for pipe %c\n",
783 num_encoders
, pipe_name(master_crtc
->pipe
));
788 static void ilk_pfit_enable(const struct intel_crtc_state
*crtc_state
)
790 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
791 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
792 const struct drm_rect
*dst
= &crtc_state
->pch_pfit
.dst
;
793 enum pipe pipe
= crtc
->pipe
;
794 int width
= drm_rect_width(dst
);
795 int height
= drm_rect_height(dst
);
799 if (!crtc_state
->pch_pfit
.enabled
)
802 /* Force use of hard-coded filter coefficients
803 * as some pre-programmed values are broken,
806 if (IS_IVYBRIDGE(dev_priv
) || IS_HASWELL(dev_priv
))
807 intel_de_write_fw(dev_priv
, PF_CTL(pipe
), PF_ENABLE
|
808 PF_FILTER_MED_3x3
| PF_PIPE_SEL_IVB(pipe
));
810 intel_de_write_fw(dev_priv
, PF_CTL(pipe
), PF_ENABLE
|
812 intel_de_write_fw(dev_priv
, PF_WIN_POS(pipe
),
813 PF_WIN_XPOS(x
) | PF_WIN_YPOS(y
));
814 intel_de_write_fw(dev_priv
, PF_WIN_SZ(pipe
),
815 PF_WIN_XSIZE(width
) | PF_WIN_YSIZE(height
));
818 static void intel_crtc_dpms_overlay_disable(struct intel_crtc
*crtc
)
821 (void) intel_overlay_switch_off(crtc
->overlay
);
823 /* Let userspace switch the overlay on again. In most cases userspace
824 * has to recompute where to put it anyway.
828 static bool needs_nv12_wa(const struct intel_crtc_state
*crtc_state
)
830 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->uapi
.crtc
->dev
);
832 if (!crtc_state
->nv12_planes
)
835 /* WA Display #0827: Gen9:all */
836 if (DISPLAY_VER(dev_priv
) == 9)
842 static bool needs_scalerclk_wa(const struct intel_crtc_state
*crtc_state
)
844 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->uapi
.crtc
->dev
);
846 /* Wa_2006604312:icl,ehl */
847 if (crtc_state
->scaler_state
.scaler_users
> 0 && DISPLAY_VER(dev_priv
) == 11)
853 static bool needs_cursorclk_wa(const struct intel_crtc_state
*crtc_state
)
855 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->uapi
.crtc
->dev
);
857 /* Wa_1604331009:icl,jsl,ehl */
858 if (is_hdr_mode(crtc_state
) &&
859 crtc_state
->active_planes
& BIT(PLANE_CURSOR
) &&
860 DISPLAY_VER(dev_priv
) == 11)
866 static void intel_async_flip_vtd_wa(struct drm_i915_private
*i915
,
867 enum pipe pipe
, bool enable
)
869 if (DISPLAY_VER(i915
) == 9) {
871 * "Plane N strech max must be programmed to 11b (x1)
872 * when Async flips are enabled on that plane."
874 intel_de_rmw(i915
, CHICKEN_PIPESL_1(pipe
),
875 SKL_PLANE1_STRETCH_MAX_MASK
,
876 enable
? SKL_PLANE1_STRETCH_MAX_X1
: SKL_PLANE1_STRETCH_MAX_X8
);
878 /* Also needed on HSW/BDW albeit undocumented */
879 intel_de_rmw(i915
, CHICKEN_PIPESL_1(pipe
),
880 HSW_PRI_STRETCH_MAX_MASK
,
881 enable
? HSW_PRI_STRETCH_MAX_X1
: HSW_PRI_STRETCH_MAX_X8
);
885 static bool needs_async_flip_vtd_wa(const struct intel_crtc_state
*crtc_state
)
887 struct drm_i915_private
*i915
= to_i915(crtc_state
->uapi
.crtc
->dev
);
889 return crtc_state
->uapi
.async_flip
&& i915_vtd_active(i915
) &&
890 (DISPLAY_VER(i915
) == 9 || IS_BROADWELL(i915
) || IS_HASWELL(i915
));
893 static void intel_encoders_audio_enable(struct intel_atomic_state
*state
,
894 struct intel_crtc
*crtc
)
896 const struct intel_crtc_state
*crtc_state
=
897 intel_atomic_get_new_crtc_state(state
, crtc
);
898 const struct drm_connector_state
*conn_state
;
899 struct drm_connector
*conn
;
902 for_each_new_connector_in_state(&state
->base
, conn
, conn_state
, i
) {
903 struct intel_encoder
*encoder
=
904 to_intel_encoder(conn_state
->best_encoder
);
906 if (conn_state
->crtc
!= &crtc
->base
)
909 if (encoder
->audio_enable
)
910 encoder
->audio_enable(encoder
, crtc_state
, conn_state
);
914 static void intel_encoders_audio_disable(struct intel_atomic_state
*state
,
915 struct intel_crtc
*crtc
)
917 const struct intel_crtc_state
*old_crtc_state
=
918 intel_atomic_get_old_crtc_state(state
, crtc
);
919 const struct drm_connector_state
*old_conn_state
;
920 struct drm_connector
*conn
;
923 for_each_old_connector_in_state(&state
->base
, conn
, old_conn_state
, i
) {
924 struct intel_encoder
*encoder
=
925 to_intel_encoder(old_conn_state
->best_encoder
);
927 if (old_conn_state
->crtc
!= &crtc
->base
)
930 if (encoder
->audio_disable
)
931 encoder
->audio_disable(encoder
, old_crtc_state
, old_conn_state
);
935 #define is_enabling(feature, old_crtc_state, new_crtc_state) \
936 ((!(old_crtc_state)->feature || intel_crtc_needs_modeset(new_crtc_state)) && \
937 (new_crtc_state)->feature)
938 #define is_disabling(feature, old_crtc_state, new_crtc_state) \
939 ((old_crtc_state)->feature && \
940 (!(new_crtc_state)->feature || intel_crtc_needs_modeset(new_crtc_state)))
942 static bool planes_enabling(const struct intel_crtc_state
*old_crtc_state
,
943 const struct intel_crtc_state
*new_crtc_state
)
945 if (!new_crtc_state
->hw
.active
)
948 return is_enabling(active_planes
, old_crtc_state
, new_crtc_state
);
951 static bool planes_disabling(const struct intel_crtc_state
*old_crtc_state
,
952 const struct intel_crtc_state
*new_crtc_state
)
954 if (!old_crtc_state
->hw
.active
)
957 return is_disabling(active_planes
, old_crtc_state
, new_crtc_state
);
960 static bool vrr_params_changed(const struct intel_crtc_state
*old_crtc_state
,
961 const struct intel_crtc_state
*new_crtc_state
)
963 return old_crtc_state
->vrr
.flipline
!= new_crtc_state
->vrr
.flipline
||
964 old_crtc_state
->vrr
.vmin
!= new_crtc_state
->vrr
.vmin
||
965 old_crtc_state
->vrr
.vmax
!= new_crtc_state
->vrr
.vmax
||
966 old_crtc_state
->vrr
.guardband
!= new_crtc_state
->vrr
.guardband
||
967 old_crtc_state
->vrr
.pipeline_full
!= new_crtc_state
->vrr
.pipeline_full
;
970 static bool vrr_enabling(const struct intel_crtc_state
*old_crtc_state
,
971 const struct intel_crtc_state
*new_crtc_state
)
973 if (!new_crtc_state
->hw
.active
)
976 return is_enabling(vrr
.enable
, old_crtc_state
, new_crtc_state
) ||
977 (new_crtc_state
->vrr
.enable
&&
978 (new_crtc_state
->update_m_n
|| new_crtc_state
->update_lrr
||
979 vrr_params_changed(old_crtc_state
, new_crtc_state
)));
982 static bool vrr_disabling(const struct intel_crtc_state
*old_crtc_state
,
983 const struct intel_crtc_state
*new_crtc_state
)
985 if (!old_crtc_state
->hw
.active
)
988 return is_disabling(vrr
.enable
, old_crtc_state
, new_crtc_state
) ||
989 (old_crtc_state
->vrr
.enable
&&
990 (new_crtc_state
->update_m_n
|| new_crtc_state
->update_lrr
||
991 vrr_params_changed(old_crtc_state
, new_crtc_state
)));
994 static bool audio_enabling(const struct intel_crtc_state
*old_crtc_state
,
995 const struct intel_crtc_state
*new_crtc_state
)
997 if (!new_crtc_state
->hw
.active
)
1000 return is_enabling(has_audio
, old_crtc_state
, new_crtc_state
) ||
1001 (new_crtc_state
->has_audio
&&
1002 memcmp(old_crtc_state
->eld
, new_crtc_state
->eld
, MAX_ELD_BYTES
) != 0);
1005 static bool audio_disabling(const struct intel_crtc_state
*old_crtc_state
,
1006 const struct intel_crtc_state
*new_crtc_state
)
1008 if (!old_crtc_state
->hw
.active
)
1011 return is_disabling(has_audio
, old_crtc_state
, new_crtc_state
) ||
1012 (old_crtc_state
->has_audio
&&
1013 memcmp(old_crtc_state
->eld
, new_crtc_state
->eld
, MAX_ELD_BYTES
) != 0);
1019 static void intel_post_plane_update(struct intel_atomic_state
*state
,
1020 struct intel_crtc
*crtc
)
1022 struct drm_i915_private
*dev_priv
= to_i915(state
->base
.dev
);
1023 const struct intel_crtc_state
*old_crtc_state
=
1024 intel_atomic_get_old_crtc_state(state
, crtc
);
1025 const struct intel_crtc_state
*new_crtc_state
=
1026 intel_atomic_get_new_crtc_state(state
, crtc
);
1027 enum pipe pipe
= crtc
->pipe
;
1029 intel_psr_post_plane_update(state
, crtc
);
1031 intel_frontbuffer_flip(dev_priv
, new_crtc_state
->fb_bits
);
1033 if (new_crtc_state
->update_wm_post
&& new_crtc_state
->hw
.active
)
1034 intel_update_watermarks(dev_priv
);
1036 intel_fbc_post_update(state
, crtc
);
1038 if (needs_async_flip_vtd_wa(old_crtc_state
) &&
1039 !needs_async_flip_vtd_wa(new_crtc_state
))
1040 intel_async_flip_vtd_wa(dev_priv
, pipe
, false);
1042 if (needs_nv12_wa(old_crtc_state
) &&
1043 !needs_nv12_wa(new_crtc_state
))
1044 skl_wa_827(dev_priv
, pipe
, false);
1046 if (needs_scalerclk_wa(old_crtc_state
) &&
1047 !needs_scalerclk_wa(new_crtc_state
))
1048 icl_wa_scalerclkgating(dev_priv
, pipe
, false);
1050 if (needs_cursorclk_wa(old_crtc_state
) &&
1051 !needs_cursorclk_wa(new_crtc_state
))
1052 icl_wa_cursorclkgating(dev_priv
, pipe
, false);
1054 if (intel_crtc_needs_color_update(new_crtc_state
))
1055 intel_color_post_update(new_crtc_state
);
1057 if (audio_enabling(old_crtc_state
, new_crtc_state
))
1058 intel_encoders_audio_enable(state
, crtc
);
1061 static void intel_crtc_enable_flip_done(struct intel_atomic_state
*state
,
1062 struct intel_crtc
*crtc
)
1064 const struct intel_crtc_state
*crtc_state
=
1065 intel_atomic_get_new_crtc_state(state
, crtc
);
1066 u8 update_planes
= crtc_state
->update_planes
;
1067 const struct intel_plane_state __maybe_unused
*plane_state
;
1068 struct intel_plane
*plane
;
1071 for_each_new_intel_plane_in_state(state
, plane
, plane_state
, i
) {
1072 if (plane
->pipe
== crtc
->pipe
&&
1073 update_planes
& BIT(plane
->id
))
1074 plane
->enable_flip_done(plane
);
1078 static void intel_crtc_disable_flip_done(struct intel_atomic_state
*state
,
1079 struct intel_crtc
*crtc
)
1081 const struct intel_crtc_state
*crtc_state
=
1082 intel_atomic_get_new_crtc_state(state
, crtc
);
1083 u8 update_planes
= crtc_state
->update_planes
;
1084 const struct intel_plane_state __maybe_unused
*plane_state
;
1085 struct intel_plane
*plane
;
1088 for_each_new_intel_plane_in_state(state
, plane
, plane_state
, i
) {
1089 if (plane
->pipe
== crtc
->pipe
&&
1090 update_planes
& BIT(plane
->id
))
1091 plane
->disable_flip_done(plane
);
1095 static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state
*state
,
1096 struct intel_crtc
*crtc
)
1098 const struct intel_crtc_state
*old_crtc_state
=
1099 intel_atomic_get_old_crtc_state(state
, crtc
);
1100 const struct intel_crtc_state
*new_crtc_state
=
1101 intel_atomic_get_new_crtc_state(state
, crtc
);
1102 u8 disable_async_flip_planes
= old_crtc_state
->async_flip_planes
&
1103 ~new_crtc_state
->async_flip_planes
;
1104 const struct intel_plane_state
*old_plane_state
;
1105 struct intel_plane
*plane
;
1106 bool need_vbl_wait
= false;
1109 for_each_old_intel_plane_in_state(state
, plane
, old_plane_state
, i
) {
1110 if (plane
->need_async_flip_disable_wa
&&
1111 plane
->pipe
== crtc
->pipe
&&
1112 disable_async_flip_planes
& BIT(plane
->id
)) {
1114 * Apart from the async flip bit we want to
1115 * preserve the old state for the plane.
1117 plane
->async_flip(plane
, old_crtc_state
,
1118 old_plane_state
, false);
1119 need_vbl_wait
= true;
1124 intel_crtc_wait_for_next_vblank(crtc
);
1127 static void intel_pre_plane_update(struct intel_atomic_state
*state
,
1128 struct intel_crtc
*crtc
)
1130 struct drm_i915_private
*dev_priv
= to_i915(state
->base
.dev
);
1131 const struct intel_crtc_state
*old_crtc_state
=
1132 intel_atomic_get_old_crtc_state(state
, crtc
);
1133 const struct intel_crtc_state
*new_crtc_state
=
1134 intel_atomic_get_new_crtc_state(state
, crtc
);
1135 enum pipe pipe
= crtc
->pipe
;
1137 if (vrr_disabling(old_crtc_state
, new_crtc_state
)) {
1138 intel_vrr_disable(old_crtc_state
);
1139 intel_crtc_update_active_timings(old_crtc_state
, false);
1142 if (audio_disabling(old_crtc_state
, new_crtc_state
))
1143 intel_encoders_audio_disable(state
, crtc
);
1145 intel_drrs_deactivate(old_crtc_state
);
1147 intel_psr_pre_plane_update(state
, crtc
);
1149 if (hsw_ips_pre_update(state
, crtc
))
1150 intel_crtc_wait_for_next_vblank(crtc
);
1152 if (intel_fbc_pre_update(state
, crtc
))
1153 intel_crtc_wait_for_next_vblank(crtc
);
1155 if (!needs_async_flip_vtd_wa(old_crtc_state
) &&
1156 needs_async_flip_vtd_wa(new_crtc_state
))
1157 intel_async_flip_vtd_wa(dev_priv
, pipe
, true);
1159 /* Display WA 827 */
1160 if (!needs_nv12_wa(old_crtc_state
) &&
1161 needs_nv12_wa(new_crtc_state
))
1162 skl_wa_827(dev_priv
, pipe
, true);
1164 /* Wa_2006604312:icl,ehl */
1165 if (!needs_scalerclk_wa(old_crtc_state
) &&
1166 needs_scalerclk_wa(new_crtc_state
))
1167 icl_wa_scalerclkgating(dev_priv
, pipe
, true);
1169 /* Wa_1604331009:icl,jsl,ehl */
1170 if (!needs_cursorclk_wa(old_crtc_state
) &&
1171 needs_cursorclk_wa(new_crtc_state
))
1172 icl_wa_cursorclkgating(dev_priv
, pipe
, true);
1175 * Vblank time updates from the shadow to live plane control register
1176 * are blocked if the memory self-refresh mode is active at that
1177 * moment. So to make sure the plane gets truly disabled, disable
1178 * first the self-refresh mode. The self-refresh enable bit in turn
1179 * will be checked/applied by the HW only at the next frame start
1180 * event which is after the vblank start event, so we need to have a
1181 * wait-for-vblank between disabling the plane and the pipe.
1183 if (HAS_GMCH(dev_priv
) && old_crtc_state
->hw
.active
&&
1184 new_crtc_state
->disable_cxsr
&& intel_set_memory_cxsr(dev_priv
, false))
1185 intel_crtc_wait_for_next_vblank(crtc
);
1188 * IVB workaround: must disable low power watermarks for at least
1189 * one frame before enabling scaling. LP watermarks can be re-enabled
1190 * when scaling is disabled.
1192 * WaCxSRDisabledForSpriteScaling:ivb
1194 if (old_crtc_state
->hw
.active
&&
1195 new_crtc_state
->disable_lp_wm
&& ilk_disable_lp_wm(dev_priv
))
1196 intel_crtc_wait_for_next_vblank(crtc
);
1199 * If we're doing a modeset we don't need to do any
1200 * pre-vblank watermark programming here.
1202 if (!intel_crtc_needs_modeset(new_crtc_state
)) {
1204 * For platforms that support atomic watermarks, program the
1205 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
1206 * will be the intermediate values that are safe for both pre- and
1207 * post- vblank; when vblank happens, the 'active' values will be set
1208 * to the final 'target' values and we'll do this again to get the
1209 * optimal watermarks. For gen9+ platforms, the values we program here
1210 * will be the final target values which will get automatically latched
1211 * at vblank time; no further programming will be necessary.
1213 * If a platform hasn't been transitioned to atomic watermarks yet,
1214 * we'll continue to update watermarks the old way, if flags tell
1217 if (!intel_initial_watermarks(state
, crtc
))
1218 if (new_crtc_state
->update_wm_pre
)
1219 intel_update_watermarks(dev_priv
);
1223 * Gen2 reports pipe underruns whenever all planes are disabled.
1224 * So disable underrun reporting before all the planes get disabled.
1226 * We do this after .initial_watermarks() so that we have a
1227 * chance of catching underruns with the intermediate watermarks
1228 * vs. the old plane configuration.
1230 if (DISPLAY_VER(dev_priv
) == 2 && planes_disabling(old_crtc_state
, new_crtc_state
))
1231 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
1234 * WA for platforms where async address update enable bit
1235 * is double buffered and only latched at start of vblank.
1237 if (old_crtc_state
->async_flip_planes
& ~new_crtc_state
->async_flip_planes
)
1238 intel_crtc_async_flip_disable_wa(state
, crtc
);
1241 static void intel_crtc_disable_planes(struct intel_atomic_state
*state
,
1242 struct intel_crtc
*crtc
)
1244 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1245 const struct intel_crtc_state
*new_crtc_state
=
1246 intel_atomic_get_new_crtc_state(state
, crtc
);
1247 unsigned int update_mask
= new_crtc_state
->update_planes
;
1248 const struct intel_plane_state
*old_plane_state
;
1249 struct intel_plane
*plane
;
1250 unsigned fb_bits
= 0;
1253 intel_crtc_dpms_overlay_disable(crtc
);
1255 for_each_old_intel_plane_in_state(state
, plane
, old_plane_state
, i
) {
1256 if (crtc
->pipe
!= plane
->pipe
||
1257 !(update_mask
& BIT(plane
->id
)))
1260 intel_plane_disable_arm(plane
, new_crtc_state
);
1262 if (old_plane_state
->uapi
.visible
)
1263 fb_bits
|= plane
->frontbuffer_bit
;
1266 intel_frontbuffer_flip(dev_priv
, fb_bits
);
1269 static void intel_encoders_update_prepare(struct intel_atomic_state
*state
)
1271 struct drm_i915_private
*i915
= to_i915(state
->base
.dev
);
1272 struct intel_crtc_state
*new_crtc_state
, *old_crtc_state
;
1273 struct intel_crtc
*crtc
;
1277 * Make sure the DPLL state is up-to-date for fastset TypeC ports after non-blocking commits.
1278 * TODO: Update the DPLL state for all cases in the encoder->update_prepare() hook.
1280 if (i915
->display
.dpll
.mgr
) {
1281 for_each_oldnew_intel_crtc_in_state(state
, crtc
, old_crtc_state
, new_crtc_state
, i
) {
1282 if (intel_crtc_needs_modeset(new_crtc_state
))
1285 new_crtc_state
->shared_dpll
= old_crtc_state
->shared_dpll
;
1286 new_crtc_state
->dpll_hw_state
= old_crtc_state
->dpll_hw_state
;
1291 static void intel_encoders_pre_pll_enable(struct intel_atomic_state
*state
,
1292 struct intel_crtc
*crtc
)
1294 const struct intel_crtc_state
*crtc_state
=
1295 intel_atomic_get_new_crtc_state(state
, crtc
);
1296 const struct drm_connector_state
*conn_state
;
1297 struct drm_connector
*conn
;
1300 for_each_new_connector_in_state(&state
->base
, conn
, conn_state
, i
) {
1301 struct intel_encoder
*encoder
=
1302 to_intel_encoder(conn_state
->best_encoder
);
1304 if (conn_state
->crtc
!= &crtc
->base
)
1307 if (encoder
->pre_pll_enable
)
1308 encoder
->pre_pll_enable(state
, encoder
,
1309 crtc_state
, conn_state
);
1313 static void intel_encoders_pre_enable(struct intel_atomic_state
*state
,
1314 struct intel_crtc
*crtc
)
1316 const struct intel_crtc_state
*crtc_state
=
1317 intel_atomic_get_new_crtc_state(state
, crtc
);
1318 const struct drm_connector_state
*conn_state
;
1319 struct drm_connector
*conn
;
1322 for_each_new_connector_in_state(&state
->base
, conn
, conn_state
, i
) {
1323 struct intel_encoder
*encoder
=
1324 to_intel_encoder(conn_state
->best_encoder
);
1326 if (conn_state
->crtc
!= &crtc
->base
)
1329 if (encoder
->pre_enable
)
1330 encoder
->pre_enable(state
, encoder
,
1331 crtc_state
, conn_state
);
1335 static void intel_encoders_enable(struct intel_atomic_state
*state
,
1336 struct intel_crtc
*crtc
)
1338 const struct intel_crtc_state
*crtc_state
=
1339 intel_atomic_get_new_crtc_state(state
, crtc
);
1340 const struct drm_connector_state
*conn_state
;
1341 struct drm_connector
*conn
;
1344 for_each_new_connector_in_state(&state
->base
, conn
, conn_state
, i
) {
1345 struct intel_encoder
*encoder
=
1346 to_intel_encoder(conn_state
->best_encoder
);
1348 if (conn_state
->crtc
!= &crtc
->base
)
1351 if (encoder
->enable
)
1352 encoder
->enable(state
, encoder
,
1353 crtc_state
, conn_state
);
1354 intel_opregion_notify_encoder(encoder
, true);
1358 static void intel_encoders_disable(struct intel_atomic_state
*state
,
1359 struct intel_crtc
*crtc
)
1361 const struct intel_crtc_state
*old_crtc_state
=
1362 intel_atomic_get_old_crtc_state(state
, crtc
);
1363 const struct drm_connector_state
*old_conn_state
;
1364 struct drm_connector
*conn
;
1367 for_each_old_connector_in_state(&state
->base
, conn
, old_conn_state
, i
) {
1368 struct intel_encoder
*encoder
=
1369 to_intel_encoder(old_conn_state
->best_encoder
);
1371 if (old_conn_state
->crtc
!= &crtc
->base
)
1374 intel_opregion_notify_encoder(encoder
, false);
1375 if (encoder
->disable
)
1376 encoder
->disable(state
, encoder
,
1377 old_crtc_state
, old_conn_state
);
1381 static void intel_encoders_post_disable(struct intel_atomic_state
*state
,
1382 struct intel_crtc
*crtc
)
1384 const struct intel_crtc_state
*old_crtc_state
=
1385 intel_atomic_get_old_crtc_state(state
, crtc
);
1386 const struct drm_connector_state
*old_conn_state
;
1387 struct drm_connector
*conn
;
1390 for_each_old_connector_in_state(&state
->base
, conn
, old_conn_state
, i
) {
1391 struct intel_encoder
*encoder
=
1392 to_intel_encoder(old_conn_state
->best_encoder
);
1394 if (old_conn_state
->crtc
!= &crtc
->base
)
1397 if (encoder
->post_disable
)
1398 encoder
->post_disable(state
, encoder
,
1399 old_crtc_state
, old_conn_state
);
1403 static void intel_encoders_post_pll_disable(struct intel_atomic_state
*state
,
1404 struct intel_crtc
*crtc
)
1406 const struct intel_crtc_state
*old_crtc_state
=
1407 intel_atomic_get_old_crtc_state(state
, crtc
);
1408 const struct drm_connector_state
*old_conn_state
;
1409 struct drm_connector
*conn
;
1412 for_each_old_connector_in_state(&state
->base
, conn
, old_conn_state
, i
) {
1413 struct intel_encoder
*encoder
=
1414 to_intel_encoder(old_conn_state
->best_encoder
);
1416 if (old_conn_state
->crtc
!= &crtc
->base
)
1419 if (encoder
->post_pll_disable
)
1420 encoder
->post_pll_disable(state
, encoder
,
1421 old_crtc_state
, old_conn_state
);
1425 static void intel_encoders_update_pipe(struct intel_atomic_state
*state
,
1426 struct intel_crtc
*crtc
)
1428 const struct intel_crtc_state
*crtc_state
=
1429 intel_atomic_get_new_crtc_state(state
, crtc
);
1430 const struct drm_connector_state
*conn_state
;
1431 struct drm_connector
*conn
;
1434 for_each_new_connector_in_state(&state
->base
, conn
, conn_state
, i
) {
1435 struct intel_encoder
*encoder
=
1436 to_intel_encoder(conn_state
->best_encoder
);
1438 if (conn_state
->crtc
!= &crtc
->base
)
1441 if (encoder
->update_pipe
)
1442 encoder
->update_pipe(state
, encoder
,
1443 crtc_state
, conn_state
);
1447 static void intel_disable_primary_plane(const struct intel_crtc_state
*crtc_state
)
1449 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
1450 struct intel_plane
*plane
= to_intel_plane(crtc
->base
.primary
);
1452 plane
->disable_arm(plane
, crtc_state
);
1455 static void ilk_configure_cpu_transcoder(const struct intel_crtc_state
*crtc_state
)
1457 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
1458 enum transcoder cpu_transcoder
= crtc_state
->cpu_transcoder
;
1460 if (crtc_state
->has_pch_encoder
) {
1461 intel_cpu_transcoder_set_m1_n1(crtc
, cpu_transcoder
,
1462 &crtc_state
->fdi_m_n
);
1463 } else if (intel_crtc_has_dp_encoder(crtc_state
)) {
1464 intel_cpu_transcoder_set_m1_n1(crtc
, cpu_transcoder
,
1465 &crtc_state
->dp_m_n
);
1466 intel_cpu_transcoder_set_m2_n2(crtc
, cpu_transcoder
,
1467 &crtc_state
->dp_m2_n2
);
1470 intel_set_transcoder_timings(crtc_state
);
1472 ilk_set_pipeconf(crtc_state
);
1475 static void ilk_crtc_enable(struct intel_atomic_state
*state
,
1476 struct intel_crtc
*crtc
)
1478 const struct intel_crtc_state
*new_crtc_state
=
1479 intel_atomic_get_new_crtc_state(state
, crtc
);
1480 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1481 enum pipe pipe
= crtc
->pipe
;
1483 if (drm_WARN_ON(&dev_priv
->drm
, crtc
->active
))
1487 * Sometimes spurious CPU pipe underruns happen during FDI
1488 * training, at least with VGA+HDMI cloning. Suppress them.
1490 * On ILK we get an occasional spurious CPU pipe underruns
1491 * between eDP port A enable and vdd enable. Also PCH port
1492 * enable seems to result in the occasional CPU pipe underrun.
1494 * Spurious PCH underruns also occur during PCH enabling.
1496 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
1497 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, false);
1499 ilk_configure_cpu_transcoder(new_crtc_state
);
1501 intel_set_pipe_src_size(new_crtc_state
);
1503 crtc
->active
= true;
1505 intel_encoders_pre_enable(state
, crtc
);
1507 if (new_crtc_state
->has_pch_encoder
) {
1508 ilk_pch_pre_enable(state
, crtc
);
1510 assert_fdi_tx_disabled(dev_priv
, pipe
);
1511 assert_fdi_rx_disabled(dev_priv
, pipe
);
1514 ilk_pfit_enable(new_crtc_state
);
1517 * On ILK+ LUT must be loaded before the pipe is running but with
1520 intel_color_load_luts(new_crtc_state
);
1521 intel_color_commit_noarm(new_crtc_state
);
1522 intel_color_commit_arm(new_crtc_state
);
1523 /* update DSPCNTR to configure gamma for pipe bottom color */
1524 intel_disable_primary_plane(new_crtc_state
);
1526 intel_initial_watermarks(state
, crtc
);
1527 intel_enable_transcoder(new_crtc_state
);
1529 if (new_crtc_state
->has_pch_encoder
)
1530 ilk_pch_enable(state
, crtc
);
1532 intel_crtc_vblank_on(new_crtc_state
);
1534 intel_encoders_enable(state
, crtc
);
1536 if (HAS_PCH_CPT(dev_priv
))
1537 intel_wait_for_pipe_scanline_moving(crtc
);
1540 * Must wait for vblank to avoid spurious PCH FIFO underruns.
1541 * And a second vblank wait is needed at least on ILK with
1542 * some interlaced HDMI modes. Let's do the double wait always
1543 * in case there are more corner cases we don't know about.
1545 if (new_crtc_state
->has_pch_encoder
) {
1546 intel_crtc_wait_for_next_vblank(crtc
);
1547 intel_crtc_wait_for_next_vblank(crtc
);
1549 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
1550 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, true);
1553 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private
*dev_priv
,
1554 enum pipe pipe
, bool apply
)
1556 u32 val
= intel_de_read(dev_priv
, CLKGATE_DIS_PSL(pipe
));
1557 u32 mask
= DPF_GATING_DIS
| DPF_RAM_GATING_DIS
| DPFR_GATING_DIS
;
1564 intel_de_write(dev_priv
, CLKGATE_DIS_PSL(pipe
), val
);
1567 static void hsw_set_linetime_wm(const struct intel_crtc_state
*crtc_state
)
1569 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
1570 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1572 intel_de_write(dev_priv
, WM_LINETIME(crtc
->pipe
),
1573 HSW_LINETIME(crtc_state
->linetime
) |
1574 HSW_IPS_LINETIME(crtc_state
->ips_linetime
));
1577 static void hsw_set_frame_start_delay(const struct intel_crtc_state
*crtc_state
)
1579 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
1580 struct drm_i915_private
*i915
= to_i915(crtc
->base
.dev
);
1582 intel_de_rmw(i915
, hsw_chicken_trans_reg(i915
, crtc_state
->cpu_transcoder
),
1583 HSW_FRAME_START_DELAY_MASK
,
1584 HSW_FRAME_START_DELAY(crtc_state
->framestart_delay
- 1));
1587 static void icl_ddi_bigjoiner_pre_enable(struct intel_atomic_state
*state
,
1588 const struct intel_crtc_state
*crtc_state
)
1590 struct intel_crtc
*master_crtc
= intel_master_crtc(crtc_state
);
1593 * Enable sequence steps 1-7 on bigjoiner master
1595 if (intel_crtc_is_bigjoiner_slave(crtc_state
))
1596 intel_encoders_pre_pll_enable(state
, master_crtc
);
1598 if (crtc_state
->shared_dpll
)
1599 intel_enable_shared_dpll(crtc_state
);
1601 if (intel_crtc_is_bigjoiner_slave(crtc_state
))
1602 intel_encoders_pre_enable(state
, master_crtc
);
1605 static void hsw_configure_cpu_transcoder(const struct intel_crtc_state
*crtc_state
)
1607 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
1608 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1609 enum transcoder cpu_transcoder
= crtc_state
->cpu_transcoder
;
1611 if (crtc_state
->has_pch_encoder
) {
1612 intel_cpu_transcoder_set_m1_n1(crtc
, cpu_transcoder
,
1613 &crtc_state
->fdi_m_n
);
1614 } else if (intel_crtc_has_dp_encoder(crtc_state
)) {
1615 intel_cpu_transcoder_set_m1_n1(crtc
, cpu_transcoder
,
1616 &crtc_state
->dp_m_n
);
1617 intel_cpu_transcoder_set_m2_n2(crtc
, cpu_transcoder
,
1618 &crtc_state
->dp_m2_n2
);
1621 intel_set_transcoder_timings(crtc_state
);
1622 if (HAS_VRR(dev_priv
))
1623 intel_vrr_set_transcoder_timings(crtc_state
);
1625 if (cpu_transcoder
!= TRANSCODER_EDP
)
1626 intel_de_write(dev_priv
, TRANS_MULT(cpu_transcoder
),
1627 crtc_state
->pixel_multiplier
- 1);
1629 hsw_set_frame_start_delay(crtc_state
);
1631 hsw_set_transconf(crtc_state
);
1634 static void hsw_crtc_enable(struct intel_atomic_state
*state
,
1635 struct intel_crtc
*crtc
)
1637 const struct intel_crtc_state
*new_crtc_state
=
1638 intel_atomic_get_new_crtc_state(state
, crtc
);
1639 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1640 enum pipe pipe
= crtc
->pipe
, hsw_workaround_pipe
;
1641 enum transcoder cpu_transcoder
= new_crtc_state
->cpu_transcoder
;
1642 bool psl_clkgate_wa
;
1644 if (drm_WARN_ON(&dev_priv
->drm
, crtc
->active
))
1647 intel_dmc_enable_pipe(dev_priv
, crtc
->pipe
);
1649 if (!new_crtc_state
->bigjoiner_pipes
) {
1650 intel_encoders_pre_pll_enable(state
, crtc
);
1652 if (new_crtc_state
->shared_dpll
)
1653 intel_enable_shared_dpll(new_crtc_state
);
1655 intel_encoders_pre_enable(state
, crtc
);
1657 icl_ddi_bigjoiner_pre_enable(state
, new_crtc_state
);
1660 intel_dsc_enable(new_crtc_state
);
1662 if (DISPLAY_VER(dev_priv
) >= 13)
1663 intel_uncompressed_joiner_enable(new_crtc_state
);
1665 intel_set_pipe_src_size(new_crtc_state
);
1666 if (DISPLAY_VER(dev_priv
) >= 9 || IS_BROADWELL(dev_priv
))
1667 bdw_set_pipe_misc(new_crtc_state
);
1669 if (!intel_crtc_is_bigjoiner_slave(new_crtc_state
) &&
1670 !transcoder_is_dsi(cpu_transcoder
))
1671 hsw_configure_cpu_transcoder(new_crtc_state
);
1673 crtc
->active
= true;
1675 /* Display WA #1180: WaDisableScalarClockGating: glk */
1676 psl_clkgate_wa
= DISPLAY_VER(dev_priv
) == 10 &&
1677 new_crtc_state
->pch_pfit
.enabled
;
1679 glk_pipe_scaler_clock_gating_wa(dev_priv
, pipe
, true);
1681 if (DISPLAY_VER(dev_priv
) >= 9)
1682 skl_pfit_enable(new_crtc_state
);
1684 ilk_pfit_enable(new_crtc_state
);
1687 * On ILK+ LUT must be loaded before the pipe is running but with
1690 intel_color_load_luts(new_crtc_state
);
1691 intel_color_commit_noarm(new_crtc_state
);
1692 intel_color_commit_arm(new_crtc_state
);
1693 /* update DSPCNTR to configure gamma/csc for pipe bottom color */
1694 if (DISPLAY_VER(dev_priv
) < 9)
1695 intel_disable_primary_plane(new_crtc_state
);
1697 hsw_set_linetime_wm(new_crtc_state
);
1699 if (DISPLAY_VER(dev_priv
) >= 11)
1700 icl_set_pipe_chicken(new_crtc_state
);
1702 intel_initial_watermarks(state
, crtc
);
1704 if (intel_crtc_is_bigjoiner_slave(new_crtc_state
))
1705 intel_crtc_vblank_on(new_crtc_state
);
1707 intel_encoders_enable(state
, crtc
);
1709 if (psl_clkgate_wa
) {
1710 intel_crtc_wait_for_next_vblank(crtc
);
1711 glk_pipe_scaler_clock_gating_wa(dev_priv
, pipe
, false);
1714 /* If we change the relative order between pipe/planes enabling, we need
1715 * to change the workaround. */
1716 hsw_workaround_pipe
= new_crtc_state
->hsw_workaround_pipe
;
1717 if (IS_HASWELL(dev_priv
) && hsw_workaround_pipe
!= INVALID_PIPE
) {
1718 struct intel_crtc
*wa_crtc
;
1720 wa_crtc
= intel_crtc_for_pipe(dev_priv
, hsw_workaround_pipe
);
1722 intel_crtc_wait_for_next_vblank(wa_crtc
);
1723 intel_crtc_wait_for_next_vblank(wa_crtc
);
1727 void ilk_pfit_disable(const struct intel_crtc_state
*old_crtc_state
)
1729 struct intel_crtc
*crtc
= to_intel_crtc(old_crtc_state
->uapi
.crtc
);
1730 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1731 enum pipe pipe
= crtc
->pipe
;
1733 /* To avoid upsetting the power well on haswell only disable the pfit if
1734 * it's in use. The hw state code will make sure we get this right. */
1735 if (!old_crtc_state
->pch_pfit
.enabled
)
1738 intel_de_write_fw(dev_priv
, PF_CTL(pipe
), 0);
1739 intel_de_write_fw(dev_priv
, PF_WIN_POS(pipe
), 0);
1740 intel_de_write_fw(dev_priv
, PF_WIN_SZ(pipe
), 0);
1743 static void ilk_crtc_disable(struct intel_atomic_state
*state
,
1744 struct intel_crtc
*crtc
)
1746 const struct intel_crtc_state
*old_crtc_state
=
1747 intel_atomic_get_old_crtc_state(state
, crtc
);
1748 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1749 enum pipe pipe
= crtc
->pipe
;
1752 * Sometimes spurious CPU pipe underruns happen when the
1753 * pipe is already disabled, but FDI RX/TX is still enabled.
1754 * Happens at least with VGA+HDMI cloning. Suppress them.
1756 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
1757 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, false);
1759 intel_encoders_disable(state
, crtc
);
1761 intel_crtc_vblank_off(old_crtc_state
);
1763 intel_disable_transcoder(old_crtc_state
);
1765 ilk_pfit_disable(old_crtc_state
);
1767 if (old_crtc_state
->has_pch_encoder
)
1768 ilk_pch_disable(state
, crtc
);
1770 intel_encoders_post_disable(state
, crtc
);
1772 if (old_crtc_state
->has_pch_encoder
)
1773 ilk_pch_post_disable(state
, crtc
);
1775 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
1776 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, true);
1778 intel_disable_shared_dpll(old_crtc_state
);
1781 static void hsw_crtc_disable(struct intel_atomic_state
*state
,
1782 struct intel_crtc
*crtc
)
1784 const struct intel_crtc_state
*old_crtc_state
=
1785 intel_atomic_get_old_crtc_state(state
, crtc
);
1786 struct drm_i915_private
*i915
= to_i915(crtc
->base
.dev
);
1789 * FIXME collapse everything to one hook.
1790 * Need care with mst->ddi interactions.
1792 if (!intel_crtc_is_bigjoiner_slave(old_crtc_state
)) {
1793 intel_encoders_disable(state
, crtc
);
1794 intel_encoders_post_disable(state
, crtc
);
1797 intel_disable_shared_dpll(old_crtc_state
);
1799 if (!intel_crtc_is_bigjoiner_slave(old_crtc_state
)) {
1800 struct intel_crtc
*slave_crtc
;
1802 intel_encoders_post_pll_disable(state
, crtc
);
1804 intel_dmc_disable_pipe(i915
, crtc
->pipe
);
1806 for_each_intel_crtc_in_pipe_mask(&i915
->drm
, slave_crtc
,
1807 intel_crtc_bigjoiner_slave_pipes(old_crtc_state
))
1808 intel_dmc_disable_pipe(i915
, slave_crtc
->pipe
);
1812 static void i9xx_pfit_enable(const struct intel_crtc_state
*crtc_state
)
1814 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
1815 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1817 if (!crtc_state
->gmch_pfit
.control
)
1821 * The panel fitter should only be adjusted whilst the pipe is disabled,
1822 * according to register description and PRM.
1824 drm_WARN_ON(&dev_priv
->drm
,
1825 intel_de_read(dev_priv
, PFIT_CONTROL
) & PFIT_ENABLE
);
1826 assert_transcoder_disabled(dev_priv
, crtc_state
->cpu_transcoder
);
1828 intel_de_write(dev_priv
, PFIT_PGM_RATIOS
,
1829 crtc_state
->gmch_pfit
.pgm_ratios
);
1830 intel_de_write(dev_priv
, PFIT_CONTROL
, crtc_state
->gmch_pfit
.control
);
1832 /* Border color in case we don't scale up to the full screen. Black by
1833 * default, change to something else for debugging. */
1834 intel_de_write(dev_priv
, BCLRPAT(crtc
->pipe
), 0);
1837 bool intel_phy_is_combo(struct drm_i915_private
*dev_priv
, enum phy phy
)
1839 if (phy
== PHY_NONE
)
1841 else if (IS_ALDERLAKE_S(dev_priv
))
1842 return phy
<= PHY_E
;
1843 else if (IS_DG1(dev_priv
) || IS_ROCKETLAKE(dev_priv
))
1844 return phy
<= PHY_D
;
1845 else if (IS_JASPERLAKE(dev_priv
) || IS_ELKHARTLAKE(dev_priv
))
1846 return phy
<= PHY_C
;
1847 else if (IS_ALDERLAKE_P(dev_priv
) || IS_DISPLAY_VER(dev_priv
, 11, 12))
1848 return phy
<= PHY_B
;
1851 * DG2 outputs labelled as "combo PHY" in the bspec use
1852 * SNPS PHYs with completely different programming,
1853 * hence we always return false here.
1858 bool intel_phy_is_tc(struct drm_i915_private
*dev_priv
, enum phy phy
)
1861 * DG2's "TC1", although TC-capable output, doesn't share the same flow
1862 * as other platforms on the display engine side and rather rely on the
1863 * SNPS PHY, that is programmed separately
1865 if (IS_DG2(dev_priv
))
1868 if (DISPLAY_VER(dev_priv
) >= 13)
1869 return phy
>= PHY_F
&& phy
<= PHY_I
;
1870 else if (IS_TIGERLAKE(dev_priv
))
1871 return phy
>= PHY_D
&& phy
<= PHY_I
;
1872 else if (IS_ICELAKE(dev_priv
))
1873 return phy
>= PHY_C
&& phy
<= PHY_F
;
1878 bool intel_phy_is_snps(struct drm_i915_private
*dev_priv
, enum phy phy
)
1881 * For DG2, and for DG2 only, all four "combo" ports and the TC1 port
1882 * (PHY E) use Synopsis PHYs. See intel_phy_is_tc().
1884 return IS_DG2(dev_priv
) && phy
> PHY_NONE
&& phy
<= PHY_E
;
1887 enum phy
intel_port_to_phy(struct drm_i915_private
*i915
, enum port port
)
1889 if (DISPLAY_VER(i915
) >= 13 && port
>= PORT_D_XELPD
)
1890 return PHY_D
+ port
- PORT_D_XELPD
;
1891 else if (DISPLAY_VER(i915
) >= 13 && port
>= PORT_TC1
)
1892 return PHY_F
+ port
- PORT_TC1
;
1893 else if (IS_ALDERLAKE_S(i915
) && port
>= PORT_TC1
)
1894 return PHY_B
+ port
- PORT_TC1
;
1895 else if ((IS_DG1(i915
) || IS_ROCKETLAKE(i915
)) && port
>= PORT_TC1
)
1896 return PHY_C
+ port
- PORT_TC1
;
1897 else if ((IS_JASPERLAKE(i915
) || IS_ELKHARTLAKE(i915
)) &&
1901 return PHY_A
+ port
- PORT_A
;
1904 enum tc_port
intel_port_to_tc(struct drm_i915_private
*dev_priv
, enum port port
)
1906 if (!intel_phy_is_tc(dev_priv
, intel_port_to_phy(dev_priv
, port
)))
1907 return TC_PORT_NONE
;
1909 if (DISPLAY_VER(dev_priv
) >= 12)
1910 return TC_PORT_1
+ port
- PORT_TC1
;
1912 return TC_PORT_1
+ port
- PORT_C
;
1915 enum intel_display_power_domain
1916 intel_aux_power_domain(struct intel_digital_port
*dig_port
)
1918 struct drm_i915_private
*i915
= to_i915(dig_port
->base
.base
.dev
);
1920 if (intel_tc_port_in_tbt_alt_mode(dig_port
))
1921 return intel_display_power_tbt_aux_domain(i915
, dig_port
->aux_ch
);
1923 return intel_display_power_legacy_aux_domain(i915
, dig_port
->aux_ch
);
1926 static void get_crtc_power_domains(struct intel_crtc_state
*crtc_state
,
1927 struct intel_power_domain_mask
*mask
)
1929 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
1930 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1931 enum transcoder cpu_transcoder
= crtc_state
->cpu_transcoder
;
1932 struct drm_encoder
*encoder
;
1933 enum pipe pipe
= crtc
->pipe
;
1935 bitmap_zero(mask
->bits
, POWER_DOMAIN_NUM
);
1937 if (!crtc_state
->hw
.active
)
1940 set_bit(POWER_DOMAIN_PIPE(pipe
), mask
->bits
);
1941 set_bit(POWER_DOMAIN_TRANSCODER(cpu_transcoder
), mask
->bits
);
1942 if (crtc_state
->pch_pfit
.enabled
||
1943 crtc_state
->pch_pfit
.force_thru
)
1944 set_bit(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe
), mask
->bits
);
1946 drm_for_each_encoder_mask(encoder
, &dev_priv
->drm
,
1947 crtc_state
->uapi
.encoder_mask
) {
1948 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
1950 set_bit(intel_encoder
->power_domain
, mask
->bits
);
1953 if (HAS_DDI(dev_priv
) && crtc_state
->has_audio
)
1954 set_bit(POWER_DOMAIN_AUDIO_MMIO
, mask
->bits
);
1956 if (crtc_state
->shared_dpll
)
1957 set_bit(POWER_DOMAIN_DISPLAY_CORE
, mask
->bits
);
1959 if (crtc_state
->dsc
.compression_enable
)
1960 set_bit(intel_dsc_power_domain(crtc
, cpu_transcoder
), mask
->bits
);
1963 void intel_modeset_get_crtc_power_domains(struct intel_crtc_state
*crtc_state
,
1964 struct intel_power_domain_mask
*old_domains
)
1966 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
1967 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1968 enum intel_display_power_domain domain
;
1969 struct intel_power_domain_mask domains
, new_domains
;
1971 get_crtc_power_domains(crtc_state
, &domains
);
1973 bitmap_andnot(new_domains
.bits
,
1975 crtc
->enabled_power_domains
.mask
.bits
,
1977 bitmap_andnot(old_domains
->bits
,
1978 crtc
->enabled_power_domains
.mask
.bits
,
1982 for_each_power_domain(domain
, &new_domains
)
1983 intel_display_power_get_in_set(dev_priv
,
1984 &crtc
->enabled_power_domains
,
1988 void intel_modeset_put_crtc_power_domains(struct intel_crtc
*crtc
,
1989 struct intel_power_domain_mask
*domains
)
1991 intel_display_power_put_mask_in_set(to_i915(crtc
->base
.dev
),
1992 &crtc
->enabled_power_domains
,
1996 static void i9xx_configure_cpu_transcoder(const struct intel_crtc_state
*crtc_state
)
1998 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
1999 enum transcoder cpu_transcoder
= crtc_state
->cpu_transcoder
;
2001 if (intel_crtc_has_dp_encoder(crtc_state
)) {
2002 intel_cpu_transcoder_set_m1_n1(crtc
, cpu_transcoder
,
2003 &crtc_state
->dp_m_n
);
2004 intel_cpu_transcoder_set_m2_n2(crtc
, cpu_transcoder
,
2005 &crtc_state
->dp_m2_n2
);
2008 intel_set_transcoder_timings(crtc_state
);
2010 i9xx_set_pipeconf(crtc_state
);
2013 static void valleyview_crtc_enable(struct intel_atomic_state
*state
,
2014 struct intel_crtc
*crtc
)
2016 const struct intel_crtc_state
*new_crtc_state
=
2017 intel_atomic_get_new_crtc_state(state
, crtc
);
2018 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2019 enum pipe pipe
= crtc
->pipe
;
2021 if (drm_WARN_ON(&dev_priv
->drm
, crtc
->active
))
2024 i9xx_configure_cpu_transcoder(new_crtc_state
);
2026 intel_set_pipe_src_size(new_crtc_state
);
2028 intel_de_write(dev_priv
, VLV_PIPE_MSA_MISC(pipe
), 0);
2030 if (IS_CHERRYVIEW(dev_priv
) && pipe
== PIPE_B
) {
2031 intel_de_write(dev_priv
, CHV_BLEND(pipe
), CHV_BLEND_LEGACY
);
2032 intel_de_write(dev_priv
, CHV_CANVAS(pipe
), 0);
2035 crtc
->active
= true;
2037 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
2039 intel_encoders_pre_pll_enable(state
, crtc
);
2041 if (IS_CHERRYVIEW(dev_priv
))
2042 chv_enable_pll(new_crtc_state
);
2044 vlv_enable_pll(new_crtc_state
);
2046 intel_encoders_pre_enable(state
, crtc
);
2048 i9xx_pfit_enable(new_crtc_state
);
2050 intel_color_load_luts(new_crtc_state
);
2051 intel_color_commit_noarm(new_crtc_state
);
2052 intel_color_commit_arm(new_crtc_state
);
2053 /* update DSPCNTR to configure gamma for pipe bottom color */
2054 intel_disable_primary_plane(new_crtc_state
);
2056 intel_initial_watermarks(state
, crtc
);
2057 intel_enable_transcoder(new_crtc_state
);
2059 intel_crtc_vblank_on(new_crtc_state
);
2061 intel_encoders_enable(state
, crtc
);
2064 static void i9xx_crtc_enable(struct intel_atomic_state
*state
,
2065 struct intel_crtc
*crtc
)
2067 const struct intel_crtc_state
*new_crtc_state
=
2068 intel_atomic_get_new_crtc_state(state
, crtc
);
2069 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2070 enum pipe pipe
= crtc
->pipe
;
2072 if (drm_WARN_ON(&dev_priv
->drm
, crtc
->active
))
2075 i9xx_configure_cpu_transcoder(new_crtc_state
);
2077 intel_set_pipe_src_size(new_crtc_state
);
2079 crtc
->active
= true;
2081 if (DISPLAY_VER(dev_priv
) != 2)
2082 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
2084 intel_encoders_pre_enable(state
, crtc
);
2086 i9xx_enable_pll(new_crtc_state
);
2088 i9xx_pfit_enable(new_crtc_state
);
2090 intel_color_load_luts(new_crtc_state
);
2091 intel_color_commit_noarm(new_crtc_state
);
2092 intel_color_commit_arm(new_crtc_state
);
2093 /* update DSPCNTR to configure gamma for pipe bottom color */
2094 intel_disable_primary_plane(new_crtc_state
);
2096 if (!intel_initial_watermarks(state
, crtc
))
2097 intel_update_watermarks(dev_priv
);
2098 intel_enable_transcoder(new_crtc_state
);
2100 intel_crtc_vblank_on(new_crtc_state
);
2102 intel_encoders_enable(state
, crtc
);
2104 /* prevents spurious underruns */
2105 if (DISPLAY_VER(dev_priv
) == 2)
2106 intel_crtc_wait_for_next_vblank(crtc
);
2109 static void i9xx_pfit_disable(const struct intel_crtc_state
*old_crtc_state
)
2111 struct intel_crtc
*crtc
= to_intel_crtc(old_crtc_state
->uapi
.crtc
);
2112 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2114 if (!old_crtc_state
->gmch_pfit
.control
)
2117 assert_transcoder_disabled(dev_priv
, old_crtc_state
->cpu_transcoder
);
2119 drm_dbg_kms(&dev_priv
->drm
, "disabling pfit, current: 0x%08x\n",
2120 intel_de_read(dev_priv
, PFIT_CONTROL
));
2121 intel_de_write(dev_priv
, PFIT_CONTROL
, 0);
2124 static void i9xx_crtc_disable(struct intel_atomic_state
*state
,
2125 struct intel_crtc
*crtc
)
2127 struct intel_crtc_state
*old_crtc_state
=
2128 intel_atomic_get_old_crtc_state(state
, crtc
);
2129 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2130 enum pipe pipe
= crtc
->pipe
;
2133 * On gen2 planes are double buffered but the pipe isn't, so we must
2134 * wait for planes to fully turn off before disabling the pipe.
2136 if (DISPLAY_VER(dev_priv
) == 2)
2137 intel_crtc_wait_for_next_vblank(crtc
);
2139 intel_encoders_disable(state
, crtc
);
2141 intel_crtc_vblank_off(old_crtc_state
);
2143 intel_disable_transcoder(old_crtc_state
);
2145 i9xx_pfit_disable(old_crtc_state
);
2147 intel_encoders_post_disable(state
, crtc
);
2149 if (!intel_crtc_has_type(old_crtc_state
, INTEL_OUTPUT_DSI
)) {
2150 if (IS_CHERRYVIEW(dev_priv
))
2151 chv_disable_pll(dev_priv
, pipe
);
2152 else if (IS_VALLEYVIEW(dev_priv
))
2153 vlv_disable_pll(dev_priv
, pipe
);
2155 i9xx_disable_pll(old_crtc_state
);
2158 intel_encoders_post_pll_disable(state
, crtc
);
2160 if (DISPLAY_VER(dev_priv
) != 2)
2161 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
2163 if (!dev_priv
->display
.funcs
.wm
->initial_watermarks
)
2164 intel_update_watermarks(dev_priv
);
2166 /* clock the pipe down to 640x480@60 to potentially save power */
2167 if (IS_I830(dev_priv
))
2168 i830_enable_pipe(dev_priv
, pipe
);
2171 void intel_encoder_destroy(struct drm_encoder
*encoder
)
2173 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
2175 drm_encoder_cleanup(encoder
);
2176 kfree(intel_encoder
);
2179 static bool intel_crtc_supports_double_wide(const struct intel_crtc
*crtc
)
2181 const struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2183 /* GDG double wide on either pipe, otherwise pipe A only */
2184 return DISPLAY_VER(dev_priv
) < 4 &&
2185 (crtc
->pipe
== PIPE_A
|| IS_I915G(dev_priv
));
2188 static u32
ilk_pipe_pixel_rate(const struct intel_crtc_state
*crtc_state
)
2190 u32 pixel_rate
= crtc_state
->hw
.pipe_mode
.crtc_clock
;
2191 struct drm_rect src
;
2194 * We only use IF-ID interlacing. If we ever use
2195 * PF-ID we'll need to adjust the pixel_rate here.
2198 if (!crtc_state
->pch_pfit
.enabled
)
2201 drm_rect_init(&src
, 0, 0,
2202 drm_rect_width(&crtc_state
->pipe_src
) << 16,
2203 drm_rect_height(&crtc_state
->pipe_src
) << 16);
2205 return intel_adjusted_rate(&src
, &crtc_state
->pch_pfit
.dst
,
2209 static void intel_mode_from_crtc_timings(struct drm_display_mode
*mode
,
2210 const struct drm_display_mode
*timings
)
2212 mode
->hdisplay
= timings
->crtc_hdisplay
;
2213 mode
->htotal
= timings
->crtc_htotal
;
2214 mode
->hsync_start
= timings
->crtc_hsync_start
;
2215 mode
->hsync_end
= timings
->crtc_hsync_end
;
2217 mode
->vdisplay
= timings
->crtc_vdisplay
;
2218 mode
->vtotal
= timings
->crtc_vtotal
;
2219 mode
->vsync_start
= timings
->crtc_vsync_start
;
2220 mode
->vsync_end
= timings
->crtc_vsync_end
;
2222 mode
->flags
= timings
->flags
;
2223 mode
->type
= DRM_MODE_TYPE_DRIVER
;
2225 mode
->clock
= timings
->crtc_clock
;
2227 drm_mode_set_name(mode
);
2230 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state
*crtc_state
)
2232 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->uapi
.crtc
->dev
);
2234 if (HAS_GMCH(dev_priv
))
2235 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
2236 crtc_state
->pixel_rate
=
2237 crtc_state
->hw
.pipe_mode
.crtc_clock
;
2239 crtc_state
->pixel_rate
=
2240 ilk_pipe_pixel_rate(crtc_state
);
2243 static void intel_bigjoiner_adjust_timings(const struct intel_crtc_state
*crtc_state
,
2244 struct drm_display_mode
*mode
)
2246 int num_pipes
= intel_bigjoiner_num_pipes(crtc_state
);
2251 mode
->crtc_clock
/= num_pipes
;
2252 mode
->crtc_hdisplay
/= num_pipes
;
2253 mode
->crtc_hblank_start
/= num_pipes
;
2254 mode
->crtc_hblank_end
/= num_pipes
;
2255 mode
->crtc_hsync_start
/= num_pipes
;
2256 mode
->crtc_hsync_end
/= num_pipes
;
2257 mode
->crtc_htotal
/= num_pipes
;
2260 static void intel_splitter_adjust_timings(const struct intel_crtc_state
*crtc_state
,
2261 struct drm_display_mode
*mode
)
2263 int overlap
= crtc_state
->splitter
.pixel_overlap
;
2264 int n
= crtc_state
->splitter
.link_count
;
2266 if (!crtc_state
->splitter
.enable
)
2270 * eDP MSO uses segment timings from EDID for transcoder
2271 * timings, but full mode for everything else.
2273 * h_full = (h_segment - pixel_overlap) * link_count
2275 mode
->crtc_hdisplay
= (mode
->crtc_hdisplay
- overlap
) * n
;
2276 mode
->crtc_hblank_start
= (mode
->crtc_hblank_start
- overlap
) * n
;
2277 mode
->crtc_hblank_end
= (mode
->crtc_hblank_end
- overlap
) * n
;
2278 mode
->crtc_hsync_start
= (mode
->crtc_hsync_start
- overlap
) * n
;
2279 mode
->crtc_hsync_end
= (mode
->crtc_hsync_end
- overlap
) * n
;
2280 mode
->crtc_htotal
= (mode
->crtc_htotal
- overlap
) * n
;
2281 mode
->crtc_clock
*= n
;
2284 static void intel_crtc_readout_derived_state(struct intel_crtc_state
*crtc_state
)
2286 struct drm_display_mode
*mode
= &crtc_state
->hw
.mode
;
2287 struct drm_display_mode
*pipe_mode
= &crtc_state
->hw
.pipe_mode
;
2288 struct drm_display_mode
*adjusted_mode
= &crtc_state
->hw
.adjusted_mode
;
2291 * Start with the adjusted_mode crtc timings, which
2292 * have been filled with the transcoder timings.
2294 drm_mode_copy(pipe_mode
, adjusted_mode
);
2296 /* Expand MSO per-segment transcoder timings to full */
2297 intel_splitter_adjust_timings(crtc_state
, pipe_mode
);
2300 * We want the full numbers in adjusted_mode normal timings,
2301 * adjusted_mode crtc timings are left with the raw transcoder
2304 intel_mode_from_crtc_timings(adjusted_mode
, pipe_mode
);
2306 /* Populate the "user" mode with full numbers */
2307 drm_mode_copy(mode
, pipe_mode
);
2308 intel_mode_from_crtc_timings(mode
, mode
);
2309 mode
->hdisplay
= drm_rect_width(&crtc_state
->pipe_src
) *
2310 (intel_bigjoiner_num_pipes(crtc_state
) ?: 1);
2311 mode
->vdisplay
= drm_rect_height(&crtc_state
->pipe_src
);
2313 /* Derive per-pipe timings in case bigjoiner is used */
2314 intel_bigjoiner_adjust_timings(crtc_state
, pipe_mode
);
2315 intel_mode_from_crtc_timings(pipe_mode
, pipe_mode
);
2317 intel_crtc_compute_pixel_rate(crtc_state
);
2320 void intel_encoder_get_config(struct intel_encoder
*encoder
,
2321 struct intel_crtc_state
*crtc_state
)
2323 encoder
->get_config(encoder
, crtc_state
);
2325 intel_crtc_readout_derived_state(crtc_state
);
2328 static void intel_bigjoiner_compute_pipe_src(struct intel_crtc_state
*crtc_state
)
2330 int num_pipes
= intel_bigjoiner_num_pipes(crtc_state
);
2336 width
= drm_rect_width(&crtc_state
->pipe_src
);
2337 height
= drm_rect_height(&crtc_state
->pipe_src
);
2339 drm_rect_init(&crtc_state
->pipe_src
, 0, 0,
2340 width
/ num_pipes
, height
);
2343 static int intel_crtc_compute_pipe_src(struct intel_crtc_state
*crtc_state
)
2345 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
2346 struct drm_i915_private
*i915
= to_i915(crtc
->base
.dev
);
2348 intel_bigjoiner_compute_pipe_src(crtc_state
);
2351 * Pipe horizontal size must be even in:
2353 * - LVDS dual channel mode
2354 * - Double wide pipe
2356 if (drm_rect_width(&crtc_state
->pipe_src
) & 1) {
2357 if (crtc_state
->double_wide
) {
2358 drm_dbg_kms(&i915
->drm
,
2359 "[CRTC:%d:%s] Odd pipe source width not supported with double wide pipe\n",
2360 crtc
->base
.base
.id
, crtc
->base
.name
);
2364 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
2365 intel_is_dual_link_lvds(i915
)) {
2366 drm_dbg_kms(&i915
->drm
,
2367 "[CRTC:%d:%s] Odd pipe source width not supported with dual link LVDS\n",
2368 crtc
->base
.base
.id
, crtc
->base
.name
);
2376 static int intel_crtc_compute_pipe_mode(struct intel_crtc_state
*crtc_state
)
2378 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
2379 struct drm_i915_private
*i915
= to_i915(crtc
->base
.dev
);
2380 struct drm_display_mode
*adjusted_mode
= &crtc_state
->hw
.adjusted_mode
;
2381 struct drm_display_mode
*pipe_mode
= &crtc_state
->hw
.pipe_mode
;
2382 int clock_limit
= i915
->max_dotclk_freq
;
2385 * Start with the adjusted_mode crtc timings, which
2386 * have been filled with the transcoder timings.
2388 drm_mode_copy(pipe_mode
, adjusted_mode
);
2390 /* Expand MSO per-segment transcoder timings to full */
2391 intel_splitter_adjust_timings(crtc_state
, pipe_mode
);
2393 /* Derive per-pipe timings in case bigjoiner is used */
2394 intel_bigjoiner_adjust_timings(crtc_state
, pipe_mode
);
2395 intel_mode_from_crtc_timings(pipe_mode
, pipe_mode
);
2397 if (DISPLAY_VER(i915
) < 4) {
2398 clock_limit
= i915
->display
.cdclk
.max_cdclk_freq
* 9 / 10;
2401 * Enable double wide mode when the dot clock
2402 * is > 90% of the (display) core speed.
2404 if (intel_crtc_supports_double_wide(crtc
) &&
2405 pipe_mode
->crtc_clock
> clock_limit
) {
2406 clock_limit
= i915
->max_dotclk_freq
;
2407 crtc_state
->double_wide
= true;
2411 if (pipe_mode
->crtc_clock
> clock_limit
) {
2412 drm_dbg_kms(&i915
->drm
,
2413 "[CRTC:%d:%s] requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
2414 crtc
->base
.base
.id
, crtc
->base
.name
,
2415 pipe_mode
->crtc_clock
, clock_limit
,
2416 str_yes_no(crtc_state
->double_wide
));
2423 static int intel_crtc_compute_config(struct intel_atomic_state
*state
,
2424 struct intel_crtc
*crtc
)
2426 struct intel_crtc_state
*crtc_state
=
2427 intel_atomic_get_new_crtc_state(state
, crtc
);
2430 ret
= intel_dpll_crtc_compute_clock(state
, crtc
);
2434 ret
= intel_crtc_compute_pipe_src(crtc_state
);
2438 ret
= intel_crtc_compute_pipe_mode(crtc_state
);
2442 intel_crtc_compute_pixel_rate(crtc_state
);
2444 if (crtc_state
->has_pch_encoder
)
2445 return ilk_fdi_compute_config(crtc
, crtc_state
);
2451 intel_reduce_m_n_ratio(u32
*num
, u32
*den
)
2453 while (*num
> DATA_LINK_M_N_MASK
||
2454 *den
> DATA_LINK_M_N_MASK
) {
2460 static void compute_m_n(u32
*ret_m
, u32
*ret_n
,
2461 u32 m
, u32 n
, u32 constant_n
)
2464 *ret_n
= constant_n
;
2466 *ret_n
= min_t(unsigned int, roundup_pow_of_two(n
), DATA_LINK_N_MAX
);
2468 *ret_m
= div_u64(mul_u32_u32(m
, *ret_n
), n
);
2469 intel_reduce_m_n_ratio(ret_m
, ret_n
);
2473 intel_link_compute_m_n(u16 bits_per_pixel_x16
, int nlanes
,
2474 int pixel_clock
, int link_clock
,
2476 struct intel_link_m_n
*m_n
)
2478 u32 link_symbol_clock
= intel_dp_link_symbol_clock(link_clock
);
2479 u32 data_m
= intel_dp_effective_data_rate(pixel_clock
, bits_per_pixel_x16
,
2481 u32 data_n
= intel_dp_max_data_rate(link_clock
, nlanes
);
2484 * Windows/BIOS uses fixed M/N values always. Follow suit.
2486 * Also several DP dongles in particular seem to be fussy
2487 * about too large link M/N values. Presumably the 20bit
2488 * value used by Windows/BIOS is acceptable to everyone.
2491 compute_m_n(&m_n
->data_m
, &m_n
->data_n
,
2495 compute_m_n(&m_n
->link_m
, &m_n
->link_n
,
2496 pixel_clock
, link_symbol_clock
,
2500 void intel_panel_sanitize_ssc(struct drm_i915_private
*dev_priv
)
2503 * There may be no VBT; and if the BIOS enabled SSC we can
2504 * just keep using it to avoid unnecessary flicker. Whereas if the
2505 * BIOS isn't using it, don't assume it will work even if the VBT
2506 * indicates as much.
2508 if (HAS_PCH_IBX(dev_priv
) || HAS_PCH_CPT(dev_priv
)) {
2509 bool bios_lvds_use_ssc
= intel_de_read(dev_priv
,
2513 if (dev_priv
->display
.vbt
.lvds_use_ssc
!= bios_lvds_use_ssc
) {
2514 drm_dbg_kms(&dev_priv
->drm
,
2515 "SSC %s by BIOS, overriding VBT which says %s\n",
2516 str_enabled_disabled(bios_lvds_use_ssc
),
2517 str_enabled_disabled(dev_priv
->display
.vbt
.lvds_use_ssc
));
2518 dev_priv
->display
.vbt
.lvds_use_ssc
= bios_lvds_use_ssc
;
2523 void intel_zero_m_n(struct intel_link_m_n
*m_n
)
2525 /* corresponds to 0 register value */
2526 memset(m_n
, 0, sizeof(*m_n
));
2530 void intel_set_m_n(struct drm_i915_private
*i915
,
2531 const struct intel_link_m_n
*m_n
,
2532 i915_reg_t data_m_reg
, i915_reg_t data_n_reg
,
2533 i915_reg_t link_m_reg
, i915_reg_t link_n_reg
)
2535 intel_de_write(i915
, data_m_reg
, TU_SIZE(m_n
->tu
) | m_n
->data_m
);
2536 intel_de_write(i915
, data_n_reg
, m_n
->data_n
);
2537 intel_de_write(i915
, link_m_reg
, m_n
->link_m
);
2539 * On BDW+ writing LINK_N arms the double buffered update
2540 * of all the M/N registers, so it must be written last.
2542 intel_de_write(i915
, link_n_reg
, m_n
->link_n
);
2545 bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private
*dev_priv
,
2546 enum transcoder transcoder
)
2548 if (IS_HASWELL(dev_priv
))
2549 return transcoder
== TRANSCODER_EDP
;
2551 return IS_DISPLAY_VER(dev_priv
, 5, 7) || IS_CHERRYVIEW(dev_priv
);
2554 void intel_cpu_transcoder_set_m1_n1(struct intel_crtc
*crtc
,
2555 enum transcoder transcoder
,
2556 const struct intel_link_m_n
*m_n
)
2558 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2559 enum pipe pipe
= crtc
->pipe
;
2561 if (DISPLAY_VER(dev_priv
) >= 5)
2562 intel_set_m_n(dev_priv
, m_n
,
2563 PIPE_DATA_M1(transcoder
), PIPE_DATA_N1(transcoder
),
2564 PIPE_LINK_M1(transcoder
), PIPE_LINK_N1(transcoder
));
2566 intel_set_m_n(dev_priv
, m_n
,
2567 PIPE_DATA_M_G4X(pipe
), PIPE_DATA_N_G4X(pipe
),
2568 PIPE_LINK_M_G4X(pipe
), PIPE_LINK_N_G4X(pipe
));
2571 void intel_cpu_transcoder_set_m2_n2(struct intel_crtc
*crtc
,
2572 enum transcoder transcoder
,
2573 const struct intel_link_m_n
*m_n
)
2575 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2577 if (!intel_cpu_transcoder_has_m2_n2(dev_priv
, transcoder
))
2580 intel_set_m_n(dev_priv
, m_n
,
2581 PIPE_DATA_M2(transcoder
), PIPE_DATA_N2(transcoder
),
2582 PIPE_LINK_M2(transcoder
), PIPE_LINK_N2(transcoder
));
2585 static void intel_set_transcoder_timings(const struct intel_crtc_state
*crtc_state
)
2587 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
2588 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2589 enum pipe pipe
= crtc
->pipe
;
2590 enum transcoder cpu_transcoder
= crtc_state
->cpu_transcoder
;
2591 const struct drm_display_mode
*adjusted_mode
= &crtc_state
->hw
.adjusted_mode
;
2592 u32 crtc_vdisplay
, crtc_vtotal
, crtc_vblank_start
, crtc_vblank_end
;
2595 /* We need to be careful not to changed the adjusted mode, for otherwise
2596 * the hw state checker will get angry at the mismatch. */
2597 crtc_vdisplay
= adjusted_mode
->crtc_vdisplay
;
2598 crtc_vtotal
= adjusted_mode
->crtc_vtotal
;
2599 crtc_vblank_start
= adjusted_mode
->crtc_vblank_start
;
2600 crtc_vblank_end
= adjusted_mode
->crtc_vblank_end
;
2602 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
2603 /* the chip adds 2 halflines automatically */
2605 crtc_vblank_end
-= 1;
2607 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_SDVO
))
2608 vsyncshift
= (adjusted_mode
->crtc_htotal
- 1) / 2;
2610 vsyncshift
= adjusted_mode
->crtc_hsync_start
-
2611 adjusted_mode
->crtc_htotal
/ 2;
2613 vsyncshift
+= adjusted_mode
->crtc_htotal
;
2617 * VBLANK_START no longer works on ADL+, instead we must use
2618 * TRANS_SET_CONTEXT_LATENCY to configure the pipe vblank start.
2620 if (DISPLAY_VER(dev_priv
) >= 13) {
2621 intel_de_write(dev_priv
, TRANS_SET_CONTEXT_LATENCY(cpu_transcoder
),
2622 crtc_vblank_start
- crtc_vdisplay
);
2625 * VBLANK_START not used by hw, just clear it
2626 * to make it stand out in register dumps.
2628 crtc_vblank_start
= 1;
2631 if (DISPLAY_VER(dev_priv
) >= 4)
2632 intel_de_write(dev_priv
, TRANS_VSYNCSHIFT(cpu_transcoder
),
2635 intel_de_write(dev_priv
, TRANS_HTOTAL(cpu_transcoder
),
2636 HACTIVE(adjusted_mode
->crtc_hdisplay
- 1) |
2637 HTOTAL(adjusted_mode
->crtc_htotal
- 1));
2638 intel_de_write(dev_priv
, TRANS_HBLANK(cpu_transcoder
),
2639 HBLANK_START(adjusted_mode
->crtc_hblank_start
- 1) |
2640 HBLANK_END(adjusted_mode
->crtc_hblank_end
- 1));
2641 intel_de_write(dev_priv
, TRANS_HSYNC(cpu_transcoder
),
2642 HSYNC_START(adjusted_mode
->crtc_hsync_start
- 1) |
2643 HSYNC_END(adjusted_mode
->crtc_hsync_end
- 1));
2645 intel_de_write(dev_priv
, TRANS_VTOTAL(cpu_transcoder
),
2646 VACTIVE(crtc_vdisplay
- 1) |
2647 VTOTAL(crtc_vtotal
- 1));
2648 intel_de_write(dev_priv
, TRANS_VBLANK(cpu_transcoder
),
2649 VBLANK_START(crtc_vblank_start
- 1) |
2650 VBLANK_END(crtc_vblank_end
- 1));
2651 intel_de_write(dev_priv
, TRANS_VSYNC(cpu_transcoder
),
2652 VSYNC_START(adjusted_mode
->crtc_vsync_start
- 1) |
2653 VSYNC_END(adjusted_mode
->crtc_vsync_end
- 1));
2655 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
2656 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
2657 * documented on the DDI_FUNC_CTL register description, EDP Input Select
2659 if (IS_HASWELL(dev_priv
) && cpu_transcoder
== TRANSCODER_EDP
&&
2660 (pipe
== PIPE_B
|| pipe
== PIPE_C
))
2661 intel_de_write(dev_priv
, TRANS_VTOTAL(pipe
),
2662 VACTIVE(crtc_vdisplay
- 1) |
2663 VTOTAL(crtc_vtotal
- 1));
2666 static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state
*crtc_state
)
2668 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
2669 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2670 enum transcoder cpu_transcoder
= crtc_state
->cpu_transcoder
;
2671 const struct drm_display_mode
*adjusted_mode
= &crtc_state
->hw
.adjusted_mode
;
2672 u32 crtc_vdisplay
, crtc_vtotal
, crtc_vblank_start
, crtc_vblank_end
;
2674 crtc_vdisplay
= adjusted_mode
->crtc_vdisplay
;
2675 crtc_vtotal
= adjusted_mode
->crtc_vtotal
;
2676 crtc_vblank_start
= adjusted_mode
->crtc_vblank_start
;
2677 crtc_vblank_end
= adjusted_mode
->crtc_vblank_end
;
2679 drm_WARN_ON(&dev_priv
->drm
, adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
);
2682 * The hardware actually ignores TRANS_VBLANK.VBLANK_END in DP mode.
2683 * But let's write it anyway to keep the state checker happy.
2685 intel_de_write(dev_priv
, TRANS_VBLANK(cpu_transcoder
),
2686 VBLANK_START(crtc_vblank_start
- 1) |
2687 VBLANK_END(crtc_vblank_end
- 1));
2689 * The double buffer latch point for TRANS_VTOTAL
2690 * is the transcoder's undelayed vblank.
2692 intel_de_write(dev_priv
, TRANS_VTOTAL(cpu_transcoder
),
2693 VACTIVE(crtc_vdisplay
- 1) |
2694 VTOTAL(crtc_vtotal
- 1));
2697 static void intel_set_pipe_src_size(const struct intel_crtc_state
*crtc_state
)
2699 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
2700 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2701 int width
= drm_rect_width(&crtc_state
->pipe_src
);
2702 int height
= drm_rect_height(&crtc_state
->pipe_src
);
2703 enum pipe pipe
= crtc
->pipe
;
2705 /* pipesrc controls the size that is scaled from, which should
2706 * always be the user's requested size.
2708 intel_de_write(dev_priv
, PIPESRC(pipe
),
2709 PIPESRC_WIDTH(width
- 1) | PIPESRC_HEIGHT(height
- 1));
2711 if (!crtc_state
->enable_psr2_su_region_et
)
2714 width
= drm_rect_width(&crtc_state
->psr2_su_area
);
2715 height
= drm_rect_height(&crtc_state
->psr2_su_area
);
2717 intel_de_write(dev_priv
, PIPE_SRCSZ_ERLY_TPT(pipe
),
2718 PIPESRC_WIDTH(width
- 1) | PIPESRC_HEIGHT(height
- 1));
2721 static bool intel_pipe_is_interlaced(const struct intel_crtc_state
*crtc_state
)
2723 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->uapi
.crtc
->dev
);
2724 enum transcoder cpu_transcoder
= crtc_state
->cpu_transcoder
;
2726 if (DISPLAY_VER(dev_priv
) == 2)
2729 if (DISPLAY_VER(dev_priv
) >= 9 ||
2730 IS_BROADWELL(dev_priv
) || IS_HASWELL(dev_priv
))
2731 return intel_de_read(dev_priv
, TRANSCONF(cpu_transcoder
)) & TRANSCONF_INTERLACE_MASK_HSW
;
2733 return intel_de_read(dev_priv
, TRANSCONF(cpu_transcoder
)) & TRANSCONF_INTERLACE_MASK
;
2736 static void intel_get_transcoder_timings(struct intel_crtc
*crtc
,
2737 struct intel_crtc_state
*pipe_config
)
2739 struct drm_device
*dev
= crtc
->base
.dev
;
2740 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2741 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
2742 struct drm_display_mode
*adjusted_mode
= &pipe_config
->hw
.adjusted_mode
;
2745 tmp
= intel_de_read(dev_priv
, TRANS_HTOTAL(cpu_transcoder
));
2746 adjusted_mode
->crtc_hdisplay
= REG_FIELD_GET(HACTIVE_MASK
, tmp
) + 1;
2747 adjusted_mode
->crtc_htotal
= REG_FIELD_GET(HTOTAL_MASK
, tmp
) + 1;
2749 if (!transcoder_is_dsi(cpu_transcoder
)) {
2750 tmp
= intel_de_read(dev_priv
, TRANS_HBLANK(cpu_transcoder
));
2751 adjusted_mode
->crtc_hblank_start
= REG_FIELD_GET(HBLANK_START_MASK
, tmp
) + 1;
2752 adjusted_mode
->crtc_hblank_end
= REG_FIELD_GET(HBLANK_END_MASK
, tmp
) + 1;
2755 tmp
= intel_de_read(dev_priv
, TRANS_HSYNC(cpu_transcoder
));
2756 adjusted_mode
->crtc_hsync_start
= REG_FIELD_GET(HSYNC_START_MASK
, tmp
) + 1;
2757 adjusted_mode
->crtc_hsync_end
= REG_FIELD_GET(HSYNC_END_MASK
, tmp
) + 1;
2759 tmp
= intel_de_read(dev_priv
, TRANS_VTOTAL(cpu_transcoder
));
2760 adjusted_mode
->crtc_vdisplay
= REG_FIELD_GET(VACTIVE_MASK
, tmp
) + 1;
2761 adjusted_mode
->crtc_vtotal
= REG_FIELD_GET(VTOTAL_MASK
, tmp
) + 1;
2763 /* FIXME TGL+ DSI transcoders have this! */
2764 if (!transcoder_is_dsi(cpu_transcoder
)) {
2765 tmp
= intel_de_read(dev_priv
, TRANS_VBLANK(cpu_transcoder
));
2766 adjusted_mode
->crtc_vblank_start
= REG_FIELD_GET(VBLANK_START_MASK
, tmp
) + 1;
2767 adjusted_mode
->crtc_vblank_end
= REG_FIELD_GET(VBLANK_END_MASK
, tmp
) + 1;
2769 tmp
= intel_de_read(dev_priv
, TRANS_VSYNC(cpu_transcoder
));
2770 adjusted_mode
->crtc_vsync_start
= REG_FIELD_GET(VSYNC_START_MASK
, tmp
) + 1;
2771 adjusted_mode
->crtc_vsync_end
= REG_FIELD_GET(VSYNC_END_MASK
, tmp
) + 1;
2773 if (intel_pipe_is_interlaced(pipe_config
)) {
2774 adjusted_mode
->flags
|= DRM_MODE_FLAG_INTERLACE
;
2775 adjusted_mode
->crtc_vtotal
+= 1;
2776 adjusted_mode
->crtc_vblank_end
+= 1;
2779 if (DISPLAY_VER(dev_priv
) >= 13 && !transcoder_is_dsi(cpu_transcoder
))
2780 adjusted_mode
->crtc_vblank_start
=
2781 adjusted_mode
->crtc_vdisplay
+
2782 intel_de_read(dev_priv
, TRANS_SET_CONTEXT_LATENCY(cpu_transcoder
));
2785 static void intel_bigjoiner_adjust_pipe_src(struct intel_crtc_state
*crtc_state
)
2787 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
2788 int num_pipes
= intel_bigjoiner_num_pipes(crtc_state
);
2789 enum pipe master_pipe
, pipe
= crtc
->pipe
;
2795 master_pipe
= bigjoiner_master_pipe(crtc_state
);
2796 width
= drm_rect_width(&crtc_state
->pipe_src
);
2798 drm_rect_translate_to(&crtc_state
->pipe_src
,
2799 (pipe
- master_pipe
) * width
, 0);
2802 static void intel_get_pipe_src_size(struct intel_crtc
*crtc
,
2803 struct intel_crtc_state
*pipe_config
)
2805 struct drm_device
*dev
= crtc
->base
.dev
;
2806 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2809 tmp
= intel_de_read(dev_priv
, PIPESRC(crtc
->pipe
));
2811 drm_rect_init(&pipe_config
->pipe_src
, 0, 0,
2812 REG_FIELD_GET(PIPESRC_WIDTH_MASK
, tmp
) + 1,
2813 REG_FIELD_GET(PIPESRC_HEIGHT_MASK
, tmp
) + 1);
2815 intel_bigjoiner_adjust_pipe_src(pipe_config
);
2818 void i9xx_set_pipeconf(const struct intel_crtc_state
*crtc_state
)
2820 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
2821 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2822 enum transcoder cpu_transcoder
= crtc_state
->cpu_transcoder
;
2826 * - We keep both pipes enabled on 830
2827 * - During modeset the pipe is still disabled and must remain so
2828 * - During fastset the pipe is already enabled and must remain so
2830 if (IS_I830(dev_priv
) || !intel_crtc_needs_modeset(crtc_state
))
2831 val
|= TRANSCONF_ENABLE
;
2833 if (crtc_state
->double_wide
)
2834 val
|= TRANSCONF_DOUBLE_WIDE
;
2836 /* only g4x and later have fancy bpc/dither controls */
2837 if (IS_G4X(dev_priv
) || IS_VALLEYVIEW(dev_priv
) ||
2838 IS_CHERRYVIEW(dev_priv
)) {
2839 /* Bspec claims that we can't use dithering for 30bpp pipes. */
2840 if (crtc_state
->dither
&& crtc_state
->pipe_bpp
!= 30)
2841 val
|= TRANSCONF_DITHER_EN
|
2842 TRANSCONF_DITHER_TYPE_SP
;
2844 switch (crtc_state
->pipe_bpp
) {
2846 /* Case prevented by intel_choose_pipe_bpp_dither. */
2847 MISSING_CASE(crtc_state
->pipe_bpp
);
2850 val
|= TRANSCONF_BPC_6
;
2853 val
|= TRANSCONF_BPC_8
;
2856 val
|= TRANSCONF_BPC_10
;
2861 if (crtc_state
->hw
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
) {
2862 if (DISPLAY_VER(dev_priv
) < 4 ||
2863 intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_SDVO
))
2864 val
|= TRANSCONF_INTERLACE_W_FIELD_INDICATION
;
2866 val
|= TRANSCONF_INTERLACE_W_SYNC_SHIFT
;
2868 val
|= TRANSCONF_INTERLACE_PROGRESSIVE
;
2871 if ((IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) &&
2872 crtc_state
->limited_color_range
)
2873 val
|= TRANSCONF_COLOR_RANGE_SELECT
;
2875 val
|= TRANSCONF_GAMMA_MODE(crtc_state
->gamma_mode
);
2877 if (crtc_state
->wgc_enable
)
2878 val
|= TRANSCONF_WGC_ENABLE
;
2880 val
|= TRANSCONF_FRAME_START_DELAY(crtc_state
->framestart_delay
- 1);
2882 intel_de_write(dev_priv
, TRANSCONF(cpu_transcoder
), val
);
2883 intel_de_posting_read(dev_priv
, TRANSCONF(cpu_transcoder
));
2886 static bool i9xx_has_pfit(struct drm_i915_private
*dev_priv
)
2888 if (IS_I830(dev_priv
))
2891 return DISPLAY_VER(dev_priv
) >= 4 ||
2892 IS_PINEVIEW(dev_priv
) || IS_MOBILE(dev_priv
);
2895 static void i9xx_get_pfit_config(struct intel_crtc_state
*crtc_state
)
2897 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
2898 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2902 if (!i9xx_has_pfit(dev_priv
))
2905 tmp
= intel_de_read(dev_priv
, PFIT_CONTROL
);
2906 if (!(tmp
& PFIT_ENABLE
))
2909 /* Check whether the pfit is attached to our pipe. */
2910 if (DISPLAY_VER(dev_priv
) >= 4)
2911 pipe
= REG_FIELD_GET(PFIT_PIPE_MASK
, tmp
);
2915 if (pipe
!= crtc
->pipe
)
2918 crtc_state
->gmch_pfit
.control
= tmp
;
2919 crtc_state
->gmch_pfit
.pgm_ratios
=
2920 intel_de_read(dev_priv
, PFIT_PGM_RATIOS
);
2923 static enum intel_output_format
2924 bdw_get_pipe_misc_output_format(struct intel_crtc
*crtc
)
2926 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2929 tmp
= intel_de_read(dev_priv
, PIPE_MISC(crtc
->pipe
));
2931 if (tmp
& PIPE_MISC_YUV420_ENABLE
) {
2932 /* We support 4:2:0 in full blend mode only */
2933 drm_WARN_ON(&dev_priv
->drm
,
2934 (tmp
& PIPE_MISC_YUV420_MODE_FULL_BLEND
) == 0);
2936 return INTEL_OUTPUT_FORMAT_YCBCR420
;
2937 } else if (tmp
& PIPE_MISC_OUTPUT_COLORSPACE_YUV
) {
2938 return INTEL_OUTPUT_FORMAT_YCBCR444
;
2940 return INTEL_OUTPUT_FORMAT_RGB
;
2944 static bool i9xx_get_pipe_config(struct intel_crtc
*crtc
,
2945 struct intel_crtc_state
*pipe_config
)
2947 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2948 enum intel_display_power_domain power_domain
;
2949 intel_wakeref_t wakeref
;
2953 power_domain
= POWER_DOMAIN_PIPE(crtc
->pipe
);
2954 wakeref
= intel_display_power_get_if_enabled(dev_priv
, power_domain
);
2958 pipe_config
->output_format
= INTEL_OUTPUT_FORMAT_RGB
;
2959 pipe_config
->sink_format
= pipe_config
->output_format
;
2960 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
2961 pipe_config
->shared_dpll
= NULL
;
2965 tmp
= intel_de_read(dev_priv
, TRANSCONF(pipe_config
->cpu_transcoder
));
2966 if (!(tmp
& TRANSCONF_ENABLE
))
2969 if (IS_G4X(dev_priv
) || IS_VALLEYVIEW(dev_priv
) ||
2970 IS_CHERRYVIEW(dev_priv
)) {
2971 switch (tmp
& TRANSCONF_BPC_MASK
) {
2972 case TRANSCONF_BPC_6
:
2973 pipe_config
->pipe_bpp
= 18;
2975 case TRANSCONF_BPC_8
:
2976 pipe_config
->pipe_bpp
= 24;
2978 case TRANSCONF_BPC_10
:
2979 pipe_config
->pipe_bpp
= 30;
2987 if ((IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) &&
2988 (tmp
& TRANSCONF_COLOR_RANGE_SELECT
))
2989 pipe_config
->limited_color_range
= true;
2991 pipe_config
->gamma_mode
= REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_I9XX
, tmp
);
2993 pipe_config
->framestart_delay
= REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK
, tmp
) + 1;
2995 if ((IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) &&
2996 (tmp
& TRANSCONF_WGC_ENABLE
))
2997 pipe_config
->wgc_enable
= true;
2999 intel_color_get_config(pipe_config
);
3001 if (DISPLAY_VER(dev_priv
) < 4)
3002 pipe_config
->double_wide
= tmp
& TRANSCONF_DOUBLE_WIDE
;
3004 intel_get_transcoder_timings(crtc
, pipe_config
);
3005 intel_get_pipe_src_size(crtc
, pipe_config
);
3007 i9xx_get_pfit_config(pipe_config
);
3009 if (DISPLAY_VER(dev_priv
) >= 4) {
3010 /* No way to read it out on pipes B and C */
3011 if (IS_CHERRYVIEW(dev_priv
) && crtc
->pipe
!= PIPE_A
)
3012 tmp
= dev_priv
->display
.state
.chv_dpll_md
[crtc
->pipe
];
3014 tmp
= intel_de_read(dev_priv
, DPLL_MD(crtc
->pipe
));
3015 pipe_config
->pixel_multiplier
=
3016 ((tmp
& DPLL_MD_UDI_MULTIPLIER_MASK
)
3017 >> DPLL_MD_UDI_MULTIPLIER_SHIFT
) + 1;
3018 pipe_config
->dpll_hw_state
.dpll_md
= tmp
;
3019 } else if (IS_I945G(dev_priv
) || IS_I945GM(dev_priv
) ||
3020 IS_G33(dev_priv
) || IS_PINEVIEW(dev_priv
)) {
3021 tmp
= intel_de_read(dev_priv
, DPLL(crtc
->pipe
));
3022 pipe_config
->pixel_multiplier
=
3023 ((tmp
& SDVO_MULTIPLIER_MASK
)
3024 >> SDVO_MULTIPLIER_SHIFT_HIRES
) + 1;
3026 /* Note that on i915G/GM the pixel multiplier is in the sdvo
3027 * port and will be fixed up in the encoder->get_config
3029 pipe_config
->pixel_multiplier
= 1;
3031 pipe_config
->dpll_hw_state
.dpll
= intel_de_read(dev_priv
,
3033 if (!IS_VALLEYVIEW(dev_priv
) && !IS_CHERRYVIEW(dev_priv
)) {
3034 pipe_config
->dpll_hw_state
.fp0
= intel_de_read(dev_priv
,
3036 pipe_config
->dpll_hw_state
.fp1
= intel_de_read(dev_priv
,
3039 /* Mask out read-only status bits. */
3040 pipe_config
->dpll_hw_state
.dpll
&= ~(DPLL_LOCK_VLV
|
3041 DPLL_PORTC_READY_MASK
|
3042 DPLL_PORTB_READY_MASK
);
3045 if (IS_CHERRYVIEW(dev_priv
))
3046 chv_crtc_clock_get(crtc
, pipe_config
);
3047 else if (IS_VALLEYVIEW(dev_priv
))
3048 vlv_crtc_clock_get(crtc
, pipe_config
);
3050 i9xx_crtc_clock_get(crtc
, pipe_config
);
3053 * Normally the dotclock is filled in by the encoder .get_config()
3054 * but in case the pipe is enabled w/o any ports we need a sane
3057 pipe_config
->hw
.adjusted_mode
.crtc_clock
=
3058 pipe_config
->port_clock
/ pipe_config
->pixel_multiplier
;
3063 intel_display_power_put(dev_priv
, power_domain
, wakeref
);
3068 void ilk_set_pipeconf(const struct intel_crtc_state
*crtc_state
)
3070 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
3071 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
3072 enum transcoder cpu_transcoder
= crtc_state
->cpu_transcoder
;
3076 * - During modeset the pipe is still disabled and must remain so
3077 * - During fastset the pipe is already enabled and must remain so
3079 if (!intel_crtc_needs_modeset(crtc_state
))
3080 val
|= TRANSCONF_ENABLE
;
3082 switch (crtc_state
->pipe_bpp
) {
3084 /* Case prevented by intel_choose_pipe_bpp_dither. */
3085 MISSING_CASE(crtc_state
->pipe_bpp
);
3088 val
|= TRANSCONF_BPC_6
;
3091 val
|= TRANSCONF_BPC_8
;
3094 val
|= TRANSCONF_BPC_10
;
3097 val
|= TRANSCONF_BPC_12
;
3101 if (crtc_state
->dither
)
3102 val
|= TRANSCONF_DITHER_EN
| TRANSCONF_DITHER_TYPE_SP
;
3104 if (crtc_state
->hw
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
3105 val
|= TRANSCONF_INTERLACE_IF_ID_ILK
;
3107 val
|= TRANSCONF_INTERLACE_PF_PD_ILK
;
3110 * This would end up with an odd purple hue over
3111 * the entire display. Make sure we don't do it.
3113 drm_WARN_ON(&dev_priv
->drm
, crtc_state
->limited_color_range
&&
3114 crtc_state
->output_format
!= INTEL_OUTPUT_FORMAT_RGB
);
3116 if (crtc_state
->limited_color_range
&&
3117 !intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_SDVO
))
3118 val
|= TRANSCONF_COLOR_RANGE_SELECT
;
3120 if (crtc_state
->output_format
!= INTEL_OUTPUT_FORMAT_RGB
)
3121 val
|= TRANSCONF_OUTPUT_COLORSPACE_YUV709
;
3123 val
|= TRANSCONF_GAMMA_MODE(crtc_state
->gamma_mode
);
3125 val
|= TRANSCONF_FRAME_START_DELAY(crtc_state
->framestart_delay
- 1);
3126 val
|= TRANSCONF_MSA_TIMING_DELAY(crtc_state
->msa_timing_delay
);
3128 intel_de_write(dev_priv
, TRANSCONF(cpu_transcoder
), val
);
3129 intel_de_posting_read(dev_priv
, TRANSCONF(cpu_transcoder
));
3132 static void hsw_set_transconf(const struct intel_crtc_state
*crtc_state
)
3134 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
3135 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
3136 enum transcoder cpu_transcoder
= crtc_state
->cpu_transcoder
;
3140 * - During modeset the pipe is still disabled and must remain so
3141 * - During fastset the pipe is already enabled and must remain so
3143 if (!intel_crtc_needs_modeset(crtc_state
))
3144 val
|= TRANSCONF_ENABLE
;
3146 if (IS_HASWELL(dev_priv
) && crtc_state
->dither
)
3147 val
|= TRANSCONF_DITHER_EN
| TRANSCONF_DITHER_TYPE_SP
;
3149 if (crtc_state
->hw
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
3150 val
|= TRANSCONF_INTERLACE_IF_ID_ILK
;
3152 val
|= TRANSCONF_INTERLACE_PF_PD_ILK
;
3154 if (IS_HASWELL(dev_priv
) &&
3155 crtc_state
->output_format
!= INTEL_OUTPUT_FORMAT_RGB
)
3156 val
|= TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW
;
3158 intel_de_write(dev_priv
, TRANSCONF(cpu_transcoder
), val
);
3159 intel_de_posting_read(dev_priv
, TRANSCONF(cpu_transcoder
));
3162 static void bdw_set_pipe_misc(const struct intel_crtc_state
*crtc_state
)
3164 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
3165 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
3168 switch (crtc_state
->pipe_bpp
) {
3170 val
|= PIPE_MISC_BPC_6
;
3173 val
|= PIPE_MISC_BPC_8
;
3176 val
|= PIPE_MISC_BPC_10
;
3179 /* Port output 12BPC defined for ADLP+ */
3180 if (DISPLAY_VER(dev_priv
) >= 13)
3181 val
|= PIPE_MISC_BPC_12_ADLP
;
3184 MISSING_CASE(crtc_state
->pipe_bpp
);
3188 if (crtc_state
->dither
)
3189 val
|= PIPE_MISC_DITHER_ENABLE
| PIPE_MISC_DITHER_TYPE_SP
;
3191 if (crtc_state
->output_format
== INTEL_OUTPUT_FORMAT_YCBCR420
||
3192 crtc_state
->output_format
== INTEL_OUTPUT_FORMAT_YCBCR444
)
3193 val
|= PIPE_MISC_OUTPUT_COLORSPACE_YUV
;
3195 if (crtc_state
->output_format
== INTEL_OUTPUT_FORMAT_YCBCR420
)
3196 val
|= PIPE_MISC_YUV420_ENABLE
|
3197 PIPE_MISC_YUV420_MODE_FULL_BLEND
;
3199 if (DISPLAY_VER(dev_priv
) >= 11 && is_hdr_mode(crtc_state
))
3200 val
|= PIPE_MISC_HDR_MODE_PRECISION
;
3202 if (DISPLAY_VER(dev_priv
) >= 12)
3203 val
|= PIPE_MISC_PIXEL_ROUNDING_TRUNC
;
3205 /* allow PSR with sprite enabled */
3206 if (IS_BROADWELL(dev_priv
))
3207 val
|= PIPE_MISC_PSR_MASK_SPRITE_ENABLE
;
3209 intel_de_write(dev_priv
, PIPE_MISC(crtc
->pipe
), val
);
3212 int bdw_get_pipe_misc_bpp(struct intel_crtc
*crtc
)
3214 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
3217 tmp
= intel_de_read(dev_priv
, PIPE_MISC(crtc
->pipe
));
3219 switch (tmp
& PIPE_MISC_BPC_MASK
) {
3220 case PIPE_MISC_BPC_6
:
3222 case PIPE_MISC_BPC_8
:
3224 case PIPE_MISC_BPC_10
:
3227 * PORT OUTPUT 12 BPC defined for ADLP+.
3230 * For previous platforms with DSI interface, bits 5:7
3231 * are used for storing pipe_bpp irrespective of dithering.
3232 * Since the value of 12 BPC is not defined for these bits
3233 * on older platforms, need to find a workaround for 12 BPC
3234 * MIPI DSI HW readout.
3236 case PIPE_MISC_BPC_12_ADLP
:
3237 if (DISPLAY_VER(dev_priv
) >= 13)
3246 int ilk_get_lanes_required(int target_clock
, int link_bw
, int bpp
)
3249 * Account for spread spectrum to avoid
3250 * oversubscribing the link. Max center spread
3251 * is 2.5%; use 5% for safety's sake.
3253 u32 bps
= target_clock
* bpp
* 21 / 20;
3254 return DIV_ROUND_UP(bps
, link_bw
* 8);
3257 void intel_get_m_n(struct drm_i915_private
*i915
,
3258 struct intel_link_m_n
*m_n
,
3259 i915_reg_t data_m_reg
, i915_reg_t data_n_reg
,
3260 i915_reg_t link_m_reg
, i915_reg_t link_n_reg
)
3262 m_n
->link_m
= intel_de_read(i915
, link_m_reg
) & DATA_LINK_M_N_MASK
;
3263 m_n
->link_n
= intel_de_read(i915
, link_n_reg
) & DATA_LINK_M_N_MASK
;
3264 m_n
->data_m
= intel_de_read(i915
, data_m_reg
) & DATA_LINK_M_N_MASK
;
3265 m_n
->data_n
= intel_de_read(i915
, data_n_reg
) & DATA_LINK_M_N_MASK
;
3266 m_n
->tu
= REG_FIELD_GET(TU_SIZE_MASK
, intel_de_read(i915
, data_m_reg
)) + 1;
3269 void intel_cpu_transcoder_get_m1_n1(struct intel_crtc
*crtc
,
3270 enum transcoder transcoder
,
3271 struct intel_link_m_n
*m_n
)
3273 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
3274 enum pipe pipe
= crtc
->pipe
;
3276 if (DISPLAY_VER(dev_priv
) >= 5)
3277 intel_get_m_n(dev_priv
, m_n
,
3278 PIPE_DATA_M1(transcoder
), PIPE_DATA_N1(transcoder
),
3279 PIPE_LINK_M1(transcoder
), PIPE_LINK_N1(transcoder
));
3281 intel_get_m_n(dev_priv
, m_n
,
3282 PIPE_DATA_M_G4X(pipe
), PIPE_DATA_N_G4X(pipe
),
3283 PIPE_LINK_M_G4X(pipe
), PIPE_LINK_N_G4X(pipe
));
3286 void intel_cpu_transcoder_get_m2_n2(struct intel_crtc
*crtc
,
3287 enum transcoder transcoder
,
3288 struct intel_link_m_n
*m_n
)
3290 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
3292 if (!intel_cpu_transcoder_has_m2_n2(dev_priv
, transcoder
))
3295 intel_get_m_n(dev_priv
, m_n
,
3296 PIPE_DATA_M2(transcoder
), PIPE_DATA_N2(transcoder
),
3297 PIPE_LINK_M2(transcoder
), PIPE_LINK_N2(transcoder
));
3300 static void ilk_get_pfit_config(struct intel_crtc_state
*crtc_state
)
3302 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
3303 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
3307 ctl
= intel_de_read(dev_priv
, PF_CTL(crtc
->pipe
));
3308 if ((ctl
& PF_ENABLE
) == 0)
3311 if (IS_IVYBRIDGE(dev_priv
) || IS_HASWELL(dev_priv
))
3312 pipe
= REG_FIELD_GET(PF_PIPE_SEL_MASK_IVB
, ctl
);
3316 crtc_state
->pch_pfit
.enabled
= true;
3318 pos
= intel_de_read(dev_priv
, PF_WIN_POS(crtc
->pipe
));
3319 size
= intel_de_read(dev_priv
, PF_WIN_SZ(crtc
->pipe
));
3321 drm_rect_init(&crtc_state
->pch_pfit
.dst
,
3322 REG_FIELD_GET(PF_WIN_XPOS_MASK
, pos
),
3323 REG_FIELD_GET(PF_WIN_YPOS_MASK
, pos
),
3324 REG_FIELD_GET(PF_WIN_XSIZE_MASK
, size
),
3325 REG_FIELD_GET(PF_WIN_YSIZE_MASK
, size
));
3328 * We currently do not free assignements of panel fitters on
3329 * ivb/hsw (since we don't use the higher upscaling modes which
3330 * differentiates them) so just WARN about this case for now.
3332 drm_WARN_ON(&dev_priv
->drm
, pipe
!= crtc
->pipe
);
3335 static bool ilk_get_pipe_config(struct intel_crtc
*crtc
,
3336 struct intel_crtc_state
*pipe_config
)
3338 struct drm_device
*dev
= crtc
->base
.dev
;
3339 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3340 enum intel_display_power_domain power_domain
;
3341 intel_wakeref_t wakeref
;
3345 power_domain
= POWER_DOMAIN_PIPE(crtc
->pipe
);
3346 wakeref
= intel_display_power_get_if_enabled(dev_priv
, power_domain
);
3350 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
3351 pipe_config
->shared_dpll
= NULL
;
3354 tmp
= intel_de_read(dev_priv
, TRANSCONF(pipe_config
->cpu_transcoder
));
3355 if (!(tmp
& TRANSCONF_ENABLE
))
3358 switch (tmp
& TRANSCONF_BPC_MASK
) {
3359 case TRANSCONF_BPC_6
:
3360 pipe_config
->pipe_bpp
= 18;
3362 case TRANSCONF_BPC_8
:
3363 pipe_config
->pipe_bpp
= 24;
3365 case TRANSCONF_BPC_10
:
3366 pipe_config
->pipe_bpp
= 30;
3368 case TRANSCONF_BPC_12
:
3369 pipe_config
->pipe_bpp
= 36;
3375 if (tmp
& TRANSCONF_COLOR_RANGE_SELECT
)
3376 pipe_config
->limited_color_range
= true;
3378 switch (tmp
& TRANSCONF_OUTPUT_COLORSPACE_MASK
) {
3379 case TRANSCONF_OUTPUT_COLORSPACE_YUV601
:
3380 case TRANSCONF_OUTPUT_COLORSPACE_YUV709
:
3381 pipe_config
->output_format
= INTEL_OUTPUT_FORMAT_YCBCR444
;
3384 pipe_config
->output_format
= INTEL_OUTPUT_FORMAT_RGB
;
3388 pipe_config
->sink_format
= pipe_config
->output_format
;
3390 pipe_config
->gamma_mode
= REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_ILK
, tmp
);
3392 pipe_config
->framestart_delay
= REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK
, tmp
) + 1;
3394 pipe_config
->msa_timing_delay
= REG_FIELD_GET(TRANSCONF_MSA_TIMING_DELAY_MASK
, tmp
);
3396 intel_color_get_config(pipe_config
);
3398 pipe_config
->pixel_multiplier
= 1;
3400 ilk_pch_get_config(pipe_config
);
3402 intel_get_transcoder_timings(crtc
, pipe_config
);
3403 intel_get_pipe_src_size(crtc
, pipe_config
);
3405 ilk_get_pfit_config(pipe_config
);
3410 intel_display_power_put(dev_priv
, power_domain
, wakeref
);
3415 static u8
bigjoiner_pipes(struct drm_i915_private
*i915
)
3419 if (DISPLAY_VER(i915
) >= 12)
3420 pipes
= BIT(PIPE_A
) | BIT(PIPE_B
) | BIT(PIPE_C
) | BIT(PIPE_D
);
3421 else if (DISPLAY_VER(i915
) >= 11)
3422 pipes
= BIT(PIPE_B
) | BIT(PIPE_C
);
3426 return pipes
& DISPLAY_RUNTIME_INFO(i915
)->pipe_mask
;
3429 static bool transcoder_ddi_func_is_enabled(struct drm_i915_private
*dev_priv
,
3430 enum transcoder cpu_transcoder
)
3432 enum intel_display_power_domain power_domain
;
3433 intel_wakeref_t wakeref
;
3436 power_domain
= POWER_DOMAIN_TRANSCODER(cpu_transcoder
);
3438 with_intel_display_power_if_enabled(dev_priv
, power_domain
, wakeref
)
3439 tmp
= intel_de_read(dev_priv
, TRANS_DDI_FUNC_CTL(cpu_transcoder
));
3441 return tmp
& TRANS_DDI_FUNC_ENABLE
;
3444 static void enabled_bigjoiner_pipes(struct drm_i915_private
*dev_priv
,
3445 u8
*master_pipes
, u8
*slave_pipes
)
3447 struct intel_crtc
*crtc
;
3452 for_each_intel_crtc_in_pipe_mask(&dev_priv
->drm
, crtc
,
3453 bigjoiner_pipes(dev_priv
)) {
3454 enum intel_display_power_domain power_domain
;
3455 enum pipe pipe
= crtc
->pipe
;
3456 intel_wakeref_t wakeref
;
3458 power_domain
= intel_dsc_power_domain(crtc
, (enum transcoder
) pipe
);
3459 with_intel_display_power_if_enabled(dev_priv
, power_domain
, wakeref
) {
3460 u32 tmp
= intel_de_read(dev_priv
, ICL_PIPE_DSS_CTL1(pipe
));
3462 if (!(tmp
& BIG_JOINER_ENABLE
))
3465 if (tmp
& MASTER_BIG_JOINER_ENABLE
)
3466 *master_pipes
|= BIT(pipe
);
3468 *slave_pipes
|= BIT(pipe
);
3471 if (DISPLAY_VER(dev_priv
) < 13)
3474 power_domain
= POWER_DOMAIN_PIPE(pipe
);
3475 with_intel_display_power_if_enabled(dev_priv
, power_domain
, wakeref
) {
3476 u32 tmp
= intel_de_read(dev_priv
, ICL_PIPE_DSS_CTL1(pipe
));
3478 if (tmp
& UNCOMPRESSED_JOINER_MASTER
)
3479 *master_pipes
|= BIT(pipe
);
3480 if (tmp
& UNCOMPRESSED_JOINER_SLAVE
)
3481 *slave_pipes
|= BIT(pipe
);
3485 /* Bigjoiner pipes should always be consecutive master and slave */
3486 drm_WARN(&dev_priv
->drm
, *slave_pipes
!= *master_pipes
<< 1,
3487 "Bigjoiner misconfigured (master pipes 0x%x, slave pipes 0x%x)\n",
3488 *master_pipes
, *slave_pipes
);
3491 static enum pipe
get_bigjoiner_master_pipe(enum pipe pipe
, u8 master_pipes
, u8 slave_pipes
)
3493 if ((slave_pipes
& BIT(pipe
)) == 0)
3496 /* ignore everything above our pipe */
3497 master_pipes
&= ~GENMASK(7, pipe
);
3499 /* highest remaining bit should be our master pipe */
3500 return fls(master_pipes
) - 1;
3503 static u8
get_bigjoiner_slave_pipes(enum pipe pipe
, u8 master_pipes
, u8 slave_pipes
)
3505 enum pipe master_pipe
, next_master_pipe
;
3507 master_pipe
= get_bigjoiner_master_pipe(pipe
, master_pipes
, slave_pipes
);
3509 if ((master_pipes
& BIT(master_pipe
)) == 0)
3512 /* ignore our master pipe and everything below it */
3513 master_pipes
&= ~GENMASK(master_pipe
, 0);
3514 /* make sure a high bit is set for the ffs() */
3515 master_pipes
|= BIT(7);
3516 /* lowest remaining bit should be the next master pipe */
3517 next_master_pipe
= ffs(master_pipes
) - 1;
3519 return slave_pipes
& GENMASK(next_master_pipe
- 1, master_pipe
);
3522 static u8
hsw_panel_transcoders(struct drm_i915_private
*i915
)
3524 u8 panel_transcoder_mask
= BIT(TRANSCODER_EDP
);
3526 if (DISPLAY_VER(i915
) >= 11)
3527 panel_transcoder_mask
|= BIT(TRANSCODER_DSI_0
) | BIT(TRANSCODER_DSI_1
);
3529 return panel_transcoder_mask
;
3532 static u8
hsw_enabled_transcoders(struct intel_crtc
*crtc
)
3534 struct drm_device
*dev
= crtc
->base
.dev
;
3535 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3536 u8 panel_transcoder_mask
= hsw_panel_transcoders(dev_priv
);
3537 enum transcoder cpu_transcoder
;
3538 u8 master_pipes
, slave_pipes
;
3539 u8 enabled_transcoders
= 0;
3542 * XXX: Do intel_display_power_get_if_enabled before reading this (for
3543 * consistency and less surprising code; it's in always on power).
3545 for_each_cpu_transcoder_masked(dev_priv
, cpu_transcoder
,
3546 panel_transcoder_mask
) {
3547 enum intel_display_power_domain power_domain
;
3548 intel_wakeref_t wakeref
;
3549 enum pipe trans_pipe
;
3552 power_domain
= POWER_DOMAIN_TRANSCODER(cpu_transcoder
);
3553 with_intel_display_power_if_enabled(dev_priv
, power_domain
, wakeref
)
3554 tmp
= intel_de_read(dev_priv
, TRANS_DDI_FUNC_CTL(cpu_transcoder
));
3556 if (!(tmp
& TRANS_DDI_FUNC_ENABLE
))
3559 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
3562 "unknown pipe linked to transcoder %s\n",
3563 transcoder_name(cpu_transcoder
));
3565 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
3566 case TRANS_DDI_EDP_INPUT_A_ON
:
3567 trans_pipe
= PIPE_A
;
3569 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
3570 trans_pipe
= PIPE_B
;
3572 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
3573 trans_pipe
= PIPE_C
;
3575 case TRANS_DDI_EDP_INPUT_D_ONOFF
:
3576 trans_pipe
= PIPE_D
;
3580 if (trans_pipe
== crtc
->pipe
)
3581 enabled_transcoders
|= BIT(cpu_transcoder
);
3584 /* single pipe or bigjoiner master */
3585 cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
3586 if (transcoder_ddi_func_is_enabled(dev_priv
, cpu_transcoder
))
3587 enabled_transcoders
|= BIT(cpu_transcoder
);
3589 /* bigjoiner slave -> consider the master pipe's transcoder as well */
3590 enabled_bigjoiner_pipes(dev_priv
, &master_pipes
, &slave_pipes
);
3591 if (slave_pipes
& BIT(crtc
->pipe
)) {
3592 cpu_transcoder
= (enum transcoder
)
3593 get_bigjoiner_master_pipe(crtc
->pipe
, master_pipes
, slave_pipes
);
3594 if (transcoder_ddi_func_is_enabled(dev_priv
, cpu_transcoder
))
3595 enabled_transcoders
|= BIT(cpu_transcoder
);
3598 return enabled_transcoders
;
3601 static bool has_edp_transcoders(u8 enabled_transcoders
)
3603 return enabled_transcoders
& BIT(TRANSCODER_EDP
);
3606 static bool has_dsi_transcoders(u8 enabled_transcoders
)
3608 return enabled_transcoders
& (BIT(TRANSCODER_DSI_0
) |
3609 BIT(TRANSCODER_DSI_1
));
3612 static bool has_pipe_transcoders(u8 enabled_transcoders
)
3614 return enabled_transcoders
& ~(BIT(TRANSCODER_EDP
) |
3615 BIT(TRANSCODER_DSI_0
) |
3616 BIT(TRANSCODER_DSI_1
));
3619 static void assert_enabled_transcoders(struct drm_i915_private
*i915
,
3620 u8 enabled_transcoders
)
3622 /* Only one type of transcoder please */
3623 drm_WARN_ON(&i915
->drm
,
3624 has_edp_transcoders(enabled_transcoders
) +
3625 has_dsi_transcoders(enabled_transcoders
) +
3626 has_pipe_transcoders(enabled_transcoders
) > 1);
3628 /* Only DSI transcoders can be ganged */
3629 drm_WARN_ON(&i915
->drm
,
3630 !has_dsi_transcoders(enabled_transcoders
) &&
3631 !is_power_of_2(enabled_transcoders
));
3634 static bool hsw_get_transcoder_state(struct intel_crtc
*crtc
,
3635 struct intel_crtc_state
*pipe_config
,
3636 struct intel_display_power_domain_set
*power_domain_set
)
3638 struct drm_device
*dev
= crtc
->base
.dev
;
3639 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3640 unsigned long enabled_transcoders
;
3643 enabled_transcoders
= hsw_enabled_transcoders(crtc
);
3644 if (!enabled_transcoders
)
3647 assert_enabled_transcoders(dev_priv
, enabled_transcoders
);
3650 * With the exception of DSI we should only ever have
3651 * a single enabled transcoder. With DSI let's just
3652 * pick the first one.
3654 pipe_config
->cpu_transcoder
= ffs(enabled_transcoders
) - 1;
3656 if (!intel_display_power_get_in_set_if_enabled(dev_priv
, power_domain_set
,
3657 POWER_DOMAIN_TRANSCODER(pipe_config
->cpu_transcoder
)))
3660 if (hsw_panel_transcoders(dev_priv
) & BIT(pipe_config
->cpu_transcoder
)) {
3661 tmp
= intel_de_read(dev_priv
, TRANS_DDI_FUNC_CTL(pipe_config
->cpu_transcoder
));
3663 if ((tmp
& TRANS_DDI_EDP_INPUT_MASK
) == TRANS_DDI_EDP_INPUT_A_ONOFF
)
3664 pipe_config
->pch_pfit
.force_thru
= true;
3667 tmp
= intel_de_read(dev_priv
, TRANSCONF(pipe_config
->cpu_transcoder
));
3669 return tmp
& TRANSCONF_ENABLE
;
3672 static bool bxt_get_dsi_transcoder_state(struct intel_crtc
*crtc
,
3673 struct intel_crtc_state
*pipe_config
,
3674 struct intel_display_power_domain_set
*power_domain_set
)
3676 struct drm_device
*dev
= crtc
->base
.dev
;
3677 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3678 enum transcoder cpu_transcoder
;
3682 for_each_port_masked(port
, BIT(PORT_A
) | BIT(PORT_C
)) {
3684 cpu_transcoder
= TRANSCODER_DSI_A
;
3686 cpu_transcoder
= TRANSCODER_DSI_C
;
3688 if (!intel_display_power_get_in_set_if_enabled(dev_priv
, power_domain_set
,
3689 POWER_DOMAIN_TRANSCODER(cpu_transcoder
)))
3693 * The PLL needs to be enabled with a valid divider
3694 * configuration, otherwise accessing DSI registers will hang
3695 * the machine. See BSpec North Display Engine
3696 * registers/MIPI[BXT]. We can break out here early, since we
3697 * need the same DSI PLL to be enabled for both DSI ports.
3699 if (!bxt_dsi_pll_is_enabled(dev_priv
))
3702 /* XXX: this works for video mode only */
3703 tmp
= intel_de_read(dev_priv
, BXT_MIPI_PORT_CTRL(port
));
3704 if (!(tmp
& DPI_ENABLE
))
3707 tmp
= intel_de_read(dev_priv
, MIPI_CTRL(port
));
3708 if ((tmp
& BXT_PIPE_SELECT_MASK
) != BXT_PIPE_SELECT(crtc
->pipe
))
3711 pipe_config
->cpu_transcoder
= cpu_transcoder
;
3715 return transcoder_is_dsi(pipe_config
->cpu_transcoder
);
3718 static void intel_bigjoiner_get_config(struct intel_crtc_state
*crtc_state
)
3720 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
3721 struct drm_i915_private
*i915
= to_i915(crtc
->base
.dev
);
3722 u8 master_pipes
, slave_pipes
;
3723 enum pipe pipe
= crtc
->pipe
;
3725 enabled_bigjoiner_pipes(i915
, &master_pipes
, &slave_pipes
);
3727 if (((master_pipes
| slave_pipes
) & BIT(pipe
)) == 0)
3730 crtc_state
->bigjoiner_pipes
=
3731 BIT(get_bigjoiner_master_pipe(pipe
, master_pipes
, slave_pipes
)) |
3732 get_bigjoiner_slave_pipes(pipe
, master_pipes
, slave_pipes
);
3735 static bool hsw_get_pipe_config(struct intel_crtc
*crtc
,
3736 struct intel_crtc_state
*pipe_config
)
3738 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
3742 if (!intel_display_power_get_in_set_if_enabled(dev_priv
, &crtc
->hw_readout_power_domains
,
3743 POWER_DOMAIN_PIPE(crtc
->pipe
)))
3746 pipe_config
->shared_dpll
= NULL
;
3748 active
= hsw_get_transcoder_state(crtc
, pipe_config
, &crtc
->hw_readout_power_domains
);
3750 if ((IS_GEMINILAKE(dev_priv
) || IS_BROXTON(dev_priv
)) &&
3751 bxt_get_dsi_transcoder_state(crtc
, pipe_config
, &crtc
->hw_readout_power_domains
)) {
3752 drm_WARN_ON(&dev_priv
->drm
, active
);
3759 intel_bigjoiner_get_config(pipe_config
);
3760 intel_dsc_get_config(pipe_config
);
3762 if (!transcoder_is_dsi(pipe_config
->cpu_transcoder
) ||
3763 DISPLAY_VER(dev_priv
) >= 11)
3764 intel_get_transcoder_timings(crtc
, pipe_config
);
3766 if (HAS_VRR(dev_priv
) && !transcoder_is_dsi(pipe_config
->cpu_transcoder
))
3767 intel_vrr_get_config(pipe_config
);
3769 intel_get_pipe_src_size(crtc
, pipe_config
);
3771 if (IS_HASWELL(dev_priv
)) {
3772 u32 tmp
= intel_de_read(dev_priv
,
3773 TRANSCONF(pipe_config
->cpu_transcoder
));
3775 if (tmp
& TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW
)
3776 pipe_config
->output_format
= INTEL_OUTPUT_FORMAT_YCBCR444
;
3778 pipe_config
->output_format
= INTEL_OUTPUT_FORMAT_RGB
;
3780 pipe_config
->output_format
=
3781 bdw_get_pipe_misc_output_format(crtc
);
3784 pipe_config
->sink_format
= pipe_config
->output_format
;
3786 intel_color_get_config(pipe_config
);
3788 tmp
= intel_de_read(dev_priv
, WM_LINETIME(crtc
->pipe
));
3789 pipe_config
->linetime
= REG_FIELD_GET(HSW_LINETIME_MASK
, tmp
);
3790 if (IS_BROADWELL(dev_priv
) || IS_HASWELL(dev_priv
))
3791 pipe_config
->ips_linetime
=
3792 REG_FIELD_GET(HSW_IPS_LINETIME_MASK
, tmp
);
3794 if (intel_display_power_get_in_set_if_enabled(dev_priv
, &crtc
->hw_readout_power_domains
,
3795 POWER_DOMAIN_PIPE_PANEL_FITTER(crtc
->pipe
))) {
3796 if (DISPLAY_VER(dev_priv
) >= 9)
3797 skl_scaler_get_config(pipe_config
);
3799 ilk_get_pfit_config(pipe_config
);
3802 hsw_ips_get_config(pipe_config
);
3804 if (pipe_config
->cpu_transcoder
!= TRANSCODER_EDP
&&
3805 !transcoder_is_dsi(pipe_config
->cpu_transcoder
)) {
3806 pipe_config
->pixel_multiplier
=
3807 intel_de_read(dev_priv
,
3808 TRANS_MULT(pipe_config
->cpu_transcoder
)) + 1;
3810 pipe_config
->pixel_multiplier
= 1;
3813 if (!transcoder_is_dsi(pipe_config
->cpu_transcoder
)) {
3814 tmp
= intel_de_read(dev_priv
, hsw_chicken_trans_reg(dev_priv
, pipe_config
->cpu_transcoder
));
3816 pipe_config
->framestart_delay
= REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK
, tmp
) + 1;
3818 /* no idea if this is correct */
3819 pipe_config
->framestart_delay
= 1;
3823 intel_display_power_put_all_in_set(dev_priv
, &crtc
->hw_readout_power_domains
);
3828 bool intel_crtc_get_pipe_config(struct intel_crtc_state
*crtc_state
)
3830 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
3831 struct drm_i915_private
*i915
= to_i915(crtc
->base
.dev
);
3833 if (!i915
->display
.funcs
.display
->get_pipe_config(crtc
, crtc_state
))
3836 crtc_state
->hw
.active
= true;
3838 intel_crtc_readout_derived_state(crtc_state
);
3843 int intel_dotclock_calculate(int link_freq
,
3844 const struct intel_link_m_n
*m_n
)
3847 * The calculation for the data clock -> pixel clock is:
3848 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
3849 * But we want to avoid losing precison if possible, so:
3850 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
3852 * and for link freq (10kbs units) -> pixel clock it is:
3853 * link_symbol_clock = link_freq * 10 / link_symbol_size
3854 * pixel_clock = (m * link_symbol_clock) / n
3855 * or for more precision:
3856 * pixel_clock = (m * link_freq * 10) / (n * link_symbol_size)
3862 return DIV_ROUND_UP_ULL(mul_u32_u32(m_n
->link_m
, link_freq
* 10),
3863 m_n
->link_n
* intel_dp_link_symbol_size(link_freq
));
3866 int intel_crtc_dotclock(const struct intel_crtc_state
*pipe_config
)
3870 if (intel_crtc_has_dp_encoder(pipe_config
))
3871 dotclock
= intel_dotclock_calculate(pipe_config
->port_clock
,
3872 &pipe_config
->dp_m_n
);
3873 else if (pipe_config
->has_hdmi_sink
&& pipe_config
->pipe_bpp
> 24)
3874 dotclock
= DIV_ROUND_CLOSEST(pipe_config
->port_clock
* 24,
3875 pipe_config
->pipe_bpp
);
3877 dotclock
= pipe_config
->port_clock
;
3879 if (pipe_config
->output_format
== INTEL_OUTPUT_FORMAT_YCBCR420
&&
3880 !intel_crtc_has_dp_encoder(pipe_config
))
3883 if (pipe_config
->pixel_multiplier
)
3884 dotclock
/= pipe_config
->pixel_multiplier
;
3889 /* Returns the currently programmed mode of the given encoder. */
3890 struct drm_display_mode
*
3891 intel_encoder_current_mode(struct intel_encoder
*encoder
)
3893 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
3894 struct intel_crtc_state
*crtc_state
;
3895 struct drm_display_mode
*mode
;
3896 struct intel_crtc
*crtc
;
3899 if (!encoder
->get_hw_state(encoder
, &pipe
))
3902 crtc
= intel_crtc_for_pipe(dev_priv
, pipe
);
3904 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
3908 crtc_state
= intel_crtc_state_alloc(crtc
);
3914 if (!intel_crtc_get_pipe_config(crtc_state
)) {
3915 intel_crtc_destroy_state(&crtc
->base
, &crtc_state
->uapi
);
3920 intel_encoder_get_config(encoder
, crtc_state
);
3922 intel_mode_from_crtc_timings(mode
, &crtc_state
->hw
.adjusted_mode
);
3924 intel_crtc_destroy_state(&crtc
->base
, &crtc_state
->uapi
);
3929 static bool encoders_cloneable(const struct intel_encoder
*a
,
3930 const struct intel_encoder
*b
)
3932 /* masks could be asymmetric, so check both ways */
3933 return a
== b
|| (a
->cloneable
& BIT(b
->type
) &&
3934 b
->cloneable
& BIT(a
->type
));
3937 static bool check_single_encoder_cloning(struct intel_atomic_state
*state
,
3938 struct intel_crtc
*crtc
,
3939 struct intel_encoder
*encoder
)
3941 struct intel_encoder
*source_encoder
;
3942 struct drm_connector
*connector
;
3943 struct drm_connector_state
*connector_state
;
3946 for_each_new_connector_in_state(&state
->base
, connector
, connector_state
, i
) {
3947 if (connector_state
->crtc
!= &crtc
->base
)
3951 to_intel_encoder(connector_state
->best_encoder
);
3952 if (!encoders_cloneable(encoder
, source_encoder
))
3959 static int icl_add_linked_planes(struct intel_atomic_state
*state
)
3961 struct intel_plane
*plane
, *linked
;
3962 struct intel_plane_state
*plane_state
, *linked_plane_state
;
3965 for_each_new_intel_plane_in_state(state
, plane
, plane_state
, i
) {
3966 linked
= plane_state
->planar_linked_plane
;
3971 linked_plane_state
= intel_atomic_get_plane_state(state
, linked
);
3972 if (IS_ERR(linked_plane_state
))
3973 return PTR_ERR(linked_plane_state
);
3975 drm_WARN_ON(state
->base
.dev
,
3976 linked_plane_state
->planar_linked_plane
!= plane
);
3977 drm_WARN_ON(state
->base
.dev
,
3978 linked_plane_state
->planar_slave
== plane_state
->planar_slave
);
3984 static int icl_check_nv12_planes(struct intel_crtc_state
*crtc_state
)
3986 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
3987 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
3988 struct intel_atomic_state
*state
= to_intel_atomic_state(crtc_state
->uapi
.state
);
3989 struct intel_plane
*plane
, *linked
;
3990 struct intel_plane_state
*plane_state
;
3993 if (DISPLAY_VER(dev_priv
) < 11)
3997 * Destroy all old plane links and make the slave plane invisible
3998 * in the crtc_state->active_planes mask.
4000 for_each_new_intel_plane_in_state(state
, plane
, plane_state
, i
) {
4001 if (plane
->pipe
!= crtc
->pipe
|| !plane_state
->planar_linked_plane
)
4004 plane_state
->planar_linked_plane
= NULL
;
4005 if (plane_state
->planar_slave
&& !plane_state
->uapi
.visible
) {
4006 crtc_state
->enabled_planes
&= ~BIT(plane
->id
);
4007 crtc_state
->active_planes
&= ~BIT(plane
->id
);
4008 crtc_state
->update_planes
|= BIT(plane
->id
);
4009 crtc_state
->data_rate
[plane
->id
] = 0;
4010 crtc_state
->rel_data_rate
[plane
->id
] = 0;
4013 plane_state
->planar_slave
= false;
4016 if (!crtc_state
->nv12_planes
)
4019 for_each_new_intel_plane_in_state(state
, plane
, plane_state
, i
) {
4020 struct intel_plane_state
*linked_state
= NULL
;
4022 if (plane
->pipe
!= crtc
->pipe
||
4023 !(crtc_state
->nv12_planes
& BIT(plane
->id
)))
4026 for_each_intel_plane_on_crtc(&dev_priv
->drm
, crtc
, linked
) {
4027 if (!icl_is_nv12_y_plane(dev_priv
, linked
->id
))
4030 if (crtc_state
->active_planes
& BIT(linked
->id
))
4033 linked_state
= intel_atomic_get_plane_state(state
, linked
);
4034 if (IS_ERR(linked_state
))
4035 return PTR_ERR(linked_state
);
4040 if (!linked_state
) {
4041 drm_dbg_kms(&dev_priv
->drm
,
4042 "Need %d free Y planes for planar YUV\n",
4043 hweight8(crtc_state
->nv12_planes
));
4048 plane_state
->planar_linked_plane
= linked
;
4050 linked_state
->planar_slave
= true;
4051 linked_state
->planar_linked_plane
= plane
;
4052 crtc_state
->enabled_planes
|= BIT(linked
->id
);
4053 crtc_state
->active_planes
|= BIT(linked
->id
);
4054 crtc_state
->update_planes
|= BIT(linked
->id
);
4055 crtc_state
->data_rate
[linked
->id
] =
4056 crtc_state
->data_rate_y
[plane
->id
];
4057 crtc_state
->rel_data_rate
[linked
->id
] =
4058 crtc_state
->rel_data_rate_y
[plane
->id
];
4059 drm_dbg_kms(&dev_priv
->drm
, "Using %s as Y plane for %s\n",
4060 linked
->base
.name
, plane
->base
.name
);
4062 /* Copy parameters to slave plane */
4063 linked_state
->ctl
= plane_state
->ctl
| PLANE_CTL_YUV420_Y_PLANE
;
4064 linked_state
->color_ctl
= plane_state
->color_ctl
;
4065 linked_state
->view
= plane_state
->view
;
4066 linked_state
->decrypt
= plane_state
->decrypt
;
4068 intel_plane_copy_hw_state(linked_state
, plane_state
);
4069 linked_state
->uapi
.src
= plane_state
->uapi
.src
;
4070 linked_state
->uapi
.dst
= plane_state
->uapi
.dst
;
4072 if (icl_is_hdr_plane(dev_priv
, plane
->id
)) {
4073 if (linked
->id
== PLANE_SPRITE5
)
4074 plane_state
->cus_ctl
|= PLANE_CUS_Y_PLANE_7_ICL
;
4075 else if (linked
->id
== PLANE_SPRITE4
)
4076 plane_state
->cus_ctl
|= PLANE_CUS_Y_PLANE_6_ICL
;
4077 else if (linked
->id
== PLANE_SPRITE3
)
4078 plane_state
->cus_ctl
|= PLANE_CUS_Y_PLANE_5_RKL
;
4079 else if (linked
->id
== PLANE_SPRITE2
)
4080 plane_state
->cus_ctl
|= PLANE_CUS_Y_PLANE_4_RKL
;
4082 MISSING_CASE(linked
->id
);
4089 static bool c8_planes_changed(const struct intel_crtc_state
*new_crtc_state
)
4091 struct intel_crtc
*crtc
= to_intel_crtc(new_crtc_state
->uapi
.crtc
);
4092 struct intel_atomic_state
*state
=
4093 to_intel_atomic_state(new_crtc_state
->uapi
.state
);
4094 const struct intel_crtc_state
*old_crtc_state
=
4095 intel_atomic_get_old_crtc_state(state
, crtc
);
4097 return !old_crtc_state
->c8_planes
!= !new_crtc_state
->c8_planes
;
4100 static u16
hsw_linetime_wm(const struct intel_crtc_state
*crtc_state
)
4102 const struct drm_display_mode
*pipe_mode
=
4103 &crtc_state
->hw
.pipe_mode
;
4106 if (!crtc_state
->hw
.enable
)
4109 linetime_wm
= DIV_ROUND_CLOSEST(pipe_mode
->crtc_htotal
* 1000 * 8,
4110 pipe_mode
->crtc_clock
);
4112 return min(linetime_wm
, 0x1ff);
4115 static u16
hsw_ips_linetime_wm(const struct intel_crtc_state
*crtc_state
,
4116 const struct intel_cdclk_state
*cdclk_state
)
4118 const struct drm_display_mode
*pipe_mode
=
4119 &crtc_state
->hw
.pipe_mode
;
4122 if (!crtc_state
->hw
.enable
)
4125 linetime_wm
= DIV_ROUND_CLOSEST(pipe_mode
->crtc_htotal
* 1000 * 8,
4126 cdclk_state
->logical
.cdclk
);
4128 return min(linetime_wm
, 0x1ff);
4131 static u16
skl_linetime_wm(const struct intel_crtc_state
*crtc_state
)
4133 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
4134 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
4135 const struct drm_display_mode
*pipe_mode
=
4136 &crtc_state
->hw
.pipe_mode
;
4139 if (!crtc_state
->hw
.enable
)
4142 linetime_wm
= DIV_ROUND_UP(pipe_mode
->crtc_htotal
* 1000 * 8,
4143 crtc_state
->pixel_rate
);
4145 /* Display WA #1135: BXT:ALL GLK:ALL */
4146 if ((IS_GEMINILAKE(dev_priv
) || IS_BROXTON(dev_priv
)) &&
4147 skl_watermark_ipc_enabled(dev_priv
))
4150 return min(linetime_wm
, 0x1ff);
4153 static int hsw_compute_linetime_wm(struct intel_atomic_state
*state
,
4154 struct intel_crtc
*crtc
)
4156 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
4157 struct intel_crtc_state
*crtc_state
=
4158 intel_atomic_get_new_crtc_state(state
, crtc
);
4159 const struct intel_cdclk_state
*cdclk_state
;
4161 if (DISPLAY_VER(dev_priv
) >= 9)
4162 crtc_state
->linetime
= skl_linetime_wm(crtc_state
);
4164 crtc_state
->linetime
= hsw_linetime_wm(crtc_state
);
4166 if (!hsw_crtc_supports_ips(crtc
))
4169 cdclk_state
= intel_atomic_get_cdclk_state(state
);
4170 if (IS_ERR(cdclk_state
))
4171 return PTR_ERR(cdclk_state
);
4173 crtc_state
->ips_linetime
= hsw_ips_linetime_wm(crtc_state
,
4179 static int intel_crtc_atomic_check(struct intel_atomic_state
*state
,
4180 struct intel_crtc
*crtc
)
4182 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
4183 struct intel_crtc_state
*crtc_state
=
4184 intel_atomic_get_new_crtc_state(state
, crtc
);
4187 if (DISPLAY_VER(dev_priv
) < 5 && !IS_G4X(dev_priv
) &&
4188 intel_crtc_needs_modeset(crtc_state
) &&
4189 !crtc_state
->hw
.active
)
4190 crtc_state
->update_wm_post
= true;
4192 if (intel_crtc_needs_modeset(crtc_state
)) {
4193 ret
= intel_dpll_crtc_get_shared_dpll(state
, crtc
);
4199 * May need to update pipe gamma enable bits
4200 * when C8 planes are getting enabled/disabled.
4202 if (c8_planes_changed(crtc_state
))
4203 crtc_state
->uapi
.color_mgmt_changed
= true;
4205 if (intel_crtc_needs_color_update(crtc_state
)) {
4206 ret
= intel_color_check(crtc_state
);
4211 ret
= intel_compute_pipe_wm(state
, crtc
);
4213 drm_dbg_kms(&dev_priv
->drm
,
4214 "Target pipe watermarks are invalid\n");
4219 * Calculate 'intermediate' watermarks that satisfy both the
4220 * old state and the new state. We can program these
4223 ret
= intel_compute_intermediate_wm(state
, crtc
);
4225 drm_dbg_kms(&dev_priv
->drm
,
4226 "No valid intermediate pipe watermarks are possible\n");
4230 if (DISPLAY_VER(dev_priv
) >= 9) {
4231 if (intel_crtc_needs_modeset(crtc_state
) ||
4232 intel_crtc_needs_fastset(crtc_state
)) {
4233 ret
= skl_update_scaler_crtc(crtc_state
);
4238 ret
= intel_atomic_setup_scalers(dev_priv
, crtc
, crtc_state
);
4243 if (HAS_IPS(dev_priv
)) {
4244 ret
= hsw_ips_compute_config(state
, crtc
);
4249 if (DISPLAY_VER(dev_priv
) >= 9 ||
4250 IS_BROADWELL(dev_priv
) || IS_HASWELL(dev_priv
)) {
4251 ret
= hsw_compute_linetime_wm(state
, crtc
);
4257 ret
= intel_psr2_sel_fetch_update(state
, crtc
);
4265 compute_sink_pipe_bpp(const struct drm_connector_state
*conn_state
,
4266 struct intel_crtc_state
*crtc_state
)
4268 struct drm_connector
*connector
= conn_state
->connector
;
4269 struct drm_i915_private
*i915
= to_i915(crtc_state
->uapi
.crtc
->dev
);
4270 const struct drm_display_info
*info
= &connector
->display_info
;
4273 switch (conn_state
->max_bpc
) {
4287 MISSING_CASE(conn_state
->max_bpc
);
4291 if (bpp
< crtc_state
->pipe_bpp
) {
4292 drm_dbg_kms(&i915
->drm
,
4293 "[CONNECTOR:%d:%s] Limiting display bpp to %d "
4294 "(EDID bpp %d, max requested bpp %d, max platform bpp %d)\n",
4295 connector
->base
.id
, connector
->name
,
4297 3 * conn_state
->max_requested_bpc
,
4298 crtc_state
->pipe_bpp
);
4300 crtc_state
->pipe_bpp
= bpp
;
4307 compute_baseline_pipe_bpp(struct intel_atomic_state
*state
,
4308 struct intel_crtc
*crtc
)
4310 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
4311 struct intel_crtc_state
*crtc_state
=
4312 intel_atomic_get_new_crtc_state(state
, crtc
);
4313 struct drm_connector
*connector
;
4314 struct drm_connector_state
*connector_state
;
4317 if ((IS_G4X(dev_priv
) || IS_VALLEYVIEW(dev_priv
) ||
4318 IS_CHERRYVIEW(dev_priv
)))
4320 else if (DISPLAY_VER(dev_priv
) >= 5)
4325 crtc_state
->pipe_bpp
= bpp
;
4327 /* Clamp display bpp to connector max bpp */
4328 for_each_new_connector_in_state(&state
->base
, connector
, connector_state
, i
) {
4331 if (connector_state
->crtc
!= &crtc
->base
)
4334 ret
= compute_sink_pipe_bpp(connector_state
, crtc_state
);
4342 static bool check_digital_port_conflicts(struct intel_atomic_state
*state
)
4344 struct drm_device
*dev
= state
->base
.dev
;
4345 struct drm_connector
*connector
;
4346 struct drm_connector_list_iter conn_iter
;
4347 unsigned int used_ports
= 0;
4348 unsigned int used_mst_ports
= 0;
4352 * We're going to peek into connector->state,
4353 * hence connection_mutex must be held.
4355 drm_modeset_lock_assert_held(&dev
->mode_config
.connection_mutex
);
4358 * Walk the connector list instead of the encoder
4359 * list to detect the problem on ddi platforms
4360 * where there's just one encoder per digital port.
4362 drm_connector_list_iter_begin(dev
, &conn_iter
);
4363 drm_for_each_connector_iter(connector
, &conn_iter
) {
4364 struct drm_connector_state
*connector_state
;
4365 struct intel_encoder
*encoder
;
4368 drm_atomic_get_new_connector_state(&state
->base
,
4370 if (!connector_state
)
4371 connector_state
= connector
->state
;
4373 if (!connector_state
->best_encoder
)
4376 encoder
= to_intel_encoder(connector_state
->best_encoder
);
4378 drm_WARN_ON(dev
, !connector_state
->crtc
);
4380 switch (encoder
->type
) {
4381 case INTEL_OUTPUT_DDI
:
4382 if (drm_WARN_ON(dev
, !HAS_DDI(to_i915(dev
))))
4385 case INTEL_OUTPUT_DP
:
4386 case INTEL_OUTPUT_HDMI
:
4387 case INTEL_OUTPUT_EDP
:
4388 /* the same port mustn't appear more than once */
4389 if (used_ports
& BIT(encoder
->port
))
4392 used_ports
|= BIT(encoder
->port
);
4394 case INTEL_OUTPUT_DP_MST
:
4402 drm_connector_list_iter_end(&conn_iter
);
4404 /* can't mix MST and SST/HDMI on the same port */
4405 if (used_ports
& used_mst_ports
)
4412 intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_atomic_state
*state
,
4413 struct intel_crtc
*crtc
)
4415 struct intel_crtc_state
*crtc_state
=
4416 intel_atomic_get_new_crtc_state(state
, crtc
);
4418 WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state
));
4420 drm_property_replace_blob(&crtc_state
->hw
.degamma_lut
,
4421 crtc_state
->uapi
.degamma_lut
);
4422 drm_property_replace_blob(&crtc_state
->hw
.gamma_lut
,
4423 crtc_state
->uapi
.gamma_lut
);
4424 drm_property_replace_blob(&crtc_state
->hw
.ctm
,
4425 crtc_state
->uapi
.ctm
);
4429 intel_crtc_copy_uapi_to_hw_state_modeset(struct intel_atomic_state
*state
,
4430 struct intel_crtc
*crtc
)
4432 struct intel_crtc_state
*crtc_state
=
4433 intel_atomic_get_new_crtc_state(state
, crtc
);
4435 WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state
));
4437 crtc_state
->hw
.enable
= crtc_state
->uapi
.enable
;
4438 crtc_state
->hw
.active
= crtc_state
->uapi
.active
;
4439 drm_mode_copy(&crtc_state
->hw
.mode
,
4440 &crtc_state
->uapi
.mode
);
4441 drm_mode_copy(&crtc_state
->hw
.adjusted_mode
,
4442 &crtc_state
->uapi
.adjusted_mode
);
4443 crtc_state
->hw
.scaling_filter
= crtc_state
->uapi
.scaling_filter
;
4445 intel_crtc_copy_uapi_to_hw_state_nomodeset(state
, crtc
);
4449 copy_bigjoiner_crtc_state_nomodeset(struct intel_atomic_state
*state
,
4450 struct intel_crtc
*slave_crtc
)
4452 struct intel_crtc_state
*slave_crtc_state
=
4453 intel_atomic_get_new_crtc_state(state
, slave_crtc
);
4454 struct intel_crtc
*master_crtc
= intel_master_crtc(slave_crtc_state
);
4455 const struct intel_crtc_state
*master_crtc_state
=
4456 intel_atomic_get_new_crtc_state(state
, master_crtc
);
4458 drm_property_replace_blob(&slave_crtc_state
->hw
.degamma_lut
,
4459 master_crtc_state
->hw
.degamma_lut
);
4460 drm_property_replace_blob(&slave_crtc_state
->hw
.gamma_lut
,
4461 master_crtc_state
->hw
.gamma_lut
);
4462 drm_property_replace_blob(&slave_crtc_state
->hw
.ctm
,
4463 master_crtc_state
->hw
.ctm
);
4465 slave_crtc_state
->uapi
.color_mgmt_changed
= master_crtc_state
->uapi
.color_mgmt_changed
;
4469 copy_bigjoiner_crtc_state_modeset(struct intel_atomic_state
*state
,
4470 struct intel_crtc
*slave_crtc
)
4472 struct intel_crtc_state
*slave_crtc_state
=
4473 intel_atomic_get_new_crtc_state(state
, slave_crtc
);
4474 struct intel_crtc
*master_crtc
= intel_master_crtc(slave_crtc_state
);
4475 const struct intel_crtc_state
*master_crtc_state
=
4476 intel_atomic_get_new_crtc_state(state
, master_crtc
);
4477 struct intel_crtc_state
*saved_state
;
4479 WARN_ON(master_crtc_state
->bigjoiner_pipes
!=
4480 slave_crtc_state
->bigjoiner_pipes
);
4482 saved_state
= kmemdup(master_crtc_state
, sizeof(*saved_state
), GFP_KERNEL
);
4486 /* preserve some things from the slave's original crtc state */
4487 saved_state
->uapi
= slave_crtc_state
->uapi
;
4488 saved_state
->scaler_state
= slave_crtc_state
->scaler_state
;
4489 saved_state
->shared_dpll
= slave_crtc_state
->shared_dpll
;
4490 saved_state
->crc_enabled
= slave_crtc_state
->crc_enabled
;
4492 intel_crtc_free_hw_state(slave_crtc_state
);
4493 memcpy(slave_crtc_state
, saved_state
, sizeof(*slave_crtc_state
));
4496 /* Re-init hw state */
4497 memset(&slave_crtc_state
->hw
, 0, sizeof(slave_crtc_state
->hw
));
4498 slave_crtc_state
->hw
.enable
= master_crtc_state
->hw
.enable
;
4499 slave_crtc_state
->hw
.active
= master_crtc_state
->hw
.active
;
4500 drm_mode_copy(&slave_crtc_state
->hw
.mode
,
4501 &master_crtc_state
->hw
.mode
);
4502 drm_mode_copy(&slave_crtc_state
->hw
.pipe_mode
,
4503 &master_crtc_state
->hw
.pipe_mode
);
4504 drm_mode_copy(&slave_crtc_state
->hw
.adjusted_mode
,
4505 &master_crtc_state
->hw
.adjusted_mode
);
4506 slave_crtc_state
->hw
.scaling_filter
= master_crtc_state
->hw
.scaling_filter
;
4508 copy_bigjoiner_crtc_state_nomodeset(state
, slave_crtc
);
4510 slave_crtc_state
->uapi
.mode_changed
= master_crtc_state
->uapi
.mode_changed
;
4511 slave_crtc_state
->uapi
.connectors_changed
= master_crtc_state
->uapi
.connectors_changed
;
4512 slave_crtc_state
->uapi
.active_changed
= master_crtc_state
->uapi
.active_changed
;
4514 WARN_ON(master_crtc_state
->bigjoiner_pipes
!=
4515 slave_crtc_state
->bigjoiner_pipes
);
4521 intel_crtc_prepare_cleared_state(struct intel_atomic_state
*state
,
4522 struct intel_crtc
*crtc
)
4524 struct intel_crtc_state
*crtc_state
=
4525 intel_atomic_get_new_crtc_state(state
, crtc
);
4526 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
4527 struct intel_crtc_state
*saved_state
;
4529 saved_state
= intel_crtc_state_alloc(crtc
);
4533 /* free the old crtc_state->hw members */
4534 intel_crtc_free_hw_state(crtc_state
);
4536 /* FIXME: before the switch to atomic started, a new pipe_config was
4537 * kzalloc'd. Code that depends on any field being zero should be
4538 * fixed, so that the crtc_state can be safely duplicated. For now,
4539 * only fields that are know to not cause problems are preserved. */
4541 saved_state
->uapi
= crtc_state
->uapi
;
4542 saved_state
->inherited
= crtc_state
->inherited
;
4543 saved_state
->scaler_state
= crtc_state
->scaler_state
;
4544 saved_state
->shared_dpll
= crtc_state
->shared_dpll
;
4545 saved_state
->dpll_hw_state
= crtc_state
->dpll_hw_state
;
4546 memcpy(saved_state
->icl_port_dplls
, crtc_state
->icl_port_dplls
,
4547 sizeof(saved_state
->icl_port_dplls
));
4548 saved_state
->crc_enabled
= crtc_state
->crc_enabled
;
4549 if (IS_G4X(dev_priv
) ||
4550 IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
4551 saved_state
->wm
= crtc_state
->wm
;
4553 memcpy(crtc_state
, saved_state
, sizeof(*crtc_state
));
4556 intel_crtc_copy_uapi_to_hw_state_modeset(state
, crtc
);
4562 intel_modeset_pipe_config(struct intel_atomic_state
*state
,
4563 struct intel_crtc
*crtc
,
4564 const struct intel_link_bw_limits
*limits
)
4566 struct drm_i915_private
*i915
= to_i915(crtc
->base
.dev
);
4567 struct intel_crtc_state
*crtc_state
=
4568 intel_atomic_get_new_crtc_state(state
, crtc
);
4569 struct drm_connector
*connector
;
4570 struct drm_connector_state
*connector_state
;
4571 int pipe_src_w
, pipe_src_h
;
4572 int base_bpp
, ret
, i
;
4574 crtc_state
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
4576 crtc_state
->framestart_delay
= 1;
4579 * Sanitize sync polarity flags based on requested ones. If neither
4580 * positive or negative polarity is requested, treat this as meaning
4581 * negative polarity.
4583 if (!(crtc_state
->hw
.adjusted_mode
.flags
&
4584 (DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NHSYNC
)))
4585 crtc_state
->hw
.adjusted_mode
.flags
|= DRM_MODE_FLAG_NHSYNC
;
4587 if (!(crtc_state
->hw
.adjusted_mode
.flags
&
4588 (DRM_MODE_FLAG_PVSYNC
| DRM_MODE_FLAG_NVSYNC
)))
4589 crtc_state
->hw
.adjusted_mode
.flags
|= DRM_MODE_FLAG_NVSYNC
;
4591 ret
= compute_baseline_pipe_bpp(state
, crtc
);
4595 crtc_state
->fec_enable
= limits
->force_fec_pipes
& BIT(crtc
->pipe
);
4596 crtc_state
->max_link_bpp_x16
= limits
->max_bpp_x16
[crtc
->pipe
];
4598 if (crtc_state
->pipe_bpp
> to_bpp_int(crtc_state
->max_link_bpp_x16
)) {
4599 drm_dbg_kms(&i915
->drm
,
4600 "[CRTC:%d:%s] Link bpp limited to " BPP_X16_FMT
"\n",
4601 crtc
->base
.base
.id
, crtc
->base
.name
,
4602 BPP_X16_ARGS(crtc_state
->max_link_bpp_x16
));
4603 crtc_state
->bw_constrained
= true;
4606 base_bpp
= crtc_state
->pipe_bpp
;
4609 * Determine the real pipe dimensions. Note that stereo modes can
4610 * increase the actual pipe size due to the frame doubling and
4611 * insertion of additional space for blanks between the frame. This
4612 * is stored in the crtc timings. We use the requested mode to do this
4613 * computation to clearly distinguish it from the adjusted mode, which
4614 * can be changed by the connectors in the below retry loop.
4616 drm_mode_get_hv_timing(&crtc_state
->hw
.mode
,
4617 &pipe_src_w
, &pipe_src_h
);
4618 drm_rect_init(&crtc_state
->pipe_src
, 0, 0,
4619 pipe_src_w
, pipe_src_h
);
4621 for_each_new_connector_in_state(&state
->base
, connector
, connector_state
, i
) {
4622 struct intel_encoder
*encoder
=
4623 to_intel_encoder(connector_state
->best_encoder
);
4625 if (connector_state
->crtc
!= &crtc
->base
)
4628 if (!check_single_encoder_cloning(state
, crtc
, encoder
)) {
4629 drm_dbg_kms(&i915
->drm
,
4630 "[ENCODER:%d:%s] rejecting invalid cloning configuration\n",
4631 encoder
->base
.base
.id
, encoder
->base
.name
);
4636 * Determine output_types before calling the .compute_config()
4637 * hooks so that the hooks can use this information safely.
4639 if (encoder
->compute_output_type
)
4640 crtc_state
->output_types
|=
4641 BIT(encoder
->compute_output_type(encoder
, crtc_state
,
4644 crtc_state
->output_types
|= BIT(encoder
->type
);
4647 /* Ensure the port clock defaults are reset when retrying. */
4648 crtc_state
->port_clock
= 0;
4649 crtc_state
->pixel_multiplier
= 1;
4651 /* Fill in default crtc timings, allow encoders to overwrite them. */
4652 drm_mode_set_crtcinfo(&crtc_state
->hw
.adjusted_mode
,
4653 CRTC_STEREO_DOUBLE
);
4655 /* Pass our mode to the connectors and the CRTC to give them a chance to
4656 * adjust it according to limitations or connector properties, and also
4657 * a chance to reject the mode entirely.
4659 for_each_new_connector_in_state(&state
->base
, connector
, connector_state
, i
) {
4660 struct intel_encoder
*encoder
=
4661 to_intel_encoder(connector_state
->best_encoder
);
4663 if (connector_state
->crtc
!= &crtc
->base
)
4666 ret
= encoder
->compute_config(encoder
, crtc_state
,
4668 if (ret
== -EDEADLK
)
4671 drm_dbg_kms(&i915
->drm
, "[ENCODER:%d:%s] config failure: %d\n",
4672 encoder
->base
.base
.id
, encoder
->base
.name
, ret
);
4677 /* Set default port clock if not overwritten by the encoder. Needs to be
4678 * done afterwards in case the encoder adjusts the mode. */
4679 if (!crtc_state
->port_clock
)
4680 crtc_state
->port_clock
= crtc_state
->hw
.adjusted_mode
.crtc_clock
4681 * crtc_state
->pixel_multiplier
;
4683 ret
= intel_crtc_compute_config(state
, crtc
);
4684 if (ret
== -EDEADLK
)
4687 drm_dbg_kms(&i915
->drm
, "[CRTC:%d:%s] config failure: %d\n",
4688 crtc
->base
.base
.id
, crtc
->base
.name
, ret
);
4692 /* Dithering seems to not pass-through bits correctly when it should, so
4693 * only enable it on 6bpc panels and when its not a compliance
4694 * test requesting 6bpc video pattern.
4696 crtc_state
->dither
= (crtc_state
->pipe_bpp
== 6*3) &&
4697 !crtc_state
->dither_force_disable
;
4698 drm_dbg_kms(&i915
->drm
,
4699 "[CRTC:%d:%s] hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
4700 crtc
->base
.base
.id
, crtc
->base
.name
,
4701 base_bpp
, crtc_state
->pipe_bpp
, crtc_state
->dither
);
4707 intel_modeset_pipe_config_late(struct intel_atomic_state
*state
,
4708 struct intel_crtc
*crtc
)
4710 struct intel_crtc_state
*crtc_state
=
4711 intel_atomic_get_new_crtc_state(state
, crtc
);
4712 struct drm_connector_state
*conn_state
;
4713 struct drm_connector
*connector
;
4716 intel_bigjoiner_adjust_pipe_src(crtc_state
);
4718 for_each_new_connector_in_state(&state
->base
, connector
,
4720 struct intel_encoder
*encoder
=
4721 to_intel_encoder(conn_state
->best_encoder
);
4724 if (conn_state
->crtc
!= &crtc
->base
||
4725 !encoder
->compute_config_late
)
4728 ret
= encoder
->compute_config_late(encoder
, crtc_state
,
4737 bool intel_fuzzy_clock_check(int clock1
, int clock2
)
4741 if (clock1
== clock2
)
4744 if (!clock1
|| !clock2
)
4747 diff
= abs(clock1
- clock2
);
4749 if (((((diff
+ clock1
+ clock2
) * 100)) / (clock1
+ clock2
)) < 105)
4756 intel_compare_link_m_n(const struct intel_link_m_n
*m_n
,
4757 const struct intel_link_m_n
*m2_n2
)
4759 return m_n
->tu
== m2_n2
->tu
&&
4760 m_n
->data_m
== m2_n2
->data_m
&&
4761 m_n
->data_n
== m2_n2
->data_n
&&
4762 m_n
->link_m
== m2_n2
->link_m
&&
4763 m_n
->link_n
== m2_n2
->link_n
;
4767 intel_compare_infoframe(const union hdmi_infoframe
*a
,
4768 const union hdmi_infoframe
*b
)
4770 return memcmp(a
, b
, sizeof(*a
)) == 0;
4774 intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp
*a
,
4775 const struct drm_dp_vsc_sdp
*b
)
4777 return a
->pixelformat
== b
->pixelformat
&&
4778 a
->colorimetry
== b
->colorimetry
&&
4780 a
->dynamic_range
== b
->dynamic_range
&&
4781 a
->content_type
== b
->content_type
;
4785 intel_compare_buffer(const u8
*a
, const u8
*b
, size_t len
)
4787 return memcmp(a
, b
, len
) == 0;
4791 pipe_config_infoframe_mismatch(struct drm_i915_private
*dev_priv
,
4792 bool fastset
, const char *name
,
4793 const union hdmi_infoframe
*a
,
4794 const union hdmi_infoframe
*b
)
4797 if (!drm_debug_enabled(DRM_UT_KMS
))
4800 drm_dbg_kms(&dev_priv
->drm
,
4801 "fastset requirement not met in %s infoframe\n", name
);
4802 drm_dbg_kms(&dev_priv
->drm
, "expected:\n");
4803 hdmi_infoframe_log(KERN_DEBUG
, dev_priv
->drm
.dev
, a
);
4804 drm_dbg_kms(&dev_priv
->drm
, "found:\n");
4805 hdmi_infoframe_log(KERN_DEBUG
, dev_priv
->drm
.dev
, b
);
4807 drm_err(&dev_priv
->drm
, "mismatch in %s infoframe\n", name
);
4808 drm_err(&dev_priv
->drm
, "expected:\n");
4809 hdmi_infoframe_log(KERN_ERR
, dev_priv
->drm
.dev
, a
);
4810 drm_err(&dev_priv
->drm
, "found:\n");
4811 hdmi_infoframe_log(KERN_ERR
, dev_priv
->drm
.dev
, b
);
4816 pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private
*dev_priv
,
4817 bool fastset
, const char *name
,
4818 const struct drm_dp_vsc_sdp
*a
,
4819 const struct drm_dp_vsc_sdp
*b
)
4822 if (!drm_debug_enabled(DRM_UT_KMS
))
4825 drm_dbg_kms(&dev_priv
->drm
,
4826 "fastset requirement not met in %s dp sdp\n", name
);
4827 drm_dbg_kms(&dev_priv
->drm
, "expected:\n");
4828 drm_dp_vsc_sdp_log(KERN_DEBUG
, dev_priv
->drm
.dev
, a
);
4829 drm_dbg_kms(&dev_priv
->drm
, "found:\n");
4830 drm_dp_vsc_sdp_log(KERN_DEBUG
, dev_priv
->drm
.dev
, b
);
4832 drm_err(&dev_priv
->drm
, "mismatch in %s dp sdp\n", name
);
4833 drm_err(&dev_priv
->drm
, "expected:\n");
4834 drm_dp_vsc_sdp_log(KERN_ERR
, dev_priv
->drm
.dev
, a
);
4835 drm_err(&dev_priv
->drm
, "found:\n");
4836 drm_dp_vsc_sdp_log(KERN_ERR
, dev_priv
->drm
.dev
, b
);
4840 /* Returns the length up to and including the last differing byte */
4842 memcmp_diff_len(const u8
*a
, const u8
*b
, size_t len
)
4846 for (i
= len
- 1; i
>= 0; i
--) {
4855 pipe_config_buffer_mismatch(bool fastset
, const struct intel_crtc
*crtc
,
4857 const u8
*a
, const u8
*b
, size_t len
)
4859 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
4862 if (!drm_debug_enabled(DRM_UT_KMS
))
4865 /* only dump up to the last difference */
4866 len
= memcmp_diff_len(a
, b
, len
);
4868 drm_dbg_kms(&dev_priv
->drm
,
4869 "[CRTC:%d:%s] fastset requirement not met in %s buffer\n",
4870 crtc
->base
.base
.id
, crtc
->base
.name
, name
);
4871 print_hex_dump(KERN_DEBUG
, "expected: ", DUMP_PREFIX_NONE
,
4872 16, 0, a
, len
, false);
4873 print_hex_dump(KERN_DEBUG
, "found: ", DUMP_PREFIX_NONE
,
4874 16, 0, b
, len
, false);
4876 /* only dump up to the last difference */
4877 len
= memcmp_diff_len(a
, b
, len
);
4879 drm_err(&dev_priv
->drm
, "[CRTC:%d:%s] mismatch in %s buffer\n",
4880 crtc
->base
.base
.id
, crtc
->base
.name
, name
);
4881 print_hex_dump(KERN_ERR
, "expected: ", DUMP_PREFIX_NONE
,
4882 16, 0, a
, len
, false);
4883 print_hex_dump(KERN_ERR
, "found: ", DUMP_PREFIX_NONE
,
4884 16, 0, b
, len
, false);
4888 static void __printf(4, 5)
4889 pipe_config_mismatch(bool fastset
, const struct intel_crtc
*crtc
,
4890 const char *name
, const char *format
, ...)
4892 struct drm_i915_private
*i915
= to_i915(crtc
->base
.dev
);
4893 struct va_format vaf
;
4896 va_start(args
, format
);
4901 drm_dbg_kms(&i915
->drm
,
4902 "[CRTC:%d:%s] fastset requirement not met in %s %pV\n",
4903 crtc
->base
.base
.id
, crtc
->base
.name
, name
, &vaf
);
4905 drm_err(&i915
->drm
, "[CRTC:%d:%s] mismatch in %s %pV\n",
4906 crtc
->base
.base
.id
, crtc
->base
.name
, name
, &vaf
);
4912 pipe_config_pll_mismatch(bool fastset
,
4913 const struct intel_crtc
*crtc
,
4915 const struct intel_dpll_hw_state
*a
,
4916 const struct intel_dpll_hw_state
*b
)
4918 struct drm_i915_private
*i915
= to_i915(crtc
->base
.dev
);
4921 if (!drm_debug_enabled(DRM_UT_KMS
))
4924 drm_dbg_kms(&i915
->drm
,
4925 "[CRTC:%d:%s] fastset requirement not met in %s\n",
4926 crtc
->base
.base
.id
, crtc
->base
.name
, name
);
4927 drm_dbg_kms(&i915
->drm
, "expected:\n");
4928 intel_dpll_dump_hw_state(i915
, a
);
4929 drm_dbg_kms(&i915
->drm
, "found:\n");
4930 intel_dpll_dump_hw_state(i915
, b
);
4932 drm_err(&i915
->drm
, "[CRTC:%d:%s] mismatch in %s buffer\n",
4933 crtc
->base
.base
.id
, crtc
->base
.name
, name
);
4934 drm_err(&i915
->drm
, "expected:\n");
4935 intel_dpll_dump_hw_state(i915
, a
);
4936 drm_err(&i915
->drm
, "found:\n");
4937 intel_dpll_dump_hw_state(i915
, b
);
4942 intel_pipe_config_compare(const struct intel_crtc_state
*current_config
,
4943 const struct intel_crtc_state
*pipe_config
,
4946 struct drm_i915_private
*dev_priv
= to_i915(current_config
->uapi
.crtc
->dev
);
4947 struct intel_crtc
*crtc
= to_intel_crtc(pipe_config
->uapi
.crtc
);
4950 #define PIPE_CONF_CHECK_X(name) do { \
4951 if (current_config->name != pipe_config->name) { \
4952 BUILD_BUG_ON_MSG(__same_type(current_config->name, bool), \
4953 __stringify(name) " is bool"); \
4954 pipe_config_mismatch(fastset, crtc, __stringify(name), \
4955 "(expected 0x%08x, found 0x%08x)", \
4956 current_config->name, \
4957 pipe_config->name); \
4962 #define PIPE_CONF_CHECK_X_WITH_MASK(name, mask) do { \
4963 if ((current_config->name & (mask)) != (pipe_config->name & (mask))) { \
4964 BUILD_BUG_ON_MSG(__same_type(current_config->name, bool), \
4965 __stringify(name) " is bool"); \
4966 pipe_config_mismatch(fastset, crtc, __stringify(name), \
4967 "(expected 0x%08x, found 0x%08x)", \
4968 current_config->name & (mask), \
4969 pipe_config->name & (mask)); \
4974 #define PIPE_CONF_CHECK_I(name) do { \
4975 if (current_config->name != pipe_config->name) { \
4976 BUILD_BUG_ON_MSG(__same_type(current_config->name, bool), \
4977 __stringify(name) " is bool"); \
4978 pipe_config_mismatch(fastset, crtc, __stringify(name), \
4979 "(expected %i, found %i)", \
4980 current_config->name, \
4981 pipe_config->name); \
4986 #define PIPE_CONF_CHECK_BOOL(name) do { \
4987 if (current_config->name != pipe_config->name) { \
4988 BUILD_BUG_ON_MSG(!__same_type(current_config->name, bool), \
4989 __stringify(name) " is not bool"); \
4990 pipe_config_mismatch(fastset, crtc, __stringify(name), \
4991 "(expected %s, found %s)", \
4992 str_yes_no(current_config->name), \
4993 str_yes_no(pipe_config->name)); \
4998 #define PIPE_CONF_CHECK_P(name) do { \
4999 if (current_config->name != pipe_config->name) { \
5000 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5001 "(expected %p, found %p)", \
5002 current_config->name, \
5003 pipe_config->name); \
5008 #define PIPE_CONF_CHECK_M_N(name) do { \
5009 if (!intel_compare_link_m_n(¤t_config->name, \
5010 &pipe_config->name)) { \
5011 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5012 "(expected tu %i data %i/%i link %i/%i, " \
5013 "found tu %i, data %i/%i link %i/%i)", \
5014 current_config->name.tu, \
5015 current_config->name.data_m, \
5016 current_config->name.data_n, \
5017 current_config->name.link_m, \
5018 current_config->name.link_n, \
5019 pipe_config->name.tu, \
5020 pipe_config->name.data_m, \
5021 pipe_config->name.data_n, \
5022 pipe_config->name.link_m, \
5023 pipe_config->name.link_n); \
5028 #define PIPE_CONF_CHECK_PLL(name) do { \
5029 if (!intel_dpll_compare_hw_state(dev_priv, ¤t_config->name, \
5030 &pipe_config->name)) { \
5031 pipe_config_pll_mismatch(fastset, crtc, __stringify(name), \
5032 ¤t_config->name, \
5033 &pipe_config->name); \
5038 #define PIPE_CONF_CHECK_TIMINGS(name) do { \
5039 PIPE_CONF_CHECK_I(name.crtc_hdisplay); \
5040 PIPE_CONF_CHECK_I(name.crtc_htotal); \
5041 PIPE_CONF_CHECK_I(name.crtc_hblank_start); \
5042 PIPE_CONF_CHECK_I(name.crtc_hblank_end); \
5043 PIPE_CONF_CHECK_I(name.crtc_hsync_start); \
5044 PIPE_CONF_CHECK_I(name.crtc_hsync_end); \
5045 PIPE_CONF_CHECK_I(name.crtc_vdisplay); \
5046 PIPE_CONF_CHECK_I(name.crtc_vblank_start); \
5047 PIPE_CONF_CHECK_I(name.crtc_vsync_start); \
5048 PIPE_CONF_CHECK_I(name.crtc_vsync_end); \
5049 if (!fastset || !pipe_config->update_lrr) { \
5050 PIPE_CONF_CHECK_I(name.crtc_vtotal); \
5051 PIPE_CONF_CHECK_I(name.crtc_vblank_end); \
5055 #define PIPE_CONF_CHECK_RECT(name) do { \
5056 PIPE_CONF_CHECK_I(name.x1); \
5057 PIPE_CONF_CHECK_I(name.x2); \
5058 PIPE_CONF_CHECK_I(name.y1); \
5059 PIPE_CONF_CHECK_I(name.y2); \
5062 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \
5063 if ((current_config->name ^ pipe_config->name) & (mask)) { \
5064 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5065 "(%x) (expected %i, found %i)", \
5067 current_config->name & (mask), \
5068 pipe_config->name & (mask)); \
5073 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \
5074 if (!intel_compare_infoframe(¤t_config->infoframes.name, \
5075 &pipe_config->infoframes.name)) { \
5076 pipe_config_infoframe_mismatch(dev_priv, fastset, __stringify(name), \
5077 ¤t_config->infoframes.name, \
5078 &pipe_config->infoframes.name); \
5083 #define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \
5084 if (!intel_compare_dp_vsc_sdp(¤t_config->infoframes.name, \
5085 &pipe_config->infoframes.name)) { \
5086 pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset, __stringify(name), \
5087 ¤t_config->infoframes.name, \
5088 &pipe_config->infoframes.name); \
5093 #define PIPE_CONF_CHECK_BUFFER(name, len) do { \
5094 BUILD_BUG_ON(sizeof(current_config->name) != (len)); \
5095 BUILD_BUG_ON(sizeof(pipe_config->name) != (len)); \
5096 if (!intel_compare_buffer(current_config->name, pipe_config->name, (len))) { \
5097 pipe_config_buffer_mismatch(fastset, crtc, __stringify(name), \
5098 current_config->name, \
5099 pipe_config->name, \
5105 #define PIPE_CONF_CHECK_COLOR_LUT(lut, is_pre_csc_lut) do { \
5106 if (current_config->gamma_mode == pipe_config->gamma_mode && \
5107 !intel_color_lut_equal(current_config, \
5108 current_config->lut, pipe_config->lut, \
5109 is_pre_csc_lut)) { \
5110 pipe_config_mismatch(fastset, crtc, __stringify(lut), \
5111 "hw_state doesn't match sw_state"); \
5116 #define PIPE_CONF_CHECK_CSC(name) do { \
5117 PIPE_CONF_CHECK_X(name.preoff[0]); \
5118 PIPE_CONF_CHECK_X(name.preoff[1]); \
5119 PIPE_CONF_CHECK_X(name.preoff[2]); \
5120 PIPE_CONF_CHECK_X(name.coeff[0]); \
5121 PIPE_CONF_CHECK_X(name.coeff[1]); \
5122 PIPE_CONF_CHECK_X(name.coeff[2]); \
5123 PIPE_CONF_CHECK_X(name.coeff[3]); \
5124 PIPE_CONF_CHECK_X(name.coeff[4]); \
5125 PIPE_CONF_CHECK_X(name.coeff[5]); \
5126 PIPE_CONF_CHECK_X(name.coeff[6]); \
5127 PIPE_CONF_CHECK_X(name.coeff[7]); \
5128 PIPE_CONF_CHECK_X(name.coeff[8]); \
5129 PIPE_CONF_CHECK_X(name.postoff[0]); \
5130 PIPE_CONF_CHECK_X(name.postoff[1]); \
5131 PIPE_CONF_CHECK_X(name.postoff[2]); \
5134 #define PIPE_CONF_QUIRK(quirk) \
5135 ((current_config->quirks | pipe_config->quirks) & (quirk))
5137 PIPE_CONF_CHECK_BOOL(hw
.enable
);
5138 PIPE_CONF_CHECK_BOOL(hw
.active
);
5140 PIPE_CONF_CHECK_I(cpu_transcoder
);
5141 PIPE_CONF_CHECK_I(mst_master_transcoder
);
5143 PIPE_CONF_CHECK_BOOL(has_pch_encoder
);
5144 PIPE_CONF_CHECK_I(fdi_lanes
);
5145 PIPE_CONF_CHECK_M_N(fdi_m_n
);
5147 PIPE_CONF_CHECK_I(lane_count
);
5148 PIPE_CONF_CHECK_X(lane_lat_optim_mask
);
5150 if (HAS_DOUBLE_BUFFERED_M_N(dev_priv
)) {
5151 if (!fastset
|| !pipe_config
->update_m_n
)
5152 PIPE_CONF_CHECK_M_N(dp_m_n
);
5154 PIPE_CONF_CHECK_M_N(dp_m_n
);
5155 PIPE_CONF_CHECK_M_N(dp_m2_n2
);
5158 PIPE_CONF_CHECK_X(output_types
);
5160 PIPE_CONF_CHECK_I(framestart_delay
);
5161 PIPE_CONF_CHECK_I(msa_timing_delay
);
5163 PIPE_CONF_CHECK_TIMINGS(hw
.pipe_mode
);
5164 PIPE_CONF_CHECK_TIMINGS(hw
.adjusted_mode
);
5166 PIPE_CONF_CHECK_I(pixel_multiplier
);
5168 PIPE_CONF_CHECK_FLAGS(hw
.adjusted_mode
.flags
,
5169 DRM_MODE_FLAG_INTERLACE
);
5171 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS
)) {
5172 PIPE_CONF_CHECK_FLAGS(hw
.adjusted_mode
.flags
,
5173 DRM_MODE_FLAG_PHSYNC
);
5174 PIPE_CONF_CHECK_FLAGS(hw
.adjusted_mode
.flags
,
5175 DRM_MODE_FLAG_NHSYNC
);
5176 PIPE_CONF_CHECK_FLAGS(hw
.adjusted_mode
.flags
,
5177 DRM_MODE_FLAG_PVSYNC
);
5178 PIPE_CONF_CHECK_FLAGS(hw
.adjusted_mode
.flags
,
5179 DRM_MODE_FLAG_NVSYNC
);
5182 PIPE_CONF_CHECK_I(output_format
);
5183 PIPE_CONF_CHECK_BOOL(has_hdmi_sink
);
5184 if ((DISPLAY_VER(dev_priv
) < 8 && !IS_HASWELL(dev_priv
)) ||
5185 IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
5186 PIPE_CONF_CHECK_BOOL(limited_color_range
);
5188 PIPE_CONF_CHECK_BOOL(hdmi_scrambling
);
5189 PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio
);
5190 PIPE_CONF_CHECK_BOOL(has_infoframe
);
5191 PIPE_CONF_CHECK_BOOL(enhanced_framing
);
5192 PIPE_CONF_CHECK_BOOL(fec_enable
);
5195 PIPE_CONF_CHECK_BOOL(has_audio
);
5196 PIPE_CONF_CHECK_BUFFER(eld
, MAX_ELD_BYTES
);
5199 PIPE_CONF_CHECK_X(gmch_pfit
.control
);
5200 /* pfit ratios are autocomputed by the hw on gen4+ */
5201 if (DISPLAY_VER(dev_priv
) < 4)
5202 PIPE_CONF_CHECK_X(gmch_pfit
.pgm_ratios
);
5203 PIPE_CONF_CHECK_X(gmch_pfit
.lvds_border_bits
);
5206 * Changing the EDP transcoder input mux
5207 * (A_ONOFF vs. A_ON) requires a full modeset.
5209 PIPE_CONF_CHECK_BOOL(pch_pfit
.force_thru
);
5212 PIPE_CONF_CHECK_RECT(pipe_src
);
5214 PIPE_CONF_CHECK_BOOL(pch_pfit
.enabled
);
5215 PIPE_CONF_CHECK_RECT(pch_pfit
.dst
);
5217 PIPE_CONF_CHECK_I(scaler_state
.scaler_id
);
5218 PIPE_CONF_CHECK_I(pixel_rate
);
5220 PIPE_CONF_CHECK_X(gamma_mode
);
5221 if (IS_CHERRYVIEW(dev_priv
))
5222 PIPE_CONF_CHECK_X(cgm_mode
);
5224 PIPE_CONF_CHECK_X(csc_mode
);
5225 PIPE_CONF_CHECK_BOOL(gamma_enable
);
5226 PIPE_CONF_CHECK_BOOL(csc_enable
);
5227 PIPE_CONF_CHECK_BOOL(wgc_enable
);
5229 PIPE_CONF_CHECK_I(linetime
);
5230 PIPE_CONF_CHECK_I(ips_linetime
);
5232 PIPE_CONF_CHECK_COLOR_LUT(pre_csc_lut
, true);
5233 PIPE_CONF_CHECK_COLOR_LUT(post_csc_lut
, false);
5235 PIPE_CONF_CHECK_CSC(csc
);
5236 PIPE_CONF_CHECK_CSC(output_csc
);
5239 PIPE_CONF_CHECK_BOOL(double_wide
);
5241 if (dev_priv
->display
.dpll
.mgr
)
5242 PIPE_CONF_CHECK_P(shared_dpll
);
5244 /* FIXME convert everything over the dpll_mgr */
5245 if (dev_priv
->display
.dpll
.mgr
|| HAS_GMCH(dev_priv
))
5246 PIPE_CONF_CHECK_PLL(dpll_hw_state
);
5248 PIPE_CONF_CHECK_X(dsi_pll
.ctrl
);
5249 PIPE_CONF_CHECK_X(dsi_pll
.div
);
5251 if (IS_G4X(dev_priv
) || DISPLAY_VER(dev_priv
) >= 5)
5252 PIPE_CONF_CHECK_I(pipe_bpp
);
5254 if (!fastset
|| !pipe_config
->update_m_n
) {
5255 PIPE_CONF_CHECK_I(hw
.pipe_mode
.crtc_clock
);
5256 PIPE_CONF_CHECK_I(hw
.adjusted_mode
.crtc_clock
);
5258 PIPE_CONF_CHECK_I(port_clock
);
5260 PIPE_CONF_CHECK_I(min_voltage_level
);
5262 if (current_config
->has_psr
|| pipe_config
->has_psr
)
5263 PIPE_CONF_CHECK_X_WITH_MASK(infoframes
.enable
,
5264 ~intel_hdmi_infoframe_enable(DP_SDP_VSC
));
5266 PIPE_CONF_CHECK_X(infoframes
.enable
);
5268 PIPE_CONF_CHECK_X(infoframes
.gcp
);
5269 PIPE_CONF_CHECK_INFOFRAME(avi
);
5270 PIPE_CONF_CHECK_INFOFRAME(spd
);
5271 PIPE_CONF_CHECK_INFOFRAME(hdmi
);
5272 PIPE_CONF_CHECK_INFOFRAME(drm
);
5273 PIPE_CONF_CHECK_DP_VSC_SDP(vsc
);
5275 PIPE_CONF_CHECK_X(sync_mode_slaves_mask
);
5276 PIPE_CONF_CHECK_I(master_transcoder
);
5277 PIPE_CONF_CHECK_X(bigjoiner_pipes
);
5279 PIPE_CONF_CHECK_BOOL(dsc
.config
.block_pred_enable
);
5280 PIPE_CONF_CHECK_BOOL(dsc
.config
.convert_rgb
);
5281 PIPE_CONF_CHECK_BOOL(dsc
.config
.simple_422
);
5282 PIPE_CONF_CHECK_BOOL(dsc
.config
.native_422
);
5283 PIPE_CONF_CHECK_BOOL(dsc
.config
.native_420
);
5284 PIPE_CONF_CHECK_BOOL(dsc
.config
.vbr_enable
);
5285 PIPE_CONF_CHECK_I(dsc
.config
.line_buf_depth
);
5286 PIPE_CONF_CHECK_I(dsc
.config
.bits_per_component
);
5287 PIPE_CONF_CHECK_I(dsc
.config
.pic_width
);
5288 PIPE_CONF_CHECK_I(dsc
.config
.pic_height
);
5289 PIPE_CONF_CHECK_I(dsc
.config
.slice_width
);
5290 PIPE_CONF_CHECK_I(dsc
.config
.slice_height
);
5291 PIPE_CONF_CHECK_I(dsc
.config
.initial_dec_delay
);
5292 PIPE_CONF_CHECK_I(dsc
.config
.initial_xmit_delay
);
5293 PIPE_CONF_CHECK_I(dsc
.config
.scale_decrement_interval
);
5294 PIPE_CONF_CHECK_I(dsc
.config
.scale_increment_interval
);
5295 PIPE_CONF_CHECK_I(dsc
.config
.initial_scale_value
);
5296 PIPE_CONF_CHECK_I(dsc
.config
.first_line_bpg_offset
);
5297 PIPE_CONF_CHECK_I(dsc
.config
.flatness_min_qp
);
5298 PIPE_CONF_CHECK_I(dsc
.config
.flatness_max_qp
);
5299 PIPE_CONF_CHECK_I(dsc
.config
.slice_bpg_offset
);
5300 PIPE_CONF_CHECK_I(dsc
.config
.nfl_bpg_offset
);
5301 PIPE_CONF_CHECK_I(dsc
.config
.initial_offset
);
5302 PIPE_CONF_CHECK_I(dsc
.config
.final_offset
);
5303 PIPE_CONF_CHECK_I(dsc
.config
.rc_model_size
);
5304 PIPE_CONF_CHECK_I(dsc
.config
.rc_quant_incr_limit0
);
5305 PIPE_CONF_CHECK_I(dsc
.config
.rc_quant_incr_limit1
);
5306 PIPE_CONF_CHECK_I(dsc
.config
.slice_chunk_size
);
5307 PIPE_CONF_CHECK_I(dsc
.config
.second_line_bpg_offset
);
5308 PIPE_CONF_CHECK_I(dsc
.config
.nsl_bpg_offset
);
5310 PIPE_CONF_CHECK_BOOL(dsc
.compression_enable
);
5311 PIPE_CONF_CHECK_BOOL(dsc
.dsc_split
);
5312 PIPE_CONF_CHECK_I(dsc
.compressed_bpp_x16
);
5314 PIPE_CONF_CHECK_BOOL(splitter
.enable
);
5315 PIPE_CONF_CHECK_I(splitter
.link_count
);
5316 PIPE_CONF_CHECK_I(splitter
.pixel_overlap
);
5319 PIPE_CONF_CHECK_BOOL(vrr
.enable
);
5320 PIPE_CONF_CHECK_I(vrr
.vmin
);
5321 PIPE_CONF_CHECK_I(vrr
.vmax
);
5322 PIPE_CONF_CHECK_I(vrr
.flipline
);
5323 PIPE_CONF_CHECK_I(vrr
.pipeline_full
);
5324 PIPE_CONF_CHECK_I(vrr
.guardband
);
5327 #undef PIPE_CONF_CHECK_X
5328 #undef PIPE_CONF_CHECK_I
5329 #undef PIPE_CONF_CHECK_BOOL
5330 #undef PIPE_CONF_CHECK_P
5331 #undef PIPE_CONF_CHECK_FLAGS
5332 #undef PIPE_CONF_CHECK_COLOR_LUT
5333 #undef PIPE_CONF_CHECK_TIMINGS
5334 #undef PIPE_CONF_CHECK_RECT
5335 #undef PIPE_CONF_QUIRK
5341 intel_verify_planes(struct intel_atomic_state
*state
)
5343 struct intel_plane
*plane
;
5344 const struct intel_plane_state
*plane_state
;
5347 for_each_new_intel_plane_in_state(state
, plane
,
5349 assert_plane(plane
, plane_state
->planar_slave
||
5350 plane_state
->uapi
.visible
);
5353 static int intel_modeset_pipe(struct intel_atomic_state
*state
,
5354 struct intel_crtc_state
*crtc_state
,
5357 struct drm_i915_private
*i915
= to_i915(state
->base
.dev
);
5358 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
5361 drm_dbg_kms(&i915
->drm
, "[CRTC:%d:%s] Full modeset due to %s\n",
5362 crtc
->base
.base
.id
, crtc
->base
.name
, reason
);
5364 ret
= drm_atomic_add_affected_connectors(&state
->base
,
5369 ret
= intel_dp_mst_add_topology_state_for_crtc(state
, crtc
);
5373 ret
= intel_atomic_add_affected_planes(state
, crtc
);
5377 crtc_state
->uapi
.mode_changed
= true;
5383 * intel_modeset_pipes_in_mask_early - force a full modeset on a set of pipes
5384 * @state: intel atomic state
5385 * @reason: the reason for the full modeset
5386 * @mask: mask of pipes to modeset
5388 * Add pipes in @mask to @state and force a full modeset on the enabled ones
5389 * due to the description in @reason.
5390 * This function can be called only before new plane states are computed.
5392 * Returns 0 in case of success, negative error code otherwise.
5394 int intel_modeset_pipes_in_mask_early(struct intel_atomic_state
*state
,
5395 const char *reason
, u8 mask
)
5397 struct drm_i915_private
*i915
= to_i915(state
->base
.dev
);
5398 struct intel_crtc
*crtc
;
5400 for_each_intel_crtc_in_pipe_mask(&i915
->drm
, crtc
, mask
) {
5401 struct intel_crtc_state
*crtc_state
;
5404 crtc_state
= intel_atomic_get_crtc_state(&state
->base
, crtc
);
5405 if (IS_ERR(crtc_state
))
5406 return PTR_ERR(crtc_state
);
5408 if (!crtc_state
->hw
.enable
||
5409 intel_crtc_needs_modeset(crtc_state
))
5412 ret
= intel_modeset_pipe(state
, crtc_state
, reason
);
5421 intel_crtc_flag_modeset(struct intel_crtc_state
*crtc_state
)
5423 crtc_state
->uapi
.mode_changed
= true;
5425 crtc_state
->update_pipe
= false;
5426 crtc_state
->update_m_n
= false;
5427 crtc_state
->update_lrr
= false;
5431 * intel_modeset_all_pipes_late - force a full modeset on all pipes
5432 * @state: intel atomic state
5433 * @reason: the reason for the full modeset
5435 * Add all pipes to @state and force a full modeset on the active ones due to
5436 * the description in @reason.
5437 * This function can be called only after new plane states are computed already.
5439 * Returns 0 in case of success, negative error code otherwise.
5441 int intel_modeset_all_pipes_late(struct intel_atomic_state
*state
,
5444 struct drm_i915_private
*dev_priv
= to_i915(state
->base
.dev
);
5445 struct intel_crtc
*crtc
;
5447 for_each_intel_crtc(&dev_priv
->drm
, crtc
) {
5448 struct intel_crtc_state
*crtc_state
;
5451 crtc_state
= intel_atomic_get_crtc_state(&state
->base
, crtc
);
5452 if (IS_ERR(crtc_state
))
5453 return PTR_ERR(crtc_state
);
5455 if (!crtc_state
->hw
.active
||
5456 intel_crtc_needs_modeset(crtc_state
))
5459 ret
= intel_modeset_pipe(state
, crtc_state
, reason
);
5463 intel_crtc_flag_modeset(crtc_state
);
5465 crtc_state
->update_planes
|= crtc_state
->active_planes
;
5466 crtc_state
->async_flip_planes
= 0;
5467 crtc_state
->do_async_flip
= false;
5474 * This implements the workaround described in the "notes" section of the mode
5475 * set sequence documentation. When going from no pipes or single pipe to
5476 * multiple pipes, and planes are enabled after the pipe, we need to wait at
5477 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
5479 static int hsw_mode_set_planes_workaround(struct intel_atomic_state
*state
)
5481 struct intel_crtc_state
*crtc_state
;
5482 struct intel_crtc
*crtc
;
5483 struct intel_crtc_state
*first_crtc_state
= NULL
;
5484 struct intel_crtc_state
*other_crtc_state
= NULL
;
5485 enum pipe first_pipe
= INVALID_PIPE
, enabled_pipe
= INVALID_PIPE
;
5488 /* look at all crtc's that are going to be enabled in during modeset */
5489 for_each_new_intel_crtc_in_state(state
, crtc
, crtc_state
, i
) {
5490 if (!crtc_state
->hw
.active
||
5491 !intel_crtc_needs_modeset(crtc_state
))
5494 if (first_crtc_state
) {
5495 other_crtc_state
= crtc_state
;
5498 first_crtc_state
= crtc_state
;
5499 first_pipe
= crtc
->pipe
;
5503 /* No workaround needed? */
5504 if (!first_crtc_state
)
5507 /* w/a possibly needed, check how many crtc's are already enabled. */
5508 for_each_intel_crtc(state
->base
.dev
, crtc
) {
5509 crtc_state
= intel_atomic_get_crtc_state(&state
->base
, crtc
);
5510 if (IS_ERR(crtc_state
))
5511 return PTR_ERR(crtc_state
);
5513 crtc_state
->hsw_workaround_pipe
= INVALID_PIPE
;
5515 if (!crtc_state
->hw
.active
||
5516 intel_crtc_needs_modeset(crtc_state
))
5519 /* 2 or more enabled crtcs means no need for w/a */
5520 if (enabled_pipe
!= INVALID_PIPE
)
5523 enabled_pipe
= crtc
->pipe
;
5526 if (enabled_pipe
!= INVALID_PIPE
)
5527 first_crtc_state
->hsw_workaround_pipe
= enabled_pipe
;
5528 else if (other_crtc_state
)
5529 other_crtc_state
->hsw_workaround_pipe
= first_pipe
;
5534 u8
intel_calc_active_pipes(struct intel_atomic_state
*state
,
5537 const struct intel_crtc_state
*crtc_state
;
5538 struct intel_crtc
*crtc
;
5541 for_each_new_intel_crtc_in_state(state
, crtc
, crtc_state
, i
) {
5542 if (crtc_state
->hw
.active
)
5543 active_pipes
|= BIT(crtc
->pipe
);
5545 active_pipes
&= ~BIT(crtc
->pipe
);
5548 return active_pipes
;
5551 static int intel_modeset_checks(struct intel_atomic_state
*state
)
5553 struct drm_i915_private
*dev_priv
= to_i915(state
->base
.dev
);
5555 state
->modeset
= true;
5557 if (IS_HASWELL(dev_priv
))
5558 return hsw_mode_set_planes_workaround(state
);
5563 static void intel_crtc_check_fastset(const struct intel_crtc_state
*old_crtc_state
,
5564 struct intel_crtc_state
*new_crtc_state
)
5566 struct drm_i915_private
*i915
= to_i915(old_crtc_state
->uapi
.crtc
->dev
);
5568 /* only allow LRR when the timings stay within the VRR range */
5569 if (old_crtc_state
->vrr
.in_range
!= new_crtc_state
->vrr
.in_range
)
5570 new_crtc_state
->update_lrr
= false;
5572 if (!intel_pipe_config_compare(old_crtc_state
, new_crtc_state
, true))
5573 drm_dbg_kms(&i915
->drm
, "fastset requirement not met, forcing full modeset\n");
5575 new_crtc_state
->uapi
.mode_changed
= false;
5577 if (intel_compare_link_m_n(&old_crtc_state
->dp_m_n
,
5578 &new_crtc_state
->dp_m_n
))
5579 new_crtc_state
->update_m_n
= false;
5581 if ((old_crtc_state
->hw
.adjusted_mode
.crtc_vtotal
== new_crtc_state
->hw
.adjusted_mode
.crtc_vtotal
&&
5582 old_crtc_state
->hw
.adjusted_mode
.crtc_vblank_end
== new_crtc_state
->hw
.adjusted_mode
.crtc_vblank_end
))
5583 new_crtc_state
->update_lrr
= false;
5585 if (intel_crtc_needs_modeset(new_crtc_state
))
5586 intel_crtc_flag_modeset(new_crtc_state
);
5588 new_crtc_state
->update_pipe
= true;
5591 static int intel_crtc_add_planes_to_state(struct intel_atomic_state
*state
,
5592 struct intel_crtc
*crtc
,
5595 struct drm_i915_private
*dev_priv
= to_i915(state
->base
.dev
);
5596 struct intel_plane
*plane
;
5598 for_each_intel_plane_on_crtc(&dev_priv
->drm
, crtc
, plane
) {
5599 struct intel_plane_state
*plane_state
;
5601 if ((plane_ids_mask
& BIT(plane
->id
)) == 0)
5604 plane_state
= intel_atomic_get_plane_state(state
, plane
);
5605 if (IS_ERR(plane_state
))
5606 return PTR_ERR(plane_state
);
5612 int intel_atomic_add_affected_planes(struct intel_atomic_state
*state
,
5613 struct intel_crtc
*crtc
)
5615 const struct intel_crtc_state
*old_crtc_state
=
5616 intel_atomic_get_old_crtc_state(state
, crtc
);
5617 const struct intel_crtc_state
*new_crtc_state
=
5618 intel_atomic_get_new_crtc_state(state
, crtc
);
5620 return intel_crtc_add_planes_to_state(state
, crtc
,
5621 old_crtc_state
->enabled_planes
|
5622 new_crtc_state
->enabled_planes
);
5625 static bool active_planes_affects_min_cdclk(struct drm_i915_private
*dev_priv
)
5627 /* See {hsw,vlv,ivb}_plane_ratio() */
5628 return IS_BROADWELL(dev_priv
) || IS_HASWELL(dev_priv
) ||
5629 IS_CHERRYVIEW(dev_priv
) || IS_VALLEYVIEW(dev_priv
) ||
5630 IS_IVYBRIDGE(dev_priv
);
5633 static int intel_crtc_add_bigjoiner_planes(struct intel_atomic_state
*state
,
5634 struct intel_crtc
*crtc
,
5635 struct intel_crtc
*other
)
5637 const struct intel_plane_state __maybe_unused
*plane_state
;
5638 struct intel_plane
*plane
;
5642 for_each_new_intel_plane_in_state(state
, plane
, plane_state
, i
) {
5643 if (plane
->pipe
== crtc
->pipe
)
5644 plane_ids
|= BIT(plane
->id
);
5647 return intel_crtc_add_planes_to_state(state
, other
, plane_ids
);
5650 static int intel_bigjoiner_add_affected_planes(struct intel_atomic_state
*state
)
5652 struct drm_i915_private
*i915
= to_i915(state
->base
.dev
);
5653 const struct intel_crtc_state
*crtc_state
;
5654 struct intel_crtc
*crtc
;
5657 for_each_new_intel_crtc_in_state(state
, crtc
, crtc_state
, i
) {
5658 struct intel_crtc
*other
;
5660 for_each_intel_crtc_in_pipe_mask(&i915
->drm
, other
,
5661 crtc_state
->bigjoiner_pipes
) {
5667 ret
= intel_crtc_add_bigjoiner_planes(state
, crtc
, other
);
5676 static int intel_atomic_check_planes(struct intel_atomic_state
*state
)
5678 struct drm_i915_private
*dev_priv
= to_i915(state
->base
.dev
);
5679 struct intel_crtc_state
*old_crtc_state
, *new_crtc_state
;
5680 struct intel_plane_state __maybe_unused
*plane_state
;
5681 struct intel_plane
*plane
;
5682 struct intel_crtc
*crtc
;
5685 ret
= icl_add_linked_planes(state
);
5689 ret
= intel_bigjoiner_add_affected_planes(state
);
5693 for_each_new_intel_plane_in_state(state
, plane
, plane_state
, i
) {
5694 ret
= intel_plane_atomic_check(state
, plane
);
5696 drm_dbg_atomic(&dev_priv
->drm
,
5697 "[PLANE:%d:%s] atomic driver check failed\n",
5698 plane
->base
.base
.id
, plane
->base
.name
);
5703 for_each_oldnew_intel_crtc_in_state(state
, crtc
, old_crtc_state
,
5704 new_crtc_state
, i
) {
5705 u8 old_active_planes
, new_active_planes
;
5707 ret
= icl_check_nv12_planes(new_crtc_state
);
5712 * On some platforms the number of active planes affects
5713 * the planes' minimum cdclk calculation. Add such planes
5714 * to the state before we compute the minimum cdclk.
5716 if (!active_planes_affects_min_cdclk(dev_priv
))
5719 old_active_planes
= old_crtc_state
->active_planes
& ~BIT(PLANE_CURSOR
);
5720 new_active_planes
= new_crtc_state
->active_planes
& ~BIT(PLANE_CURSOR
);
5722 if (hweight8(old_active_planes
) == hweight8(new_active_planes
))
5725 ret
= intel_crtc_add_planes_to_state(state
, crtc
, new_active_planes
);
5733 static int intel_atomic_check_crtcs(struct intel_atomic_state
*state
)
5735 struct intel_crtc_state __maybe_unused
*crtc_state
;
5736 struct intel_crtc
*crtc
;
5739 for_each_new_intel_crtc_in_state(state
, crtc
, crtc_state
, i
) {
5740 struct drm_i915_private
*i915
= to_i915(crtc
->base
.dev
);
5743 ret
= intel_crtc_atomic_check(state
, crtc
);
5745 drm_dbg_atomic(&i915
->drm
,
5746 "[CRTC:%d:%s] atomic driver check failed\n",
5747 crtc
->base
.base
.id
, crtc
->base
.name
);
5755 static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state
*state
,
5758 const struct intel_crtc_state
*new_crtc_state
;
5759 struct intel_crtc
*crtc
;
5762 for_each_new_intel_crtc_in_state(state
, crtc
, new_crtc_state
, i
) {
5763 if (new_crtc_state
->hw
.enable
&&
5764 transcoders
& BIT(new_crtc_state
->cpu_transcoder
) &&
5765 intel_crtc_needs_modeset(new_crtc_state
))
5772 static bool intel_pipes_need_modeset(struct intel_atomic_state
*state
,
5775 const struct intel_crtc_state
*new_crtc_state
;
5776 struct intel_crtc
*crtc
;
5779 for_each_new_intel_crtc_in_state(state
, crtc
, new_crtc_state
, i
) {
5780 if (new_crtc_state
->hw
.enable
&&
5781 pipes
& BIT(crtc
->pipe
) &&
5782 intel_crtc_needs_modeset(new_crtc_state
))
5789 static int intel_atomic_check_bigjoiner(struct intel_atomic_state
*state
,
5790 struct intel_crtc
*master_crtc
)
5792 struct drm_i915_private
*i915
= to_i915(state
->base
.dev
);
5793 struct intel_crtc_state
*master_crtc_state
=
5794 intel_atomic_get_new_crtc_state(state
, master_crtc
);
5795 struct intel_crtc
*slave_crtc
;
5797 if (!master_crtc_state
->bigjoiner_pipes
)
5801 if (drm_WARN_ON(&i915
->drm
,
5802 master_crtc
->pipe
!= bigjoiner_master_pipe(master_crtc_state
)))
5805 if (master_crtc_state
->bigjoiner_pipes
& ~bigjoiner_pipes(i915
)) {
5806 drm_dbg_kms(&i915
->drm
,
5807 "[CRTC:%d:%s] Cannot act as big joiner master "
5808 "(need 0x%x as pipes, only 0x%x possible)\n",
5809 master_crtc
->base
.base
.id
, master_crtc
->base
.name
,
5810 master_crtc_state
->bigjoiner_pipes
, bigjoiner_pipes(i915
));
5814 for_each_intel_crtc_in_pipe_mask(&i915
->drm
, slave_crtc
,
5815 intel_crtc_bigjoiner_slave_pipes(master_crtc_state
)) {
5816 struct intel_crtc_state
*slave_crtc_state
;
5819 slave_crtc_state
= intel_atomic_get_crtc_state(&state
->base
, slave_crtc
);
5820 if (IS_ERR(slave_crtc_state
))
5821 return PTR_ERR(slave_crtc_state
);
5823 /* master being enabled, slave was already configured? */
5824 if (slave_crtc_state
->uapi
.enable
) {
5825 drm_dbg_kms(&i915
->drm
,
5826 "[CRTC:%d:%s] Slave is enabled as normal CRTC, but "
5827 "[CRTC:%d:%s] claiming this CRTC for bigjoiner.\n",
5828 slave_crtc
->base
.base
.id
, slave_crtc
->base
.name
,
5829 master_crtc
->base
.base
.id
, master_crtc
->base
.name
);
5834 * The state copy logic assumes the master crtc gets processed
5835 * before the slave crtc during the main compute_config loop.
5836 * This works because the crtcs are created in pipe order,
5837 * and the hardware requires master pipe < slave pipe as well.
5838 * Should that change we need to rethink the logic.
5840 if (WARN_ON(drm_crtc_index(&master_crtc
->base
) >
5841 drm_crtc_index(&slave_crtc
->base
)))
5844 drm_dbg_kms(&i915
->drm
,
5845 "[CRTC:%d:%s] Used as slave for big joiner master [CRTC:%d:%s]\n",
5846 slave_crtc
->base
.base
.id
, slave_crtc
->base
.name
,
5847 master_crtc
->base
.base
.id
, master_crtc
->base
.name
);
5849 slave_crtc_state
->bigjoiner_pipes
=
5850 master_crtc_state
->bigjoiner_pipes
;
5852 ret
= copy_bigjoiner_crtc_state_modeset(state
, slave_crtc
);
5860 static void kill_bigjoiner_slave(struct intel_atomic_state
*state
,
5861 struct intel_crtc
*master_crtc
)
5863 struct drm_i915_private
*i915
= to_i915(state
->base
.dev
);
5864 struct intel_crtc_state
*master_crtc_state
=
5865 intel_atomic_get_new_crtc_state(state
, master_crtc
);
5866 struct intel_crtc
*slave_crtc
;
5868 for_each_intel_crtc_in_pipe_mask(&i915
->drm
, slave_crtc
,
5869 intel_crtc_bigjoiner_slave_pipes(master_crtc_state
)) {
5870 struct intel_crtc_state
*slave_crtc_state
=
5871 intel_atomic_get_new_crtc_state(state
, slave_crtc
);
5873 slave_crtc_state
->bigjoiner_pipes
= 0;
5875 intel_crtc_copy_uapi_to_hw_state_modeset(state
, slave_crtc
);
5878 master_crtc_state
->bigjoiner_pipes
= 0;
5882 * DOC: asynchronous flip implementation
5884 * Asynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC
5885 * flag. Currently async flip is only supported via the drmModePageFlip IOCTL.
5886 * Correspondingly, support is currently added for primary plane only.
5888 * Async flip can only change the plane surface address, so anything else
5889 * changing is rejected from the intel_async_flip_check_hw() function.
5890 * Once this check is cleared, flip done interrupt is enabled using
5891 * the intel_crtc_enable_flip_done() function.
5893 * As soon as the surface address register is written, flip done interrupt is
5894 * generated and the requested events are sent to the usersapce in the interrupt
5895 * handler itself. The timestamp and sequence sent during the flip done event
5896 * correspond to the last vblank and have no relation to the actual time when
5897 * the flip done event was sent.
5899 static int intel_async_flip_check_uapi(struct intel_atomic_state
*state
,
5900 struct intel_crtc
*crtc
)
5902 struct drm_i915_private
*i915
= to_i915(state
->base
.dev
);
5903 const struct intel_crtc_state
*new_crtc_state
=
5904 intel_atomic_get_new_crtc_state(state
, crtc
);
5905 const struct intel_plane_state
*old_plane_state
;
5906 struct intel_plane_state
*new_plane_state
;
5907 struct intel_plane
*plane
;
5910 if (!new_crtc_state
->uapi
.async_flip
)
5913 if (!new_crtc_state
->uapi
.active
) {
5914 drm_dbg_kms(&i915
->drm
,
5915 "[CRTC:%d:%s] not active\n",
5916 crtc
->base
.base
.id
, crtc
->base
.name
);
5920 if (intel_crtc_needs_modeset(new_crtc_state
)) {
5921 drm_dbg_kms(&i915
->drm
,
5922 "[CRTC:%d:%s] modeset required\n",
5923 crtc
->base
.base
.id
, crtc
->base
.name
);
5928 * FIXME: Bigjoiner+async flip is busted currently.
5929 * Remove this check once the issues are fixed.
5931 if (new_crtc_state
->bigjoiner_pipes
) {
5932 drm_dbg_kms(&i915
->drm
,
5933 "[CRTC:%d:%s] async flip disallowed with bigjoiner\n",
5934 crtc
->base
.base
.id
, crtc
->base
.name
);
5938 for_each_oldnew_intel_plane_in_state(state
, plane
, old_plane_state
,
5939 new_plane_state
, i
) {
5940 if (plane
->pipe
!= crtc
->pipe
)
5944 * TODO: Async flip is only supported through the page flip IOCTL
5945 * as of now. So support currently added for primary plane only.
5946 * Support for other planes on platforms on which supports
5947 * this(vlv/chv and icl+) should be added when async flip is
5948 * enabled in the atomic IOCTL path.
5950 if (!plane
->async_flip
) {
5951 drm_dbg_kms(&i915
->drm
,
5952 "[PLANE:%d:%s] async flip not supported\n",
5953 plane
->base
.base
.id
, plane
->base
.name
);
5957 if (!old_plane_state
->uapi
.fb
|| !new_plane_state
->uapi
.fb
) {
5958 drm_dbg_kms(&i915
->drm
,
5959 "[PLANE:%d:%s] no old or new framebuffer\n",
5960 plane
->base
.base
.id
, plane
->base
.name
);
5968 static int intel_async_flip_check_hw(struct intel_atomic_state
*state
, struct intel_crtc
*crtc
)
5970 struct drm_i915_private
*i915
= to_i915(state
->base
.dev
);
5971 const struct intel_crtc_state
*old_crtc_state
, *new_crtc_state
;
5972 const struct intel_plane_state
*new_plane_state
, *old_plane_state
;
5973 struct intel_plane
*plane
;
5976 old_crtc_state
= intel_atomic_get_old_crtc_state(state
, crtc
);
5977 new_crtc_state
= intel_atomic_get_new_crtc_state(state
, crtc
);
5979 if (!new_crtc_state
->uapi
.async_flip
)
5982 if (!new_crtc_state
->hw
.active
) {
5983 drm_dbg_kms(&i915
->drm
,
5984 "[CRTC:%d:%s] not active\n",
5985 crtc
->base
.base
.id
, crtc
->base
.name
);
5989 if (intel_crtc_needs_modeset(new_crtc_state
)) {
5990 drm_dbg_kms(&i915
->drm
,
5991 "[CRTC:%d:%s] modeset required\n",
5992 crtc
->base
.base
.id
, crtc
->base
.name
);
5996 if (old_crtc_state
->active_planes
!= new_crtc_state
->active_planes
) {
5997 drm_dbg_kms(&i915
->drm
,
5998 "[CRTC:%d:%s] Active planes cannot be in async flip\n",
5999 crtc
->base
.base
.id
, crtc
->base
.name
);
6003 for_each_oldnew_intel_plane_in_state(state
, plane
, old_plane_state
,
6004 new_plane_state
, i
) {
6005 if (plane
->pipe
!= crtc
->pipe
)
6009 * Only async flip capable planes should be in the state
6010 * if we're really about to ask the hardware to perform
6011 * an async flip. We should never get this far otherwise.
6013 if (drm_WARN_ON(&i915
->drm
,
6014 new_crtc_state
->do_async_flip
&& !plane
->async_flip
))
6018 * Only check async flip capable planes other planes
6019 * may be involved in the initial commit due to
6020 * the wm0/ddb optimization.
6022 * TODO maybe should track which planes actually
6023 * were requested to do the async flip...
6025 if (!plane
->async_flip
)
6029 * FIXME: This check is kept generic for all platforms.
6030 * Need to verify this for all gen9 platforms to enable
6031 * this selectively if required.
6033 switch (new_plane_state
->hw
.fb
->modifier
) {
6034 case DRM_FORMAT_MOD_LINEAR
:
6036 * FIXME: Async on Linear buffer is supported on ICL as
6037 * but with additional alignment and fbc restrictions
6038 * need to be taken care of. These aren't applicable for
6041 if (DISPLAY_VER(i915
) < 12) {
6042 drm_dbg_kms(&i915
->drm
,
6043 "[PLANE:%d:%s] Modifier 0x%llx does not support async flip on display ver %d\n",
6044 plane
->base
.base
.id
, plane
->base
.name
,
6045 new_plane_state
->hw
.fb
->modifier
, DISPLAY_VER(i915
));
6050 case I915_FORMAT_MOD_X_TILED
:
6051 case I915_FORMAT_MOD_Y_TILED
:
6052 case I915_FORMAT_MOD_Yf_TILED
:
6053 case I915_FORMAT_MOD_4_TILED
:
6056 drm_dbg_kms(&i915
->drm
,
6057 "[PLANE:%d:%s] Modifier 0x%llx does not support async flip\n",
6058 plane
->base
.base
.id
, plane
->base
.name
,
6059 new_plane_state
->hw
.fb
->modifier
);
6063 if (new_plane_state
->hw
.fb
->format
->num_planes
> 1) {
6064 drm_dbg_kms(&i915
->drm
,
6065 "[PLANE:%d:%s] Planar formats do not support async flips\n",
6066 plane
->base
.base
.id
, plane
->base
.name
);
6070 if (old_plane_state
->view
.color_plane
[0].mapping_stride
!=
6071 new_plane_state
->view
.color_plane
[0].mapping_stride
) {
6072 drm_dbg_kms(&i915
->drm
,
6073 "[PLANE:%d:%s] Stride cannot be changed in async flip\n",
6074 plane
->base
.base
.id
, plane
->base
.name
);
6078 if (old_plane_state
->hw
.fb
->modifier
!=
6079 new_plane_state
->hw
.fb
->modifier
) {
6080 drm_dbg_kms(&i915
->drm
,
6081 "[PLANE:%d:%s] Modifier cannot be changed in async flip\n",
6082 plane
->base
.base
.id
, plane
->base
.name
);
6086 if (old_plane_state
->hw
.fb
->format
!=
6087 new_plane_state
->hw
.fb
->format
) {
6088 drm_dbg_kms(&i915
->drm
,
6089 "[PLANE:%d:%s] Pixel format cannot be changed in async flip\n",
6090 plane
->base
.base
.id
, plane
->base
.name
);
6094 if (old_plane_state
->hw
.rotation
!=
6095 new_plane_state
->hw
.rotation
) {
6096 drm_dbg_kms(&i915
->drm
,
6097 "[PLANE:%d:%s] Rotation cannot be changed in async flip\n",
6098 plane
->base
.base
.id
, plane
->base
.name
);
6102 if (!drm_rect_equals(&old_plane_state
->uapi
.src
, &new_plane_state
->uapi
.src
) ||
6103 !drm_rect_equals(&old_plane_state
->uapi
.dst
, &new_plane_state
->uapi
.dst
)) {
6104 drm_dbg_kms(&i915
->drm
,
6105 "[PLANE:%d:%s] Size/co-ordinates cannot be changed in async flip\n",
6106 plane
->base
.base
.id
, plane
->base
.name
);
6110 if (old_plane_state
->hw
.alpha
!= new_plane_state
->hw
.alpha
) {
6111 drm_dbg_kms(&i915
->drm
,
6112 "[PLANES:%d:%s] Alpha value cannot be changed in async flip\n",
6113 plane
->base
.base
.id
, plane
->base
.name
);
6117 if (old_plane_state
->hw
.pixel_blend_mode
!=
6118 new_plane_state
->hw
.pixel_blend_mode
) {
6119 drm_dbg_kms(&i915
->drm
,
6120 "[PLANE:%d:%s] Pixel blend mode cannot be changed in async flip\n",
6121 plane
->base
.base
.id
, plane
->base
.name
);
6125 if (old_plane_state
->hw
.color_encoding
!= new_plane_state
->hw
.color_encoding
) {
6126 drm_dbg_kms(&i915
->drm
,
6127 "[PLANE:%d:%s] Color encoding cannot be changed in async flip\n",
6128 plane
->base
.base
.id
, plane
->base
.name
);
6132 if (old_plane_state
->hw
.color_range
!= new_plane_state
->hw
.color_range
) {
6133 drm_dbg_kms(&i915
->drm
,
6134 "[PLANE:%d:%s] Color range cannot be changed in async flip\n",
6135 plane
->base
.base
.id
, plane
->base
.name
);
6139 /* plane decryption is allow to change only in synchronous flips */
6140 if (old_plane_state
->decrypt
!= new_plane_state
->decrypt
) {
6141 drm_dbg_kms(&i915
->drm
,
6142 "[PLANE:%d:%s] Decryption cannot be changed in async flip\n",
6143 plane
->base
.base
.id
, plane
->base
.name
);
6151 static int intel_bigjoiner_add_affected_crtcs(struct intel_atomic_state
*state
)
6153 struct drm_i915_private
*i915
= to_i915(state
->base
.dev
);
6154 struct intel_crtc_state
*crtc_state
;
6155 struct intel_crtc
*crtc
;
6156 u8 affected_pipes
= 0;
6157 u8 modeset_pipes
= 0;
6160 for_each_new_intel_crtc_in_state(state
, crtc
, crtc_state
, i
) {
6161 affected_pipes
|= crtc_state
->bigjoiner_pipes
;
6162 if (intel_crtc_needs_modeset(crtc_state
))
6163 modeset_pipes
|= crtc_state
->bigjoiner_pipes
;
6166 for_each_intel_crtc_in_pipe_mask(&i915
->drm
, crtc
, affected_pipes
) {
6167 crtc_state
= intel_atomic_get_crtc_state(&state
->base
, crtc
);
6168 if (IS_ERR(crtc_state
))
6169 return PTR_ERR(crtc_state
);
6172 for_each_intel_crtc_in_pipe_mask(&i915
->drm
, crtc
, modeset_pipes
) {
6175 crtc_state
= intel_atomic_get_new_crtc_state(state
, crtc
);
6177 crtc_state
->uapi
.mode_changed
= true;
6179 ret
= drm_atomic_add_affected_connectors(&state
->base
, &crtc
->base
);
6183 ret
= intel_atomic_add_affected_planes(state
, crtc
);
6188 for_each_new_intel_crtc_in_state(state
, crtc
, crtc_state
, i
) {
6189 /* Kill old bigjoiner link, we may re-establish afterwards */
6190 if (intel_crtc_needs_modeset(crtc_state
) &&
6191 intel_crtc_is_bigjoiner_master(crtc_state
))
6192 kill_bigjoiner_slave(state
, crtc
);
6198 static int intel_atomic_check_config(struct intel_atomic_state
*state
,
6199 struct intel_link_bw_limits
*limits
,
6200 enum pipe
*failed_pipe
)
6202 struct drm_i915_private
*i915
= to_i915(state
->base
.dev
);
6203 struct intel_crtc_state
*new_crtc_state
;
6204 struct intel_crtc
*crtc
;
6208 *failed_pipe
= INVALID_PIPE
;
6210 ret
= intel_bigjoiner_add_affected_crtcs(state
);
6214 ret
= intel_fdi_add_affected_crtcs(state
);
6218 for_each_new_intel_crtc_in_state(state
, crtc
, new_crtc_state
, i
) {
6219 if (!intel_crtc_needs_modeset(new_crtc_state
)) {
6220 if (intel_crtc_is_bigjoiner_slave(new_crtc_state
))
6221 copy_bigjoiner_crtc_state_nomodeset(state
, crtc
);
6223 intel_crtc_copy_uapi_to_hw_state_nomodeset(state
, crtc
);
6227 if (intel_crtc_is_bigjoiner_slave(new_crtc_state
)) {
6228 drm_WARN_ON(&i915
->drm
, new_crtc_state
->uapi
.enable
);
6232 ret
= intel_crtc_prepare_cleared_state(state
, crtc
);
6236 if (!new_crtc_state
->hw
.enable
)
6239 ret
= intel_modeset_pipe_config(state
, crtc
, limits
);
6243 ret
= intel_atomic_check_bigjoiner(state
, crtc
);
6249 *failed_pipe
= crtc
->pipe
;
6254 static int intel_atomic_check_config_and_link(struct intel_atomic_state
*state
)
6256 struct intel_link_bw_limits new_limits
;
6257 struct intel_link_bw_limits old_limits
;
6260 intel_link_bw_init_limits(state
, &new_limits
);
6261 old_limits
= new_limits
;
6264 enum pipe failed_pipe
;
6266 ret
= intel_atomic_check_config(state
, &new_limits
,
6270 * The bpp limit for a pipe is below the minimum it supports, set the
6271 * limit to the minimum and recalculate the config.
6273 if (ret
== -EINVAL
&&
6274 intel_link_bw_set_bpp_limit_for_pipe(state
,
6283 old_limits
= new_limits
;
6285 ret
= intel_link_bw_atomic_check(state
, &new_limits
);
6293 * intel_atomic_check - validate state object
6295 * @_state: state to validate
6297 int intel_atomic_check(struct drm_device
*dev
,
6298 struct drm_atomic_state
*_state
)
6300 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6301 struct intel_atomic_state
*state
= to_intel_atomic_state(_state
);
6302 struct intel_crtc_state
*old_crtc_state
, *new_crtc_state
;
6303 struct intel_crtc
*crtc
;
6305 bool any_ms
= false;
6307 if (!intel_display_driver_check_access(dev_priv
))
6310 for_each_oldnew_intel_crtc_in_state(state
, crtc
, old_crtc_state
,
6311 new_crtc_state
, i
) {
6313 * crtc's state no longer considered to be inherited
6314 * after the first userspace/client initiated commit.
6316 if (!state
->internal
)
6317 new_crtc_state
->inherited
= false;
6319 if (new_crtc_state
->inherited
!= old_crtc_state
->inherited
)
6320 new_crtc_state
->uapi
.mode_changed
= true;
6322 if (new_crtc_state
->uapi
.scaling_filter
!=
6323 old_crtc_state
->uapi
.scaling_filter
)
6324 new_crtc_state
->uapi
.mode_changed
= true;
6327 intel_vrr_check_modeset(state
);
6329 ret
= drm_atomic_helper_check_modeset(dev
, &state
->base
);
6333 for_each_new_intel_crtc_in_state(state
, crtc
, new_crtc_state
, i
) {
6334 ret
= intel_async_flip_check_uapi(state
, crtc
);
6339 ret
= intel_atomic_check_config_and_link(state
);
6343 for_each_oldnew_intel_crtc_in_state(state
, crtc
, old_crtc_state
,
6344 new_crtc_state
, i
) {
6345 if (!intel_crtc_needs_modeset(new_crtc_state
))
6348 if (new_crtc_state
->hw
.enable
) {
6349 ret
= intel_modeset_pipe_config_late(state
, crtc
);
6354 intel_crtc_check_fastset(old_crtc_state
, new_crtc_state
);
6358 * Check if fastset is allowed by external dependencies like other
6359 * pipes and transcoders.
6361 * Right now it only forces a fullmodeset when the MST master
6362 * transcoder did not changed but the pipe of the master transcoder
6363 * needs a fullmodeset so all slaves also needs to do a fullmodeset or
6364 * in case of port synced crtcs, if one of the synced crtcs
6365 * needs a full modeset, all other synced crtcs should be
6366 * forced a full modeset.
6368 for_each_new_intel_crtc_in_state(state
, crtc
, new_crtc_state
, i
) {
6369 if (!new_crtc_state
->hw
.enable
|| intel_crtc_needs_modeset(new_crtc_state
))
6372 if (intel_dp_mst_crtc_needs_modeset(state
, crtc
))
6373 intel_crtc_flag_modeset(new_crtc_state
);
6375 if (intel_dp_mst_is_slave_trans(new_crtc_state
)) {
6376 enum transcoder master
= new_crtc_state
->mst_master_transcoder
;
6378 if (intel_cpu_transcoders_need_modeset(state
, BIT(master
)))
6379 intel_crtc_flag_modeset(new_crtc_state
);
6382 if (is_trans_port_sync_mode(new_crtc_state
)) {
6383 u8 trans
= new_crtc_state
->sync_mode_slaves_mask
;
6385 if (new_crtc_state
->master_transcoder
!= INVALID_TRANSCODER
)
6386 trans
|= BIT(new_crtc_state
->master_transcoder
);
6388 if (intel_cpu_transcoders_need_modeset(state
, trans
))
6389 intel_crtc_flag_modeset(new_crtc_state
);
6392 if (new_crtc_state
->bigjoiner_pipes
) {
6393 if (intel_pipes_need_modeset(state
, new_crtc_state
->bigjoiner_pipes
))
6394 intel_crtc_flag_modeset(new_crtc_state
);
6398 for_each_oldnew_intel_crtc_in_state(state
, crtc
, old_crtc_state
,
6399 new_crtc_state
, i
) {
6400 if (!intel_crtc_needs_modeset(new_crtc_state
))
6405 intel_release_shared_dplls(state
, crtc
);
6408 if (any_ms
&& !check_digital_port_conflicts(state
)) {
6409 drm_dbg_kms(&dev_priv
->drm
,
6410 "rejecting conflicting digital port configuration\n");
6415 ret
= intel_atomic_check_planes(state
);
6419 ret
= intel_compute_global_watermarks(state
);
6423 ret
= intel_bw_atomic_check(state
);
6427 ret
= intel_cdclk_atomic_check(state
, &any_ms
);
6431 if (intel_any_crtc_needs_modeset(state
))
6435 ret
= intel_modeset_checks(state
);
6439 ret
= intel_modeset_calc_cdclk(state
);
6444 ret
= intel_pmdemand_atomic_check(state
);
6448 ret
= intel_atomic_check_crtcs(state
);
6452 ret
= intel_fbc_atomic_check(state
);
6456 for_each_oldnew_intel_crtc_in_state(state
, crtc
, old_crtc_state
,
6457 new_crtc_state
, i
) {
6458 intel_color_assert_luts(new_crtc_state
);
6460 ret
= intel_async_flip_check_hw(state
, crtc
);
6464 /* Either full modeset or fastset (or neither), never both */
6465 drm_WARN_ON(&dev_priv
->drm
,
6466 intel_crtc_needs_modeset(new_crtc_state
) &&
6467 intel_crtc_needs_fastset(new_crtc_state
));
6469 if (!intel_crtc_needs_modeset(new_crtc_state
) &&
6470 !intel_crtc_needs_fastset(new_crtc_state
))
6473 intel_crtc_state_dump(new_crtc_state
, state
,
6474 intel_crtc_needs_modeset(new_crtc_state
) ?
6475 "modeset" : "fastset");
6481 if (ret
== -EDEADLK
)
6485 * FIXME would probably be nice to know which crtc specifically
6486 * caused the failure, in cases where we can pinpoint it.
6488 for_each_oldnew_intel_crtc_in_state(state
, crtc
, old_crtc_state
,
6490 intel_crtc_state_dump(new_crtc_state
, state
, "failed");
6495 static int intel_atomic_prepare_commit(struct intel_atomic_state
*state
)
6497 struct intel_crtc_state
*crtc_state
;
6498 struct intel_crtc
*crtc
;
6501 ret
= drm_atomic_helper_prepare_planes(state
->base
.dev
, &state
->base
);
6505 for_each_new_intel_crtc_in_state(state
, crtc
, crtc_state
, i
) {
6506 if (intel_crtc_needs_color_update(crtc_state
))
6507 intel_color_prepare_commit(crtc_state
);
6513 void intel_crtc_arm_fifo_underrun(struct intel_crtc
*crtc
,
6514 struct intel_crtc_state
*crtc_state
)
6516 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
6518 if (DISPLAY_VER(dev_priv
) != 2 || crtc_state
->active_planes
)
6519 intel_set_cpu_fifo_underrun_reporting(dev_priv
, crtc
->pipe
, true);
6521 if (crtc_state
->has_pch_encoder
) {
6522 enum pipe pch_transcoder
=
6523 intel_crtc_pch_transcoder(crtc
);
6525 intel_set_pch_fifo_underrun_reporting(dev_priv
, pch_transcoder
, true);
6529 static void intel_pipe_fastset(const struct intel_crtc_state
*old_crtc_state
,
6530 const struct intel_crtc_state
*new_crtc_state
)
6532 struct intel_crtc
*crtc
= to_intel_crtc(new_crtc_state
->uapi
.crtc
);
6533 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
6536 * Update pipe size and adjust fitter if needed: the reason for this is
6537 * that in compute_mode_changes we check the native mode (not the pfit
6538 * mode) to see if we can flip rather than do a full mode set. In the
6539 * fastboot case, we'll flip, but if we don't update the pipesrc and
6540 * pfit state, we'll end up with a big fb scanned out into the wrong
6543 intel_set_pipe_src_size(new_crtc_state
);
6545 /* on skylake this is done by detaching scalers */
6546 if (DISPLAY_VER(dev_priv
) >= 9) {
6547 if (new_crtc_state
->pch_pfit
.enabled
)
6548 skl_pfit_enable(new_crtc_state
);
6549 } else if (HAS_PCH_SPLIT(dev_priv
)) {
6550 if (new_crtc_state
->pch_pfit
.enabled
)
6551 ilk_pfit_enable(new_crtc_state
);
6552 else if (old_crtc_state
->pch_pfit
.enabled
)
6553 ilk_pfit_disable(old_crtc_state
);
6557 * The register is supposedly single buffered so perhaps
6558 * not 100% correct to do this here. But SKL+ calculate
6559 * this based on the adjust pixel rate so pfit changes do
6560 * affect it and so it must be updated for fastsets.
6561 * HSW/BDW only really need this here for fastboot, after
6562 * that the value should not change without a full modeset.
6564 if (DISPLAY_VER(dev_priv
) >= 9 ||
6565 IS_BROADWELL(dev_priv
) || IS_HASWELL(dev_priv
))
6566 hsw_set_linetime_wm(new_crtc_state
);
6568 if (new_crtc_state
->update_m_n
)
6569 intel_cpu_transcoder_set_m1_n1(crtc
, new_crtc_state
->cpu_transcoder
,
6570 &new_crtc_state
->dp_m_n
);
6572 if (new_crtc_state
->update_lrr
)
6573 intel_set_transcoder_timings_lrr(new_crtc_state
);
6576 static void commit_pipe_pre_planes(struct intel_atomic_state
*state
,
6577 struct intel_crtc
*crtc
)
6579 struct drm_i915_private
*dev_priv
= to_i915(state
->base
.dev
);
6580 const struct intel_crtc_state
*old_crtc_state
=
6581 intel_atomic_get_old_crtc_state(state
, crtc
);
6582 const struct intel_crtc_state
*new_crtc_state
=
6583 intel_atomic_get_new_crtc_state(state
, crtc
);
6584 bool modeset
= intel_crtc_needs_modeset(new_crtc_state
);
6587 * During modesets pipe configuration was programmed as the
6591 if (intel_crtc_needs_color_update(new_crtc_state
))
6592 intel_color_commit_arm(new_crtc_state
);
6594 if (DISPLAY_VER(dev_priv
) >= 9 || IS_BROADWELL(dev_priv
))
6595 bdw_set_pipe_misc(new_crtc_state
);
6597 if (intel_crtc_needs_fastset(new_crtc_state
))
6598 intel_pipe_fastset(old_crtc_state
, new_crtc_state
);
6601 intel_psr2_program_trans_man_trk_ctl(new_crtc_state
);
6603 intel_atomic_update_watermarks(state
, crtc
);
6606 static void commit_pipe_post_planes(struct intel_atomic_state
*state
,
6607 struct intel_crtc
*crtc
)
6609 struct drm_i915_private
*dev_priv
= to_i915(state
->base
.dev
);
6610 const struct intel_crtc_state
*old_crtc_state
=
6611 intel_atomic_get_old_crtc_state(state
, crtc
);
6612 const struct intel_crtc_state
*new_crtc_state
=
6613 intel_atomic_get_new_crtc_state(state
, crtc
);
6616 * Disable the scaler(s) after the plane(s) so that we don't
6617 * get a catastrophic underrun even if the two operations
6618 * end up happening in two different frames.
6620 if (DISPLAY_VER(dev_priv
) >= 9 &&
6621 !intel_crtc_needs_modeset(new_crtc_state
))
6622 skl_detach_scalers(new_crtc_state
);
6624 if (vrr_enabling(old_crtc_state
, new_crtc_state
))
6625 intel_vrr_enable(new_crtc_state
);
6628 static void intel_enable_crtc(struct intel_atomic_state
*state
,
6629 struct intel_crtc
*crtc
)
6631 struct drm_i915_private
*dev_priv
= to_i915(state
->base
.dev
);
6632 const struct intel_crtc_state
*new_crtc_state
=
6633 intel_atomic_get_new_crtc_state(state
, crtc
);
6635 if (!intel_crtc_needs_modeset(new_crtc_state
))
6638 /* VRR will be enable later, if required */
6639 intel_crtc_update_active_timings(new_crtc_state
, false);
6641 dev_priv
->display
.funcs
.display
->crtc_enable(state
, crtc
);
6643 if (intel_crtc_is_bigjoiner_slave(new_crtc_state
))
6646 /* vblanks work again, re-enable pipe CRC. */
6647 intel_crtc_enable_pipe_crc(crtc
);
6650 static void intel_pre_update_crtc(struct intel_atomic_state
*state
,
6651 struct intel_crtc
*crtc
)
6653 struct drm_i915_private
*i915
= to_i915(state
->base
.dev
);
6654 const struct intel_crtc_state
*old_crtc_state
=
6655 intel_atomic_get_old_crtc_state(state
, crtc
);
6656 struct intel_crtc_state
*new_crtc_state
=
6657 intel_atomic_get_new_crtc_state(state
, crtc
);
6658 bool modeset
= intel_crtc_needs_modeset(new_crtc_state
);
6660 if (old_crtc_state
->inherited
||
6661 intel_crtc_needs_modeset(new_crtc_state
)) {
6663 intel_dpt_configure(crtc
);
6667 if (new_crtc_state
->preload_luts
&&
6668 intel_crtc_needs_color_update(new_crtc_state
))
6669 intel_color_load_luts(new_crtc_state
);
6671 intel_pre_plane_update(state
, crtc
);
6673 if (intel_crtc_needs_fastset(new_crtc_state
))
6674 intel_encoders_update_pipe(state
, crtc
);
6676 if (DISPLAY_VER(i915
) >= 11 &&
6677 intel_crtc_needs_fastset(new_crtc_state
))
6678 icl_set_pipe_chicken(new_crtc_state
);
6680 if (vrr_params_changed(old_crtc_state
, new_crtc_state
))
6681 intel_vrr_set_transcoder_timings(new_crtc_state
);
6684 intel_fbc_update(state
, crtc
);
6686 drm_WARN_ON(&i915
->drm
, !intel_display_power_is_enabled(i915
, POWER_DOMAIN_DC_OFF
));
6689 intel_crtc_needs_color_update(new_crtc_state
))
6690 intel_color_commit_noarm(new_crtc_state
);
6692 intel_crtc_planes_update_noarm(state
, crtc
);
6695 static void intel_update_crtc(struct intel_atomic_state
*state
,
6696 struct intel_crtc
*crtc
)
6698 const struct intel_crtc_state
*old_crtc_state
=
6699 intel_atomic_get_old_crtc_state(state
, crtc
);
6700 struct intel_crtc_state
*new_crtc_state
=
6701 intel_atomic_get_new_crtc_state(state
, crtc
);
6703 /* Perform vblank evasion around commit operation */
6704 intel_pipe_update_start(state
, crtc
);
6706 commit_pipe_pre_planes(state
, crtc
);
6708 intel_crtc_planes_update_arm(state
, crtc
);
6710 commit_pipe_post_planes(state
, crtc
);
6712 intel_pipe_update_end(state
, crtc
);
6715 * VRR/Seamless M/N update may need to update frame timings.
6717 * FIXME Should be synchronized with the start of vblank somehow...
6719 if (vrr_enabling(old_crtc_state
, new_crtc_state
) ||
6720 new_crtc_state
->update_m_n
|| new_crtc_state
->update_lrr
)
6721 intel_crtc_update_active_timings(new_crtc_state
,
6722 new_crtc_state
->vrr
.enable
);
6725 * We usually enable FIFO underrun interrupts as part of the
6726 * CRTC enable sequence during modesets. But when we inherit a
6727 * valid pipe configuration from the BIOS we need to take care
6728 * of enabling them on the CRTC's first fastset.
6730 if (intel_crtc_needs_fastset(new_crtc_state
) &&
6731 old_crtc_state
->inherited
)
6732 intel_crtc_arm_fifo_underrun(crtc
, new_crtc_state
);
6735 static void intel_old_crtc_state_disables(struct intel_atomic_state
*state
,
6736 struct intel_crtc_state
*old_crtc_state
,
6737 struct intel_crtc_state
*new_crtc_state
,
6738 struct intel_crtc
*crtc
)
6740 struct drm_i915_private
*dev_priv
= to_i915(state
->base
.dev
);
6743 * We need to disable pipe CRC before disabling the pipe,
6744 * or we race against vblank off.
6746 intel_crtc_disable_pipe_crc(crtc
);
6748 dev_priv
->display
.funcs
.display
->crtc_disable(state
, crtc
);
6749 crtc
->active
= false;
6750 intel_fbc_disable(crtc
);
6752 if (!new_crtc_state
->hw
.active
)
6753 intel_initial_watermarks(state
, crtc
);
6756 static void intel_commit_modeset_disables(struct intel_atomic_state
*state
)
6758 struct intel_crtc_state
*new_crtc_state
, *old_crtc_state
;
6759 struct intel_crtc
*crtc
;
6763 for_each_oldnew_intel_crtc_in_state(state
, crtc
, old_crtc_state
,
6764 new_crtc_state
, i
) {
6765 if (!intel_crtc_needs_modeset(new_crtc_state
))
6768 intel_pre_plane_update(state
, crtc
);
6770 if (!old_crtc_state
->hw
.active
)
6773 intel_crtc_disable_planes(state
, crtc
);
6776 /* Only disable port sync and MST slaves */
6777 for_each_oldnew_intel_crtc_in_state(state
, crtc
, old_crtc_state
,
6778 new_crtc_state
, i
) {
6779 if (!intel_crtc_needs_modeset(new_crtc_state
))
6782 if (!old_crtc_state
->hw
.active
)
6785 /* In case of Transcoder port Sync master slave CRTCs can be
6786 * assigned in any order and we need to make sure that
6787 * slave CRTCs are disabled first and then master CRTC since
6788 * Slave vblanks are masked till Master Vblanks.
6790 if (!is_trans_port_sync_slave(old_crtc_state
) &&
6791 !intel_dp_mst_is_slave_trans(old_crtc_state
) &&
6792 !intel_crtc_is_bigjoiner_slave(old_crtc_state
))
6795 intel_old_crtc_state_disables(state
, old_crtc_state
,
6796 new_crtc_state
, crtc
);
6797 handled
|= BIT(crtc
->pipe
);
6800 /* Disable everything else left on */
6801 for_each_oldnew_intel_crtc_in_state(state
, crtc
, old_crtc_state
,
6802 new_crtc_state
, i
) {
6803 if (!intel_crtc_needs_modeset(new_crtc_state
) ||
6804 (handled
& BIT(crtc
->pipe
)))
6807 if (!old_crtc_state
->hw
.active
)
6810 intel_old_crtc_state_disables(state
, old_crtc_state
,
6811 new_crtc_state
, crtc
);
6815 static void intel_commit_modeset_enables(struct intel_atomic_state
*state
)
6817 struct intel_crtc_state
*new_crtc_state
;
6818 struct intel_crtc
*crtc
;
6821 for_each_new_intel_crtc_in_state(state
, crtc
, new_crtc_state
, i
) {
6822 if (!new_crtc_state
->hw
.active
)
6825 intel_enable_crtc(state
, crtc
);
6826 intel_pre_update_crtc(state
, crtc
);
6829 for_each_new_intel_crtc_in_state(state
, crtc
, new_crtc_state
, i
) {
6830 if (!new_crtc_state
->hw
.active
)
6833 intel_update_crtc(state
, crtc
);
6837 static void skl_commit_modeset_enables(struct intel_atomic_state
*state
)
6839 struct drm_i915_private
*dev_priv
= to_i915(state
->base
.dev
);
6840 struct intel_crtc
*crtc
;
6841 struct intel_crtc_state
*old_crtc_state
, *new_crtc_state
;
6842 struct skl_ddb_entry entries
[I915_MAX_PIPES
] = {};
6843 u8 update_pipes
= 0, modeset_pipes
= 0;
6846 for_each_oldnew_intel_crtc_in_state(state
, crtc
, old_crtc_state
, new_crtc_state
, i
) {
6847 enum pipe pipe
= crtc
->pipe
;
6849 if (!new_crtc_state
->hw
.active
)
6852 /* ignore allocations for crtc's that have been turned off. */
6853 if (!intel_crtc_needs_modeset(new_crtc_state
)) {
6854 entries
[pipe
] = old_crtc_state
->wm
.skl
.ddb
;
6855 update_pipes
|= BIT(pipe
);
6857 modeset_pipes
|= BIT(pipe
);
6862 * Whenever the number of active pipes changes, we need to make sure we
6863 * update the pipes in the right order so that their ddb allocations
6864 * never overlap with each other between CRTC updates. Otherwise we'll
6865 * cause pipe underruns and other bad stuff.
6867 * So first lets enable all pipes that do not need a fullmodeset as
6868 * those don't have any external dependency.
6870 for_each_new_intel_crtc_in_state(state
, crtc
, new_crtc_state
, i
) {
6871 enum pipe pipe
= crtc
->pipe
;
6873 if ((update_pipes
& BIT(pipe
)) == 0)
6876 intel_pre_update_crtc(state
, crtc
);
6879 while (update_pipes
) {
6880 for_each_oldnew_intel_crtc_in_state(state
, crtc
, old_crtc_state
,
6881 new_crtc_state
, i
) {
6882 enum pipe pipe
= crtc
->pipe
;
6884 if ((update_pipes
& BIT(pipe
)) == 0)
6887 if (skl_ddb_allocation_overlaps(&new_crtc_state
->wm
.skl
.ddb
,
6888 entries
, I915_MAX_PIPES
, pipe
))
6891 entries
[pipe
] = new_crtc_state
->wm
.skl
.ddb
;
6892 update_pipes
&= ~BIT(pipe
);
6894 intel_update_crtc(state
, crtc
);
6897 * If this is an already active pipe, it's DDB changed,
6898 * and this isn't the last pipe that needs updating
6899 * then we need to wait for a vblank to pass for the
6900 * new ddb allocation to take effect.
6902 if (!skl_ddb_entry_equal(&new_crtc_state
->wm
.skl
.ddb
,
6903 &old_crtc_state
->wm
.skl
.ddb
) &&
6904 (update_pipes
| modeset_pipes
))
6905 intel_crtc_wait_for_next_vblank(crtc
);
6909 update_pipes
= modeset_pipes
;
6912 * Enable all pipes that needs a modeset and do not depends on other
6915 for_each_new_intel_crtc_in_state(state
, crtc
, new_crtc_state
, i
) {
6916 enum pipe pipe
= crtc
->pipe
;
6918 if ((modeset_pipes
& BIT(pipe
)) == 0)
6921 if (intel_dp_mst_is_slave_trans(new_crtc_state
) ||
6922 is_trans_port_sync_master(new_crtc_state
) ||
6923 intel_crtc_is_bigjoiner_master(new_crtc_state
))
6926 modeset_pipes
&= ~BIT(pipe
);
6928 intel_enable_crtc(state
, crtc
);
6932 * Then we enable all remaining pipes that depend on other
6933 * pipes: MST slaves and port sync masters, big joiner master
6935 for_each_new_intel_crtc_in_state(state
, crtc
, new_crtc_state
, i
) {
6936 enum pipe pipe
= crtc
->pipe
;
6938 if ((modeset_pipes
& BIT(pipe
)) == 0)
6941 modeset_pipes
&= ~BIT(pipe
);
6943 intel_enable_crtc(state
, crtc
);
6947 * Finally we do the plane updates/etc. for all pipes that got enabled.
6949 for_each_new_intel_crtc_in_state(state
, crtc
, new_crtc_state
, i
) {
6950 enum pipe pipe
= crtc
->pipe
;
6952 if ((update_pipes
& BIT(pipe
)) == 0)
6955 intel_pre_update_crtc(state
, crtc
);
6958 for_each_new_intel_crtc_in_state(state
, crtc
, new_crtc_state
, i
) {
6959 enum pipe pipe
= crtc
->pipe
;
6961 if ((update_pipes
& BIT(pipe
)) == 0)
6964 drm_WARN_ON(&dev_priv
->drm
, skl_ddb_allocation_overlaps(&new_crtc_state
->wm
.skl
.ddb
,
6965 entries
, I915_MAX_PIPES
, pipe
));
6967 entries
[pipe
] = new_crtc_state
->wm
.skl
.ddb
;
6968 update_pipes
&= ~BIT(pipe
);
6970 intel_update_crtc(state
, crtc
);
6973 drm_WARN_ON(&dev_priv
->drm
, modeset_pipes
);
6974 drm_WARN_ON(&dev_priv
->drm
, update_pipes
);
6977 static void intel_atomic_commit_fence_wait(struct intel_atomic_state
*intel_state
)
6979 struct drm_i915_private
*i915
= to_i915(intel_state
->base
.dev
);
6980 struct drm_plane
*plane
;
6981 struct drm_plane_state
*new_plane_state
;
6984 for_each_new_plane_in_state(&intel_state
->base
, plane
, new_plane_state
, i
) {
6985 if (new_plane_state
->fence
) {
6986 ret
= dma_fence_wait_timeout(new_plane_state
->fence
, false,
6987 i915_fence_timeout(i915
));
6991 dma_fence_put(new_plane_state
->fence
);
6992 new_plane_state
->fence
= NULL
;
6997 static void intel_atomic_cleanup_work(struct work_struct
*work
)
6999 struct intel_atomic_state
*state
=
7000 container_of(work
, struct intel_atomic_state
, base
.commit_work
);
7001 struct drm_i915_private
*i915
= to_i915(state
->base
.dev
);
7002 struct intel_crtc_state
*old_crtc_state
;
7003 struct intel_crtc
*crtc
;
7006 for_each_old_intel_crtc_in_state(state
, crtc
, old_crtc_state
, i
)
7007 intel_color_cleanup_commit(old_crtc_state
);
7009 drm_atomic_helper_cleanup_planes(&i915
->drm
, &state
->base
);
7010 drm_atomic_helper_commit_cleanup_done(&state
->base
);
7011 drm_atomic_state_put(&state
->base
);
7014 static void intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state
*state
)
7016 struct drm_i915_private
*i915
= to_i915(state
->base
.dev
);
7017 struct intel_plane
*plane
;
7018 struct intel_plane_state
*plane_state
;
7021 for_each_new_intel_plane_in_state(state
, plane
, plane_state
, i
) {
7022 struct drm_framebuffer
*fb
= plane_state
->hw
.fb
;
7029 cc_plane
= intel_fb_rc_ccs_cc_plane(fb
);
7034 * The layout of the fast clear color value expected by HW
7035 * (the DRM ABI requiring this value to be located in fb at
7036 * offset 0 of cc plane, plane #2 previous generations or
7037 * plane #1 for flat ccs):
7038 * - 4 x 4 bytes per-channel value
7039 * (in surface type specific float/int format provided by the fb user)
7040 * - 8 bytes native color value used by the display
7041 * (converted/written by GPU during a fast clear operation using the
7042 * above per-channel values)
7044 * The commit's FB prepare hook already ensured that FB obj is pinned and the
7045 * caller made sure that the object is synced wrt. the related color clear value
7048 ret
= i915_gem_object_read_from_page(intel_fb_obj(fb
),
7049 fb
->offsets
[cc_plane
] + 16,
7050 &plane_state
->ccval
,
7051 sizeof(plane_state
->ccval
));
7052 /* The above could only fail if the FB obj has an unexpected backing store type. */
7053 drm_WARN_ON(&i915
->drm
, ret
);
7057 static void intel_atomic_commit_tail(struct intel_atomic_state
*state
)
7059 struct drm_device
*dev
= state
->base
.dev
;
7060 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7061 struct intel_crtc_state
*new_crtc_state
, *old_crtc_state
;
7062 struct intel_crtc
*crtc
;
7063 struct intel_power_domain_mask put_domains
[I915_MAX_PIPES
] = {};
7064 intel_wakeref_t wakeref
= 0;
7067 intel_atomic_commit_fence_wait(state
);
7069 drm_atomic_helper_wait_for_dependencies(&state
->base
);
7070 drm_dp_mst_atomic_wait_for_dependencies(&state
->base
);
7071 intel_atomic_global_state_wait_for_dependencies(state
);
7074 * During full modesets we write a lot of registers, wait
7075 * for PLLs, etc. Doing that while DC states are enabled
7076 * is not a good idea.
7078 * During fastsets and other updates we also need to
7079 * disable DC states due to the following scenario:
7080 * 1. DC5 exit and PSR exit happen
7081 * 2. Some or all _noarm() registers are written
7082 * 3. Due to some long delay PSR is re-entered
7083 * 4. DC5 entry -> DMC saves the already written new
7084 * _noarm() registers and the old not yet written
7086 * 5. DC5 exit -> DMC restores a mixture of old and
7087 * new register values and arms the update
7088 * 6. PSR exit -> hardware latches a mixture of old and
7089 * new register values -> corrupted frame, or worse
7090 * 7. New _arm() registers are finally written
7091 * 8. Hardware finally latches a complete set of new
7092 * register values, and subsequent frames will be OK again
7094 * Also note that due to the pipe CSC hardware issues on
7095 * SKL/GLK DC states must remain off until the pipe CSC
7096 * state readout has happened. Otherwise we risk corrupting
7097 * the CSC latched register values with the readout (see
7098 * skl_read_csc() and skl_color_commit_noarm()).
7100 wakeref
= intel_display_power_get(dev_priv
, POWER_DOMAIN_DC_OFF
);
7102 intel_atomic_prepare_plane_clear_colors(state
);
7104 for_each_oldnew_intel_crtc_in_state(state
, crtc
, old_crtc_state
,
7105 new_crtc_state
, i
) {
7106 if (intel_crtc_needs_modeset(new_crtc_state
) ||
7107 intel_crtc_needs_fastset(new_crtc_state
))
7108 intel_modeset_get_crtc_power_domains(new_crtc_state
, &put_domains
[crtc
->pipe
]);
7111 intel_commit_modeset_disables(state
);
7113 /* FIXME: Eventually get rid of our crtc->config pointer */
7114 for_each_new_intel_crtc_in_state(state
, crtc
, new_crtc_state
, i
)
7115 crtc
->config
= new_crtc_state
;
7118 * In XE_LPD+ Pmdemand combines many parameters such as voltage index,
7119 * plls, cdclk frequency, QGV point selection parameter etc. Voltage
7120 * index, cdclk/ddiclk frequencies are supposed to be configured before
7121 * the cdclk config is set.
7123 intel_pmdemand_pre_plane_update(state
);
7125 if (state
->modeset
) {
7126 drm_atomic_helper_update_legacy_modeset_state(dev
, &state
->base
);
7128 intel_set_cdclk_pre_plane_update(state
);
7130 intel_modeset_verify_disabled(state
);
7133 intel_sagv_pre_plane_update(state
);
7135 /* Complete the events for pipes that have now been disabled */
7136 for_each_new_intel_crtc_in_state(state
, crtc
, new_crtc_state
, i
) {
7137 bool modeset
= intel_crtc_needs_modeset(new_crtc_state
);
7139 /* Complete events for now disable pipes here. */
7140 if (modeset
&& !new_crtc_state
->hw
.active
&& new_crtc_state
->uapi
.event
) {
7141 spin_lock_irq(&dev
->event_lock
);
7142 drm_crtc_send_vblank_event(&crtc
->base
,
7143 new_crtc_state
->uapi
.event
);
7144 spin_unlock_irq(&dev
->event_lock
);
7146 new_crtc_state
->uapi
.event
= NULL
;
7150 intel_encoders_update_prepare(state
);
7152 intel_dbuf_pre_plane_update(state
);
7153 intel_mbus_dbox_update(state
);
7155 for_each_new_intel_crtc_in_state(state
, crtc
, new_crtc_state
, i
) {
7156 if (new_crtc_state
->do_async_flip
)
7157 intel_crtc_enable_flip_done(state
, crtc
);
7160 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7161 dev_priv
->display
.funcs
.display
->commit_modeset_enables(state
);
7164 intel_set_cdclk_post_plane_update(state
);
7166 intel_wait_for_vblank_workers(state
);
7168 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
7169 * already, but still need the state for the delayed optimization. To
7171 * - wrap the optimization/post_plane_update stuff into a per-crtc work.
7172 * - schedule that vblank worker _before_ calling hw_done
7173 * - at the start of commit_tail, cancel it _synchrously
7174 * - switch over to the vblank wait helper in the core after that since
7175 * we don't need out special handling any more.
7177 drm_atomic_helper_wait_for_flip_done(dev
, &state
->base
);
7179 for_each_new_intel_crtc_in_state(state
, crtc
, new_crtc_state
, i
) {
7180 if (new_crtc_state
->do_async_flip
)
7181 intel_crtc_disable_flip_done(state
, crtc
);
7183 intel_color_wait_commit(new_crtc_state
);
7187 * Now that the vblank has passed, we can go ahead and program the
7188 * optimal watermarks on platforms that need two-step watermark
7191 * TODO: Move this (and other cleanup) to an async worker eventually.
7193 for_each_oldnew_intel_crtc_in_state(state
, crtc
, old_crtc_state
,
7194 new_crtc_state
, i
) {
7196 * Gen2 reports pipe underruns whenever all planes are disabled.
7197 * So re-enable underrun reporting after some planes get enabled.
7199 * We do this before .optimize_watermarks() so that we have a
7200 * chance of catching underruns with the intermediate watermarks
7201 * vs. the new plane configuration.
7203 if (DISPLAY_VER(dev_priv
) == 2 && planes_enabling(old_crtc_state
, new_crtc_state
))
7204 intel_set_cpu_fifo_underrun_reporting(dev_priv
, crtc
->pipe
, true);
7206 intel_optimize_watermarks(state
, crtc
);
7209 intel_dbuf_post_plane_update(state
);
7211 for_each_oldnew_intel_crtc_in_state(state
, crtc
, old_crtc_state
, new_crtc_state
, i
) {
7212 intel_post_plane_update(state
, crtc
);
7214 intel_modeset_put_crtc_power_domains(crtc
, &put_domains
[crtc
->pipe
]);
7216 intel_modeset_verify_crtc(state
, crtc
);
7218 /* Must be done after gamma readout due to HSW split gamma vs. IPS w/a */
7219 hsw_ips_post_update(state
, crtc
);
7222 * Activate DRRS after state readout to avoid
7223 * dp_m_n vs. dp_m2_n2 confusion on BDW+.
7225 intel_drrs_activate(new_crtc_state
);
7228 * DSB cleanup is done in cleanup_work aligning with framebuffer
7229 * cleanup. So copy and reset the dsb structure to sync with
7230 * commit_done and later do dsb cleanup in cleanup_work.
7232 * FIXME get rid of this funny new->old swapping
7234 old_crtc_state
->dsb
= fetch_and_zero(&new_crtc_state
->dsb
);
7237 /* Underruns don't always raise interrupts, so check manually */
7238 intel_check_cpu_fifo_underruns(dev_priv
);
7239 intel_check_pch_fifo_underruns(dev_priv
);
7242 intel_verify_planes(state
);
7244 intel_sagv_post_plane_update(state
);
7245 intel_pmdemand_post_plane_update(state
);
7247 drm_atomic_helper_commit_hw_done(&state
->base
);
7248 intel_atomic_global_state_commit_done(state
);
7250 if (state
->modeset
) {
7251 /* As one of the primary mmio accessors, KMS has a high
7252 * likelihood of triggering bugs in unclaimed access. After we
7253 * finish modesetting, see if an error has been flagged, and if
7254 * so enable debugging for the next modeset - and hope we catch
7257 intel_uncore_arm_unclaimed_mmio_detection(&dev_priv
->uncore
);
7260 * Delay re-enabling DC states by 17 ms to avoid the off->on->off
7261 * toggling overhead at and above 60 FPS.
7263 intel_display_power_put_async_delay(dev_priv
, POWER_DOMAIN_DC_OFF
, wakeref
, 17);
7264 intel_runtime_pm_put(&dev_priv
->runtime_pm
, state
->wakeref
);
7267 * Defer the cleanup of the old state to a separate worker to not
7268 * impede the current task (userspace for blocking modesets) that
7269 * are executed inline. For out-of-line asynchronous modesets/flips,
7270 * deferring to a new worker seems overkill, but we would place a
7271 * schedule point (cond_resched()) here anyway to keep latencies
7274 INIT_WORK(&state
->base
.commit_work
, intel_atomic_cleanup_work
);
7275 queue_work(system_highpri_wq
, &state
->base
.commit_work
);
7278 static void intel_atomic_commit_work(struct work_struct
*work
)
7280 struct intel_atomic_state
*state
=
7281 container_of(work
, struct intel_atomic_state
, base
.commit_work
);
7283 intel_atomic_commit_tail(state
);
7286 static void intel_atomic_track_fbs(struct intel_atomic_state
*state
)
7288 struct intel_plane_state
*old_plane_state
, *new_plane_state
;
7289 struct intel_plane
*plane
;
7292 for_each_oldnew_intel_plane_in_state(state
, plane
, old_plane_state
,
7294 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state
->hw
.fb
),
7295 to_intel_frontbuffer(new_plane_state
->hw
.fb
),
7296 plane
->frontbuffer_bit
);
7299 static int intel_atomic_setup_commit(struct intel_atomic_state
*state
, bool nonblock
)
7303 ret
= drm_atomic_helper_setup_commit(&state
->base
, nonblock
);
7307 ret
= intel_atomic_global_state_setup_commit(state
);
7314 static int intel_atomic_swap_state(struct intel_atomic_state
*state
)
7318 ret
= drm_atomic_helper_swap_state(&state
->base
, true);
7322 intel_atomic_swap_global_state(state
);
7324 intel_shared_dpll_swap_state(state
);
7326 intel_atomic_track_fbs(state
);
7331 int intel_atomic_commit(struct drm_device
*dev
, struct drm_atomic_state
*_state
,
7334 struct intel_atomic_state
*state
= to_intel_atomic_state(_state
);
7335 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7338 state
->wakeref
= intel_runtime_pm_get(&dev_priv
->runtime_pm
);
7341 * The intel_legacy_cursor_update() fast path takes care
7342 * of avoiding the vblank waits for simple cursor
7343 * movement and flips. For cursor on/off and size changes,
7344 * we want to perform the vblank waits so that watermark
7345 * updates happen during the correct frames. Gen9+ have
7346 * double buffered watermarks and so shouldn't need this.
7348 * Unset state->legacy_cursor_update before the call to
7349 * drm_atomic_helper_setup_commit() because otherwise
7350 * drm_atomic_helper_wait_for_flip_done() is a noop and
7351 * we get FIFO underruns because we didn't wait
7354 * FIXME doing watermarks and fb cleanup from a vblank worker
7355 * (assuming we had any) would solve these problems.
7357 if (DISPLAY_VER(dev_priv
) < 9 && state
->base
.legacy_cursor_update
) {
7358 struct intel_crtc_state
*new_crtc_state
;
7359 struct intel_crtc
*crtc
;
7362 for_each_new_intel_crtc_in_state(state
, crtc
, new_crtc_state
, i
)
7363 if (new_crtc_state
->wm
.need_postvbl_update
||
7364 new_crtc_state
->update_wm_post
)
7365 state
->base
.legacy_cursor_update
= false;
7368 ret
= intel_atomic_prepare_commit(state
);
7370 drm_dbg_atomic(&dev_priv
->drm
,
7371 "Preparing state failed with %i\n", ret
);
7372 intel_runtime_pm_put(&dev_priv
->runtime_pm
, state
->wakeref
);
7376 ret
= intel_atomic_setup_commit(state
, nonblock
);
7378 ret
= intel_atomic_swap_state(state
);
7381 struct intel_crtc_state
*new_crtc_state
;
7382 struct intel_crtc
*crtc
;
7385 for_each_new_intel_crtc_in_state(state
, crtc
, new_crtc_state
, i
)
7386 intel_color_cleanup_commit(new_crtc_state
);
7388 drm_atomic_helper_unprepare_planes(dev
, &state
->base
);
7389 intel_runtime_pm_put(&dev_priv
->runtime_pm
, state
->wakeref
);
7393 drm_atomic_state_get(&state
->base
);
7394 INIT_WORK(&state
->base
.commit_work
, intel_atomic_commit_work
);
7396 if (nonblock
&& state
->modeset
) {
7397 queue_work(dev_priv
->display
.wq
.modeset
, &state
->base
.commit_work
);
7398 } else if (nonblock
) {
7399 queue_work(dev_priv
->display
.wq
.flip
, &state
->base
.commit_work
);
7402 flush_workqueue(dev_priv
->display
.wq
.modeset
);
7403 intel_atomic_commit_tail(state
);
7410 * intel_plane_destroy - destroy a plane
7411 * @plane: plane to destroy
7413 * Common destruction function for all types of planes (primary, cursor,
7416 void intel_plane_destroy(struct drm_plane
*plane
)
7418 drm_plane_cleanup(plane
);
7419 kfree(to_intel_plane(plane
));
7422 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device
*dev
, void *data
,
7423 struct drm_file
*file
)
7425 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
7426 struct drm_crtc
*drmmode_crtc
;
7427 struct intel_crtc
*crtc
;
7429 drmmode_crtc
= drm_crtc_find(dev
, file
, pipe_from_crtc_id
->crtc_id
);
7433 crtc
= to_intel_crtc(drmmode_crtc
);
7434 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
7439 static u32
intel_encoder_possible_clones(struct intel_encoder
*encoder
)
7441 struct drm_device
*dev
= encoder
->base
.dev
;
7442 struct intel_encoder
*source_encoder
;
7443 u32 possible_clones
= 0;
7445 for_each_intel_encoder(dev
, source_encoder
) {
7446 if (encoders_cloneable(encoder
, source_encoder
))
7447 possible_clones
|= drm_encoder_mask(&source_encoder
->base
);
7450 return possible_clones
;
7453 static u32
intel_encoder_possible_crtcs(struct intel_encoder
*encoder
)
7455 struct drm_device
*dev
= encoder
->base
.dev
;
7456 struct intel_crtc
*crtc
;
7457 u32 possible_crtcs
= 0;
7459 for_each_intel_crtc_in_pipe_mask(dev
, crtc
, encoder
->pipe_mask
)
7460 possible_crtcs
|= drm_crtc_mask(&crtc
->base
);
7462 return possible_crtcs
;
7465 static bool ilk_has_edp_a(struct drm_i915_private
*dev_priv
)
7467 if (!IS_MOBILE(dev_priv
))
7470 if ((intel_de_read(dev_priv
, DP_A
) & DP_DETECTED
) == 0)
7473 if (IS_IRONLAKE(dev_priv
) && (intel_de_read(dev_priv
, FUSE_STRAP
) & ILK_eDP_A_DISABLE
))
7479 static bool intel_ddi_crt_present(struct drm_i915_private
*dev_priv
)
7481 if (DISPLAY_VER(dev_priv
) >= 9)
7484 if (IS_HASWELL_ULT(dev_priv
) || IS_BROADWELL_ULT(dev_priv
))
7487 if (HAS_PCH_LPT_H(dev_priv
) &&
7488 intel_de_read(dev_priv
, SFUSE_STRAP
) & SFUSE_STRAP_CRT_DISABLED
)
7491 /* DDI E can't be used if DDI A requires 4 lanes */
7492 if (intel_de_read(dev_priv
, DDI_BUF_CTL(PORT_A
)) & DDI_A_4_LANES
)
7495 if (!dev_priv
->display
.vbt
.int_crt_support
)
7501 bool assert_port_valid(struct drm_i915_private
*i915
, enum port port
)
7503 return !drm_WARN(&i915
->drm
, !(DISPLAY_RUNTIME_INFO(i915
)->port_mask
& BIT(port
)),
7504 "Platform does not support port %c\n", port_name(port
));
7507 void intel_setup_outputs(struct drm_i915_private
*dev_priv
)
7509 struct intel_encoder
*encoder
;
7510 bool dpd_is_edp
= false;
7512 intel_pps_unlock_regs_wa(dev_priv
);
7514 if (!HAS_DISPLAY(dev_priv
))
7517 if (HAS_DDI(dev_priv
)) {
7518 if (intel_ddi_crt_present(dev_priv
))
7519 intel_crt_init(dev_priv
);
7521 intel_bios_for_each_encoder(dev_priv
, intel_ddi_init
);
7523 if (IS_GEMINILAKE(dev_priv
) || IS_BROXTON(dev_priv
))
7524 vlv_dsi_init(dev_priv
);
7525 } else if (HAS_PCH_SPLIT(dev_priv
)) {
7529 * intel_edp_init_connector() depends on this completing first,
7530 * to prevent the registration of both eDP and LVDS and the
7531 * incorrect sharing of the PPS.
7533 intel_lvds_init(dev_priv
);
7534 intel_crt_init(dev_priv
);
7536 dpd_is_edp
= intel_dp_is_port_edp(dev_priv
, PORT_D
);
7538 if (ilk_has_edp_a(dev_priv
))
7539 g4x_dp_init(dev_priv
, DP_A
, PORT_A
);
7541 if (intel_de_read(dev_priv
, PCH_HDMIB
) & SDVO_DETECTED
) {
7542 /* PCH SDVOB multiplex with HDMIB */
7543 found
= intel_sdvo_init(dev_priv
, PCH_SDVOB
, PORT_B
);
7545 g4x_hdmi_init(dev_priv
, PCH_HDMIB
, PORT_B
);
7546 if (!found
&& (intel_de_read(dev_priv
, PCH_DP_B
) & DP_DETECTED
))
7547 g4x_dp_init(dev_priv
, PCH_DP_B
, PORT_B
);
7550 if (intel_de_read(dev_priv
, PCH_HDMIC
) & SDVO_DETECTED
)
7551 g4x_hdmi_init(dev_priv
, PCH_HDMIC
, PORT_C
);
7553 if (!dpd_is_edp
&& intel_de_read(dev_priv
, PCH_HDMID
) & SDVO_DETECTED
)
7554 g4x_hdmi_init(dev_priv
, PCH_HDMID
, PORT_D
);
7556 if (intel_de_read(dev_priv
, PCH_DP_C
) & DP_DETECTED
)
7557 g4x_dp_init(dev_priv
, PCH_DP_C
, PORT_C
);
7559 if (intel_de_read(dev_priv
, PCH_DP_D
) & DP_DETECTED
)
7560 g4x_dp_init(dev_priv
, PCH_DP_D
, PORT_D
);
7561 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
7562 bool has_edp
, has_port
;
7564 if (IS_VALLEYVIEW(dev_priv
) && dev_priv
->display
.vbt
.int_crt_support
)
7565 intel_crt_init(dev_priv
);
7568 * The DP_DETECTED bit is the latched state of the DDC
7569 * SDA pin at boot. However since eDP doesn't require DDC
7570 * (no way to plug in a DP->HDMI dongle) the DDC pins for
7571 * eDP ports may have been muxed to an alternate function.
7572 * Thus we can't rely on the DP_DETECTED bit alone to detect
7573 * eDP ports. Consult the VBT as well as DP_DETECTED to
7576 * Sadly the straps seem to be missing sometimes even for HDMI
7577 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
7578 * and VBT for the presence of the port. Additionally we can't
7579 * trust the port type the VBT declares as we've seen at least
7580 * HDMI ports that the VBT claim are DP or eDP.
7582 has_edp
= intel_dp_is_port_edp(dev_priv
, PORT_B
);
7583 has_port
= intel_bios_is_port_present(dev_priv
, PORT_B
);
7584 if (intel_de_read(dev_priv
, VLV_DP_B
) & DP_DETECTED
|| has_port
)
7585 has_edp
&= g4x_dp_init(dev_priv
, VLV_DP_B
, PORT_B
);
7586 if ((intel_de_read(dev_priv
, VLV_HDMIB
) & SDVO_DETECTED
|| has_port
) && !has_edp
)
7587 g4x_hdmi_init(dev_priv
, VLV_HDMIB
, PORT_B
);
7589 has_edp
= intel_dp_is_port_edp(dev_priv
, PORT_C
);
7590 has_port
= intel_bios_is_port_present(dev_priv
, PORT_C
);
7591 if (intel_de_read(dev_priv
, VLV_DP_C
) & DP_DETECTED
|| has_port
)
7592 has_edp
&= g4x_dp_init(dev_priv
, VLV_DP_C
, PORT_C
);
7593 if ((intel_de_read(dev_priv
, VLV_HDMIC
) & SDVO_DETECTED
|| has_port
) && !has_edp
)
7594 g4x_hdmi_init(dev_priv
, VLV_HDMIC
, PORT_C
);
7596 if (IS_CHERRYVIEW(dev_priv
)) {
7598 * eDP not supported on port D,
7599 * so no need to worry about it
7601 has_port
= intel_bios_is_port_present(dev_priv
, PORT_D
);
7602 if (intel_de_read(dev_priv
, CHV_DP_D
) & DP_DETECTED
|| has_port
)
7603 g4x_dp_init(dev_priv
, CHV_DP_D
, PORT_D
);
7604 if (intel_de_read(dev_priv
, CHV_HDMID
) & SDVO_DETECTED
|| has_port
)
7605 g4x_hdmi_init(dev_priv
, CHV_HDMID
, PORT_D
);
7608 vlv_dsi_init(dev_priv
);
7609 } else if (IS_PINEVIEW(dev_priv
)) {
7610 intel_lvds_init(dev_priv
);
7611 intel_crt_init(dev_priv
);
7612 } else if (IS_DISPLAY_VER(dev_priv
, 3, 4)) {
7615 if (IS_MOBILE(dev_priv
))
7616 intel_lvds_init(dev_priv
);
7618 intel_crt_init(dev_priv
);
7620 if (intel_de_read(dev_priv
, GEN3_SDVOB
) & SDVO_DETECTED
) {
7621 drm_dbg_kms(&dev_priv
->drm
, "probing SDVOB\n");
7622 found
= intel_sdvo_init(dev_priv
, GEN3_SDVOB
, PORT_B
);
7623 if (!found
&& IS_G4X(dev_priv
)) {
7624 drm_dbg_kms(&dev_priv
->drm
,
7625 "probing HDMI on SDVOB\n");
7626 g4x_hdmi_init(dev_priv
, GEN4_HDMIB
, PORT_B
);
7629 if (!found
&& IS_G4X(dev_priv
))
7630 g4x_dp_init(dev_priv
, DP_B
, PORT_B
);
7633 /* Before G4X SDVOC doesn't have its own detect register */
7635 if (intel_de_read(dev_priv
, GEN3_SDVOB
) & SDVO_DETECTED
) {
7636 drm_dbg_kms(&dev_priv
->drm
, "probing SDVOC\n");
7637 found
= intel_sdvo_init(dev_priv
, GEN3_SDVOC
, PORT_C
);
7640 if (!found
&& (intel_de_read(dev_priv
, GEN3_SDVOC
) & SDVO_DETECTED
)) {
7642 if (IS_G4X(dev_priv
)) {
7643 drm_dbg_kms(&dev_priv
->drm
,
7644 "probing HDMI on SDVOC\n");
7645 g4x_hdmi_init(dev_priv
, GEN4_HDMIC
, PORT_C
);
7647 if (IS_G4X(dev_priv
))
7648 g4x_dp_init(dev_priv
, DP_C
, PORT_C
);
7651 if (IS_G4X(dev_priv
) && (intel_de_read(dev_priv
, DP_D
) & DP_DETECTED
))
7652 g4x_dp_init(dev_priv
, DP_D
, PORT_D
);
7654 if (SUPPORTS_TV(dev_priv
))
7655 intel_tv_init(dev_priv
);
7656 } else if (DISPLAY_VER(dev_priv
) == 2) {
7657 if (IS_I85X(dev_priv
))
7658 intel_lvds_init(dev_priv
);
7660 intel_crt_init(dev_priv
);
7661 intel_dvo_init(dev_priv
);
7664 for_each_intel_encoder(&dev_priv
->drm
, encoder
) {
7665 encoder
->base
.possible_crtcs
=
7666 intel_encoder_possible_crtcs(encoder
);
7667 encoder
->base
.possible_clones
=
7668 intel_encoder_possible_clones(encoder
);
7671 intel_init_pch_refclk(dev_priv
);
7673 drm_helper_move_panel_connectors_to_head(&dev_priv
->drm
);
7676 static int max_dotclock(struct drm_i915_private
*i915
)
7678 int max_dotclock
= i915
->max_dotclk_freq
;
7680 /* icl+ might use bigjoiner */
7681 if (DISPLAY_VER(i915
) >= 11)
7684 return max_dotclock
;
7687 enum drm_mode_status
intel_mode_valid(struct drm_device
*dev
,
7688 const struct drm_display_mode
*mode
)
7690 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7691 int hdisplay_max
, htotal_max
;
7692 int vdisplay_max
, vtotal_max
;
7695 * Can't reject DBLSCAN here because Xorg ddxen can add piles
7696 * of DBLSCAN modes to the output's mode list when they detect
7697 * the scaling mode property on the connector. And they don't
7698 * ask the kernel to validate those modes in any way until
7699 * modeset time at which point the client gets a protocol error.
7700 * So in order to not upset those clients we silently ignore the
7701 * DBLSCAN flag on such connectors. For other connectors we will
7702 * reject modes with the DBLSCAN flag in encoder->compute_config().
7703 * And we always reject DBLSCAN modes in connector->mode_valid()
7704 * as we never want such modes on the connector's mode list.
7707 if (mode
->vscan
> 1)
7708 return MODE_NO_VSCAN
;
7710 if (mode
->flags
& DRM_MODE_FLAG_HSKEW
)
7711 return MODE_H_ILLEGAL
;
7713 if (mode
->flags
& (DRM_MODE_FLAG_CSYNC
|
7714 DRM_MODE_FLAG_NCSYNC
|
7715 DRM_MODE_FLAG_PCSYNC
))
7718 if (mode
->flags
& (DRM_MODE_FLAG_BCAST
|
7719 DRM_MODE_FLAG_PIXMUX
|
7720 DRM_MODE_FLAG_CLKDIV2
))
7724 * Reject clearly excessive dotclocks early to
7725 * avoid having to worry about huge integers later.
7727 if (mode
->clock
> max_dotclock(dev_priv
))
7728 return MODE_CLOCK_HIGH
;
7730 /* Transcoder timing limits */
7731 if (DISPLAY_VER(dev_priv
) >= 11) {
7732 hdisplay_max
= 16384;
7733 vdisplay_max
= 8192;
7736 } else if (DISPLAY_VER(dev_priv
) >= 9 ||
7737 IS_BROADWELL(dev_priv
) || IS_HASWELL(dev_priv
)) {
7738 hdisplay_max
= 8192; /* FDI max 4096 handled elsewhere */
7739 vdisplay_max
= 4096;
7742 } else if (DISPLAY_VER(dev_priv
) >= 3) {
7743 hdisplay_max
= 4096;
7744 vdisplay_max
= 4096;
7748 hdisplay_max
= 2048;
7749 vdisplay_max
= 2048;
7754 if (mode
->hdisplay
> hdisplay_max
||
7755 mode
->hsync_start
> htotal_max
||
7756 mode
->hsync_end
> htotal_max
||
7757 mode
->htotal
> htotal_max
)
7758 return MODE_H_ILLEGAL
;
7760 if (mode
->vdisplay
> vdisplay_max
||
7761 mode
->vsync_start
> vtotal_max
||
7762 mode
->vsync_end
> vtotal_max
||
7763 mode
->vtotal
> vtotal_max
)
7764 return MODE_V_ILLEGAL
;
7769 enum drm_mode_status
intel_cpu_transcoder_mode_valid(struct drm_i915_private
*dev_priv
,
7770 const struct drm_display_mode
*mode
)
7773 * Additional transcoder timing limits,
7774 * excluding BXT/GLK DSI transcoders.
7776 if (DISPLAY_VER(dev_priv
) >= 5) {
7777 if (mode
->hdisplay
< 64 ||
7778 mode
->htotal
- mode
->hdisplay
< 32)
7779 return MODE_H_ILLEGAL
;
7781 if (mode
->vtotal
- mode
->vdisplay
< 5)
7782 return MODE_V_ILLEGAL
;
7784 if (mode
->htotal
- mode
->hdisplay
< 32)
7785 return MODE_H_ILLEGAL
;
7787 if (mode
->vtotal
- mode
->vdisplay
< 3)
7788 return MODE_V_ILLEGAL
;
7792 * Cantiga+ cannot handle modes with a hsync front porch of 0.
7793 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
7795 if ((DISPLAY_VER(dev_priv
) >= 5 || IS_G4X(dev_priv
)) &&
7796 mode
->hsync_start
== mode
->hdisplay
)
7797 return MODE_H_ILLEGAL
;
7802 enum drm_mode_status
7803 intel_mode_valid_max_plane_size(struct drm_i915_private
*dev_priv
,
7804 const struct drm_display_mode
*mode
,
7807 int plane_width_max
, plane_height_max
;
7810 * intel_mode_valid() should be
7811 * sufficient on older platforms.
7813 if (DISPLAY_VER(dev_priv
) < 9)
7817 * Most people will probably want a fullscreen
7818 * plane so let's not advertize modes that are
7821 if (DISPLAY_VER(dev_priv
) >= 11) {
7822 plane_width_max
= 5120 << bigjoiner
;
7823 plane_height_max
= 4320;
7825 plane_width_max
= 5120;
7826 plane_height_max
= 4096;
7829 if (mode
->hdisplay
> plane_width_max
)
7830 return MODE_H_ILLEGAL
;
7832 if (mode
->vdisplay
> plane_height_max
)
7833 return MODE_V_ILLEGAL
;
7838 static const struct intel_display_funcs skl_display_funcs
= {
7839 .get_pipe_config
= hsw_get_pipe_config
,
7840 .crtc_enable
= hsw_crtc_enable
,
7841 .crtc_disable
= hsw_crtc_disable
,
7842 .commit_modeset_enables
= skl_commit_modeset_enables
,
7843 .get_initial_plane_config
= skl_get_initial_plane_config
,
7844 .fixup_initial_plane_config
= skl_fixup_initial_plane_config
,
7847 static const struct intel_display_funcs ddi_display_funcs
= {
7848 .get_pipe_config
= hsw_get_pipe_config
,
7849 .crtc_enable
= hsw_crtc_enable
,
7850 .crtc_disable
= hsw_crtc_disable
,
7851 .commit_modeset_enables
= intel_commit_modeset_enables
,
7852 .get_initial_plane_config
= i9xx_get_initial_plane_config
,
7853 .fixup_initial_plane_config
= i9xx_fixup_initial_plane_config
,
7856 static const struct intel_display_funcs pch_split_display_funcs
= {
7857 .get_pipe_config
= ilk_get_pipe_config
,
7858 .crtc_enable
= ilk_crtc_enable
,
7859 .crtc_disable
= ilk_crtc_disable
,
7860 .commit_modeset_enables
= intel_commit_modeset_enables
,
7861 .get_initial_plane_config
= i9xx_get_initial_plane_config
,
7862 .fixup_initial_plane_config
= i9xx_fixup_initial_plane_config
,
7865 static const struct intel_display_funcs vlv_display_funcs
= {
7866 .get_pipe_config
= i9xx_get_pipe_config
,
7867 .crtc_enable
= valleyview_crtc_enable
,
7868 .crtc_disable
= i9xx_crtc_disable
,
7869 .commit_modeset_enables
= intel_commit_modeset_enables
,
7870 .get_initial_plane_config
= i9xx_get_initial_plane_config
,
7871 .fixup_initial_plane_config
= i9xx_fixup_initial_plane_config
,
7874 static const struct intel_display_funcs i9xx_display_funcs
= {
7875 .get_pipe_config
= i9xx_get_pipe_config
,
7876 .crtc_enable
= i9xx_crtc_enable
,
7877 .crtc_disable
= i9xx_crtc_disable
,
7878 .commit_modeset_enables
= intel_commit_modeset_enables
,
7879 .get_initial_plane_config
= i9xx_get_initial_plane_config
,
7880 .fixup_initial_plane_config
= i9xx_fixup_initial_plane_config
,
7884 * intel_init_display_hooks - initialize the display modesetting hooks
7885 * @dev_priv: device private
7887 void intel_init_display_hooks(struct drm_i915_private
*dev_priv
)
7889 if (DISPLAY_VER(dev_priv
) >= 9) {
7890 dev_priv
->display
.funcs
.display
= &skl_display_funcs
;
7891 } else if (HAS_DDI(dev_priv
)) {
7892 dev_priv
->display
.funcs
.display
= &ddi_display_funcs
;
7893 } else if (HAS_PCH_SPLIT(dev_priv
)) {
7894 dev_priv
->display
.funcs
.display
= &pch_split_display_funcs
;
7895 } else if (IS_CHERRYVIEW(dev_priv
) ||
7896 IS_VALLEYVIEW(dev_priv
)) {
7897 dev_priv
->display
.funcs
.display
= &vlv_display_funcs
;
7899 dev_priv
->display
.funcs
.display
= &i9xx_display_funcs
;
7903 int intel_initial_commit(struct drm_device
*dev
)
7905 struct drm_atomic_state
*state
= NULL
;
7906 struct drm_modeset_acquire_ctx ctx
;
7907 struct intel_crtc
*crtc
;
7910 state
= drm_atomic_state_alloc(dev
);
7914 drm_modeset_acquire_init(&ctx
, 0);
7916 state
->acquire_ctx
= &ctx
;
7917 to_intel_atomic_state(state
)->internal
= true;
7920 for_each_intel_crtc(dev
, crtc
) {
7921 struct intel_crtc_state
*crtc_state
=
7922 intel_atomic_get_crtc_state(state
, crtc
);
7924 if (IS_ERR(crtc_state
)) {
7925 ret
= PTR_ERR(crtc_state
);
7929 if (crtc_state
->hw
.active
) {
7930 struct intel_encoder
*encoder
;
7932 ret
= drm_atomic_add_affected_planes(state
, &crtc
->base
);
7937 * FIXME hack to force a LUT update to avoid the
7938 * plane update forcing the pipe gamma on without
7939 * having a proper LUT loaded. Remove once we
7940 * have readout for pipe gamma enable.
7942 crtc_state
->uapi
.color_mgmt_changed
= true;
7944 for_each_intel_encoder_mask(dev
, encoder
,
7945 crtc_state
->uapi
.encoder_mask
) {
7946 if (encoder
->initial_fastset_check
&&
7947 !encoder
->initial_fastset_check(encoder
, crtc_state
)) {
7948 ret
= drm_atomic_add_affected_connectors(state
,
7957 ret
= drm_atomic_commit(state
);
7960 if (ret
== -EDEADLK
) {
7961 drm_atomic_state_clear(state
);
7962 drm_modeset_backoff(&ctx
);
7966 drm_atomic_state_put(state
);
7968 drm_modeset_drop_locks(&ctx
);
7969 drm_modeset_acquire_fini(&ctx
);
7974 void i830_enable_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
7976 struct intel_crtc
*crtc
= intel_crtc_for_pipe(dev_priv
, pipe
);
7977 enum transcoder cpu_transcoder
= (enum transcoder
)pipe
;
7978 /* 640x480@60Hz, ~25175 kHz */
7979 struct dpll clock
= {
7989 drm_WARN_ON(&dev_priv
->drm
,
7990 i9xx_calc_dpll_params(48000, &clock
) != 25154);
7992 drm_dbg_kms(&dev_priv
->drm
,
7993 "enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
7994 pipe_name(pipe
), clock
.vco
, clock
.dot
);
7996 fp
= i9xx_dpll_compute_fp(&clock
);
7997 dpll
= DPLL_DVO_2X_MODE
|
7999 ((clock
.p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
) |
8000 PLL_P2_DIVIDE_BY_4
|
8001 PLL_REF_INPUT_DREFCLK
|
8004 intel_de_write(dev_priv
, TRANS_HTOTAL(cpu_transcoder
),
8005 HACTIVE(640 - 1) | HTOTAL(800 - 1));
8006 intel_de_write(dev_priv
, TRANS_HBLANK(cpu_transcoder
),
8007 HBLANK_START(640 - 1) | HBLANK_END(800 - 1));
8008 intel_de_write(dev_priv
, TRANS_HSYNC(cpu_transcoder
),
8009 HSYNC_START(656 - 1) | HSYNC_END(752 - 1));
8010 intel_de_write(dev_priv
, TRANS_VTOTAL(cpu_transcoder
),
8011 VACTIVE(480 - 1) | VTOTAL(525 - 1));
8012 intel_de_write(dev_priv
, TRANS_VBLANK(cpu_transcoder
),
8013 VBLANK_START(480 - 1) | VBLANK_END(525 - 1));
8014 intel_de_write(dev_priv
, TRANS_VSYNC(cpu_transcoder
),
8015 VSYNC_START(490 - 1) | VSYNC_END(492 - 1));
8016 intel_de_write(dev_priv
, PIPESRC(pipe
),
8017 PIPESRC_WIDTH(640 - 1) | PIPESRC_HEIGHT(480 - 1));
8019 intel_de_write(dev_priv
, FP0(pipe
), fp
);
8020 intel_de_write(dev_priv
, FP1(pipe
), fp
);
8023 * Apparently we need to have VGA mode enabled prior to changing
8024 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
8025 * dividers, even though the register value does change.
8027 intel_de_write(dev_priv
, DPLL(pipe
), dpll
& ~DPLL_VGA_MODE_DIS
);
8028 intel_de_write(dev_priv
, DPLL(pipe
), dpll
);
8030 /* Wait for the clocks to stabilize. */
8031 intel_de_posting_read(dev_priv
, DPLL(pipe
));
8034 /* The pixel multiplier can only be updated once the
8035 * DPLL is enabled and the clocks are stable.
8037 * So write it again.
8039 intel_de_write(dev_priv
, DPLL(pipe
), dpll
);
8041 /* We do this three times for luck */
8042 for (i
= 0; i
< 3 ; i
++) {
8043 intel_de_write(dev_priv
, DPLL(pipe
), dpll
);
8044 intel_de_posting_read(dev_priv
, DPLL(pipe
));
8045 udelay(150); /* wait for warmup */
8048 intel_de_write(dev_priv
, TRANSCONF(pipe
), TRANSCONF_ENABLE
);
8049 intel_de_posting_read(dev_priv
, TRANSCONF(pipe
));
8051 intel_wait_for_pipe_scanline_moving(crtc
);
8054 void i830_disable_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
8056 struct intel_crtc
*crtc
= intel_crtc_for_pipe(dev_priv
, pipe
);
8058 drm_dbg_kms(&dev_priv
->drm
, "disabling pipe %c due to force quirk\n",
8061 drm_WARN_ON(&dev_priv
->drm
,
8062 intel_de_read(dev_priv
, DSPCNTR(PLANE_A
)) & DISP_ENABLE
);
8063 drm_WARN_ON(&dev_priv
->drm
,
8064 intel_de_read(dev_priv
, DSPCNTR(PLANE_B
)) & DISP_ENABLE
);
8065 drm_WARN_ON(&dev_priv
->drm
,
8066 intel_de_read(dev_priv
, DSPCNTR(PLANE_C
)) & DISP_ENABLE
);
8067 drm_WARN_ON(&dev_priv
->drm
,
8068 intel_de_read(dev_priv
, CURCNTR(PIPE_A
)) & MCURSOR_MODE_MASK
);
8069 drm_WARN_ON(&dev_priv
->drm
,
8070 intel_de_read(dev_priv
, CURCNTR(PIPE_B
)) & MCURSOR_MODE_MASK
);
8072 intel_de_write(dev_priv
, TRANSCONF(pipe
), 0);
8073 intel_de_posting_read(dev_priv
, TRANSCONF(pipe
));
8075 intel_wait_for_pipe_scanline_stopped(crtc
);
8077 intel_de_write(dev_priv
, DPLL(pipe
), DPLL_VGA_MODE_DIS
);
8078 intel_de_posting_read(dev_priv
, DPLL(pipe
));
8081 void intel_hpd_poll_fini(struct drm_i915_private
*i915
)
8083 struct intel_connector
*connector
;
8084 struct drm_connector_list_iter conn_iter
;
8086 /* Kill all the work that may have been queued by hpd. */
8087 drm_connector_list_iter_begin(&i915
->drm
, &conn_iter
);
8088 for_each_intel_connector_iter(connector
, &conn_iter
) {
8089 if (connector
->modeset_retry_work
.func
&&
8090 cancel_work_sync(&connector
->modeset_retry_work
))
8091 drm_connector_put(&connector
->base
);
8092 if (connector
->hdcp
.shim
) {
8093 cancel_delayed_work_sync(&connector
->hdcp
.check_work
);
8094 cancel_work_sync(&connector
->hdcp
.prop_work
);
8097 drm_connector_list_iter_end(&conn_iter
);
8100 bool intel_scanout_needs_vtd_wa(struct drm_i915_private
*i915
)
8102 return DISPLAY_VER(i915
) >= 6 && i915_vtd_active(i915
);