1 /* SPDX-License-Identifier: MIT */
3 * Copyright (C) 2020 Google, Inc.
6 * Sean Paul <seanpaul@chromium.org>
9 #include <drm/display/drm_dp_helper.h>
10 #include <drm/display/drm_dp_mst_helper.h>
11 #include <drm/display/drm_hdcp_helper.h>
12 #include <drm/drm_print.h>
15 #include "intel_ddi.h"
17 #include "intel_display_types.h"
19 #include "intel_dp_hdcp.h"
20 #include "intel_hdcp.h"
21 #include "intel_hdcp_regs.h"
23 static u32
transcoder_to_stream_enc_status(enum transcoder cpu_transcoder
)
25 switch (cpu_transcoder
) {
27 return HDCP_STATUS_STREAM_A_ENC
;
29 return HDCP_STATUS_STREAM_B_ENC
;
31 return HDCP_STATUS_STREAM_C_ENC
;
33 return HDCP_STATUS_STREAM_D_ENC
;
39 static void intel_dp_hdcp_wait_for_cp_irq(struct intel_connector
*connector
,
42 struct intel_hdcp
*hdcp
= &connector
->hdcp
;
45 #define C (hdcp->cp_irq_count_cached != atomic_read(&hdcp->cp_irq_count))
46 ret
= wait_event_interruptible_timeout(hdcp
->cp_irq_queue
, C
,
47 msecs_to_jiffies(timeout
));
50 drm_dbg_kms(connector
->base
.dev
,
51 "Timedout at waiting for CP_IRQ\n");
55 int intel_dp_hdcp_write_an_aksv(struct intel_digital_port
*dig_port
,
58 struct drm_i915_private
*i915
= to_i915(dig_port
->base
.base
.dev
);
59 u8 aksv
[DRM_HDCP_KSV_LEN
] = {};
62 /* Output An first, that's easy */
63 dpcd_ret
= drm_dp_dpcd_write(&dig_port
->dp
.aux
, DP_AUX_HDCP_AN
,
65 if (dpcd_ret
!= DRM_HDCP_AN_LEN
) {
66 drm_dbg_kms(&i915
->drm
,
67 "Failed to write An over DP/AUX (%zd)\n",
69 return dpcd_ret
>= 0 ? -EIO
: dpcd_ret
;
73 * Since Aksv is Oh-So-Secret, we can't access it in software. So we
74 * send an empty buffer of the correct length through the DP helpers. On
75 * the other side, in the transfer hook, we'll generate a flag based on
76 * the destination address which will tickle the hardware to output the
77 * Aksv on our behalf after the header is sent.
79 dpcd_ret
= drm_dp_dpcd_write(&dig_port
->dp
.aux
, DP_AUX_HDCP_AKSV
,
80 aksv
, DRM_HDCP_KSV_LEN
);
81 if (dpcd_ret
!= DRM_HDCP_KSV_LEN
) {
82 drm_dbg_kms(&i915
->drm
,
83 "Failed to write Aksv over DP/AUX (%zd)\n",
85 return dpcd_ret
>= 0 ? -EIO
: dpcd_ret
;
90 static int intel_dp_hdcp_read_bksv(struct intel_digital_port
*dig_port
,
93 struct drm_i915_private
*i915
= to_i915(dig_port
->base
.base
.dev
);
96 ret
= drm_dp_dpcd_read(&dig_port
->dp
.aux
, DP_AUX_HDCP_BKSV
, bksv
,
98 if (ret
!= DRM_HDCP_KSV_LEN
) {
99 drm_dbg_kms(&i915
->drm
,
100 "Read Bksv from DP/AUX failed (%zd)\n", ret
);
101 return ret
>= 0 ? -EIO
: ret
;
106 static int intel_dp_hdcp_read_bstatus(struct intel_digital_port
*dig_port
,
109 struct drm_i915_private
*i915
= to_i915(dig_port
->base
.base
.dev
);
113 * For some reason the HDMI and DP HDCP specs call this register
114 * definition by different names. In the HDMI spec, it's called BSTATUS,
115 * but in DP it's called BINFO.
117 ret
= drm_dp_dpcd_read(&dig_port
->dp
.aux
, DP_AUX_HDCP_BINFO
,
118 bstatus
, DRM_HDCP_BSTATUS_LEN
);
119 if (ret
!= DRM_HDCP_BSTATUS_LEN
) {
120 drm_dbg_kms(&i915
->drm
,
121 "Read bstatus from DP/AUX failed (%zd)\n", ret
);
122 return ret
>= 0 ? -EIO
: ret
;
128 int intel_dp_hdcp_read_bcaps(struct drm_dp_aux
*aux
,
129 struct drm_i915_private
*i915
,
134 ret
= drm_dp_dpcd_read(aux
, DP_AUX_HDCP_BCAPS
,
137 drm_dbg_kms(&i915
->drm
,
138 "Read bcaps from DP/AUX failed (%zd)\n", ret
);
139 return ret
>= 0 ? -EIO
: ret
;
146 int intel_dp_hdcp_repeater_present(struct intel_digital_port
*dig_port
,
147 bool *repeater_present
)
149 struct drm_i915_private
*i915
= to_i915(dig_port
->base
.base
.dev
);
153 ret
= intel_dp_hdcp_read_bcaps(&dig_port
->dp
.aux
, i915
, &bcaps
);
157 *repeater_present
= bcaps
& DP_BCAPS_REPEATER_PRESENT
;
162 int intel_dp_hdcp_read_ri_prime(struct intel_digital_port
*dig_port
,
165 struct drm_i915_private
*i915
= to_i915(dig_port
->base
.base
.dev
);
168 ret
= drm_dp_dpcd_read(&dig_port
->dp
.aux
, DP_AUX_HDCP_RI_PRIME
,
169 ri_prime
, DRM_HDCP_RI_LEN
);
170 if (ret
!= DRM_HDCP_RI_LEN
) {
171 drm_dbg_kms(&i915
->drm
, "Read Ri' from DP/AUX failed (%zd)\n",
173 return ret
>= 0 ? -EIO
: ret
;
179 int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port
*dig_port
,
182 struct drm_i915_private
*i915
= to_i915(dig_port
->base
.base
.dev
);
186 ret
= drm_dp_dpcd_read(&dig_port
->dp
.aux
, DP_AUX_HDCP_BSTATUS
,
189 drm_dbg_kms(&i915
->drm
,
190 "Read bstatus from DP/AUX failed (%zd)\n", ret
);
191 return ret
>= 0 ? -EIO
: ret
;
193 *ksv_ready
= bstatus
& DP_BSTATUS_READY
;
198 int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port
*dig_port
,
199 int num_downstream
, u8
*ksv_fifo
)
201 struct drm_i915_private
*i915
= to_i915(dig_port
->base
.base
.dev
);
205 /* KSV list is read via 15 byte window (3 entries @ 5 bytes each) */
206 for (i
= 0; i
< num_downstream
; i
+= 3) {
207 size_t len
= min(num_downstream
- i
, 3) * DRM_HDCP_KSV_LEN
;
208 ret
= drm_dp_dpcd_read(&dig_port
->dp
.aux
,
209 DP_AUX_HDCP_KSV_FIFO
,
210 ksv_fifo
+ i
* DRM_HDCP_KSV_LEN
,
213 drm_dbg_kms(&i915
->drm
,
214 "Read ksv[%d] from DP/AUX failed (%zd)\n",
216 return ret
>= 0 ? -EIO
: ret
;
223 int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port
*dig_port
,
226 struct drm_i915_private
*i915
= to_i915(dig_port
->base
.base
.dev
);
229 if (i
>= DRM_HDCP_V_PRIME_NUM_PARTS
)
232 ret
= drm_dp_dpcd_read(&dig_port
->dp
.aux
,
233 DP_AUX_HDCP_V_PRIME(i
), part
,
234 DRM_HDCP_V_PRIME_PART_LEN
);
235 if (ret
!= DRM_HDCP_V_PRIME_PART_LEN
) {
236 drm_dbg_kms(&i915
->drm
,
237 "Read v'[%d] from DP/AUX failed (%zd)\n", i
, ret
);
238 return ret
>= 0 ? -EIO
: ret
;
244 int intel_dp_hdcp_toggle_signalling(struct intel_digital_port
*dig_port
,
245 enum transcoder cpu_transcoder
,
248 /* Not used for single stream DisplayPort setups */
253 bool intel_dp_hdcp_check_link(struct intel_digital_port
*dig_port
,
254 struct intel_connector
*connector
)
256 struct drm_i915_private
*i915
= to_i915(dig_port
->base
.base
.dev
);
260 ret
= drm_dp_dpcd_read(&dig_port
->dp
.aux
, DP_AUX_HDCP_BSTATUS
,
263 drm_dbg_kms(&i915
->drm
,
264 "Read bstatus from DP/AUX failed (%zd)\n", ret
);
268 return !(bstatus
& (DP_BSTATUS_LINK_FAILURE
| DP_BSTATUS_REAUTH_REQ
));
272 int intel_dp_hdcp_get_capability(struct intel_digital_port
*dig_port
,
275 struct drm_i915_private
*i915
= to_i915(dig_port
->base
.base
.dev
);
279 ret
= intel_dp_hdcp_read_bcaps(&dig_port
->dp
.aux
, i915
, &bcaps
);
283 *hdcp_capable
= bcaps
& DP_BCAPS_HDCP_CAPABLE
;
287 struct hdcp2_dp_errata_stream_type
{
292 struct hdcp2_dp_msg_data
{
297 u32 timeout2
; /* Added for non_paired situation */
298 /* Timeout to read entire msg */
299 u32 msg_read_timeout
;
302 static const struct hdcp2_dp_msg_data hdcp2_dp_msg_data
[] = {
303 { HDCP_2_2_AKE_INIT
, DP_HDCP_2_2_AKE_INIT_OFFSET
, false, 0, 0, 0},
304 { HDCP_2_2_AKE_SEND_CERT
, DP_HDCP_2_2_AKE_SEND_CERT_OFFSET
,
305 false, HDCP_2_2_CERT_TIMEOUT_MS
, 0, HDCP_2_2_DP_CERT_READ_TIMEOUT_MS
},
306 { HDCP_2_2_AKE_NO_STORED_KM
, DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET
,
308 { HDCP_2_2_AKE_STORED_KM
, DP_HDCP_2_2_AKE_STORED_KM_OFFSET
,
310 { HDCP_2_2_AKE_SEND_HPRIME
, DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET
,
311 true, HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS
,
312 HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS
, HDCP_2_2_DP_HPRIME_READ_TIMEOUT_MS
},
313 { HDCP_2_2_AKE_SEND_PAIRING_INFO
,
314 DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET
, true,
315 HDCP_2_2_PAIRING_TIMEOUT_MS
, 0, HDCP_2_2_DP_PAIRING_READ_TIMEOUT_MS
},
316 { HDCP_2_2_LC_INIT
, DP_HDCP_2_2_LC_INIT_OFFSET
, false, 0, 0, 0 },
317 { HDCP_2_2_LC_SEND_LPRIME
, DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET
,
318 false, HDCP_2_2_DP_LPRIME_TIMEOUT_MS
, 0, 0 },
319 { HDCP_2_2_SKE_SEND_EKS
, DP_HDCP_2_2_SKE_SEND_EKS_OFFSET
, false,
321 { HDCP_2_2_REP_SEND_RECVID_LIST
,
322 DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET
, true,
323 HDCP_2_2_RECVID_LIST_TIMEOUT_MS
, 0, 0 },
324 { HDCP_2_2_REP_SEND_ACK
, DP_HDCP_2_2_REP_SEND_ACK_OFFSET
, false,
326 { HDCP_2_2_REP_STREAM_MANAGE
,
327 DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET
, false,
329 { HDCP_2_2_REP_STREAM_READY
, DP_HDCP_2_2_REP_STREAM_READY_OFFSET
,
330 false, HDCP_2_2_STREAM_READY_TIMEOUT_MS
, 0, 0 },
331 /* local define to shovel this through the write_2_2 interface */
332 #define HDCP_2_2_ERRATA_DP_STREAM_TYPE 50
333 { HDCP_2_2_ERRATA_DP_STREAM_TYPE
,
334 DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET
, false,
339 intel_dp_hdcp2_read_rx_status(struct intel_connector
*connector
,
342 struct drm_i915_private
*i915
= to_i915(connector
->base
.dev
);
343 struct intel_digital_port
*dig_port
= intel_attached_dig_port(connector
);
344 struct drm_dp_aux
*aux
= &dig_port
->dp
.aux
;
347 ret
= drm_dp_dpcd_read(aux
,
348 DP_HDCP_2_2_REG_RXSTATUS_OFFSET
, rx_status
,
349 HDCP_2_2_DP_RXSTATUS_LEN
);
350 if (ret
!= HDCP_2_2_DP_RXSTATUS_LEN
) {
351 drm_dbg_kms(&i915
->drm
,
352 "Read bstatus from DP/AUX failed (%zd)\n", ret
);
353 return ret
>= 0 ? -EIO
: ret
;
360 int hdcp2_detect_msg_availability(struct intel_connector
*connector
,
361 u8 msg_id
, bool *msg_ready
)
367 ret
= intel_dp_hdcp2_read_rx_status(connector
, &rx_status
);
372 case HDCP_2_2_AKE_SEND_HPRIME
:
373 if (HDCP_2_2_DP_RXSTATUS_H_PRIME(rx_status
))
376 case HDCP_2_2_AKE_SEND_PAIRING_INFO
:
377 if (HDCP_2_2_DP_RXSTATUS_PAIRING(rx_status
))
380 case HDCP_2_2_REP_SEND_RECVID_LIST
:
381 if (HDCP_2_2_DP_RXSTATUS_READY(rx_status
))
385 drm_err(connector
->base
.dev
,
386 "Unidentified msg_id: %d\n", msg_id
);
394 intel_dp_hdcp2_wait_for_msg(struct intel_connector
*connector
,
395 const struct hdcp2_dp_msg_data
*hdcp2_msg_data
)
397 struct drm_i915_private
*i915
= to_i915(connector
->base
.dev
);
398 struct intel_digital_port
*dig_port
= intel_attached_dig_port(connector
);
399 struct intel_dp
*dp
= &dig_port
->dp
;
400 struct intel_hdcp
*hdcp
= &dp
->attached_connector
->hdcp
;
401 u8 msg_id
= hdcp2_msg_data
->msg_id
;
403 bool msg_ready
= false;
405 if (msg_id
== HDCP_2_2_AKE_SEND_HPRIME
&& !hdcp
->is_paired
)
406 timeout
= hdcp2_msg_data
->timeout2
;
408 timeout
= hdcp2_msg_data
->timeout
;
411 * There is no way to detect the CERT, LPRIME and STREAM_READY
412 * availability. So Wait for timeout and read the msg.
414 if (!hdcp2_msg_data
->msg_detectable
) {
419 * As we want to check the msg availability at timeout, Ignoring
420 * the timeout at wait for CP_IRQ.
422 intel_dp_hdcp_wait_for_cp_irq(connector
, timeout
);
423 ret
= hdcp2_detect_msg_availability(connector
, msg_id
,
430 drm_dbg_kms(&i915
->drm
,
431 "msg_id %d, ret %d, timeout(mSec): %d\n",
432 hdcp2_msg_data
->msg_id
, ret
, timeout
);
437 static const struct hdcp2_dp_msg_data
*get_hdcp2_dp_msg_data(u8 msg_id
)
441 for (i
= 0; i
< ARRAY_SIZE(hdcp2_dp_msg_data
); i
++)
442 if (hdcp2_dp_msg_data
[i
].msg_id
== msg_id
)
443 return &hdcp2_dp_msg_data
[i
];
449 int intel_dp_hdcp2_write_msg(struct intel_connector
*connector
,
450 void *buf
, size_t size
)
454 ssize_t ret
, bytes_to_write
, len
;
455 struct intel_digital_port
*dig_port
= intel_attached_dig_port(connector
);
456 struct drm_dp_aux
*aux
= &dig_port
->dp
.aux
;
457 const struct hdcp2_dp_msg_data
*hdcp2_msg_data
;
459 hdcp2_msg_data
= get_hdcp2_dp_msg_data(*byte
);
463 offset
= hdcp2_msg_data
->offset
;
465 /* No msg_id in DP HDCP2.2 msgs */
466 bytes_to_write
= size
- 1;
469 while (bytes_to_write
) {
470 len
= bytes_to_write
> DP_AUX_MAX_PAYLOAD_BYTES
?
471 DP_AUX_MAX_PAYLOAD_BYTES
: bytes_to_write
;
473 ret
= drm_dp_dpcd_write(aux
,
474 offset
, (void *)byte
, len
);
478 bytes_to_write
-= ret
;
487 ssize_t
get_receiver_id_list_rx_info(struct intel_connector
*connector
,
488 u32
*dev_cnt
, u8
*byte
)
490 struct intel_digital_port
*dig_port
= intel_attached_dig_port(connector
);
491 struct drm_dp_aux
*aux
= &dig_port
->dp
.aux
;
495 ret
= drm_dp_dpcd_read(aux
,
496 DP_HDCP_2_2_REG_RXINFO_OFFSET
,
497 (void *)rx_info
, HDCP_2_2_RXINFO_LEN
);
498 if (ret
!= HDCP_2_2_RXINFO_LEN
)
499 return ret
>= 0 ? -EIO
: ret
;
501 *dev_cnt
= (HDCP_2_2_DEV_COUNT_HI(rx_info
[0]) << 4 |
502 HDCP_2_2_DEV_COUNT_LO(rx_info
[1]));
504 if (*dev_cnt
> HDCP_2_2_MAX_DEVICE_COUNT
)
505 *dev_cnt
= HDCP_2_2_MAX_DEVICE_COUNT
;
511 int intel_dp_hdcp2_read_msg(struct intel_connector
*connector
,
512 u8 msg_id
, void *buf
, size_t size
)
514 struct intel_digital_port
*dig_port
= intel_attached_dig_port(connector
);
515 struct drm_i915_private
*i915
= to_i915(dig_port
->base
.base
.dev
);
516 struct drm_dp_aux
*aux
= &dig_port
->dp
.aux
;
517 struct intel_dp
*dp
= &dig_port
->dp
;
518 struct intel_hdcp
*hdcp
= &dp
->attached_connector
->hdcp
;
521 ssize_t ret
, bytes_to_recv
, len
;
522 const struct hdcp2_dp_msg_data
*hdcp2_msg_data
;
523 ktime_t msg_end
= ktime_set(0, 0);
527 hdcp2_msg_data
= get_hdcp2_dp_msg_data(msg_id
);
530 offset
= hdcp2_msg_data
->offset
;
532 ret
= intel_dp_hdcp2_wait_for_msg(connector
, hdcp2_msg_data
);
536 hdcp
->cp_irq_count_cached
= atomic_read(&hdcp
->cp_irq_count
);
538 /* DP adaptation msgs has no msg_id */
541 if (msg_id
== HDCP_2_2_REP_SEND_RECVID_LIST
) {
542 ret
= get_receiver_id_list_rx_info(connector
, &dev_cnt
, byte
);
547 size
= sizeof(struct hdcp2_rep_send_receiverid_list
) -
548 HDCP_2_2_RXINFO_LEN
- HDCP_2_2_RECEIVER_IDS_MAX_LEN
+
549 (dev_cnt
* HDCP_2_2_RECEIVER_ID_LEN
);
550 offset
+= HDCP_2_2_RXINFO_LEN
;
553 bytes_to_recv
= size
- 1;
555 while (bytes_to_recv
) {
556 len
= bytes_to_recv
> DP_AUX_MAX_PAYLOAD_BYTES
?
557 DP_AUX_MAX_PAYLOAD_BYTES
: bytes_to_recv
;
559 /* Entire msg read timeout since initiate of msg read */
560 if (bytes_to_recv
== size
- 1 && hdcp2_msg_data
->msg_read_timeout
> 0) {
561 msg_end
= ktime_add_ms(ktime_get_raw(),
562 hdcp2_msg_data
->msg_read_timeout
);
565 ret
= drm_dp_dpcd_read(aux
, offset
,
568 drm_dbg_kms(&i915
->drm
, "msg_id %d, ret %zd\n",
573 bytes_to_recv
-= ret
;
578 if (hdcp2_msg_data
->msg_read_timeout
> 0) {
579 msg_expired
= ktime_after(ktime_get_raw(), msg_end
);
581 drm_dbg_kms(&i915
->drm
, "msg_id %d, entire msg read timeout(mSec): %d\n",
582 msg_id
, hdcp2_msg_data
->msg_read_timeout
);
594 int intel_dp_hdcp2_config_stream_type(struct intel_connector
*connector
,
595 bool is_repeater
, u8 content_type
)
598 struct hdcp2_dp_errata_stream_type stream_type_msg
;
604 * Errata for DP: As Stream type is used for encryption, Receiver
605 * should be communicated with stream type for the decryption of the
607 * Repeater will be communicated with stream type as a part of it's
608 * auth later in time.
610 stream_type_msg
.msg_id
= HDCP_2_2_ERRATA_DP_STREAM_TYPE
;
611 stream_type_msg
.stream_type
= content_type
;
613 ret
= intel_dp_hdcp2_write_msg(connector
, &stream_type_msg
,
614 sizeof(stream_type_msg
));
616 return ret
< 0 ? ret
: 0;
621 int intel_dp_hdcp2_check_link(struct intel_digital_port
*dig_port
,
622 struct intel_connector
*connector
)
627 ret
= intel_dp_hdcp2_read_rx_status(connector
,
632 if (HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(rx_status
))
633 ret
= HDCP_REAUTH_REQUEST
;
634 else if (HDCP_2_2_DP_RXSTATUS_LINK_FAILED(rx_status
))
635 ret
= HDCP_LINK_INTEGRITY_FAILURE
;
636 else if (HDCP_2_2_DP_RXSTATUS_READY(rx_status
))
637 ret
= HDCP_TOPOLOGY_CHANGE
;
643 int _intel_dp_hdcp2_get_capability(struct drm_dp_aux
*aux
,
652 * Some HDCP monitors act really shady by not giving the correct hdcp
653 * capability on the first rx_caps read and usually take an extra read
654 * to give the capability. We read rx_caps three times before we
655 * declare a monitor not capable of HDCP 2.2.
657 for (i
= 0; i
< 3; i
++) {
658 ret
= drm_dp_dpcd_read(aux
,
659 DP_HDCP_2_2_REG_RX_CAPS_OFFSET
,
660 rx_caps
, HDCP_2_2_RXCAPS_LEN
);
661 if (ret
!= HDCP_2_2_RXCAPS_LEN
)
662 return ret
>= 0 ? -EIO
: ret
;
664 if (rx_caps
[0] == HDCP_2_2_RX_CAPS_VERSION_VAL
&&
665 HDCP_2_2_DP_HDCP_CAPABLE(rx_caps
[2])) {
675 int intel_dp_hdcp2_get_capability(struct intel_connector
*connector
,
678 struct intel_digital_port
*dig_port
= intel_attached_dig_port(connector
);
679 struct drm_dp_aux
*aux
= &dig_port
->dp
.aux
;
681 return _intel_dp_hdcp2_get_capability(aux
, capable
);
685 int intel_dp_hdcp_get_remote_capability(struct intel_connector
*connector
,
689 struct drm_i915_private
*i915
= to_i915(connector
->base
.dev
);
690 struct drm_dp_aux
*aux
= &connector
->port
->aux
;
694 if (!intel_encoder_is_mst(connector
->encoder
))
697 ret
= _intel_dp_hdcp2_get_capability(aux
, hdcp2_capable
);
701 ret
= intel_dp_hdcp_read_bcaps(aux
, i915
, &bcaps
);
705 *hdcp_capable
= bcaps
& DP_BCAPS_HDCP_CAPABLE
;
710 static const struct intel_hdcp_shim intel_dp_hdcp_shim
= {
711 .write_an_aksv
= intel_dp_hdcp_write_an_aksv
,
712 .read_bksv
= intel_dp_hdcp_read_bksv
,
713 .read_bstatus
= intel_dp_hdcp_read_bstatus
,
714 .repeater_present
= intel_dp_hdcp_repeater_present
,
715 .read_ri_prime
= intel_dp_hdcp_read_ri_prime
,
716 .read_ksv_ready
= intel_dp_hdcp_read_ksv_ready
,
717 .read_ksv_fifo
= intel_dp_hdcp_read_ksv_fifo
,
718 .read_v_prime_part
= intel_dp_hdcp_read_v_prime_part
,
719 .toggle_signalling
= intel_dp_hdcp_toggle_signalling
,
720 .check_link
= intel_dp_hdcp_check_link
,
721 .hdcp_get_capability
= intel_dp_hdcp_get_capability
,
722 .write_2_2_msg
= intel_dp_hdcp2_write_msg
,
723 .read_2_2_msg
= intel_dp_hdcp2_read_msg
,
724 .config_stream_type
= intel_dp_hdcp2_config_stream_type
,
725 .check_2_2_link
= intel_dp_hdcp2_check_link
,
726 .hdcp_2_2_get_capability
= intel_dp_hdcp2_get_capability
,
727 .protocol
= HDCP_PROTOCOL_DP
,
731 intel_dp_mst_toggle_hdcp_stream_select(struct intel_connector
*connector
,
734 struct intel_digital_port
*dig_port
= intel_attached_dig_port(connector
);
735 struct drm_i915_private
*i915
= to_i915(connector
->base
.dev
);
736 struct intel_hdcp
*hdcp
= &connector
->hdcp
;
739 ret
= intel_ddi_toggle_hdcp_bits(&dig_port
->base
,
740 hdcp
->stream_transcoder
, enable
,
741 TRANS_DDI_HDCP_SELECT
);
743 drm_err(&i915
->drm
, "%s HDCP stream select failed (%d)\n",
744 enable
? "Enable" : "Disable", ret
);
749 intel_dp_mst_hdcp_stream_encryption(struct intel_connector
*connector
,
752 struct intel_digital_port
*dig_port
= intel_attached_dig_port(connector
);
753 struct drm_i915_private
*i915
= to_i915(connector
->base
.dev
);
754 struct intel_hdcp
*hdcp
= &connector
->hdcp
;
755 enum port port
= dig_port
->base
.port
;
756 enum transcoder cpu_transcoder
= hdcp
->stream_transcoder
;
757 u32 stream_enc_status
;
760 ret
= intel_dp_mst_toggle_hdcp_stream_select(connector
, enable
);
764 stream_enc_status
= transcoder_to_stream_enc_status(cpu_transcoder
);
765 if (!stream_enc_status
)
768 /* Wait for encryption confirmation */
769 if (intel_de_wait_for_register(i915
,
770 HDCP_STATUS(i915
, cpu_transcoder
, port
),
772 enable
? stream_enc_status
: 0,
773 HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS
)) {
774 drm_err(&i915
->drm
, "Timed out waiting for transcoder: %s stream encryption %s\n",
775 transcoder_name(cpu_transcoder
), enable
? "enabled" : "disabled");
783 intel_dp_mst_hdcp2_stream_encryption(struct intel_connector
*connector
,
786 struct intel_digital_port
*dig_port
= intel_attached_dig_port(connector
);
787 struct drm_i915_private
*i915
= to_i915(connector
->base
.dev
);
788 struct hdcp_port_data
*data
= &dig_port
->hdcp_port_data
;
789 struct intel_hdcp
*hdcp
= &connector
->hdcp
;
790 enum transcoder cpu_transcoder
= hdcp
->stream_transcoder
;
791 enum pipe pipe
= (enum pipe
)cpu_transcoder
;
792 enum port port
= dig_port
->base
.port
;
795 drm_WARN_ON(&i915
->drm
, enable
&&
796 !!(intel_de_read(i915
, HDCP2_AUTH_STREAM(i915
, cpu_transcoder
, port
))
797 & AUTH_STREAM_TYPE
) != data
->streams
[0].stream_type
);
799 ret
= intel_dp_mst_toggle_hdcp_stream_select(connector
, enable
);
803 /* Wait for encryption confirmation */
804 if (intel_de_wait_for_register(i915
,
805 HDCP2_STREAM_STATUS(i915
, cpu_transcoder
, pipe
),
806 STREAM_ENCRYPTION_STATUS
,
807 enable
? STREAM_ENCRYPTION_STATUS
: 0,
808 HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS
)) {
809 drm_err(&i915
->drm
, "Timed out waiting for transcoder: %s stream encryption %s\n",
810 transcoder_name(cpu_transcoder
), enable
? "enabled" : "disabled");
818 int intel_dp_mst_hdcp2_check_link(struct intel_digital_port
*dig_port
,
819 struct intel_connector
*connector
)
821 struct intel_hdcp
*hdcp
= &connector
->hdcp
;
825 * We do need to do the Link Check only for the connector involved with
826 * HDCP port authentication and encryption.
827 * We can re-use the hdcp->is_repeater flag to know that the connector
828 * involved with HDCP port authentication and encryption.
830 if (hdcp
->is_repeater
) {
831 ret
= intel_dp_hdcp2_check_link(dig_port
, connector
);
839 static const struct intel_hdcp_shim intel_dp_mst_hdcp_shim
= {
840 .write_an_aksv
= intel_dp_hdcp_write_an_aksv
,
841 .read_bksv
= intel_dp_hdcp_read_bksv
,
842 .read_bstatus
= intel_dp_hdcp_read_bstatus
,
843 .repeater_present
= intel_dp_hdcp_repeater_present
,
844 .read_ri_prime
= intel_dp_hdcp_read_ri_prime
,
845 .read_ksv_ready
= intel_dp_hdcp_read_ksv_ready
,
846 .read_ksv_fifo
= intel_dp_hdcp_read_ksv_fifo
,
847 .read_v_prime_part
= intel_dp_hdcp_read_v_prime_part
,
848 .toggle_signalling
= intel_dp_hdcp_toggle_signalling
,
849 .stream_encryption
= intel_dp_mst_hdcp_stream_encryption
,
850 .check_link
= intel_dp_hdcp_check_link
,
851 .hdcp_get_capability
= intel_dp_hdcp_get_capability
,
852 .write_2_2_msg
= intel_dp_hdcp2_write_msg
,
853 .read_2_2_msg
= intel_dp_hdcp2_read_msg
,
854 .config_stream_type
= intel_dp_hdcp2_config_stream_type
,
855 .stream_2_2_encryption
= intel_dp_mst_hdcp2_stream_encryption
,
856 .check_2_2_link
= intel_dp_mst_hdcp2_check_link
,
857 .hdcp_2_2_get_capability
= intel_dp_hdcp2_get_capability
,
858 .get_remote_hdcp_capability
= intel_dp_hdcp_get_remote_capability
,
859 .protocol
= HDCP_PROTOCOL_DP
,
862 int intel_dp_hdcp_init(struct intel_digital_port
*dig_port
,
863 struct intel_connector
*intel_connector
)
865 struct drm_device
*dev
= intel_connector
->base
.dev
;
866 struct drm_i915_private
*dev_priv
= to_i915(dev
);
867 struct intel_encoder
*intel_encoder
= &dig_port
->base
;
868 enum port port
= intel_encoder
->port
;
869 struct intel_dp
*intel_dp
= &dig_port
->dp
;
871 if (!is_hdcp_supported(dev_priv
, port
))
874 if (intel_connector
->mst_port
)
875 return intel_hdcp_init(intel_connector
, dig_port
,
876 &intel_dp_mst_hdcp_shim
);
877 else if (!intel_dp_is_edp(intel_dp
))
878 return intel_hdcp_init(intel_connector
, dig_port
,
879 &intel_dp_hdcp_shim
);