drivers/gpu/drm/i915/display/intel_dp_mst.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *             2014 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  *
  24  */
  25
  26 #include <drm/drm_atomic.h>
  27 #include <drm/drm_atomic_helper.h>
  28 #include <drm/drm_edid.h>
  29 #include <drm/drm_fixed.h>
  30 #include <drm/drm_probe_helper.h>
  31
  32 #include "i915_drv.h"
  33 #include "i915_reg.h"
  34 #include "intel_atomic.h"
  35 #include "intel_audio.h"
  36 #include "intel_connector.h"
  37 #include "intel_crtc.h"
  38 #include "intel_ddi.h"
  39 #include "intel_de.h"
  40 #include "intel_display_driver.h"
  41 #include "intel_display_types.h"
  42 #include "intel_dp.h"
  43 #include "intel_dp_hdcp.h"
  44 #include "intel_dp_mst.h"
  45 #include "intel_dp_tunnel.h"
  46 #include "intel_dpio_phy.h"
  47 #include "intel_hdcp.h"
  48 #include "intel_hotplug.h"
  49 #include "intel_link_bw.h"
  50 #include "intel_psr.h"
  51 #include "intel_vdsc.h"
  52 #include "skl_scaler.h"
  53
  54 static int intel_dp_mst_check_constraints(struct drm_i915_private *i915, int bpp,
  55                                           const struct drm_display_mode *adjusted_mode,
  56                                           struct intel_crtc_state *crtc_state,
  57                                           bool dsc)
  58 {
  59         if (intel_dp_is_uhbr(crtc_state) && DISPLAY_VER(i915) < 14 && dsc) {
  60                 int output_bpp = bpp;
  61                 /* DisplayPort 2 128b/132b, bits per lane is always 32 */
  62                 int symbol_clock = crtc_state->port_clock / 32;
  63
  64                 if (output_bpp * adjusted_mode->crtc_clock >=
  65                     symbol_clock * 72) {
  66                         drm_dbg_kms(&i915->drm, "UHBR check failed(required bw %d available %d)\n",
  67                                     output_bpp * adjusted_mode->crtc_clock, symbol_clock * 72);
  68                         return -EINVAL;
  69                 }
  70         }
  71
  72         return 0;
  73 }
  74
  75 static int intel_dp_mst_bw_overhead(const struct intel_crtc_state *crtc_state,
  76                                     const struct intel_connector *connector,
  77                                     bool ssc, bool dsc, int bpp_x16)
  78 {
  79         const struct drm_display_mode *adjusted_mode =
  80                 &crtc_state->hw.adjusted_mode;
  81         unsigned long flags = DRM_DP_BW_OVERHEAD_MST;
  82         int dsc_slice_count = 0;
  83         int overhead;
  84
  85         flags |= intel_dp_is_uhbr(crtc_state) ? DRM_DP_BW_OVERHEAD_UHBR : 0;
  86         flags |= ssc ? DRM_DP_BW_OVERHEAD_SSC_REF_CLK : 0;
  87         flags |= crtc_state->fec_enable ? DRM_DP_BW_OVERHEAD_FEC : 0;
  88
  89         if (dsc) {
  90                 flags |= DRM_DP_BW_OVERHEAD_DSC;
  91                 /* TODO: add support for bigjoiner */
  92                 dsc_slice_count = intel_dp_dsc_get_slice_count(connector,
  93                                                                adjusted_mode->clock,
  94                                                                adjusted_mode->hdisplay,
  95                                                                false);
  96         }
  97
  98         overhead = drm_dp_bw_overhead(crtc_state->lane_count,
  99                                       adjusted_mode->hdisplay,
 100                                       dsc_slice_count,
 101                                       bpp_x16,
 102                                       flags);
 103
 104         /*
 105          * TODO: clarify whether a minimum required by the fixed FEC overhead
 106          * in the bspec audio programming sequence is required here.
 107          */
 108         return max(overhead, intel_dp_bw_fec_overhead(crtc_state->fec_enable));
 109 }
 110
 111 static void intel_dp_mst_compute_m_n(const struct intel_crtc_state *crtc_state,
 112                                      const struct intel_connector *connector,
 113                                      int overhead,
 114                                      int bpp_x16,
 115                                      struct intel_link_m_n *m_n)
 116 {
 117         const struct drm_display_mode *adjusted_mode =
 118                 &crtc_state->hw.adjusted_mode;
 119
 120         /* TODO: Check WA 14013163432 to set data M/N for full BW utilization. */
 121         intel_link_compute_m_n(bpp_x16, crtc_state->lane_count,
 122                                adjusted_mode->crtc_clock,
 123                                crtc_state->port_clock,
 124                                overhead,
 125                                m_n);
 126
 127         m_n->tu = DIV_ROUND_UP_ULL(mul_u32_u32(m_n->data_m, 64), m_n->data_n);
 128 }
 129
 130 static int intel_dp_mst_calc_pbn(int pixel_clock, int bpp_x16, int bw_overhead)
 131 {
 132         int effective_data_rate =
 133                 intel_dp_effective_data_rate(pixel_clock, bpp_x16, bw_overhead);
 134
 135         /*
 136          * TODO: Use drm_dp_calc_pbn_mode() instead, once it's converted
 137          * to calculate PBN with the BW overhead passed to it.
 138          */
 139         return DIV_ROUND_UP(effective_data_rate * 64, 54 * 1000);
 140 }
 141
 142 static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
 143                                                 struct intel_crtc_state *crtc_state,
 144                                                 int max_bpp,
 145                                                 int min_bpp,
 146                                                 struct link_config_limits *limits,
 147                                                 struct drm_connector_state *conn_state,
 148                                                 int step,
 149                                                 bool dsc)
 150 {
 151         struct drm_atomic_state *state = crtc_state->uapi.state;
 152         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
 153         struct intel_dp *intel_dp = &intel_mst->primary->dp;
 154         struct drm_dp_mst_topology_state *mst_state;
 155         struct intel_connector *connector =
 156                 to_intel_connector(conn_state->connector);
 157         struct drm_i915_private *i915 = to_i915(connector->base.dev);
 158         const struct drm_display_mode *adjusted_mode =
 159                 &crtc_state->hw.adjusted_mode;
 160         int bpp, slots = -EINVAL;
 161         int ret = 0;
 162
 163         mst_state = drm_atomic_get_mst_topology_state(state, &intel_dp->mst_mgr);
 164         if (IS_ERR(mst_state))
 165                 return PTR_ERR(mst_state);
 166
 167         crtc_state->lane_count = limits->max_lane_count;
 168         crtc_state->port_clock = limits->max_rate;
 169
 170         if (dsc) {
 171                 if (!intel_dp_supports_fec(intel_dp, connector, crtc_state))
 172                         return -EINVAL;
 173
 174                 crtc_state->fec_enable = !intel_dp_is_uhbr(crtc_state);
 175         }
 176
 177         mst_state->pbn_div = drm_dp_get_vc_payload_bw(&intel_dp->mst_mgr,
 178                                                       crtc_state->port_clock,
 179                                                       crtc_state->lane_count);
 180
 181         drm_dbg_kms(&i915->drm, "Looking for slots in range min bpp %d max bpp %d\n",
 182                     min_bpp, max_bpp);
 183
 184         for (bpp = max_bpp; bpp >= min_bpp; bpp -= step) {
 185                 int local_bw_overhead;
 186                 int remote_bw_overhead;
 187                 int link_bpp_x16;
 188                 int remote_tu;
 189
 190                 drm_dbg_kms(&i915->drm, "Trying bpp %d\n", bpp);
 191
 192                 ret = intel_dp_mst_check_constraints(i915, bpp, adjusted_mode, crtc_state, dsc);
 193                 if (ret)
 194                         continue;
 195
 196                 link_bpp_x16 = to_bpp_x16(dsc ? bpp :
 197                                           intel_dp_output_bpp(crtc_state->output_format, bpp));
 198
 199                 local_bw_overhead = intel_dp_mst_bw_overhead(crtc_state, connector,
 200                                                              false, dsc, link_bpp_x16);
 201                 remote_bw_overhead = intel_dp_mst_bw_overhead(crtc_state, connector,
 202                                                               true, dsc, link_bpp_x16);
 203
 204                 intel_dp_mst_compute_m_n(crtc_state, connector,
 205                                          local_bw_overhead,
 206                                          link_bpp_x16,
 207                                          &crtc_state->dp_m_n);
 208
 209                 /*
 210                  * The TU size programmed to the HW determines which slots in
 211                  * an MTP frame are used for this stream, which needs to match
 212                  * the payload size programmed to the first downstream branch
 213                  * device's payload table.
 214                  *
 215                  * Note that atm the payload's PBN value DRM core sends via
 216                  * the ALLOCATE_PAYLOAD side-band message matches the payload
 217                  * size (which it calculates from the PBN value) it programs
 218                  * to the first branch device's payload table. The allocation
 219                  * in the payload table could be reduced though (to
 220                  * crtc_state->dp_m_n.tu), provided that the driver doesn't
 221                  * enable SSC on the corresponding link.
 222                  */
 223                 crtc_state->pbn = intel_dp_mst_calc_pbn(adjusted_mode->crtc_clock,
 224                                                         link_bpp_x16,
 225                                                         remote_bw_overhead);
 226
 227                 remote_tu = DIV_ROUND_UP(dfixed_const(crtc_state->pbn), mst_state->pbn_div.full);
 228
 229                 drm_WARN_ON(&i915->drm, remote_tu < crtc_state->dp_m_n.tu);
 230                 crtc_state->dp_m_n.tu = remote_tu;
 231
 232                 slots = drm_dp_atomic_find_time_slots(state, &intel_dp->mst_mgr,
 233                                                       connector->port,
 234                                                       crtc_state->pbn);
 235                 if (slots == -EDEADLK)
 236                         return slots;
 237
 238                 if (slots >= 0) {
 239                         drm_WARN_ON(&i915->drm, slots != crtc_state->dp_m_n.tu);
 240
 241                         break;
 242                 }
 243         }
 244
 245         /* We failed to find a proper bpp/timeslots, return error */
 246         if (ret)
 247                 slots = ret;
 248
 249         if (slots < 0) {
 250                 drm_dbg_kms(&i915->drm, "failed finding vcpi slots:%d\n",
 251                             slots);
 252         } else {
 253                 if (!dsc)
 254                         crtc_state->pipe_bpp = bpp;
 255                 else
 256                         crtc_state->dsc.compressed_bpp_x16 = to_bpp_x16(bpp);
 257                 drm_dbg_kms(&i915->drm, "Got %d slots for pipe bpp %d dsc %d\n", slots, bpp, dsc);
 258         }
 259
 260         return slots;
 261 }
 262
 263 static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
 264                                             struct intel_crtc_state *crtc_state,
 265                                             struct drm_connector_state *conn_state,
 266                                             struct link_config_limits *limits)
 267 {
 268         int slots = -EINVAL;
 269
 270         /*
 271          * FIXME: allocate the BW according to link_bpp, which in the case of
 272          * YUV420 is only half of the pipe bpp value.
 273          */
 274         slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state,
 275                                                      to_bpp_int(limits->link.max_bpp_x16),
 276                                                      to_bpp_int(limits->link.min_bpp_x16),
 277                                                      limits,
 278                                                      conn_state, 2 * 3, false);
 279
 280         if (slots < 0)
 281                 return slots;
 282
 283         return 0;
 284 }
 285
 286 static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
 287                                                 struct intel_crtc_state *crtc_state,
 288                                                 struct drm_connector_state *conn_state,
 289                                                 struct link_config_limits *limits)
 290 {
 291         struct intel_connector *connector =
 292                 to_intel_connector(conn_state->connector);
 293         struct drm_i915_private *i915 = to_i915(connector->base.dev);
 294         int slots = -EINVAL;
 295         int i, num_bpc;
 296         u8 dsc_bpc[3] = {};
 297         int min_bpp, max_bpp, sink_min_bpp, sink_max_bpp;
 298         u8 dsc_max_bpc;
 299         int min_compressed_bpp, max_compressed_bpp;
 300
 301         /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
 302         if (DISPLAY_VER(i915) >= 12)
 303                 dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc);
 304         else
 305                 dsc_max_bpc = min_t(u8, 10, conn_state->max_requested_bpc);
 306
 307         max_bpp = min_t(u8, dsc_max_bpc * 3, limits->pipe.max_bpp);
 308         min_bpp = limits->pipe.min_bpp;
 309
 310         num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd,
 311                                                        dsc_bpc);
 312
 313         drm_dbg_kms(&i915->drm, "DSC Source supported min bpp %d max bpp %d\n",
 314                     min_bpp, max_bpp);
 315
 316         sink_max_bpp = dsc_bpc[0] * 3;
 317         sink_min_bpp = sink_max_bpp;
 318
 319         for (i = 1; i < num_bpc; i++) {
 320                 if (sink_min_bpp > dsc_bpc[i] * 3)
 321                         sink_min_bpp = dsc_bpc[i] * 3;
 322                 if (sink_max_bpp < dsc_bpc[i] * 3)
 323                         sink_max_bpp = dsc_bpc[i] * 3;
 324         }
 325
 326         drm_dbg_kms(&i915->drm, "DSC Sink supported min bpp %d max bpp %d\n",
 327                     sink_min_bpp, sink_max_bpp);
 328
 329         if (min_bpp < sink_min_bpp)
 330                 min_bpp = sink_min_bpp;
 331
 332         if (max_bpp > sink_max_bpp)
 333                 max_bpp = sink_max_bpp;
 334
 335         max_compressed_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector,
 336                                                                   crtc_state,
 337                                                                   max_bpp / 3);
 338         max_compressed_bpp = min(max_compressed_bpp,
 339                                  to_bpp_int(limits->link.max_bpp_x16));
 340
 341         min_compressed_bpp = intel_dp_dsc_sink_min_compressed_bpp(crtc_state);
 342         min_compressed_bpp = max(min_compressed_bpp,
 343                                  to_bpp_int_roundup(limits->link.min_bpp_x16));
 344
 345         drm_dbg_kms(&i915->drm, "DSC Sink supported compressed min bpp %d compressed max bpp %d\n",
 346                     min_compressed_bpp, max_compressed_bpp);
 347
 348         /* Align compressed bpps according to our own constraints */
 349         max_compressed_bpp = intel_dp_dsc_nearest_valid_bpp(i915, max_compressed_bpp,
 350                                                             crtc_state->pipe_bpp);
 351         min_compressed_bpp = intel_dp_dsc_nearest_valid_bpp(i915, min_compressed_bpp,
 352                                                             crtc_state->pipe_bpp);
 353
 354         slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state, max_compressed_bpp,
 355                                                      min_compressed_bpp, limits,
 356                                                      conn_state, 1, true);
 357
 358         if (slots < 0)
 359                 return slots;
 360
 361         return 0;
 362 }
 363 static int intel_dp_mst_update_slots(struct intel_encoder *encoder,
 364                                      struct intel_crtc_state *crtc_state,
 365                                      struct drm_connector_state *conn_state)
 366 {
 367         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 368         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
 369         struct intel_dp *intel_dp = &intel_mst->primary->dp;
 370         struct drm_dp_mst_topology_mgr *mgr = &intel_dp->mst_mgr;
 371         struct drm_dp_mst_topology_state *topology_state;
 372         u8 link_coding_cap = intel_dp_is_uhbr(crtc_state) ?
 373                 DP_CAP_ANSI_128B132B : DP_CAP_ANSI_8B10B;
 374
 375         topology_state = drm_atomic_get_mst_topology_state(conn_state->state, mgr);
 376         if (IS_ERR(topology_state)) {
 377                 drm_dbg_kms(&i915->drm, "slot update failed\n");
 378                 return PTR_ERR(topology_state);
 379         }
 380
 381         drm_dp_mst_update_slots(topology_state, link_coding_cap);
 382
 383         return 0;
 384 }
 385
 386 static bool
 387 intel_dp_mst_dsc_source_support(const struct intel_crtc_state *crtc_state)
 388 {
 389         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
 390
 391         /*
 392          * FIXME: Enabling DSC on ICL results in blank screen and FIFO pipe /
 393          * transcoder underruns, re-enable DSC after fixing this issue.
 394          */
 395         return DISPLAY_VER(i915) >= 12 && intel_dsc_source_support(crtc_state);
 396 }
 397
 398 static int mode_hblank_period_ns(const struct drm_display_mode *mode)
 399 {
 400         return DIV_ROUND_CLOSEST_ULL(mul_u32_u32(mode->htotal - mode->hdisplay,
 401                                                  NSEC_PER_SEC / 1000),
 402                                      mode->crtc_clock);
 403 }
 404
 405 static bool
 406 hblank_expansion_quirk_needs_dsc(const struct intel_connector *connector,
 407                                  const struct intel_crtc_state *crtc_state)
 408 {
 409         const struct drm_display_mode *adjusted_mode =
 410                 &crtc_state->hw.adjusted_mode;
 411
 412         if (!connector->dp.dsc_hblank_expansion_quirk)
 413                 return false;
 414
 415         if (mode_hblank_period_ns(adjusted_mode) > 300)
 416                 return false;
 417
 418         return true;
 419 }
 420
 421 static bool
 422 adjust_limits_for_dsc_hblank_expansion_quirk(const struct intel_connector *connector,
 423                                              const struct intel_crtc_state *crtc_state,
 424                                              struct link_config_limits *limits,
 425                                              bool dsc)
 426 {
 427         struct drm_i915_private *i915 = to_i915(connector->base.dev);
 428         const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 429         int min_bpp_x16 = limits->link.min_bpp_x16;
 430
 431         if (!hblank_expansion_quirk_needs_dsc(connector, crtc_state))
 432                 return true;
 433
 434         if (!dsc) {
 435                 if (intel_dp_mst_dsc_source_support(crtc_state)) {
 436                         drm_dbg_kms(&i915->drm,
 437                                     "[CRTC:%d:%s][CONNECTOR:%d:%s] DSC needed by hblank expansion quirk\n",
 438                                     crtc->base.base.id, crtc->base.name,
 439                                     connector->base.base.id, connector->base.name);
 440                         return false;
 441                 }
 442
 443                 drm_dbg_kms(&i915->drm,
 444                             "[CRTC:%d:%s][CONNECTOR:%d:%s] Increasing link min bpp to 24 due to hblank expansion quirk\n",
 445                             crtc->base.base.id, crtc->base.name,
 446                             connector->base.base.id, connector->base.name);
 447
 448                 if (limits->link.max_bpp_x16 < to_bpp_x16(24))
 449                         return false;
 450
 451                 limits->link.min_bpp_x16 = to_bpp_x16(24);
 452
 453                 return true;
 454         }
 455
 456         drm_WARN_ON(&i915->drm, limits->min_rate != limits->max_rate);
 457
 458         if (limits->max_rate < 540000)
 459                 min_bpp_x16 = to_bpp_x16(13);
 460         else if (limits->max_rate < 810000)
 461                 min_bpp_x16 = to_bpp_x16(10);
 462
 463         if (limits->link.min_bpp_x16 >= min_bpp_x16)
 464                 return true;
 465
 466         drm_dbg_kms(&i915->drm,
 467                     "[CRTC:%d:%s][CONNECTOR:%d:%s] Increasing link min bpp to " BPP_X16_FMT " in DSC mode due to hblank expansion quirk\n",
 468                     crtc->base.base.id, crtc->base.name,
 469                     connector->base.base.id, connector->base.name,
 470                     BPP_X16_ARGS(min_bpp_x16));
 471
 472         if (limits->link.max_bpp_x16 < min_bpp_x16)
 473                 return false;
 474
 475         limits->link.min_bpp_x16 = min_bpp_x16;
 476
 477         return true;
 478 }
 479
 480 static bool
 481 intel_dp_mst_compute_config_limits(struct intel_dp *intel_dp,
 482                                    const struct intel_connector *connector,
 483                                    struct intel_crtc_state *crtc_state,
 484                                    bool dsc,
 485                                    struct link_config_limits *limits)
 486 {
 487         /*
 488          * for MST we always configure max link bw - the spec doesn't
 489          * seem to suggest we should do otherwise.
 490          */
 491         limits->min_rate = limits->max_rate =
 492                 intel_dp_max_link_rate(intel_dp);
 493
 494         limits->min_lane_count = limits->max_lane_count =
 495                 intel_dp_max_lane_count(intel_dp);
 496
 497         limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state->output_format);
 498         /*
 499          * FIXME: If all the streams can't fit into the link with
 500          * their current pipe_bpp we should reduce pipe_bpp across
 501          * the board until things start to fit. Until then we
 502          * limit to <= 8bpc since that's what was hardcoded for all
 503          * MST streams previously. This hack should be removed once
 504          * we have the proper retry logic in place.
 505          */
 506         limits->pipe.max_bpp = min(crtc_state->pipe_bpp, 24);
 507
 508         intel_dp_adjust_compliance_config(intel_dp, crtc_state, limits);
 509
 510         if (!intel_dp_compute_config_link_bpp_limits(intel_dp,
 511                                                      crtc_state,
 512                                                      dsc,
 513                                                      limits))
 514                 return false;
 515
 516         return adjust_limits_for_dsc_hblank_expansion_quirk(connector,
 517                                                             crtc_state,
 518                                                             limits,
 519                                                             dsc);
 520 }
 521
 522 static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
 523                                        struct intel_crtc_state *pipe_config,
 524                                        struct drm_connector_state *conn_state)
 525 {
 526         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 527         struct intel_atomic_state *state = to_intel_atomic_state(conn_state->state);
 528         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
 529         struct intel_dp *intel_dp = &intel_mst->primary->dp;
 530         const struct intel_connector *connector =
 531                 to_intel_connector(conn_state->connector);
 532         const struct drm_display_mode *adjusted_mode =
 533                 &pipe_config->hw.adjusted_mode;
 534         struct link_config_limits limits;
 535         bool dsc_needed;
 536         int ret = 0;
 537
 538         if (pipe_config->fec_enable &&
 539             !intel_dp_supports_fec(intel_dp, connector, pipe_config))
 540                 return -EINVAL;
 541
 542         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
 543                 return -EINVAL;
 544
 545         pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
 546         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
 547         pipe_config->has_pch_encoder = false;
 548
 549         dsc_needed = intel_dp->force_dsc_en ||
 550                      !intel_dp_mst_compute_config_limits(intel_dp,
 551                                                          connector,
 552                                                          pipe_config,
 553                                                          false,
 554                                                          &limits);
 555
 556         if (!dsc_needed) {
 557                 ret = intel_dp_mst_compute_link_config(encoder, pipe_config,
 558                                                        conn_state, &limits);
 559
 560                 if (ret == -EDEADLK)
 561                         return ret;
 562
 563                 if (ret)
 564                         dsc_needed = true;
 565         }
 566
 567         /* enable compression if the mode doesn't fit available BW */
 568         if (dsc_needed) {
 569                 drm_dbg_kms(&dev_priv->drm, "Try DSC (fallback=%s, force=%s)\n",
 570                             str_yes_no(ret),
 571                             str_yes_no(intel_dp->force_dsc_en));
 572
 573                 if (!intel_dp_mst_dsc_source_support(pipe_config))
 574                         return -EINVAL;
 575
 576                 if (!intel_dp_mst_compute_config_limits(intel_dp,
 577                                                         connector,
 578                                                         pipe_config,
 579                                                         true,
 580                                                         &limits))
 581                         return -EINVAL;
 582
 583                 /*
 584                  * FIXME: As bpc is hardcoded to 8, as mentioned above,
 585                  * WARN and ignore the debug flag force_dsc_bpc for now.
 586                  */
 587                 drm_WARN(&dev_priv->drm, intel_dp->force_dsc_bpc, "Cannot Force BPC for MST\n");
 588                 /*
 589                  * Try to get at least some timeslots and then see, if
 590                  * we can fit there with DSC.
 591                  */
 592                 drm_dbg_kms(&dev_priv->drm, "Trying to find VCPI slots in DSC mode\n");
 593
 594                 ret = intel_dp_dsc_mst_compute_link_config(encoder, pipe_config,
 595                                                            conn_state, &limits);
 596                 if (ret < 0)
 597                         return ret;
 598
 599                 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
 600                                                   conn_state, &limits,
 601                                                   pipe_config->dp_m_n.tu, false);
 602         }
 603
 604         if (ret)
 605                 return ret;
 606
 607         ret = intel_dp_mst_update_slots(encoder, pipe_config, conn_state);
 608         if (ret)
 609                 return ret;
 610
 611         pipe_config->limited_color_range =
 612                 intel_dp_limited_color_range(pipe_config, conn_state);
 613
 614         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
 615                 pipe_config->lane_lat_optim_mask =
 616                         bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
 617
 618         intel_dp_audio_compute_config(encoder, pipe_config, conn_state);
 619
 620         intel_ddi_compute_min_voltage_level(pipe_config);
 621
 622         intel_psr_compute_config(intel_dp, pipe_config, conn_state);
 623
 624         return intel_dp_tunnel_atomic_compute_stream_bw(state, intel_dp, connector,
 625                                                         pipe_config);
 626 }
 627
 628 /*
 629  * Iterate over all connectors and return a mask of
 630  * all CPU transcoders streaming over the same DP link.
 631  */
 632 static unsigned int
 633 intel_dp_mst_transcoder_mask(struct intel_atomic_state *state,
 634                              struct intel_dp *mst_port)
 635 {
 636         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 637         const struct intel_digital_connector_state *conn_state;
 638         struct intel_connector *connector;
 639         u8 transcoders = 0;
 640         int i;
 641
 642         if (DISPLAY_VER(dev_priv) < 12)
 643                 return 0;
 644
 645         for_each_new_intel_connector_in_state(state, connector, conn_state, i) {
 646                 const struct intel_crtc_state *crtc_state;
 647                 struct intel_crtc *crtc;
 648
 649                 if (connector->mst_port != mst_port || !conn_state->base.crtc)
 650                         continue;
 651
 652                 crtc = to_intel_crtc(conn_state->base.crtc);
 653                 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
 654
 655                 if (!crtc_state->hw.active)
 656                         continue;
 657
 658                 transcoders |= BIT(crtc_state->cpu_transcoder);
 659         }
 660
 661         return transcoders;
 662 }
 663
 664 static u8 get_pipes_downstream_of_mst_port(struct intel_atomic_state *state,
 665                                            struct drm_dp_mst_topology_mgr *mst_mgr,
 666                                            struct drm_dp_mst_port *parent_port)
 667 {
 668         const struct intel_digital_connector_state *conn_state;
 669         struct intel_connector *connector;
 670         u8 mask = 0;
 671         int i;
 672
 673         for_each_new_intel_connector_in_state(state, connector, conn_state, i) {
 674                 if (!conn_state->base.crtc)
 675                         continue;
 676
 677                 if (&connector->mst_port->mst_mgr != mst_mgr)
 678                         continue;
 679
 680                 if (connector->port != parent_port &&
 681                     !drm_dp_mst_port_downstream_of_parent(mst_mgr,
 682                                                           connector->port,
 683                                                           parent_port))
 684                         continue;
 685
 686                 mask |= BIT(to_intel_crtc(conn_state->base.crtc)->pipe);
 687         }
 688
 689         return mask;
 690 }
 691
 692 static int intel_dp_mst_check_fec_change(struct intel_atomic_state *state,
 693                                          struct drm_dp_mst_topology_mgr *mst_mgr,
 694                                          struct intel_link_bw_limits *limits)
 695 {
 696         struct drm_i915_private *i915 = to_i915(state->base.dev);
 697         struct intel_crtc *crtc;
 698         u8 mst_pipe_mask;
 699         u8 fec_pipe_mask = 0;
 700         int ret;
 701
 702         mst_pipe_mask = get_pipes_downstream_of_mst_port(state, mst_mgr, NULL);
 703
 704         for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, mst_pipe_mask) {
 705                 struct intel_crtc_state *crtc_state =
 706                         intel_atomic_get_new_crtc_state(state, crtc);
 707
 708                 /* Atomic connector check should've added all the MST CRTCs. */
 709                 if (drm_WARN_ON(&i915->drm, !crtc_state))
 710                         return -EINVAL;
 711
 712                 if (crtc_state->fec_enable)
 713                         fec_pipe_mask |= BIT(crtc->pipe);
 714         }
 715
 716         if (!fec_pipe_mask || mst_pipe_mask == fec_pipe_mask)
 717                 return 0;
 718
 719         limits->force_fec_pipes |= mst_pipe_mask;
 720
 721         ret = intel_modeset_pipes_in_mask_early(state, "MST FEC",
 722                                                 mst_pipe_mask);
 723
 724         return ret ? : -EAGAIN;
 725 }
 726
 727 static int intel_dp_mst_check_bw(struct intel_atomic_state *state,
 728                                  struct drm_dp_mst_topology_mgr *mst_mgr,
 729                                  struct drm_dp_mst_topology_state *mst_state,
 730                                  struct intel_link_bw_limits *limits)
 731 {
 732         struct drm_dp_mst_port *mst_port;
 733         u8 mst_port_pipes;
 734         int ret;
 735
 736         ret = drm_dp_mst_atomic_check_mgr(&state->base, mst_mgr, mst_state, &mst_port);
 737         if (ret != -ENOSPC)
 738                 return ret;
 739
 740         mst_port_pipes = get_pipes_downstream_of_mst_port(state, mst_mgr, mst_port);
 741
 742         ret = intel_link_bw_reduce_bpp(state, limits,
 743                                        mst_port_pipes, "MST link BW");
 744
 745         return ret ? : -EAGAIN;
 746 }
 747
 748 /**
 749  * intel_dp_mst_atomic_check_link - check all modeset MST link configuration
 750  * @state: intel atomic state
 751  * @limits: link BW limits
 752  *
 753  * Check the link configuration for all modeset MST outputs. If the
 754  * configuration is invalid @limits will be updated if possible to
 755  * reduce the total BW, after which the configuration for all CRTCs in
 756  * @state must be recomputed with the updated @limits.
 757  *
 758  * Returns:
 759  *   - 0 if the confugration is valid
 760  *   - %-EAGAIN, if the configuration is invalid and @limits got updated
 761  *     with fallback values with which the configuration of all CRTCs in
 762  *     @state must be recomputed
 763  *   - Other negative error, if the configuration is invalid without a
 764  *     fallback possibility, or the check failed for another reason
 765  */
 766 int intel_dp_mst_atomic_check_link(struct intel_atomic_state *state,
 767                                    struct intel_link_bw_limits *limits)
 768 {
 769         struct drm_dp_mst_topology_mgr *mgr;
 770         struct drm_dp_mst_topology_state *mst_state;
 771         int ret;
 772         int i;
 773
 774         for_each_new_mst_mgr_in_state(&state->base, mgr, mst_state, i) {
 775                 ret = intel_dp_mst_check_fec_change(state, mgr, limits);
 776                 if (ret)
 777                         return ret;
 778
 779                 ret = intel_dp_mst_check_bw(state, mgr, mst_state,
 780                                             limits);
 781                 if (ret)
 782                         return ret;
 783         }
 784
 785         return 0;
 786 }
 787
 788 static int intel_dp_mst_compute_config_late(struct intel_encoder *encoder,
 789                                             struct intel_crtc_state *crtc_state,
 790                                             struct drm_connector_state *conn_state)
 791 {
 792         struct intel_atomic_state *state = to_intel_atomic_state(conn_state->state);
 793         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
 794         struct intel_dp *intel_dp = &intel_mst->primary->dp;
 795
 796         /* lowest numbered transcoder will be designated master */
 797         crtc_state->mst_master_transcoder =
 798                 ffs(intel_dp_mst_transcoder_mask(state, intel_dp)) - 1;
 799
 800         return 0;
 801 }
 802
 803 /*
 804  * If one of the connectors in a MST stream needs a modeset, mark all CRTCs
 805  * that shares the same MST stream as mode changed,
 806  * intel_modeset_pipe_config()+intel_crtc_check_fastset() will take care to do
 807  * a fastset when possible.
 808  *
 809  * On TGL+ this is required since each stream go through a master transcoder,
 810  * so if the master transcoder needs modeset, all other streams in the
 811  * topology need a modeset. All platforms need to add the atomic state
 812  * for all streams in the topology, since a modeset on one may require
 813  * changing the MST link BW usage of the others, which in turn needs a
 814  * recomputation of the corresponding CRTC states.
 815  */
 816 static int
 817 intel_dp_mst_atomic_topology_check(struct intel_connector *connector,
 818                                    struct intel_atomic_state *state)
 819 {
 820         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 821         struct drm_connector_list_iter connector_list_iter;
 822         struct intel_connector *connector_iter;
 823         int ret = 0;
 824
 825         if (!intel_connector_needs_modeset(state, &connector->base))
 826                 return 0;
 827
 828         drm_connector_list_iter_begin(&dev_priv->drm, &connector_list_iter);
 829         for_each_intel_connector_iter(connector_iter, &connector_list_iter) {
 830                 struct intel_digital_connector_state *conn_iter_state;
 831                 struct intel_crtc_state *crtc_state;
 832                 struct intel_crtc *crtc;
 833
 834                 if (connector_iter->mst_port != connector->mst_port ||
 835                     connector_iter == connector)
 836                         continue;
 837
 838                 conn_iter_state = intel_atomic_get_digital_connector_state(state,
 839                                                                            connector_iter);
 840                 if (IS_ERR(conn_iter_state)) {
 841                         ret = PTR_ERR(conn_iter_state);
 842                         break;
 843                 }
 844
 845                 if (!conn_iter_state->base.crtc)
 846                         continue;
 847
 848                 crtc = to_intel_crtc(conn_iter_state->base.crtc);
 849                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
 850                 if (IS_ERR(crtc_state)) {
 851                         ret = PTR_ERR(crtc_state);
 852                         break;
 853                 }
 854
 855                 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
 856                 if (ret)
 857                         break;
 858                 crtc_state->uapi.mode_changed = true;
 859         }
 860         drm_connector_list_iter_end(&connector_list_iter);
 861
 862         return ret;
 863 }
 864
 865 static int
 866 intel_dp_mst_atomic_check(struct drm_connector *connector,
 867                           struct drm_atomic_state *_state)
 868 {
 869         struct intel_atomic_state *state = to_intel_atomic_state(_state);
 870         struct intel_connector *intel_connector =
 871                 to_intel_connector(connector);
 872         int ret;
 873
 874         ret = intel_digital_connector_atomic_check(connector, &state->base);
 875         if (ret)
 876                 return ret;
 877
 878         ret = intel_dp_mst_atomic_topology_check(intel_connector, state);
 879         if (ret)
 880                 return ret;
 881
 882         if (intel_connector_needs_modeset(state, connector)) {
 883                 ret = intel_dp_tunnel_atomic_check_state(state,
 884                                                          intel_connector->mst_port,
 885                                                          intel_connector);
 886                 if (ret)
 887                         return ret;
 888         }
 889
 890         return drm_dp_atomic_release_time_slots(&state->base,
 891                                                 &intel_connector->mst_port->mst_mgr,
 892                                                 intel_connector->port);
 893 }
 894
 895 static void clear_act_sent(struct intel_encoder *encoder,
 896                            const struct intel_crtc_state *crtc_state)
 897 {
 898         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 899
 900         intel_de_write(i915, dp_tp_status_reg(encoder, crtc_state),
 901                        DP_TP_STATUS_ACT_SENT);
 902 }
 903
 904 static void wait_for_act_sent(struct intel_encoder *encoder,
 905                               const struct intel_crtc_state *crtc_state)
 906 {
 907         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 908         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
 909         struct intel_dp *intel_dp = &intel_mst->primary->dp;
 910
 911         if (intel_de_wait_for_set(i915, dp_tp_status_reg(encoder, crtc_state),
 912                                   DP_TP_STATUS_ACT_SENT, 1))
 913                 drm_err(&i915->drm, "Timed out waiting for ACT sent\n");
 914
 915         drm_dp_check_act_status(&intel_dp->mst_mgr);
 916 }
 917
 918 static void intel_mst_disable_dp(struct intel_atomic_state *state,
 919                                  struct intel_encoder *encoder,
 920                                  const struct intel_crtc_state *old_crtc_state,
 921                                  const struct drm_connector_state *old_conn_state)
 922 {
 923         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
 924         struct intel_digital_port *dig_port = intel_mst->primary;
 925         struct intel_dp *intel_dp = &dig_port->dp;
 926         struct intel_connector *connector =
 927                 to_intel_connector(old_conn_state->connector);
 928         struct drm_i915_private *i915 = to_i915(connector->base.dev);
 929
 930         drm_dbg_kms(&i915->drm, "active links %d\n",
 931                     intel_dp->active_mst_links);
 932
 933         intel_hdcp_disable(intel_mst->connector);
 934
 935         intel_dp_sink_disable_decompression(state, connector, old_crtc_state);
 936 }
 937
 938 static void intel_mst_post_disable_dp(struct intel_atomic_state *state,
 939                                       struct intel_encoder *encoder,
 940                                       const struct intel_crtc_state *old_crtc_state,
 941                                       const struct drm_connector_state *old_conn_state)
 942 {
 943         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
 944         struct intel_digital_port *dig_port = intel_mst->primary;
 945         struct intel_dp *intel_dp = &dig_port->dp;
 946         struct intel_connector *connector =
 947                 to_intel_connector(old_conn_state->connector);
 948         struct drm_dp_mst_topology_state *old_mst_state =
 949                 drm_atomic_get_old_mst_topology_state(&state->base, &intel_dp->mst_mgr);
 950         struct drm_dp_mst_topology_state *new_mst_state =
 951                 drm_atomic_get_new_mst_topology_state(&state->base, &intel_dp->mst_mgr);
 952         const struct drm_dp_mst_atomic_payload *old_payload =
 953                 drm_atomic_get_mst_payload_state(old_mst_state, connector->port);
 954         struct drm_dp_mst_atomic_payload *new_payload =
 955                 drm_atomic_get_mst_payload_state(new_mst_state, connector->port);
 956         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
 957         bool last_mst_stream;
 958
 959         intel_dp->active_mst_links--;
 960         last_mst_stream = intel_dp->active_mst_links == 0;
 961         drm_WARN_ON(&dev_priv->drm,
 962                     DISPLAY_VER(dev_priv) >= 12 && last_mst_stream &&
 963                     !intel_dp_mst_is_master_trans(old_crtc_state));
 964
 965         intel_crtc_vblank_off(old_crtc_state);
 966
 967         intel_disable_transcoder(old_crtc_state);
 968
 969         drm_dp_remove_payload_part1(&intel_dp->mst_mgr, new_mst_state, new_payload);
 970
 971         clear_act_sent(encoder, old_crtc_state);
 972
 973         intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(old_crtc_state->cpu_transcoder),
 974                      TRANS_DDI_DP_VC_PAYLOAD_ALLOC, 0);
 975
 976         wait_for_act_sent(encoder, old_crtc_state);
 977
 978         drm_dp_remove_payload_part2(&intel_dp->mst_mgr, new_mst_state,
 979                                     old_payload, new_payload);
 980
 981         intel_ddi_disable_transcoder_func(old_crtc_state);
 982
 983         intel_dsc_disable(old_crtc_state);
 984
 985         if (DISPLAY_VER(dev_priv) >= 9)
 986                 skl_scaler_disable(old_crtc_state);
 987         else
 988                 ilk_pfit_disable(old_crtc_state);
 989
 990         /*
 991          * Power down mst path before disabling the port, otherwise we end
 992          * up getting interrupts from the sink upon detecting link loss.
 993          */
 994         drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port,
 995                                      false);
 996
 997         /*
 998          * BSpec 4287: disable DIP after the transcoder is disabled and before
 999          * the transcoder clock select is set to none.
1000          */
1001         intel_dp_set_infoframes(&dig_port->base, false,
1002                                 old_crtc_state, NULL);
1003         /*
1004          * From TGL spec: "If multi-stream slave transcoder: Configure
1005          * Transcoder Clock Select to direct no clock to the transcoder"
1006          *
1007          * From older GENs spec: "Configure Transcoder Clock Select to direct
1008          * no clock to the transcoder"
1009          */
1010         if (DISPLAY_VER(dev_priv) < 12 || !last_mst_stream)
1011                 intel_ddi_disable_transcoder_clock(old_crtc_state);
1012
1013
1014         intel_mst->connector = NULL;
1015         if (last_mst_stream)
1016                 dig_port->base.post_disable(state, &dig_port->base,
1017                                                   old_crtc_state, NULL);
1018
1019         drm_dbg_kms(&dev_priv->drm, "active links %d\n",
1020                     intel_dp->active_mst_links);
1021 }
1022
1023 static void intel_mst_post_pll_disable_dp(struct intel_atomic_state *state,
1024                                           struct intel_encoder *encoder,
1025                                           const struct intel_crtc_state *old_crtc_state,
1026                                           const struct drm_connector_state *old_conn_state)
1027 {
1028         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
1029         struct intel_digital_port *dig_port = intel_mst->primary;
1030         struct intel_dp *intel_dp = &dig_port->dp;
1031
1032         if (intel_dp->active_mst_links == 0 &&
1033             dig_port->base.post_pll_disable)
1034                 dig_port->base.post_pll_disable(state, encoder, old_crtc_state, old_conn_state);
1035 }
1036
1037 static void intel_mst_pre_pll_enable_dp(struct intel_atomic_state *state,
1038                                         struct intel_encoder *encoder,
1039                                         const struct intel_crtc_state *pipe_config,
1040                                         const struct drm_connector_state *conn_state)
1041 {
1042         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
1043         struct intel_digital_port *dig_port = intel_mst->primary;
1044         struct intel_dp *intel_dp = &dig_port->dp;
1045
1046         if (intel_dp->active_mst_links == 0)
1047                 dig_port->base.pre_pll_enable(state, &dig_port->base,
1048                                                     pipe_config, NULL);
1049         else
1050                 /*
1051                  * The port PLL state needs to get updated for secondary
1052                  * streams as for the primary stream.
1053                  */
1054                 intel_ddi_update_active_dpll(state, &dig_port->base,
1055                                              to_intel_crtc(pipe_config->uapi.crtc));
1056 }
1057
1058 static void intel_mst_pre_enable_dp(struct intel_atomic_state *state,
1059                                     struct intel_encoder *encoder,
1060                                     const struct intel_crtc_state *pipe_config,
1061                                     const struct drm_connector_state *conn_state)
1062 {
1063         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
1064         struct intel_digital_port *dig_port = intel_mst->primary;
1065         struct intel_dp *intel_dp = &dig_port->dp;
1066         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1067         struct intel_connector *connector =
1068                 to_intel_connector(conn_state->connector);
1069         struct drm_dp_mst_topology_state *mst_state =
1070                 drm_atomic_get_new_mst_topology_state(&state->base, &intel_dp->mst_mgr);
1071         int ret;
1072         bool first_mst_stream;
1073
1074         /* MST encoders are bound to a crtc, not to a connector,
1075          * force the mapping here for get_hw_state.
1076          */
1077         connector->encoder = encoder;
1078         intel_mst->connector = connector;
1079         first_mst_stream = intel_dp->active_mst_links == 0;
1080         drm_WARN_ON(&dev_priv->drm,
1081                     DISPLAY_VER(dev_priv) >= 12 && first_mst_stream &&
1082                     !intel_dp_mst_is_master_trans(pipe_config));
1083
1084         drm_dbg_kms(&dev_priv->drm, "active links %d\n",
1085                     intel_dp->active_mst_links);
1086
1087         if (first_mst_stream)
1088                 intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
1089
1090         drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port, true);
1091
1092         intel_dp_sink_enable_decompression(state, connector, pipe_config);
1093
1094         if (first_mst_stream)
1095                 dig_port->base.pre_enable(state, &dig_port->base,
1096                                                 pipe_config, NULL);
1097
1098         intel_dp->active_mst_links++;
1099
1100         ret = drm_dp_add_payload_part1(&intel_dp->mst_mgr, mst_state,
1101                                        drm_atomic_get_mst_payload_state(mst_state, connector->port));
1102         if (ret < 0)
1103                 drm_dbg_kms(&dev_priv->drm, "Failed to create MST payload for %s: %d\n",
1104                             connector->base.name, ret);
1105
1106         /*
1107          * Before Gen 12 this is not done as part of
1108          * dig_port->base.pre_enable() and should be done here. For
1109          * Gen 12+ the step in which this should be done is different for the
1110          * first MST stream, so it's done on the DDI for the first stream and
1111          * here for the following ones.
1112          */
1113         if (DISPLAY_VER(dev_priv) < 12 || !first_mst_stream)
1114                 intel_ddi_enable_transcoder_clock(encoder, pipe_config);
1115
1116         intel_dsc_dp_pps_write(&dig_port->base, pipe_config);
1117         intel_ddi_set_dp_msa(pipe_config, conn_state);
1118 }
1119
1120 static void intel_mst_enable_dp(struct intel_atomic_state *state,
1121                                 struct intel_encoder *encoder,
1122                                 const struct intel_crtc_state *pipe_config,
1123                                 const struct drm_connector_state *conn_state)
1124 {
1125         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
1126         struct intel_digital_port *dig_port = intel_mst->primary;
1127         struct intel_dp *intel_dp = &dig_port->dp;
1128         struct intel_connector *connector = to_intel_connector(conn_state->connector);
1129         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1130         struct drm_dp_mst_topology_state *mst_state =
1131                 drm_atomic_get_new_mst_topology_state(&state->base, &intel_dp->mst_mgr);
1132         enum transcoder trans = pipe_config->cpu_transcoder;
1133         bool first_mst_stream = intel_dp->active_mst_links == 1;
1134
1135         drm_WARN_ON(&dev_priv->drm, pipe_config->has_pch_encoder);
1136
1137         if (intel_dp_is_uhbr(pipe_config)) {
1138                 const struct drm_display_mode *adjusted_mode =
1139                         &pipe_config->hw.adjusted_mode;
1140                 u64 crtc_clock_hz = KHz(adjusted_mode->crtc_clock);
1141
1142                 intel_de_write(dev_priv, TRANS_DP2_VFREQHIGH(pipe_config->cpu_transcoder),
1143                                TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz >> 24));
1144                 intel_de_write(dev_priv, TRANS_DP2_VFREQLOW(pipe_config->cpu_transcoder),
1145                                TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 0xffffff));
1146         }
1147
1148         intel_ddi_enable_transcoder_func(encoder, pipe_config);
1149
1150         clear_act_sent(encoder, pipe_config);
1151
1152         intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(trans), 0,
1153                      TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1154
1155         drm_dbg_kms(&dev_priv->drm, "active links %d\n",
1156                     intel_dp->active_mst_links);
1157
1158         wait_for_act_sent(encoder, pipe_config);
1159
1160         if (first_mst_stream)
1161                 intel_ddi_wait_for_fec_status(encoder, pipe_config, true);
1162
1163         drm_dp_add_payload_part2(&intel_dp->mst_mgr, &state->base,
1164                                  drm_atomic_get_mst_payload_state(mst_state, connector->port));
1165
1166         if (DISPLAY_VER(dev_priv) >= 12)
1167                 intel_de_rmw(dev_priv, hsw_chicken_trans_reg(dev_priv, trans),
1168                              FECSTALL_DIS_DPTSTREAM_DPTTG,
1169                              pipe_config->fec_enable ? FECSTALL_DIS_DPTSTREAM_DPTTG : 0);
1170
1171         intel_audio_sdp_split_update(pipe_config);
1172
1173         intel_enable_transcoder(pipe_config);
1174
1175         intel_crtc_vblank_on(pipe_config);
1176
1177         intel_hdcp_enable(state, encoder, pipe_config, conn_state);
1178 }
1179
1180 static bool intel_dp_mst_enc_get_hw_state(struct intel_encoder *encoder,
1181                                       enum pipe *pipe)
1182 {
1183         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
1184         *pipe = intel_mst->pipe;
1185         if (intel_mst->connector)
1186                 return true;
1187         return false;
1188 }
1189
1190 static void intel_dp_mst_enc_get_config(struct intel_encoder *encoder,
1191                                         struct intel_crtc_state *pipe_config)
1192 {
1193         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
1194         struct intel_digital_port *dig_port = intel_mst->primary;
1195
1196         dig_port->base.get_config(&dig_port->base, pipe_config);
1197 }
1198
1199 static bool intel_dp_mst_initial_fastset_check(struct intel_encoder *encoder,
1200                                                struct intel_crtc_state *crtc_state)
1201 {
1202         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
1203         struct intel_digital_port *dig_port = intel_mst->primary;
1204
1205         return intel_dp_initial_fastset_check(&dig_port->base, crtc_state);
1206 }
1207
1208 static int intel_dp_mst_get_ddc_modes(struct drm_connector *connector)
1209 {
1210         struct intel_connector *intel_connector = to_intel_connector(connector);
1211         struct drm_i915_private *i915 = to_i915(intel_connector->base.dev);
1212         struct intel_dp *intel_dp = intel_connector->mst_port;
1213         const struct drm_edid *drm_edid;
1214         int ret;
1215
1216         if (drm_connector_is_unregistered(connector))
1217                 return intel_connector_update_modes(connector, NULL);
1218
1219         if (!intel_display_driver_check_access(i915))
1220                 return drm_edid_connector_add_modes(connector);
1221
1222         drm_edid = drm_dp_mst_edid_read(connector, &intel_dp->mst_mgr, intel_connector->port);
1223
1224         ret = intel_connector_update_modes(connector, drm_edid);
1225
1226         drm_edid_free(drm_edid);
1227
1228         return ret;
1229 }
1230
1231 static int
1232 intel_dp_mst_connector_late_register(struct drm_connector *connector)
1233 {
1234         struct intel_connector *intel_connector = to_intel_connector(connector);
1235         int ret;
1236
1237         ret = drm_dp_mst_connector_late_register(connector,
1238                                                  intel_connector->port);
1239         if (ret < 0)
1240                 return ret;
1241
1242         ret = intel_connector_register(connector);
1243         if (ret < 0)
1244                 drm_dp_mst_connector_early_unregister(connector,
1245                                                       intel_connector->port);
1246
1247         return ret;
1248 }
1249
1250 static void
1251 intel_dp_mst_connector_early_unregister(struct drm_connector *connector)
1252 {
1253         struct intel_connector *intel_connector = to_intel_connector(connector);
1254
1255         intel_connector_unregister(connector);
1256         drm_dp_mst_connector_early_unregister(connector,
1257                                               intel_connector->port);
1258 }
1259
1260 static const struct drm_connector_funcs intel_dp_mst_connector_funcs = {
1261         .fill_modes = drm_helper_probe_single_connector_modes,
1262         .atomic_get_property = intel_digital_connector_atomic_get_property,
1263         .atomic_set_property = intel_digital_connector_atomic_set_property,
1264         .late_register = intel_dp_mst_connector_late_register,
1265         .early_unregister = intel_dp_mst_connector_early_unregister,
1266         .destroy = intel_connector_destroy,
1267         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1268         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
1269 };
1270
1271 static int intel_dp_mst_get_modes(struct drm_connector *connector)
1272 {
1273         return intel_dp_mst_get_ddc_modes(connector);
1274 }
1275
1276 static int
1277 intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
1278                             struct drm_display_mode *mode,
1279                             struct drm_modeset_acquire_ctx *ctx,
1280                             enum drm_mode_status *status)
1281 {
1282         struct drm_i915_private *dev_priv = to_i915(connector->dev);
1283         struct intel_connector *intel_connector = to_intel_connector(connector);
1284         struct intel_dp *intel_dp = intel_connector->mst_port;
1285         struct drm_dp_mst_topology_mgr *mgr = &intel_dp->mst_mgr;
1286         struct drm_dp_mst_port *port = intel_connector->port;
1287         const int min_bpp = 18;
1288         int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
1289         int max_rate, mode_rate, max_lanes, max_link_clock;
1290         int ret;
1291         bool dsc = false, bigjoiner = false;
1292         u16 dsc_max_compressed_bpp = 0;
1293         u8 dsc_slice_count = 0;
1294         int target_clock = mode->clock;
1295
1296         if (drm_connector_is_unregistered(connector)) {
1297                 *status = MODE_ERROR;
1298                 return 0;
1299         }
1300
1301         *status = intel_cpu_transcoder_mode_valid(dev_priv, mode);
1302         if (*status != MODE_OK)
1303                 return 0;
1304
1305         if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {
1306                 *status = MODE_NO_DBLESCAN;
1307                 return 0;
1308         }
1309
1310         max_link_clock = intel_dp_max_link_rate(intel_dp);
1311         max_lanes = intel_dp_max_lane_count(intel_dp);
1312
1313         max_rate = intel_dp_max_link_data_rate(intel_dp,
1314                                                max_link_clock, max_lanes);
1315         mode_rate = intel_dp_link_required(mode->clock, min_bpp);
1316
1317         ret = drm_modeset_lock(&mgr->base.lock, ctx);
1318         if (ret)
1319                 return ret;
1320
1321         /*
1322          * TODO:
1323          * - Also check if compression would allow for the mode
1324          * - Calculate the overhead using drm_dp_bw_overhead() /
1325          *   drm_dp_bw_channel_coding_efficiency(), similarly to the
1326          *   compute config code, as drm_dp_calc_pbn_mode() doesn't
1327          *   account with all the overheads.
1328          * - Check here and during compute config the BW reported by
1329          *   DFP_Link_Available_Payload_Bandwidth_Number (or the
1330          *   corresponding link capabilities of the sink) in case the
1331          *   stream is uncompressed for it by the last branch device.
1332          */
1333         if (mode_rate > max_rate || mode->clock > max_dotclk ||
1334             drm_dp_calc_pbn_mode(mode->clock, min_bpp << 4) > port->full_pbn) {
1335                 *status = MODE_CLOCK_HIGH;
1336                 return 0;
1337         }
1338
1339         if (mode->clock < 10000) {
1340                 *status = MODE_CLOCK_LOW;
1341                 return 0;
1342         }
1343
1344         if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
1345                 *status = MODE_H_ILLEGAL;
1346                 return 0;
1347         }
1348
1349         if (intel_dp_need_bigjoiner(intel_dp, mode->hdisplay, target_clock)) {
1350                 bigjoiner = true;
1351                 max_dotclk *= 2;
1352
1353                 /* TODO: add support for bigjoiner */
1354                 *status = MODE_CLOCK_HIGH;
1355                 return 0;
1356         }
1357
1358         if (DISPLAY_VER(dev_priv) >= 10 &&
1359             drm_dp_sink_supports_dsc(intel_connector->dp.dsc_dpcd)) {
1360                 /*
1361                  * TBD pass the connector BPC,
1362                  * for now U8_MAX so that max BPC on that platform would be picked
1363                  */
1364                 int pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_connector, U8_MAX);
1365
1366                 if (drm_dp_sink_supports_fec(intel_connector->dp.fec_capability)) {
1367                         dsc_max_compressed_bpp =
1368                                 intel_dp_dsc_get_max_compressed_bpp(dev_priv,
1369                                                                     max_link_clock,
1370                                                                     max_lanes,
1371                                                                     target_clock,
1372                                                                     mode->hdisplay,
1373                                                                     bigjoiner,
1374                                                                     INTEL_OUTPUT_FORMAT_RGB,
1375                                                                     pipe_bpp, 64);
1376                         dsc_slice_count =
1377                                 intel_dp_dsc_get_slice_count(intel_connector,
1378                                                              target_clock,
1379                                                              mode->hdisplay,
1380                                                              bigjoiner);
1381                 }
1382
1383                 dsc = dsc_max_compressed_bpp && dsc_slice_count;
1384         }
1385
1386         /*
1387          * Big joiner configuration needs DSC for TGL which is not true for
1388          * XE_LPD where uncompressed joiner is supported.
1389          */
1390         if (DISPLAY_VER(dev_priv) < 13 && bigjoiner && !dsc) {
1391                 *status = MODE_CLOCK_HIGH;
1392                 return 0;
1393         }
1394
1395         if (mode_rate > max_rate && !dsc) {
1396                 *status = MODE_CLOCK_HIGH;
1397                 return 0;
1398         }
1399
1400         *status = intel_mode_valid_max_plane_size(dev_priv, mode, false);
1401         return 0;
1402 }
1403
1404 static struct drm_encoder *intel_mst_atomic_best_encoder(struct drm_connector *connector,
1405                                                          struct drm_atomic_state *state)
1406 {
1407         struct drm_connector_state *connector_state = drm_atomic_get_new_connector_state(state,
1408                                                                                          connector);
1409         struct intel_connector *intel_connector = to_intel_connector(connector);
1410         struct intel_dp *intel_dp = intel_connector->mst_port;
1411         struct intel_crtc *crtc = to_intel_crtc(connector_state->crtc);
1412
1413         return &intel_dp->mst_encoders[crtc->pipe]->base.base;
1414 }
1415
1416 static int
1417 intel_dp_mst_detect(struct drm_connector *connector,
1418                     struct drm_modeset_acquire_ctx *ctx, bool force)
1419 {
1420         struct drm_i915_private *i915 = to_i915(connector->dev);
1421         struct intel_connector *intel_connector = to_intel_connector(connector);
1422         struct intel_dp *intel_dp = intel_connector->mst_port;
1423
1424         if (!intel_display_device_enabled(i915))
1425                 return connector_status_disconnected;
1426
1427         if (drm_connector_is_unregistered(connector))
1428                 return connector_status_disconnected;
1429
1430         if (!intel_display_driver_check_access(i915))
1431                 return connector->status;
1432
1433         return drm_dp_mst_detect_port(connector, ctx, &intel_dp->mst_mgr,
1434                                       intel_connector->port);
1435 }
1436
1437 static const struct drm_connector_helper_funcs intel_dp_mst_connector_helper_funcs = {
1438         .get_modes = intel_dp_mst_get_modes,
1439         .mode_valid_ctx = intel_dp_mst_mode_valid_ctx,
1440         .atomic_best_encoder = intel_mst_atomic_best_encoder,
1441         .atomic_check = intel_dp_mst_atomic_check,
1442         .detect_ctx = intel_dp_mst_detect,
1443 };
1444
1445 static void intel_dp_mst_encoder_destroy(struct drm_encoder *encoder)
1446 {
1447         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(to_intel_encoder(encoder));
1448
1449         drm_encoder_cleanup(encoder);
1450         kfree(intel_mst);
1451 }
1452
1453 static const struct drm_encoder_funcs intel_dp_mst_enc_funcs = {
1454         .destroy = intel_dp_mst_encoder_destroy,
1455 };
1456
1457 static bool intel_dp_mst_get_hw_state(struct intel_connector *connector)
1458 {
1459         if (intel_attached_encoder(connector) && connector->base.state->crtc) {
1460                 enum pipe pipe;
1461                 if (!intel_attached_encoder(connector)->get_hw_state(intel_attached_encoder(connector), &pipe))
1462                         return false;
1463                 return true;
1464         }
1465         return false;
1466 }
1467
1468 static int intel_dp_mst_add_properties(struct intel_dp *intel_dp,
1469                                        struct drm_connector *connector,
1470                                        const char *pathprop)
1471 {
1472         struct drm_i915_private *i915 = to_i915(connector->dev);
1473
1474         drm_object_attach_property(&connector->base,
1475                                    i915->drm.mode_config.path_property, 0);
1476         drm_object_attach_property(&connector->base,
1477                                    i915->drm.mode_config.tile_property, 0);
1478
1479         intel_attach_force_audio_property(connector);
1480         intel_attach_broadcast_rgb_property(connector);
1481
1482         /*
1483          * Reuse the prop from the SST connector because we're
1484          * not allowed to create new props after device registration.
1485          */
1486         connector->max_bpc_property =
1487                 intel_dp->attached_connector->base.max_bpc_property;
1488         if (connector->max_bpc_property)
1489                 drm_connector_attach_max_bpc_property(connector, 6, 12);
1490
1491         return drm_connector_set_path_property(connector, pathprop);
1492 }
1493
1494 static void
1495 intel_dp_mst_read_decompression_port_dsc_caps(struct intel_dp *intel_dp,
1496                                               struct intel_connector *connector)
1497 {
1498         u8 dpcd_caps[DP_RECEIVER_CAP_SIZE];
1499
1500         if (!connector->dp.dsc_decompression_aux)
1501                 return;
1502
1503         if (drm_dp_read_dpcd_caps(connector->dp.dsc_decompression_aux, dpcd_caps) < 0)
1504                 return;
1505
1506         intel_dp_get_dsc_sink_cap(dpcd_caps[DP_DPCD_REV], connector);
1507 }
1508
1509 static bool detect_dsc_hblank_expansion_quirk(const struct intel_connector *connector)
1510 {
1511         struct drm_i915_private *i915 = to_i915(connector->base.dev);
1512         struct drm_dp_desc desc;
1513         u8 dpcd[DP_RECEIVER_CAP_SIZE];
1514
1515         if (!connector->dp.dsc_decompression_aux)
1516                 return false;
1517
1518         if (drm_dp_read_desc(connector->dp.dsc_decompression_aux,
1519                              &desc, true) < 0)
1520                 return false;
1521
1522         if (!drm_dp_has_quirk(&desc,
1523                               DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC))
1524                 return false;
1525
1526         if (drm_dp_read_dpcd_caps(connector->dp.dsc_decompression_aux, dpcd) < 0)
1527                 return false;
1528
1529         if (!(dpcd[DP_RECEIVE_PORT_0_CAP_0] & DP_HBLANK_EXPANSION_CAPABLE))
1530                 return false;
1531
1532         drm_dbg_kms(&i915->drm,
1533                     "[CONNECTOR:%d:%s] DSC HBLANK expansion quirk detected\n",
1534                     connector->base.base.id, connector->base.name);
1535
1536         return true;
1537 }
1538
1539 static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
1540                                                         struct drm_dp_mst_port *port,
1541                                                         const char *pathprop)
1542 {
1543         struct intel_dp *intel_dp = container_of(mgr, struct intel_dp, mst_mgr);
1544         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1545         struct drm_device *dev = dig_port->base.base.dev;
1546         struct drm_i915_private *dev_priv = to_i915(dev);
1547         struct intel_connector *intel_connector;
1548         struct drm_connector *connector;
1549         enum pipe pipe;
1550         int ret;
1551
1552         intel_connector = intel_connector_alloc();
1553         if (!intel_connector)
1554                 return NULL;
1555
1556         intel_connector->get_hw_state = intel_dp_mst_get_hw_state;
1557         intel_connector->mst_port = intel_dp;
1558         intel_connector->port = port;
1559         drm_dp_mst_get_port_malloc(port);
1560
1561         intel_dp_init_modeset_retry_work(intel_connector);
1562
1563         intel_connector->dp.dsc_decompression_aux = drm_dp_mst_dsc_aux_for_port(port);
1564         intel_dp_mst_read_decompression_port_dsc_caps(intel_dp, intel_connector);
1565         intel_connector->dp.dsc_hblank_expansion_quirk =
1566                 detect_dsc_hblank_expansion_quirk(intel_connector);
1567
1568         connector = &intel_connector->base;
1569         ret = drm_connector_init(dev, connector, &intel_dp_mst_connector_funcs,
1570                                  DRM_MODE_CONNECTOR_DisplayPort);
1571         if (ret) {
1572                 drm_dp_mst_put_port_malloc(port);
1573                 intel_connector_free(intel_connector);
1574                 return NULL;
1575         }
1576
1577         drm_connector_helper_add(connector, &intel_dp_mst_connector_helper_funcs);
1578
1579         for_each_pipe(dev_priv, pipe) {
1580                 struct drm_encoder *enc =
1581                         &intel_dp->mst_encoders[pipe]->base.base;
1582
1583                 ret = drm_connector_attach_encoder(&intel_connector->base, enc);
1584                 if (ret)
1585                         goto err;
1586         }
1587
1588         ret = intel_dp_mst_add_properties(intel_dp, connector, pathprop);
1589         if (ret)
1590                 goto err;
1591
1592         ret = intel_dp_hdcp_init(dig_port, intel_connector);
1593         if (ret)
1594                 drm_dbg_kms(&dev_priv->drm, "[%s:%d] HDCP MST init failed, skipping.\n",
1595                             connector->name, connector->base.id);
1596
1597         return connector;
1598
1599 err:
1600         drm_connector_cleanup(connector);
1601         return NULL;
1602 }
1603
1604 static void
1605 intel_dp_mst_poll_hpd_irq(struct drm_dp_mst_topology_mgr *mgr)
1606 {
1607         struct intel_dp *intel_dp = container_of(mgr, struct intel_dp, mst_mgr);
1608
1609         intel_hpd_trigger_irq(dp_to_dig_port(intel_dp));
1610 }
1611
1612 static const struct drm_dp_mst_topology_cbs mst_cbs = {
1613         .add_connector = intel_dp_add_mst_connector,
1614         .poll_hpd_irq = intel_dp_mst_poll_hpd_irq,
1615 };
1616
1617 static struct intel_dp_mst_encoder *
1618 intel_dp_create_fake_mst_encoder(struct intel_digital_port *dig_port, enum pipe pipe)
1619 {
1620         struct intel_dp_mst_encoder *intel_mst;
1621         struct intel_encoder *intel_encoder;
1622         struct drm_device *dev = dig_port->base.base.dev;
1623
1624         intel_mst = kzalloc(sizeof(*intel_mst), GFP_KERNEL);
1625
1626         if (!intel_mst)
1627                 return NULL;
1628
1629         intel_mst->pipe = pipe;
1630         intel_encoder = &intel_mst->base;
1631         intel_mst->primary = dig_port;
1632
1633         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_mst_enc_funcs,
1634                          DRM_MODE_ENCODER_DPMST, "DP-MST %c", pipe_name(pipe));
1635
1636         intel_encoder->type = INTEL_OUTPUT_DP_MST;
1637         intel_encoder->power_domain = dig_port->base.power_domain;
1638         intel_encoder->port = dig_port->base.port;
1639         intel_encoder->cloneable = 0;
1640         /*
1641          * This is wrong, but broken userspace uses the intersection
1642          * of possible_crtcs of all the encoders of a given connector
1643          * to figure out which crtcs can drive said connector. What
1644          * should be used instead is the union of possible_crtcs.
1645          * To keep such userspace functioning we must misconfigure
1646          * this to make sure the intersection is not empty :(
1647          */
1648         intel_encoder->pipe_mask = ~0;
1649
1650         intel_encoder->compute_config = intel_dp_mst_compute_config;
1651         intel_encoder->compute_config_late = intel_dp_mst_compute_config_late;
1652         intel_encoder->disable = intel_mst_disable_dp;
1653         intel_encoder->post_disable = intel_mst_post_disable_dp;
1654         intel_encoder->post_pll_disable = intel_mst_post_pll_disable_dp;
1655         intel_encoder->update_pipe = intel_ddi_update_pipe;
1656         intel_encoder->pre_pll_enable = intel_mst_pre_pll_enable_dp;
1657         intel_encoder->pre_enable = intel_mst_pre_enable_dp;
1658         intel_encoder->enable = intel_mst_enable_dp;
1659         intel_encoder->audio_enable = intel_audio_codec_enable;
1660         intel_encoder->audio_disable = intel_audio_codec_disable;
1661         intel_encoder->get_hw_state = intel_dp_mst_enc_get_hw_state;
1662         intel_encoder->get_config = intel_dp_mst_enc_get_config;
1663         intel_encoder->initial_fastset_check = intel_dp_mst_initial_fastset_check;
1664
1665         return intel_mst;
1666
1667 }
1668
1669 static bool
1670 intel_dp_create_fake_mst_encoders(struct intel_digital_port *dig_port)
1671 {
1672         struct intel_dp *intel_dp = &dig_port->dp;
1673         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
1674         enum pipe pipe;
1675
1676         for_each_pipe(dev_priv, pipe)
1677                 intel_dp->mst_encoders[pipe] = intel_dp_create_fake_mst_encoder(dig_port, pipe);
1678         return true;
1679 }
1680
1681 int
1682 intel_dp_mst_encoder_active_links(struct intel_digital_port *dig_port)
1683 {
1684         return dig_port->dp.active_mst_links;
1685 }
1686
1687 int
1688 intel_dp_mst_encoder_init(struct intel_digital_port *dig_port, int conn_base_id)
1689 {
1690         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1691         struct intel_dp *intel_dp = &dig_port->dp;
1692         enum port port = dig_port->base.port;
1693         int ret;
1694
1695         if (!HAS_DP_MST(i915) || intel_dp_is_edp(intel_dp))
1696                 return 0;
1697
1698         if (DISPLAY_VER(i915) < 12 && port == PORT_A)
1699                 return 0;
1700
1701         if (DISPLAY_VER(i915) < 11 && port == PORT_E)
1702                 return 0;
1703
1704         intel_dp->mst_mgr.cbs = &mst_cbs;
1705
1706         /* create encoders */
1707         intel_dp_create_fake_mst_encoders(dig_port);
1708         ret = drm_dp_mst_topology_mgr_init(&intel_dp->mst_mgr, &i915->drm,
1709                                            &intel_dp->aux, 16, 3, conn_base_id);
1710         if (ret) {
1711                 intel_dp->mst_mgr.cbs = NULL;
1712                 return ret;
1713         }
1714
1715         return 0;
1716 }
1717
1718 bool intel_dp_mst_source_support(struct intel_dp *intel_dp)
1719 {
1720         return intel_dp->mst_mgr.cbs;
1721 }
1722
1723 void
1724 intel_dp_mst_encoder_cleanup(struct intel_digital_port *dig_port)
1725 {
1726         struct intel_dp *intel_dp = &dig_port->dp;
1727
1728         if (!intel_dp_mst_source_support(intel_dp))
1729                 return;
1730
1731         drm_dp_mst_topology_mgr_destroy(&intel_dp->mst_mgr);
1732         /* encoders will get killed by normal cleanup */
1733
1734         intel_dp->mst_mgr.cbs = NULL;
1735 }
1736
1737 bool intel_dp_mst_is_master_trans(const struct intel_crtc_state *crtc_state)
1738 {
1739         return crtc_state->mst_master_transcoder == crtc_state->cpu_transcoder;
1740 }
1741
1742 bool intel_dp_mst_is_slave_trans(const struct intel_crtc_state *crtc_state)
1743 {
1744         return crtc_state->mst_master_transcoder != INVALID_TRANSCODER &&
1745                crtc_state->mst_master_transcoder != crtc_state->cpu_transcoder;
1746 }
1747
1748 /**
1749  * intel_dp_mst_add_topology_state_for_connector - add MST topology state for a connector
1750  * @state: atomic state
1751  * @connector: connector to add the state for
1752  * @crtc: the CRTC @connector is attached to
1753  *
1754  * Add the MST topology state for @connector to @state.
1755  *
1756  * Returns 0 on success, negative error code on failure.
1757  */
1758 static int
1759 intel_dp_mst_add_topology_state_for_connector(struct intel_atomic_state *state,
1760                                               struct intel_connector *connector,
1761                                               struct intel_crtc *crtc)
1762 {
1763         struct drm_dp_mst_topology_state *mst_state;
1764
1765         if (!connector->mst_port)
1766                 return 0;
1767
1768         mst_state = drm_atomic_get_mst_topology_state(&state->base,
1769                                                       &connector->mst_port->mst_mgr);
1770         if (IS_ERR(mst_state))
1771                 return PTR_ERR(mst_state);
1772
1773         mst_state->pending_crtc_mask |= drm_crtc_mask(&crtc->base);
1774
1775         return 0;
1776 }
1777
1778 /**
1779  * intel_dp_mst_add_topology_state_for_crtc - add MST topology state for a CRTC
1780  * @state: atomic state
1781  * @crtc: CRTC to add the state for
1782  *
1783  * Add the MST topology state for @crtc to @state.
1784  *
1785  * Returns 0 on success, negative error code on failure.
1786  */
1787 int intel_dp_mst_add_topology_state_for_crtc(struct intel_atomic_state *state,
1788                                              struct intel_crtc *crtc)
1789 {
1790         struct drm_connector *_connector;
1791         struct drm_connector_state *conn_state;
1792         int i;
1793
1794         for_each_new_connector_in_state(&state->base, _connector, conn_state, i) {
1795                 struct intel_connector *connector = to_intel_connector(_connector);
1796                 int ret;
1797
1798                 if (conn_state->crtc != &crtc->base)
1799                         continue;
1800
1801                 ret = intel_dp_mst_add_topology_state_for_connector(state, connector, crtc);
1802                 if (ret)
1803                         return ret;
1804         }
1805
1806         return 0;
1807 }
1808
1809 static struct intel_connector *
1810 get_connector_in_state_for_crtc(struct intel_atomic_state *state,
1811                                 const struct intel_crtc *crtc)
1812 {
1813         struct drm_connector_state *old_conn_state;
1814         struct drm_connector_state *new_conn_state;
1815         struct drm_connector *_connector;
1816         int i;
1817
1818         for_each_oldnew_connector_in_state(&state->base, _connector,
1819                                            old_conn_state, new_conn_state, i) {
1820                 struct intel_connector *connector =
1821                         to_intel_connector(_connector);
1822
1823                 if (old_conn_state->crtc == &crtc->base ||
1824                     new_conn_state->crtc == &crtc->base)
1825                         return connector;
1826         }
1827
1828         return NULL;
1829 }
1830
1831 /**
1832  * intel_dp_mst_crtc_needs_modeset - check if changes in topology need to modeset the given CRTC
1833  * @state: atomic state
1834  * @crtc: CRTC for which to check the modeset requirement
1835  *
1836  * Check if any change in a MST topology requires a forced modeset on @crtc in
1837  * this topology. One such change is enabling/disabling the DSC decompression
1838  * state in the first branch device's UFP DPCD as required by one CRTC, while
1839  * the other @crtc in the same topology is still active, requiring a full modeset
1840  * on @crtc.
1841  */
1842 bool intel_dp_mst_crtc_needs_modeset(struct intel_atomic_state *state,
1843                                      struct intel_crtc *crtc)
1844 {
1845         const struct intel_connector *crtc_connector;
1846         const struct drm_connector_state *conn_state;
1847         const struct drm_connector *_connector;
1848         int i;
1849
1850         if (!intel_crtc_has_type(intel_atomic_get_new_crtc_state(state, crtc),
1851                                  INTEL_OUTPUT_DP_MST))
1852                 return false;
1853
1854         crtc_connector = get_connector_in_state_for_crtc(state, crtc);
1855
1856         if (!crtc_connector)
1857                 /* None of the connectors in the topology needs modeset */
1858                 return false;
1859
1860         for_each_new_connector_in_state(&state->base, _connector, conn_state, i) {
1861                 const struct intel_connector *connector =
1862                         to_intel_connector(_connector);
1863                 const struct intel_crtc_state *new_crtc_state;
1864                 const struct intel_crtc_state *old_crtc_state;
1865                 struct intel_crtc *crtc_iter;
1866
1867                 if (connector->mst_port != crtc_connector->mst_port ||
1868                     !conn_state->crtc)
1869                         continue;
1870
1871                 crtc_iter = to_intel_crtc(conn_state->crtc);
1872
1873                 new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc_iter);
1874                 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc_iter);
1875
1876                 if (!intel_crtc_needs_modeset(new_crtc_state))
1877                         continue;
1878
1879                 if (old_crtc_state->dsc.compression_enable ==
1880                     new_crtc_state->dsc.compression_enable)
1881                         continue;
1882                 /*
1883                  * Toggling the decompression flag because of this stream in
1884                  * the first downstream branch device's UFP DPCD may reset the
1885                  * whole branch device. To avoid the reset while other streams
1886                  * are also active modeset the whole MST topology in this
1887                  * case.
1888                  */
1889                 if (connector->dp.dsc_decompression_aux ==
1890                     &connector->mst_port->aux)
1891                         return true;
1892         }
1893
1894         return false;
1895 }