2 * Copyright © 2012-2016 Intel Corporation
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25 #ifndef _INTEL_DPLL_MGR_H_
26 #define _INTEL_DPLL_MGR_H_
28 #include <linux/types.h>
30 #include "intel_display_power.h"
31 #include "intel_wakeref.h"
33 #define for_each_shared_dpll(__i915, __pll, __i) \
34 for ((__i) = 0; (__i) < (__i915)->display.dpll.num_shared_dpll && \
35 ((__pll) = &(__i915)->display.dpll.shared_dplls[(__i)]) ; (__i)++)
38 struct drm_i915_private
;
39 struct intel_atomic_state
;
41 struct intel_crtc_state
;
43 struct intel_shared_dpll
;
44 struct intel_shared_dpll_funcs
;
47 * enum intel_dpll_id - possible DPLL ids
49 * Enumeration of possible IDs for a DPLL. Real shared dpll ids must be >= 0.
53 * @DPLL_ID_PRIVATE: non-shared dpll in use
58 * @DPLL_ID_PCH_PLL_A: DPLL A in ILK, SNB and IVB
60 DPLL_ID_PCH_PLL_A
= 0,
62 * @DPLL_ID_PCH_PLL_B: DPLL B in ILK, SNB and IVB
64 DPLL_ID_PCH_PLL_B
= 1,
68 * @DPLL_ID_WRPLL1: HSW and BDW WRPLL1
72 * @DPLL_ID_WRPLL2: HSW and BDW WRPLL2
76 * @DPLL_ID_SPLL: HSW and BDW SPLL
80 * @DPLL_ID_LCPLL_810: HSW and BDW 0.81 GHz LCPLL
82 DPLL_ID_LCPLL_810
= 3,
84 * @DPLL_ID_LCPLL_1350: HSW and BDW 1.35 GHz LCPLL
86 DPLL_ID_LCPLL_1350
= 4,
88 * @DPLL_ID_LCPLL_2700: HSW and BDW 2.7 GHz LCPLL
90 DPLL_ID_LCPLL_2700
= 5,
94 * @DPLL_ID_SKL_DPLL0: SKL and later DPLL0
96 DPLL_ID_SKL_DPLL0
= 0,
98 * @DPLL_ID_SKL_DPLL1: SKL and later DPLL1
100 DPLL_ID_SKL_DPLL1
= 1,
102 * @DPLL_ID_SKL_DPLL2: SKL and later DPLL2
104 DPLL_ID_SKL_DPLL2
= 2,
106 * @DPLL_ID_SKL_DPLL3: SKL and later DPLL3
108 DPLL_ID_SKL_DPLL3
= 3,
112 * @DPLL_ID_ICL_DPLL0: ICL/TGL combo PHY DPLL0
114 DPLL_ID_ICL_DPLL0
= 0,
116 * @DPLL_ID_ICL_DPLL1: ICL/TGL combo PHY DPLL1
118 DPLL_ID_ICL_DPLL1
= 1,
120 * @DPLL_ID_EHL_DPLL4: EHL combo PHY DPLL4
122 DPLL_ID_EHL_DPLL4
= 2,
124 * @DPLL_ID_ICL_TBTPLL: ICL/TGL TBT PLL
126 DPLL_ID_ICL_TBTPLL
= 2,
128 * @DPLL_ID_ICL_MGPLL1: ICL MG PLL 1 port 1 (C),
129 * TGL TC PLL 1 port 1 (TC1)
131 DPLL_ID_ICL_MGPLL1
= 3,
133 * @DPLL_ID_ICL_MGPLL2: ICL MG PLL 1 port 2 (D)
134 * TGL TC PLL 1 port 2 (TC2)
136 DPLL_ID_ICL_MGPLL2
= 4,
138 * @DPLL_ID_ICL_MGPLL3: ICL MG PLL 1 port 3 (E)
139 * TGL TC PLL 1 port 3 (TC3)
141 DPLL_ID_ICL_MGPLL3
= 5,
143 * @DPLL_ID_ICL_MGPLL4: ICL MG PLL 1 port 4 (F)
144 * TGL TC PLL 1 port 4 (TC4)
146 DPLL_ID_ICL_MGPLL4
= 6,
148 * @DPLL_ID_TGL_MGPLL5: TGL TC PLL port 5 (TC5)
150 DPLL_ID_TGL_MGPLL5
= 7,
152 * @DPLL_ID_TGL_MGPLL6: TGL TC PLL port 6 (TC6)
154 DPLL_ID_TGL_MGPLL6
= 8,
157 * @DPLL_ID_DG1_DPLL0: DG1 combo PHY DPLL0
159 DPLL_ID_DG1_DPLL0
= 0,
161 * @DPLL_ID_DG1_DPLL1: DG1 combo PHY DPLL1
163 DPLL_ID_DG1_DPLL1
= 1,
165 * @DPLL_ID_DG1_DPLL2: DG1 combo PHY DPLL2
167 DPLL_ID_DG1_DPLL2
= 2,
169 * @DPLL_ID_DG1_DPLL3: DG1 combo PHY DPLL3
171 DPLL_ID_DG1_DPLL3
= 3,
174 #define I915_NUM_PLLS 9
176 enum icl_port_dpll_id
{
177 ICL_PORT_DPLL_DEFAULT
,
178 ICL_PORT_DPLL_MG_PHY
,
183 struct intel_dpll_hw_state
{
196 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
197 * lower part of ctrl1 and they get shifted into position when writing
198 * the register. This allows us to easily compare the state to share
202 /* HDMI only, 0 when used for DP */
212 u32 ebb0
, ebb4
, pll0
, pll1
, pll2
, pll3
, pll6
, pll8
, pll9
, pll10
, pcsdw12
;
215 * ICL uses the following, already defined:
216 * u32 cfgcr0, cfgcr1;
219 u32 mg_clktop2_coreclkctl1
;
220 u32 mg_clktop2_hsclkctl
;
224 u32 mg_pll_frac_lock
;
227 u32 mg_pll_tdc_coldst_bias
;
228 u32 mg_pll_bias_mask
;
229 u32 mg_pll_tdc_coldst_bias_mask
;
233 * struct intel_shared_dpll_state - hold the DPLL atomic state
235 * This structure holds an atomic state for the DPLL, that can represent
236 * either its current state (in struct &intel_shared_dpll) or a desired
237 * future state which would be applied by an atomic mode set (stored in
238 * a struct &intel_atomic_state).
240 * See also intel_reserve_shared_dplls() and intel_release_shared_dplls().
242 struct intel_shared_dpll_state
{
244 * @pipe_mask: mask of pipes using this DPLL, active or not
249 * @hw_state: hardware configuration for the DPLL stored in
250 * struct &intel_dpll_hw_state.
252 struct intel_dpll_hw_state hw_state
;
256 * struct dpll_info - display PLL platform specific info
260 * @name: DPLL name; used for logging
265 * @funcs: platform specific hooks
267 const struct intel_shared_dpll_funcs
*funcs
;
270 * @id: unique indentifier for this DPLL
272 enum intel_dpll_id id
;
275 * @power_domain: extra power domain required by the DPLL
277 enum intel_display_power_domain power_domain
;
282 * Inform the state checker that the DPLL is kept enabled even if
283 * not in use by any CRTC.
290 * Inform the state checker that the DPLL can be used as a fallback
291 * (for TC->TBT fallback).
293 bool is_alt_port_dpll
;
297 * struct intel_shared_dpll - display PLL with tracked state and users
299 struct intel_shared_dpll
{
303 * Store the state for the pll, including its hw state
304 * and CRTCs using it.
306 struct intel_shared_dpll_state state
;
309 * @index: index for atomic state
314 * @active_mask: mask of active pipes (i.e. DPMS on) using this DPLL
319 * @on: is the PLL actually active? Disabled during modeset
324 * @info: platform specific info
326 const struct dpll_info
*info
;
329 * @wakeref: In some platforms a device-level runtime pm reference may
330 * need to be grabbed to disable DC states while this DPLL is enabled
332 intel_wakeref_t wakeref
;
340 /* shared dpll functions */
341 struct intel_shared_dpll
*
342 intel_get_shared_dpll_by_id(struct drm_i915_private
*i915
,
343 enum intel_dpll_id id
);
344 void assert_shared_dpll(struct drm_i915_private
*i915
,
345 struct intel_shared_dpll
*pll
,
347 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
348 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
349 int intel_compute_shared_dplls(struct intel_atomic_state
*state
,
350 struct intel_crtc
*crtc
,
351 struct intel_encoder
*encoder
);
352 int intel_reserve_shared_dplls(struct intel_atomic_state
*state
,
353 struct intel_crtc
*crtc
,
354 struct intel_encoder
*encoder
);
355 void intel_release_shared_dplls(struct intel_atomic_state
*state
,
356 struct intel_crtc
*crtc
);
357 void intel_unreference_shared_dpll_crtc(const struct intel_crtc
*crtc
,
358 const struct intel_shared_dpll
*pll
,
359 struct intel_shared_dpll_state
*shared_dpll_state
);
360 void icl_set_active_port_dpll(struct intel_crtc_state
*crtc_state
,
361 enum icl_port_dpll_id port_dpll_id
);
362 void intel_update_active_dpll(struct intel_atomic_state
*state
,
363 struct intel_crtc
*crtc
,
364 struct intel_encoder
*encoder
);
365 int intel_dpll_get_freq(struct drm_i915_private
*i915
,
366 const struct intel_shared_dpll
*pll
,
367 const struct intel_dpll_hw_state
*pll_state
);
368 bool intel_dpll_get_hw_state(struct drm_i915_private
*i915
,
369 struct intel_shared_dpll
*pll
,
370 struct intel_dpll_hw_state
*hw_state
);
371 void intel_enable_shared_dpll(const struct intel_crtc_state
*crtc_state
);
372 void intel_disable_shared_dpll(const struct intel_crtc_state
*crtc_state
);
373 void intel_shared_dpll_swap_state(struct intel_atomic_state
*state
);
374 void intel_shared_dpll_init(struct drm_i915_private
*i915
);
375 void intel_dpll_update_ref_clks(struct drm_i915_private
*i915
);
376 void intel_dpll_readout_hw_state(struct drm_i915_private
*i915
);
377 void intel_dpll_sanitize_state(struct drm_i915_private
*i915
);
379 void intel_dpll_dump_hw_state(struct drm_i915_private
*i915
,
380 const struct intel_dpll_hw_state
*hw_state
);
381 bool intel_dpll_compare_hw_state(struct drm_i915_private
*i915
,
382 const struct intel_dpll_hw_state
*a
,
383 const struct intel_dpll_hw_state
*b
);
384 enum intel_dpll_id
icl_tc_port_to_pll_id(enum tc_port tc_port
);
385 bool intel_dpll_is_combophy(enum intel_dpll_id id
);
387 void intel_shared_dpll_state_verify(struct intel_atomic_state
*state
,
388 struct intel_crtc
*crtc
);
389 void intel_shared_dpll_verify_disabled(struct intel_atomic_state
*state
);
391 #endif /* _INTEL_DPLL_MGR_H_ */