1 // SPDX-License-Identifier: MIT
3 * Copyright © 2019 Intel Corporation
7 #include "gem/i915_gem_internal.h"
8 #include "gem/i915_gem_lmem.h"
13 #include "intel_crtc.h"
15 #include "intel_display_types.h"
16 #include "intel_dsb.h"
17 #include "intel_dsb_regs.h"
18 #include "intel_vblank.h"
19 #include "intel_vrr.h"
20 #include "skl_watermark.h"
37 struct intel_crtc
*crtc
;
40 * maximum number of dwords the buffer will hold.
45 * free_pos will point the first free dword and
46 * help in calculating tail of command buffer.
48 unsigned int free_pos
;
51 * ins_start_offset will help to store start dword of the dsb
52 * instuction and help in identifying the batch of auto-increment
55 unsigned int ins_start_offset
;
63 * A DSB (Display State Buffer) is a queue of MMIO instructions in the memory
64 * which can be offloaded to DSB HW in Display Controller. DSB HW is a DMA
65 * engine that can be programmed to download the DSB from memory.
66 * It allows driver to batch submit display HW programming. This helps to
67 * reduce loading time and CPU activity, thereby making the context switch
68 * faster. DSB Support added from Gen12 Intel graphics based platform.
70 * DSB's can access only the pipe, plane, and transcoder Data Island Packet
73 * DSB HW can support only register writes (both indexed and direct MMIO
74 * writes). There are no registers reads possible with DSB HW engine.
78 #define DSB_OPCODE_SHIFT 24
79 #define DSB_OPCODE_NOOP 0x0
80 #define DSB_OPCODE_MMIO_WRITE 0x1
81 #define DSB_BYTE_EN 0xf
82 #define DSB_BYTE_EN_SHIFT 20
83 #define DSB_REG_VALUE_MASK 0xfffff
84 #define DSB_OPCODE_WAIT_USEC 0x2
85 #define DSB_OPCODE_WAIT_SCANLINE 0x3
86 #define DSB_OPCODE_WAIT_VBLANKS 0x4
87 #define DSB_OPCODE_WAIT_DSL_IN 0x5
88 #define DSB_OPCODE_WAIT_DSL_OUT 0x6
89 #define DSB_SCANLINE_UPPER_SHIFT 20
90 #define DSB_SCANLINE_LOWER_SHIFT 0
91 #define DSB_OPCODE_INTERRUPT 0x7
92 #define DSB_OPCODE_INDEXED_WRITE 0x9
93 /* see DSB_REG_VALUE_MASK */
94 #define DSB_OPCODE_POLL 0xA
95 /* see DSB_REG_VALUE_MASK */
97 static bool assert_dsb_has_room(struct intel_dsb
*dsb
)
99 struct intel_crtc
*crtc
= dsb
->crtc
;
100 struct drm_i915_private
*i915
= to_i915(crtc
->base
.dev
);
102 /* each instruction is 2 dwords */
103 return !drm_WARN(&i915
->drm
, dsb
->free_pos
> dsb
->size
- 2,
104 "[CRTC:%d:%s] DSB %d buffer overflow\n",
105 crtc
->base
.base
.id
, crtc
->base
.name
, dsb
->id
);
108 static void intel_dsb_dump(struct intel_dsb
*dsb
)
110 struct intel_crtc
*crtc
= dsb
->crtc
;
111 struct drm_i915_private
*i915
= to_i915(crtc
->base
.dev
);
112 const u32
*buf
= dsb
->cmd_buf
;
115 drm_dbg_kms(&i915
->drm
, "[CRTC:%d:%s] DSB %d commands {\n",
116 crtc
->base
.base
.id
, crtc
->base
.name
, dsb
->id
);
117 for (i
= 0; i
< ALIGN(dsb
->free_pos
, 64 / 4); i
+= 4)
118 drm_dbg_kms(&i915
->drm
,
119 " 0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
120 i
* 4, buf
[i
], buf
[i
+1], buf
[i
+2], buf
[i
+3]);
121 drm_dbg_kms(&i915
->drm
, "}\n");
124 static bool is_dsb_busy(struct drm_i915_private
*i915
, enum pipe pipe
,
127 return intel_de_read_fw(i915
, DSB_CTRL(pipe
, id
)) & DSB_STATUS_BUSY
;
130 static void intel_dsb_emit(struct intel_dsb
*dsb
, u32 ldw
, u32 udw
)
132 u32
*buf
= dsb
->cmd_buf
;
134 if (!assert_dsb_has_room(dsb
))
137 /* Every instruction should be 8 byte aligned. */
138 dsb
->free_pos
= ALIGN(dsb
->free_pos
, 2);
140 dsb
->ins_start_offset
= dsb
->free_pos
;
142 buf
[dsb
->free_pos
++] = ldw
;
143 buf
[dsb
->free_pos
++] = udw
;
146 static bool intel_dsb_prev_ins_is_write(struct intel_dsb
*dsb
,
147 u32 opcode
, i915_reg_t reg
)
149 const u32
*buf
= dsb
->cmd_buf
;
150 u32 prev_opcode
, prev_reg
;
153 * Nothing emitted yet? Must check before looking
154 * at the actual data since i915_gem_object_create_internal()
155 * does *not* give you zeroed memory!
157 if (dsb
->free_pos
== 0)
160 prev_opcode
= buf
[dsb
->ins_start_offset
+ 1] & ~DSB_REG_VALUE_MASK
;
161 prev_reg
= buf
[dsb
->ins_start_offset
+ 1] & DSB_REG_VALUE_MASK
;
163 return prev_opcode
== opcode
&& prev_reg
== i915_mmio_reg_offset(reg
);
166 static bool intel_dsb_prev_ins_is_mmio_write(struct intel_dsb
*dsb
, i915_reg_t reg
)
168 /* only full byte-enables can be converted to indexed writes */
169 return intel_dsb_prev_ins_is_write(dsb
,
170 DSB_OPCODE_MMIO_WRITE
<< DSB_OPCODE_SHIFT
|
171 DSB_BYTE_EN
<< DSB_BYTE_EN_SHIFT
,
175 static bool intel_dsb_prev_ins_is_indexed_write(struct intel_dsb
*dsb
, i915_reg_t reg
)
177 return intel_dsb_prev_ins_is_write(dsb
,
178 DSB_OPCODE_INDEXED_WRITE
<< DSB_OPCODE_SHIFT
,
183 * intel_dsb_reg_write() - Emit register wriite to the DSB context
185 * @reg: register address.
188 * This function is used for writing register-value pair in command
191 void intel_dsb_reg_write(struct intel_dsb
*dsb
,
192 i915_reg_t reg
, u32 val
)
195 * For example the buffer will look like below for 3 dwords for auto
196 * increment register:
197 * +--------------------------------------------------------+
198 * | size = 3 | offset &| value1 | value2 | value3 | zero |
199 * | | opcode | | | | |
200 * +--------------------------------------------------------+
205 * As every instruction is 8 byte aligned the index of dsb instruction
206 * will start always from even number while dealing with u32 array. If
207 * we are writing odd no of dwords, Zeros will be added in the end for
210 if (!intel_dsb_prev_ins_is_mmio_write(dsb
, reg
) &&
211 !intel_dsb_prev_ins_is_indexed_write(dsb
, reg
)) {
212 intel_dsb_emit(dsb
, val
,
213 (DSB_OPCODE_MMIO_WRITE
<< DSB_OPCODE_SHIFT
) |
214 (DSB_BYTE_EN
<< DSB_BYTE_EN_SHIFT
) |
215 i915_mmio_reg_offset(reg
));
217 u32
*buf
= dsb
->cmd_buf
;
219 if (!assert_dsb_has_room(dsb
))
222 /* convert to indexed write? */
223 if (intel_dsb_prev_ins_is_mmio_write(dsb
, reg
)) {
224 u32 prev_val
= buf
[dsb
->ins_start_offset
+ 0];
226 buf
[dsb
->ins_start_offset
+ 0] = 1; /* count */
227 buf
[dsb
->ins_start_offset
+ 1] =
228 (DSB_OPCODE_INDEXED_WRITE
<< DSB_OPCODE_SHIFT
) |
229 i915_mmio_reg_offset(reg
);
230 buf
[dsb
->ins_start_offset
+ 2] = prev_val
;
235 buf
[dsb
->free_pos
++] = val
;
236 /* Update the count */
237 buf
[dsb
->ins_start_offset
]++;
239 /* if number of data words is odd, then the last dword should be 0.*/
240 if (dsb
->free_pos
& 0x1)
241 buf
[dsb
->free_pos
] = 0;
245 static u32
intel_dsb_mask_to_byte_en(u32 mask
)
247 return (!!(mask
& 0xff000000) << 3 |
248 !!(mask
& 0x00ff0000) << 2 |
249 !!(mask
& 0x0000ff00) << 1 |
250 !!(mask
& 0x000000ff) << 0);
253 /* Note: mask implemented via byte enables! */
254 void intel_dsb_reg_write_masked(struct intel_dsb
*dsb
,
255 i915_reg_t reg
, u32 mask
, u32 val
)
257 intel_dsb_emit(dsb
, val
,
258 (DSB_OPCODE_MMIO_WRITE
<< DSB_OPCODE_SHIFT
) |
259 (intel_dsb_mask_to_byte_en(mask
) << DSB_BYTE_EN_SHIFT
) |
260 i915_mmio_reg_offset(reg
));
263 void intel_dsb_noop(struct intel_dsb
*dsb
, int count
)
267 for (i
= 0; i
< count
; i
++)
268 intel_dsb_emit(dsb
, 0,
269 DSB_OPCODE_NOOP
<< DSB_OPCODE_SHIFT
);
272 void intel_dsb_nonpost_start(struct intel_dsb
*dsb
)
274 struct intel_crtc
*crtc
= dsb
->crtc
;
275 enum pipe pipe
= crtc
->pipe
;
277 intel_dsb_reg_write_masked(dsb
, DSB_CTRL(pipe
, dsb
->id
),
278 DSB_NON_POSTED
, DSB_NON_POSTED
);
279 intel_dsb_noop(dsb
, 4);
282 void intel_dsb_nonpost_end(struct intel_dsb
*dsb
)
284 struct intel_crtc
*crtc
= dsb
->crtc
;
285 enum pipe pipe
= crtc
->pipe
;
287 intel_dsb_reg_write_masked(dsb
, DSB_CTRL(pipe
, dsb
->id
),
289 intel_dsb_noop(dsb
, 4);
292 static void intel_dsb_align_tail(struct intel_dsb
*dsb
)
294 u32 aligned_tail
, tail
;
296 tail
= dsb
->free_pos
* 4;
297 aligned_tail
= ALIGN(tail
, CACHELINE_BYTES
);
299 if (aligned_tail
> tail
)
300 memset(&dsb
->cmd_buf
[dsb
->free_pos
], 0,
301 aligned_tail
- tail
);
303 dsb
->free_pos
= aligned_tail
/ 4;
306 void intel_dsb_finish(struct intel_dsb
*dsb
)
308 struct intel_crtc
*crtc
= dsb
->crtc
;
311 * DSB_FORCE_DEWAKE remains active even after DSB is
312 * disabled, so make sure to clear it (if set during
313 * intel_dsb_commit()).
315 intel_dsb_reg_write_masked(dsb
, DSB_PMCTRL_2(crtc
->pipe
, dsb
->id
),
316 DSB_FORCE_DEWAKE
, 0);
318 intel_dsb_align_tail(dsb
);
320 i915_gem_object_flush_map(dsb
->vma
->obj
);
323 static int intel_dsb_dewake_scanline(const struct intel_crtc_state
*crtc_state
)
325 struct drm_i915_private
*i915
= to_i915(crtc_state
->uapi
.crtc
->dev
);
326 const struct drm_display_mode
*adjusted_mode
= &crtc_state
->hw
.adjusted_mode
;
327 unsigned int latency
= skl_watermark_max_latency(i915
);
330 if (crtc_state
->vrr
.enable
) {
331 vblank_start
= intel_vrr_vmin_vblank_start(crtc_state
);
333 vblank_start
= adjusted_mode
->crtc_vblank_start
;
335 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
336 vblank_start
= DIV_ROUND_UP(vblank_start
, 2);
339 return max(0, vblank_start
- intel_usecs_to_scanlines(adjusted_mode
, latency
));
342 static void _intel_dsb_commit(struct intel_dsb
*dsb
, u32 ctrl
,
345 struct intel_crtc
*crtc
= dsb
->crtc
;
346 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
347 enum pipe pipe
= crtc
->pipe
;
350 tail
= dsb
->free_pos
* 4;
351 if (drm_WARN_ON(&dev_priv
->drm
, !IS_ALIGNED(tail
, CACHELINE_BYTES
)))
354 if (is_dsb_busy(dev_priv
, pipe
, dsb
->id
)) {
355 drm_err(&dev_priv
->drm
, "[CRTC:%d:%s] DSB %d is busy\n",
356 crtc
->base
.base
.id
, crtc
->base
.name
, dsb
->id
);
360 intel_de_write_fw(dev_priv
, DSB_CTRL(pipe
, dsb
->id
),
363 intel_de_write_fw(dev_priv
, DSB_HEAD(pipe
, dsb
->id
),
364 i915_ggtt_offset(dsb
->vma
));
366 if (dewake_scanline
>= 0) {
367 int diff
, hw_dewake_scanline
;
369 hw_dewake_scanline
= intel_crtc_scanline_to_hw(crtc
, dewake_scanline
);
371 intel_de_write_fw(dev_priv
, DSB_PMCTRL(pipe
, dsb
->id
),
373 DSB_SCANLINE_FOR_DEWAKE(hw_dewake_scanline
));
376 * Force DEwake immediately if we're already past
377 * or close to racing past the target scanline.
379 diff
= dewake_scanline
- intel_get_crtc_scanline(crtc
);
380 intel_de_write_fw(dev_priv
, DSB_PMCTRL_2(pipe
, dsb
->id
),
381 (diff
>= 0 && diff
< 5 ? DSB_FORCE_DEWAKE
: 0) |
382 DSB_BLOCK_DEWAKE_EXTENSION
);
385 intel_de_write_fw(dev_priv
, DSB_TAIL(pipe
, dsb
->id
),
386 i915_ggtt_offset(dsb
->vma
) + tail
);
390 * intel_dsb_commit() - Trigger workload execution of DSB.
392 * @wait_for_vblank: wait for vblank before executing
394 * This function is used to do actual write to hardware using DSB.
396 void intel_dsb_commit(struct intel_dsb
*dsb
,
397 bool wait_for_vblank
)
399 _intel_dsb_commit(dsb
,
400 wait_for_vblank
? DSB_WAIT_FOR_VBLANK
: 0,
401 wait_for_vblank
? dsb
->dewake_scanline
: -1);
404 void intel_dsb_wait(struct intel_dsb
*dsb
)
406 struct intel_crtc
*crtc
= dsb
->crtc
;
407 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
408 enum pipe pipe
= crtc
->pipe
;
410 if (wait_for(!is_dsb_busy(dev_priv
, pipe
, dsb
->id
), 1)) {
411 u32 offset
= i915_ggtt_offset(dsb
->vma
);
413 intel_de_write_fw(dev_priv
, DSB_CTRL(pipe
, dsb
->id
),
414 DSB_ENABLE
| DSB_HALT
);
416 drm_err(&dev_priv
->drm
,
417 "[CRTC:%d:%s] DSB %d timed out waiting for idle (current head=0x%x, head=0x%x, tail=0x%x)\n",
418 crtc
->base
.base
.id
, crtc
->base
.name
, dsb
->id
,
419 intel_de_read_fw(dev_priv
, DSB_CURRENT_HEAD(pipe
, dsb
->id
)) - offset
,
420 intel_de_read_fw(dev_priv
, DSB_HEAD(pipe
, dsb
->id
)) - offset
,
421 intel_de_read_fw(dev_priv
, DSB_TAIL(pipe
, dsb
->id
)) - offset
);
426 /* Attempt to reset it */
428 dsb
->ins_start_offset
= 0;
429 intel_de_write_fw(dev_priv
, DSB_CTRL(pipe
, dsb
->id
), 0);
433 * intel_dsb_prepare() - Allocate, pin and map the DSB command buffer.
434 * @crtc_state: the CRTC state
435 * @max_cmds: number of commands we need to fit into command buffer
437 * This function prepare the command buffer which is used to store dsb
438 * instructions with data.
441 * DSB context, NULL on failure
443 struct intel_dsb
*intel_dsb_prepare(const struct intel_crtc_state
*crtc_state
,
444 unsigned int max_cmds
)
446 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
447 struct drm_i915_private
*i915
= to_i915(crtc
->base
.dev
);
448 struct drm_i915_gem_object
*obj
;
449 intel_wakeref_t wakeref
;
450 struct intel_dsb
*dsb
;
451 struct i915_vma
*vma
;
458 dsb
= kzalloc(sizeof(*dsb
), GFP_KERNEL
);
462 wakeref
= intel_runtime_pm_get(&i915
->runtime_pm
);
464 /* ~1 qword per instruction, full cachelines */
465 size
= ALIGN(max_cmds
* 8, CACHELINE_BYTES
);
467 if (HAS_LMEM(i915
)) {
468 obj
= i915_gem_object_create_lmem(i915
, PAGE_ALIGN(size
),
469 I915_BO_ALLOC_CONTIGUOUS
);
473 obj
= i915_gem_object_create_internal(i915
, PAGE_ALIGN(size
));
477 i915_gem_object_set_cache_coherency(obj
, I915_CACHE_NONE
);
480 vma
= i915_gem_object_ggtt_pin(obj
, NULL
, 0, 0, 0);
482 i915_gem_object_put(obj
);
486 buf
= i915_gem_object_pin_map_unlocked(vma
->obj
, I915_MAP_WC
);
488 i915_vma_unpin_and_release(&vma
, I915_VMA_RELEASE_MAP
);
492 intel_runtime_pm_put(&i915
->runtime_pm
, wakeref
);
498 dsb
->size
= size
/ 4; /* in dwords */
500 dsb
->ins_start_offset
= 0;
501 dsb
->dewake_scanline
= intel_dsb_dewake_scanline(crtc_state
);
506 intel_runtime_pm_put(&i915
->runtime_pm
, wakeref
);
509 drm_info_once(&i915
->drm
,
510 "[CRTC:%d:%s] DSB %d queue setup failed, will fallback to MMIO for display HW programming\n",
511 crtc
->base
.base
.id
, crtc
->base
.name
, DSB1
);
517 * intel_dsb_cleanup() - To cleanup DSB context.
520 * This function cleanup the DSB context by unpinning and releasing
521 * the VMA object associated with it.
523 void intel_dsb_cleanup(struct intel_dsb
*dsb
)
525 i915_vma_unpin_and_release(&dsb
->vma
, I915_VMA_RELEASE_MAP
);