2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2009 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Eric Anholt <eric@anholt.net>
26 * Jesse Barnes <jesse.barnes@intel.com>
29 #include <linux/delay.h>
30 #include <linux/hdmi.h>
31 #include <linux/i2c.h>
32 #include <linux/slab.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_edid.h>
37 #include <drm/drm_hdcp.h>
38 #include <drm/drm_scdc_helper.h>
39 #include <drm/intel_lpe_audio.h>
41 #include "i915_debugfs.h"
43 #include "intel_atomic.h"
44 #include "intel_audio.h"
45 #include "intel_connector.h"
46 #include "intel_ddi.h"
47 #include "intel_display_debugfs.h"
48 #include "intel_display_types.h"
50 #include "intel_dpio_phy.h"
51 #include "intel_fifo_underrun.h"
52 #include "intel_gmbus.h"
53 #include "intel_hdcp.h"
54 #include "intel_hdmi.h"
55 #include "intel_hotplug.h"
56 #include "intel_lspcon.h"
57 #include "intel_panel.h"
58 #include "intel_sdvo.h"
59 #include "intel_sideband.h"
61 static struct drm_device
*intel_hdmi_to_dev(struct intel_hdmi
*intel_hdmi
)
63 return hdmi_to_dig_port(intel_hdmi
)->base
.base
.dev
;
67 assert_hdmi_port_disabled(struct intel_hdmi
*intel_hdmi
)
69 struct drm_device
*dev
= intel_hdmi_to_dev(intel_hdmi
);
70 struct drm_i915_private
*dev_priv
= to_i915(dev
);
73 enabled_bits
= HAS_DDI(dev_priv
) ? DDI_BUF_CTL_ENABLE
: SDVO_ENABLE
;
76 intel_de_read(dev_priv
, intel_hdmi
->hdmi_reg
) & enabled_bits
,
77 "HDMI port enabled, expecting disabled\n");
81 assert_hdmi_transcoder_func_disabled(struct drm_i915_private
*dev_priv
,
82 enum transcoder cpu_transcoder
)
84 drm_WARN(&dev_priv
->drm
,
85 intel_de_read(dev_priv
, TRANS_DDI_FUNC_CTL(cpu_transcoder
)) &
86 TRANS_DDI_FUNC_ENABLE
,
87 "HDMI transcoder function enabled, expecting disabled\n");
90 struct intel_hdmi
*enc_to_intel_hdmi(struct intel_encoder
*encoder
)
92 struct intel_digital_port
*intel_dig_port
=
93 container_of(&encoder
->base
, struct intel_digital_port
,
95 return &intel_dig_port
->hdmi
;
98 static struct intel_hdmi
*intel_attached_hdmi(struct intel_connector
*connector
)
100 return enc_to_intel_hdmi(intel_attached_encoder(connector
));
103 static u32
g4x_infoframe_index(unsigned int type
)
106 case HDMI_PACKET_TYPE_GAMUT_METADATA
:
107 return VIDEO_DIP_SELECT_GAMUT
;
108 case HDMI_INFOFRAME_TYPE_AVI
:
109 return VIDEO_DIP_SELECT_AVI
;
110 case HDMI_INFOFRAME_TYPE_SPD
:
111 return VIDEO_DIP_SELECT_SPD
;
112 case HDMI_INFOFRAME_TYPE_VENDOR
:
113 return VIDEO_DIP_SELECT_VENDOR
;
120 static u32
g4x_infoframe_enable(unsigned int type
)
123 case HDMI_PACKET_TYPE_GENERAL_CONTROL
:
124 return VIDEO_DIP_ENABLE_GCP
;
125 case HDMI_PACKET_TYPE_GAMUT_METADATA
:
126 return VIDEO_DIP_ENABLE_GAMUT
;
129 case HDMI_INFOFRAME_TYPE_AVI
:
130 return VIDEO_DIP_ENABLE_AVI
;
131 case HDMI_INFOFRAME_TYPE_SPD
:
132 return VIDEO_DIP_ENABLE_SPD
;
133 case HDMI_INFOFRAME_TYPE_VENDOR
:
134 return VIDEO_DIP_ENABLE_VENDOR
;
135 case HDMI_INFOFRAME_TYPE_DRM
:
143 static u32
hsw_infoframe_enable(unsigned int type
)
146 case HDMI_PACKET_TYPE_GENERAL_CONTROL
:
147 return VIDEO_DIP_ENABLE_GCP_HSW
;
148 case HDMI_PACKET_TYPE_GAMUT_METADATA
:
149 return VIDEO_DIP_ENABLE_GMP_HSW
;
151 return VIDEO_DIP_ENABLE_VSC_HSW
;
153 return VDIP_ENABLE_PPS
;
154 case HDMI_INFOFRAME_TYPE_AVI
:
155 return VIDEO_DIP_ENABLE_AVI_HSW
;
156 case HDMI_INFOFRAME_TYPE_SPD
:
157 return VIDEO_DIP_ENABLE_SPD_HSW
;
158 case HDMI_INFOFRAME_TYPE_VENDOR
:
159 return VIDEO_DIP_ENABLE_VS_HSW
;
160 case HDMI_INFOFRAME_TYPE_DRM
:
161 return VIDEO_DIP_ENABLE_DRM_GLK
;
169 hsw_dip_data_reg(struct drm_i915_private
*dev_priv
,
170 enum transcoder cpu_transcoder
,
175 case HDMI_PACKET_TYPE_GAMUT_METADATA
:
176 return HSW_TVIDEO_DIP_GMP_DATA(cpu_transcoder
, i
);
178 return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder
, i
);
180 return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder
, i
);
181 case HDMI_INFOFRAME_TYPE_AVI
:
182 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder
, i
);
183 case HDMI_INFOFRAME_TYPE_SPD
:
184 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder
, i
);
185 case HDMI_INFOFRAME_TYPE_VENDOR
:
186 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder
, i
);
187 case HDMI_INFOFRAME_TYPE_DRM
:
188 return GLK_TVIDEO_DIP_DRM_DATA(cpu_transcoder
, i
);
191 return INVALID_MMIO_REG
;
195 static int hsw_dip_data_size(struct drm_i915_private
*dev_priv
,
200 return VIDEO_DIP_VSC_DATA_SIZE
;
202 return VIDEO_DIP_PPS_DATA_SIZE
;
203 case HDMI_PACKET_TYPE_GAMUT_METADATA
:
204 if (INTEL_GEN(dev_priv
) >= 11)
205 return VIDEO_DIP_GMP_DATA_SIZE
;
207 return VIDEO_DIP_DATA_SIZE
;
209 return VIDEO_DIP_DATA_SIZE
;
213 static void g4x_write_infoframe(struct intel_encoder
*encoder
,
214 const struct intel_crtc_state
*crtc_state
,
216 const void *frame
, ssize_t len
)
218 const u32
*data
= frame
;
219 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
220 u32 val
= intel_de_read(dev_priv
, VIDEO_DIP_CTL
);
223 drm_WARN(&dev_priv
->drm
, !(val
& VIDEO_DIP_ENABLE
),
224 "Writing DIP with CTL reg disabled\n");
226 val
&= ~(VIDEO_DIP_SELECT_MASK
| 0xf); /* clear DIP data offset */
227 val
|= g4x_infoframe_index(type
);
229 val
&= ~g4x_infoframe_enable(type
);
231 intel_de_write(dev_priv
, VIDEO_DIP_CTL
, val
);
233 for (i
= 0; i
< len
; i
+= 4) {
234 intel_de_write(dev_priv
, VIDEO_DIP_DATA
, *data
);
237 /* Write every possible data byte to force correct ECC calculation. */
238 for (; i
< VIDEO_DIP_DATA_SIZE
; i
+= 4)
239 intel_de_write(dev_priv
, VIDEO_DIP_DATA
, 0);
241 val
|= g4x_infoframe_enable(type
);
242 val
&= ~VIDEO_DIP_FREQ_MASK
;
243 val
|= VIDEO_DIP_FREQ_VSYNC
;
245 intel_de_write(dev_priv
, VIDEO_DIP_CTL
, val
);
246 intel_de_posting_read(dev_priv
, VIDEO_DIP_CTL
);
249 static void g4x_read_infoframe(struct intel_encoder
*encoder
,
250 const struct intel_crtc_state
*crtc_state
,
252 void *frame
, ssize_t len
)
254 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
255 u32 val
, *data
= frame
;
258 val
= intel_de_read(dev_priv
, VIDEO_DIP_CTL
);
260 val
&= ~(VIDEO_DIP_SELECT_MASK
| 0xf); /* clear DIP data offset */
261 val
|= g4x_infoframe_index(type
);
263 intel_de_write(dev_priv
, VIDEO_DIP_CTL
, val
);
265 for (i
= 0; i
< len
; i
+= 4)
266 *data
++ = intel_de_read(dev_priv
, VIDEO_DIP_DATA
);
269 static u32
g4x_infoframes_enabled(struct intel_encoder
*encoder
,
270 const struct intel_crtc_state
*pipe_config
)
272 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
273 u32 val
= intel_de_read(dev_priv
, VIDEO_DIP_CTL
);
275 if ((val
& VIDEO_DIP_ENABLE
) == 0)
278 if ((val
& VIDEO_DIP_PORT_MASK
) != VIDEO_DIP_PORT(encoder
->port
))
281 return val
& (VIDEO_DIP_ENABLE_AVI
|
282 VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_SPD
);
285 static void ibx_write_infoframe(struct intel_encoder
*encoder
,
286 const struct intel_crtc_state
*crtc_state
,
288 const void *frame
, ssize_t len
)
290 const u32
*data
= frame
;
291 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
292 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
293 i915_reg_t reg
= TVIDEO_DIP_CTL(intel_crtc
->pipe
);
294 u32 val
= intel_de_read(dev_priv
, reg
);
297 drm_WARN(&dev_priv
->drm
, !(val
& VIDEO_DIP_ENABLE
),
298 "Writing DIP with CTL reg disabled\n");
300 val
&= ~(VIDEO_DIP_SELECT_MASK
| 0xf); /* clear DIP data offset */
301 val
|= g4x_infoframe_index(type
);
303 val
&= ~g4x_infoframe_enable(type
);
305 intel_de_write(dev_priv
, reg
, val
);
307 for (i
= 0; i
< len
; i
+= 4) {
308 intel_de_write(dev_priv
, TVIDEO_DIP_DATA(intel_crtc
->pipe
),
312 /* Write every possible data byte to force correct ECC calculation. */
313 for (; i
< VIDEO_DIP_DATA_SIZE
; i
+= 4)
314 intel_de_write(dev_priv
, TVIDEO_DIP_DATA(intel_crtc
->pipe
), 0);
316 val
|= g4x_infoframe_enable(type
);
317 val
&= ~VIDEO_DIP_FREQ_MASK
;
318 val
|= VIDEO_DIP_FREQ_VSYNC
;
320 intel_de_write(dev_priv
, reg
, val
);
321 intel_de_posting_read(dev_priv
, reg
);
324 static void ibx_read_infoframe(struct intel_encoder
*encoder
,
325 const struct intel_crtc_state
*crtc_state
,
327 void *frame
, ssize_t len
)
329 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
330 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
331 u32 val
, *data
= frame
;
334 val
= intel_de_read(dev_priv
, TVIDEO_DIP_CTL(crtc
->pipe
));
336 val
&= ~(VIDEO_DIP_SELECT_MASK
| 0xf); /* clear DIP data offset */
337 val
|= g4x_infoframe_index(type
);
339 intel_de_write(dev_priv
, TVIDEO_DIP_CTL(crtc
->pipe
), val
);
341 for (i
= 0; i
< len
; i
+= 4)
342 *data
++ = intel_de_read(dev_priv
, TVIDEO_DIP_DATA(crtc
->pipe
));
345 static u32
ibx_infoframes_enabled(struct intel_encoder
*encoder
,
346 const struct intel_crtc_state
*pipe_config
)
348 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
349 enum pipe pipe
= to_intel_crtc(pipe_config
->uapi
.crtc
)->pipe
;
350 i915_reg_t reg
= TVIDEO_DIP_CTL(pipe
);
351 u32 val
= intel_de_read(dev_priv
, reg
);
353 if ((val
& VIDEO_DIP_ENABLE
) == 0)
356 if ((val
& VIDEO_DIP_PORT_MASK
) != VIDEO_DIP_PORT(encoder
->port
))
359 return val
& (VIDEO_DIP_ENABLE_AVI
|
360 VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_GAMUT
|
361 VIDEO_DIP_ENABLE_SPD
| VIDEO_DIP_ENABLE_GCP
);
364 static void cpt_write_infoframe(struct intel_encoder
*encoder
,
365 const struct intel_crtc_state
*crtc_state
,
367 const void *frame
, ssize_t len
)
369 const u32
*data
= frame
;
370 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
371 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
372 i915_reg_t reg
= TVIDEO_DIP_CTL(intel_crtc
->pipe
);
373 u32 val
= intel_de_read(dev_priv
, reg
);
376 drm_WARN(&dev_priv
->drm
, !(val
& VIDEO_DIP_ENABLE
),
377 "Writing DIP with CTL reg disabled\n");
379 val
&= ~(VIDEO_DIP_SELECT_MASK
| 0xf); /* clear DIP data offset */
380 val
|= g4x_infoframe_index(type
);
382 /* The DIP control register spec says that we need to update the AVI
383 * infoframe without clearing its enable bit */
384 if (type
!= HDMI_INFOFRAME_TYPE_AVI
)
385 val
&= ~g4x_infoframe_enable(type
);
387 intel_de_write(dev_priv
, reg
, val
);
389 for (i
= 0; i
< len
; i
+= 4) {
390 intel_de_write(dev_priv
, TVIDEO_DIP_DATA(intel_crtc
->pipe
),
394 /* Write every possible data byte to force correct ECC calculation. */
395 for (; i
< VIDEO_DIP_DATA_SIZE
; i
+= 4)
396 intel_de_write(dev_priv
, TVIDEO_DIP_DATA(intel_crtc
->pipe
), 0);
398 val
|= g4x_infoframe_enable(type
);
399 val
&= ~VIDEO_DIP_FREQ_MASK
;
400 val
|= VIDEO_DIP_FREQ_VSYNC
;
402 intel_de_write(dev_priv
, reg
, val
);
403 intel_de_posting_read(dev_priv
, reg
);
406 static void cpt_read_infoframe(struct intel_encoder
*encoder
,
407 const struct intel_crtc_state
*crtc_state
,
409 void *frame
, ssize_t len
)
411 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
412 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
413 u32 val
, *data
= frame
;
416 val
= intel_de_read(dev_priv
, TVIDEO_DIP_CTL(crtc
->pipe
));
418 val
&= ~(VIDEO_DIP_SELECT_MASK
| 0xf); /* clear DIP data offset */
419 val
|= g4x_infoframe_index(type
);
421 intel_de_write(dev_priv
, TVIDEO_DIP_CTL(crtc
->pipe
), val
);
423 for (i
= 0; i
< len
; i
+= 4)
424 *data
++ = intel_de_read(dev_priv
, TVIDEO_DIP_DATA(crtc
->pipe
));
427 static u32
cpt_infoframes_enabled(struct intel_encoder
*encoder
,
428 const struct intel_crtc_state
*pipe_config
)
430 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
431 enum pipe pipe
= to_intel_crtc(pipe_config
->uapi
.crtc
)->pipe
;
432 u32 val
= intel_de_read(dev_priv
, TVIDEO_DIP_CTL(pipe
));
434 if ((val
& VIDEO_DIP_ENABLE
) == 0)
437 return val
& (VIDEO_DIP_ENABLE_AVI
|
438 VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_GAMUT
|
439 VIDEO_DIP_ENABLE_SPD
| VIDEO_DIP_ENABLE_GCP
);
442 static void vlv_write_infoframe(struct intel_encoder
*encoder
,
443 const struct intel_crtc_state
*crtc_state
,
445 const void *frame
, ssize_t len
)
447 const u32
*data
= frame
;
448 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
449 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
450 i915_reg_t reg
= VLV_TVIDEO_DIP_CTL(intel_crtc
->pipe
);
451 u32 val
= intel_de_read(dev_priv
, reg
);
454 drm_WARN(&dev_priv
->drm
, !(val
& VIDEO_DIP_ENABLE
),
455 "Writing DIP with CTL reg disabled\n");
457 val
&= ~(VIDEO_DIP_SELECT_MASK
| 0xf); /* clear DIP data offset */
458 val
|= g4x_infoframe_index(type
);
460 val
&= ~g4x_infoframe_enable(type
);
462 intel_de_write(dev_priv
, reg
, val
);
464 for (i
= 0; i
< len
; i
+= 4) {
465 intel_de_write(dev_priv
,
466 VLV_TVIDEO_DIP_DATA(intel_crtc
->pipe
), *data
);
469 /* Write every possible data byte to force correct ECC calculation. */
470 for (; i
< VIDEO_DIP_DATA_SIZE
; i
+= 4)
471 intel_de_write(dev_priv
,
472 VLV_TVIDEO_DIP_DATA(intel_crtc
->pipe
), 0);
474 val
|= g4x_infoframe_enable(type
);
475 val
&= ~VIDEO_DIP_FREQ_MASK
;
476 val
|= VIDEO_DIP_FREQ_VSYNC
;
478 intel_de_write(dev_priv
, reg
, val
);
479 intel_de_posting_read(dev_priv
, reg
);
482 static void vlv_read_infoframe(struct intel_encoder
*encoder
,
483 const struct intel_crtc_state
*crtc_state
,
485 void *frame
, ssize_t len
)
487 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
488 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
489 u32 val
, *data
= frame
;
492 val
= intel_de_read(dev_priv
, VLV_TVIDEO_DIP_CTL(crtc
->pipe
));
494 val
&= ~(VIDEO_DIP_SELECT_MASK
| 0xf); /* clear DIP data offset */
495 val
|= g4x_infoframe_index(type
);
497 intel_de_write(dev_priv
, VLV_TVIDEO_DIP_CTL(crtc
->pipe
), val
);
499 for (i
= 0; i
< len
; i
+= 4)
500 *data
++ = intel_de_read(dev_priv
,
501 VLV_TVIDEO_DIP_DATA(crtc
->pipe
));
504 static u32
vlv_infoframes_enabled(struct intel_encoder
*encoder
,
505 const struct intel_crtc_state
*pipe_config
)
507 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
508 enum pipe pipe
= to_intel_crtc(pipe_config
->uapi
.crtc
)->pipe
;
509 u32 val
= intel_de_read(dev_priv
, VLV_TVIDEO_DIP_CTL(pipe
));
511 if ((val
& VIDEO_DIP_ENABLE
) == 0)
514 if ((val
& VIDEO_DIP_PORT_MASK
) != VIDEO_DIP_PORT(encoder
->port
))
517 return val
& (VIDEO_DIP_ENABLE_AVI
|
518 VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_GAMUT
|
519 VIDEO_DIP_ENABLE_SPD
| VIDEO_DIP_ENABLE_GCP
);
522 static void hsw_write_infoframe(struct intel_encoder
*encoder
,
523 const struct intel_crtc_state
*crtc_state
,
525 const void *frame
, ssize_t len
)
527 const u32
*data
= frame
;
528 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
529 enum transcoder cpu_transcoder
= crtc_state
->cpu_transcoder
;
530 i915_reg_t ctl_reg
= HSW_TVIDEO_DIP_CTL(cpu_transcoder
);
533 u32 val
= intel_de_read(dev_priv
, ctl_reg
);
535 data_size
= hsw_dip_data_size(dev_priv
, type
);
537 drm_WARN_ON(&dev_priv
->drm
, len
> data_size
);
539 val
&= ~hsw_infoframe_enable(type
);
540 intel_de_write(dev_priv
, ctl_reg
, val
);
542 for (i
= 0; i
< len
; i
+= 4) {
543 intel_de_write(dev_priv
,
544 hsw_dip_data_reg(dev_priv
, cpu_transcoder
, type
, i
>> 2),
548 /* Write every possible data byte to force correct ECC calculation. */
549 for (; i
< data_size
; i
+= 4)
550 intel_de_write(dev_priv
,
551 hsw_dip_data_reg(dev_priv
, cpu_transcoder
, type
, i
>> 2),
554 val
|= hsw_infoframe_enable(type
);
555 intel_de_write(dev_priv
, ctl_reg
, val
);
556 intel_de_posting_read(dev_priv
, ctl_reg
);
559 static void hsw_read_infoframe(struct intel_encoder
*encoder
,
560 const struct intel_crtc_state
*crtc_state
,
562 void *frame
, ssize_t len
)
564 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
565 enum transcoder cpu_transcoder
= crtc_state
->cpu_transcoder
;
566 u32 val
, *data
= frame
;
569 val
= intel_de_read(dev_priv
, HSW_TVIDEO_DIP_CTL(cpu_transcoder
));
571 for (i
= 0; i
< len
; i
+= 4)
572 *data
++ = intel_de_read(dev_priv
,
573 hsw_dip_data_reg(dev_priv
, cpu_transcoder
, type
, i
>> 2));
576 static u32
hsw_infoframes_enabled(struct intel_encoder
*encoder
,
577 const struct intel_crtc_state
*pipe_config
)
579 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
580 u32 val
= intel_de_read(dev_priv
,
581 HSW_TVIDEO_DIP_CTL(pipe_config
->cpu_transcoder
));
584 mask
= (VIDEO_DIP_ENABLE_VSC_HSW
| VIDEO_DIP_ENABLE_AVI_HSW
|
585 VIDEO_DIP_ENABLE_GCP_HSW
| VIDEO_DIP_ENABLE_VS_HSW
|
586 VIDEO_DIP_ENABLE_GMP_HSW
| VIDEO_DIP_ENABLE_SPD_HSW
);
588 if (INTEL_GEN(dev_priv
) >= 10 || IS_GEMINILAKE(dev_priv
))
589 mask
|= VIDEO_DIP_ENABLE_DRM_GLK
;
594 static const u8 infoframe_type_to_idx
[] = {
595 HDMI_PACKET_TYPE_GENERAL_CONTROL
,
596 HDMI_PACKET_TYPE_GAMUT_METADATA
,
598 HDMI_INFOFRAME_TYPE_AVI
,
599 HDMI_INFOFRAME_TYPE_SPD
,
600 HDMI_INFOFRAME_TYPE_VENDOR
,
601 HDMI_INFOFRAME_TYPE_DRM
,
604 u32
intel_hdmi_infoframe_enable(unsigned int type
)
608 for (i
= 0; i
< ARRAY_SIZE(infoframe_type_to_idx
); i
++) {
609 if (infoframe_type_to_idx
[i
] == type
)
616 u32
intel_hdmi_infoframes_enabled(struct intel_encoder
*encoder
,
617 const struct intel_crtc_state
*crtc_state
)
619 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
620 struct intel_digital_port
*dig_port
= enc_to_dig_port(encoder
);
624 val
= dig_port
->infoframes_enabled(encoder
, crtc_state
);
626 /* map from hardware bits to dip idx */
627 for (i
= 0; i
< ARRAY_SIZE(infoframe_type_to_idx
); i
++) {
628 unsigned int type
= infoframe_type_to_idx
[i
];
630 if (HAS_DDI(dev_priv
)) {
631 if (val
& hsw_infoframe_enable(type
))
634 if (val
& g4x_infoframe_enable(type
))
643 * The data we write to the DIP data buffer registers is 1 byte bigger than the
644 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
645 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
646 * used for both technologies.
648 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
649 * DW1: DB3 | DB2 | DB1 | DB0
650 * DW2: DB7 | DB6 | DB5 | DB4
653 * (HB is Header Byte, DB is Data Byte)
655 * The hdmi pack() functions don't know about that hardware specific hole so we
656 * trick them by giving an offset into the buffer and moving back the header
659 static void intel_write_infoframe(struct intel_encoder
*encoder
,
660 const struct intel_crtc_state
*crtc_state
,
661 enum hdmi_infoframe_type type
,
662 const union hdmi_infoframe
*frame
)
664 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
665 u8 buffer
[VIDEO_DIP_DATA_SIZE
];
668 if ((crtc_state
->infoframes
.enable
&
669 intel_hdmi_infoframe_enable(type
)) == 0)
672 if (drm_WARN_ON(encoder
->base
.dev
, frame
->any
.type
!= type
))
675 /* see comment above for the reason for this offset */
676 len
= hdmi_infoframe_pack_only(frame
, buffer
+ 1, sizeof(buffer
) - 1);
677 if (drm_WARN_ON(encoder
->base
.dev
, len
< 0))
680 /* Insert the 'hole' (see big comment above) at position 3 */
681 memmove(&buffer
[0], &buffer
[1], 3);
685 intel_dig_port
->write_infoframe(encoder
, crtc_state
, type
, buffer
, len
);
688 void intel_read_infoframe(struct intel_encoder
*encoder
,
689 const struct intel_crtc_state
*crtc_state
,
690 enum hdmi_infoframe_type type
,
691 union hdmi_infoframe
*frame
)
693 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
694 u8 buffer
[VIDEO_DIP_DATA_SIZE
];
697 if ((crtc_state
->infoframes
.enable
&
698 intel_hdmi_infoframe_enable(type
)) == 0)
701 intel_dig_port
->read_infoframe(encoder
, crtc_state
,
702 type
, buffer
, sizeof(buffer
));
704 /* Fill the 'hole' (see big comment above) at position 3 */
705 memmove(&buffer
[1], &buffer
[0], 3);
707 /* see comment above for the reason for this offset */
708 ret
= hdmi_infoframe_unpack(frame
, buffer
+ 1, sizeof(buffer
) - 1);
710 DRM_DEBUG_KMS("Failed to unpack infoframe type 0x%02x\n", type
);
714 if (frame
->any
.type
!= type
)
715 DRM_DEBUG_KMS("Found the wrong infoframe type 0x%x (expected 0x%02x)\n",
716 frame
->any
.type
, type
);
720 intel_hdmi_compute_avi_infoframe(struct intel_encoder
*encoder
,
721 struct intel_crtc_state
*crtc_state
,
722 struct drm_connector_state
*conn_state
)
724 struct hdmi_avi_infoframe
*frame
= &crtc_state
->infoframes
.avi
.avi
;
725 const struct drm_display_mode
*adjusted_mode
=
726 &crtc_state
->hw
.adjusted_mode
;
727 struct drm_connector
*connector
= conn_state
->connector
;
730 if (!crtc_state
->has_infoframe
)
733 crtc_state
->infoframes
.enable
|=
734 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI
);
736 ret
= drm_hdmi_avi_infoframe_from_display_mode(frame
, connector
,
741 if (crtc_state
->output_format
== INTEL_OUTPUT_FORMAT_YCBCR420
)
742 frame
->colorspace
= HDMI_COLORSPACE_YUV420
;
743 else if (crtc_state
->output_format
== INTEL_OUTPUT_FORMAT_YCBCR444
)
744 frame
->colorspace
= HDMI_COLORSPACE_YUV444
;
746 frame
->colorspace
= HDMI_COLORSPACE_RGB
;
748 drm_hdmi_avi_infoframe_colorspace(frame
, conn_state
);
750 /* nonsense combination */
751 drm_WARN_ON(encoder
->base
.dev
, crtc_state
->limited_color_range
&&
752 crtc_state
->output_format
!= INTEL_OUTPUT_FORMAT_RGB
);
754 if (crtc_state
->output_format
== INTEL_OUTPUT_FORMAT_RGB
) {
755 drm_hdmi_avi_infoframe_quant_range(frame
, connector
,
757 crtc_state
->limited_color_range
?
758 HDMI_QUANTIZATION_RANGE_LIMITED
:
759 HDMI_QUANTIZATION_RANGE_FULL
);
761 frame
->quantization_range
= HDMI_QUANTIZATION_RANGE_DEFAULT
;
762 frame
->ycc_quantization_range
= HDMI_YCC_QUANTIZATION_RANGE_LIMITED
;
765 drm_hdmi_avi_infoframe_content_type(frame
, conn_state
);
767 /* TODO: handle pixel repetition for YCBCR420 outputs */
769 ret
= hdmi_avi_infoframe_check(frame
);
770 if (drm_WARN_ON(encoder
->base
.dev
, ret
))
777 intel_hdmi_compute_spd_infoframe(struct intel_encoder
*encoder
,
778 struct intel_crtc_state
*crtc_state
,
779 struct drm_connector_state
*conn_state
)
781 struct hdmi_spd_infoframe
*frame
= &crtc_state
->infoframes
.spd
.spd
;
784 if (!crtc_state
->has_infoframe
)
787 crtc_state
->infoframes
.enable
|=
788 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD
);
790 ret
= hdmi_spd_infoframe_init(frame
, "Intel", "Integrated gfx");
791 if (drm_WARN_ON(encoder
->base
.dev
, ret
))
794 frame
->sdi
= HDMI_SPD_SDI_PC
;
796 ret
= hdmi_spd_infoframe_check(frame
);
797 if (drm_WARN_ON(encoder
->base
.dev
, ret
))
804 intel_hdmi_compute_hdmi_infoframe(struct intel_encoder
*encoder
,
805 struct intel_crtc_state
*crtc_state
,
806 struct drm_connector_state
*conn_state
)
808 struct hdmi_vendor_infoframe
*frame
=
809 &crtc_state
->infoframes
.hdmi
.vendor
.hdmi
;
810 const struct drm_display_info
*info
=
811 &conn_state
->connector
->display_info
;
814 if (!crtc_state
->has_infoframe
|| !info
->has_hdmi_infoframe
)
817 crtc_state
->infoframes
.enable
|=
818 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR
);
820 ret
= drm_hdmi_vendor_infoframe_from_display_mode(frame
,
821 conn_state
->connector
,
822 &crtc_state
->hw
.adjusted_mode
);
823 if (drm_WARN_ON(encoder
->base
.dev
, ret
))
826 ret
= hdmi_vendor_infoframe_check(frame
);
827 if (drm_WARN_ON(encoder
->base
.dev
, ret
))
834 intel_hdmi_compute_drm_infoframe(struct intel_encoder
*encoder
,
835 struct intel_crtc_state
*crtc_state
,
836 struct drm_connector_state
*conn_state
)
838 struct hdmi_drm_infoframe
*frame
= &crtc_state
->infoframes
.drm
.drm
;
839 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
842 if (!(INTEL_GEN(dev_priv
) >= 10 || IS_GEMINILAKE(dev_priv
)))
845 if (!crtc_state
->has_infoframe
)
848 if (!conn_state
->hdr_output_metadata
)
851 crtc_state
->infoframes
.enable
|=
852 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM
);
854 ret
= drm_hdmi_infoframe_set_hdr_metadata(frame
, conn_state
);
856 DRM_DEBUG_KMS("couldn't set HDR metadata in infoframe\n");
860 ret
= hdmi_drm_infoframe_check(frame
);
861 if (drm_WARN_ON(&dev_priv
->drm
, ret
))
867 static void g4x_set_infoframes(struct intel_encoder
*encoder
,
869 const struct intel_crtc_state
*crtc_state
,
870 const struct drm_connector_state
*conn_state
)
872 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
873 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
874 struct intel_hdmi
*intel_hdmi
= &intel_dig_port
->hdmi
;
875 i915_reg_t reg
= VIDEO_DIP_CTL
;
876 u32 val
= intel_de_read(dev_priv
, reg
);
877 u32 port
= VIDEO_DIP_PORT(encoder
->port
);
879 assert_hdmi_port_disabled(intel_hdmi
);
881 /* If the registers were not initialized yet, they might be zeroes,
882 * which means we're selecting the AVI DIP and we're setting its
883 * frequency to once. This seems to really confuse the HW and make
884 * things stop working (the register spec says the AVI always needs to
885 * be sent every VSync). So here we avoid writing to the register more
886 * than we need and also explicitly select the AVI DIP and explicitly
887 * set its frequency to every VSync. Avoiding to write it twice seems to
888 * be enough to solve the problem, but being defensive shouldn't hurt us
890 val
|= VIDEO_DIP_SELECT_AVI
| VIDEO_DIP_FREQ_VSYNC
;
893 if (!(val
& VIDEO_DIP_ENABLE
))
895 if (port
!= (val
& VIDEO_DIP_PORT_MASK
)) {
896 DRM_DEBUG_KMS("video DIP still enabled on port %c\n",
897 (val
& VIDEO_DIP_PORT_MASK
) >> 29);
900 val
&= ~(VIDEO_DIP_ENABLE
| VIDEO_DIP_ENABLE_AVI
|
901 VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_SPD
);
902 intel_de_write(dev_priv
, reg
, val
);
903 intel_de_posting_read(dev_priv
, reg
);
907 if (port
!= (val
& VIDEO_DIP_PORT_MASK
)) {
908 if (val
& VIDEO_DIP_ENABLE
) {
909 DRM_DEBUG_KMS("video DIP already enabled on port %c\n",
910 (val
& VIDEO_DIP_PORT_MASK
) >> 29);
913 val
&= ~VIDEO_DIP_PORT_MASK
;
917 val
|= VIDEO_DIP_ENABLE
;
918 val
&= ~(VIDEO_DIP_ENABLE_AVI
|
919 VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_SPD
);
921 intel_de_write(dev_priv
, reg
, val
);
922 intel_de_posting_read(dev_priv
, reg
);
924 intel_write_infoframe(encoder
, crtc_state
,
925 HDMI_INFOFRAME_TYPE_AVI
,
926 &crtc_state
->infoframes
.avi
);
927 intel_write_infoframe(encoder
, crtc_state
,
928 HDMI_INFOFRAME_TYPE_SPD
,
929 &crtc_state
->infoframes
.spd
);
930 intel_write_infoframe(encoder
, crtc_state
,
931 HDMI_INFOFRAME_TYPE_VENDOR
,
932 &crtc_state
->infoframes
.hdmi
);
936 * Determine if default_phase=1 can be indicated in the GCP infoframe.
938 * From HDMI specification 1.4a:
939 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
940 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
941 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
942 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
945 static bool gcp_default_phase_possible(int pipe_bpp
,
946 const struct drm_display_mode
*mode
)
948 unsigned int pixels_per_group
;
952 /* 4 pixels in 5 clocks */
953 pixels_per_group
= 4;
956 /* 2 pixels in 3 clocks */
957 pixels_per_group
= 2;
960 /* 1 pixel in 2 clocks */
961 pixels_per_group
= 1;
964 /* phase information not relevant for 8bpc */
968 return mode
->crtc_hdisplay
% pixels_per_group
== 0 &&
969 mode
->crtc_htotal
% pixels_per_group
== 0 &&
970 mode
->crtc_hblank_start
% pixels_per_group
== 0 &&
971 mode
->crtc_hblank_end
% pixels_per_group
== 0 &&
972 mode
->crtc_hsync_start
% pixels_per_group
== 0 &&
973 mode
->crtc_hsync_end
% pixels_per_group
== 0 &&
974 ((mode
->flags
& DRM_MODE_FLAG_INTERLACE
) == 0 ||
975 mode
->crtc_htotal
/2 % pixels_per_group
== 0);
978 static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder
*encoder
,
979 const struct intel_crtc_state
*crtc_state
,
980 const struct drm_connector_state
*conn_state
)
982 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
983 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
986 if ((crtc_state
->infoframes
.enable
&
987 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL
)) == 0)
990 if (HAS_DDI(dev_priv
))
991 reg
= HSW_TVIDEO_DIP_GCP(crtc_state
->cpu_transcoder
);
992 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
993 reg
= VLV_TVIDEO_DIP_GCP(crtc
->pipe
);
994 else if (HAS_PCH_SPLIT(dev_priv
))
995 reg
= TVIDEO_DIP_GCP(crtc
->pipe
);
999 intel_de_write(dev_priv
, reg
, crtc_state
->infoframes
.gcp
);
1004 void intel_hdmi_read_gcp_infoframe(struct intel_encoder
*encoder
,
1005 struct intel_crtc_state
*crtc_state
)
1007 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
1008 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
1011 if ((crtc_state
->infoframes
.enable
&
1012 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL
)) == 0)
1015 if (HAS_DDI(dev_priv
))
1016 reg
= HSW_TVIDEO_DIP_GCP(crtc_state
->cpu_transcoder
);
1017 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
1018 reg
= VLV_TVIDEO_DIP_GCP(crtc
->pipe
);
1019 else if (HAS_PCH_SPLIT(dev_priv
))
1020 reg
= TVIDEO_DIP_GCP(crtc
->pipe
);
1024 crtc_state
->infoframes
.gcp
= intel_de_read(dev_priv
, reg
);
1027 static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder
*encoder
,
1028 struct intel_crtc_state
*crtc_state
,
1029 struct drm_connector_state
*conn_state
)
1031 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
1033 if (IS_G4X(dev_priv
) || !crtc_state
->has_infoframe
)
1036 crtc_state
->infoframes
.enable
|=
1037 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL
);
1039 /* Indicate color indication for deep color mode */
1040 if (crtc_state
->pipe_bpp
> 24)
1041 crtc_state
->infoframes
.gcp
|= GCP_COLOR_INDICATION
;
1043 /* Enable default_phase whenever the display mode is suitably aligned */
1044 if (gcp_default_phase_possible(crtc_state
->pipe_bpp
,
1045 &crtc_state
->hw
.adjusted_mode
))
1046 crtc_state
->infoframes
.gcp
|= GCP_DEFAULT_PHASE_ENABLE
;
1049 static void ibx_set_infoframes(struct intel_encoder
*encoder
,
1051 const struct intel_crtc_state
*crtc_state
,
1052 const struct drm_connector_state
*conn_state
)
1054 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
1055 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
1056 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
1057 struct intel_hdmi
*intel_hdmi
= &intel_dig_port
->hdmi
;
1058 i915_reg_t reg
= TVIDEO_DIP_CTL(intel_crtc
->pipe
);
1059 u32 val
= intel_de_read(dev_priv
, reg
);
1060 u32 port
= VIDEO_DIP_PORT(encoder
->port
);
1062 assert_hdmi_port_disabled(intel_hdmi
);
1064 /* See the big comment in g4x_set_infoframes() */
1065 val
|= VIDEO_DIP_SELECT_AVI
| VIDEO_DIP_FREQ_VSYNC
;
1068 if (!(val
& VIDEO_DIP_ENABLE
))
1070 val
&= ~(VIDEO_DIP_ENABLE
| VIDEO_DIP_ENABLE_AVI
|
1071 VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_GAMUT
|
1072 VIDEO_DIP_ENABLE_SPD
| VIDEO_DIP_ENABLE_GCP
);
1073 intel_de_write(dev_priv
, reg
, val
);
1074 intel_de_posting_read(dev_priv
, reg
);
1078 if (port
!= (val
& VIDEO_DIP_PORT_MASK
)) {
1079 drm_WARN(&dev_priv
->drm
, val
& VIDEO_DIP_ENABLE
,
1080 "DIP already enabled on port %c\n",
1081 (val
& VIDEO_DIP_PORT_MASK
) >> 29);
1082 val
&= ~VIDEO_DIP_PORT_MASK
;
1086 val
|= VIDEO_DIP_ENABLE
;
1087 val
&= ~(VIDEO_DIP_ENABLE_AVI
|
1088 VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_GAMUT
|
1089 VIDEO_DIP_ENABLE_SPD
| VIDEO_DIP_ENABLE_GCP
);
1091 if (intel_hdmi_set_gcp_infoframe(encoder
, crtc_state
, conn_state
))
1092 val
|= VIDEO_DIP_ENABLE_GCP
;
1094 intel_de_write(dev_priv
, reg
, val
);
1095 intel_de_posting_read(dev_priv
, reg
);
1097 intel_write_infoframe(encoder
, crtc_state
,
1098 HDMI_INFOFRAME_TYPE_AVI
,
1099 &crtc_state
->infoframes
.avi
);
1100 intel_write_infoframe(encoder
, crtc_state
,
1101 HDMI_INFOFRAME_TYPE_SPD
,
1102 &crtc_state
->infoframes
.spd
);
1103 intel_write_infoframe(encoder
, crtc_state
,
1104 HDMI_INFOFRAME_TYPE_VENDOR
,
1105 &crtc_state
->infoframes
.hdmi
);
1108 static void cpt_set_infoframes(struct intel_encoder
*encoder
,
1110 const struct intel_crtc_state
*crtc_state
,
1111 const struct drm_connector_state
*conn_state
)
1113 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
1114 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
1115 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
1116 i915_reg_t reg
= TVIDEO_DIP_CTL(intel_crtc
->pipe
);
1117 u32 val
= intel_de_read(dev_priv
, reg
);
1119 assert_hdmi_port_disabled(intel_hdmi
);
1121 /* See the big comment in g4x_set_infoframes() */
1122 val
|= VIDEO_DIP_SELECT_AVI
| VIDEO_DIP_FREQ_VSYNC
;
1125 if (!(val
& VIDEO_DIP_ENABLE
))
1127 val
&= ~(VIDEO_DIP_ENABLE
| VIDEO_DIP_ENABLE_AVI
|
1128 VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_GAMUT
|
1129 VIDEO_DIP_ENABLE_SPD
| VIDEO_DIP_ENABLE_GCP
);
1130 intel_de_write(dev_priv
, reg
, val
);
1131 intel_de_posting_read(dev_priv
, reg
);
1135 /* Set both together, unset both together: see the spec. */
1136 val
|= VIDEO_DIP_ENABLE
| VIDEO_DIP_ENABLE_AVI
;
1137 val
&= ~(VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_GAMUT
|
1138 VIDEO_DIP_ENABLE_SPD
| VIDEO_DIP_ENABLE_GCP
);
1140 if (intel_hdmi_set_gcp_infoframe(encoder
, crtc_state
, conn_state
))
1141 val
|= VIDEO_DIP_ENABLE_GCP
;
1143 intel_de_write(dev_priv
, reg
, val
);
1144 intel_de_posting_read(dev_priv
, reg
);
1146 intel_write_infoframe(encoder
, crtc_state
,
1147 HDMI_INFOFRAME_TYPE_AVI
,
1148 &crtc_state
->infoframes
.avi
);
1149 intel_write_infoframe(encoder
, crtc_state
,
1150 HDMI_INFOFRAME_TYPE_SPD
,
1151 &crtc_state
->infoframes
.spd
);
1152 intel_write_infoframe(encoder
, crtc_state
,
1153 HDMI_INFOFRAME_TYPE_VENDOR
,
1154 &crtc_state
->infoframes
.hdmi
);
1157 static void vlv_set_infoframes(struct intel_encoder
*encoder
,
1159 const struct intel_crtc_state
*crtc_state
,
1160 const struct drm_connector_state
*conn_state
)
1162 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
1163 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
1164 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
1165 i915_reg_t reg
= VLV_TVIDEO_DIP_CTL(intel_crtc
->pipe
);
1166 u32 val
= intel_de_read(dev_priv
, reg
);
1167 u32 port
= VIDEO_DIP_PORT(encoder
->port
);
1169 assert_hdmi_port_disabled(intel_hdmi
);
1171 /* See the big comment in g4x_set_infoframes() */
1172 val
|= VIDEO_DIP_SELECT_AVI
| VIDEO_DIP_FREQ_VSYNC
;
1175 if (!(val
& VIDEO_DIP_ENABLE
))
1177 val
&= ~(VIDEO_DIP_ENABLE
| VIDEO_DIP_ENABLE_AVI
|
1178 VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_GAMUT
|
1179 VIDEO_DIP_ENABLE_SPD
| VIDEO_DIP_ENABLE_GCP
);
1180 intel_de_write(dev_priv
, reg
, val
);
1181 intel_de_posting_read(dev_priv
, reg
);
1185 if (port
!= (val
& VIDEO_DIP_PORT_MASK
)) {
1186 drm_WARN(&dev_priv
->drm
, val
& VIDEO_DIP_ENABLE
,
1187 "DIP already enabled on port %c\n",
1188 (val
& VIDEO_DIP_PORT_MASK
) >> 29);
1189 val
&= ~VIDEO_DIP_PORT_MASK
;
1193 val
|= VIDEO_DIP_ENABLE
;
1194 val
&= ~(VIDEO_DIP_ENABLE_AVI
|
1195 VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_GAMUT
|
1196 VIDEO_DIP_ENABLE_SPD
| VIDEO_DIP_ENABLE_GCP
);
1198 if (intel_hdmi_set_gcp_infoframe(encoder
, crtc_state
, conn_state
))
1199 val
|= VIDEO_DIP_ENABLE_GCP
;
1201 intel_de_write(dev_priv
, reg
, val
);
1202 intel_de_posting_read(dev_priv
, reg
);
1204 intel_write_infoframe(encoder
, crtc_state
,
1205 HDMI_INFOFRAME_TYPE_AVI
,
1206 &crtc_state
->infoframes
.avi
);
1207 intel_write_infoframe(encoder
, crtc_state
,
1208 HDMI_INFOFRAME_TYPE_SPD
,
1209 &crtc_state
->infoframes
.spd
);
1210 intel_write_infoframe(encoder
, crtc_state
,
1211 HDMI_INFOFRAME_TYPE_VENDOR
,
1212 &crtc_state
->infoframes
.hdmi
);
1215 static void hsw_set_infoframes(struct intel_encoder
*encoder
,
1217 const struct intel_crtc_state
*crtc_state
,
1218 const struct drm_connector_state
*conn_state
)
1220 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
1221 i915_reg_t reg
= HSW_TVIDEO_DIP_CTL(crtc_state
->cpu_transcoder
);
1222 u32 val
= intel_de_read(dev_priv
, reg
);
1224 assert_hdmi_transcoder_func_disabled(dev_priv
,
1225 crtc_state
->cpu_transcoder
);
1227 val
&= ~(VIDEO_DIP_ENABLE_VSC_HSW
| VIDEO_DIP_ENABLE_AVI_HSW
|
1228 VIDEO_DIP_ENABLE_GCP_HSW
| VIDEO_DIP_ENABLE_VS_HSW
|
1229 VIDEO_DIP_ENABLE_GMP_HSW
| VIDEO_DIP_ENABLE_SPD_HSW
|
1230 VIDEO_DIP_ENABLE_DRM_GLK
);
1233 intel_de_write(dev_priv
, reg
, val
);
1234 intel_de_posting_read(dev_priv
, reg
);
1238 if (intel_hdmi_set_gcp_infoframe(encoder
, crtc_state
, conn_state
))
1239 val
|= VIDEO_DIP_ENABLE_GCP_HSW
;
1241 intel_de_write(dev_priv
, reg
, val
);
1242 intel_de_posting_read(dev_priv
, reg
);
1244 intel_write_infoframe(encoder
, crtc_state
,
1245 HDMI_INFOFRAME_TYPE_AVI
,
1246 &crtc_state
->infoframes
.avi
);
1247 intel_write_infoframe(encoder
, crtc_state
,
1248 HDMI_INFOFRAME_TYPE_SPD
,
1249 &crtc_state
->infoframes
.spd
);
1250 intel_write_infoframe(encoder
, crtc_state
,
1251 HDMI_INFOFRAME_TYPE_VENDOR
,
1252 &crtc_state
->infoframes
.hdmi
);
1253 intel_write_infoframe(encoder
, crtc_state
,
1254 HDMI_INFOFRAME_TYPE_DRM
,
1255 &crtc_state
->infoframes
.drm
);
1258 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi
*hdmi
, bool enable
)
1260 struct drm_i915_private
*dev_priv
= to_i915(intel_hdmi_to_dev(hdmi
));
1261 struct i2c_adapter
*adapter
=
1262 intel_gmbus_get_adapter(dev_priv
, hdmi
->ddc_bus
);
1264 if (hdmi
->dp_dual_mode
.type
< DRM_DP_DUAL_MODE_TYPE2_DVI
)
1267 DRM_DEBUG_KMS("%s DP dual mode adaptor TMDS output\n",
1268 enable
? "Enabling" : "Disabling");
1270 drm_dp_dual_mode_set_tmds_output(hdmi
->dp_dual_mode
.type
,
1274 static int intel_hdmi_hdcp_read(struct intel_digital_port
*intel_dig_port
,
1275 unsigned int offset
, void *buffer
, size_t size
)
1277 struct drm_i915_private
*i915
= to_i915(intel_dig_port
->base
.base
.dev
);
1278 struct intel_hdmi
*hdmi
= &intel_dig_port
->hdmi
;
1279 struct i2c_adapter
*adapter
= intel_gmbus_get_adapter(i915
,
1282 u8 start
= offset
& 0xff;
1283 struct i2c_msg msgs
[] = {
1285 .addr
= DRM_HDCP_DDC_ADDR
,
1291 .addr
= DRM_HDCP_DDC_ADDR
,
1297 ret
= i2c_transfer(adapter
, msgs
, ARRAY_SIZE(msgs
));
1298 if (ret
== ARRAY_SIZE(msgs
))
1300 return ret
>= 0 ? -EIO
: ret
;
1303 static int intel_hdmi_hdcp_write(struct intel_digital_port
*intel_dig_port
,
1304 unsigned int offset
, void *buffer
, size_t size
)
1306 struct drm_i915_private
*i915
= to_i915(intel_dig_port
->base
.base
.dev
);
1307 struct intel_hdmi
*hdmi
= &intel_dig_port
->hdmi
;
1308 struct i2c_adapter
*adapter
= intel_gmbus_get_adapter(i915
,
1314 write_buf
= kzalloc(size
+ 1, GFP_KERNEL
);
1318 write_buf
[0] = offset
& 0xff;
1319 memcpy(&write_buf
[1], buffer
, size
);
1321 msg
.addr
= DRM_HDCP_DDC_ADDR
;
1324 msg
.buf
= write_buf
;
1326 ret
= i2c_transfer(adapter
, &msg
, 1);
1337 int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port
*intel_dig_port
,
1340 struct drm_i915_private
*i915
= to_i915(intel_dig_port
->base
.base
.dev
);
1341 struct intel_hdmi
*hdmi
= &intel_dig_port
->hdmi
;
1342 struct i2c_adapter
*adapter
= intel_gmbus_get_adapter(i915
,
1346 ret
= intel_hdmi_hdcp_write(intel_dig_port
, DRM_HDCP_DDC_AN
, an
,
1349 DRM_DEBUG_KMS("Write An over DDC failed (%d)\n", ret
);
1353 ret
= intel_gmbus_output_aksv(adapter
);
1355 DRM_DEBUG_KMS("Failed to output aksv (%d)\n", ret
);
1361 static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port
*intel_dig_port
,
1365 ret
= intel_hdmi_hdcp_read(intel_dig_port
, DRM_HDCP_DDC_BKSV
, bksv
,
1368 DRM_DEBUG_KMS("Read Bksv over DDC failed (%d)\n", ret
);
1373 int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port
*intel_dig_port
,
1377 ret
= intel_hdmi_hdcp_read(intel_dig_port
, DRM_HDCP_DDC_BSTATUS
,
1378 bstatus
, DRM_HDCP_BSTATUS_LEN
);
1380 DRM_DEBUG_KMS("Read bstatus over DDC failed (%d)\n", ret
);
1385 int intel_hdmi_hdcp_repeater_present(struct intel_digital_port
*intel_dig_port
,
1386 bool *repeater_present
)
1391 ret
= intel_hdmi_hdcp_read(intel_dig_port
, DRM_HDCP_DDC_BCAPS
, &val
, 1);
1393 DRM_DEBUG_KMS("Read bcaps over DDC failed (%d)\n", ret
);
1396 *repeater_present
= val
& DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT
;
1401 int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port
*intel_dig_port
,
1405 ret
= intel_hdmi_hdcp_read(intel_dig_port
, DRM_HDCP_DDC_RI_PRIME
,
1406 ri_prime
, DRM_HDCP_RI_LEN
);
1408 DRM_DEBUG_KMS("Read Ri' over DDC failed (%d)\n", ret
);
1413 int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port
*intel_dig_port
,
1419 ret
= intel_hdmi_hdcp_read(intel_dig_port
, DRM_HDCP_DDC_BCAPS
, &val
, 1);
1421 DRM_DEBUG_KMS("Read bcaps over DDC failed (%d)\n", ret
);
1424 *ksv_ready
= val
& DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY
;
1429 int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port
*intel_dig_port
,
1430 int num_downstream
, u8
*ksv_fifo
)
1433 ret
= intel_hdmi_hdcp_read(intel_dig_port
, DRM_HDCP_DDC_KSV_FIFO
,
1434 ksv_fifo
, num_downstream
* DRM_HDCP_KSV_LEN
);
1436 DRM_DEBUG_KMS("Read ksv fifo over DDC failed (%d)\n", ret
);
1443 int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port
*intel_dig_port
,
1448 if (i
>= DRM_HDCP_V_PRIME_NUM_PARTS
)
1451 ret
= intel_hdmi_hdcp_read(intel_dig_port
, DRM_HDCP_DDC_V_PRIME(i
),
1452 part
, DRM_HDCP_V_PRIME_PART_LEN
);
1454 DRM_DEBUG_KMS("Read V'[%d] over DDC failed (%d)\n", i
, ret
);
1458 static int kbl_repositioning_enc_en_signal(struct intel_connector
*connector
)
1460 struct drm_i915_private
*dev_priv
= to_i915(connector
->base
.dev
);
1461 struct intel_digital_port
*intel_dig_port
= intel_attached_dig_port(connector
);
1462 struct drm_crtc
*crtc
= connector
->base
.state
->crtc
;
1463 struct intel_crtc
*intel_crtc
= container_of(crtc
,
1464 struct intel_crtc
, base
);
1469 scanline
= intel_de_read(dev_priv
, PIPEDSL(intel_crtc
->pipe
));
1470 if (scanline
> 100 && scanline
< 200)
1472 usleep_range(25, 50);
1475 ret
= intel_ddi_toggle_hdcp_signalling(&intel_dig_port
->base
, false);
1477 DRM_ERROR("Disable HDCP signalling failed (%d)\n", ret
);
1480 ret
= intel_ddi_toggle_hdcp_signalling(&intel_dig_port
->base
, true);
1482 DRM_ERROR("Enable HDCP signalling failed (%d)\n", ret
);
1490 int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port
*intel_dig_port
,
1493 struct intel_hdmi
*hdmi
= &intel_dig_port
->hdmi
;
1494 struct intel_connector
*connector
= hdmi
->attached_connector
;
1495 struct drm_i915_private
*dev_priv
= to_i915(connector
->base
.dev
);
1499 usleep_range(6, 60); /* Bspec says >= 6us */
1501 ret
= intel_ddi_toggle_hdcp_signalling(&intel_dig_port
->base
, enable
);
1503 DRM_ERROR("%s HDCP signalling failed (%d)\n",
1504 enable
? "Enable" : "Disable", ret
);
1509 * WA: To fix incorrect positioning of the window of
1510 * opportunity and enc_en signalling in KABYLAKE.
1512 if (IS_KABYLAKE(dev_priv
) && enable
)
1513 return kbl_repositioning_enc_en_signal(connector
);
1519 bool intel_hdmi_hdcp_check_link(struct intel_digital_port
*intel_dig_port
)
1521 struct drm_i915_private
*i915
= to_i915(intel_dig_port
->base
.base
.dev
);
1522 struct intel_connector
*connector
=
1523 intel_dig_port
->hdmi
.attached_connector
;
1524 enum port port
= intel_dig_port
->base
.port
;
1525 enum transcoder cpu_transcoder
= connector
->hdcp
.cpu_transcoder
;
1529 u8 shim
[DRM_HDCP_RI_LEN
];
1532 ret
= intel_hdmi_hdcp_read_ri_prime(intel_dig_port
, ri
.shim
);
1536 intel_de_write(i915
, HDCP_RPRIME(i915
, cpu_transcoder
, port
), ri
.reg
);
1538 /* Wait for Ri prime match */
1539 if (wait_for((intel_de_read(i915
, HDCP_STATUS(i915
, cpu_transcoder
, port
)) &
1540 (HDCP_STATUS_RI_MATCH
| HDCP_STATUS_ENC
)) ==
1541 (HDCP_STATUS_RI_MATCH
| HDCP_STATUS_ENC
), 1)) {
1542 DRM_ERROR("Ri' mismatch detected, link check failed (%x)\n",
1543 intel_de_read(i915
, HDCP_STATUS(i915
, cpu_transcoder
, port
)));
1549 struct hdcp2_hdmi_msg_timeout
{
1554 static const struct hdcp2_hdmi_msg_timeout hdcp2_msg_timeout
[] = {
1555 { HDCP_2_2_AKE_SEND_CERT
, HDCP_2_2_CERT_TIMEOUT_MS
, },
1556 { HDCP_2_2_AKE_SEND_PAIRING_INFO
, HDCP_2_2_PAIRING_TIMEOUT_MS
, },
1557 { HDCP_2_2_LC_SEND_LPRIME
, HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS
, },
1558 { HDCP_2_2_REP_SEND_RECVID_LIST
, HDCP_2_2_RECVID_LIST_TIMEOUT_MS
, },
1559 { HDCP_2_2_REP_STREAM_READY
, HDCP_2_2_STREAM_READY_TIMEOUT_MS
, },
1563 int intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port
*intel_dig_port
,
1566 return intel_hdmi_hdcp_read(intel_dig_port
,
1567 HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET
,
1569 HDCP_2_2_HDMI_RXSTATUS_LEN
);
1572 static int get_hdcp2_msg_timeout(u8 msg_id
, bool is_paired
)
1576 if (msg_id
== HDCP_2_2_AKE_SEND_HPRIME
) {
1578 return HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS
;
1580 return HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS
;
1583 for (i
= 0; i
< ARRAY_SIZE(hdcp2_msg_timeout
); i
++) {
1584 if (hdcp2_msg_timeout
[i
].msg_id
== msg_id
)
1585 return hdcp2_msg_timeout
[i
].timeout
;
1592 int hdcp2_detect_msg_availability(struct intel_digital_port
*intel_digital_port
,
1593 u8 msg_id
, bool *msg_ready
,
1596 u8 rx_status
[HDCP_2_2_HDMI_RXSTATUS_LEN
];
1599 ret
= intel_hdmi_hdcp2_read_rx_status(intel_digital_port
, rx_status
);
1601 DRM_DEBUG_KMS("rx_status read failed. Err %d\n", ret
);
1605 *msg_sz
= ((HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(rx_status
[1]) << 8) |
1608 if (msg_id
== HDCP_2_2_REP_SEND_RECVID_LIST
)
1609 *msg_ready
= (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status
[1]) &&
1612 *msg_ready
= *msg_sz
;
1618 intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port
*intel_dig_port
,
1619 u8 msg_id
, bool paired
)
1621 bool msg_ready
= false;
1625 timeout
= get_hdcp2_msg_timeout(msg_id
, paired
);
1629 ret
= __wait_for(ret
= hdcp2_detect_msg_availability(intel_dig_port
,
1632 !ret
&& msg_ready
&& msg_sz
, timeout
* 1000,
1635 DRM_DEBUG_KMS("msg_id: %d, ret: %d, timeout: %d\n",
1636 msg_id
, ret
, timeout
);
1638 return ret
? ret
: msg_sz
;
1642 int intel_hdmi_hdcp2_write_msg(struct intel_digital_port
*intel_dig_port
,
1643 void *buf
, size_t size
)
1645 unsigned int offset
;
1647 offset
= HDCP_2_2_HDMI_REG_WR_MSG_OFFSET
;
1648 return intel_hdmi_hdcp_write(intel_dig_port
, offset
, buf
, size
);
1652 int intel_hdmi_hdcp2_read_msg(struct intel_digital_port
*intel_dig_port
,
1653 u8 msg_id
, void *buf
, size_t size
)
1655 struct intel_hdmi
*hdmi
= &intel_dig_port
->hdmi
;
1656 struct intel_hdcp
*hdcp
= &hdmi
->attached_connector
->hdcp
;
1657 unsigned int offset
;
1660 ret
= intel_hdmi_hdcp2_wait_for_msg(intel_dig_port
, msg_id
,
1666 * Available msg size should be equal to or lesser than the
1670 DRM_DEBUG_KMS("msg_sz(%zd) is more than exp size(%zu)\n",
1675 offset
= HDCP_2_2_HDMI_REG_RD_MSG_OFFSET
;
1676 ret
= intel_hdmi_hdcp_read(intel_dig_port
, offset
, buf
, ret
);
1678 DRM_DEBUG_KMS("Failed to read msg_id: %d(%zd)\n", msg_id
, ret
);
1684 int intel_hdmi_hdcp2_check_link(struct intel_digital_port
*intel_dig_port
)
1686 u8 rx_status
[HDCP_2_2_HDMI_RXSTATUS_LEN
];
1689 ret
= intel_hdmi_hdcp2_read_rx_status(intel_dig_port
, rx_status
);
1694 * Re-auth request and Link Integrity Failures are represented by
1695 * same bit. i.e reauth_req.
1697 if (HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(rx_status
[1]))
1698 ret
= HDCP_REAUTH_REQUEST
;
1699 else if (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status
[1]))
1700 ret
= HDCP_TOPOLOGY_CHANGE
;
1706 int intel_hdmi_hdcp2_capable(struct intel_digital_port
*intel_dig_port
,
1713 ret
= intel_hdmi_hdcp_read(intel_dig_port
, HDCP_2_2_HDMI_REG_VER_OFFSET
,
1714 &hdcp2_version
, sizeof(hdcp2_version
));
1715 if (!ret
&& hdcp2_version
& HDCP_2_2_HDMI_SUPPORT_MASK
)
1722 enum hdcp_wired_protocol
intel_hdmi_hdcp2_protocol(void)
1724 return HDCP_PROTOCOL_HDMI
;
1727 static const struct intel_hdcp_shim intel_hdmi_hdcp_shim
= {
1728 .write_an_aksv
= intel_hdmi_hdcp_write_an_aksv
,
1729 .read_bksv
= intel_hdmi_hdcp_read_bksv
,
1730 .read_bstatus
= intel_hdmi_hdcp_read_bstatus
,
1731 .repeater_present
= intel_hdmi_hdcp_repeater_present
,
1732 .read_ri_prime
= intel_hdmi_hdcp_read_ri_prime
,
1733 .read_ksv_ready
= intel_hdmi_hdcp_read_ksv_ready
,
1734 .read_ksv_fifo
= intel_hdmi_hdcp_read_ksv_fifo
,
1735 .read_v_prime_part
= intel_hdmi_hdcp_read_v_prime_part
,
1736 .toggle_signalling
= intel_hdmi_hdcp_toggle_signalling
,
1737 .check_link
= intel_hdmi_hdcp_check_link
,
1738 .write_2_2_msg
= intel_hdmi_hdcp2_write_msg
,
1739 .read_2_2_msg
= intel_hdmi_hdcp2_read_msg
,
1740 .check_2_2_link
= intel_hdmi_hdcp2_check_link
,
1741 .hdcp_2_2_capable
= intel_hdmi_hdcp2_capable
,
1742 .protocol
= HDCP_PROTOCOL_HDMI
,
1745 static void intel_hdmi_prepare(struct intel_encoder
*encoder
,
1746 const struct intel_crtc_state
*crtc_state
)
1748 struct drm_device
*dev
= encoder
->base
.dev
;
1749 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1750 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
1751 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
1752 const struct drm_display_mode
*adjusted_mode
= &crtc_state
->hw
.adjusted_mode
;
1755 intel_dp_dual_mode_set_tmds_output(intel_hdmi
, true);
1757 hdmi_val
= SDVO_ENCODING_HDMI
;
1758 if (!HAS_PCH_SPLIT(dev_priv
) && crtc_state
->limited_color_range
)
1759 hdmi_val
|= HDMI_COLOR_RANGE_16_235
;
1760 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1761 hdmi_val
|= SDVO_VSYNC_ACTIVE_HIGH
;
1762 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1763 hdmi_val
|= SDVO_HSYNC_ACTIVE_HIGH
;
1765 if (crtc_state
->pipe_bpp
> 24)
1766 hdmi_val
|= HDMI_COLOR_FORMAT_12bpc
;
1768 hdmi_val
|= SDVO_COLOR_FORMAT_8bpc
;
1770 if (crtc_state
->has_hdmi_sink
)
1771 hdmi_val
|= HDMI_MODE_SELECT_HDMI
;
1773 if (HAS_PCH_CPT(dev_priv
))
1774 hdmi_val
|= SDVO_PIPE_SEL_CPT(crtc
->pipe
);
1775 else if (IS_CHERRYVIEW(dev_priv
))
1776 hdmi_val
|= SDVO_PIPE_SEL_CHV(crtc
->pipe
);
1778 hdmi_val
|= SDVO_PIPE_SEL(crtc
->pipe
);
1780 intel_de_write(dev_priv
, intel_hdmi
->hdmi_reg
, hdmi_val
);
1781 intel_de_posting_read(dev_priv
, intel_hdmi
->hdmi_reg
);
1784 static bool intel_hdmi_get_hw_state(struct intel_encoder
*encoder
,
1787 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
1788 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
1789 intel_wakeref_t wakeref
;
1792 wakeref
= intel_display_power_get_if_enabled(dev_priv
,
1793 encoder
->power_domain
);
1797 ret
= intel_sdvo_port_enabled(dev_priv
, intel_hdmi
->hdmi_reg
, pipe
);
1799 intel_display_power_put(dev_priv
, encoder
->power_domain
, wakeref
);
1804 static void intel_hdmi_get_config(struct intel_encoder
*encoder
,
1805 struct intel_crtc_state
*pipe_config
)
1807 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
1808 struct drm_device
*dev
= encoder
->base
.dev
;
1809 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1813 pipe_config
->output_types
|= BIT(INTEL_OUTPUT_HDMI
);
1815 tmp
= intel_de_read(dev_priv
, intel_hdmi
->hdmi_reg
);
1817 if (tmp
& SDVO_HSYNC_ACTIVE_HIGH
)
1818 flags
|= DRM_MODE_FLAG_PHSYNC
;
1820 flags
|= DRM_MODE_FLAG_NHSYNC
;
1822 if (tmp
& SDVO_VSYNC_ACTIVE_HIGH
)
1823 flags
|= DRM_MODE_FLAG_PVSYNC
;
1825 flags
|= DRM_MODE_FLAG_NVSYNC
;
1827 if (tmp
& HDMI_MODE_SELECT_HDMI
)
1828 pipe_config
->has_hdmi_sink
= true;
1830 pipe_config
->infoframes
.enable
|=
1831 intel_hdmi_infoframes_enabled(encoder
, pipe_config
);
1833 if (pipe_config
->infoframes
.enable
)
1834 pipe_config
->has_infoframe
= true;
1836 if (tmp
& HDMI_AUDIO_ENABLE
)
1837 pipe_config
->has_audio
= true;
1839 if (!HAS_PCH_SPLIT(dev_priv
) &&
1840 tmp
& HDMI_COLOR_RANGE_16_235
)
1841 pipe_config
->limited_color_range
= true;
1843 pipe_config
->hw
.adjusted_mode
.flags
|= flags
;
1845 if ((tmp
& SDVO_COLOR_FORMAT_MASK
) == HDMI_COLOR_FORMAT_12bpc
)
1846 dotclock
= pipe_config
->port_clock
* 2 / 3;
1848 dotclock
= pipe_config
->port_clock
;
1850 if (pipe_config
->pixel_multiplier
)
1851 dotclock
/= pipe_config
->pixel_multiplier
;
1853 pipe_config
->hw
.adjusted_mode
.crtc_clock
= dotclock
;
1855 pipe_config
->lane_count
= 4;
1857 intel_hdmi_read_gcp_infoframe(encoder
, pipe_config
);
1859 intel_read_infoframe(encoder
, pipe_config
,
1860 HDMI_INFOFRAME_TYPE_AVI
,
1861 &pipe_config
->infoframes
.avi
);
1862 intel_read_infoframe(encoder
, pipe_config
,
1863 HDMI_INFOFRAME_TYPE_SPD
,
1864 &pipe_config
->infoframes
.spd
);
1865 intel_read_infoframe(encoder
, pipe_config
,
1866 HDMI_INFOFRAME_TYPE_VENDOR
,
1867 &pipe_config
->infoframes
.hdmi
);
1870 static void intel_enable_hdmi_audio(struct intel_encoder
*encoder
,
1871 const struct intel_crtc_state
*pipe_config
,
1872 const struct drm_connector_state
*conn_state
)
1874 struct intel_crtc
*crtc
= to_intel_crtc(pipe_config
->uapi
.crtc
);
1876 drm_WARN_ON(encoder
->base
.dev
, !pipe_config
->has_hdmi_sink
);
1877 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
1878 pipe_name(crtc
->pipe
));
1879 intel_audio_codec_enable(encoder
, pipe_config
, conn_state
);
1882 static void g4x_enable_hdmi(struct intel_encoder
*encoder
,
1883 const struct intel_crtc_state
*pipe_config
,
1884 const struct drm_connector_state
*conn_state
)
1886 struct drm_device
*dev
= encoder
->base
.dev
;
1887 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1888 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
1891 temp
= intel_de_read(dev_priv
, intel_hdmi
->hdmi_reg
);
1893 temp
|= SDVO_ENABLE
;
1894 if (pipe_config
->has_audio
)
1895 temp
|= HDMI_AUDIO_ENABLE
;
1897 intel_de_write(dev_priv
, intel_hdmi
->hdmi_reg
, temp
);
1898 intel_de_posting_read(dev_priv
, intel_hdmi
->hdmi_reg
);
1900 if (pipe_config
->has_audio
)
1901 intel_enable_hdmi_audio(encoder
, pipe_config
, conn_state
);
1904 static void ibx_enable_hdmi(struct intel_encoder
*encoder
,
1905 const struct intel_crtc_state
*pipe_config
,
1906 const struct drm_connector_state
*conn_state
)
1908 struct drm_device
*dev
= encoder
->base
.dev
;
1909 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1910 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
1913 temp
= intel_de_read(dev_priv
, intel_hdmi
->hdmi_reg
);
1915 temp
|= SDVO_ENABLE
;
1916 if (pipe_config
->has_audio
)
1917 temp
|= HDMI_AUDIO_ENABLE
;
1920 * HW workaround, need to write this twice for issue
1921 * that may result in first write getting masked.
1923 intel_de_write(dev_priv
, intel_hdmi
->hdmi_reg
, temp
);
1924 intel_de_posting_read(dev_priv
, intel_hdmi
->hdmi_reg
);
1925 intel_de_write(dev_priv
, intel_hdmi
->hdmi_reg
, temp
);
1926 intel_de_posting_read(dev_priv
, intel_hdmi
->hdmi_reg
);
1929 * HW workaround, need to toggle enable bit off and on
1930 * for 12bpc with pixel repeat.
1932 * FIXME: BSpec says this should be done at the end of
1933 * of the modeset sequence, so not sure if this isn't too soon.
1935 if (pipe_config
->pipe_bpp
> 24 &&
1936 pipe_config
->pixel_multiplier
> 1) {
1937 intel_de_write(dev_priv
, intel_hdmi
->hdmi_reg
,
1938 temp
& ~SDVO_ENABLE
);
1939 intel_de_posting_read(dev_priv
, intel_hdmi
->hdmi_reg
);
1942 * HW workaround, need to write this twice for issue
1943 * that may result in first write getting masked.
1945 intel_de_write(dev_priv
, intel_hdmi
->hdmi_reg
, temp
);
1946 intel_de_posting_read(dev_priv
, intel_hdmi
->hdmi_reg
);
1947 intel_de_write(dev_priv
, intel_hdmi
->hdmi_reg
, temp
);
1948 intel_de_posting_read(dev_priv
, intel_hdmi
->hdmi_reg
);
1951 if (pipe_config
->has_audio
)
1952 intel_enable_hdmi_audio(encoder
, pipe_config
, conn_state
);
1955 static void cpt_enable_hdmi(struct intel_encoder
*encoder
,
1956 const struct intel_crtc_state
*pipe_config
,
1957 const struct drm_connector_state
*conn_state
)
1959 struct drm_device
*dev
= encoder
->base
.dev
;
1960 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1961 struct intel_crtc
*crtc
= to_intel_crtc(pipe_config
->uapi
.crtc
);
1962 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
1963 enum pipe pipe
= crtc
->pipe
;
1966 temp
= intel_de_read(dev_priv
, intel_hdmi
->hdmi_reg
);
1968 temp
|= SDVO_ENABLE
;
1969 if (pipe_config
->has_audio
)
1970 temp
|= HDMI_AUDIO_ENABLE
;
1973 * WaEnableHDMI8bpcBefore12bpc:snb,ivb
1975 * The procedure for 12bpc is as follows:
1976 * 1. disable HDMI clock gating
1977 * 2. enable HDMI with 8bpc
1978 * 3. enable HDMI with 12bpc
1979 * 4. enable HDMI clock gating
1982 if (pipe_config
->pipe_bpp
> 24) {
1983 intel_de_write(dev_priv
, TRANS_CHICKEN1(pipe
),
1984 intel_de_read(dev_priv
, TRANS_CHICKEN1(pipe
)) | TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE
);
1986 temp
&= ~SDVO_COLOR_FORMAT_MASK
;
1987 temp
|= SDVO_COLOR_FORMAT_8bpc
;
1990 intel_de_write(dev_priv
, intel_hdmi
->hdmi_reg
, temp
);
1991 intel_de_posting_read(dev_priv
, intel_hdmi
->hdmi_reg
);
1993 if (pipe_config
->pipe_bpp
> 24) {
1994 temp
&= ~SDVO_COLOR_FORMAT_MASK
;
1995 temp
|= HDMI_COLOR_FORMAT_12bpc
;
1997 intel_de_write(dev_priv
, intel_hdmi
->hdmi_reg
, temp
);
1998 intel_de_posting_read(dev_priv
, intel_hdmi
->hdmi_reg
);
2000 intel_de_write(dev_priv
, TRANS_CHICKEN1(pipe
),
2001 intel_de_read(dev_priv
, TRANS_CHICKEN1(pipe
)) & ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE
);
2004 if (pipe_config
->has_audio
)
2005 intel_enable_hdmi_audio(encoder
, pipe_config
, conn_state
);
2008 static void vlv_enable_hdmi(struct intel_encoder
*encoder
,
2009 const struct intel_crtc_state
*pipe_config
,
2010 const struct drm_connector_state
*conn_state
)
2014 static void intel_disable_hdmi(struct intel_encoder
*encoder
,
2015 const struct intel_crtc_state
*old_crtc_state
,
2016 const struct drm_connector_state
*old_conn_state
)
2018 struct drm_device
*dev
= encoder
->base
.dev
;
2019 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2020 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
2021 struct intel_digital_port
*intel_dig_port
=
2022 hdmi_to_dig_port(intel_hdmi
);
2023 struct intel_crtc
*crtc
= to_intel_crtc(old_crtc_state
->uapi
.crtc
);
2026 temp
= intel_de_read(dev_priv
, intel_hdmi
->hdmi_reg
);
2028 temp
&= ~(SDVO_ENABLE
| HDMI_AUDIO_ENABLE
);
2029 intel_de_write(dev_priv
, intel_hdmi
->hdmi_reg
, temp
);
2030 intel_de_posting_read(dev_priv
, intel_hdmi
->hdmi_reg
);
2033 * HW workaround for IBX, we need to move the port
2034 * to transcoder A after disabling it to allow the
2035 * matching DP port to be enabled on transcoder A.
2037 if (HAS_PCH_IBX(dev_priv
) && crtc
->pipe
== PIPE_B
) {
2039 * We get CPU/PCH FIFO underruns on the other pipe when
2040 * doing the workaround. Sweep them under the rug.
2042 intel_set_cpu_fifo_underrun_reporting(dev_priv
, PIPE_A
, false);
2043 intel_set_pch_fifo_underrun_reporting(dev_priv
, PIPE_A
, false);
2045 temp
&= ~SDVO_PIPE_SEL_MASK
;
2046 temp
|= SDVO_ENABLE
| SDVO_PIPE_SEL(PIPE_A
);
2048 * HW workaround, need to write this twice for issue
2049 * that may result in first write getting masked.
2051 intel_de_write(dev_priv
, intel_hdmi
->hdmi_reg
, temp
);
2052 intel_de_posting_read(dev_priv
, intel_hdmi
->hdmi_reg
);
2053 intel_de_write(dev_priv
, intel_hdmi
->hdmi_reg
, temp
);
2054 intel_de_posting_read(dev_priv
, intel_hdmi
->hdmi_reg
);
2056 temp
&= ~SDVO_ENABLE
;
2057 intel_de_write(dev_priv
, intel_hdmi
->hdmi_reg
, temp
);
2058 intel_de_posting_read(dev_priv
, intel_hdmi
->hdmi_reg
);
2060 intel_wait_for_vblank_if_active(dev_priv
, PIPE_A
);
2061 intel_set_cpu_fifo_underrun_reporting(dev_priv
, PIPE_A
, true);
2062 intel_set_pch_fifo_underrun_reporting(dev_priv
, PIPE_A
, true);
2065 intel_dig_port
->set_infoframes(encoder
,
2067 old_crtc_state
, old_conn_state
);
2069 intel_dp_dual_mode_set_tmds_output(intel_hdmi
, false);
2072 static void g4x_disable_hdmi(struct intel_encoder
*encoder
,
2073 const struct intel_crtc_state
*old_crtc_state
,
2074 const struct drm_connector_state
*old_conn_state
)
2076 if (old_crtc_state
->has_audio
)
2077 intel_audio_codec_disable(encoder
,
2078 old_crtc_state
, old_conn_state
);
2080 intel_disable_hdmi(encoder
, old_crtc_state
, old_conn_state
);
2083 static void pch_disable_hdmi(struct intel_encoder
*encoder
,
2084 const struct intel_crtc_state
*old_crtc_state
,
2085 const struct drm_connector_state
*old_conn_state
)
2087 if (old_crtc_state
->has_audio
)
2088 intel_audio_codec_disable(encoder
,
2089 old_crtc_state
, old_conn_state
);
2092 static void pch_post_disable_hdmi(struct intel_encoder
*encoder
,
2093 const struct intel_crtc_state
*old_crtc_state
,
2094 const struct drm_connector_state
*old_conn_state
)
2096 intel_disable_hdmi(encoder
, old_crtc_state
, old_conn_state
);
2099 static int intel_hdmi_source_max_tmds_clock(struct intel_encoder
*encoder
)
2101 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
2102 int max_tmds_clock
, vbt_max_tmds_clock
;
2104 if (INTEL_GEN(dev_priv
) >= 10 || IS_GEMINILAKE(dev_priv
))
2105 max_tmds_clock
= 594000;
2106 else if (INTEL_GEN(dev_priv
) >= 8 || IS_HASWELL(dev_priv
))
2107 max_tmds_clock
= 300000;
2108 else if (INTEL_GEN(dev_priv
) >= 5)
2109 max_tmds_clock
= 225000;
2111 max_tmds_clock
= 165000;
2113 vbt_max_tmds_clock
= intel_bios_max_tmds_clock(encoder
);
2114 if (vbt_max_tmds_clock
)
2115 max_tmds_clock
= min(max_tmds_clock
, vbt_max_tmds_clock
);
2117 return max_tmds_clock
;
2120 static bool intel_has_hdmi_sink(struct intel_hdmi
*hdmi
,
2121 const struct drm_connector_state
*conn_state
)
2123 return hdmi
->has_hdmi_sink
&&
2124 READ_ONCE(to_intel_digital_connector_state(conn_state
)->force_audio
) != HDMI_AUDIO_OFF_DVI
;
2127 static int hdmi_port_clock_limit(struct intel_hdmi
*hdmi
,
2128 bool respect_downstream_limits
,
2131 struct intel_encoder
*encoder
= &hdmi_to_dig_port(hdmi
)->base
;
2132 int max_tmds_clock
= intel_hdmi_source_max_tmds_clock(encoder
);
2134 if (respect_downstream_limits
) {
2135 struct intel_connector
*connector
= hdmi
->attached_connector
;
2136 const struct drm_display_info
*info
= &connector
->base
.display_info
;
2138 if (hdmi
->dp_dual_mode
.max_tmds_clock
)
2139 max_tmds_clock
= min(max_tmds_clock
,
2140 hdmi
->dp_dual_mode
.max_tmds_clock
);
2142 if (info
->max_tmds_clock
)
2143 max_tmds_clock
= min(max_tmds_clock
,
2144 info
->max_tmds_clock
);
2145 else if (!has_hdmi_sink
)
2146 max_tmds_clock
= min(max_tmds_clock
, 165000);
2149 return max_tmds_clock
;
2152 static enum drm_mode_status
2153 hdmi_port_clock_valid(struct intel_hdmi
*hdmi
,
2154 int clock
, bool respect_downstream_limits
,
2157 struct drm_i915_private
*dev_priv
= to_i915(intel_hdmi_to_dev(hdmi
));
2160 return MODE_CLOCK_LOW
;
2161 if (clock
> hdmi_port_clock_limit(hdmi
, respect_downstream_limits
,
2163 return MODE_CLOCK_HIGH
;
2165 /* BXT DPLL can't generate 223-240 MHz */
2166 if (IS_GEN9_LP(dev_priv
) && clock
> 223333 && clock
< 240000)
2167 return MODE_CLOCK_RANGE
;
2169 /* CHV DPLL can't generate 216-240 MHz */
2170 if (IS_CHERRYVIEW(dev_priv
) && clock
> 216000 && clock
< 240000)
2171 return MODE_CLOCK_RANGE
;
2176 static enum drm_mode_status
2177 intel_hdmi_mode_valid(struct drm_connector
*connector
,
2178 struct drm_display_mode
*mode
)
2180 struct intel_hdmi
*hdmi
= intel_attached_hdmi(to_intel_connector(connector
));
2181 struct drm_device
*dev
= intel_hdmi_to_dev(hdmi
);
2182 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2183 enum drm_mode_status status
;
2184 int clock
= mode
->clock
;
2185 int max_dotclk
= to_i915(connector
->dev
)->max_dotclk_freq
;
2186 bool has_hdmi_sink
= intel_has_hdmi_sink(hdmi
, connector
->state
);
2188 if (mode
->flags
& DRM_MODE_FLAG_DBLSCAN
)
2189 return MODE_NO_DBLESCAN
;
2191 if ((mode
->flags
& DRM_MODE_FLAG_3D_MASK
) == DRM_MODE_FLAG_3D_FRAME_PACKING
)
2194 if (clock
> max_dotclk
)
2195 return MODE_CLOCK_HIGH
;
2197 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
2200 if (drm_mode_is_420_only(&connector
->display_info
, mode
))
2203 /* check if we can do 8bpc */
2204 status
= hdmi_port_clock_valid(hdmi
, clock
, true, has_hdmi_sink
);
2206 if (has_hdmi_sink
) {
2207 /* if we can't do 8bpc we may still be able to do 12bpc */
2208 if (status
!= MODE_OK
&& !HAS_GMCH(dev_priv
))
2209 status
= hdmi_port_clock_valid(hdmi
, clock
* 3 / 2,
2210 true, has_hdmi_sink
);
2212 /* if we can't do 8,12bpc we may still be able to do 10bpc */
2213 if (status
!= MODE_OK
&& INTEL_GEN(dev_priv
) >= 11)
2214 status
= hdmi_port_clock_valid(hdmi
, clock
* 5 / 4,
2215 true, has_hdmi_sink
);
2217 if (status
!= MODE_OK
)
2220 return intel_mode_valid_max_plane_size(dev_priv
, mode
);
2223 static bool hdmi_deep_color_possible(const struct intel_crtc_state
*crtc_state
,
2226 struct drm_i915_private
*dev_priv
=
2227 to_i915(crtc_state
->uapi
.crtc
->dev
);
2228 struct drm_atomic_state
*state
= crtc_state
->uapi
.state
;
2229 struct drm_connector_state
*connector_state
;
2230 struct drm_connector
*connector
;
2231 const struct drm_display_mode
*adjusted_mode
=
2232 &crtc_state
->hw
.adjusted_mode
;
2235 if (HAS_GMCH(dev_priv
))
2238 if (bpc
== 10 && INTEL_GEN(dev_priv
) < 11)
2241 if (crtc_state
->pipe_bpp
< bpc
* 3)
2244 if (!crtc_state
->has_hdmi_sink
)
2248 * HDMI deep color affects the clocks, so it's only possible
2249 * when not cloning with other encoder types.
2251 if (crtc_state
->output_types
!= 1 << INTEL_OUTPUT_HDMI
)
2254 for_each_new_connector_in_state(state
, connector
, connector_state
, i
) {
2255 const struct drm_display_info
*info
= &connector
->display_info
;
2257 if (connector_state
->crtc
!= crtc_state
->uapi
.crtc
)
2260 if (crtc_state
->output_format
== INTEL_OUTPUT_FORMAT_YCBCR420
) {
2261 const struct drm_hdmi_info
*hdmi
= &info
->hdmi
;
2263 if (bpc
== 12 && !(hdmi
->y420_dc_modes
&
2264 DRM_EDID_YCBCR420_DC_36
))
2266 else if (bpc
== 10 && !(hdmi
->y420_dc_modes
&
2267 DRM_EDID_YCBCR420_DC_30
))
2270 if (bpc
== 12 && !(info
->edid_hdmi_dc_modes
&
2271 DRM_EDID_HDMI_DC_36
))
2273 else if (bpc
== 10 && !(info
->edid_hdmi_dc_modes
&
2274 DRM_EDID_HDMI_DC_30
))
2279 /* Display Wa_1405510057:icl,ehl */
2280 if (crtc_state
->output_format
== INTEL_OUTPUT_FORMAT_YCBCR420
&&
2281 bpc
== 10 && IS_GEN(dev_priv
, 11) &&
2282 (adjusted_mode
->crtc_hblank_end
-
2283 adjusted_mode
->crtc_hblank_start
) % 8 == 2)
2290 intel_hdmi_ycbcr420_config(struct drm_connector
*connector
,
2291 struct intel_crtc_state
*config
)
2293 struct intel_crtc
*intel_crtc
= to_intel_crtc(config
->uapi
.crtc
);
2295 if (!connector
->ycbcr_420_allowed
) {
2296 DRM_ERROR("Platform doesn't support YCBCR420 output\n");
2300 config
->output_format
= INTEL_OUTPUT_FORMAT_YCBCR420
;
2302 /* YCBCR 420 output conversion needs a scaler */
2303 if (skl_update_scaler_crtc(config
)) {
2304 DRM_DEBUG_KMS("Scaler allocation for output failed\n");
2308 intel_pch_panel_fitting(intel_crtc
, config
,
2309 DRM_MODE_SCALE_FULLSCREEN
);
2314 static int intel_hdmi_port_clock(int clock
, int bpc
)
2317 * Need to adjust the port link by:
2321 return clock
* bpc
/ 8;
2324 static int intel_hdmi_compute_bpc(struct intel_encoder
*encoder
,
2325 struct intel_crtc_state
*crtc_state
,
2328 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
2331 for (bpc
= 12; bpc
>= 10; bpc
-= 2) {
2332 if (hdmi_deep_color_possible(crtc_state
, bpc
) &&
2333 hdmi_port_clock_valid(intel_hdmi
,
2334 intel_hdmi_port_clock(clock
, bpc
),
2335 true, crtc_state
->has_hdmi_sink
) == MODE_OK
)
2342 static int intel_hdmi_compute_clock(struct intel_encoder
*encoder
,
2343 struct intel_crtc_state
*crtc_state
)
2345 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
2346 const struct drm_display_mode
*adjusted_mode
=
2347 &crtc_state
->hw
.adjusted_mode
;
2348 int bpc
, clock
= adjusted_mode
->crtc_clock
;
2350 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
2353 /* YCBCR420 TMDS rate requirement is half the pixel clock */
2354 if (crtc_state
->output_format
== INTEL_OUTPUT_FORMAT_YCBCR420
)
2357 bpc
= intel_hdmi_compute_bpc(encoder
, crtc_state
, clock
);
2359 crtc_state
->port_clock
= intel_hdmi_port_clock(clock
, bpc
);
2362 * pipe_bpp could already be below 8bpc due to
2363 * FDI bandwidth constraints. We shouldn't bump it
2364 * back up to 8bpc in that case.
2366 if (crtc_state
->pipe_bpp
> bpc
* 3)
2367 crtc_state
->pipe_bpp
= bpc
* 3;
2369 DRM_DEBUG_KMS("picking %d bpc for HDMI output (pipe bpp: %d)\n",
2370 bpc
, crtc_state
->pipe_bpp
);
2372 if (hdmi_port_clock_valid(intel_hdmi
, crtc_state
->port_clock
,
2373 false, crtc_state
->has_hdmi_sink
) != MODE_OK
) {
2374 DRM_DEBUG_KMS("unsupported HDMI clock (%d kHz), rejecting mode\n",
2375 crtc_state
->port_clock
);
2382 static bool intel_hdmi_limited_color_range(const struct intel_crtc_state
*crtc_state
,
2383 const struct drm_connector_state
*conn_state
)
2385 const struct intel_digital_connector_state
*intel_conn_state
=
2386 to_intel_digital_connector_state(conn_state
);
2387 const struct drm_display_mode
*adjusted_mode
=
2388 &crtc_state
->hw
.adjusted_mode
;
2391 * Our YCbCr output is always limited range.
2392 * crtc_state->limited_color_range only applies to RGB,
2393 * and it must never be set for YCbCr or we risk setting
2394 * some conflicting bits in PIPECONF which will mess up
2395 * the colors on the monitor.
2397 if (crtc_state
->output_format
!= INTEL_OUTPUT_FORMAT_RGB
)
2400 if (intel_conn_state
->broadcast_rgb
== INTEL_BROADCAST_RGB_AUTO
) {
2401 /* See CEA-861-E - 5.1 Default Encoding Parameters */
2402 return crtc_state
->has_hdmi_sink
&&
2403 drm_default_rgb_quant_range(adjusted_mode
) ==
2404 HDMI_QUANTIZATION_RANGE_LIMITED
;
2406 return intel_conn_state
->broadcast_rgb
== INTEL_BROADCAST_RGB_LIMITED
;
2410 int intel_hdmi_compute_config(struct intel_encoder
*encoder
,
2411 struct intel_crtc_state
*pipe_config
,
2412 struct drm_connector_state
*conn_state
)
2414 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
2415 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
2416 struct drm_display_mode
*adjusted_mode
= &pipe_config
->hw
.adjusted_mode
;
2417 struct drm_connector
*connector
= conn_state
->connector
;
2418 struct drm_scdc
*scdc
= &connector
->display_info
.hdmi
.scdc
;
2419 struct intel_digital_connector_state
*intel_conn_state
=
2420 to_intel_digital_connector_state(conn_state
);
2423 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLSCAN
)
2426 pipe_config
->output_format
= INTEL_OUTPUT_FORMAT_RGB
;
2427 pipe_config
->has_hdmi_sink
= intel_has_hdmi_sink(intel_hdmi
,
2430 if (pipe_config
->has_hdmi_sink
)
2431 pipe_config
->has_infoframe
= true;
2433 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
2434 pipe_config
->pixel_multiplier
= 2;
2436 if (drm_mode_is_420_only(&connector
->display_info
, adjusted_mode
)) {
2437 if (!intel_hdmi_ycbcr420_config(connector
, pipe_config
)) {
2438 DRM_ERROR("Can't support YCBCR420 output\n");
2443 pipe_config
->limited_color_range
=
2444 intel_hdmi_limited_color_range(pipe_config
, conn_state
);
2446 if (HAS_PCH_SPLIT(dev_priv
) && !HAS_DDI(dev_priv
))
2447 pipe_config
->has_pch_encoder
= true;
2449 if (pipe_config
->has_hdmi_sink
) {
2450 if (intel_conn_state
->force_audio
== HDMI_AUDIO_AUTO
)
2451 pipe_config
->has_audio
= intel_hdmi
->has_audio
;
2453 pipe_config
->has_audio
=
2454 intel_conn_state
->force_audio
== HDMI_AUDIO_ON
;
2457 ret
= intel_hdmi_compute_clock(encoder
, pipe_config
);
2461 if (conn_state
->picture_aspect_ratio
)
2462 adjusted_mode
->picture_aspect_ratio
=
2463 conn_state
->picture_aspect_ratio
;
2465 pipe_config
->lane_count
= 4;
2467 if (scdc
->scrambling
.supported
&& (INTEL_GEN(dev_priv
) >= 10 ||
2468 IS_GEMINILAKE(dev_priv
))) {
2469 if (scdc
->scrambling
.low_rates
)
2470 pipe_config
->hdmi_scrambling
= true;
2472 if (pipe_config
->port_clock
> 340000) {
2473 pipe_config
->hdmi_scrambling
= true;
2474 pipe_config
->hdmi_high_tmds_clock_ratio
= true;
2478 intel_hdmi_compute_gcp_infoframe(encoder
, pipe_config
, conn_state
);
2480 if (!intel_hdmi_compute_avi_infoframe(encoder
, pipe_config
, conn_state
)) {
2481 DRM_DEBUG_KMS("bad AVI infoframe\n");
2485 if (!intel_hdmi_compute_spd_infoframe(encoder
, pipe_config
, conn_state
)) {
2486 DRM_DEBUG_KMS("bad SPD infoframe\n");
2490 if (!intel_hdmi_compute_hdmi_infoframe(encoder
, pipe_config
, conn_state
)) {
2491 DRM_DEBUG_KMS("bad HDMI infoframe\n");
2495 if (!intel_hdmi_compute_drm_infoframe(encoder
, pipe_config
, conn_state
)) {
2496 DRM_DEBUG_KMS("bad DRM infoframe\n");
2504 intel_hdmi_unset_edid(struct drm_connector
*connector
)
2506 struct intel_hdmi
*intel_hdmi
= intel_attached_hdmi(to_intel_connector(connector
));
2508 intel_hdmi
->has_hdmi_sink
= false;
2509 intel_hdmi
->has_audio
= false;
2511 intel_hdmi
->dp_dual_mode
.type
= DRM_DP_DUAL_MODE_NONE
;
2512 intel_hdmi
->dp_dual_mode
.max_tmds_clock
= 0;
2514 kfree(to_intel_connector(connector
)->detect_edid
);
2515 to_intel_connector(connector
)->detect_edid
= NULL
;
2519 intel_hdmi_dp_dual_mode_detect(struct drm_connector
*connector
, bool has_edid
)
2521 struct drm_i915_private
*dev_priv
= to_i915(connector
->dev
);
2522 struct intel_hdmi
*hdmi
= intel_attached_hdmi(to_intel_connector(connector
));
2523 enum port port
= hdmi_to_dig_port(hdmi
)->base
.port
;
2524 struct i2c_adapter
*adapter
=
2525 intel_gmbus_get_adapter(dev_priv
, hdmi
->ddc_bus
);
2526 enum drm_dp_dual_mode_type type
= drm_dp_dual_mode_detect(adapter
);
2529 * Type 1 DVI adaptors are not required to implement any
2530 * registers, so we can't always detect their presence.
2531 * Ideally we should be able to check the state of the
2532 * CONFIG1 pin, but no such luck on our hardware.
2534 * The only method left to us is to check the VBT to see
2535 * if the port is a dual mode capable DP port. But let's
2536 * only do that when we sucesfully read the EDID, to avoid
2537 * confusing log messages about DP dual mode adaptors when
2538 * there's nothing connected to the port.
2540 if (type
== DRM_DP_DUAL_MODE_UNKNOWN
) {
2541 /* An overridden EDID imply that we want this port for testing.
2542 * Make sure not to set limits for that port.
2544 if (has_edid
&& !connector
->override_edid
&&
2545 intel_bios_is_port_dp_dual_mode(dev_priv
, port
)) {
2546 DRM_DEBUG_KMS("Assuming DP dual mode adaptor presence based on VBT\n");
2547 type
= DRM_DP_DUAL_MODE_TYPE1_DVI
;
2549 type
= DRM_DP_DUAL_MODE_NONE
;
2553 if (type
== DRM_DP_DUAL_MODE_NONE
)
2556 hdmi
->dp_dual_mode
.type
= type
;
2557 hdmi
->dp_dual_mode
.max_tmds_clock
=
2558 drm_dp_dual_mode_max_tmds_clock(type
, adapter
);
2560 DRM_DEBUG_KMS("DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n",
2561 drm_dp_get_dual_mode_type_name(type
),
2562 hdmi
->dp_dual_mode
.max_tmds_clock
);
2566 intel_hdmi_set_edid(struct drm_connector
*connector
)
2568 struct drm_i915_private
*dev_priv
= to_i915(connector
->dev
);
2569 struct intel_hdmi
*intel_hdmi
= intel_attached_hdmi(to_intel_connector(connector
));
2570 intel_wakeref_t wakeref
;
2572 bool connected
= false;
2573 struct i2c_adapter
*i2c
;
2575 wakeref
= intel_display_power_get(dev_priv
, POWER_DOMAIN_GMBUS
);
2577 i2c
= intel_gmbus_get_adapter(dev_priv
, intel_hdmi
->ddc_bus
);
2579 edid
= drm_get_edid(connector
, i2c
);
2581 if (!edid
&& !intel_gmbus_is_forced_bit(i2c
)) {
2582 DRM_DEBUG_KMS("HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n");
2583 intel_gmbus_force_bit(i2c
, true);
2584 edid
= drm_get_edid(connector
, i2c
);
2585 intel_gmbus_force_bit(i2c
, false);
2588 intel_hdmi_dp_dual_mode_detect(connector
, edid
!= NULL
);
2590 intel_display_power_put(dev_priv
, POWER_DOMAIN_GMBUS
, wakeref
);
2592 to_intel_connector(connector
)->detect_edid
= edid
;
2593 if (edid
&& edid
->input
& DRM_EDID_INPUT_DIGITAL
) {
2594 intel_hdmi
->has_audio
= drm_detect_monitor_audio(edid
);
2595 intel_hdmi
->has_hdmi_sink
= drm_detect_hdmi_monitor(edid
);
2600 cec_notifier_set_phys_addr_from_edid(intel_hdmi
->cec_notifier
, edid
);
2605 static enum drm_connector_status
2606 intel_hdmi_detect(struct drm_connector
*connector
, bool force
)
2608 enum drm_connector_status status
= connector_status_disconnected
;
2609 struct drm_i915_private
*dev_priv
= to_i915(connector
->dev
);
2610 struct intel_hdmi
*intel_hdmi
= intel_attached_hdmi(to_intel_connector(connector
));
2611 struct intel_encoder
*encoder
= &hdmi_to_dig_port(intel_hdmi
)->base
;
2612 intel_wakeref_t wakeref
;
2614 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
2615 connector
->base
.id
, connector
->name
);
2617 wakeref
= intel_display_power_get(dev_priv
, POWER_DOMAIN_GMBUS
);
2619 if (INTEL_GEN(dev_priv
) >= 11 &&
2620 !intel_digital_port_connected(encoder
))
2623 intel_hdmi_unset_edid(connector
);
2625 if (intel_hdmi_set_edid(connector
))
2626 status
= connector_status_connected
;
2629 intel_display_power_put(dev_priv
, POWER_DOMAIN_GMBUS
, wakeref
);
2631 if (status
!= connector_status_connected
)
2632 cec_notifier_phys_addr_invalidate(intel_hdmi
->cec_notifier
);
2635 * Make sure the refs for power wells enabled during detect are
2636 * dropped to avoid a new detect cycle triggered by HPD polling.
2638 intel_display_power_flush_work(dev_priv
);
2644 intel_hdmi_force(struct drm_connector
*connector
)
2646 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
2647 connector
->base
.id
, connector
->name
);
2649 intel_hdmi_unset_edid(connector
);
2651 if (connector
->status
!= connector_status_connected
)
2654 intel_hdmi_set_edid(connector
);
2657 static int intel_hdmi_get_modes(struct drm_connector
*connector
)
2661 edid
= to_intel_connector(connector
)->detect_edid
;
2665 return intel_connector_update_modes(connector
, edid
);
2668 static void intel_hdmi_pre_enable(struct intel_encoder
*encoder
,
2669 const struct intel_crtc_state
*pipe_config
,
2670 const struct drm_connector_state
*conn_state
)
2672 struct intel_digital_port
*intel_dig_port
=
2673 enc_to_dig_port(encoder
);
2675 intel_hdmi_prepare(encoder
, pipe_config
);
2677 intel_dig_port
->set_infoframes(encoder
,
2678 pipe_config
->has_infoframe
,
2679 pipe_config
, conn_state
);
2682 static void vlv_hdmi_pre_enable(struct intel_encoder
*encoder
,
2683 const struct intel_crtc_state
*pipe_config
,
2684 const struct drm_connector_state
*conn_state
)
2686 struct intel_digital_port
*dport
= enc_to_dig_port(encoder
);
2687 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
2689 vlv_phy_pre_encoder_enable(encoder
, pipe_config
);
2692 vlv_set_phy_signal_level(encoder
, 0x2b245f5f, 0x00002000, 0x5578b83a,
2695 dport
->set_infoframes(encoder
,
2696 pipe_config
->has_infoframe
,
2697 pipe_config
, conn_state
);
2699 g4x_enable_hdmi(encoder
, pipe_config
, conn_state
);
2701 vlv_wait_port_ready(dev_priv
, dport
, 0x0);
2704 static void vlv_hdmi_pre_pll_enable(struct intel_encoder
*encoder
,
2705 const struct intel_crtc_state
*pipe_config
,
2706 const struct drm_connector_state
*conn_state
)
2708 intel_hdmi_prepare(encoder
, pipe_config
);
2710 vlv_phy_pre_pll_enable(encoder
, pipe_config
);
2713 static void chv_hdmi_pre_pll_enable(struct intel_encoder
*encoder
,
2714 const struct intel_crtc_state
*pipe_config
,
2715 const struct drm_connector_state
*conn_state
)
2717 intel_hdmi_prepare(encoder
, pipe_config
);
2719 chv_phy_pre_pll_enable(encoder
, pipe_config
);
2722 static void chv_hdmi_post_pll_disable(struct intel_encoder
*encoder
,
2723 const struct intel_crtc_state
*old_crtc_state
,
2724 const struct drm_connector_state
*old_conn_state
)
2726 chv_phy_post_pll_disable(encoder
, old_crtc_state
);
2729 static void vlv_hdmi_post_disable(struct intel_encoder
*encoder
,
2730 const struct intel_crtc_state
*old_crtc_state
,
2731 const struct drm_connector_state
*old_conn_state
)
2733 /* Reset lanes to avoid HDMI flicker (VLV w/a) */
2734 vlv_phy_reset_lanes(encoder
, old_crtc_state
);
2737 static void chv_hdmi_post_disable(struct intel_encoder
*encoder
,
2738 const struct intel_crtc_state
*old_crtc_state
,
2739 const struct drm_connector_state
*old_conn_state
)
2741 struct drm_device
*dev
= encoder
->base
.dev
;
2742 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2744 vlv_dpio_get(dev_priv
);
2746 /* Assert data lane reset */
2747 chv_data_lane_soft_reset(encoder
, old_crtc_state
, true);
2749 vlv_dpio_put(dev_priv
);
2752 static void chv_hdmi_pre_enable(struct intel_encoder
*encoder
,
2753 const struct intel_crtc_state
*pipe_config
,
2754 const struct drm_connector_state
*conn_state
)
2756 struct intel_digital_port
*dport
= enc_to_dig_port(encoder
);
2757 struct drm_device
*dev
= encoder
->base
.dev
;
2758 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2760 chv_phy_pre_encoder_enable(encoder
, pipe_config
);
2762 /* FIXME: Program the support xxx V-dB */
2764 chv_set_phy_signal_level(encoder
, 128, 102, false);
2766 dport
->set_infoframes(encoder
,
2767 pipe_config
->has_infoframe
,
2768 pipe_config
, conn_state
);
2770 g4x_enable_hdmi(encoder
, pipe_config
, conn_state
);
2772 vlv_wait_port_ready(dev_priv
, dport
, 0x0);
2774 /* Second common lane will stay alive on its own now */
2775 chv_phy_release_cl2_override(encoder
);
2778 static struct i2c_adapter
*
2779 intel_hdmi_get_i2c_adapter(struct drm_connector
*connector
)
2781 struct drm_i915_private
*dev_priv
= to_i915(connector
->dev
);
2782 struct intel_hdmi
*intel_hdmi
= intel_attached_hdmi(to_intel_connector(connector
));
2784 return intel_gmbus_get_adapter(dev_priv
, intel_hdmi
->ddc_bus
);
2787 static void intel_hdmi_create_i2c_symlink(struct drm_connector
*connector
)
2789 struct i2c_adapter
*adapter
= intel_hdmi_get_i2c_adapter(connector
);
2790 struct kobject
*i2c_kobj
= &adapter
->dev
.kobj
;
2791 struct kobject
*connector_kobj
= &connector
->kdev
->kobj
;
2794 ret
= sysfs_create_link(connector_kobj
, i2c_kobj
, i2c_kobj
->name
);
2796 DRM_ERROR("Failed to create i2c symlink (%d)\n", ret
);
2799 static void intel_hdmi_remove_i2c_symlink(struct drm_connector
*connector
)
2801 struct i2c_adapter
*adapter
= intel_hdmi_get_i2c_adapter(connector
);
2802 struct kobject
*i2c_kobj
= &adapter
->dev
.kobj
;
2803 struct kobject
*connector_kobj
= &connector
->kdev
->kobj
;
2805 sysfs_remove_link(connector_kobj
, i2c_kobj
->name
);
2809 intel_hdmi_connector_register(struct drm_connector
*connector
)
2813 ret
= intel_connector_register(connector
);
2817 intel_connector_debugfs_add(connector
);
2819 intel_hdmi_create_i2c_symlink(connector
);
2824 static void intel_hdmi_destroy(struct drm_connector
*connector
)
2826 struct cec_notifier
*n
= intel_attached_hdmi(to_intel_connector(connector
))->cec_notifier
;
2828 cec_notifier_conn_unregister(n
);
2830 intel_connector_destroy(connector
);
2833 static void intel_hdmi_connector_unregister(struct drm_connector
*connector
)
2835 intel_hdmi_remove_i2c_symlink(connector
);
2837 intel_connector_unregister(connector
);
2840 static const struct drm_connector_funcs intel_hdmi_connector_funcs
= {
2841 .detect
= intel_hdmi_detect
,
2842 .force
= intel_hdmi_force
,
2843 .fill_modes
= drm_helper_probe_single_connector_modes
,
2844 .atomic_get_property
= intel_digital_connector_atomic_get_property
,
2845 .atomic_set_property
= intel_digital_connector_atomic_set_property
,
2846 .late_register
= intel_hdmi_connector_register
,
2847 .early_unregister
= intel_hdmi_connector_unregister
,
2848 .destroy
= intel_hdmi_destroy
,
2849 .atomic_destroy_state
= drm_atomic_helper_connector_destroy_state
,
2850 .atomic_duplicate_state
= intel_digital_connector_duplicate_state
,
2853 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs
= {
2854 .get_modes
= intel_hdmi_get_modes
,
2855 .mode_valid
= intel_hdmi_mode_valid
,
2856 .atomic_check
= intel_digital_connector_atomic_check
,
2859 static const struct drm_encoder_funcs intel_hdmi_enc_funcs
= {
2860 .destroy
= intel_encoder_destroy
,
2864 intel_hdmi_add_properties(struct intel_hdmi
*intel_hdmi
, struct drm_connector
*connector
)
2866 struct drm_i915_private
*dev_priv
= to_i915(connector
->dev
);
2867 struct intel_digital_port
*intel_dig_port
=
2868 hdmi_to_dig_port(intel_hdmi
);
2870 intel_attach_force_audio_property(connector
);
2871 intel_attach_broadcast_rgb_property(connector
);
2872 intel_attach_aspect_ratio_property(connector
);
2875 * Attach Colorspace property for Non LSPCON based device
2876 * ToDo: This needs to be extended for LSPCON implementation
2877 * as well. Will be implemented separately.
2879 if (!intel_dig_port
->lspcon
.active
)
2880 intel_attach_colorspace_property(connector
);
2882 drm_connector_attach_content_type_property(connector
);
2884 if (INTEL_GEN(dev_priv
) >= 10 || IS_GEMINILAKE(dev_priv
))
2885 drm_object_attach_property(&connector
->base
,
2886 connector
->dev
->mode_config
.hdr_output_metadata_property
, 0);
2888 if (!HAS_GMCH(dev_priv
))
2889 drm_connector_attach_max_bpc_property(connector
, 8, 12);
2893 * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup
2894 * @encoder: intel_encoder
2895 * @connector: drm_connector
2896 * @high_tmds_clock_ratio = bool to indicate if the function needs to set
2897 * or reset the high tmds clock ratio for scrambling
2898 * @scrambling: bool to Indicate if the function needs to set or reset
2901 * This function handles scrambling on HDMI 2.0 capable sinks.
2902 * If required clock rate is > 340 Mhz && scrambling is supported by sink
2903 * it enables scrambling. This should be called before enabling the HDMI
2904 * 2.0 port, as the sink can choose to disable the scrambling if it doesn't
2905 * detect a scrambled clock within 100 ms.
2908 * True on success, false on failure.
2910 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder
*encoder
,
2911 struct drm_connector
*connector
,
2912 bool high_tmds_clock_ratio
,
2915 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
2916 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
2917 struct drm_scrambling
*sink_scrambling
=
2918 &connector
->display_info
.hdmi
.scdc
.scrambling
;
2919 struct i2c_adapter
*adapter
=
2920 intel_gmbus_get_adapter(dev_priv
, intel_hdmi
->ddc_bus
);
2922 if (!sink_scrambling
->supported
)
2925 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n",
2926 connector
->base
.id
, connector
->name
,
2927 yesno(scrambling
), high_tmds_clock_ratio
? 40 : 10);
2929 /* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */
2930 return drm_scdc_set_high_tmds_clock_ratio(adapter
,
2931 high_tmds_clock_ratio
) &&
2932 drm_scdc_set_scrambling(adapter
, scrambling
);
2935 static u8
chv_port_to_ddc_pin(struct drm_i915_private
*dev_priv
, enum port port
)
2941 ddc_pin
= GMBUS_PIN_DPB
;
2944 ddc_pin
= GMBUS_PIN_DPC
;
2947 ddc_pin
= GMBUS_PIN_DPD_CHV
;
2951 ddc_pin
= GMBUS_PIN_DPB
;
2957 static u8
bxt_port_to_ddc_pin(struct drm_i915_private
*dev_priv
, enum port port
)
2963 ddc_pin
= GMBUS_PIN_1_BXT
;
2966 ddc_pin
= GMBUS_PIN_2_BXT
;
2970 ddc_pin
= GMBUS_PIN_1_BXT
;
2976 static u8
cnp_port_to_ddc_pin(struct drm_i915_private
*dev_priv
,
2983 ddc_pin
= GMBUS_PIN_1_BXT
;
2986 ddc_pin
= GMBUS_PIN_2_BXT
;
2989 ddc_pin
= GMBUS_PIN_4_CNP
;
2992 ddc_pin
= GMBUS_PIN_3_BXT
;
2996 ddc_pin
= GMBUS_PIN_1_BXT
;
3002 static u8
icl_port_to_ddc_pin(struct drm_i915_private
*dev_priv
, enum port port
)
3004 enum phy phy
= intel_port_to_phy(dev_priv
, port
);
3006 if (intel_phy_is_combo(dev_priv
, phy
))
3007 return GMBUS_PIN_1_BXT
+ port
;
3008 else if (intel_phy_is_tc(dev_priv
, phy
))
3009 return GMBUS_PIN_9_TC1_ICP
+ intel_port_to_tc(dev_priv
, port
);
3011 drm_WARN(&dev_priv
->drm
, 1, "Unknown port:%c\n", port_name(port
));
3012 return GMBUS_PIN_2_BXT
;
3015 static u8
mcc_port_to_ddc_pin(struct drm_i915_private
*dev_priv
, enum port port
)
3017 enum phy phy
= intel_port_to_phy(dev_priv
, port
);
3022 ddc_pin
= GMBUS_PIN_1_BXT
;
3025 ddc_pin
= GMBUS_PIN_2_BXT
;
3028 ddc_pin
= GMBUS_PIN_9_TC1_ICP
;
3032 ddc_pin
= GMBUS_PIN_1_BXT
;
3038 static u8
g4x_port_to_ddc_pin(struct drm_i915_private
*dev_priv
,
3045 ddc_pin
= GMBUS_PIN_DPB
;
3048 ddc_pin
= GMBUS_PIN_DPC
;
3051 ddc_pin
= GMBUS_PIN_DPD
;
3055 ddc_pin
= GMBUS_PIN_DPB
;
3061 static u8
intel_hdmi_ddc_pin(struct intel_encoder
*encoder
)
3063 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
3064 enum port port
= encoder
->port
;
3067 ddc_pin
= intel_bios_alternate_ddc_pin(encoder
);
3069 DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (VBT)\n",
3070 ddc_pin
, port_name(port
));
3074 if (HAS_PCH_MCC(dev_priv
))
3075 ddc_pin
= mcc_port_to_ddc_pin(dev_priv
, port
);
3076 else if (INTEL_PCH_TYPE(dev_priv
) >= PCH_ICP
)
3077 ddc_pin
= icl_port_to_ddc_pin(dev_priv
, port
);
3078 else if (HAS_PCH_CNP(dev_priv
))
3079 ddc_pin
= cnp_port_to_ddc_pin(dev_priv
, port
);
3080 else if (IS_GEN9_LP(dev_priv
))
3081 ddc_pin
= bxt_port_to_ddc_pin(dev_priv
, port
);
3082 else if (IS_CHERRYVIEW(dev_priv
))
3083 ddc_pin
= chv_port_to_ddc_pin(dev_priv
, port
);
3085 ddc_pin
= g4x_port_to_ddc_pin(dev_priv
, port
);
3087 DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (platform default)\n",
3088 ddc_pin
, port_name(port
));
3093 void intel_infoframe_init(struct intel_digital_port
*intel_dig_port
)
3095 struct drm_i915_private
*dev_priv
=
3096 to_i915(intel_dig_port
->base
.base
.dev
);
3098 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
3099 intel_dig_port
->write_infoframe
= vlv_write_infoframe
;
3100 intel_dig_port
->read_infoframe
= vlv_read_infoframe
;
3101 intel_dig_port
->set_infoframes
= vlv_set_infoframes
;
3102 intel_dig_port
->infoframes_enabled
= vlv_infoframes_enabled
;
3103 } else if (IS_G4X(dev_priv
)) {
3104 intel_dig_port
->write_infoframe
= g4x_write_infoframe
;
3105 intel_dig_port
->read_infoframe
= g4x_read_infoframe
;
3106 intel_dig_port
->set_infoframes
= g4x_set_infoframes
;
3107 intel_dig_port
->infoframes_enabled
= g4x_infoframes_enabled
;
3108 } else if (HAS_DDI(dev_priv
)) {
3109 if (intel_dig_port
->lspcon
.active
) {
3110 intel_dig_port
->write_infoframe
= lspcon_write_infoframe
;
3111 intel_dig_port
->read_infoframe
= lspcon_read_infoframe
;
3112 intel_dig_port
->set_infoframes
= lspcon_set_infoframes
;
3113 intel_dig_port
->infoframes_enabled
= lspcon_infoframes_enabled
;
3115 intel_dig_port
->write_infoframe
= hsw_write_infoframe
;
3116 intel_dig_port
->read_infoframe
= hsw_read_infoframe
;
3117 intel_dig_port
->set_infoframes
= hsw_set_infoframes
;
3118 intel_dig_port
->infoframes_enabled
= hsw_infoframes_enabled
;
3120 } else if (HAS_PCH_IBX(dev_priv
)) {
3121 intel_dig_port
->write_infoframe
= ibx_write_infoframe
;
3122 intel_dig_port
->read_infoframe
= ibx_read_infoframe
;
3123 intel_dig_port
->set_infoframes
= ibx_set_infoframes
;
3124 intel_dig_port
->infoframes_enabled
= ibx_infoframes_enabled
;
3126 intel_dig_port
->write_infoframe
= cpt_write_infoframe
;
3127 intel_dig_port
->read_infoframe
= cpt_read_infoframe
;
3128 intel_dig_port
->set_infoframes
= cpt_set_infoframes
;
3129 intel_dig_port
->infoframes_enabled
= cpt_infoframes_enabled
;
3133 void intel_hdmi_init_connector(struct intel_digital_port
*intel_dig_port
,
3134 struct intel_connector
*intel_connector
)
3136 struct drm_connector
*connector
= &intel_connector
->base
;
3137 struct intel_hdmi
*intel_hdmi
= &intel_dig_port
->hdmi
;
3138 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
3139 struct drm_device
*dev
= intel_encoder
->base
.dev
;
3140 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3141 struct i2c_adapter
*ddc
;
3142 enum port port
= intel_encoder
->port
;
3143 struct cec_connector_info conn_info
;
3145 DRM_DEBUG_KMS("Adding HDMI connector on [ENCODER:%d:%s]\n",
3146 intel_encoder
->base
.base
.id
, intel_encoder
->base
.name
);
3148 if (INTEL_GEN(dev_priv
) < 12 && drm_WARN_ON(dev
, port
== PORT_A
))
3151 if (drm_WARN(dev
, intel_dig_port
->max_lanes
< 4,
3152 "Not enough lanes (%d) for HDMI on [ENCODER:%d:%s]\n",
3153 intel_dig_port
->max_lanes
, intel_encoder
->base
.base
.id
,
3154 intel_encoder
->base
.name
))
3157 intel_hdmi
->ddc_bus
= intel_hdmi_ddc_pin(intel_encoder
);
3158 ddc
= intel_gmbus_get_adapter(dev_priv
, intel_hdmi
->ddc_bus
);
3160 drm_connector_init_with_ddc(dev
, connector
,
3161 &intel_hdmi_connector_funcs
,
3162 DRM_MODE_CONNECTOR_HDMIA
,
3164 drm_connector_helper_add(connector
, &intel_hdmi_connector_helper_funcs
);
3166 connector
->interlace_allowed
= 1;
3167 connector
->doublescan_allowed
= 0;
3168 connector
->stereo_allowed
= 1;
3170 if (INTEL_GEN(dev_priv
) >= 10 || IS_GEMINILAKE(dev_priv
))
3171 connector
->ycbcr_420_allowed
= true;
3173 intel_encoder
->hpd_pin
= intel_hpd_pin_default(dev_priv
, port
);
3174 intel_connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
3176 if (HAS_DDI(dev_priv
))
3177 intel_connector
->get_hw_state
= intel_ddi_connector_get_hw_state
;
3179 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
3181 intel_hdmi_add_properties(intel_hdmi
, connector
);
3183 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
3184 intel_hdmi
->attached_connector
= intel_connector
;
3186 if (is_hdcp_supported(dev_priv
, port
)) {
3187 int ret
= intel_hdcp_init(intel_connector
,
3188 &intel_hdmi_hdcp_shim
);
3190 DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
3193 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3194 * 0xd. Failure to do so will result in spurious interrupts being
3195 * generated on the port when a cable is not attached.
3197 if (IS_G45(dev_priv
)) {
3198 u32 temp
= intel_de_read(dev_priv
, PEG_BAND_GAP_DATA
);
3199 intel_de_write(dev_priv
, PEG_BAND_GAP_DATA
,
3200 (temp
& ~0xf) | 0xd);
3203 cec_fill_conn_info_from_drm(&conn_info
, connector
);
3205 intel_hdmi
->cec_notifier
=
3206 cec_notifier_conn_register(dev
->dev
, port_identifier(port
),
3208 if (!intel_hdmi
->cec_notifier
)
3209 DRM_DEBUG_KMS("CEC notifier get failed\n");
3212 static enum intel_hotplug_state
3213 intel_hdmi_hotplug(struct intel_encoder
*encoder
,
3214 struct intel_connector
*connector
, bool irq_received
)
3216 enum intel_hotplug_state state
;
3218 state
= intel_encoder_hotplug(encoder
, connector
, irq_received
);
3221 * On many platforms the HDMI live state signal is known to be
3222 * unreliable, so we can't use it to detect if a sink is connected or
3223 * not. Instead we detect if it's connected based on whether we can
3224 * read the EDID or not. That in turn has a problem during disconnect,
3225 * since the HPD interrupt may be raised before the DDC lines get
3226 * disconnected (due to how the required length of DDC vs. HPD
3227 * connector pins are specified) and so we'll still be able to get a
3228 * valid EDID. To solve this schedule another detection cycle if this
3229 * time around we didn't detect any change in the sink's connection
3232 if (state
== INTEL_HOTPLUG_UNCHANGED
&& irq_received
)
3233 state
= INTEL_HOTPLUG_RETRY
;
3238 void intel_hdmi_init(struct drm_i915_private
*dev_priv
,
3239 i915_reg_t hdmi_reg
, enum port port
)
3241 struct intel_digital_port
*intel_dig_port
;
3242 struct intel_encoder
*intel_encoder
;
3243 struct intel_connector
*intel_connector
;
3245 intel_dig_port
= kzalloc(sizeof(*intel_dig_port
), GFP_KERNEL
);
3246 if (!intel_dig_port
)
3249 intel_connector
= intel_connector_alloc();
3250 if (!intel_connector
) {
3251 kfree(intel_dig_port
);
3255 intel_encoder
= &intel_dig_port
->base
;
3257 drm_encoder_init(&dev_priv
->drm
, &intel_encoder
->base
,
3258 &intel_hdmi_enc_funcs
, DRM_MODE_ENCODER_TMDS
,
3259 "HDMI %c", port_name(port
));
3261 intel_encoder
->hotplug
= intel_hdmi_hotplug
;
3262 intel_encoder
->compute_config
= intel_hdmi_compute_config
;
3263 if (HAS_PCH_SPLIT(dev_priv
)) {
3264 intel_encoder
->disable
= pch_disable_hdmi
;
3265 intel_encoder
->post_disable
= pch_post_disable_hdmi
;
3267 intel_encoder
->disable
= g4x_disable_hdmi
;
3269 intel_encoder
->get_hw_state
= intel_hdmi_get_hw_state
;
3270 intel_encoder
->get_config
= intel_hdmi_get_config
;
3271 if (IS_CHERRYVIEW(dev_priv
)) {
3272 intel_encoder
->pre_pll_enable
= chv_hdmi_pre_pll_enable
;
3273 intel_encoder
->pre_enable
= chv_hdmi_pre_enable
;
3274 intel_encoder
->enable
= vlv_enable_hdmi
;
3275 intel_encoder
->post_disable
= chv_hdmi_post_disable
;
3276 intel_encoder
->post_pll_disable
= chv_hdmi_post_pll_disable
;
3277 } else if (IS_VALLEYVIEW(dev_priv
)) {
3278 intel_encoder
->pre_pll_enable
= vlv_hdmi_pre_pll_enable
;
3279 intel_encoder
->pre_enable
= vlv_hdmi_pre_enable
;
3280 intel_encoder
->enable
= vlv_enable_hdmi
;
3281 intel_encoder
->post_disable
= vlv_hdmi_post_disable
;
3283 intel_encoder
->pre_enable
= intel_hdmi_pre_enable
;
3284 if (HAS_PCH_CPT(dev_priv
))
3285 intel_encoder
->enable
= cpt_enable_hdmi
;
3286 else if (HAS_PCH_IBX(dev_priv
))
3287 intel_encoder
->enable
= ibx_enable_hdmi
;
3289 intel_encoder
->enable
= g4x_enable_hdmi
;
3292 intel_encoder
->type
= INTEL_OUTPUT_HDMI
;
3293 intel_encoder
->power_domain
= intel_port_to_power_domain(port
);
3294 intel_encoder
->port
= port
;
3295 if (IS_CHERRYVIEW(dev_priv
)) {
3297 intel_encoder
->pipe_mask
= BIT(PIPE_C
);
3299 intel_encoder
->pipe_mask
= BIT(PIPE_A
) | BIT(PIPE_B
);
3301 intel_encoder
->pipe_mask
= ~0;
3303 intel_encoder
->cloneable
= 1 << INTEL_OUTPUT_ANALOG
;
3305 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
3306 * to work on real hardware. And since g4x can send infoframes to
3307 * only one port anyway, nothing is lost by allowing it.
3309 if (IS_G4X(dev_priv
))
3310 intel_encoder
->cloneable
|= 1 << INTEL_OUTPUT_HDMI
;
3312 intel_dig_port
->hdmi
.hdmi_reg
= hdmi_reg
;
3313 intel_dig_port
->dp
.output_reg
= INVALID_MMIO_REG
;
3314 intel_dig_port
->max_lanes
= 4;
3316 intel_infoframe_init(intel_dig_port
);
3318 intel_dig_port
->aux_ch
= intel_bios_port_aux_ch(dev_priv
, port
);
3319 intel_hdmi_init_connector(intel_dig_port
, intel_connector
);