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Merge v6.8-rc6 into drm-next
[thirdparty/linux.git] / drivers / gpu / drm / i915 / display / intel_sdvo.c
1 /*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2007 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 */
28
29 #include <linux/delay.h>
30 #include <linux/export.h>
31 #include <linux/i2c.h>
32 #include <linux/slab.h>
33
34 #include <drm/display/drm_hdmi_helper.h>
35 #include <drm/drm_atomic_helper.h>
36 #include <drm/drm_crtc.h>
37 #include <drm/drm_edid.h>
38 #include <drm/drm_eld.h>
39
40 #include "i915_drv.h"
41 #include "i915_reg.h"
42 #include "intel_atomic.h"
43 #include "intel_audio.h"
44 #include "intel_connector.h"
45 #include "intel_crtc.h"
46 #include "intel_de.h"
47 #include "intel_display_driver.h"
48 #include "intel_display_types.h"
49 #include "intel_fdi.h"
50 #include "intel_fifo_underrun.h"
51 #include "intel_gmbus.h"
52 #include "intel_hdmi.h"
53 #include "intel_hotplug.h"
54 #include "intel_panel.h"
55 #include "intel_sdvo.h"
56 #include "intel_sdvo_regs.h"
57
58 #define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
59 #define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
60 #define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
61 #define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0)
62
63 #define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK | SDVO_TV_MASK)
64
65 #define IS_TV(c) ((c)->output_flag & SDVO_TV_MASK)
66 #define IS_TMDS(c) ((c)->output_flag & SDVO_TMDS_MASK)
67 #define IS_LVDS(c) ((c)->output_flag & SDVO_LVDS_MASK)
68 #define IS_TV_OR_LVDS(c) ((c)->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
69 #define IS_DIGITAL(c) ((c)->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK))
70
71 #define HAS_DDC(c) ((c)->output_flag & (SDVO_RGB_MASK | SDVO_TMDS_MASK | \
72 SDVO_LVDS_MASK))
73
74 static const char * const tv_format_names[] = {
75 "NTSC_M" , "NTSC_J" , "NTSC_443",
76 "PAL_B" , "PAL_D" , "PAL_G" ,
77 "PAL_H" , "PAL_I" , "PAL_M" ,
78 "PAL_N" , "PAL_NC" , "PAL_60" ,
79 "SECAM_B" , "SECAM_D" , "SECAM_G" ,
80 "SECAM_K" , "SECAM_K1", "SECAM_L" ,
81 "SECAM_60"
82 };
83
84 #define TV_FORMAT_NUM ARRAY_SIZE(tv_format_names)
85
86 struct intel_sdvo;
87
88 struct intel_sdvo_ddc {
89 struct i2c_adapter ddc;
90 struct intel_sdvo *sdvo;
91 u8 ddc_bus;
92 };
93
94 struct intel_sdvo {
95 struct intel_encoder base;
96
97 struct i2c_adapter *i2c;
98 u8 slave_addr;
99
100 struct intel_sdvo_ddc ddc[3];
101
102 /* Register for the SDVO device: SDVOB or SDVOC */
103 i915_reg_t sdvo_reg;
104
105 /*
106 * Capabilities of the SDVO device returned by
107 * intel_sdvo_get_capabilities()
108 */
109 struct intel_sdvo_caps caps;
110
111 u8 colorimetry_cap;
112
113 /* Pixel clock limitations reported by the SDVO device, in kHz */
114 int pixel_clock_min, pixel_clock_max;
115
116 /*
117 * Hotplug activation bits for this device
118 */
119 u16 hotplug_active;
120
121 /*
122 * the sdvo flag gets lost in round trip: dtd->adjusted_mode->dtd
123 */
124 u8 dtd_sdvo_flags;
125 };
126
127 struct intel_sdvo_connector {
128 struct intel_connector base;
129
130 /* Mark the type of connector */
131 u16 output_flag;
132
133 /* This contains all current supported TV format */
134 u8 tv_format_supported[TV_FORMAT_NUM];
135 int format_supported_num;
136 struct drm_property *tv_format;
137
138 /* add the property for the SDVO-TV */
139 struct drm_property *left;
140 struct drm_property *right;
141 struct drm_property *top;
142 struct drm_property *bottom;
143 struct drm_property *hpos;
144 struct drm_property *vpos;
145 struct drm_property *contrast;
146 struct drm_property *saturation;
147 struct drm_property *hue;
148 struct drm_property *sharpness;
149 struct drm_property *flicker_filter;
150 struct drm_property *flicker_filter_adaptive;
151 struct drm_property *flicker_filter_2d;
152 struct drm_property *tv_chroma_filter;
153 struct drm_property *tv_luma_filter;
154 struct drm_property *dot_crawl;
155
156 /* add the property for the SDVO-TV/LVDS */
157 struct drm_property *brightness;
158
159 /* this is to get the range of margin.*/
160 u32 max_hscan, max_vscan;
161
162 /**
163 * This is set if we treat the device as HDMI, instead of DVI.
164 */
165 bool is_hdmi;
166 };
167
168 struct intel_sdvo_connector_state {
169 /* base.base: tv.saturation/contrast/hue/brightness */
170 struct intel_digital_connector_state base;
171
172 struct {
173 unsigned overscan_h, overscan_v, hpos, vpos, sharpness;
174 unsigned flicker_filter, flicker_filter_2d, flicker_filter_adaptive;
175 unsigned chroma_filter, luma_filter, dot_crawl;
176 } tv;
177 };
178
179 static struct intel_sdvo *to_sdvo(struct intel_encoder *encoder)
180 {
181 return container_of(encoder, struct intel_sdvo, base);
182 }
183
184 static struct intel_sdvo *intel_attached_sdvo(struct intel_connector *connector)
185 {
186 return to_sdvo(intel_attached_encoder(connector));
187 }
188
189 static struct intel_sdvo_connector *
190 to_intel_sdvo_connector(struct drm_connector *connector)
191 {
192 return container_of(connector, struct intel_sdvo_connector, base.base);
193 }
194
195 #define to_intel_sdvo_connector_state(conn_state) \
196 container_of((conn_state), struct intel_sdvo_connector_state, base.base)
197
198 static bool
199 intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo);
200 static bool
201 intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
202 struct intel_sdvo_connector *intel_sdvo_connector,
203 int type);
204 static bool
205 intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
206 struct intel_sdvo_connector *intel_sdvo_connector);
207
208 /*
209 * Writes the SDVOB or SDVOC with the given value, but always writes both
210 * SDVOB and SDVOC to work around apparent hardware issues (according to
211 * comments in the BIOS).
212 */
213 static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
214 {
215 struct drm_device *dev = intel_sdvo->base.base.dev;
216 struct drm_i915_private *dev_priv = to_i915(dev);
217 u32 bval = val, cval = val;
218 int i;
219
220 if (HAS_PCH_SPLIT(dev_priv)) {
221 intel_de_write(dev_priv, intel_sdvo->sdvo_reg, val);
222 intel_de_posting_read(dev_priv, intel_sdvo->sdvo_reg);
223 /*
224 * HW workaround, need to write this twice for issue
225 * that may result in first write getting masked.
226 */
227 if (HAS_PCH_IBX(dev_priv)) {
228 intel_de_write(dev_priv, intel_sdvo->sdvo_reg, val);
229 intel_de_posting_read(dev_priv, intel_sdvo->sdvo_reg);
230 }
231 return;
232 }
233
234 if (intel_sdvo->base.port == PORT_B)
235 cval = intel_de_read(dev_priv, GEN3_SDVOC);
236 else
237 bval = intel_de_read(dev_priv, GEN3_SDVOB);
238
239 /*
240 * Write the registers twice for luck. Sometimes,
241 * writing them only once doesn't appear to 'stick'.
242 * The BIOS does this too. Yay, magic
243 */
244 for (i = 0; i < 2; i++) {
245 intel_de_write(dev_priv, GEN3_SDVOB, bval);
246 intel_de_posting_read(dev_priv, GEN3_SDVOB);
247
248 intel_de_write(dev_priv, GEN3_SDVOC, cval);
249 intel_de_posting_read(dev_priv, GEN3_SDVOC);
250 }
251 }
252
253 static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
254 {
255 struct i2c_msg msgs[] = {
256 {
257 .addr = intel_sdvo->slave_addr,
258 .flags = 0,
259 .len = 1,
260 .buf = &addr,
261 },
262 {
263 .addr = intel_sdvo->slave_addr,
264 .flags = I2C_M_RD,
265 .len = 1,
266 .buf = ch,
267 }
268 };
269 int ret;
270
271 if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2)
272 return true;
273
274 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
275 return false;
276 }
277
278 #define SDVO_CMD_NAME_ENTRY(cmd_) { .cmd = SDVO_CMD_ ## cmd_, .name = #cmd_ }
279
280 /** Mapping of command numbers to names, for debug output */
281 static const struct {
282 u8 cmd;
283 const char *name;
284 } __packed sdvo_cmd_names[] = {
285 SDVO_CMD_NAME_ENTRY(RESET),
286 SDVO_CMD_NAME_ENTRY(GET_DEVICE_CAPS),
287 SDVO_CMD_NAME_ENTRY(GET_FIRMWARE_REV),
288 SDVO_CMD_NAME_ENTRY(GET_TRAINED_INPUTS),
289 SDVO_CMD_NAME_ENTRY(GET_ACTIVE_OUTPUTS),
290 SDVO_CMD_NAME_ENTRY(SET_ACTIVE_OUTPUTS),
291 SDVO_CMD_NAME_ENTRY(GET_IN_OUT_MAP),
292 SDVO_CMD_NAME_ENTRY(SET_IN_OUT_MAP),
293 SDVO_CMD_NAME_ENTRY(GET_ATTACHED_DISPLAYS),
294 SDVO_CMD_NAME_ENTRY(GET_HOT_PLUG_SUPPORT),
295 SDVO_CMD_NAME_ENTRY(SET_ACTIVE_HOT_PLUG),
296 SDVO_CMD_NAME_ENTRY(GET_ACTIVE_HOT_PLUG),
297 SDVO_CMD_NAME_ENTRY(GET_INTERRUPT_EVENT_SOURCE),
298 SDVO_CMD_NAME_ENTRY(SET_TARGET_INPUT),
299 SDVO_CMD_NAME_ENTRY(SET_TARGET_OUTPUT),
300 SDVO_CMD_NAME_ENTRY(GET_INPUT_TIMINGS_PART1),
301 SDVO_CMD_NAME_ENTRY(GET_INPUT_TIMINGS_PART2),
302 SDVO_CMD_NAME_ENTRY(SET_INPUT_TIMINGS_PART1),
303 SDVO_CMD_NAME_ENTRY(SET_INPUT_TIMINGS_PART2),
304 SDVO_CMD_NAME_ENTRY(SET_OUTPUT_TIMINGS_PART1),
305 SDVO_CMD_NAME_ENTRY(SET_OUTPUT_TIMINGS_PART2),
306 SDVO_CMD_NAME_ENTRY(GET_OUTPUT_TIMINGS_PART1),
307 SDVO_CMD_NAME_ENTRY(GET_OUTPUT_TIMINGS_PART2),
308 SDVO_CMD_NAME_ENTRY(CREATE_PREFERRED_INPUT_TIMING),
309 SDVO_CMD_NAME_ENTRY(GET_PREFERRED_INPUT_TIMING_PART1),
310 SDVO_CMD_NAME_ENTRY(GET_PREFERRED_INPUT_TIMING_PART2),
311 SDVO_CMD_NAME_ENTRY(GET_INPUT_PIXEL_CLOCK_RANGE),
312 SDVO_CMD_NAME_ENTRY(GET_OUTPUT_PIXEL_CLOCK_RANGE),
313 SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_CLOCK_RATE_MULTS),
314 SDVO_CMD_NAME_ENTRY(GET_CLOCK_RATE_MULT),
315 SDVO_CMD_NAME_ENTRY(SET_CLOCK_RATE_MULT),
316 SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_TV_FORMATS),
317 SDVO_CMD_NAME_ENTRY(GET_TV_FORMAT),
318 SDVO_CMD_NAME_ENTRY(SET_TV_FORMAT),
319 SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_POWER_STATES),
320 SDVO_CMD_NAME_ENTRY(GET_POWER_STATE),
321 SDVO_CMD_NAME_ENTRY(SET_ENCODER_POWER_STATE),
322 SDVO_CMD_NAME_ENTRY(SET_DISPLAY_POWER_STATE),
323 SDVO_CMD_NAME_ENTRY(SET_CONTROL_BUS_SWITCH),
324 SDVO_CMD_NAME_ENTRY(GET_SDTV_RESOLUTION_SUPPORT),
325 SDVO_CMD_NAME_ENTRY(GET_SCALED_HDTV_RESOLUTION_SUPPORT),
326 SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_ENHANCEMENTS),
327
328 /* Add the op code for SDVO enhancements */
329 SDVO_CMD_NAME_ENTRY(GET_MAX_HPOS),
330 SDVO_CMD_NAME_ENTRY(GET_HPOS),
331 SDVO_CMD_NAME_ENTRY(SET_HPOS),
332 SDVO_CMD_NAME_ENTRY(GET_MAX_VPOS),
333 SDVO_CMD_NAME_ENTRY(GET_VPOS),
334 SDVO_CMD_NAME_ENTRY(SET_VPOS),
335 SDVO_CMD_NAME_ENTRY(GET_MAX_SATURATION),
336 SDVO_CMD_NAME_ENTRY(GET_SATURATION),
337 SDVO_CMD_NAME_ENTRY(SET_SATURATION),
338 SDVO_CMD_NAME_ENTRY(GET_MAX_HUE),
339 SDVO_CMD_NAME_ENTRY(GET_HUE),
340 SDVO_CMD_NAME_ENTRY(SET_HUE),
341 SDVO_CMD_NAME_ENTRY(GET_MAX_CONTRAST),
342 SDVO_CMD_NAME_ENTRY(GET_CONTRAST),
343 SDVO_CMD_NAME_ENTRY(SET_CONTRAST),
344 SDVO_CMD_NAME_ENTRY(GET_MAX_BRIGHTNESS),
345 SDVO_CMD_NAME_ENTRY(GET_BRIGHTNESS),
346 SDVO_CMD_NAME_ENTRY(SET_BRIGHTNESS),
347 SDVO_CMD_NAME_ENTRY(GET_MAX_OVERSCAN_H),
348 SDVO_CMD_NAME_ENTRY(GET_OVERSCAN_H),
349 SDVO_CMD_NAME_ENTRY(SET_OVERSCAN_H),
350 SDVO_CMD_NAME_ENTRY(GET_MAX_OVERSCAN_V),
351 SDVO_CMD_NAME_ENTRY(GET_OVERSCAN_V),
352 SDVO_CMD_NAME_ENTRY(SET_OVERSCAN_V),
353 SDVO_CMD_NAME_ENTRY(GET_MAX_FLICKER_FILTER),
354 SDVO_CMD_NAME_ENTRY(GET_FLICKER_FILTER),
355 SDVO_CMD_NAME_ENTRY(SET_FLICKER_FILTER),
356 SDVO_CMD_NAME_ENTRY(GET_MAX_FLICKER_FILTER_ADAPTIVE),
357 SDVO_CMD_NAME_ENTRY(GET_FLICKER_FILTER_ADAPTIVE),
358 SDVO_CMD_NAME_ENTRY(SET_FLICKER_FILTER_ADAPTIVE),
359 SDVO_CMD_NAME_ENTRY(GET_MAX_FLICKER_FILTER_2D),
360 SDVO_CMD_NAME_ENTRY(GET_FLICKER_FILTER_2D),
361 SDVO_CMD_NAME_ENTRY(SET_FLICKER_FILTER_2D),
362 SDVO_CMD_NAME_ENTRY(GET_MAX_SHARPNESS),
363 SDVO_CMD_NAME_ENTRY(GET_SHARPNESS),
364 SDVO_CMD_NAME_ENTRY(SET_SHARPNESS),
365 SDVO_CMD_NAME_ENTRY(GET_DOT_CRAWL),
366 SDVO_CMD_NAME_ENTRY(SET_DOT_CRAWL),
367 SDVO_CMD_NAME_ENTRY(GET_MAX_TV_CHROMA_FILTER),
368 SDVO_CMD_NAME_ENTRY(GET_TV_CHROMA_FILTER),
369 SDVO_CMD_NAME_ENTRY(SET_TV_CHROMA_FILTER),
370 SDVO_CMD_NAME_ENTRY(GET_MAX_TV_LUMA_FILTER),
371 SDVO_CMD_NAME_ENTRY(GET_TV_LUMA_FILTER),
372 SDVO_CMD_NAME_ENTRY(SET_TV_LUMA_FILTER),
373
374 /* HDMI op code */
375 SDVO_CMD_NAME_ENTRY(GET_SUPP_ENCODE),
376 SDVO_CMD_NAME_ENTRY(GET_ENCODE),
377 SDVO_CMD_NAME_ENTRY(SET_ENCODE),
378 SDVO_CMD_NAME_ENTRY(SET_PIXEL_REPLI),
379 SDVO_CMD_NAME_ENTRY(GET_PIXEL_REPLI),
380 SDVO_CMD_NAME_ENTRY(GET_COLORIMETRY_CAP),
381 SDVO_CMD_NAME_ENTRY(SET_COLORIMETRY),
382 SDVO_CMD_NAME_ENTRY(GET_COLORIMETRY),
383 SDVO_CMD_NAME_ENTRY(GET_AUDIO_ENCRYPT_PREFER),
384 SDVO_CMD_NAME_ENTRY(SET_AUDIO_STAT),
385 SDVO_CMD_NAME_ENTRY(GET_AUDIO_STAT),
386 SDVO_CMD_NAME_ENTRY(GET_HBUF_INDEX),
387 SDVO_CMD_NAME_ENTRY(SET_HBUF_INDEX),
388 SDVO_CMD_NAME_ENTRY(GET_HBUF_INFO),
389 SDVO_CMD_NAME_ENTRY(GET_HBUF_AV_SPLIT),
390 SDVO_CMD_NAME_ENTRY(SET_HBUF_AV_SPLIT),
391 SDVO_CMD_NAME_ENTRY(GET_HBUF_TXRATE),
392 SDVO_CMD_NAME_ENTRY(SET_HBUF_TXRATE),
393 SDVO_CMD_NAME_ENTRY(SET_HBUF_DATA),
394 SDVO_CMD_NAME_ENTRY(GET_HBUF_DATA),
395 };
396
397 #undef SDVO_CMD_NAME_ENTRY
398
399 static const char *sdvo_cmd_name(u8 cmd)
400 {
401 int i;
402
403 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
404 if (cmd == sdvo_cmd_names[i].cmd)
405 return sdvo_cmd_names[i].name;
406 }
407
408 return NULL;
409 }
410
411 #define SDVO_NAME(svdo) ((svdo)->base.port == PORT_B ? "SDVOB" : "SDVOC")
412
413 static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
414 const void *args, int args_len)
415 {
416 struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev);
417 const char *cmd_name;
418 int i, pos = 0;
419 char buffer[64];
420
421 #define BUF_PRINT(args...) \
422 pos += snprintf(buffer + pos, max_t(int, sizeof(buffer) - pos, 0), args)
423
424 for (i = 0; i < args_len; i++) {
425 BUF_PRINT("%02X ", ((u8 *)args)[i]);
426 }
427 for (; i < 8; i++) {
428 BUF_PRINT(" ");
429 }
430
431 cmd_name = sdvo_cmd_name(cmd);
432 if (cmd_name)
433 BUF_PRINT("(%s)", cmd_name);
434 else
435 BUF_PRINT("(%02X)", cmd);
436
437 drm_WARN_ON(&dev_priv->drm, pos >= sizeof(buffer) - 1);
438 #undef BUF_PRINT
439
440 DRM_DEBUG_KMS("%s: W: %02X %s\n", SDVO_NAME(intel_sdvo), cmd, buffer);
441 }
442
443 static const char * const cmd_status_names[] = {
444 [SDVO_CMD_STATUS_POWER_ON] = "Power on",
445 [SDVO_CMD_STATUS_SUCCESS] = "Success",
446 [SDVO_CMD_STATUS_NOTSUPP] = "Not supported",
447 [SDVO_CMD_STATUS_INVALID_ARG] = "Invalid arg",
448 [SDVO_CMD_STATUS_PENDING] = "Pending",
449 [SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED] = "Target not specified",
450 [SDVO_CMD_STATUS_SCALING_NOT_SUPP] = "Scaling not supported",
451 };
452
453 static const char *sdvo_cmd_status(u8 status)
454 {
455 if (status < ARRAY_SIZE(cmd_status_names))
456 return cmd_status_names[status];
457 else
458 return NULL;
459 }
460
461 static bool __intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
462 const void *args, int args_len,
463 bool unlocked)
464 {
465 u8 *buf, status;
466 struct i2c_msg *msgs;
467 int i, ret = true;
468
469 /* Would be simpler to allocate both in one go ? */
470 buf = kzalloc(args_len * 2 + 2, GFP_KERNEL);
471 if (!buf)
472 return false;
473
474 msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL);
475 if (!msgs) {
476 kfree(buf);
477 return false;
478 }
479
480 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
481
482 for (i = 0; i < args_len; i++) {
483 msgs[i].addr = intel_sdvo->slave_addr;
484 msgs[i].flags = 0;
485 msgs[i].len = 2;
486 msgs[i].buf = buf + 2 *i;
487 buf[2*i + 0] = SDVO_I2C_ARG_0 - i;
488 buf[2*i + 1] = ((u8*)args)[i];
489 }
490 msgs[i].addr = intel_sdvo->slave_addr;
491 msgs[i].flags = 0;
492 msgs[i].len = 2;
493 msgs[i].buf = buf + 2*i;
494 buf[2*i + 0] = SDVO_I2C_OPCODE;
495 buf[2*i + 1] = cmd;
496
497 /* the following two are to read the response */
498 status = SDVO_I2C_CMD_STATUS;
499 msgs[i+1].addr = intel_sdvo->slave_addr;
500 msgs[i+1].flags = 0;
501 msgs[i+1].len = 1;
502 msgs[i+1].buf = &status;
503
504 msgs[i+2].addr = intel_sdvo->slave_addr;
505 msgs[i+2].flags = I2C_M_RD;
506 msgs[i+2].len = 1;
507 msgs[i+2].buf = &status;
508
509 if (unlocked)
510 ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3);
511 else
512 ret = __i2c_transfer(intel_sdvo->i2c, msgs, i+3);
513 if (ret < 0) {
514 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
515 ret = false;
516 goto out;
517 }
518 if (ret != i+3) {
519 /* failure in I2C transfer */
520 DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3);
521 ret = false;
522 }
523
524 out:
525 kfree(msgs);
526 kfree(buf);
527 return ret;
528 }
529
530 static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
531 const void *args, int args_len)
532 {
533 return __intel_sdvo_write_cmd(intel_sdvo, cmd, args, args_len, true);
534 }
535
536 static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
537 void *response, int response_len)
538 {
539 struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev);
540 const char *cmd_status;
541 u8 retry = 15; /* 5 quick checks, followed by 10 long checks */
542 u8 status;
543 int i, pos = 0;
544 char buffer[64];
545
546 buffer[0] = '\0';
547
548 /*
549 * The documentation states that all commands will be
550 * processed within 15µs, and that we need only poll
551 * the status byte a maximum of 3 times in order for the
552 * command to be complete.
553 *
554 * Check 5 times in case the hardware failed to read the docs.
555 *
556 * Also beware that the first response by many devices is to
557 * reply PENDING and stall for time. TVs are notorious for
558 * requiring longer than specified to complete their replies.
559 * Originally (in the DDX long ago), the delay was only ever 15ms
560 * with an additional delay of 30ms applied for TVs added later after
561 * many experiments. To accommodate both sets of delays, we do a
562 * sequence of slow checks if the device is falling behind and fails
563 * to reply within 5*15µs.
564 */
565 if (!intel_sdvo_read_byte(intel_sdvo,
566 SDVO_I2C_CMD_STATUS,
567 &status))
568 goto log_fail;
569
570 while ((status == SDVO_CMD_STATUS_PENDING ||
571 status == SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED) && --retry) {
572 if (retry < 10)
573 msleep(15);
574 else
575 udelay(15);
576
577 if (!intel_sdvo_read_byte(intel_sdvo,
578 SDVO_I2C_CMD_STATUS,
579 &status))
580 goto log_fail;
581 }
582
583 #define BUF_PRINT(args...) \
584 pos += snprintf(buffer + pos, max_t(int, sizeof(buffer) - pos, 0), args)
585
586 cmd_status = sdvo_cmd_status(status);
587 if (cmd_status)
588 BUF_PRINT("(%s)", cmd_status);
589 else
590 BUF_PRINT("(??? %d)", status);
591
592 if (status != SDVO_CMD_STATUS_SUCCESS)
593 goto log_fail;
594
595 /* Read the command response */
596 for (i = 0; i < response_len; i++) {
597 if (!intel_sdvo_read_byte(intel_sdvo,
598 SDVO_I2C_RETURN_0 + i,
599 &((u8 *)response)[i]))
600 goto log_fail;
601 BUF_PRINT(" %02X", ((u8 *)response)[i]);
602 }
603
604 drm_WARN_ON(&dev_priv->drm, pos >= sizeof(buffer) - 1);
605 #undef BUF_PRINT
606
607 DRM_DEBUG_KMS("%s: R: %s\n", SDVO_NAME(intel_sdvo), buffer);
608 return true;
609
610 log_fail:
611 DRM_DEBUG_KMS("%s: R: ... failed %s\n",
612 SDVO_NAME(intel_sdvo), buffer);
613 return false;
614 }
615
616 static int intel_sdvo_get_pixel_multiplier(const struct drm_display_mode *adjusted_mode)
617 {
618 if (adjusted_mode->crtc_clock >= 100000)
619 return 1;
620 else if (adjusted_mode->crtc_clock >= 50000)
621 return 2;
622 else
623 return 4;
624 }
625
626 static bool __intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
627 u8 ddc_bus)
628 {
629 /* This must be the immediately preceding write before the i2c xfer */
630 return __intel_sdvo_write_cmd(intel_sdvo,
631 SDVO_CMD_SET_CONTROL_BUS_SWITCH,
632 &ddc_bus, 1, false);
633 }
634
635 static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
636 {
637 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
638 return false;
639
640 return intel_sdvo_read_response(intel_sdvo, NULL, 0);
641 }
642
643 static bool
644 intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)
645 {
646 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
647 return false;
648
649 return intel_sdvo_read_response(intel_sdvo, value, len);
650 }
651
652 static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
653 {
654 struct intel_sdvo_set_target_input_args targets = {};
655 return intel_sdvo_set_value(intel_sdvo,
656 SDVO_CMD_SET_TARGET_INPUT,
657 &targets, sizeof(targets));
658 }
659
660 /*
661 * Return whether each input is trained.
662 *
663 * This function is making an assumption about the layout of the response,
664 * which should be checked against the docs.
665 */
666 static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
667 {
668 struct intel_sdvo_get_trained_inputs_response response;
669
670 BUILD_BUG_ON(sizeof(response) != 1);
671 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
672 &response, sizeof(response)))
673 return false;
674
675 *input_1 = response.input0_trained;
676 *input_2 = response.input1_trained;
677 return true;
678 }
679
680 static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
681 u16 outputs)
682 {
683 return intel_sdvo_set_value(intel_sdvo,
684 SDVO_CMD_SET_ACTIVE_OUTPUTS,
685 &outputs, sizeof(outputs));
686 }
687
688 static bool intel_sdvo_get_active_outputs(struct intel_sdvo *intel_sdvo,
689 u16 *outputs)
690 {
691 return intel_sdvo_get_value(intel_sdvo,
692 SDVO_CMD_GET_ACTIVE_OUTPUTS,
693 outputs, sizeof(*outputs));
694 }
695
696 static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
697 int mode)
698 {
699 u8 state = SDVO_ENCODER_STATE_ON;
700
701 switch (mode) {
702 case DRM_MODE_DPMS_ON:
703 state = SDVO_ENCODER_STATE_ON;
704 break;
705 case DRM_MODE_DPMS_STANDBY:
706 state = SDVO_ENCODER_STATE_STANDBY;
707 break;
708 case DRM_MODE_DPMS_SUSPEND:
709 state = SDVO_ENCODER_STATE_SUSPEND;
710 break;
711 case DRM_MODE_DPMS_OFF:
712 state = SDVO_ENCODER_STATE_OFF;
713 break;
714 }
715
716 return intel_sdvo_set_value(intel_sdvo,
717 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
718 }
719
720 static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
721 int *clock_min,
722 int *clock_max)
723 {
724 struct intel_sdvo_pixel_clock_range clocks;
725
726 BUILD_BUG_ON(sizeof(clocks) != 4);
727 if (!intel_sdvo_get_value(intel_sdvo,
728 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
729 &clocks, sizeof(clocks)))
730 return false;
731
732 /* Convert the values from units of 10 kHz to kHz. */
733 *clock_min = clocks.min * 10;
734 *clock_max = clocks.max * 10;
735 return true;
736 }
737
738 static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
739 u16 outputs)
740 {
741 return intel_sdvo_set_value(intel_sdvo,
742 SDVO_CMD_SET_TARGET_OUTPUT,
743 &outputs, sizeof(outputs));
744 }
745
746 static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
747 struct intel_sdvo_dtd *dtd)
748 {
749 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
750 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
751 }
752
753 static bool intel_sdvo_get_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
754 struct intel_sdvo_dtd *dtd)
755 {
756 return intel_sdvo_get_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
757 intel_sdvo_get_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
758 }
759
760 static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
761 struct intel_sdvo_dtd *dtd)
762 {
763 return intel_sdvo_set_timing(intel_sdvo,
764 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
765 }
766
767 static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
768 struct intel_sdvo_dtd *dtd)
769 {
770 return intel_sdvo_set_timing(intel_sdvo,
771 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
772 }
773
774 static bool intel_sdvo_get_input_timing(struct intel_sdvo *intel_sdvo,
775 struct intel_sdvo_dtd *dtd)
776 {
777 return intel_sdvo_get_timing(intel_sdvo,
778 SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd);
779 }
780
781 static bool
782 intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
783 struct intel_sdvo_connector *intel_sdvo_connector,
784 const struct drm_display_mode *mode)
785 {
786 struct intel_sdvo_preferred_input_timing_args args;
787
788 memset(&args, 0, sizeof(args));
789 args.clock = mode->clock / 10;
790 args.width = mode->hdisplay;
791 args.height = mode->vdisplay;
792 args.interlace = 0;
793
794 if (IS_LVDS(intel_sdvo_connector)) {
795 const struct drm_display_mode *fixed_mode =
796 intel_panel_fixed_mode(&intel_sdvo_connector->base, mode);
797
798 if (fixed_mode->hdisplay != args.width ||
799 fixed_mode->vdisplay != args.height)
800 args.scaled = 1;
801 }
802
803 return intel_sdvo_set_value(intel_sdvo,
804 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
805 &args, sizeof(args));
806 }
807
808 static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
809 struct intel_sdvo_dtd *dtd)
810 {
811 BUILD_BUG_ON(sizeof(dtd->part1) != 8);
812 BUILD_BUG_ON(sizeof(dtd->part2) != 8);
813 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
814 &dtd->part1, sizeof(dtd->part1)) &&
815 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
816 &dtd->part2, sizeof(dtd->part2));
817 }
818
819 static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
820 {
821 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
822 }
823
824 static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
825 const struct drm_display_mode *mode)
826 {
827 u16 width, height;
828 u16 h_blank_len, h_sync_len, v_blank_len, v_sync_len;
829 u16 h_sync_offset, v_sync_offset;
830 int mode_clock;
831
832 memset(dtd, 0, sizeof(*dtd));
833
834 width = mode->hdisplay;
835 height = mode->vdisplay;
836
837 /* do some mode translations */
838 h_blank_len = mode->htotal - mode->hdisplay;
839 h_sync_len = mode->hsync_end - mode->hsync_start;
840
841 v_blank_len = mode->vtotal - mode->vdisplay;
842 v_sync_len = mode->vsync_end - mode->vsync_start;
843
844 h_sync_offset = mode->hsync_start - mode->hdisplay;
845 v_sync_offset = mode->vsync_start - mode->vdisplay;
846
847 mode_clock = mode->clock;
848 mode_clock /= 10;
849 dtd->part1.clock = mode_clock;
850
851 dtd->part1.h_active = width & 0xff;
852 dtd->part1.h_blank = h_blank_len & 0xff;
853 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
854 ((h_blank_len >> 8) & 0xf);
855 dtd->part1.v_active = height & 0xff;
856 dtd->part1.v_blank = v_blank_len & 0xff;
857 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
858 ((v_blank_len >> 8) & 0xf);
859
860 dtd->part2.h_sync_off = h_sync_offset & 0xff;
861 dtd->part2.h_sync_width = h_sync_len & 0xff;
862 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
863 (v_sync_len & 0xf);
864 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
865 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
866 ((v_sync_len & 0x30) >> 4);
867
868 dtd->part2.dtd_flags = 0x18;
869 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
870 dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE;
871 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
872 dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE;
873 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
874 dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE;
875
876 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
877 }
878
879 static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode *pmode,
880 const struct intel_sdvo_dtd *dtd)
881 {
882 struct drm_display_mode mode = {};
883
884 mode.hdisplay = dtd->part1.h_active;
885 mode.hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
886 mode.hsync_start = mode.hdisplay + dtd->part2.h_sync_off;
887 mode.hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
888 mode.hsync_end = mode.hsync_start + dtd->part2.h_sync_width;
889 mode.hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
890 mode.htotal = mode.hdisplay + dtd->part1.h_blank;
891 mode.htotal += (dtd->part1.h_high & 0xf) << 8;
892
893 mode.vdisplay = dtd->part1.v_active;
894 mode.vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
895 mode.vsync_start = mode.vdisplay;
896 mode.vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
897 mode.vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
898 mode.vsync_start += dtd->part2.v_sync_off_high & 0xc0;
899 mode.vsync_end = mode.vsync_start +
900 (dtd->part2.v_sync_off_width & 0xf);
901 mode.vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
902 mode.vtotal = mode.vdisplay + dtd->part1.v_blank;
903 mode.vtotal += (dtd->part1.v_high & 0xf) << 8;
904
905 mode.clock = dtd->part1.clock * 10;
906
907 if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE)
908 mode.flags |= DRM_MODE_FLAG_INTERLACE;
909 if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
910 mode.flags |= DRM_MODE_FLAG_PHSYNC;
911 else
912 mode.flags |= DRM_MODE_FLAG_NHSYNC;
913 if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
914 mode.flags |= DRM_MODE_FLAG_PVSYNC;
915 else
916 mode.flags |= DRM_MODE_FLAG_NVSYNC;
917
918 drm_mode_set_crtcinfo(&mode, 0);
919
920 drm_mode_copy(pmode, &mode);
921 }
922
923 static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo)
924 {
925 struct intel_sdvo_encode encode;
926
927 BUILD_BUG_ON(sizeof(encode) != 2);
928 return intel_sdvo_get_value(intel_sdvo,
929 SDVO_CMD_GET_SUPP_ENCODE,
930 &encode, sizeof(encode));
931 }
932
933 static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
934 u8 mode)
935 {
936 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
937 }
938
939 static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
940 u8 mode)
941 {
942 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
943 }
944
945 static bool intel_sdvo_set_pixel_replication(struct intel_sdvo *intel_sdvo,
946 u8 pixel_repeat)
947 {
948 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_PIXEL_REPLI,
949 &pixel_repeat, 1);
950 }
951
952 static bool intel_sdvo_set_audio_state(struct intel_sdvo *intel_sdvo,
953 u8 audio_state)
954 {
955 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_AUDIO_STAT,
956 &audio_state, 1);
957 }
958
959 static bool intel_sdvo_get_hbuf_size(struct intel_sdvo *intel_sdvo,
960 u8 *hbuf_size)
961 {
962 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO,
963 hbuf_size, 1))
964 return false;
965
966 /* Buffer size is 0 based, hooray! However zero means zero. */
967 if (*hbuf_size)
968 (*hbuf_size)++;
969
970 return true;
971 }
972
973 #if 0
974 static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
975 {
976 int i, j;
977 u8 set_buf_index[2];
978 u8 av_split;
979 u8 buf_size;
980 u8 buf[48];
981 u8 *pos;
982
983 intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
984
985 for (i = 0; i <= av_split; i++) {
986 set_buf_index[0] = i; set_buf_index[1] = 0;
987 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
988 set_buf_index, 2);
989 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
990 intel_sdvo_read_response(encoder, &buf_size, 1);
991
992 pos = buf;
993 for (j = 0; j <= buf_size; j += 8) {
994 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
995 NULL, 0);
996 intel_sdvo_read_response(encoder, pos, 8);
997 pos += 8;
998 }
999 }
1000 }
1001 #endif
1002
1003 static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo,
1004 unsigned int if_index, u8 tx_rate,
1005 const u8 *data, unsigned int length)
1006 {
1007 u8 set_buf_index[2] = { if_index, 0 };
1008 u8 hbuf_size, tmp[8];
1009 int i;
1010
1011 if (!intel_sdvo_set_value(intel_sdvo,
1012 SDVO_CMD_SET_HBUF_INDEX,
1013 set_buf_index, 2))
1014 return false;
1015
1016 if (!intel_sdvo_get_hbuf_size(intel_sdvo, &hbuf_size))
1017 return false;
1018
1019 DRM_DEBUG_KMS("writing sdvo hbuf: %i, length %u, hbuf_size: %i\n",
1020 if_index, length, hbuf_size);
1021
1022 if (hbuf_size < length)
1023 return false;
1024
1025 for (i = 0; i < hbuf_size; i += 8) {
1026 memset(tmp, 0, 8);
1027 if (i < length)
1028 memcpy(tmp, data + i, min_t(unsigned, 8, length - i));
1029
1030 if (!intel_sdvo_set_value(intel_sdvo,
1031 SDVO_CMD_SET_HBUF_DATA,
1032 tmp, 8))
1033 return false;
1034 }
1035
1036 return intel_sdvo_set_value(intel_sdvo,
1037 SDVO_CMD_SET_HBUF_TXRATE,
1038 &tx_rate, 1);
1039 }
1040
1041 static ssize_t intel_sdvo_read_infoframe(struct intel_sdvo *intel_sdvo,
1042 unsigned int if_index,
1043 u8 *data, unsigned int length)
1044 {
1045 u8 set_buf_index[2] = { if_index, 0 };
1046 u8 hbuf_size, tx_rate, av_split;
1047 int i;
1048
1049 if (!intel_sdvo_get_value(intel_sdvo,
1050 SDVO_CMD_GET_HBUF_AV_SPLIT,
1051 &av_split, 1))
1052 return -ENXIO;
1053
1054 if (av_split < if_index)
1055 return 0;
1056
1057 if (!intel_sdvo_set_value(intel_sdvo,
1058 SDVO_CMD_SET_HBUF_INDEX,
1059 set_buf_index, 2))
1060 return -ENXIO;
1061
1062 if (!intel_sdvo_get_value(intel_sdvo,
1063 SDVO_CMD_GET_HBUF_TXRATE,
1064 &tx_rate, 1))
1065 return -ENXIO;
1066
1067 /* TX_DISABLED doesn't mean disabled for ELD */
1068 if (if_index != SDVO_HBUF_INDEX_ELD && tx_rate == SDVO_HBUF_TX_DISABLED)
1069 return 0;
1070
1071 if (!intel_sdvo_get_hbuf_size(intel_sdvo, &hbuf_size))
1072 return false;
1073
1074 DRM_DEBUG_KMS("reading sdvo hbuf: %i, length %u, hbuf_size: %i\n",
1075 if_index, length, hbuf_size);
1076
1077 hbuf_size = min_t(unsigned int, length, hbuf_size);
1078
1079 for (i = 0; i < hbuf_size; i += 8) {
1080 if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_HBUF_DATA, NULL, 0))
1081 return -ENXIO;
1082 if (!intel_sdvo_read_response(intel_sdvo, &data[i],
1083 min_t(unsigned int, 8, hbuf_size - i)))
1084 return -ENXIO;
1085 }
1086
1087 return hbuf_size;
1088 }
1089
1090 static bool intel_sdvo_compute_avi_infoframe(struct intel_sdvo *intel_sdvo,
1091 struct intel_crtc_state *crtc_state,
1092 struct drm_connector_state *conn_state)
1093 {
1094 struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev);
1095 struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi;
1096 const struct drm_display_mode *adjusted_mode =
1097 &crtc_state->hw.adjusted_mode;
1098 int ret;
1099
1100 if (!crtc_state->has_hdmi_sink)
1101 return true;
1102
1103 crtc_state->infoframes.enable |=
1104 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI);
1105
1106 ret = drm_hdmi_avi_infoframe_from_display_mode(frame,
1107 conn_state->connector,
1108 adjusted_mode);
1109 if (ret)
1110 return false;
1111
1112 drm_hdmi_avi_infoframe_quant_range(frame,
1113 conn_state->connector,
1114 adjusted_mode,
1115 crtc_state->limited_color_range ?
1116 HDMI_QUANTIZATION_RANGE_LIMITED :
1117 HDMI_QUANTIZATION_RANGE_FULL);
1118
1119 ret = hdmi_avi_infoframe_check(frame);
1120 if (drm_WARN_ON(&dev_priv->drm, ret))
1121 return false;
1122
1123 return true;
1124 }
1125
1126 static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo,
1127 const struct intel_crtc_state *crtc_state)
1128 {
1129 struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev);
1130 u8 sdvo_data[HDMI_INFOFRAME_SIZE(AVI)];
1131 const union hdmi_infoframe *frame = &crtc_state->infoframes.avi;
1132 ssize_t len;
1133
1134 if ((crtc_state->infoframes.enable &
1135 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI)) == 0)
1136 return true;
1137
1138 if (drm_WARN_ON(&dev_priv->drm,
1139 frame->any.type != HDMI_INFOFRAME_TYPE_AVI))
1140 return false;
1141
1142 len = hdmi_infoframe_pack_only(frame, sdvo_data, sizeof(sdvo_data));
1143 if (drm_WARN_ON(&dev_priv->drm, len < 0))
1144 return false;
1145
1146 return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF,
1147 SDVO_HBUF_TX_VSYNC,
1148 sdvo_data, len);
1149 }
1150
1151 static void intel_sdvo_get_avi_infoframe(struct intel_sdvo *intel_sdvo,
1152 struct intel_crtc_state *crtc_state)
1153 {
1154 u8 sdvo_data[HDMI_INFOFRAME_SIZE(AVI)];
1155 union hdmi_infoframe *frame = &crtc_state->infoframes.avi;
1156 ssize_t len;
1157 int ret;
1158
1159 if (!crtc_state->has_hdmi_sink)
1160 return;
1161
1162 len = intel_sdvo_read_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF,
1163 sdvo_data, sizeof(sdvo_data));
1164 if (len < 0) {
1165 DRM_DEBUG_KMS("failed to read AVI infoframe\n");
1166 return;
1167 } else if (len == 0) {
1168 return;
1169 }
1170
1171 crtc_state->infoframes.enable |=
1172 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI);
1173
1174 ret = hdmi_infoframe_unpack(frame, sdvo_data, len);
1175 if (ret) {
1176 DRM_DEBUG_KMS("Failed to unpack AVI infoframe\n");
1177 return;
1178 }
1179
1180 if (frame->any.type != HDMI_INFOFRAME_TYPE_AVI)
1181 DRM_DEBUG_KMS("Found the wrong infoframe type 0x%x (expected 0x%02x)\n",
1182 frame->any.type, HDMI_INFOFRAME_TYPE_AVI);
1183 }
1184
1185 static void intel_sdvo_get_eld(struct intel_sdvo *intel_sdvo,
1186 struct intel_crtc_state *crtc_state)
1187 {
1188 struct drm_i915_private *i915 = to_i915(intel_sdvo->base.base.dev);
1189 ssize_t len;
1190 u8 val;
1191
1192 if (!crtc_state->has_audio)
1193 return;
1194
1195 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_AUDIO_STAT, &val, 1))
1196 return;
1197
1198 if ((val & SDVO_AUDIO_ELD_VALID) == 0)
1199 return;
1200
1201 len = intel_sdvo_read_infoframe(intel_sdvo, SDVO_HBUF_INDEX_ELD,
1202 crtc_state->eld, sizeof(crtc_state->eld));
1203 if (len < 0)
1204 drm_dbg_kms(&i915->drm, "failed to read ELD\n");
1205 }
1206
1207 static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo,
1208 const struct drm_connector_state *conn_state)
1209 {
1210 struct intel_sdvo_tv_format format;
1211 u32 format_map;
1212
1213 format_map = 1 << conn_state->tv.legacy_mode;
1214 memset(&format, 0, sizeof(format));
1215 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
1216
1217 BUILD_BUG_ON(sizeof(format) != 6);
1218 return intel_sdvo_set_value(intel_sdvo,
1219 SDVO_CMD_SET_TV_FORMAT,
1220 &format, sizeof(format));
1221 }
1222
1223 static bool
1224 intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
1225 struct intel_sdvo_connector *intel_sdvo_connector,
1226 const struct drm_display_mode *mode)
1227 {
1228 struct intel_sdvo_dtd output_dtd;
1229
1230 if (!intel_sdvo_set_target_output(intel_sdvo,
1231 intel_sdvo_connector->output_flag))
1232 return false;
1233
1234 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
1235 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1236 return false;
1237
1238 return true;
1239 }
1240
1241 /*
1242 * Asks the sdvo controller for the preferred input mode given the output mode.
1243 * Unfortunately we have to set up the full output mode to do that.
1244 */
1245 static bool
1246 intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo,
1247 struct intel_sdvo_connector *intel_sdvo_connector,
1248 const struct drm_display_mode *mode,
1249 struct drm_display_mode *adjusted_mode)
1250 {
1251 struct intel_sdvo_dtd input_dtd;
1252
1253 /* Reset the input timing to the screen. Assume always input 0. */
1254 if (!intel_sdvo_set_target_input(intel_sdvo))
1255 return false;
1256
1257 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
1258 intel_sdvo_connector,
1259 mode))
1260 return false;
1261
1262 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
1263 &input_dtd))
1264 return false;
1265
1266 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
1267 intel_sdvo->dtd_sdvo_flags = input_dtd.part2.sdvo_flags;
1268
1269 return true;
1270 }
1271
1272 static int i9xx_adjust_sdvo_tv_clock(struct intel_crtc_state *pipe_config)
1273 {
1274 struct drm_i915_private *dev_priv = to_i915(pipe_config->uapi.crtc->dev);
1275 unsigned int dotclock = pipe_config->hw.adjusted_mode.crtc_clock;
1276 struct dpll *clock = &pipe_config->dpll;
1277
1278 /*
1279 * SDVO TV has fixed PLL values depend on its clock range,
1280 * this mirrors vbios setting.
1281 */
1282 if (dotclock >= 100000 && dotclock < 140500) {
1283 clock->p1 = 2;
1284 clock->p2 = 10;
1285 clock->n = 3;
1286 clock->m1 = 16;
1287 clock->m2 = 8;
1288 } else if (dotclock >= 140500 && dotclock <= 200000) {
1289 clock->p1 = 1;
1290 clock->p2 = 10;
1291 clock->n = 6;
1292 clock->m1 = 12;
1293 clock->m2 = 8;
1294 } else {
1295 drm_dbg_kms(&dev_priv->drm,
1296 "SDVO TV clock out of range: %i\n", dotclock);
1297 return -EINVAL;
1298 }
1299
1300 pipe_config->clock_set = true;
1301
1302 return 0;
1303 }
1304
1305 static bool intel_has_hdmi_sink(struct intel_sdvo_connector *intel_sdvo_connector,
1306 const struct drm_connector_state *conn_state)
1307 {
1308 struct drm_connector *connector = conn_state->connector;
1309
1310 return intel_sdvo_connector->is_hdmi &&
1311 connector->display_info.is_hdmi &&
1312 READ_ONCE(to_intel_digital_connector_state(conn_state)->force_audio) != HDMI_AUDIO_OFF_DVI;
1313 }
1314
1315 static bool intel_sdvo_limited_color_range(struct intel_encoder *encoder,
1316 const struct intel_crtc_state *crtc_state,
1317 const struct drm_connector_state *conn_state)
1318 {
1319 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1320
1321 if ((intel_sdvo->colorimetry_cap & SDVO_COLORIMETRY_RGB220) == 0)
1322 return false;
1323
1324 return intel_hdmi_limited_color_range(crtc_state, conn_state);
1325 }
1326
1327 static bool intel_sdvo_has_audio(struct intel_encoder *encoder,
1328 const struct intel_crtc_state *crtc_state,
1329 const struct drm_connector_state *conn_state)
1330 {
1331 struct drm_connector *connector = conn_state->connector;
1332 struct intel_sdvo_connector *intel_sdvo_connector =
1333 to_intel_sdvo_connector(connector);
1334 const struct intel_digital_connector_state *intel_conn_state =
1335 to_intel_digital_connector_state(conn_state);
1336
1337 if (!crtc_state->has_hdmi_sink)
1338 return false;
1339
1340 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
1341 return intel_sdvo_connector->is_hdmi &&
1342 connector->display_info.has_audio;
1343 else
1344 return intel_conn_state->force_audio == HDMI_AUDIO_ON;
1345 }
1346
1347 static int intel_sdvo_compute_config(struct intel_encoder *encoder,
1348 struct intel_crtc_state *pipe_config,
1349 struct drm_connector_state *conn_state)
1350 {
1351 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1352 struct intel_sdvo_connector *intel_sdvo_connector =
1353 to_intel_sdvo_connector(conn_state->connector);
1354 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
1355 struct drm_display_mode *mode = &pipe_config->hw.mode;
1356
1357 if (HAS_PCH_SPLIT(to_i915(encoder->base.dev))) {
1358 pipe_config->has_pch_encoder = true;
1359 if (!intel_fdi_compute_pipe_bpp(pipe_config))
1360 return -EINVAL;
1361 }
1362
1363 DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n");
1364 /* FIXME: Don't increase pipe_bpp */
1365 pipe_config->pipe_bpp = 8*3;
1366 pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
1367 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
1368
1369 /*
1370 * We need to construct preferred input timings based on our
1371 * output timings. To do that, we have to set the output
1372 * timings, even though this isn't really the right place in
1373 * the sequence to do it. Oh well.
1374 */
1375 if (IS_TV(intel_sdvo_connector)) {
1376 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
1377 intel_sdvo_connector,
1378 mode))
1379 return -EINVAL;
1380
1381 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
1382 intel_sdvo_connector,
1383 mode,
1384 adjusted_mode);
1385 pipe_config->sdvo_tv_clock = true;
1386 } else if (IS_LVDS(intel_sdvo_connector)) {
1387 const struct drm_display_mode *fixed_mode =
1388 intel_panel_fixed_mode(&intel_sdvo_connector->base, mode);
1389 int ret;
1390
1391 ret = intel_panel_compute_config(&intel_sdvo_connector->base,
1392 adjusted_mode);
1393 if (ret)
1394 return ret;
1395
1396 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
1397 intel_sdvo_connector,
1398 fixed_mode))
1399 return -EINVAL;
1400
1401 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
1402 intel_sdvo_connector,
1403 mode,
1404 adjusted_mode);
1405 }
1406
1407 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
1408 return -EINVAL;
1409
1410 /*
1411 * Make the CRTC code factor in the SDVO pixel multiplier. The
1412 * SDVO device will factor out the multiplier during mode_set.
1413 */
1414 pipe_config->pixel_multiplier =
1415 intel_sdvo_get_pixel_multiplier(adjusted_mode);
1416
1417 pipe_config->has_hdmi_sink = intel_has_hdmi_sink(intel_sdvo_connector, conn_state);
1418
1419 pipe_config->has_audio =
1420 intel_sdvo_has_audio(encoder, pipe_config, conn_state) &&
1421 intel_audio_compute_config(encoder, pipe_config, conn_state);
1422
1423 pipe_config->limited_color_range =
1424 intel_sdvo_limited_color_range(encoder, pipe_config,
1425 conn_state);
1426
1427 /* Clock computation needs to happen after pixel multiplier. */
1428 if (IS_TV(intel_sdvo_connector)) {
1429 int ret;
1430
1431 ret = i9xx_adjust_sdvo_tv_clock(pipe_config);
1432 if (ret)
1433 return ret;
1434 }
1435
1436 if (conn_state->picture_aspect_ratio)
1437 adjusted_mode->picture_aspect_ratio =
1438 conn_state->picture_aspect_ratio;
1439
1440 if (!intel_sdvo_compute_avi_infoframe(intel_sdvo,
1441 pipe_config, conn_state)) {
1442 DRM_DEBUG_KMS("bad AVI infoframe\n");
1443 return -EINVAL;
1444 }
1445
1446 return 0;
1447 }
1448
1449 #define UPDATE_PROPERTY(input, NAME) \
1450 do { \
1451 val = input; \
1452 intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_##NAME, &val, sizeof(val)); \
1453 } while (0)
1454
1455 static void intel_sdvo_update_props(struct intel_sdvo *intel_sdvo,
1456 const struct intel_sdvo_connector_state *sdvo_state)
1457 {
1458 const struct drm_connector_state *conn_state = &sdvo_state->base.base;
1459 struct intel_sdvo_connector *intel_sdvo_conn =
1460 to_intel_sdvo_connector(conn_state->connector);
1461 u16 val;
1462
1463 if (intel_sdvo_conn->left)
1464 UPDATE_PROPERTY(sdvo_state->tv.overscan_h, OVERSCAN_H);
1465
1466 if (intel_sdvo_conn->top)
1467 UPDATE_PROPERTY(sdvo_state->tv.overscan_v, OVERSCAN_V);
1468
1469 if (intel_sdvo_conn->hpos)
1470 UPDATE_PROPERTY(sdvo_state->tv.hpos, HPOS);
1471
1472 if (intel_sdvo_conn->vpos)
1473 UPDATE_PROPERTY(sdvo_state->tv.vpos, VPOS);
1474
1475 if (intel_sdvo_conn->saturation)
1476 UPDATE_PROPERTY(conn_state->tv.saturation, SATURATION);
1477
1478 if (intel_sdvo_conn->contrast)
1479 UPDATE_PROPERTY(conn_state->tv.contrast, CONTRAST);
1480
1481 if (intel_sdvo_conn->hue)
1482 UPDATE_PROPERTY(conn_state->tv.hue, HUE);
1483
1484 if (intel_sdvo_conn->brightness)
1485 UPDATE_PROPERTY(conn_state->tv.brightness, BRIGHTNESS);
1486
1487 if (intel_sdvo_conn->sharpness)
1488 UPDATE_PROPERTY(sdvo_state->tv.sharpness, SHARPNESS);
1489
1490 if (intel_sdvo_conn->flicker_filter)
1491 UPDATE_PROPERTY(sdvo_state->tv.flicker_filter, FLICKER_FILTER);
1492
1493 if (intel_sdvo_conn->flicker_filter_2d)
1494 UPDATE_PROPERTY(sdvo_state->tv.flicker_filter_2d, FLICKER_FILTER_2D);
1495
1496 if (intel_sdvo_conn->flicker_filter_adaptive)
1497 UPDATE_PROPERTY(sdvo_state->tv.flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
1498
1499 if (intel_sdvo_conn->tv_chroma_filter)
1500 UPDATE_PROPERTY(sdvo_state->tv.chroma_filter, TV_CHROMA_FILTER);
1501
1502 if (intel_sdvo_conn->tv_luma_filter)
1503 UPDATE_PROPERTY(sdvo_state->tv.luma_filter, TV_LUMA_FILTER);
1504
1505 if (intel_sdvo_conn->dot_crawl)
1506 UPDATE_PROPERTY(sdvo_state->tv.dot_crawl, DOT_CRAWL);
1507
1508 #undef UPDATE_PROPERTY
1509 }
1510
1511 static void intel_sdvo_pre_enable(struct intel_atomic_state *state,
1512 struct intel_encoder *intel_encoder,
1513 const struct intel_crtc_state *crtc_state,
1514 const struct drm_connector_state *conn_state)
1515 {
1516 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
1517 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1518 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
1519 const struct intel_sdvo_connector_state *sdvo_state =
1520 to_intel_sdvo_connector_state(conn_state);
1521 struct intel_sdvo_connector *intel_sdvo_connector =
1522 to_intel_sdvo_connector(conn_state->connector);
1523 const struct drm_display_mode *mode = &crtc_state->hw.mode;
1524 struct intel_sdvo *intel_sdvo = to_sdvo(intel_encoder);
1525 u32 sdvox;
1526 struct intel_sdvo_in_out_map in_out;
1527 struct intel_sdvo_dtd input_dtd, output_dtd;
1528 int rate;
1529
1530 intel_sdvo_update_props(intel_sdvo, sdvo_state);
1531
1532 /*
1533 * First, set the input mapping for the first input to our controlled
1534 * output. This is only correct if we're a single-input device, in
1535 * which case the first input is the output from the appropriate SDVO
1536 * channel on the motherboard. In a two-input device, the first input
1537 * will be SDVOB and the second SDVOC.
1538 */
1539 in_out.in0 = intel_sdvo_connector->output_flag;
1540 in_out.in1 = 0;
1541
1542 intel_sdvo_set_value(intel_sdvo,
1543 SDVO_CMD_SET_IN_OUT_MAP,
1544 &in_out, sizeof(in_out));
1545
1546 /* Set the output timings to the screen */
1547 if (!intel_sdvo_set_target_output(intel_sdvo,
1548 intel_sdvo_connector->output_flag))
1549 return;
1550
1551 /* lvds has a special fixed output timing. */
1552 if (IS_LVDS(intel_sdvo_connector)) {
1553 const struct drm_display_mode *fixed_mode =
1554 intel_panel_fixed_mode(&intel_sdvo_connector->base, mode);
1555
1556 intel_sdvo_get_dtd_from_mode(&output_dtd, fixed_mode);
1557 } else {
1558 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
1559 }
1560 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1561 drm_info(&dev_priv->drm,
1562 "Setting output timings on %s failed\n",
1563 SDVO_NAME(intel_sdvo));
1564
1565 /* Set the input timing to the screen. Assume always input 0. */
1566 if (!intel_sdvo_set_target_input(intel_sdvo))
1567 return;
1568
1569 if (crtc_state->has_hdmi_sink) {
1570 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
1571 intel_sdvo_set_colorimetry(intel_sdvo,
1572 crtc_state->limited_color_range ?
1573 SDVO_COLORIMETRY_RGB220 :
1574 SDVO_COLORIMETRY_RGB256);
1575 intel_sdvo_set_avi_infoframe(intel_sdvo, crtc_state);
1576 intel_sdvo_set_pixel_replication(intel_sdvo,
1577 !!(adjusted_mode->flags &
1578 DRM_MODE_FLAG_DBLCLK));
1579 } else
1580 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI);
1581
1582 if (IS_TV(intel_sdvo_connector) &&
1583 !intel_sdvo_set_tv_format(intel_sdvo, conn_state))
1584 return;
1585
1586 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
1587
1588 if (IS_TV(intel_sdvo_connector) || IS_LVDS(intel_sdvo_connector))
1589 input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags;
1590 if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd))
1591 drm_info(&dev_priv->drm,
1592 "Setting input timings on %s failed\n",
1593 SDVO_NAME(intel_sdvo));
1594
1595 switch (crtc_state->pixel_multiplier) {
1596 default:
1597 drm_WARN(&dev_priv->drm, 1,
1598 "unknown pixel multiplier specified\n");
1599 fallthrough;
1600 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
1601 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
1602 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
1603 }
1604 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
1605 return;
1606
1607 /* Set the SDVO control regs. */
1608 if (DISPLAY_VER(dev_priv) >= 4) {
1609 /* The real mode polarity is set by the SDVO commands, using
1610 * struct intel_sdvo_dtd. */
1611 sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
1612 if (DISPLAY_VER(dev_priv) < 5)
1613 sdvox |= SDVO_BORDER_ENABLE;
1614 } else {
1615 sdvox = intel_de_read(dev_priv, intel_sdvo->sdvo_reg);
1616 if (intel_sdvo->base.port == PORT_B)
1617 sdvox &= SDVOB_PRESERVE_MASK;
1618 else
1619 sdvox &= SDVOC_PRESERVE_MASK;
1620 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1621 }
1622
1623 if (HAS_PCH_CPT(dev_priv))
1624 sdvox |= SDVO_PIPE_SEL_CPT(crtc->pipe);
1625 else
1626 sdvox |= SDVO_PIPE_SEL(crtc->pipe);
1627
1628 if (DISPLAY_VER(dev_priv) >= 4) {
1629 /* done in crtc_mode_set as the dpll_md reg must be written early */
1630 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
1631 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
1632 /* done in crtc_mode_set as it lives inside the dpll register */
1633 } else {
1634 sdvox |= (crtc_state->pixel_multiplier - 1)
1635 << SDVO_PORT_MULTIPLY_SHIFT;
1636 }
1637
1638 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
1639 DISPLAY_VER(dev_priv) < 5)
1640 sdvox |= SDVO_STALL_SELECT;
1641 intel_sdvo_write_sdvox(intel_sdvo, sdvox);
1642 }
1643
1644 static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector)
1645 {
1646 struct intel_sdvo_connector *intel_sdvo_connector =
1647 to_intel_sdvo_connector(&connector->base);
1648 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1649 u16 active_outputs = 0;
1650
1651 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
1652
1653 return active_outputs & intel_sdvo_connector->output_flag;
1654 }
1655
1656 bool intel_sdvo_port_enabled(struct drm_i915_private *dev_priv,
1657 i915_reg_t sdvo_reg, enum pipe *pipe)
1658 {
1659 u32 val;
1660
1661 val = intel_de_read(dev_priv, sdvo_reg);
1662
1663 /* asserts want to know the pipe even if the port is disabled */
1664 if (HAS_PCH_CPT(dev_priv))
1665 *pipe = (val & SDVO_PIPE_SEL_MASK_CPT) >> SDVO_PIPE_SEL_SHIFT_CPT;
1666 else if (IS_CHERRYVIEW(dev_priv))
1667 *pipe = (val & SDVO_PIPE_SEL_MASK_CHV) >> SDVO_PIPE_SEL_SHIFT_CHV;
1668 else
1669 *pipe = (val & SDVO_PIPE_SEL_MASK) >> SDVO_PIPE_SEL_SHIFT;
1670
1671 return val & SDVO_ENABLE;
1672 }
1673
1674 static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder,
1675 enum pipe *pipe)
1676 {
1677 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1678 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1679 u16 active_outputs = 0;
1680 bool ret;
1681
1682 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
1683
1684 ret = intel_sdvo_port_enabled(dev_priv, intel_sdvo->sdvo_reg, pipe);
1685
1686 return ret || active_outputs;
1687 }
1688
1689 static void intel_sdvo_get_config(struct intel_encoder *encoder,
1690 struct intel_crtc_state *pipe_config)
1691 {
1692 struct drm_device *dev = encoder->base.dev;
1693 struct drm_i915_private *dev_priv = to_i915(dev);
1694 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1695 struct intel_sdvo_dtd dtd;
1696 int encoder_pixel_multiplier = 0;
1697 int dotclock;
1698 u32 flags = 0, sdvox;
1699 u8 val;
1700 bool ret;
1701
1702 pipe_config->output_types |= BIT(INTEL_OUTPUT_SDVO);
1703
1704 sdvox = intel_de_read(dev_priv, intel_sdvo->sdvo_reg);
1705
1706 ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd);
1707 if (!ret) {
1708 /*
1709 * Some sdvo encoders are not spec compliant and don't
1710 * implement the mandatory get_timings function.
1711 */
1712 drm_dbg(&dev_priv->drm, "failed to retrieve SDVO DTD\n");
1713 pipe_config->quirks |= PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS;
1714 } else {
1715 if (dtd.part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
1716 flags |= DRM_MODE_FLAG_PHSYNC;
1717 else
1718 flags |= DRM_MODE_FLAG_NHSYNC;
1719
1720 if (dtd.part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
1721 flags |= DRM_MODE_FLAG_PVSYNC;
1722 else
1723 flags |= DRM_MODE_FLAG_NVSYNC;
1724 }
1725
1726 pipe_config->hw.adjusted_mode.flags |= flags;
1727
1728 /*
1729 * pixel multiplier readout is tricky: Only on i915g/gm it is stored in
1730 * the sdvo port register, on all other platforms it is part of the dpll
1731 * state. Since the general pipe state readout happens before the
1732 * encoder->get_config we so already have a valid pixel multplier on all
1733 * other platfroms.
1734 */
1735 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
1736 pipe_config->pixel_multiplier =
1737 ((sdvox & SDVO_PORT_MULTIPLY_MASK)
1738 >> SDVO_PORT_MULTIPLY_SHIFT) + 1;
1739 }
1740
1741 dotclock = pipe_config->port_clock;
1742
1743 if (pipe_config->pixel_multiplier)
1744 dotclock /= pipe_config->pixel_multiplier;
1745
1746 pipe_config->hw.adjusted_mode.crtc_clock = dotclock;
1747
1748 /* Cross check the port pixel multiplier with the sdvo encoder state. */
1749 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT,
1750 &val, 1)) {
1751 switch (val) {
1752 case SDVO_CLOCK_RATE_MULT_1X:
1753 encoder_pixel_multiplier = 1;
1754 break;
1755 case SDVO_CLOCK_RATE_MULT_2X:
1756 encoder_pixel_multiplier = 2;
1757 break;
1758 case SDVO_CLOCK_RATE_MULT_4X:
1759 encoder_pixel_multiplier = 4;
1760 break;
1761 }
1762 }
1763
1764 drm_WARN(dev,
1765 encoder_pixel_multiplier != pipe_config->pixel_multiplier,
1766 "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n",
1767 pipe_config->pixel_multiplier, encoder_pixel_multiplier);
1768
1769 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_COLORIMETRY,
1770 &val, 1)) {
1771 if (val == SDVO_COLORIMETRY_RGB220)
1772 pipe_config->limited_color_range = true;
1773 }
1774
1775 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_AUDIO_STAT,
1776 &val, 1)) {
1777 if (val & SDVO_AUDIO_PRESENCE_DETECT)
1778 pipe_config->has_audio = true;
1779 }
1780
1781 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ENCODE,
1782 &val, 1)) {
1783 if (val == SDVO_ENCODE_HDMI)
1784 pipe_config->has_hdmi_sink = true;
1785 }
1786
1787 intel_sdvo_get_avi_infoframe(intel_sdvo, pipe_config);
1788
1789 intel_sdvo_get_eld(intel_sdvo, pipe_config);
1790 }
1791
1792 static void intel_sdvo_disable_audio(struct intel_encoder *encoder,
1793 const struct intel_crtc_state *old_crtc_state,
1794 const struct drm_connector_state *old_conn_state)
1795 {
1796 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1797
1798 if (!old_crtc_state->has_audio)
1799 return;
1800
1801 intel_sdvo_set_audio_state(intel_sdvo, 0);
1802 }
1803
1804 static void intel_sdvo_enable_audio(struct intel_encoder *encoder,
1805 const struct intel_crtc_state *crtc_state,
1806 const struct drm_connector_state *conn_state)
1807 {
1808 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1809 const u8 *eld = crtc_state->eld;
1810
1811 if (!crtc_state->has_audio)
1812 return;
1813
1814 intel_sdvo_set_audio_state(intel_sdvo, 0);
1815
1816 intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_ELD,
1817 SDVO_HBUF_TX_DISABLED,
1818 eld, drm_eld_size(eld));
1819
1820 intel_sdvo_set_audio_state(intel_sdvo, SDVO_AUDIO_ELD_VALID |
1821 SDVO_AUDIO_PRESENCE_DETECT);
1822 }
1823
1824 static void intel_disable_sdvo(struct intel_atomic_state *state,
1825 struct intel_encoder *encoder,
1826 const struct intel_crtc_state *old_crtc_state,
1827 const struct drm_connector_state *conn_state)
1828 {
1829 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1830 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1831 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1832 u32 temp;
1833
1834 encoder->audio_disable(encoder, old_crtc_state, conn_state);
1835
1836 intel_sdvo_set_active_outputs(intel_sdvo, 0);
1837 if (0)
1838 intel_sdvo_set_encoder_power_state(intel_sdvo,
1839 DRM_MODE_DPMS_OFF);
1840
1841 temp = intel_de_read(dev_priv, intel_sdvo->sdvo_reg);
1842
1843 temp &= ~SDVO_ENABLE;
1844 intel_sdvo_write_sdvox(intel_sdvo, temp);
1845
1846 /*
1847 * HW workaround for IBX, we need to move the port
1848 * to transcoder A after disabling it to allow the
1849 * matching DP port to be enabled on transcoder A.
1850 */
1851 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {
1852 /*
1853 * We get CPU/PCH FIFO underruns on the other pipe when
1854 * doing the workaround. Sweep them under the rug.
1855 */
1856 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1857 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1858
1859 temp &= ~SDVO_PIPE_SEL_MASK;
1860 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A);
1861 intel_sdvo_write_sdvox(intel_sdvo, temp);
1862
1863 temp &= ~SDVO_ENABLE;
1864 intel_sdvo_write_sdvox(intel_sdvo, temp);
1865
1866 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
1867 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1868 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1869 }
1870 }
1871
1872 static void pch_disable_sdvo(struct intel_atomic_state *state,
1873 struct intel_encoder *encoder,
1874 const struct intel_crtc_state *old_crtc_state,
1875 const struct drm_connector_state *old_conn_state)
1876 {
1877 }
1878
1879 static void pch_post_disable_sdvo(struct intel_atomic_state *state,
1880 struct intel_encoder *encoder,
1881 const struct intel_crtc_state *old_crtc_state,
1882 const struct drm_connector_state *old_conn_state)
1883 {
1884 intel_disable_sdvo(state, encoder, old_crtc_state, old_conn_state);
1885 }
1886
1887 static void intel_enable_sdvo(struct intel_atomic_state *state,
1888 struct intel_encoder *encoder,
1889 const struct intel_crtc_state *pipe_config,
1890 const struct drm_connector_state *conn_state)
1891 {
1892 struct drm_device *dev = encoder->base.dev;
1893 struct drm_i915_private *dev_priv = to_i915(dev);
1894 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1895 struct intel_sdvo_connector *intel_sdvo_connector =
1896 to_intel_sdvo_connector(conn_state->connector);
1897 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
1898 u32 temp;
1899 bool input1, input2;
1900 int i;
1901 bool success;
1902
1903 temp = intel_de_read(dev_priv, intel_sdvo->sdvo_reg);
1904 temp |= SDVO_ENABLE;
1905 intel_sdvo_write_sdvox(intel_sdvo, temp);
1906
1907 for (i = 0; i < 2; i++)
1908 intel_crtc_wait_for_next_vblank(crtc);
1909
1910 success = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
1911 /*
1912 * Warn if the device reported failure to sync.
1913 *
1914 * A lot of SDVO devices fail to notify of sync, but it's
1915 * a given it the status is a success, we succeeded.
1916 */
1917 if (success && !input1) {
1918 drm_dbg_kms(&dev_priv->drm,
1919 "First %s output reported failure to "
1920 "sync\n", SDVO_NAME(intel_sdvo));
1921 }
1922
1923 if (0)
1924 intel_sdvo_set_encoder_power_state(intel_sdvo,
1925 DRM_MODE_DPMS_ON);
1926 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo_connector->output_flag);
1927
1928 encoder->audio_enable(encoder, pipe_config, conn_state);
1929 }
1930
1931 static enum drm_mode_status
1932 intel_sdvo_mode_valid(struct drm_connector *connector,
1933 struct drm_display_mode *mode)
1934 {
1935 struct drm_i915_private *i915 = to_i915(connector->dev);
1936 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector));
1937 struct intel_sdvo_connector *intel_sdvo_connector =
1938 to_intel_sdvo_connector(connector);
1939 bool has_hdmi_sink = intel_has_hdmi_sink(intel_sdvo_connector, connector->state);
1940 int max_dotclk = i915->max_dotclk_freq;
1941 enum drm_mode_status status;
1942 int clock = mode->clock;
1943
1944 status = intel_cpu_transcoder_mode_valid(i915, mode);
1945 if (status != MODE_OK)
1946 return status;
1947
1948 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1949 return MODE_NO_DBLESCAN;
1950
1951 if (clock > max_dotclk)
1952 return MODE_CLOCK_HIGH;
1953
1954 if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
1955 if (!has_hdmi_sink)
1956 return MODE_CLOCK_LOW;
1957 clock *= 2;
1958 }
1959
1960 if (intel_sdvo->pixel_clock_min > clock)
1961 return MODE_CLOCK_LOW;
1962
1963 if (intel_sdvo->pixel_clock_max < clock)
1964 return MODE_CLOCK_HIGH;
1965
1966 if (IS_LVDS(intel_sdvo_connector)) {
1967 enum drm_mode_status status;
1968
1969 status = intel_panel_mode_valid(&intel_sdvo_connector->base, mode);
1970 if (status != MODE_OK)
1971 return status;
1972 }
1973
1974 return MODE_OK;
1975 }
1976
1977 static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
1978 {
1979 BUILD_BUG_ON(sizeof(*caps) != 8);
1980 if (!intel_sdvo_get_value(intel_sdvo,
1981 SDVO_CMD_GET_DEVICE_CAPS,
1982 caps, sizeof(*caps)))
1983 return false;
1984
1985 DRM_DEBUG_KMS("SDVO capabilities:\n"
1986 " vendor_id: %d\n"
1987 " device_id: %d\n"
1988 " device_rev_id: %d\n"
1989 " sdvo_version_major: %d\n"
1990 " sdvo_version_minor: %d\n"
1991 " sdvo_num_inputs: %d\n"
1992 " smooth_scaling: %d\n"
1993 " sharp_scaling: %d\n"
1994 " up_scaling: %d\n"
1995 " down_scaling: %d\n"
1996 " stall_support: %d\n"
1997 " output_flags: %d\n",
1998 caps->vendor_id,
1999 caps->device_id,
2000 caps->device_rev_id,
2001 caps->sdvo_version_major,
2002 caps->sdvo_version_minor,
2003 caps->sdvo_num_inputs,
2004 caps->smooth_scaling,
2005 caps->sharp_scaling,
2006 caps->up_scaling,
2007 caps->down_scaling,
2008 caps->stall_support,
2009 caps->output_flags);
2010
2011 return true;
2012 }
2013
2014 static u8 intel_sdvo_get_colorimetry_cap(struct intel_sdvo *intel_sdvo)
2015 {
2016 u8 cap;
2017
2018 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_COLORIMETRY_CAP,
2019 &cap, sizeof(cap)))
2020 return SDVO_COLORIMETRY_RGB256;
2021
2022 return cap;
2023 }
2024
2025 static u16 intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo)
2026 {
2027 struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev);
2028 u16 hotplug;
2029
2030 if (!I915_HAS_HOTPLUG(dev_priv))
2031 return 0;
2032
2033 /*
2034 * HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise
2035 * on the line.
2036 */
2037 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
2038 return 0;
2039
2040 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
2041 &hotplug, sizeof(hotplug)))
2042 return 0;
2043
2044 return hotplug;
2045 }
2046
2047 static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder)
2048 {
2049 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
2050
2051 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG,
2052 &intel_sdvo->hotplug_active, 2);
2053 }
2054
2055 static enum intel_hotplug_state
2056 intel_sdvo_hotplug(struct intel_encoder *encoder,
2057 struct intel_connector *connector)
2058 {
2059 intel_sdvo_enable_hotplug(encoder);
2060
2061 return intel_encoder_hotplug(encoder, connector);
2062 }
2063
2064 static const struct drm_edid *
2065 intel_sdvo_get_edid(struct drm_connector *connector)
2066 {
2067 struct i2c_adapter *ddc = connector->ddc;
2068
2069 if (!ddc)
2070 return NULL;
2071
2072 return drm_edid_read_ddc(connector, ddc);
2073 }
2074
2075 /* Mac mini hack -- use the same DDC as the analog connector */
2076 static const struct drm_edid *
2077 intel_sdvo_get_analog_edid(struct drm_connector *connector)
2078 {
2079 struct drm_i915_private *i915 = to_i915(connector->dev);
2080 struct i2c_adapter *ddc;
2081
2082 ddc = intel_gmbus_get_adapter(i915, i915->display.vbt.crt_ddc_pin);
2083 if (!ddc)
2084 return NULL;
2085
2086 return drm_edid_read_ddc(connector, ddc);
2087 }
2088
2089 static enum drm_connector_status
2090 intel_sdvo_tmds_sink_detect(struct drm_connector *connector)
2091 {
2092 enum drm_connector_status status;
2093 const struct drm_edid *drm_edid;
2094
2095 drm_edid = intel_sdvo_get_edid(connector);
2096
2097 /*
2098 * When there is no edid and no monitor is connected with VGA
2099 * port, try to use the CRT ddc to read the EDID for DVI-connector.
2100 */
2101 if (!drm_edid)
2102 drm_edid = intel_sdvo_get_analog_edid(connector);
2103
2104 status = connector_status_unknown;
2105 if (drm_edid) {
2106 /* DDC bus is shared, match EDID to connector type */
2107 if (drm_edid_is_digital(drm_edid))
2108 status = connector_status_connected;
2109 else
2110 status = connector_status_disconnected;
2111 drm_edid_free(drm_edid);
2112 }
2113
2114 return status;
2115 }
2116
2117 static bool
2118 intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo,
2119 const struct drm_edid *drm_edid)
2120 {
2121 bool monitor_is_digital = drm_edid_is_digital(drm_edid);
2122 bool connector_is_digital = !!IS_DIGITAL(sdvo);
2123
2124 DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n",
2125 connector_is_digital, monitor_is_digital);
2126 return connector_is_digital == monitor_is_digital;
2127 }
2128
2129 static enum drm_connector_status
2130 intel_sdvo_detect(struct drm_connector *connector, bool force)
2131 {
2132 struct drm_i915_private *i915 = to_i915(connector->dev);
2133 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector));
2134 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
2135 enum drm_connector_status ret;
2136 u16 response;
2137
2138 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
2139 connector->base.id, connector->name);
2140
2141 if (!intel_display_device_enabled(i915))
2142 return connector_status_disconnected;
2143
2144 if (!intel_display_driver_check_access(i915))
2145 return connector->status;
2146
2147 if (!intel_sdvo_set_target_output(intel_sdvo,
2148 intel_sdvo_connector->output_flag))
2149 return connector_status_unknown;
2150
2151 if (!intel_sdvo_get_value(intel_sdvo,
2152 SDVO_CMD_GET_ATTACHED_DISPLAYS,
2153 &response, 2))
2154 return connector_status_unknown;
2155
2156 DRM_DEBUG_KMS("SDVO response %d %d [%x]\n",
2157 response & 0xff, response >> 8,
2158 intel_sdvo_connector->output_flag);
2159
2160 if (response == 0)
2161 return connector_status_disconnected;
2162
2163 if ((intel_sdvo_connector->output_flag & response) == 0)
2164 ret = connector_status_disconnected;
2165 else if (IS_TMDS(intel_sdvo_connector))
2166 ret = intel_sdvo_tmds_sink_detect(connector);
2167 else {
2168 const struct drm_edid *drm_edid;
2169
2170 /* if we have an edid check it matches the connection */
2171 drm_edid = intel_sdvo_get_edid(connector);
2172 if (!drm_edid)
2173 drm_edid = intel_sdvo_get_analog_edid(connector);
2174 if (drm_edid) {
2175 if (intel_sdvo_connector_matches_edid(intel_sdvo_connector,
2176 drm_edid))
2177 ret = connector_status_connected;
2178 else
2179 ret = connector_status_disconnected;
2180
2181 drm_edid_free(drm_edid);
2182 } else {
2183 ret = connector_status_connected;
2184 }
2185 }
2186
2187 return ret;
2188 }
2189
2190 static int intel_sdvo_get_ddc_modes(struct drm_connector *connector)
2191 {
2192 int num_modes = 0;
2193 const struct drm_edid *drm_edid;
2194
2195 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
2196 connector->base.id, connector->name);
2197
2198 /* set the bus switch and get the modes */
2199 drm_edid = intel_sdvo_get_edid(connector);
2200
2201 /*
2202 * Mac mini hack. On this device, the DVI-I connector shares one DDC
2203 * link between analog and digital outputs. So, if the regular SDVO
2204 * DDC fails, check to see if the analog output is disconnected, in
2205 * which case we'll look there for the digital DDC data.
2206 */
2207 if (!drm_edid)
2208 drm_edid = intel_sdvo_get_analog_edid(connector);
2209
2210 if (!drm_edid)
2211 return 0;
2212
2213 if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector),
2214 drm_edid))
2215 num_modes += intel_connector_update_modes(connector, drm_edid);
2216
2217 drm_edid_free(drm_edid);
2218
2219 return num_modes;
2220 }
2221
2222 /*
2223 * Set of SDVO TV modes.
2224 * Note! This is in reply order (see loop in get_tv_modes).
2225 * XXX: all 60Hz refresh?
2226 */
2227 static const struct drm_display_mode sdvo_tv_modes[] = {
2228 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
2229 416, 0, 200, 201, 232, 233, 0,
2230 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2231 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
2232 416, 0, 240, 241, 272, 273, 0,
2233 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2234 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
2235 496, 0, 300, 301, 332, 333, 0,
2236 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2237 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
2238 736, 0, 350, 351, 382, 383, 0,
2239 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2240 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
2241 736, 0, 400, 401, 432, 433, 0,
2242 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2243 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
2244 736, 0, 480, 481, 512, 513, 0,
2245 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2246 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
2247 800, 0, 480, 481, 512, 513, 0,
2248 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2249 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
2250 800, 0, 576, 577, 608, 609, 0,
2251 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2252 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
2253 816, 0, 350, 351, 382, 383, 0,
2254 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2255 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
2256 816, 0, 400, 401, 432, 433, 0,
2257 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2258 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
2259 816, 0, 480, 481, 512, 513, 0,
2260 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2261 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
2262 816, 0, 540, 541, 572, 573, 0,
2263 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2264 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
2265 816, 0, 576, 577, 608, 609, 0,
2266 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2267 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
2268 864, 0, 576, 577, 608, 609, 0,
2269 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2270 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
2271 896, 0, 600, 601, 632, 633, 0,
2272 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2273 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
2274 928, 0, 624, 625, 656, 657, 0,
2275 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2276 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
2277 1016, 0, 766, 767, 798, 799, 0,
2278 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2279 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
2280 1120, 0, 768, 769, 800, 801, 0,
2281 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2282 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
2283 1376, 0, 1024, 1025, 1056, 1057, 0,
2284 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2285 };
2286
2287 static int intel_sdvo_get_tv_modes(struct drm_connector *connector)
2288 {
2289 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector));
2290 struct intel_sdvo_connector *intel_sdvo_connector =
2291 to_intel_sdvo_connector(connector);
2292 const struct drm_connector_state *conn_state = connector->state;
2293 struct intel_sdvo_sdtv_resolution_request tv_res;
2294 u32 reply = 0, format_map = 0;
2295 int num_modes = 0;
2296 int i;
2297
2298 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
2299 connector->base.id, connector->name);
2300
2301 /*
2302 * Read the list of supported input resolutions for the selected TV
2303 * format.
2304 */
2305 format_map = 1 << conn_state->tv.legacy_mode;
2306 memcpy(&tv_res, &format_map,
2307 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
2308
2309 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo_connector->output_flag))
2310 return 0;
2311
2312 BUILD_BUG_ON(sizeof(tv_res) != 3);
2313 if (!intel_sdvo_write_cmd(intel_sdvo,
2314 SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
2315 &tv_res, sizeof(tv_res)))
2316 return 0;
2317 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
2318 return 0;
2319
2320 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++) {
2321 if (reply & (1 << i)) {
2322 struct drm_display_mode *nmode;
2323 nmode = drm_mode_duplicate(connector->dev,
2324 &sdvo_tv_modes[i]);
2325 if (nmode) {
2326 drm_mode_probed_add(connector, nmode);
2327 num_modes++;
2328 }
2329 }
2330 }
2331
2332 return num_modes;
2333 }
2334
2335 static int intel_sdvo_get_lvds_modes(struct drm_connector *connector)
2336 {
2337 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2338
2339 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
2340 connector->base.id, connector->name);
2341
2342 return intel_panel_get_modes(to_intel_connector(connector));
2343 }
2344
2345 static int intel_sdvo_get_modes(struct drm_connector *connector)
2346 {
2347 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
2348
2349 if (IS_TV(intel_sdvo_connector))
2350 return intel_sdvo_get_tv_modes(connector);
2351 else if (IS_LVDS(intel_sdvo_connector))
2352 return intel_sdvo_get_lvds_modes(connector);
2353 else
2354 return intel_sdvo_get_ddc_modes(connector);
2355 }
2356
2357 static int
2358 intel_sdvo_connector_atomic_get_property(struct drm_connector *connector,
2359 const struct drm_connector_state *state,
2360 struct drm_property *property,
2361 u64 *val)
2362 {
2363 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
2364 const struct intel_sdvo_connector_state *sdvo_state = to_intel_sdvo_connector_state((void *)state);
2365
2366 if (property == intel_sdvo_connector->tv_format) {
2367 int i;
2368
2369 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
2370 if (state->tv.legacy_mode == intel_sdvo_connector->tv_format_supported[i]) {
2371 *val = i;
2372
2373 return 0;
2374 }
2375
2376 drm_WARN_ON(connector->dev, 1);
2377 *val = 0;
2378 } else if (property == intel_sdvo_connector->top ||
2379 property == intel_sdvo_connector->bottom)
2380 *val = intel_sdvo_connector->max_vscan - sdvo_state->tv.overscan_v;
2381 else if (property == intel_sdvo_connector->left ||
2382 property == intel_sdvo_connector->right)
2383 *val = intel_sdvo_connector->max_hscan - sdvo_state->tv.overscan_h;
2384 else if (property == intel_sdvo_connector->hpos)
2385 *val = sdvo_state->tv.hpos;
2386 else if (property == intel_sdvo_connector->vpos)
2387 *val = sdvo_state->tv.vpos;
2388 else if (property == intel_sdvo_connector->saturation)
2389 *val = state->tv.saturation;
2390 else if (property == intel_sdvo_connector->contrast)
2391 *val = state->tv.contrast;
2392 else if (property == intel_sdvo_connector->hue)
2393 *val = state->tv.hue;
2394 else if (property == intel_sdvo_connector->brightness)
2395 *val = state->tv.brightness;
2396 else if (property == intel_sdvo_connector->sharpness)
2397 *val = sdvo_state->tv.sharpness;
2398 else if (property == intel_sdvo_connector->flicker_filter)
2399 *val = sdvo_state->tv.flicker_filter;
2400 else if (property == intel_sdvo_connector->flicker_filter_2d)
2401 *val = sdvo_state->tv.flicker_filter_2d;
2402 else if (property == intel_sdvo_connector->flicker_filter_adaptive)
2403 *val = sdvo_state->tv.flicker_filter_adaptive;
2404 else if (property == intel_sdvo_connector->tv_chroma_filter)
2405 *val = sdvo_state->tv.chroma_filter;
2406 else if (property == intel_sdvo_connector->tv_luma_filter)
2407 *val = sdvo_state->tv.luma_filter;
2408 else if (property == intel_sdvo_connector->dot_crawl)
2409 *val = sdvo_state->tv.dot_crawl;
2410 else
2411 return intel_digital_connector_atomic_get_property(connector, state, property, val);
2412
2413 return 0;
2414 }
2415
2416 static int
2417 intel_sdvo_connector_atomic_set_property(struct drm_connector *connector,
2418 struct drm_connector_state *state,
2419 struct drm_property *property,
2420 u64 val)
2421 {
2422 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
2423 struct intel_sdvo_connector_state *sdvo_state = to_intel_sdvo_connector_state(state);
2424
2425 if (property == intel_sdvo_connector->tv_format) {
2426 state->tv.legacy_mode = intel_sdvo_connector->tv_format_supported[val];
2427
2428 if (state->crtc) {
2429 struct drm_crtc_state *crtc_state =
2430 drm_atomic_get_new_crtc_state(state->state, state->crtc);
2431
2432 crtc_state->connectors_changed = true;
2433 }
2434 } else if (property == intel_sdvo_connector->top ||
2435 property == intel_sdvo_connector->bottom)
2436 /* Cannot set these independent from each other */
2437 sdvo_state->tv.overscan_v = intel_sdvo_connector->max_vscan - val;
2438 else if (property == intel_sdvo_connector->left ||
2439 property == intel_sdvo_connector->right)
2440 /* Cannot set these independent from each other */
2441 sdvo_state->tv.overscan_h = intel_sdvo_connector->max_hscan - val;
2442 else if (property == intel_sdvo_connector->hpos)
2443 sdvo_state->tv.hpos = val;
2444 else if (property == intel_sdvo_connector->vpos)
2445 sdvo_state->tv.vpos = val;
2446 else if (property == intel_sdvo_connector->saturation)
2447 state->tv.saturation = val;
2448 else if (property == intel_sdvo_connector->contrast)
2449 state->tv.contrast = val;
2450 else if (property == intel_sdvo_connector->hue)
2451 state->tv.hue = val;
2452 else if (property == intel_sdvo_connector->brightness)
2453 state->tv.brightness = val;
2454 else if (property == intel_sdvo_connector->sharpness)
2455 sdvo_state->tv.sharpness = val;
2456 else if (property == intel_sdvo_connector->flicker_filter)
2457 sdvo_state->tv.flicker_filter = val;
2458 else if (property == intel_sdvo_connector->flicker_filter_2d)
2459 sdvo_state->tv.flicker_filter_2d = val;
2460 else if (property == intel_sdvo_connector->flicker_filter_adaptive)
2461 sdvo_state->tv.flicker_filter_adaptive = val;
2462 else if (property == intel_sdvo_connector->tv_chroma_filter)
2463 sdvo_state->tv.chroma_filter = val;
2464 else if (property == intel_sdvo_connector->tv_luma_filter)
2465 sdvo_state->tv.luma_filter = val;
2466 else if (property == intel_sdvo_connector->dot_crawl)
2467 sdvo_state->tv.dot_crawl = val;
2468 else
2469 return intel_digital_connector_atomic_set_property(connector, state, property, val);
2470
2471 return 0;
2472 }
2473
2474 static struct drm_connector_state *
2475 intel_sdvo_connector_duplicate_state(struct drm_connector *connector)
2476 {
2477 struct intel_sdvo_connector_state *state;
2478
2479 state = kmemdup(connector->state, sizeof(*state), GFP_KERNEL);
2480 if (!state)
2481 return NULL;
2482
2483 __drm_atomic_helper_connector_duplicate_state(connector, &state->base.base);
2484 return &state->base.base;
2485 }
2486
2487 static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
2488 .detect = intel_sdvo_detect,
2489 .fill_modes = drm_helper_probe_single_connector_modes,
2490 .atomic_get_property = intel_sdvo_connector_atomic_get_property,
2491 .atomic_set_property = intel_sdvo_connector_atomic_set_property,
2492 .late_register = intel_connector_register,
2493 .early_unregister = intel_connector_unregister,
2494 .destroy = intel_connector_destroy,
2495 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2496 .atomic_duplicate_state = intel_sdvo_connector_duplicate_state,
2497 };
2498
2499 static int intel_sdvo_atomic_check(struct drm_connector *conn,
2500 struct drm_atomic_state *state)
2501 {
2502 struct drm_connector_state *new_conn_state =
2503 drm_atomic_get_new_connector_state(state, conn);
2504 struct drm_connector_state *old_conn_state =
2505 drm_atomic_get_old_connector_state(state, conn);
2506 struct intel_sdvo_connector_state *old_state =
2507 to_intel_sdvo_connector_state(old_conn_state);
2508 struct intel_sdvo_connector_state *new_state =
2509 to_intel_sdvo_connector_state(new_conn_state);
2510
2511 if (new_conn_state->crtc &&
2512 (memcmp(&old_state->tv, &new_state->tv, sizeof(old_state->tv)) ||
2513 memcmp(&old_conn_state->tv, &new_conn_state->tv, sizeof(old_conn_state->tv)))) {
2514 struct drm_crtc_state *crtc_state =
2515 drm_atomic_get_new_crtc_state(state,
2516 new_conn_state->crtc);
2517
2518 crtc_state->connectors_changed = true;
2519 }
2520
2521 return intel_digital_connector_atomic_check(conn, state);
2522 }
2523
2524 static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
2525 .get_modes = intel_sdvo_get_modes,
2526 .mode_valid = intel_sdvo_mode_valid,
2527 .atomic_check = intel_sdvo_atomic_check,
2528 };
2529
2530 static void intel_sdvo_encoder_destroy(struct drm_encoder *_encoder)
2531 {
2532 struct intel_encoder *encoder = to_intel_encoder(_encoder);
2533 struct intel_sdvo *sdvo = to_sdvo(encoder);
2534 int i;
2535
2536 for (i = 0; i < ARRAY_SIZE(sdvo->ddc); i++) {
2537 if (sdvo->ddc[i].ddc_bus)
2538 i2c_del_adapter(&sdvo->ddc[i].ddc);
2539 }
2540
2541 drm_encoder_cleanup(&encoder->base);
2542 kfree(sdvo);
2543 };
2544
2545 static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
2546 .destroy = intel_sdvo_encoder_destroy,
2547 };
2548
2549 static int
2550 intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo,
2551 struct intel_sdvo_connector *connector)
2552 {
2553 u16 mask = 0;
2554 int num_bits;
2555
2556 /*
2557 * Make a mask of outputs less than or equal to our own priority in the
2558 * list.
2559 */
2560 switch (connector->output_flag) {
2561 case SDVO_OUTPUT_LVDS1:
2562 mask |= SDVO_OUTPUT_LVDS1;
2563 fallthrough;
2564 case SDVO_OUTPUT_LVDS0:
2565 mask |= SDVO_OUTPUT_LVDS0;
2566 fallthrough;
2567 case SDVO_OUTPUT_TMDS1:
2568 mask |= SDVO_OUTPUT_TMDS1;
2569 fallthrough;
2570 case SDVO_OUTPUT_TMDS0:
2571 mask |= SDVO_OUTPUT_TMDS0;
2572 fallthrough;
2573 case SDVO_OUTPUT_RGB1:
2574 mask |= SDVO_OUTPUT_RGB1;
2575 fallthrough;
2576 case SDVO_OUTPUT_RGB0:
2577 mask |= SDVO_OUTPUT_RGB0;
2578 break;
2579 }
2580
2581 /* Count bits to find what number we are in the priority list. */
2582 mask &= sdvo->caps.output_flags;
2583 num_bits = hweight16(mask);
2584 /* If more than 3 outputs, default to DDC bus 3 for now. */
2585 if (num_bits > 3)
2586 num_bits = 3;
2587
2588 /* Corresponds to SDVO_CONTROL_BUS_DDCx */
2589 return num_bits;
2590 }
2591
2592 /*
2593 * Choose the appropriate DDC bus for control bus switch command for this
2594 * SDVO output based on the controlled output.
2595 *
2596 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
2597 * outputs, then LVDS outputs.
2598 */
2599 static struct intel_sdvo_ddc *
2600 intel_sdvo_select_ddc_bus(struct intel_sdvo *sdvo,
2601 struct intel_sdvo_connector *connector)
2602 {
2603 struct drm_i915_private *dev_priv = to_i915(sdvo->base.base.dev);
2604 const struct sdvo_device_mapping *mapping;
2605 int ddc_bus;
2606
2607 if (sdvo->base.port == PORT_B)
2608 mapping = &dev_priv->display.vbt.sdvo_mappings[0];
2609 else
2610 mapping = &dev_priv->display.vbt.sdvo_mappings[1];
2611
2612 if (mapping->initialized)
2613 ddc_bus = (mapping->ddc_pin & 0xf0) >> 4;
2614 else
2615 ddc_bus = intel_sdvo_guess_ddc_bus(sdvo, connector);
2616
2617 if (ddc_bus < 1 || ddc_bus > 3)
2618 return NULL;
2619
2620 return &sdvo->ddc[ddc_bus - 1];
2621 }
2622
2623 static void
2624 intel_sdvo_select_i2c_bus(struct intel_sdvo *sdvo)
2625 {
2626 struct drm_i915_private *dev_priv = to_i915(sdvo->base.base.dev);
2627 const struct sdvo_device_mapping *mapping;
2628 u8 pin;
2629
2630 if (sdvo->base.port == PORT_B)
2631 mapping = &dev_priv->display.vbt.sdvo_mappings[0];
2632 else
2633 mapping = &dev_priv->display.vbt.sdvo_mappings[1];
2634
2635 if (mapping->initialized &&
2636 intel_gmbus_is_valid_pin(dev_priv, mapping->i2c_pin))
2637 pin = mapping->i2c_pin;
2638 else
2639 pin = GMBUS_PIN_DPB;
2640
2641 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] I2C pin %d, slave addr 0x%x\n",
2642 sdvo->base.base.base.id, sdvo->base.base.name,
2643 pin, sdvo->slave_addr);
2644
2645 sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin);
2646
2647 /*
2648 * With gmbus we should be able to drive sdvo i2c at 2MHz, but somehow
2649 * our code totally fails once we start using gmbus. Hence fall back to
2650 * bit banging for now.
2651 */
2652 intel_gmbus_force_bit(sdvo->i2c, true);
2653 }
2654
2655 /* undo any changes intel_sdvo_select_i2c_bus() did to sdvo->i2c */
2656 static void
2657 intel_sdvo_unselect_i2c_bus(struct intel_sdvo *sdvo)
2658 {
2659 intel_gmbus_force_bit(sdvo->i2c, false);
2660 }
2661
2662 static bool
2663 intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo)
2664 {
2665 return intel_sdvo_check_supp_encode(intel_sdvo);
2666 }
2667
2668 static u8
2669 intel_sdvo_get_slave_addr(struct intel_sdvo *sdvo)
2670 {
2671 struct drm_i915_private *dev_priv = to_i915(sdvo->base.base.dev);
2672 const struct sdvo_device_mapping *my_mapping, *other_mapping;
2673
2674 if (sdvo->base.port == PORT_B) {
2675 my_mapping = &dev_priv->display.vbt.sdvo_mappings[0];
2676 other_mapping = &dev_priv->display.vbt.sdvo_mappings[1];
2677 } else {
2678 my_mapping = &dev_priv->display.vbt.sdvo_mappings[1];
2679 other_mapping = &dev_priv->display.vbt.sdvo_mappings[0];
2680 }
2681
2682 /* If the BIOS described our SDVO device, take advantage of it. */
2683 if (my_mapping->slave_addr)
2684 return my_mapping->slave_addr;
2685
2686 /*
2687 * If the BIOS only described a different SDVO device, use the
2688 * address that it isn't using.
2689 */
2690 if (other_mapping->slave_addr) {
2691 if (other_mapping->slave_addr == 0x70)
2692 return 0x72;
2693 else
2694 return 0x70;
2695 }
2696
2697 /*
2698 * No SDVO device info is found for another DVO port,
2699 * so use mapping assumption we had before BIOS parsing.
2700 */
2701 if (sdvo->base.port == PORT_B)
2702 return 0x70;
2703 else
2704 return 0x72;
2705 }
2706
2707 static int
2708 intel_sdvo_init_ddc_proxy(struct intel_sdvo_ddc *ddc,
2709 struct intel_sdvo *sdvo, int bit);
2710
2711 static int
2712 intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
2713 struct intel_sdvo *encoder)
2714 {
2715 struct drm_i915_private *i915 = to_i915(encoder->base.base.dev);
2716 struct intel_sdvo_ddc *ddc = NULL;
2717 int ret;
2718
2719 if (HAS_DDC(connector))
2720 ddc = intel_sdvo_select_ddc_bus(encoder, connector);
2721
2722 ret = drm_connector_init_with_ddc(encoder->base.base.dev,
2723 &connector->base.base,
2724 &intel_sdvo_connector_funcs,
2725 connector->base.base.connector_type,
2726 ddc ? &ddc->ddc : NULL);
2727 if (ret < 0)
2728 return ret;
2729
2730 drm_connector_helper_add(&connector->base.base,
2731 &intel_sdvo_connector_helper_funcs);
2732
2733 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
2734 connector->base.base.interlace_allowed = true;
2735 connector->base.get_hw_state = intel_sdvo_connector_get_hw_state;
2736
2737 intel_connector_attach_encoder(&connector->base, &encoder->base);
2738
2739 if (ddc)
2740 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] using %s\n",
2741 connector->base.base.base.id, connector->base.base.name,
2742 ddc->ddc.name);
2743
2744 return 0;
2745 }
2746
2747 static void
2748 intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo,
2749 struct intel_sdvo_connector *connector)
2750 {
2751 intel_attach_force_audio_property(&connector->base.base);
2752 if (intel_sdvo->colorimetry_cap & SDVO_COLORIMETRY_RGB220)
2753 intel_attach_broadcast_rgb_property(&connector->base.base);
2754 intel_attach_aspect_ratio_property(&connector->base.base);
2755 }
2756
2757 static struct intel_sdvo_connector *intel_sdvo_connector_alloc(void)
2758 {
2759 struct intel_sdvo_connector *sdvo_connector;
2760 struct intel_sdvo_connector_state *conn_state;
2761
2762 sdvo_connector = kzalloc(sizeof(*sdvo_connector), GFP_KERNEL);
2763 if (!sdvo_connector)
2764 return NULL;
2765
2766 conn_state = kzalloc(sizeof(*conn_state), GFP_KERNEL);
2767 if (!conn_state) {
2768 kfree(sdvo_connector);
2769 return NULL;
2770 }
2771
2772 __drm_atomic_helper_connector_reset(&sdvo_connector->base.base,
2773 &conn_state->base.base);
2774
2775 intel_panel_init_alloc(&sdvo_connector->base);
2776
2777 return sdvo_connector;
2778 }
2779
2780 static bool
2781 intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, u16 type)
2782 {
2783 struct drm_encoder *encoder = &intel_sdvo->base.base;
2784 struct drm_connector *connector;
2785 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
2786 struct intel_connector *intel_connector;
2787 struct intel_sdvo_connector *intel_sdvo_connector;
2788
2789 DRM_DEBUG_KMS("initialising DVI type 0x%x\n", type);
2790
2791 intel_sdvo_connector = intel_sdvo_connector_alloc();
2792 if (!intel_sdvo_connector)
2793 return false;
2794
2795 intel_sdvo_connector->output_flag = type;
2796
2797 intel_connector = &intel_sdvo_connector->base;
2798 connector = &intel_connector->base;
2799 if (intel_sdvo_get_hotplug_support(intel_sdvo) &
2800 intel_sdvo_connector->output_flag) {
2801 intel_sdvo->hotplug_active |= intel_sdvo_connector->output_flag;
2802 /*
2803 * Some SDVO devices have one-shot hotplug interrupts.
2804 * Ensure that they get re-enabled when an interrupt happens.
2805 */
2806 intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
2807 intel_encoder->hotplug = intel_sdvo_hotplug;
2808 intel_sdvo_enable_hotplug(intel_encoder);
2809 } else {
2810 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
2811 }
2812 intel_connector->base.polled = intel_connector->polled;
2813 encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
2814 connector->connector_type = DRM_MODE_CONNECTOR_DVID;
2815
2816 if (intel_sdvo_is_hdmi_connector(intel_sdvo)) {
2817 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
2818 intel_sdvo_connector->is_hdmi = true;
2819 }
2820
2821 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2822 kfree(intel_sdvo_connector);
2823 return false;
2824 }
2825
2826 if (intel_sdvo_connector->is_hdmi)
2827 intel_sdvo_add_hdmi_properties(intel_sdvo, intel_sdvo_connector);
2828
2829 return true;
2830 }
2831
2832 static bool
2833 intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, u16 type)
2834 {
2835 struct drm_encoder *encoder = &intel_sdvo->base.base;
2836 struct drm_connector *connector;
2837 struct intel_connector *intel_connector;
2838 struct intel_sdvo_connector *intel_sdvo_connector;
2839
2840 DRM_DEBUG_KMS("initialising TV type 0x%x\n", type);
2841
2842 intel_sdvo_connector = intel_sdvo_connector_alloc();
2843 if (!intel_sdvo_connector)
2844 return false;
2845
2846 intel_connector = &intel_sdvo_connector->base;
2847 connector = &intel_connector->base;
2848 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2849 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
2850
2851 intel_sdvo_connector->output_flag = type;
2852
2853 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2854 kfree(intel_sdvo_connector);
2855 return false;
2856 }
2857
2858 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
2859 goto err;
2860
2861 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
2862 goto err;
2863
2864 return true;
2865
2866 err:
2867 intel_connector_destroy(connector);
2868 return false;
2869 }
2870
2871 static bool
2872 intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, u16 type)
2873 {
2874 struct drm_encoder *encoder = &intel_sdvo->base.base;
2875 struct drm_connector *connector;
2876 struct intel_connector *intel_connector;
2877 struct intel_sdvo_connector *intel_sdvo_connector;
2878
2879 DRM_DEBUG_KMS("initialising analog type 0x%x\n", type);
2880
2881 intel_sdvo_connector = intel_sdvo_connector_alloc();
2882 if (!intel_sdvo_connector)
2883 return false;
2884
2885 intel_connector = &intel_sdvo_connector->base;
2886 connector = &intel_connector->base;
2887 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
2888 intel_connector->base.polled = intel_connector->polled;
2889 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2890 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2891
2892 intel_sdvo_connector->output_flag = type;
2893
2894 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2895 kfree(intel_sdvo_connector);
2896 return false;
2897 }
2898
2899 return true;
2900 }
2901
2902 static bool
2903 intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, u16 type)
2904 {
2905 struct drm_encoder *encoder = &intel_sdvo->base.base;
2906 struct drm_i915_private *i915 = to_i915(encoder->dev);
2907 struct drm_connector *connector;
2908 struct intel_connector *intel_connector;
2909 struct intel_sdvo_connector *intel_sdvo_connector;
2910
2911 DRM_DEBUG_KMS("initialising LVDS type 0x%x\n", type);
2912
2913 intel_sdvo_connector = intel_sdvo_connector_alloc();
2914 if (!intel_sdvo_connector)
2915 return false;
2916
2917 intel_connector = &intel_sdvo_connector->base;
2918 connector = &intel_connector->base;
2919 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2920 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2921
2922 intel_sdvo_connector->output_flag = type;
2923
2924 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2925 kfree(intel_sdvo_connector);
2926 return false;
2927 }
2928
2929 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
2930 goto err;
2931
2932 intel_bios_init_panel_late(i915, &intel_connector->panel, NULL, NULL);
2933
2934 /*
2935 * Fetch modes from VBT. For SDVO prefer the VBT mode since some
2936 * SDVO->LVDS transcoders can't cope with the EDID mode.
2937 */
2938 intel_panel_add_vbt_sdvo_fixed_mode(intel_connector);
2939
2940 if (!intel_panel_preferred_fixed_mode(intel_connector)) {
2941 mutex_lock(&i915->drm.mode_config.mutex);
2942
2943 intel_ddc_get_modes(connector, connector->ddc);
2944 intel_panel_add_edid_fixed_modes(intel_connector, false);
2945
2946 mutex_unlock(&i915->drm.mode_config.mutex);
2947 }
2948
2949 intel_panel_init(intel_connector, NULL);
2950
2951 if (!intel_panel_preferred_fixed_mode(intel_connector))
2952 goto err;
2953
2954 return true;
2955
2956 err:
2957 intel_connector_destroy(connector);
2958 return false;
2959 }
2960
2961 static u16 intel_sdvo_filter_output_flags(u16 flags)
2962 {
2963 flags &= SDVO_OUTPUT_MASK;
2964
2965 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
2966 if (!(flags & SDVO_OUTPUT_TMDS0))
2967 flags &= ~SDVO_OUTPUT_TMDS1;
2968
2969 if (!(flags & SDVO_OUTPUT_RGB0))
2970 flags &= ~SDVO_OUTPUT_RGB1;
2971
2972 if (!(flags & SDVO_OUTPUT_LVDS0))
2973 flags &= ~SDVO_OUTPUT_LVDS1;
2974
2975 return flags;
2976 }
2977
2978 static bool intel_sdvo_output_init(struct intel_sdvo *sdvo, u16 type)
2979 {
2980 if (type & SDVO_TMDS_MASK)
2981 return intel_sdvo_dvi_init(sdvo, type);
2982 else if (type & SDVO_TV_MASK)
2983 return intel_sdvo_tv_init(sdvo, type);
2984 else if (type & SDVO_RGB_MASK)
2985 return intel_sdvo_analog_init(sdvo, type);
2986 else if (type & SDVO_LVDS_MASK)
2987 return intel_sdvo_lvds_init(sdvo, type);
2988 else
2989 return false;
2990 }
2991
2992 static bool
2993 intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo)
2994 {
2995 static const u16 probe_order[] = {
2996 SDVO_OUTPUT_TMDS0,
2997 SDVO_OUTPUT_TMDS1,
2998 /* TV has no XXX1 function block */
2999 SDVO_OUTPUT_SVID0,
3000 SDVO_OUTPUT_CVBS0,
3001 SDVO_OUTPUT_YPRPB0,
3002 SDVO_OUTPUT_RGB0,
3003 SDVO_OUTPUT_RGB1,
3004 SDVO_OUTPUT_LVDS0,
3005 SDVO_OUTPUT_LVDS1,
3006 };
3007 u16 flags;
3008 int i;
3009
3010 flags = intel_sdvo_filter_output_flags(intel_sdvo->caps.output_flags);
3011
3012 if (flags == 0) {
3013 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%04x)\n",
3014 SDVO_NAME(intel_sdvo), intel_sdvo->caps.output_flags);
3015 return false;
3016 }
3017
3018 for (i = 0; i < ARRAY_SIZE(probe_order); i++) {
3019 u16 type = flags & probe_order[i];
3020
3021 if (!type)
3022 continue;
3023
3024 if (!intel_sdvo_output_init(intel_sdvo, type))
3025 return false;
3026 }
3027
3028 intel_sdvo->base.pipe_mask = ~0;
3029
3030 return true;
3031 }
3032
3033 static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo)
3034 {
3035 struct drm_device *dev = intel_sdvo->base.base.dev;
3036 struct drm_connector *connector, *tmp;
3037
3038 list_for_each_entry_safe(connector, tmp,
3039 &dev->mode_config.connector_list, head) {
3040 if (intel_attached_encoder(to_intel_connector(connector)) == &intel_sdvo->base) {
3041 drm_connector_unregister(connector);
3042 intel_connector_destroy(connector);
3043 }
3044 }
3045 }
3046
3047 static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
3048 struct intel_sdvo_connector *intel_sdvo_connector,
3049 int type)
3050 {
3051 struct drm_device *dev = intel_sdvo->base.base.dev;
3052 struct intel_sdvo_tv_format format;
3053 u32 format_map, i;
3054
3055 if (!intel_sdvo_set_target_output(intel_sdvo, type))
3056 return false;
3057
3058 BUILD_BUG_ON(sizeof(format) != 6);
3059 if (!intel_sdvo_get_value(intel_sdvo,
3060 SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
3061 &format, sizeof(format)))
3062 return false;
3063
3064 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
3065
3066 if (format_map == 0)
3067 return false;
3068
3069 intel_sdvo_connector->format_supported_num = 0;
3070 for (i = 0 ; i < TV_FORMAT_NUM; i++)
3071 if (format_map & (1 << i))
3072 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
3073
3074
3075 intel_sdvo_connector->tv_format =
3076 drm_property_create(dev, DRM_MODE_PROP_ENUM,
3077 "mode", intel_sdvo_connector->format_supported_num);
3078 if (!intel_sdvo_connector->tv_format)
3079 return false;
3080
3081 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
3082 drm_property_add_enum(intel_sdvo_connector->tv_format, i,
3083 tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
3084
3085 intel_sdvo_connector->base.base.state->tv.legacy_mode = intel_sdvo_connector->tv_format_supported[0];
3086 drm_object_attach_property(&intel_sdvo_connector->base.base.base,
3087 intel_sdvo_connector->tv_format, 0);
3088 return true;
3089
3090 }
3091
3092 #define _ENHANCEMENT(state_assignment, name, NAME) do { \
3093 if (enhancements.name) { \
3094 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
3095 !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
3096 return false; \
3097 intel_sdvo_connector->name = \
3098 drm_property_create_range(dev, 0, #name, 0, data_value[0]); \
3099 if (!intel_sdvo_connector->name) return false; \
3100 state_assignment = response; \
3101 drm_object_attach_property(&connector->base, \
3102 intel_sdvo_connector->name, 0); \
3103 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
3104 data_value[0], data_value[1], response); \
3105 } \
3106 } while (0)
3107
3108 #define ENHANCEMENT(state, name, NAME) _ENHANCEMENT((state)->name, name, NAME)
3109
3110 static bool
3111 intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
3112 struct intel_sdvo_connector *intel_sdvo_connector,
3113 struct intel_sdvo_enhancements_reply enhancements)
3114 {
3115 struct drm_device *dev = intel_sdvo->base.base.dev;
3116 struct drm_connector *connector = &intel_sdvo_connector->base.base;
3117 struct drm_connector_state *conn_state = connector->state;
3118 struct intel_sdvo_connector_state *sdvo_state =
3119 to_intel_sdvo_connector_state(conn_state);
3120 u16 response, data_value[2];
3121
3122 /* when horizontal overscan is supported, Add the left/right property */
3123 if (enhancements.overscan_h) {
3124 if (!intel_sdvo_get_value(intel_sdvo,
3125 SDVO_CMD_GET_MAX_OVERSCAN_H,
3126 &data_value, 4))
3127 return false;
3128
3129 if (!intel_sdvo_get_value(intel_sdvo,
3130 SDVO_CMD_GET_OVERSCAN_H,
3131 &response, 2))
3132 return false;
3133
3134 sdvo_state->tv.overscan_h = response;
3135
3136 intel_sdvo_connector->max_hscan = data_value[0];
3137 intel_sdvo_connector->left =
3138 drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]);
3139 if (!intel_sdvo_connector->left)
3140 return false;
3141
3142 drm_object_attach_property(&connector->base,
3143 intel_sdvo_connector->left, 0);
3144
3145 intel_sdvo_connector->right =
3146 drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]);
3147 if (!intel_sdvo_connector->right)
3148 return false;
3149
3150 drm_object_attach_property(&connector->base,
3151 intel_sdvo_connector->right, 0);
3152 DRM_DEBUG_KMS("h_overscan: max %d, "
3153 "default %d, current %d\n",
3154 data_value[0], data_value[1], response);
3155 }
3156
3157 if (enhancements.overscan_v) {
3158 if (!intel_sdvo_get_value(intel_sdvo,
3159 SDVO_CMD_GET_MAX_OVERSCAN_V,
3160 &data_value, 4))
3161 return false;
3162
3163 if (!intel_sdvo_get_value(intel_sdvo,
3164 SDVO_CMD_GET_OVERSCAN_V,
3165 &response, 2))
3166 return false;
3167
3168 sdvo_state->tv.overscan_v = response;
3169
3170 intel_sdvo_connector->max_vscan = data_value[0];
3171 intel_sdvo_connector->top =
3172 drm_property_create_range(dev, 0,
3173 "top_margin", 0, data_value[0]);
3174 if (!intel_sdvo_connector->top)
3175 return false;
3176
3177 drm_object_attach_property(&connector->base,
3178 intel_sdvo_connector->top, 0);
3179
3180 intel_sdvo_connector->bottom =
3181 drm_property_create_range(dev, 0,
3182 "bottom_margin", 0, data_value[0]);
3183 if (!intel_sdvo_connector->bottom)
3184 return false;
3185
3186 drm_object_attach_property(&connector->base,
3187 intel_sdvo_connector->bottom, 0);
3188 DRM_DEBUG_KMS("v_overscan: max %d, "
3189 "default %d, current %d\n",
3190 data_value[0], data_value[1], response);
3191 }
3192
3193 ENHANCEMENT(&sdvo_state->tv, hpos, HPOS);
3194 ENHANCEMENT(&sdvo_state->tv, vpos, VPOS);
3195 ENHANCEMENT(&conn_state->tv, saturation, SATURATION);
3196 ENHANCEMENT(&conn_state->tv, contrast, CONTRAST);
3197 ENHANCEMENT(&conn_state->tv, hue, HUE);
3198 ENHANCEMENT(&conn_state->tv, brightness, BRIGHTNESS);
3199 ENHANCEMENT(&sdvo_state->tv, sharpness, SHARPNESS);
3200 ENHANCEMENT(&sdvo_state->tv, flicker_filter, FLICKER_FILTER);
3201 ENHANCEMENT(&sdvo_state->tv, flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
3202 ENHANCEMENT(&sdvo_state->tv, flicker_filter_2d, FLICKER_FILTER_2D);
3203 _ENHANCEMENT(sdvo_state->tv.chroma_filter, tv_chroma_filter, TV_CHROMA_FILTER);
3204 _ENHANCEMENT(sdvo_state->tv.luma_filter, tv_luma_filter, TV_LUMA_FILTER);
3205
3206 if (enhancements.dot_crawl) {
3207 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
3208 return false;
3209
3210 sdvo_state->tv.dot_crawl = response & 0x1;
3211 intel_sdvo_connector->dot_crawl =
3212 drm_property_create_range(dev, 0, "dot_crawl", 0, 1);
3213 if (!intel_sdvo_connector->dot_crawl)
3214 return false;
3215
3216 drm_object_attach_property(&connector->base,
3217 intel_sdvo_connector->dot_crawl, 0);
3218 DRM_DEBUG_KMS("dot crawl: current %d\n", response);
3219 }
3220
3221 return true;
3222 }
3223
3224 static bool
3225 intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
3226 struct intel_sdvo_connector *intel_sdvo_connector,
3227 struct intel_sdvo_enhancements_reply enhancements)
3228 {
3229 struct drm_device *dev = intel_sdvo->base.base.dev;
3230 struct drm_connector *connector = &intel_sdvo_connector->base.base;
3231 u16 response, data_value[2];
3232
3233 ENHANCEMENT(&connector->state->tv, brightness, BRIGHTNESS);
3234
3235 return true;
3236 }
3237 #undef ENHANCEMENT
3238 #undef _ENHANCEMENT
3239
3240 static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
3241 struct intel_sdvo_connector *intel_sdvo_connector)
3242 {
3243 union {
3244 struct intel_sdvo_enhancements_reply reply;
3245 u16 response;
3246 } enhancements;
3247
3248 BUILD_BUG_ON(sizeof(enhancements) != 2);
3249
3250 if (!intel_sdvo_get_value(intel_sdvo,
3251 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
3252 &enhancements, sizeof(enhancements)) ||
3253 enhancements.response == 0) {
3254 DRM_DEBUG_KMS("No enhancement is supported\n");
3255 return true;
3256 }
3257
3258 if (IS_TV(intel_sdvo_connector))
3259 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
3260 else if (IS_LVDS(intel_sdvo_connector))
3261 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
3262 else
3263 return true;
3264 }
3265
3266 static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter,
3267 struct i2c_msg *msgs,
3268 int num)
3269 {
3270 struct intel_sdvo_ddc *ddc = adapter->algo_data;
3271 struct intel_sdvo *sdvo = ddc->sdvo;
3272
3273 if (!__intel_sdvo_set_control_bus_switch(sdvo, 1 << ddc->ddc_bus))
3274 return -EIO;
3275
3276 return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num);
3277 }
3278
3279 static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter)
3280 {
3281 struct intel_sdvo_ddc *ddc = adapter->algo_data;
3282 struct intel_sdvo *sdvo = ddc->sdvo;
3283
3284 return sdvo->i2c->algo->functionality(sdvo->i2c);
3285 }
3286
3287 static const struct i2c_algorithm intel_sdvo_ddc_proxy = {
3288 .master_xfer = intel_sdvo_ddc_proxy_xfer,
3289 .functionality = intel_sdvo_ddc_proxy_func
3290 };
3291
3292 static void proxy_lock_bus(struct i2c_adapter *adapter,
3293 unsigned int flags)
3294 {
3295 struct intel_sdvo_ddc *ddc = adapter->algo_data;
3296 struct intel_sdvo *sdvo = ddc->sdvo;
3297
3298 sdvo->i2c->lock_ops->lock_bus(sdvo->i2c, flags);
3299 }
3300
3301 static int proxy_trylock_bus(struct i2c_adapter *adapter,
3302 unsigned int flags)
3303 {
3304 struct intel_sdvo_ddc *ddc = adapter->algo_data;
3305 struct intel_sdvo *sdvo = ddc->sdvo;
3306
3307 return sdvo->i2c->lock_ops->trylock_bus(sdvo->i2c, flags);
3308 }
3309
3310 static void proxy_unlock_bus(struct i2c_adapter *adapter,
3311 unsigned int flags)
3312 {
3313 struct intel_sdvo_ddc *ddc = adapter->algo_data;
3314 struct intel_sdvo *sdvo = ddc->sdvo;
3315
3316 sdvo->i2c->lock_ops->unlock_bus(sdvo->i2c, flags);
3317 }
3318
3319 static const struct i2c_lock_operations proxy_lock_ops = {
3320 .lock_bus = proxy_lock_bus,
3321 .trylock_bus = proxy_trylock_bus,
3322 .unlock_bus = proxy_unlock_bus,
3323 };
3324
3325 static int
3326 intel_sdvo_init_ddc_proxy(struct intel_sdvo_ddc *ddc,
3327 struct intel_sdvo *sdvo, int ddc_bus)
3328 {
3329 struct drm_i915_private *dev_priv = to_i915(sdvo->base.base.dev);
3330 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
3331
3332 ddc->sdvo = sdvo;
3333 ddc->ddc_bus = ddc_bus;
3334
3335 ddc->ddc.owner = THIS_MODULE;
3336 snprintf(ddc->ddc.name, I2C_NAME_SIZE, "SDVO %c DDC%d",
3337 port_name(sdvo->base.port), ddc_bus);
3338 ddc->ddc.dev.parent = &pdev->dev;
3339 ddc->ddc.algo_data = ddc;
3340 ddc->ddc.algo = &intel_sdvo_ddc_proxy;
3341 ddc->ddc.lock_ops = &proxy_lock_ops;
3342
3343 return i2c_add_adapter(&ddc->ddc);
3344 }
3345
3346 static bool is_sdvo_port_valid(struct drm_i915_private *dev_priv, enum port port)
3347 {
3348 if (HAS_PCH_SPLIT(dev_priv))
3349 return port == PORT_B;
3350 else
3351 return port == PORT_B || port == PORT_C;
3352 }
3353
3354 static bool assert_sdvo_port_valid(struct drm_i915_private *dev_priv,
3355 enum port port)
3356 {
3357 return !drm_WARN(&dev_priv->drm, !is_sdvo_port_valid(dev_priv, port),
3358 "Platform does not support SDVO %c\n", port_name(port));
3359 }
3360
3361 bool intel_sdvo_init(struct drm_i915_private *dev_priv,
3362 i915_reg_t sdvo_reg, enum port port)
3363 {
3364 struct intel_encoder *intel_encoder;
3365 struct intel_sdvo *intel_sdvo;
3366 int i;
3367
3368 if (!assert_port_valid(dev_priv, port))
3369 return false;
3370
3371 if (!assert_sdvo_port_valid(dev_priv, port))
3372 return false;
3373
3374 intel_sdvo = kzalloc(sizeof(*intel_sdvo), GFP_KERNEL);
3375 if (!intel_sdvo)
3376 return false;
3377
3378 /* encoder type will be decided later */
3379 intel_encoder = &intel_sdvo->base;
3380 intel_encoder->type = INTEL_OUTPUT_SDVO;
3381 intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER;
3382 intel_encoder->port = port;
3383
3384 drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
3385 &intel_sdvo_enc_funcs, 0,
3386 "SDVO %c", port_name(port));
3387
3388 intel_sdvo->sdvo_reg = sdvo_reg;
3389 intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(intel_sdvo) >> 1;
3390
3391 intel_sdvo_select_i2c_bus(intel_sdvo);
3392
3393 /* Read the regs to test if we can talk to the device */
3394 for (i = 0; i < 0x40; i++) {
3395 u8 byte;
3396
3397 if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) {
3398 drm_dbg_kms(&dev_priv->drm,
3399 "No SDVO device found on %s\n",
3400 SDVO_NAME(intel_sdvo));
3401 goto err;
3402 }
3403 }
3404
3405 intel_encoder->compute_config = intel_sdvo_compute_config;
3406 if (HAS_PCH_SPLIT(dev_priv)) {
3407 intel_encoder->disable = pch_disable_sdvo;
3408 intel_encoder->post_disable = pch_post_disable_sdvo;
3409 } else {
3410 intel_encoder->disable = intel_disable_sdvo;
3411 }
3412 intel_encoder->pre_enable = intel_sdvo_pre_enable;
3413 intel_encoder->enable = intel_enable_sdvo;
3414 intel_encoder->audio_enable = intel_sdvo_enable_audio;
3415 intel_encoder->audio_disable = intel_sdvo_disable_audio;
3416 intel_encoder->get_hw_state = intel_sdvo_get_hw_state;
3417 intel_encoder->get_config = intel_sdvo_get_config;
3418
3419 /* In default case sdvo lvds is false */
3420 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
3421 goto err;
3422
3423 intel_sdvo->colorimetry_cap =
3424 intel_sdvo_get_colorimetry_cap(intel_sdvo);
3425
3426 for (i = 0; i < ARRAY_SIZE(intel_sdvo->ddc); i++) {
3427 int ret;
3428
3429 ret = intel_sdvo_init_ddc_proxy(&intel_sdvo->ddc[i],
3430 intel_sdvo, i + 1);
3431 if (ret)
3432 goto err;
3433 }
3434
3435 if (!intel_sdvo_output_setup(intel_sdvo)) {
3436 drm_dbg_kms(&dev_priv->drm,
3437 "SDVO output failed to setup on %s\n",
3438 SDVO_NAME(intel_sdvo));
3439 /* Output_setup can leave behind connectors! */
3440 goto err_output;
3441 }
3442
3443 /*
3444 * Only enable the hotplug irq if we need it, to work around noisy
3445 * hotplug lines.
3446 */
3447 if (intel_sdvo->hotplug_active) {
3448 if (intel_sdvo->base.port == PORT_B)
3449 intel_encoder->hpd_pin = HPD_SDVO_B;
3450 else
3451 intel_encoder->hpd_pin = HPD_SDVO_C;
3452 }
3453
3454 /*
3455 * Cloning SDVO with anything is often impossible, since the SDVO
3456 * encoder can request a special input timing mode. And even if that's
3457 * not the case we have evidence that cloning a plain unscaled mode with
3458 * VGA doesn't really work. Furthermore the cloning flags are way too
3459 * simplistic anyway to express such constraints, so just give up on
3460 * cloning for SDVO encoders.
3461 */
3462 intel_sdvo->base.cloneable = 0;
3463
3464 /* Set the input timing to the screen. Assume always input 0. */
3465 if (!intel_sdvo_set_target_input(intel_sdvo))
3466 goto err_output;
3467
3468 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
3469 &intel_sdvo->pixel_clock_min,
3470 &intel_sdvo->pixel_clock_max))
3471 goto err_output;
3472
3473 drm_dbg_kms(&dev_priv->drm, "%s device VID/DID: %02X:%02X.%02X, "
3474 "clock range %dMHz - %dMHz, "
3475 "num inputs: %d, "
3476 "output 1: %c, output 2: %c\n",
3477 SDVO_NAME(intel_sdvo),
3478 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
3479 intel_sdvo->caps.device_rev_id,
3480 intel_sdvo->pixel_clock_min / 1000,
3481 intel_sdvo->pixel_clock_max / 1000,
3482 intel_sdvo->caps.sdvo_num_inputs,
3483 /* check currently supported outputs */
3484 intel_sdvo->caps.output_flags &
3485 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0 |
3486 SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_SVID0 |
3487 SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_YPRPB0) ? 'Y' : 'N',
3488 intel_sdvo->caps.output_flags &
3489 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1 |
3490 SDVO_OUTPUT_LVDS1) ? 'Y' : 'N');
3491 return true;
3492
3493 err_output:
3494 intel_sdvo_output_cleanup(intel_sdvo);
3495 err:
3496 intel_sdvo_unselect_i2c_bus(intel_sdvo);
3497 intel_sdvo_encoder_destroy(&intel_encoder->base);
3498
3499 return false;
3500 }
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