1 // SPDX-License-Identifier: MIT
3 * Copyright © 2022 Intel Corporation
6 #include <drm/drm_blend.h>
9 #include "i915_fixed.h"
12 #include "intel_atomic.h"
13 #include "intel_atomic_plane.h"
15 #include "intel_crtc.h"
17 #include "intel_display.h"
18 #include "intel_display_power.h"
19 #include "intel_display_types.h"
21 #include "intel_pcode.h"
23 #include "skl_watermark.h"
24 #include "skl_watermark_regs.h"
26 /*It is expected that DSB can do posted writes to every register in
27 * the pipe and planes within 100us. For flip queue use case, the
28 * recommended DSB execution time is 100us + one SAGV block time.
30 #define DSB_EXE_TIME 100
32 static void skl_sagv_disable(struct drm_i915_private
*i915
);
34 /* Stores plane specific WM parameters */
35 struct skl_wm_params
{
36 bool x_tiled
, y_tiled
;
43 u32 plane_bytes_per_line
;
44 uint_fixed_16_16_t plane_blocks_per_line
;
45 uint_fixed_16_16_t y_tile_minimum
;
50 u8
intel_enabled_dbuf_slices_mask(struct drm_i915_private
*i915
)
52 u8 enabled_slices
= 0;
53 enum dbuf_slice slice
;
55 for_each_dbuf_slice(i915
, slice
) {
56 if (intel_de_read(i915
, DBUF_CTL_S(slice
)) & DBUF_POWER_STATE
)
57 enabled_slices
|= BIT(slice
);
60 return enabled_slices
;
64 * FIXME: We still don't have the proper code detect if we need to apply the WA,
65 * so assume we'll always need it in order to avoid underruns.
67 static bool skl_needs_memory_bw_wa(struct drm_i915_private
*i915
)
69 return DISPLAY_VER(i915
) == 9;
73 intel_has_sagv(struct drm_i915_private
*i915
)
75 return HAS_SAGV(i915
) &&
76 i915
->display
.sagv
.status
!= I915_SAGV_NOT_CONTROLLED
;
80 intel_sagv_block_time(struct drm_i915_private
*i915
)
82 if (DISPLAY_VER(i915
) >= 14) {
85 val
= intel_de_read(i915
, MTL_LATENCY_SAGV
);
87 return REG_FIELD_GET(MTL_LATENCY_QCLK_SAGV
, val
);
88 } else if (DISPLAY_VER(i915
) >= 12) {
92 ret
= snb_pcode_read(&i915
->uncore
,
93 GEN12_PCODE_READ_SAGV_BLOCK_TIME_US
,
96 drm_dbg_kms(&i915
->drm
, "Couldn't read SAGV block time!\n");
101 } else if (DISPLAY_VER(i915
) == 11) {
103 } else if (HAS_SAGV(i915
)) {
110 static void intel_sagv_init(struct drm_i915_private
*i915
)
113 i915
->display
.sagv
.status
= I915_SAGV_NOT_CONTROLLED
;
116 * Probe to see if we have working SAGV control.
117 * For icl+ this was already determined by intel_bw_init_hw().
119 if (DISPLAY_VER(i915
) < 11)
120 skl_sagv_disable(i915
);
122 drm_WARN_ON(&i915
->drm
, i915
->display
.sagv
.status
== I915_SAGV_UNKNOWN
);
124 i915
->display
.sagv
.block_time_us
= intel_sagv_block_time(i915
);
126 drm_dbg_kms(&i915
->drm
, "SAGV supported: %s, original SAGV block time: %u us\n",
127 str_yes_no(intel_has_sagv(i915
)), i915
->display
.sagv
.block_time_us
);
129 /* avoid overflow when adding with wm0 latency/etc. */
130 if (drm_WARN(&i915
->drm
, i915
->display
.sagv
.block_time_us
> U16_MAX
,
131 "Excessive SAGV block time %u, ignoring\n",
132 i915
->display
.sagv
.block_time_us
))
133 i915
->display
.sagv
.block_time_us
= 0;
135 if (!intel_has_sagv(i915
))
136 i915
->display
.sagv
.block_time_us
= 0;
140 * SAGV dynamically adjusts the system agent voltage and clock frequencies
141 * depending on power and performance requirements. The display engine access
142 * to system memory is blocked during the adjustment time. Because of the
143 * blocking time, having this enabled can cause full system hangs and/or pipe
144 * underruns if we don't meet all of the following requirements:
146 * - <= 1 pipe enabled
147 * - All planes can enable watermarks for latencies >= SAGV engine block time
148 * - We're not using an interlaced display configuration
150 static void skl_sagv_enable(struct drm_i915_private
*i915
)
154 if (!intel_has_sagv(i915
))
157 if (i915
->display
.sagv
.status
== I915_SAGV_ENABLED
)
160 drm_dbg_kms(&i915
->drm
, "Enabling SAGV\n");
161 ret
= snb_pcode_write(&i915
->uncore
, GEN9_PCODE_SAGV_CONTROL
,
164 /* We don't need to wait for SAGV when enabling */
167 * Some skl systems, pre-release machines in particular,
168 * don't actually have SAGV.
170 if (IS_SKYLAKE(i915
) && ret
== -ENXIO
) {
171 drm_dbg(&i915
->drm
, "No SAGV found on system, ignoring\n");
172 i915
->display
.sagv
.status
= I915_SAGV_NOT_CONTROLLED
;
174 } else if (ret
< 0) {
175 drm_err(&i915
->drm
, "Failed to enable SAGV\n");
179 i915
->display
.sagv
.status
= I915_SAGV_ENABLED
;
182 static void skl_sagv_disable(struct drm_i915_private
*i915
)
186 if (!intel_has_sagv(i915
))
189 if (i915
->display
.sagv
.status
== I915_SAGV_DISABLED
)
192 drm_dbg_kms(&i915
->drm
, "Disabling SAGV\n");
193 /* bspec says to keep retrying for at least 1 ms */
194 ret
= skl_pcode_request(&i915
->uncore
, GEN9_PCODE_SAGV_CONTROL
,
196 GEN9_SAGV_IS_DISABLED
, GEN9_SAGV_IS_DISABLED
,
199 * Some skl systems, pre-release machines in particular,
200 * don't actually have SAGV.
202 if (IS_SKYLAKE(i915
) && ret
== -ENXIO
) {
203 drm_dbg(&i915
->drm
, "No SAGV found on system, ignoring\n");
204 i915
->display
.sagv
.status
= I915_SAGV_NOT_CONTROLLED
;
206 } else if (ret
< 0) {
207 drm_err(&i915
->drm
, "Failed to disable SAGV (%d)\n", ret
);
211 i915
->display
.sagv
.status
= I915_SAGV_DISABLED
;
214 static void skl_sagv_pre_plane_update(struct intel_atomic_state
*state
)
216 struct drm_i915_private
*i915
= to_i915(state
->base
.dev
);
217 const struct intel_bw_state
*new_bw_state
=
218 intel_atomic_get_new_bw_state(state
);
223 if (!intel_can_enable_sagv(i915
, new_bw_state
))
224 skl_sagv_disable(i915
);
227 static void skl_sagv_post_plane_update(struct intel_atomic_state
*state
)
229 struct drm_i915_private
*i915
= to_i915(state
->base
.dev
);
230 const struct intel_bw_state
*new_bw_state
=
231 intel_atomic_get_new_bw_state(state
);
236 if (intel_can_enable_sagv(i915
, new_bw_state
))
237 skl_sagv_enable(i915
);
240 static void icl_sagv_pre_plane_update(struct intel_atomic_state
*state
)
242 struct drm_i915_private
*i915
= to_i915(state
->base
.dev
);
243 const struct intel_bw_state
*old_bw_state
=
244 intel_atomic_get_old_bw_state(state
);
245 const struct intel_bw_state
*new_bw_state
=
246 intel_atomic_get_new_bw_state(state
);
247 u16 old_mask
, new_mask
;
252 old_mask
= old_bw_state
->qgv_points_mask
;
253 new_mask
= old_bw_state
->qgv_points_mask
| new_bw_state
->qgv_points_mask
;
255 if (old_mask
== new_mask
)
258 WARN_ON(!new_bw_state
->base
.changed
);
260 drm_dbg_kms(&i915
->drm
, "Restricting QGV points: 0x%x -> 0x%x\n",
264 * Restrict required qgv points before updating the configuration.
265 * According to BSpec we can't mask and unmask qgv points at the same
266 * time. Also masking should be done before updating the configuration
267 * and unmasking afterwards.
269 icl_pcode_restrict_qgv_points(i915
, new_mask
);
272 static void icl_sagv_post_plane_update(struct intel_atomic_state
*state
)
274 struct drm_i915_private
*i915
= to_i915(state
->base
.dev
);
275 const struct intel_bw_state
*old_bw_state
=
276 intel_atomic_get_old_bw_state(state
);
277 const struct intel_bw_state
*new_bw_state
=
278 intel_atomic_get_new_bw_state(state
);
279 u16 old_mask
, new_mask
;
284 old_mask
= old_bw_state
->qgv_points_mask
| new_bw_state
->qgv_points_mask
;
285 new_mask
= new_bw_state
->qgv_points_mask
;
287 if (old_mask
== new_mask
)
290 WARN_ON(!new_bw_state
->base
.changed
);
292 drm_dbg_kms(&i915
->drm
, "Relaxing QGV points: 0x%x -> 0x%x\n",
296 * Allow required qgv points after updating the configuration.
297 * According to BSpec we can't mask and unmask qgv points at the same
298 * time. Also masking should be done before updating the configuration
299 * and unmasking afterwards.
301 icl_pcode_restrict_qgv_points(i915
, new_mask
);
304 void intel_sagv_pre_plane_update(struct intel_atomic_state
*state
)
306 struct drm_i915_private
*i915
= to_i915(state
->base
.dev
);
309 * Just return if we can't control SAGV or don't have it.
310 * This is different from situation when we have SAGV but just can't
311 * afford it due to DBuf limitation - in case if SAGV is completely
312 * disabled in a BIOS, we are not even allowed to send a PCode request,
313 * as it will throw an error. So have to check it here.
315 if (!intel_has_sagv(i915
))
318 if (DISPLAY_VER(i915
) >= 11)
319 icl_sagv_pre_plane_update(state
);
321 skl_sagv_pre_plane_update(state
);
324 void intel_sagv_post_plane_update(struct intel_atomic_state
*state
)
326 struct drm_i915_private
*i915
= to_i915(state
->base
.dev
);
329 * Just return if we can't control SAGV or don't have it.
330 * This is different from situation when we have SAGV but just can't
331 * afford it due to DBuf limitation - in case if SAGV is completely
332 * disabled in a BIOS, we are not even allowed to send a PCode request,
333 * as it will throw an error. So have to check it here.
335 if (!intel_has_sagv(i915
))
338 if (DISPLAY_VER(i915
) >= 11)
339 icl_sagv_post_plane_update(state
);
341 skl_sagv_post_plane_update(state
);
344 static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state
*crtc_state
)
346 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
347 struct drm_i915_private
*i915
= to_i915(crtc
->base
.dev
);
348 enum plane_id plane_id
;
349 int max_level
= INT_MAX
;
351 if (!intel_has_sagv(i915
))
354 if (!crtc_state
->hw
.active
)
357 if (crtc_state
->hw
.pipe_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
360 for_each_plane_id_on_crtc(crtc
, plane_id
) {
361 const struct skl_plane_wm
*wm
=
362 &crtc_state
->wm
.skl
.optimal
.planes
[plane_id
];
365 /* Skip this plane if it's not enabled */
366 if (!wm
->wm
[0].enable
)
369 /* Find the highest enabled wm level for this plane */
370 for (level
= i915
->display
.wm
.num_levels
- 1;
371 !wm
->wm
[level
].enable
; --level
)
374 /* Highest common enabled wm level for all planes */
375 max_level
= min(level
, max_level
);
378 /* No enabled planes? */
379 if (max_level
== INT_MAX
)
382 for_each_plane_id_on_crtc(crtc
, plane_id
) {
383 const struct skl_plane_wm
*wm
=
384 &crtc_state
->wm
.skl
.optimal
.planes
[plane_id
];
387 * All enabled planes must have enabled a common wm level that
388 * can tolerate memory latencies higher than sagv_block_time_us
390 if (wm
->wm
[0].enable
&& !wm
->wm
[max_level
].can_sagv
)
397 static bool tgl_crtc_can_enable_sagv(const struct intel_crtc_state
*crtc_state
)
399 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
400 enum plane_id plane_id
;
402 if (!crtc_state
->hw
.active
)
405 for_each_plane_id_on_crtc(crtc
, plane_id
) {
406 const struct skl_plane_wm
*wm
=
407 &crtc_state
->wm
.skl
.optimal
.planes
[plane_id
];
409 if (wm
->wm
[0].enable
&& !wm
->sagv
.wm0
.enable
)
416 static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state
*crtc_state
)
418 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
419 struct drm_i915_private
*i915
= to_i915(crtc
->base
.dev
);
421 if (!i915
->display
.params
.enable_sagv
)
424 if (DISPLAY_VER(i915
) >= 12)
425 return tgl_crtc_can_enable_sagv(crtc_state
);
427 return skl_crtc_can_enable_sagv(crtc_state
);
430 bool intel_can_enable_sagv(struct drm_i915_private
*i915
,
431 const struct intel_bw_state
*bw_state
)
433 if (DISPLAY_VER(i915
) < 11 &&
434 bw_state
->active_pipes
&& !is_power_of_2(bw_state
->active_pipes
))
437 return bw_state
->pipe_sagv_reject
== 0;
440 static int intel_compute_sagv_mask(struct intel_atomic_state
*state
)
442 struct drm_i915_private
*i915
= to_i915(state
->base
.dev
);
444 struct intel_crtc
*crtc
;
445 struct intel_crtc_state
*new_crtc_state
;
446 struct intel_bw_state
*new_bw_state
= NULL
;
447 const struct intel_bw_state
*old_bw_state
= NULL
;
450 for_each_new_intel_crtc_in_state(state
, crtc
,
452 struct skl_pipe_wm
*pipe_wm
= &new_crtc_state
->wm
.skl
.optimal
;
454 new_bw_state
= intel_atomic_get_bw_state(state
);
455 if (IS_ERR(new_bw_state
))
456 return PTR_ERR(new_bw_state
);
458 old_bw_state
= intel_atomic_get_old_bw_state(state
);
461 * We store use_sagv_wm in the crtc state rather than relying on
462 * that bw state since we have no convenient way to get at the
463 * latter from the plane commit hooks (especially in the legacy
466 * drm_atomic_check_only() gets upset if we pull more crtcs
467 * into the state, so we have to calculate this based on the
468 * individual intel_crtc_can_enable_sagv() rather than
469 * the overall intel_can_enable_sagv(). Otherwise the
470 * crtcs not included in the commit would not switch to the
471 * SAGV watermarks when we are about to enable SAGV, and that
472 * would lead to underruns. This does mean extra power draw
473 * when only a subset of the crtcs are blocking SAGV as the
474 * other crtcs can't be allowed to use the more optimal
475 * normal (ie. non-SAGV) watermarks.
477 pipe_wm
->use_sagv_wm
= !HAS_HW_SAGV_WM(i915
) &&
478 DISPLAY_VER(i915
) >= 12 &&
479 intel_crtc_can_enable_sagv(new_crtc_state
);
481 if (intel_crtc_can_enable_sagv(new_crtc_state
))
482 new_bw_state
->pipe_sagv_reject
&= ~BIT(crtc
->pipe
);
484 new_bw_state
->pipe_sagv_reject
|= BIT(crtc
->pipe
);
490 new_bw_state
->active_pipes
=
491 intel_calc_active_pipes(state
, old_bw_state
->active_pipes
);
493 if (new_bw_state
->active_pipes
!= old_bw_state
->active_pipes
) {
494 ret
= intel_atomic_lock_global_state(&new_bw_state
->base
);
499 if (intel_can_enable_sagv(i915
, new_bw_state
) !=
500 intel_can_enable_sagv(i915
, old_bw_state
)) {
501 ret
= intel_atomic_serialize_global_state(&new_bw_state
->base
);
504 } else if (new_bw_state
->pipe_sagv_reject
!= old_bw_state
->pipe_sagv_reject
) {
505 ret
= intel_atomic_lock_global_state(&new_bw_state
->base
);
513 static u16
skl_ddb_entry_init(struct skl_ddb_entry
*entry
,
516 entry
->start
= start
;
522 static int intel_dbuf_slice_size(struct drm_i915_private
*i915
)
524 return DISPLAY_INFO(i915
)->dbuf
.size
/
525 hweight8(DISPLAY_INFO(i915
)->dbuf
.slice_mask
);
529 skl_ddb_entry_for_slices(struct drm_i915_private
*i915
, u8 slice_mask
,
530 struct skl_ddb_entry
*ddb
)
532 int slice_size
= intel_dbuf_slice_size(i915
);
540 ddb
->start
= (ffs(slice_mask
) - 1) * slice_size
;
541 ddb
->end
= fls(slice_mask
) * slice_size
;
543 WARN_ON(ddb
->start
>= ddb
->end
);
544 WARN_ON(ddb
->end
> DISPLAY_INFO(i915
)->dbuf
.size
);
547 static unsigned int mbus_ddb_offset(struct drm_i915_private
*i915
, u8 slice_mask
)
549 struct skl_ddb_entry ddb
;
551 if (slice_mask
& (BIT(DBUF_S1
) | BIT(DBUF_S2
)))
552 slice_mask
= BIT(DBUF_S1
);
553 else if (slice_mask
& (BIT(DBUF_S3
) | BIT(DBUF_S4
)))
554 slice_mask
= BIT(DBUF_S3
);
556 skl_ddb_entry_for_slices(i915
, slice_mask
, &ddb
);
561 u32
skl_ddb_dbuf_slice_mask(struct drm_i915_private
*i915
,
562 const struct skl_ddb_entry
*entry
)
564 int slice_size
= intel_dbuf_slice_size(i915
);
565 enum dbuf_slice start_slice
, end_slice
;
568 if (!skl_ddb_entry_size(entry
))
571 start_slice
= entry
->start
/ slice_size
;
572 end_slice
= (entry
->end
- 1) / slice_size
;
575 * Per plane DDB entry can in a really worst case be on multiple slices
576 * but single entry is anyway contigious.
578 while (start_slice
<= end_slice
) {
579 slice_mask
|= BIT(start_slice
);
586 static unsigned int intel_crtc_ddb_weight(const struct intel_crtc_state
*crtc_state
)
588 const struct drm_display_mode
*pipe_mode
= &crtc_state
->hw
.pipe_mode
;
589 int hdisplay
, vdisplay
;
591 if (!crtc_state
->hw
.active
)
595 * Watermark/ddb requirement highly depends upon width of the
596 * framebuffer, So instead of allocating DDB equally among pipes
597 * distribute DDB based on resolution/width of the display.
599 drm_mode_get_hv_timing(pipe_mode
, &hdisplay
, &vdisplay
);
604 static void intel_crtc_dbuf_weights(const struct intel_dbuf_state
*dbuf_state
,
606 unsigned int *weight_start
,
607 unsigned int *weight_end
,
608 unsigned int *weight_total
)
610 struct drm_i915_private
*i915
=
611 to_i915(dbuf_state
->base
.state
->base
.dev
);
618 for_each_pipe(i915
, pipe
) {
619 int weight
= dbuf_state
->weight
[pipe
];
622 * Do not account pipes using other slice sets
623 * luckily as of current BSpec slice sets do not partially
624 * intersect(pipes share either same one slice or same slice set
625 * i.e no partial intersection), so it is enough to check for
628 if (dbuf_state
->slices
[pipe
] != dbuf_state
->slices
[for_pipe
])
631 *weight_total
+= weight
;
632 if (pipe
< for_pipe
) {
633 *weight_start
+= weight
;
634 *weight_end
+= weight
;
635 } else if (pipe
== for_pipe
) {
636 *weight_end
+= weight
;
642 skl_crtc_allocate_ddb(struct intel_atomic_state
*state
, struct intel_crtc
*crtc
)
644 struct drm_i915_private
*i915
= to_i915(crtc
->base
.dev
);
645 unsigned int weight_total
, weight_start
, weight_end
;
646 const struct intel_dbuf_state
*old_dbuf_state
=
647 intel_atomic_get_old_dbuf_state(state
);
648 struct intel_dbuf_state
*new_dbuf_state
=
649 intel_atomic_get_new_dbuf_state(state
);
650 struct intel_crtc_state
*crtc_state
;
651 struct skl_ddb_entry ddb_slices
;
652 enum pipe pipe
= crtc
->pipe
;
653 unsigned int mbus_offset
= 0;
659 if (new_dbuf_state
->weight
[pipe
] == 0) {
660 skl_ddb_entry_init(&new_dbuf_state
->ddb
[pipe
], 0, 0);
664 dbuf_slice_mask
= new_dbuf_state
->slices
[pipe
];
666 skl_ddb_entry_for_slices(i915
, dbuf_slice_mask
, &ddb_slices
);
667 mbus_offset
= mbus_ddb_offset(i915
, dbuf_slice_mask
);
668 ddb_range_size
= skl_ddb_entry_size(&ddb_slices
);
670 intel_crtc_dbuf_weights(new_dbuf_state
, pipe
,
671 &weight_start
, &weight_end
, &weight_total
);
673 start
= ddb_range_size
* weight_start
/ weight_total
;
674 end
= ddb_range_size
* weight_end
/ weight_total
;
676 skl_ddb_entry_init(&new_dbuf_state
->ddb
[pipe
],
677 ddb_slices
.start
- mbus_offset
+ start
,
678 ddb_slices
.start
- mbus_offset
+ end
);
681 if (old_dbuf_state
->slices
[pipe
] == new_dbuf_state
->slices
[pipe
] &&
682 skl_ddb_entry_equal(&old_dbuf_state
->ddb
[pipe
],
683 &new_dbuf_state
->ddb
[pipe
]))
686 ret
= intel_atomic_lock_global_state(&new_dbuf_state
->base
);
690 crtc_state
= intel_atomic_get_crtc_state(&state
->base
, crtc
);
691 if (IS_ERR(crtc_state
))
692 return PTR_ERR(crtc_state
);
695 * Used for checking overlaps, so we need absolute
696 * offsets instead of MBUS relative offsets.
698 crtc_state
->wm
.skl
.ddb
.start
= mbus_offset
+ new_dbuf_state
->ddb
[pipe
].start
;
699 crtc_state
->wm
.skl
.ddb
.end
= mbus_offset
+ new_dbuf_state
->ddb
[pipe
].end
;
701 drm_dbg_kms(&i915
->drm
,
702 "[CRTC:%d:%s] dbuf slices 0x%x -> 0x%x, ddb (%d - %d) -> (%d - %d), active pipes 0x%x -> 0x%x\n",
703 crtc
->base
.base
.id
, crtc
->base
.name
,
704 old_dbuf_state
->slices
[pipe
], new_dbuf_state
->slices
[pipe
],
705 old_dbuf_state
->ddb
[pipe
].start
, old_dbuf_state
->ddb
[pipe
].end
,
706 new_dbuf_state
->ddb
[pipe
].start
, new_dbuf_state
->ddb
[pipe
].end
,
707 old_dbuf_state
->active_pipes
, new_dbuf_state
->active_pipes
);
712 static int skl_compute_wm_params(const struct intel_crtc_state
*crtc_state
,
713 int width
, const struct drm_format_info
*format
,
714 u64 modifier
, unsigned int rotation
,
715 u32 plane_pixel_rate
, struct skl_wm_params
*wp
,
718 static void skl_compute_plane_wm(const struct intel_crtc_state
*crtc_state
,
719 struct intel_plane
*plane
,
721 unsigned int latency
,
722 const struct skl_wm_params
*wp
,
723 const struct skl_wm_level
*result_prev
,
724 struct skl_wm_level
*result
/* out */);
726 static unsigned int skl_wm_latency(struct drm_i915_private
*i915
, int level
,
727 const struct skl_wm_params
*wp
)
729 unsigned int latency
= i915
->display
.wm
.skl_latency
[level
];
735 * WaIncreaseLatencyIPCEnabled: kbl,cfl
736 * Display WA #1141: kbl,cfl
738 if ((IS_KABYLAKE(i915
) || IS_COFFEELAKE(i915
) || IS_COMETLAKE(i915
)) &&
739 skl_watermark_ipc_enabled(i915
))
742 if (skl_needs_memory_bw_wa(i915
) && wp
&& wp
->x_tiled
)
749 skl_cursor_allocation(const struct intel_crtc_state
*crtc_state
,
752 struct intel_plane
*plane
= to_intel_plane(crtc_state
->uapi
.crtc
->cursor
);
753 struct drm_i915_private
*i915
= to_i915(crtc_state
->uapi
.crtc
->dev
);
754 struct skl_wm_level wm
= {};
755 int ret
, min_ddb_alloc
= 0;
756 struct skl_wm_params wp
;
759 ret
= skl_compute_wm_params(crtc_state
, 256,
760 drm_format_info(DRM_FORMAT_ARGB8888
),
761 DRM_FORMAT_MOD_LINEAR
,
763 crtc_state
->pixel_rate
, &wp
, 0);
764 drm_WARN_ON(&i915
->drm
, ret
);
766 for (level
= 0; level
< i915
->display
.wm
.num_levels
; level
++) {
767 unsigned int latency
= skl_wm_latency(i915
, level
, &wp
);
769 skl_compute_plane_wm(crtc_state
, plane
, level
, latency
, &wp
, &wm
, &wm
);
770 if (wm
.min_ddb_alloc
== U16_MAX
)
773 min_ddb_alloc
= wm
.min_ddb_alloc
;
776 return max(num_active
== 1 ? 32 : 8, min_ddb_alloc
);
779 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry
*entry
, u32 reg
)
781 skl_ddb_entry_init(entry
,
782 REG_FIELD_GET(PLANE_BUF_START_MASK
, reg
),
783 REG_FIELD_GET(PLANE_BUF_END_MASK
, reg
));
789 skl_ddb_get_hw_plane_state(struct drm_i915_private
*i915
,
790 const enum pipe pipe
,
791 const enum plane_id plane_id
,
792 struct skl_ddb_entry
*ddb
,
793 struct skl_ddb_entry
*ddb_y
)
797 /* Cursor doesn't support NV12/planar, so no extra calculation needed */
798 if (plane_id
== PLANE_CURSOR
) {
799 val
= intel_de_read(i915
, CUR_BUF_CFG(pipe
));
800 skl_ddb_entry_init_from_hw(ddb
, val
);
804 val
= intel_de_read(i915
, PLANE_BUF_CFG(pipe
, plane_id
));
805 skl_ddb_entry_init_from_hw(ddb
, val
);
807 if (DISPLAY_VER(i915
) >= 11)
810 val
= intel_de_read(i915
, PLANE_NV12_BUF_CFG(pipe
, plane_id
));
811 skl_ddb_entry_init_from_hw(ddb_y
, val
);
814 static void skl_pipe_ddb_get_hw_state(struct intel_crtc
*crtc
,
815 struct skl_ddb_entry
*ddb
,
816 struct skl_ddb_entry
*ddb_y
)
818 struct drm_i915_private
*i915
= to_i915(crtc
->base
.dev
);
819 enum intel_display_power_domain power_domain
;
820 enum pipe pipe
= crtc
->pipe
;
821 intel_wakeref_t wakeref
;
822 enum plane_id plane_id
;
824 power_domain
= POWER_DOMAIN_PIPE(pipe
);
825 wakeref
= intel_display_power_get_if_enabled(i915
, power_domain
);
829 for_each_plane_id_on_crtc(crtc
, plane_id
)
830 skl_ddb_get_hw_plane_state(i915
, pipe
,
835 intel_display_power_put(i915
, power_domain
, wakeref
);
838 struct dbuf_slice_conf_entry
{
840 u8 dbuf_mask
[I915_MAX_PIPES
];
845 * Table taken from Bspec 12716
846 * Pipes do have some preferred DBuf slice affinity,
847 * plus there are some hardcoded requirements on how
848 * those should be distributed for multipipe scenarios.
849 * For more DBuf slices algorithm can get even more messy
850 * and less readable, so decided to use a table almost
851 * as is from BSpec itself - that way it is at least easier
852 * to compare, change and check.
854 static const struct dbuf_slice_conf_entry icl_allowed_dbufs
[] =
855 /* Autogenerated with igt/tools/intel_dbuf_map tool: */
858 .active_pipes
= BIT(PIPE_A
),
860 [PIPE_A
] = BIT(DBUF_S1
),
864 .active_pipes
= BIT(PIPE_B
),
866 [PIPE_B
] = BIT(DBUF_S1
),
870 .active_pipes
= BIT(PIPE_A
) | BIT(PIPE_B
),
872 [PIPE_A
] = BIT(DBUF_S1
),
873 [PIPE_B
] = BIT(DBUF_S2
),
877 .active_pipes
= BIT(PIPE_C
),
879 [PIPE_C
] = BIT(DBUF_S2
),
883 .active_pipes
= BIT(PIPE_A
) | BIT(PIPE_C
),
885 [PIPE_A
] = BIT(DBUF_S1
),
886 [PIPE_C
] = BIT(DBUF_S2
),
890 .active_pipes
= BIT(PIPE_B
) | BIT(PIPE_C
),
892 [PIPE_B
] = BIT(DBUF_S1
),
893 [PIPE_C
] = BIT(DBUF_S2
),
897 .active_pipes
= BIT(PIPE_A
) | BIT(PIPE_B
) | BIT(PIPE_C
),
899 [PIPE_A
] = BIT(DBUF_S1
),
900 [PIPE_B
] = BIT(DBUF_S1
),
901 [PIPE_C
] = BIT(DBUF_S2
),
908 * Table taken from Bspec 49255
909 * Pipes do have some preferred DBuf slice affinity,
910 * plus there are some hardcoded requirements on how
911 * those should be distributed for multipipe scenarios.
912 * For more DBuf slices algorithm can get even more messy
913 * and less readable, so decided to use a table almost
914 * as is from BSpec itself - that way it is at least easier
915 * to compare, change and check.
917 static const struct dbuf_slice_conf_entry tgl_allowed_dbufs
[] =
918 /* Autogenerated with igt/tools/intel_dbuf_map tool: */
921 .active_pipes
= BIT(PIPE_A
),
923 [PIPE_A
] = BIT(DBUF_S1
) | BIT(DBUF_S2
),
927 .active_pipes
= BIT(PIPE_B
),
929 [PIPE_B
] = BIT(DBUF_S1
) | BIT(DBUF_S2
),
933 .active_pipes
= BIT(PIPE_A
) | BIT(PIPE_B
),
935 [PIPE_A
] = BIT(DBUF_S2
),
936 [PIPE_B
] = BIT(DBUF_S1
),
940 .active_pipes
= BIT(PIPE_C
),
942 [PIPE_C
] = BIT(DBUF_S2
) | BIT(DBUF_S1
),
946 .active_pipes
= BIT(PIPE_A
) | BIT(PIPE_C
),
948 [PIPE_A
] = BIT(DBUF_S1
),
949 [PIPE_C
] = BIT(DBUF_S2
),
953 .active_pipes
= BIT(PIPE_B
) | BIT(PIPE_C
),
955 [PIPE_B
] = BIT(DBUF_S1
),
956 [PIPE_C
] = BIT(DBUF_S2
),
960 .active_pipes
= BIT(PIPE_A
) | BIT(PIPE_B
) | BIT(PIPE_C
),
962 [PIPE_A
] = BIT(DBUF_S1
),
963 [PIPE_B
] = BIT(DBUF_S1
),
964 [PIPE_C
] = BIT(DBUF_S2
),
968 .active_pipes
= BIT(PIPE_D
),
970 [PIPE_D
] = BIT(DBUF_S2
) | BIT(DBUF_S1
),
974 .active_pipes
= BIT(PIPE_A
) | BIT(PIPE_D
),
976 [PIPE_A
] = BIT(DBUF_S1
),
977 [PIPE_D
] = BIT(DBUF_S2
),
981 .active_pipes
= BIT(PIPE_B
) | BIT(PIPE_D
),
983 [PIPE_B
] = BIT(DBUF_S1
),
984 [PIPE_D
] = BIT(DBUF_S2
),
988 .active_pipes
= BIT(PIPE_A
) | BIT(PIPE_B
) | BIT(PIPE_D
),
990 [PIPE_A
] = BIT(DBUF_S1
),
991 [PIPE_B
] = BIT(DBUF_S1
),
992 [PIPE_D
] = BIT(DBUF_S2
),
996 .active_pipes
= BIT(PIPE_C
) | BIT(PIPE_D
),
998 [PIPE_C
] = BIT(DBUF_S1
),
999 [PIPE_D
] = BIT(DBUF_S2
),
1003 .active_pipes
= BIT(PIPE_A
) | BIT(PIPE_C
) | BIT(PIPE_D
),
1005 [PIPE_A
] = BIT(DBUF_S1
),
1006 [PIPE_C
] = BIT(DBUF_S2
),
1007 [PIPE_D
] = BIT(DBUF_S2
),
1011 .active_pipes
= BIT(PIPE_B
) | BIT(PIPE_C
) | BIT(PIPE_D
),
1013 [PIPE_B
] = BIT(DBUF_S1
),
1014 [PIPE_C
] = BIT(DBUF_S2
),
1015 [PIPE_D
] = BIT(DBUF_S2
),
1019 .active_pipes
= BIT(PIPE_A
) | BIT(PIPE_B
) | BIT(PIPE_C
) | BIT(PIPE_D
),
1021 [PIPE_A
] = BIT(DBUF_S1
),
1022 [PIPE_B
] = BIT(DBUF_S1
),
1023 [PIPE_C
] = BIT(DBUF_S2
),
1024 [PIPE_D
] = BIT(DBUF_S2
),
1030 static const struct dbuf_slice_conf_entry dg2_allowed_dbufs
[] = {
1032 .active_pipes
= BIT(PIPE_A
),
1034 [PIPE_A
] = BIT(DBUF_S1
) | BIT(DBUF_S2
),
1038 .active_pipes
= BIT(PIPE_B
),
1040 [PIPE_B
] = BIT(DBUF_S1
) | BIT(DBUF_S2
),
1044 .active_pipes
= BIT(PIPE_A
) | BIT(PIPE_B
),
1046 [PIPE_A
] = BIT(DBUF_S1
),
1047 [PIPE_B
] = BIT(DBUF_S2
),
1051 .active_pipes
= BIT(PIPE_C
),
1053 [PIPE_C
] = BIT(DBUF_S3
) | BIT(DBUF_S4
),
1057 .active_pipes
= BIT(PIPE_A
) | BIT(PIPE_C
),
1059 [PIPE_A
] = BIT(DBUF_S1
) | BIT(DBUF_S2
),
1060 [PIPE_C
] = BIT(DBUF_S3
) | BIT(DBUF_S4
),
1064 .active_pipes
= BIT(PIPE_B
) | BIT(PIPE_C
),
1066 [PIPE_B
] = BIT(DBUF_S1
) | BIT(DBUF_S2
),
1067 [PIPE_C
] = BIT(DBUF_S3
) | BIT(DBUF_S4
),
1071 .active_pipes
= BIT(PIPE_A
) | BIT(PIPE_B
) | BIT(PIPE_C
),
1073 [PIPE_A
] = BIT(DBUF_S1
),
1074 [PIPE_B
] = BIT(DBUF_S2
),
1075 [PIPE_C
] = BIT(DBUF_S3
) | BIT(DBUF_S4
),
1079 .active_pipes
= BIT(PIPE_D
),
1081 [PIPE_D
] = BIT(DBUF_S3
) | BIT(DBUF_S4
),
1085 .active_pipes
= BIT(PIPE_A
) | BIT(PIPE_D
),
1087 [PIPE_A
] = BIT(DBUF_S1
) | BIT(DBUF_S2
),
1088 [PIPE_D
] = BIT(DBUF_S3
) | BIT(DBUF_S4
),
1092 .active_pipes
= BIT(PIPE_B
) | BIT(PIPE_D
),
1094 [PIPE_B
] = BIT(DBUF_S1
) | BIT(DBUF_S2
),
1095 [PIPE_D
] = BIT(DBUF_S3
) | BIT(DBUF_S4
),
1099 .active_pipes
= BIT(PIPE_A
) | BIT(PIPE_B
) | BIT(PIPE_D
),
1101 [PIPE_A
] = BIT(DBUF_S1
),
1102 [PIPE_B
] = BIT(DBUF_S2
),
1103 [PIPE_D
] = BIT(DBUF_S3
) | BIT(DBUF_S4
),
1107 .active_pipes
= BIT(PIPE_C
) | BIT(PIPE_D
),
1109 [PIPE_C
] = BIT(DBUF_S3
),
1110 [PIPE_D
] = BIT(DBUF_S4
),
1114 .active_pipes
= BIT(PIPE_A
) | BIT(PIPE_C
) | BIT(PIPE_D
),
1116 [PIPE_A
] = BIT(DBUF_S1
) | BIT(DBUF_S2
),
1117 [PIPE_C
] = BIT(DBUF_S3
),
1118 [PIPE_D
] = BIT(DBUF_S4
),
1122 .active_pipes
= BIT(PIPE_B
) | BIT(PIPE_C
) | BIT(PIPE_D
),
1124 [PIPE_B
] = BIT(DBUF_S1
) | BIT(DBUF_S2
),
1125 [PIPE_C
] = BIT(DBUF_S3
),
1126 [PIPE_D
] = BIT(DBUF_S4
),
1130 .active_pipes
= BIT(PIPE_A
) | BIT(PIPE_B
) | BIT(PIPE_C
) | BIT(PIPE_D
),
1132 [PIPE_A
] = BIT(DBUF_S1
),
1133 [PIPE_B
] = BIT(DBUF_S2
),
1134 [PIPE_C
] = BIT(DBUF_S3
),
1135 [PIPE_D
] = BIT(DBUF_S4
),
1141 static const struct dbuf_slice_conf_entry adlp_allowed_dbufs
[] = {
1143 * Keep the join_mbus cases first so check_mbus_joined()
1144 * will prefer them over the !join_mbus cases.
1147 .active_pipes
= BIT(PIPE_A
),
1149 [PIPE_A
] = BIT(DBUF_S1
) | BIT(DBUF_S2
) | BIT(DBUF_S3
) | BIT(DBUF_S4
),
1154 .active_pipes
= BIT(PIPE_B
),
1156 [PIPE_B
] = BIT(DBUF_S1
) | BIT(DBUF_S2
) | BIT(DBUF_S3
) | BIT(DBUF_S4
),
1161 .active_pipes
= BIT(PIPE_A
),
1163 [PIPE_A
] = BIT(DBUF_S1
) | BIT(DBUF_S2
),
1168 .active_pipes
= BIT(PIPE_B
),
1170 [PIPE_B
] = BIT(DBUF_S3
) | BIT(DBUF_S4
),
1175 .active_pipes
= BIT(PIPE_A
) | BIT(PIPE_B
),
1177 [PIPE_A
] = BIT(DBUF_S1
) | BIT(DBUF_S2
),
1178 [PIPE_B
] = BIT(DBUF_S3
) | BIT(DBUF_S4
),
1182 .active_pipes
= BIT(PIPE_C
),
1184 [PIPE_C
] = BIT(DBUF_S3
) | BIT(DBUF_S4
),
1188 .active_pipes
= BIT(PIPE_A
) | BIT(PIPE_C
),
1190 [PIPE_A
] = BIT(DBUF_S1
) | BIT(DBUF_S2
),
1191 [PIPE_C
] = BIT(DBUF_S3
) | BIT(DBUF_S4
),
1195 .active_pipes
= BIT(PIPE_B
) | BIT(PIPE_C
),
1197 [PIPE_B
] = BIT(DBUF_S3
) | BIT(DBUF_S4
),
1198 [PIPE_C
] = BIT(DBUF_S3
) | BIT(DBUF_S4
),
1202 .active_pipes
= BIT(PIPE_A
) | BIT(PIPE_B
) | BIT(PIPE_C
),
1204 [PIPE_A
] = BIT(DBUF_S1
) | BIT(DBUF_S2
),
1205 [PIPE_B
] = BIT(DBUF_S3
) | BIT(DBUF_S4
),
1206 [PIPE_C
] = BIT(DBUF_S3
) | BIT(DBUF_S4
),
1210 .active_pipes
= BIT(PIPE_D
),
1212 [PIPE_D
] = BIT(DBUF_S1
) | BIT(DBUF_S2
),
1216 .active_pipes
= BIT(PIPE_A
) | BIT(PIPE_D
),
1218 [PIPE_A
] = BIT(DBUF_S1
) | BIT(DBUF_S2
),
1219 [PIPE_D
] = BIT(DBUF_S1
) | BIT(DBUF_S2
),
1223 .active_pipes
= BIT(PIPE_B
) | BIT(PIPE_D
),
1225 [PIPE_B
] = BIT(DBUF_S3
) | BIT(DBUF_S4
),
1226 [PIPE_D
] = BIT(DBUF_S1
) | BIT(DBUF_S2
),
1230 .active_pipes
= BIT(PIPE_A
) | BIT(PIPE_B
) | BIT(PIPE_D
),
1232 [PIPE_A
] = BIT(DBUF_S1
) | BIT(DBUF_S2
),
1233 [PIPE_B
] = BIT(DBUF_S3
) | BIT(DBUF_S4
),
1234 [PIPE_D
] = BIT(DBUF_S1
) | BIT(DBUF_S2
),
1238 .active_pipes
= BIT(PIPE_C
) | BIT(PIPE_D
),
1240 [PIPE_C
] = BIT(DBUF_S3
) | BIT(DBUF_S4
),
1241 [PIPE_D
] = BIT(DBUF_S1
) | BIT(DBUF_S2
),
1245 .active_pipes
= BIT(PIPE_A
) | BIT(PIPE_C
) | BIT(PIPE_D
),
1247 [PIPE_A
] = BIT(DBUF_S1
) | BIT(DBUF_S2
),
1248 [PIPE_C
] = BIT(DBUF_S3
) | BIT(DBUF_S4
),
1249 [PIPE_D
] = BIT(DBUF_S1
) | BIT(DBUF_S2
),
1253 .active_pipes
= BIT(PIPE_B
) | BIT(PIPE_C
) | BIT(PIPE_D
),
1255 [PIPE_B
] = BIT(DBUF_S3
) | BIT(DBUF_S4
),
1256 [PIPE_C
] = BIT(DBUF_S3
) | BIT(DBUF_S4
),
1257 [PIPE_D
] = BIT(DBUF_S1
) | BIT(DBUF_S2
),
1261 .active_pipes
= BIT(PIPE_A
) | BIT(PIPE_B
) | BIT(PIPE_C
) | BIT(PIPE_D
),
1263 [PIPE_A
] = BIT(DBUF_S1
) | BIT(DBUF_S2
),
1264 [PIPE_B
] = BIT(DBUF_S3
) | BIT(DBUF_S4
),
1265 [PIPE_C
] = BIT(DBUF_S3
) | BIT(DBUF_S4
),
1266 [PIPE_D
] = BIT(DBUF_S1
) | BIT(DBUF_S2
),
1273 static bool check_mbus_joined(u8 active_pipes
,
1274 const struct dbuf_slice_conf_entry
*dbuf_slices
)
1278 for (i
= 0; dbuf_slices
[i
].active_pipes
!= 0; i
++) {
1279 if (dbuf_slices
[i
].active_pipes
== active_pipes
)
1280 return dbuf_slices
[i
].join_mbus
;
1285 static bool adlp_check_mbus_joined(u8 active_pipes
)
1287 return check_mbus_joined(active_pipes
, adlp_allowed_dbufs
);
1290 static u8
compute_dbuf_slices(enum pipe pipe
, u8 active_pipes
, bool join_mbus
,
1291 const struct dbuf_slice_conf_entry
*dbuf_slices
)
1295 for (i
= 0; dbuf_slices
[i
].active_pipes
!= 0; i
++) {
1296 if (dbuf_slices
[i
].active_pipes
== active_pipes
&&
1297 dbuf_slices
[i
].join_mbus
== join_mbus
)
1298 return dbuf_slices
[i
].dbuf_mask
[pipe
];
1304 * This function finds an entry with same enabled pipe configuration and
1305 * returns correspondent DBuf slice mask as stated in BSpec for particular
1308 static u8
icl_compute_dbuf_slices(enum pipe pipe
, u8 active_pipes
, bool join_mbus
)
1311 * FIXME: For ICL this is still a bit unclear as prev BSpec revision
1312 * required calculating "pipe ratio" in order to determine
1313 * if one or two slices can be used for single pipe configurations
1314 * as additional constraint to the existing table.
1315 * However based on recent info, it should be not "pipe ratio"
1316 * but rather ratio between pixel_rate and cdclk with additional
1317 * constants, so for now we are using only table until this is
1318 * clarified. Also this is the reason why crtc_state param is
1319 * still here - we will need it once those additional constraints
1322 return compute_dbuf_slices(pipe
, active_pipes
, join_mbus
,
1326 static u8
tgl_compute_dbuf_slices(enum pipe pipe
, u8 active_pipes
, bool join_mbus
)
1328 return compute_dbuf_slices(pipe
, active_pipes
, join_mbus
,
1332 static u8
adlp_compute_dbuf_slices(enum pipe pipe
, u8 active_pipes
, bool join_mbus
)
1334 return compute_dbuf_slices(pipe
, active_pipes
, join_mbus
,
1335 adlp_allowed_dbufs
);
1338 static u8
dg2_compute_dbuf_slices(enum pipe pipe
, u8 active_pipes
, bool join_mbus
)
1340 return compute_dbuf_slices(pipe
, active_pipes
, join_mbus
,
1344 static u8
skl_compute_dbuf_slices(struct intel_crtc
*crtc
, u8 active_pipes
, bool join_mbus
)
1346 struct drm_i915_private
*i915
= to_i915(crtc
->base
.dev
);
1347 enum pipe pipe
= crtc
->pipe
;
1350 return dg2_compute_dbuf_slices(pipe
, active_pipes
, join_mbus
);
1351 else if (DISPLAY_VER(i915
) >= 13)
1352 return adlp_compute_dbuf_slices(pipe
, active_pipes
, join_mbus
);
1353 else if (DISPLAY_VER(i915
) == 12)
1354 return tgl_compute_dbuf_slices(pipe
, active_pipes
, join_mbus
);
1355 else if (DISPLAY_VER(i915
) == 11)
1356 return icl_compute_dbuf_slices(pipe
, active_pipes
, join_mbus
);
1358 * For anything else just return one slice yet.
1359 * Should be extended for other platforms.
1361 return active_pipes
& BIT(pipe
) ? BIT(DBUF_S1
) : 0;
1365 use_minimal_wm0_only(const struct intel_crtc_state
*crtc_state
,
1366 struct intel_plane
*plane
)
1368 struct drm_i915_private
*i915
= to_i915(plane
->base
.dev
);
1370 return DISPLAY_VER(i915
) >= 13 &&
1371 crtc_state
->uapi
.async_flip
&&
1376 skl_total_relative_data_rate(const struct intel_crtc_state
*crtc_state
)
1378 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
1379 struct drm_i915_private
*i915
= to_i915(crtc
->base
.dev
);
1380 enum plane_id plane_id
;
1383 for_each_plane_id_on_crtc(crtc
, plane_id
) {
1384 if (plane_id
== PLANE_CURSOR
)
1387 data_rate
+= crtc_state
->rel_data_rate
[plane_id
];
1389 if (DISPLAY_VER(i915
) < 11)
1390 data_rate
+= crtc_state
->rel_data_rate_y
[plane_id
];
1396 static const struct skl_wm_level
*
1397 skl_plane_wm_level(const struct skl_pipe_wm
*pipe_wm
,
1398 enum plane_id plane_id
,
1401 const struct skl_plane_wm
*wm
= &pipe_wm
->planes
[plane_id
];
1403 if (level
== 0 && pipe_wm
->use_sagv_wm
)
1404 return &wm
->sagv
.wm0
;
1406 return &wm
->wm
[level
];
1409 static const struct skl_wm_level
*
1410 skl_plane_trans_wm(const struct skl_pipe_wm
*pipe_wm
,
1411 enum plane_id plane_id
)
1413 const struct skl_plane_wm
*wm
= &pipe_wm
->planes
[plane_id
];
1415 if (pipe_wm
->use_sagv_wm
)
1416 return &wm
->sagv
.trans_wm
;
1418 return &wm
->trans_wm
;
1422 * We only disable the watermarks for each plane if
1423 * they exceed the ddb allocation of said plane. This
1424 * is done so that we don't end up touching cursor
1425 * watermarks needlessly when some other plane reduces
1426 * our max possible watermark level.
1428 * Bspec has this to say about the PLANE_WM enable bit:
1429 * "All the watermarks at this level for all enabled
1430 * planes must be enabled before the level will be used."
1431 * So this is actually safe to do.
1434 skl_check_wm_level(struct skl_wm_level
*wm
, const struct skl_ddb_entry
*ddb
)
1436 if (wm
->min_ddb_alloc
> skl_ddb_entry_size(ddb
))
1437 memset(wm
, 0, sizeof(*wm
));
1441 skl_check_nv12_wm_level(struct skl_wm_level
*wm
, struct skl_wm_level
*uv_wm
,
1442 const struct skl_ddb_entry
*ddb_y
, const struct skl_ddb_entry
*ddb
)
1444 if (wm
->min_ddb_alloc
> skl_ddb_entry_size(ddb_y
) ||
1445 uv_wm
->min_ddb_alloc
> skl_ddb_entry_size(ddb
)) {
1446 memset(wm
, 0, sizeof(*wm
));
1447 memset(uv_wm
, 0, sizeof(*uv_wm
));
1451 static bool skl_need_wm_copy_wa(struct drm_i915_private
*i915
, int level
,
1452 const struct skl_plane_wm
*wm
)
1455 * Wa_1408961008:icl, ehl
1456 * Wa_14012656716:tgl, adl
1457 * Wa_14017887344:icl
1458 * Wa_14017868169:adl, tgl
1459 * Due to some power saving optimizations, different subsystems
1460 * like PSR, might still use even disabled wm level registers,
1461 * for "reference", so lets keep at least the values sane.
1462 * Considering amount of WA requiring us to do similar things, was
1463 * decided to simply do it for all of the platforms, as those wm
1464 * levels are disabled, this isn't going to do harm anyway.
1466 return level
> 0 && !wm
->wm
[level
].enable
;
1469 struct skl_plane_ddb_iter
{
1475 skl_allocate_plane_ddb(struct skl_plane_ddb_iter
*iter
,
1476 struct skl_ddb_entry
*ddb
,
1477 const struct skl_wm_level
*wm
,
1480 u16 size
, extra
= 0;
1483 extra
= min_t(u16
, iter
->size
,
1484 DIV64_U64_ROUND_UP(iter
->size
* data_rate
,
1486 iter
->size
-= extra
;
1487 iter
->data_rate
-= data_rate
;
1491 * Keep ddb entry of all disabled planes explicitly zeroed
1492 * to avoid skl_ddb_add_affected_planes() adding them to
1493 * the state when other planes change their allocations.
1495 size
= wm
->min_ddb_alloc
+ extra
;
1497 iter
->start
= skl_ddb_entry_init(ddb
, iter
->start
,
1498 iter
->start
+ size
);
1502 skl_crtc_allocate_plane_ddb(struct intel_atomic_state
*state
,
1503 struct intel_crtc
*crtc
)
1505 struct drm_i915_private
*i915
= to_i915(crtc
->base
.dev
);
1506 struct intel_crtc_state
*crtc_state
=
1507 intel_atomic_get_new_crtc_state(state
, crtc
);
1508 const struct intel_dbuf_state
*dbuf_state
=
1509 intel_atomic_get_new_dbuf_state(state
);
1510 const struct skl_ddb_entry
*alloc
= &dbuf_state
->ddb
[crtc
->pipe
];
1511 int num_active
= hweight8(dbuf_state
->active_pipes
);
1512 struct skl_plane_ddb_iter iter
;
1513 enum plane_id plane_id
;
1518 /* Clear the partitioning for disabled planes. */
1519 memset(crtc_state
->wm
.skl
.plane_ddb
, 0, sizeof(crtc_state
->wm
.skl
.plane_ddb
));
1520 memset(crtc_state
->wm
.skl
.plane_ddb_y
, 0, sizeof(crtc_state
->wm
.skl
.plane_ddb_y
));
1522 if (!crtc_state
->hw
.active
)
1525 iter
.start
= alloc
->start
;
1526 iter
.size
= skl_ddb_entry_size(alloc
);
1530 /* Allocate fixed number of blocks for cursor. */
1531 cursor_size
= skl_cursor_allocation(crtc_state
, num_active
);
1532 iter
.size
-= cursor_size
;
1533 skl_ddb_entry_init(&crtc_state
->wm
.skl
.plane_ddb
[PLANE_CURSOR
],
1534 alloc
->end
- cursor_size
, alloc
->end
);
1536 iter
.data_rate
= skl_total_relative_data_rate(crtc_state
);
1539 * Find the highest watermark level for which we can satisfy the block
1540 * requirement of active planes.
1542 for (level
= i915
->display
.wm
.num_levels
- 1; level
>= 0; level
--) {
1544 for_each_plane_id_on_crtc(crtc
, plane_id
) {
1545 const struct skl_plane_wm
*wm
=
1546 &crtc_state
->wm
.skl
.optimal
.planes
[plane_id
];
1548 if (plane_id
== PLANE_CURSOR
) {
1549 const struct skl_ddb_entry
*ddb
=
1550 &crtc_state
->wm
.skl
.plane_ddb
[plane_id
];
1552 if (wm
->wm
[level
].min_ddb_alloc
> skl_ddb_entry_size(ddb
)) {
1553 drm_WARN_ON(&i915
->drm
,
1554 wm
->wm
[level
].min_ddb_alloc
!= U16_MAX
);
1561 blocks
+= wm
->wm
[level
].min_ddb_alloc
;
1562 blocks
+= wm
->uv_wm
[level
].min_ddb_alloc
;
1565 if (blocks
<= iter
.size
) {
1566 iter
.size
-= blocks
;
1572 drm_dbg_kms(&i915
->drm
,
1573 "Requested display configuration exceeds system DDB limitations");
1574 drm_dbg_kms(&i915
->drm
, "minimum required %d/%d\n",
1579 /* avoid the WARN later when we don't allocate any extra DDB */
1580 if (iter
.data_rate
== 0)
1584 * Grant each plane the blocks it requires at the highest achievable
1585 * watermark level, plus an extra share of the leftover blocks
1586 * proportional to its relative data rate.
1588 for_each_plane_id_on_crtc(crtc
, plane_id
) {
1589 struct skl_ddb_entry
*ddb
=
1590 &crtc_state
->wm
.skl
.plane_ddb
[plane_id
];
1591 struct skl_ddb_entry
*ddb_y
=
1592 &crtc_state
->wm
.skl
.plane_ddb_y
[plane_id
];
1593 const struct skl_plane_wm
*wm
=
1594 &crtc_state
->wm
.skl
.optimal
.planes
[plane_id
];
1596 if (plane_id
== PLANE_CURSOR
)
1599 if (DISPLAY_VER(i915
) < 11 &&
1600 crtc_state
->nv12_planes
& BIT(plane_id
)) {
1601 skl_allocate_plane_ddb(&iter
, ddb_y
, &wm
->wm
[level
],
1602 crtc_state
->rel_data_rate_y
[plane_id
]);
1603 skl_allocate_plane_ddb(&iter
, ddb
, &wm
->uv_wm
[level
],
1604 crtc_state
->rel_data_rate
[plane_id
]);
1606 skl_allocate_plane_ddb(&iter
, ddb
, &wm
->wm
[level
],
1607 crtc_state
->rel_data_rate
[plane_id
]);
1610 drm_WARN_ON(&i915
->drm
, iter
.size
!= 0 || iter
.data_rate
!= 0);
1613 * When we calculated watermark values we didn't know how high
1614 * of a level we'd actually be able to hit, so we just marked
1615 * all levels as "enabled." Go back now and disable the ones
1616 * that aren't actually possible.
1618 for (level
++; level
< i915
->display
.wm
.num_levels
; level
++) {
1619 for_each_plane_id_on_crtc(crtc
, plane_id
) {
1620 const struct skl_ddb_entry
*ddb
=
1621 &crtc_state
->wm
.skl
.plane_ddb
[plane_id
];
1622 const struct skl_ddb_entry
*ddb_y
=
1623 &crtc_state
->wm
.skl
.plane_ddb_y
[plane_id
];
1624 struct skl_plane_wm
*wm
=
1625 &crtc_state
->wm
.skl
.optimal
.planes
[plane_id
];
1627 if (DISPLAY_VER(i915
) < 11 &&
1628 crtc_state
->nv12_planes
& BIT(plane_id
))
1629 skl_check_nv12_wm_level(&wm
->wm
[level
],
1633 skl_check_wm_level(&wm
->wm
[level
], ddb
);
1635 if (skl_need_wm_copy_wa(i915
, level
, wm
)) {
1636 wm
->wm
[level
].blocks
= wm
->wm
[level
- 1].blocks
;
1637 wm
->wm
[level
].lines
= wm
->wm
[level
- 1].lines
;
1638 wm
->wm
[level
].ignore_lines
= wm
->wm
[level
- 1].ignore_lines
;
1644 * Go back and disable the transition and SAGV watermarks
1645 * if it turns out we don't have enough DDB blocks for them.
1647 for_each_plane_id_on_crtc(crtc
, plane_id
) {
1648 const struct skl_ddb_entry
*ddb
=
1649 &crtc_state
->wm
.skl
.plane_ddb
[plane_id
];
1650 const struct skl_ddb_entry
*ddb_y
=
1651 &crtc_state
->wm
.skl
.plane_ddb_y
[plane_id
];
1652 struct skl_plane_wm
*wm
=
1653 &crtc_state
->wm
.skl
.optimal
.planes
[plane_id
];
1655 if (DISPLAY_VER(i915
) < 11 &&
1656 crtc_state
->nv12_planes
& BIT(plane_id
)) {
1657 skl_check_wm_level(&wm
->trans_wm
, ddb_y
);
1659 WARN_ON(skl_ddb_entry_size(ddb_y
));
1661 skl_check_wm_level(&wm
->trans_wm
, ddb
);
1664 skl_check_wm_level(&wm
->sagv
.wm0
, ddb
);
1665 skl_check_wm_level(&wm
->sagv
.trans_wm
, ddb
);
1672 * The max latency should be 257 (max the punit can code is 255 and we add 2us
1673 * for the read latency) and cpp should always be <= 8, so that
1674 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
1675 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
1677 static uint_fixed_16_16_t
1678 skl_wm_method1(const struct drm_i915_private
*i915
, u32 pixel_rate
,
1679 u8 cpp
, u32 latency
, u32 dbuf_block_size
)
1681 u32 wm_intermediate_val
;
1682 uint_fixed_16_16_t ret
;
1685 return FP_16_16_MAX
;
1687 wm_intermediate_val
= latency
* pixel_rate
* cpp
;
1688 ret
= div_fixed16(wm_intermediate_val
, 1000 * dbuf_block_size
);
1690 if (DISPLAY_VER(i915
) >= 10)
1691 ret
= add_fixed16_u32(ret
, 1);
1696 static uint_fixed_16_16_t
1697 skl_wm_method2(u32 pixel_rate
, u32 pipe_htotal
, u32 latency
,
1698 uint_fixed_16_16_t plane_blocks_per_line
)
1700 u32 wm_intermediate_val
;
1701 uint_fixed_16_16_t ret
;
1704 return FP_16_16_MAX
;
1706 wm_intermediate_val
= latency
* pixel_rate
;
1707 wm_intermediate_val
= DIV_ROUND_UP(wm_intermediate_val
,
1708 pipe_htotal
* 1000);
1709 ret
= mul_u32_fixed16(wm_intermediate_val
, plane_blocks_per_line
);
1713 static uint_fixed_16_16_t
1714 intel_get_linetime_us(const struct intel_crtc_state
*crtc_state
)
1716 struct drm_i915_private
*i915
= to_i915(crtc_state
->uapi
.crtc
->dev
);
1719 uint_fixed_16_16_t linetime_us
;
1721 if (!crtc_state
->hw
.active
)
1722 return u32_to_fixed16(0);
1724 pixel_rate
= crtc_state
->pixel_rate
;
1726 if (drm_WARN_ON(&i915
->drm
, pixel_rate
== 0))
1727 return u32_to_fixed16(0);
1729 crtc_htotal
= crtc_state
->hw
.pipe_mode
.crtc_htotal
;
1730 linetime_us
= div_fixed16(crtc_htotal
* 1000, pixel_rate
);
1736 skl_compute_wm_params(const struct intel_crtc_state
*crtc_state
,
1737 int width
, const struct drm_format_info
*format
,
1738 u64 modifier
, unsigned int rotation
,
1739 u32 plane_pixel_rate
, struct skl_wm_params
*wp
,
1742 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
1743 struct drm_i915_private
*i915
= to_i915(crtc
->base
.dev
);
1746 /* only planar format has two planes */
1747 if (color_plane
== 1 &&
1748 !intel_format_info_is_yuv_semiplanar(format
, modifier
)) {
1749 drm_dbg_kms(&i915
->drm
,
1750 "Non planar format have single plane\n");
1754 wp
->x_tiled
= modifier
== I915_FORMAT_MOD_X_TILED
;
1755 wp
->y_tiled
= modifier
!= I915_FORMAT_MOD_X_TILED
&&
1756 intel_fb_is_tiled_modifier(modifier
);
1757 wp
->rc_surface
= intel_fb_is_ccs_modifier(modifier
);
1758 wp
->is_planar
= intel_format_info_is_yuv_semiplanar(format
, modifier
);
1761 if (color_plane
== 1 && wp
->is_planar
)
1764 wp
->cpp
= format
->cpp
[color_plane
];
1765 wp
->plane_pixel_rate
= plane_pixel_rate
;
1767 if (DISPLAY_VER(i915
) >= 11 &&
1768 modifier
== I915_FORMAT_MOD_Yf_TILED
&& wp
->cpp
== 1)
1769 wp
->dbuf_block_size
= 256;
1771 wp
->dbuf_block_size
= 512;
1773 if (drm_rotation_90_or_270(rotation
)) {
1776 wp
->y_min_scanlines
= 16;
1779 wp
->y_min_scanlines
= 8;
1782 wp
->y_min_scanlines
= 4;
1785 MISSING_CASE(wp
->cpp
);
1789 wp
->y_min_scanlines
= 4;
1792 if (skl_needs_memory_bw_wa(i915
))
1793 wp
->y_min_scanlines
*= 2;
1795 wp
->plane_bytes_per_line
= wp
->width
* wp
->cpp
;
1797 interm_pbpl
= DIV_ROUND_UP(wp
->plane_bytes_per_line
*
1798 wp
->y_min_scanlines
,
1799 wp
->dbuf_block_size
);
1801 if (DISPLAY_VER(i915
) >= 10)
1804 wp
->plane_blocks_per_line
= div_fixed16(interm_pbpl
,
1805 wp
->y_min_scanlines
);
1807 interm_pbpl
= DIV_ROUND_UP(wp
->plane_bytes_per_line
,
1808 wp
->dbuf_block_size
);
1810 if (!wp
->x_tiled
|| DISPLAY_VER(i915
) >= 10)
1813 wp
->plane_blocks_per_line
= u32_to_fixed16(interm_pbpl
);
1816 wp
->y_tile_minimum
= mul_u32_fixed16(wp
->y_min_scanlines
,
1817 wp
->plane_blocks_per_line
);
1819 wp
->linetime_us
= fixed16_to_u32_round_up(intel_get_linetime_us(crtc_state
));
1825 skl_compute_plane_wm_params(const struct intel_crtc_state
*crtc_state
,
1826 const struct intel_plane_state
*plane_state
,
1827 struct skl_wm_params
*wp
, int color_plane
)
1829 const struct drm_framebuffer
*fb
= plane_state
->hw
.fb
;
1833 * Src coordinates are already rotated by 270 degrees for
1834 * the 90/270 degree plane rotation cases (to match the
1835 * GTT mapping), hence no need to account for rotation here.
1837 width
= drm_rect_width(&plane_state
->uapi
.src
) >> 16;
1839 return skl_compute_wm_params(crtc_state
, width
,
1840 fb
->format
, fb
->modifier
,
1841 plane_state
->hw
.rotation
,
1842 intel_plane_pixel_rate(crtc_state
, plane_state
),
1846 static bool skl_wm_has_lines(struct drm_i915_private
*i915
, int level
)
1848 if (DISPLAY_VER(i915
) >= 10)
1851 /* The number of lines are ignored for the level 0 watermark. */
1855 static int skl_wm_max_lines(struct drm_i915_private
*i915
)
1857 if (DISPLAY_VER(i915
) >= 13)
1863 static void skl_compute_plane_wm(const struct intel_crtc_state
*crtc_state
,
1864 struct intel_plane
*plane
,
1866 unsigned int latency
,
1867 const struct skl_wm_params
*wp
,
1868 const struct skl_wm_level
*result_prev
,
1869 struct skl_wm_level
*result
/* out */)
1871 struct drm_i915_private
*i915
= to_i915(crtc_state
->uapi
.crtc
->dev
);
1872 uint_fixed_16_16_t method1
, method2
;
1873 uint_fixed_16_16_t selected_result
;
1874 u32 blocks
, lines
, min_ddb_alloc
= 0;
1877 (use_minimal_wm0_only(crtc_state
, plane
) && level
> 0)) {
1879 result
->min_ddb_alloc
= U16_MAX
;
1883 method1
= skl_wm_method1(i915
, wp
->plane_pixel_rate
,
1884 wp
->cpp
, latency
, wp
->dbuf_block_size
);
1885 method2
= skl_wm_method2(wp
->plane_pixel_rate
,
1886 crtc_state
->hw
.pipe_mode
.crtc_htotal
,
1888 wp
->plane_blocks_per_line
);
1891 selected_result
= max_fixed16(method2
, wp
->y_tile_minimum
);
1893 if ((wp
->cpp
* crtc_state
->hw
.pipe_mode
.crtc_htotal
/
1894 wp
->dbuf_block_size
< 1) &&
1895 (wp
->plane_bytes_per_line
/ wp
->dbuf_block_size
< 1)) {
1896 selected_result
= method2
;
1897 } else if (latency
>= wp
->linetime_us
) {
1898 if (DISPLAY_VER(i915
) == 9)
1899 selected_result
= min_fixed16(method1
, method2
);
1901 selected_result
= method2
;
1903 selected_result
= method1
;
1907 blocks
= fixed16_to_u32_round_up(selected_result
) + 1;
1909 * Lets have blocks at minimum equivalent to plane_blocks_per_line
1910 * as there will be at minimum one line for lines configuration. This
1911 * is a work around for FIFO underruns observed with resolutions like
1912 * 4k 60 Hz in single channel DRAM configurations.
1914 * As per the Bspec 49325, if the ddb allocation can hold at least
1915 * one plane_blocks_per_line, we should have selected method2 in
1916 * the above logic. Assuming that modern versions have enough dbuf
1917 * and method2 guarantees blocks equivalent to at least 1 line,
1918 * select the blocks as plane_blocks_per_line.
1920 * TODO: Revisit the logic when we have better understanding on DRAM
1921 * channels' impact on the level 0 memory latency and the relevant
1924 if (skl_wm_has_lines(i915
, level
))
1925 blocks
= max(blocks
,
1926 fixed16_to_u32_round_up(wp
->plane_blocks_per_line
));
1927 lines
= div_round_up_fixed16(selected_result
,
1928 wp
->plane_blocks_per_line
);
1930 if (DISPLAY_VER(i915
) == 9) {
1931 /* Display WA #1125: skl,bxt,kbl */
1932 if (level
== 0 && wp
->rc_surface
)
1933 blocks
+= fixed16_to_u32_round_up(wp
->y_tile_minimum
);
1935 /* Display WA #1126: skl,bxt,kbl */
1936 if (level
>= 1 && level
<= 7) {
1938 blocks
+= fixed16_to_u32_round_up(wp
->y_tile_minimum
);
1939 lines
+= wp
->y_min_scanlines
;
1945 * Make sure result blocks for higher latency levels are
1946 * at least as high as level below the current level.
1947 * Assumption in DDB algorithm optimization for special
1948 * cases. Also covers Display WA #1125 for RC.
1950 if (result_prev
->blocks
> blocks
)
1951 blocks
= result_prev
->blocks
;
1955 if (DISPLAY_VER(i915
) >= 11) {
1959 if (lines
% wp
->y_min_scanlines
== 0)
1960 extra_lines
= wp
->y_min_scanlines
;
1962 extra_lines
= wp
->y_min_scanlines
* 2 -
1963 lines
% wp
->y_min_scanlines
;
1965 min_ddb_alloc
= mul_round_up_u32_fixed16(lines
+ extra_lines
,
1966 wp
->plane_blocks_per_line
);
1968 min_ddb_alloc
= blocks
+ DIV_ROUND_UP(blocks
, 10);
1972 if (!skl_wm_has_lines(i915
, level
))
1975 if (lines
> skl_wm_max_lines(i915
)) {
1977 result
->min_ddb_alloc
= U16_MAX
;
1982 * If lines is valid, assume we can use this watermark level
1983 * for now. We'll come back and disable it after we calculate the
1984 * DDB allocation if it turns out we don't actually have enough
1985 * blocks to satisfy it.
1987 result
->blocks
= blocks
;
1988 result
->lines
= lines
;
1989 /* Bspec says: value >= plane ddb allocation -> invalid, hence the +1 here */
1990 result
->min_ddb_alloc
= max(min_ddb_alloc
, blocks
) + 1;
1991 result
->enable
= true;
1993 if (DISPLAY_VER(i915
) < 12 && i915
->display
.sagv
.block_time_us
)
1994 result
->can_sagv
= latency
>= i915
->display
.sagv
.block_time_us
;
1998 skl_compute_wm_levels(const struct intel_crtc_state
*crtc_state
,
1999 struct intel_plane
*plane
,
2000 const struct skl_wm_params
*wm_params
,
2001 struct skl_wm_level
*levels
)
2003 struct drm_i915_private
*i915
= to_i915(crtc_state
->uapi
.crtc
->dev
);
2004 struct skl_wm_level
*result_prev
= &levels
[0];
2007 for (level
= 0; level
< i915
->display
.wm
.num_levels
; level
++) {
2008 struct skl_wm_level
*result
= &levels
[level
];
2009 unsigned int latency
= skl_wm_latency(i915
, level
, wm_params
);
2011 skl_compute_plane_wm(crtc_state
, plane
, level
, latency
,
2012 wm_params
, result_prev
, result
);
2014 result_prev
= result
;
2018 static void tgl_compute_sagv_wm(const struct intel_crtc_state
*crtc_state
,
2019 struct intel_plane
*plane
,
2020 const struct skl_wm_params
*wm_params
,
2021 struct skl_plane_wm
*plane_wm
)
2023 struct drm_i915_private
*i915
= to_i915(crtc_state
->uapi
.crtc
->dev
);
2024 struct skl_wm_level
*sagv_wm
= &plane_wm
->sagv
.wm0
;
2025 struct skl_wm_level
*levels
= plane_wm
->wm
;
2026 unsigned int latency
= 0;
2028 if (i915
->display
.sagv
.block_time_us
)
2029 latency
= i915
->display
.sagv
.block_time_us
+
2030 skl_wm_latency(i915
, 0, wm_params
);
2032 skl_compute_plane_wm(crtc_state
, plane
, 0, latency
,
2033 wm_params
, &levels
[0],
2037 static void skl_compute_transition_wm(struct drm_i915_private
*i915
,
2038 struct skl_wm_level
*trans_wm
,
2039 const struct skl_wm_level
*wm0
,
2040 const struct skl_wm_params
*wp
)
2042 u16 trans_min
, trans_amount
, trans_y_tile_min
;
2043 u16 wm0_blocks
, trans_offset
, blocks
;
2045 /* Transition WM don't make any sense if ipc is disabled */
2046 if (!skl_watermark_ipc_enabled(i915
))
2050 * WaDisableTWM:skl,kbl,cfl,bxt
2051 * Transition WM are not recommended by HW team for GEN9
2053 if (DISPLAY_VER(i915
) == 9)
2056 if (DISPLAY_VER(i915
) >= 11)
2061 /* Display WA #1140: glk,cnl */
2062 if (DISPLAY_VER(i915
) == 10)
2065 trans_amount
= 10; /* This is configurable amount */
2067 trans_offset
= trans_min
+ trans_amount
;
2070 * The spec asks for Selected Result Blocks for wm0 (the real value),
2071 * not Result Blocks (the integer value). Pay attention to the capital
2072 * letters. The value wm_l0->blocks is actually Result Blocks, but
2073 * since Result Blocks is the ceiling of Selected Result Blocks plus 1,
2074 * and since we later will have to get the ceiling of the sum in the
2075 * transition watermarks calculation, we can just pretend Selected
2076 * Result Blocks is Result Blocks minus 1 and it should work for the
2077 * current platforms.
2079 wm0_blocks
= wm0
->blocks
- 1;
2083 (u16
)mul_round_up_u32_fixed16(2, wp
->y_tile_minimum
);
2084 blocks
= max(wm0_blocks
, trans_y_tile_min
) + trans_offset
;
2086 blocks
= wm0_blocks
+ trans_offset
;
2091 * Just assume we can enable the transition watermark. After
2092 * computing the DDB we'll come back and disable it if that
2093 * assumption turns out to be false.
2095 trans_wm
->blocks
= blocks
;
2096 trans_wm
->min_ddb_alloc
= max_t(u16
, wm0
->min_ddb_alloc
, blocks
+ 1);
2097 trans_wm
->enable
= true;
2100 static int skl_build_plane_wm_single(struct intel_crtc_state
*crtc_state
,
2101 const struct intel_plane_state
*plane_state
,
2102 struct intel_plane
*plane
, int color_plane
)
2104 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
2105 struct drm_i915_private
*i915
= to_i915(crtc
->base
.dev
);
2106 struct skl_plane_wm
*wm
= &crtc_state
->wm
.skl
.raw
.planes
[plane
->id
];
2107 struct skl_wm_params wm_params
;
2110 ret
= skl_compute_plane_wm_params(crtc_state
, plane_state
,
2111 &wm_params
, color_plane
);
2115 skl_compute_wm_levels(crtc_state
, plane
, &wm_params
, wm
->wm
);
2117 skl_compute_transition_wm(i915
, &wm
->trans_wm
,
2118 &wm
->wm
[0], &wm_params
);
2120 if (DISPLAY_VER(i915
) >= 12) {
2121 tgl_compute_sagv_wm(crtc_state
, plane
, &wm_params
, wm
);
2123 skl_compute_transition_wm(i915
, &wm
->sagv
.trans_wm
,
2124 &wm
->sagv
.wm0
, &wm_params
);
2130 static int skl_build_plane_wm_uv(struct intel_crtc_state
*crtc_state
,
2131 const struct intel_plane_state
*plane_state
,
2132 struct intel_plane
*plane
)
2134 struct skl_plane_wm
*wm
= &crtc_state
->wm
.skl
.raw
.planes
[plane
->id
];
2135 struct skl_wm_params wm_params
;
2138 wm
->is_planar
= true;
2140 /* uv plane watermarks must also be validated for NV12/Planar */
2141 ret
= skl_compute_plane_wm_params(crtc_state
, plane_state
,
2146 skl_compute_wm_levels(crtc_state
, plane
, &wm_params
, wm
->uv_wm
);
2151 static int skl_build_plane_wm(struct intel_crtc_state
*crtc_state
,
2152 const struct intel_plane_state
*plane_state
)
2154 struct intel_plane
*plane
= to_intel_plane(plane_state
->uapi
.plane
);
2155 enum plane_id plane_id
= plane
->id
;
2156 struct skl_plane_wm
*wm
= &crtc_state
->wm
.skl
.raw
.planes
[plane_id
];
2157 const struct drm_framebuffer
*fb
= plane_state
->hw
.fb
;
2160 memset(wm
, 0, sizeof(*wm
));
2162 if (!intel_wm_plane_visible(crtc_state
, plane_state
))
2165 ret
= skl_build_plane_wm_single(crtc_state
, plane_state
,
2170 if (fb
->format
->is_yuv
&& fb
->format
->num_planes
> 1) {
2171 ret
= skl_build_plane_wm_uv(crtc_state
, plane_state
,
2180 static int icl_build_plane_wm(struct intel_crtc_state
*crtc_state
,
2181 const struct intel_plane_state
*plane_state
)
2183 struct intel_plane
*plane
= to_intel_plane(plane_state
->uapi
.plane
);
2184 struct drm_i915_private
*i915
= to_i915(plane
->base
.dev
);
2185 enum plane_id plane_id
= plane
->id
;
2186 struct skl_plane_wm
*wm
= &crtc_state
->wm
.skl
.raw
.planes
[plane_id
];
2189 /* Watermarks calculated in master */
2190 if (plane_state
->planar_slave
)
2193 memset(wm
, 0, sizeof(*wm
));
2195 if (plane_state
->planar_linked_plane
) {
2196 const struct drm_framebuffer
*fb
= plane_state
->hw
.fb
;
2198 drm_WARN_ON(&i915
->drm
,
2199 !intel_wm_plane_visible(crtc_state
, plane_state
));
2200 drm_WARN_ON(&i915
->drm
, !fb
->format
->is_yuv
||
2201 fb
->format
->num_planes
== 1);
2203 ret
= skl_build_plane_wm_single(crtc_state
, plane_state
,
2204 plane_state
->planar_linked_plane
, 0);
2208 ret
= skl_build_plane_wm_single(crtc_state
, plane_state
,
2212 } else if (intel_wm_plane_visible(crtc_state
, plane_state
)) {
2213 ret
= skl_build_plane_wm_single(crtc_state
, plane_state
,
2223 skl_is_vblank_too_short(const struct intel_crtc_state
*crtc_state
,
2224 int wm0_lines
, int latency
)
2226 const struct drm_display_mode
*adjusted_mode
=
2227 &crtc_state
->hw
.adjusted_mode
;
2229 /* FIXME missing scaler and DSC pre-fill time */
2230 return crtc_state
->framestart_delay
+
2231 intel_usecs_to_scanlines(adjusted_mode
, latency
) +
2233 adjusted_mode
->crtc_vtotal
- adjusted_mode
->crtc_vblank_start
;
2236 static int skl_max_wm0_lines(const struct intel_crtc_state
*crtc_state
)
2238 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
2239 enum plane_id plane_id
;
2242 for_each_plane_id_on_crtc(crtc
, plane_id
) {
2243 const struct skl_plane_wm
*wm
= &crtc_state
->wm
.skl
.optimal
.planes
[plane_id
];
2245 /* FIXME what about !skl_wm_has_lines() platforms? */
2246 wm0_lines
= max_t(int, wm0_lines
, wm
->wm
[0].lines
);
2252 static int skl_max_wm_level_for_vblank(struct intel_crtc_state
*crtc_state
,
2255 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
2256 struct drm_i915_private
*i915
= to_i915(crtc
->base
.dev
);
2259 for (level
= i915
->display
.wm
.num_levels
- 1; level
>= 0; level
--) {
2262 /* FIXME should we care about the latency w/a's? */
2263 latency
= skl_wm_latency(i915
, level
, NULL
);
2267 /* FIXME is it correct to use 0 latency for wm0 here? */
2271 if (!skl_is_vblank_too_short(crtc_state
, wm0_lines
, latency
))
2278 static int skl_wm_check_vblank(struct intel_crtc_state
*crtc_state
)
2280 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
2281 struct drm_i915_private
*i915
= to_i915(crtc
->base
.dev
);
2282 int wm0_lines
, level
;
2284 if (!crtc_state
->hw
.active
)
2287 wm0_lines
= skl_max_wm0_lines(crtc_state
);
2289 level
= skl_max_wm_level_for_vblank(crtc_state
, wm0_lines
);
2294 * PSR needs to toggle LATENCY_REPORTING_REMOVED_PIPE_*
2295 * based on whether we're limited by the vblank duration.
2297 crtc_state
->wm_level_disabled
= level
< i915
->display
.wm
.num_levels
- 1;
2299 for (level
++; level
< i915
->display
.wm
.num_levels
; level
++) {
2300 enum plane_id plane_id
;
2302 for_each_plane_id_on_crtc(crtc
, plane_id
) {
2303 struct skl_plane_wm
*wm
=
2304 &crtc_state
->wm
.skl
.optimal
.planes
[plane_id
];
2307 * FIXME just clear enable or flag the entire
2308 * thing as bad via min_ddb_alloc=U16_MAX?
2310 wm
->wm
[level
].enable
= false;
2311 wm
->uv_wm
[level
].enable
= false;
2315 if (DISPLAY_VER(i915
) >= 12 &&
2316 i915
->display
.sagv
.block_time_us
&&
2317 skl_is_vblank_too_short(crtc_state
, wm0_lines
,
2318 i915
->display
.sagv
.block_time_us
)) {
2319 enum plane_id plane_id
;
2321 for_each_plane_id_on_crtc(crtc
, plane_id
) {
2322 struct skl_plane_wm
*wm
=
2323 &crtc_state
->wm
.skl
.optimal
.planes
[plane_id
];
2325 wm
->sagv
.wm0
.enable
= false;
2326 wm
->sagv
.trans_wm
.enable
= false;
2333 static int skl_build_pipe_wm(struct intel_atomic_state
*state
,
2334 struct intel_crtc
*crtc
)
2336 struct drm_i915_private
*i915
= to_i915(crtc
->base
.dev
);
2337 struct intel_crtc_state
*crtc_state
=
2338 intel_atomic_get_new_crtc_state(state
, crtc
);
2339 const struct intel_plane_state
*plane_state
;
2340 struct intel_plane
*plane
;
2343 for_each_new_intel_plane_in_state(state
, plane
, plane_state
, i
) {
2345 * FIXME should perhaps check {old,new}_plane_crtc->hw.crtc
2346 * instead but we don't populate that correctly for NV12 Y
2347 * planes so for now hack this.
2349 if (plane
->pipe
!= crtc
->pipe
)
2352 if (DISPLAY_VER(i915
) >= 11)
2353 ret
= icl_build_plane_wm(crtc_state
, plane_state
);
2355 ret
= skl_build_plane_wm(crtc_state
, plane_state
);
2360 crtc_state
->wm
.skl
.optimal
= crtc_state
->wm
.skl
.raw
;
2362 return skl_wm_check_vblank(crtc_state
);
2365 static void skl_ddb_entry_write(struct drm_i915_private
*i915
,
2367 const struct skl_ddb_entry
*entry
)
2370 intel_de_write_fw(i915
, reg
,
2371 PLANE_BUF_END(entry
->end
- 1) |
2372 PLANE_BUF_START(entry
->start
));
2374 intel_de_write_fw(i915
, reg
, 0);
2377 static void skl_write_wm_level(struct drm_i915_private
*i915
,
2379 const struct skl_wm_level
*level
)
2385 if (level
->ignore_lines
)
2386 val
|= PLANE_WM_IGNORE_LINES
;
2387 val
|= REG_FIELD_PREP(PLANE_WM_BLOCKS_MASK
, level
->blocks
);
2388 val
|= REG_FIELD_PREP(PLANE_WM_LINES_MASK
, level
->lines
);
2390 intel_de_write_fw(i915
, reg
, val
);
2393 void skl_write_plane_wm(struct intel_plane
*plane
,
2394 const struct intel_crtc_state
*crtc_state
)
2396 struct drm_i915_private
*i915
= to_i915(plane
->base
.dev
);
2397 enum plane_id plane_id
= plane
->id
;
2398 enum pipe pipe
= plane
->pipe
;
2399 const struct skl_pipe_wm
*pipe_wm
= &crtc_state
->wm
.skl
.optimal
;
2400 const struct skl_ddb_entry
*ddb
=
2401 &crtc_state
->wm
.skl
.plane_ddb
[plane_id
];
2402 const struct skl_ddb_entry
*ddb_y
=
2403 &crtc_state
->wm
.skl
.plane_ddb_y
[plane_id
];
2406 for (level
= 0; level
< i915
->display
.wm
.num_levels
; level
++)
2407 skl_write_wm_level(i915
, PLANE_WM(pipe
, plane_id
, level
),
2408 skl_plane_wm_level(pipe_wm
, plane_id
, level
));
2410 skl_write_wm_level(i915
, PLANE_WM_TRANS(pipe
, plane_id
),
2411 skl_plane_trans_wm(pipe_wm
, plane_id
));
2413 if (HAS_HW_SAGV_WM(i915
)) {
2414 const struct skl_plane_wm
*wm
= &pipe_wm
->planes
[plane_id
];
2416 skl_write_wm_level(i915
, PLANE_WM_SAGV(pipe
, plane_id
),
2418 skl_write_wm_level(i915
, PLANE_WM_SAGV_TRANS(pipe
, plane_id
),
2419 &wm
->sagv
.trans_wm
);
2422 skl_ddb_entry_write(i915
,
2423 PLANE_BUF_CFG(pipe
, plane_id
), ddb
);
2425 if (DISPLAY_VER(i915
) < 11)
2426 skl_ddb_entry_write(i915
,
2427 PLANE_NV12_BUF_CFG(pipe
, plane_id
), ddb_y
);
2430 void skl_write_cursor_wm(struct intel_plane
*plane
,
2431 const struct intel_crtc_state
*crtc_state
)
2433 struct drm_i915_private
*i915
= to_i915(plane
->base
.dev
);
2434 enum plane_id plane_id
= plane
->id
;
2435 enum pipe pipe
= plane
->pipe
;
2436 const struct skl_pipe_wm
*pipe_wm
= &crtc_state
->wm
.skl
.optimal
;
2437 const struct skl_ddb_entry
*ddb
=
2438 &crtc_state
->wm
.skl
.plane_ddb
[plane_id
];
2441 for (level
= 0; level
< i915
->display
.wm
.num_levels
; level
++)
2442 skl_write_wm_level(i915
, CUR_WM(pipe
, level
),
2443 skl_plane_wm_level(pipe_wm
, plane_id
, level
));
2445 skl_write_wm_level(i915
, CUR_WM_TRANS(pipe
),
2446 skl_plane_trans_wm(pipe_wm
, plane_id
));
2448 if (HAS_HW_SAGV_WM(i915
)) {
2449 const struct skl_plane_wm
*wm
= &pipe_wm
->planes
[plane_id
];
2451 skl_write_wm_level(i915
, CUR_WM_SAGV(pipe
),
2453 skl_write_wm_level(i915
, CUR_WM_SAGV_TRANS(pipe
),
2454 &wm
->sagv
.trans_wm
);
2457 skl_ddb_entry_write(i915
, CUR_BUF_CFG(pipe
), ddb
);
2460 static bool skl_wm_level_equals(const struct skl_wm_level
*l1
,
2461 const struct skl_wm_level
*l2
)
2463 return l1
->enable
== l2
->enable
&&
2464 l1
->ignore_lines
== l2
->ignore_lines
&&
2465 l1
->lines
== l2
->lines
&&
2466 l1
->blocks
== l2
->blocks
;
2469 static bool skl_plane_wm_equals(struct drm_i915_private
*i915
,
2470 const struct skl_plane_wm
*wm1
,
2471 const struct skl_plane_wm
*wm2
)
2475 for (level
= 0; level
< i915
->display
.wm
.num_levels
; level
++) {
2477 * We don't check uv_wm as the hardware doesn't actually
2478 * use it. It only gets used for calculating the required
2481 if (!skl_wm_level_equals(&wm1
->wm
[level
], &wm2
->wm
[level
]))
2485 return skl_wm_level_equals(&wm1
->trans_wm
, &wm2
->trans_wm
) &&
2486 skl_wm_level_equals(&wm1
->sagv
.wm0
, &wm2
->sagv
.wm0
) &&
2487 skl_wm_level_equals(&wm1
->sagv
.trans_wm
, &wm2
->sagv
.trans_wm
);
2490 static bool skl_ddb_entries_overlap(const struct skl_ddb_entry
*a
,
2491 const struct skl_ddb_entry
*b
)
2493 return a
->start
< b
->end
&& b
->start
< a
->end
;
2496 static void skl_ddb_entry_union(struct skl_ddb_entry
*a
,
2497 const struct skl_ddb_entry
*b
)
2499 if (a
->end
&& b
->end
) {
2500 a
->start
= min(a
->start
, b
->start
);
2501 a
->end
= max(a
->end
, b
->end
);
2502 } else if (b
->end
) {
2503 a
->start
= b
->start
;
2508 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry
*ddb
,
2509 const struct skl_ddb_entry
*entries
,
2510 int num_entries
, int ignore_idx
)
2514 for (i
= 0; i
< num_entries
; i
++) {
2515 if (i
!= ignore_idx
&&
2516 skl_ddb_entries_overlap(ddb
, &entries
[i
]))
2524 skl_ddb_add_affected_planes(const struct intel_crtc_state
*old_crtc_state
,
2525 struct intel_crtc_state
*new_crtc_state
)
2527 struct intel_atomic_state
*state
= to_intel_atomic_state(new_crtc_state
->uapi
.state
);
2528 struct intel_crtc
*crtc
= to_intel_crtc(new_crtc_state
->uapi
.crtc
);
2529 struct drm_i915_private
*i915
= to_i915(crtc
->base
.dev
);
2530 struct intel_plane
*plane
;
2532 for_each_intel_plane_on_crtc(&i915
->drm
, crtc
, plane
) {
2533 struct intel_plane_state
*plane_state
;
2534 enum plane_id plane_id
= plane
->id
;
2536 if (skl_ddb_entry_equal(&old_crtc_state
->wm
.skl
.plane_ddb
[plane_id
],
2537 &new_crtc_state
->wm
.skl
.plane_ddb
[plane_id
]) &&
2538 skl_ddb_entry_equal(&old_crtc_state
->wm
.skl
.plane_ddb_y
[plane_id
],
2539 &new_crtc_state
->wm
.skl
.plane_ddb_y
[plane_id
]))
2542 plane_state
= intel_atomic_get_plane_state(state
, plane
);
2543 if (IS_ERR(plane_state
))
2544 return PTR_ERR(plane_state
);
2546 new_crtc_state
->update_planes
|= BIT(plane_id
);
2547 new_crtc_state
->async_flip_planes
= 0;
2548 new_crtc_state
->do_async_flip
= false;
2554 static u8
intel_dbuf_enabled_slices(const struct intel_dbuf_state
*dbuf_state
)
2556 struct drm_i915_private
*i915
= to_i915(dbuf_state
->base
.state
->base
.dev
);
2561 * FIXME: For now we always enable slice S1 as per
2562 * the Bspec display initialization sequence.
2564 enabled_slices
= BIT(DBUF_S1
);
2566 for_each_pipe(i915
, pipe
)
2567 enabled_slices
|= dbuf_state
->slices
[pipe
];
2569 return enabled_slices
;
2573 skl_compute_ddb(struct intel_atomic_state
*state
)
2575 struct drm_i915_private
*i915
= to_i915(state
->base
.dev
);
2576 const struct intel_dbuf_state
*old_dbuf_state
;
2577 struct intel_dbuf_state
*new_dbuf_state
= NULL
;
2578 const struct intel_crtc_state
*old_crtc_state
;
2579 struct intel_crtc_state
*new_crtc_state
;
2580 struct intel_crtc
*crtc
;
2583 for_each_new_intel_crtc_in_state(state
, crtc
, new_crtc_state
, i
) {
2584 new_dbuf_state
= intel_atomic_get_dbuf_state(state
);
2585 if (IS_ERR(new_dbuf_state
))
2586 return PTR_ERR(new_dbuf_state
);
2588 old_dbuf_state
= intel_atomic_get_old_dbuf_state(state
);
2592 if (!new_dbuf_state
)
2595 new_dbuf_state
->active_pipes
=
2596 intel_calc_active_pipes(state
, old_dbuf_state
->active_pipes
);
2598 if (old_dbuf_state
->active_pipes
!= new_dbuf_state
->active_pipes
) {
2599 ret
= intel_atomic_lock_global_state(&new_dbuf_state
->base
);
2604 if (HAS_MBUS_JOINING(i915
))
2605 new_dbuf_state
->joined_mbus
=
2606 adlp_check_mbus_joined(new_dbuf_state
->active_pipes
);
2608 for_each_intel_crtc(&i915
->drm
, crtc
) {
2609 enum pipe pipe
= crtc
->pipe
;
2611 new_dbuf_state
->slices
[pipe
] =
2612 skl_compute_dbuf_slices(crtc
, new_dbuf_state
->active_pipes
,
2613 new_dbuf_state
->joined_mbus
);
2615 if (old_dbuf_state
->slices
[pipe
] == new_dbuf_state
->slices
[pipe
])
2618 ret
= intel_atomic_lock_global_state(&new_dbuf_state
->base
);
2623 new_dbuf_state
->enabled_slices
= intel_dbuf_enabled_slices(new_dbuf_state
);
2625 if (old_dbuf_state
->enabled_slices
!= new_dbuf_state
->enabled_slices
||
2626 old_dbuf_state
->joined_mbus
!= new_dbuf_state
->joined_mbus
) {
2627 ret
= intel_atomic_serialize_global_state(&new_dbuf_state
->base
);
2631 if (old_dbuf_state
->joined_mbus
!= new_dbuf_state
->joined_mbus
) {
2632 /* TODO: Implement vblank synchronized MBUS joining changes */
2633 ret
= intel_modeset_all_pipes_late(state
, "MBUS joining change");
2638 drm_dbg_kms(&i915
->drm
,
2639 "Enabled dbuf slices 0x%x -> 0x%x (total dbuf slices 0x%x), mbus joined? %s->%s\n",
2640 old_dbuf_state
->enabled_slices
,
2641 new_dbuf_state
->enabled_slices
,
2642 DISPLAY_INFO(i915
)->dbuf
.slice_mask
,
2643 str_yes_no(old_dbuf_state
->joined_mbus
),
2644 str_yes_no(new_dbuf_state
->joined_mbus
));
2647 for_each_new_intel_crtc_in_state(state
, crtc
, new_crtc_state
, i
) {
2648 enum pipe pipe
= crtc
->pipe
;
2650 new_dbuf_state
->weight
[pipe
] = intel_crtc_ddb_weight(new_crtc_state
);
2652 if (old_dbuf_state
->weight
[pipe
] == new_dbuf_state
->weight
[pipe
])
2655 ret
= intel_atomic_lock_global_state(&new_dbuf_state
->base
);
2660 for_each_intel_crtc(&i915
->drm
, crtc
) {
2661 ret
= skl_crtc_allocate_ddb(state
, crtc
);
2666 for_each_oldnew_intel_crtc_in_state(state
, crtc
, old_crtc_state
,
2667 new_crtc_state
, i
) {
2668 ret
= skl_crtc_allocate_plane_ddb(state
, crtc
);
2672 ret
= skl_ddb_add_affected_planes(old_crtc_state
,
2681 static char enast(bool enable
)
2683 return enable
? '*' : ' ';
2687 skl_print_wm_changes(struct intel_atomic_state
*state
)
2689 struct drm_i915_private
*i915
= to_i915(state
->base
.dev
);
2690 const struct intel_crtc_state
*old_crtc_state
;
2691 const struct intel_crtc_state
*new_crtc_state
;
2692 struct intel_plane
*plane
;
2693 struct intel_crtc
*crtc
;
2696 if (!drm_debug_enabled(DRM_UT_KMS
))
2699 for_each_oldnew_intel_crtc_in_state(state
, crtc
, old_crtc_state
,
2700 new_crtc_state
, i
) {
2701 const struct skl_pipe_wm
*old_pipe_wm
, *new_pipe_wm
;
2703 old_pipe_wm
= &old_crtc_state
->wm
.skl
.optimal
;
2704 new_pipe_wm
= &new_crtc_state
->wm
.skl
.optimal
;
2706 for_each_intel_plane_on_crtc(&i915
->drm
, crtc
, plane
) {
2707 enum plane_id plane_id
= plane
->id
;
2708 const struct skl_ddb_entry
*old
, *new;
2710 old
= &old_crtc_state
->wm
.skl
.plane_ddb
[plane_id
];
2711 new = &new_crtc_state
->wm
.skl
.plane_ddb
[plane_id
];
2713 if (skl_ddb_entry_equal(old
, new))
2716 drm_dbg_kms(&i915
->drm
,
2717 "[PLANE:%d:%s] ddb (%4d - %4d) -> (%4d - %4d), size %4d -> %4d\n",
2718 plane
->base
.base
.id
, plane
->base
.name
,
2719 old
->start
, old
->end
, new->start
, new->end
,
2720 skl_ddb_entry_size(old
), skl_ddb_entry_size(new));
2723 for_each_intel_plane_on_crtc(&i915
->drm
, crtc
, plane
) {
2724 enum plane_id plane_id
= plane
->id
;
2725 const struct skl_plane_wm
*old_wm
, *new_wm
;
2727 old_wm
= &old_pipe_wm
->planes
[plane_id
];
2728 new_wm
= &new_pipe_wm
->planes
[plane_id
];
2730 if (skl_plane_wm_equals(i915
, old_wm
, new_wm
))
2733 drm_dbg_kms(&i915
->drm
,
2734 "[PLANE:%d:%s] level %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm,%cswm,%cstwm"
2735 " -> %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm,%cswm,%cstwm\n",
2736 plane
->base
.base
.id
, plane
->base
.name
,
2737 enast(old_wm
->wm
[0].enable
), enast(old_wm
->wm
[1].enable
),
2738 enast(old_wm
->wm
[2].enable
), enast(old_wm
->wm
[3].enable
),
2739 enast(old_wm
->wm
[4].enable
), enast(old_wm
->wm
[5].enable
),
2740 enast(old_wm
->wm
[6].enable
), enast(old_wm
->wm
[7].enable
),
2741 enast(old_wm
->trans_wm
.enable
),
2742 enast(old_wm
->sagv
.wm0
.enable
),
2743 enast(old_wm
->sagv
.trans_wm
.enable
),
2744 enast(new_wm
->wm
[0].enable
), enast(new_wm
->wm
[1].enable
),
2745 enast(new_wm
->wm
[2].enable
), enast(new_wm
->wm
[3].enable
),
2746 enast(new_wm
->wm
[4].enable
), enast(new_wm
->wm
[5].enable
),
2747 enast(new_wm
->wm
[6].enable
), enast(new_wm
->wm
[7].enable
),
2748 enast(new_wm
->trans_wm
.enable
),
2749 enast(new_wm
->sagv
.wm0
.enable
),
2750 enast(new_wm
->sagv
.trans_wm
.enable
));
2752 drm_dbg_kms(&i915
->drm
,
2753 "[PLANE:%d:%s] lines %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%4d"
2754 " -> %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%4d\n",
2755 plane
->base
.base
.id
, plane
->base
.name
,
2756 enast(old_wm
->wm
[0].ignore_lines
), old_wm
->wm
[0].lines
,
2757 enast(old_wm
->wm
[1].ignore_lines
), old_wm
->wm
[1].lines
,
2758 enast(old_wm
->wm
[2].ignore_lines
), old_wm
->wm
[2].lines
,
2759 enast(old_wm
->wm
[3].ignore_lines
), old_wm
->wm
[3].lines
,
2760 enast(old_wm
->wm
[4].ignore_lines
), old_wm
->wm
[4].lines
,
2761 enast(old_wm
->wm
[5].ignore_lines
), old_wm
->wm
[5].lines
,
2762 enast(old_wm
->wm
[6].ignore_lines
), old_wm
->wm
[6].lines
,
2763 enast(old_wm
->wm
[7].ignore_lines
), old_wm
->wm
[7].lines
,
2764 enast(old_wm
->trans_wm
.ignore_lines
), old_wm
->trans_wm
.lines
,
2765 enast(old_wm
->sagv
.wm0
.ignore_lines
), old_wm
->sagv
.wm0
.lines
,
2766 enast(old_wm
->sagv
.trans_wm
.ignore_lines
), old_wm
->sagv
.trans_wm
.lines
,
2767 enast(new_wm
->wm
[0].ignore_lines
), new_wm
->wm
[0].lines
,
2768 enast(new_wm
->wm
[1].ignore_lines
), new_wm
->wm
[1].lines
,
2769 enast(new_wm
->wm
[2].ignore_lines
), new_wm
->wm
[2].lines
,
2770 enast(new_wm
->wm
[3].ignore_lines
), new_wm
->wm
[3].lines
,
2771 enast(new_wm
->wm
[4].ignore_lines
), new_wm
->wm
[4].lines
,
2772 enast(new_wm
->wm
[5].ignore_lines
), new_wm
->wm
[5].lines
,
2773 enast(new_wm
->wm
[6].ignore_lines
), new_wm
->wm
[6].lines
,
2774 enast(new_wm
->wm
[7].ignore_lines
), new_wm
->wm
[7].lines
,
2775 enast(new_wm
->trans_wm
.ignore_lines
), new_wm
->trans_wm
.lines
,
2776 enast(new_wm
->sagv
.wm0
.ignore_lines
), new_wm
->sagv
.wm0
.lines
,
2777 enast(new_wm
->sagv
.trans_wm
.ignore_lines
), new_wm
->sagv
.trans_wm
.lines
);
2779 drm_dbg_kms(&i915
->drm
,
2780 "[PLANE:%d:%s] blocks %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d"
2781 " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d\n",
2782 plane
->base
.base
.id
, plane
->base
.name
,
2783 old_wm
->wm
[0].blocks
, old_wm
->wm
[1].blocks
,
2784 old_wm
->wm
[2].blocks
, old_wm
->wm
[3].blocks
,
2785 old_wm
->wm
[4].blocks
, old_wm
->wm
[5].blocks
,
2786 old_wm
->wm
[6].blocks
, old_wm
->wm
[7].blocks
,
2787 old_wm
->trans_wm
.blocks
,
2788 old_wm
->sagv
.wm0
.blocks
,
2789 old_wm
->sagv
.trans_wm
.blocks
,
2790 new_wm
->wm
[0].blocks
, new_wm
->wm
[1].blocks
,
2791 new_wm
->wm
[2].blocks
, new_wm
->wm
[3].blocks
,
2792 new_wm
->wm
[4].blocks
, new_wm
->wm
[5].blocks
,
2793 new_wm
->wm
[6].blocks
, new_wm
->wm
[7].blocks
,
2794 new_wm
->trans_wm
.blocks
,
2795 new_wm
->sagv
.wm0
.blocks
,
2796 new_wm
->sagv
.trans_wm
.blocks
);
2798 drm_dbg_kms(&i915
->drm
,
2799 "[PLANE:%d:%s] min_ddb %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d"
2800 " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d\n",
2801 plane
->base
.base
.id
, plane
->base
.name
,
2802 old_wm
->wm
[0].min_ddb_alloc
, old_wm
->wm
[1].min_ddb_alloc
,
2803 old_wm
->wm
[2].min_ddb_alloc
, old_wm
->wm
[3].min_ddb_alloc
,
2804 old_wm
->wm
[4].min_ddb_alloc
, old_wm
->wm
[5].min_ddb_alloc
,
2805 old_wm
->wm
[6].min_ddb_alloc
, old_wm
->wm
[7].min_ddb_alloc
,
2806 old_wm
->trans_wm
.min_ddb_alloc
,
2807 old_wm
->sagv
.wm0
.min_ddb_alloc
,
2808 old_wm
->sagv
.trans_wm
.min_ddb_alloc
,
2809 new_wm
->wm
[0].min_ddb_alloc
, new_wm
->wm
[1].min_ddb_alloc
,
2810 new_wm
->wm
[2].min_ddb_alloc
, new_wm
->wm
[3].min_ddb_alloc
,
2811 new_wm
->wm
[4].min_ddb_alloc
, new_wm
->wm
[5].min_ddb_alloc
,
2812 new_wm
->wm
[6].min_ddb_alloc
, new_wm
->wm
[7].min_ddb_alloc
,
2813 new_wm
->trans_wm
.min_ddb_alloc
,
2814 new_wm
->sagv
.wm0
.min_ddb_alloc
,
2815 new_wm
->sagv
.trans_wm
.min_ddb_alloc
);
2820 static bool skl_plane_selected_wm_equals(struct intel_plane
*plane
,
2821 const struct skl_pipe_wm
*old_pipe_wm
,
2822 const struct skl_pipe_wm
*new_pipe_wm
)
2824 struct drm_i915_private
*i915
= to_i915(plane
->base
.dev
);
2827 for (level
= 0; level
< i915
->display
.wm
.num_levels
; level
++) {
2829 * We don't check uv_wm as the hardware doesn't actually
2830 * use it. It only gets used for calculating the required
2833 if (!skl_wm_level_equals(skl_plane_wm_level(old_pipe_wm
, plane
->id
, level
),
2834 skl_plane_wm_level(new_pipe_wm
, plane
->id
, level
)))
2838 if (HAS_HW_SAGV_WM(i915
)) {
2839 const struct skl_plane_wm
*old_wm
= &old_pipe_wm
->planes
[plane
->id
];
2840 const struct skl_plane_wm
*new_wm
= &new_pipe_wm
->planes
[plane
->id
];
2842 if (!skl_wm_level_equals(&old_wm
->sagv
.wm0
, &new_wm
->sagv
.wm0
) ||
2843 !skl_wm_level_equals(&old_wm
->sagv
.trans_wm
, &new_wm
->sagv
.trans_wm
))
2847 return skl_wm_level_equals(skl_plane_trans_wm(old_pipe_wm
, plane
->id
),
2848 skl_plane_trans_wm(new_pipe_wm
, plane
->id
));
2852 * To make sure the cursor watermark registers are always consistent
2853 * with our computed state the following scenario needs special
2857 * 2. move cursor entirely offscreen
2860 * Step 2. does call .disable_plane() but does not zero the watermarks
2861 * (since we consider an offscreen cursor still active for the purposes
2862 * of watermarks). Step 3. would not normally call .disable_plane()
2863 * because the actual plane visibility isn't changing, and we don't
2864 * deallocate the cursor ddb until the pipe gets disabled. So we must
2865 * force step 3. to call .disable_plane() to update the watermark
2866 * registers properly.
2868 * Other planes do not suffer from this issues as their watermarks are
2869 * calculated based on the actual plane visibility. The only time this
2870 * can trigger for the other planes is during the initial readout as the
2871 * default value of the watermarks registers is not zero.
2873 static int skl_wm_add_affected_planes(struct intel_atomic_state
*state
,
2874 struct intel_crtc
*crtc
)
2876 struct drm_i915_private
*i915
= to_i915(crtc
->base
.dev
);
2877 const struct intel_crtc_state
*old_crtc_state
=
2878 intel_atomic_get_old_crtc_state(state
, crtc
);
2879 struct intel_crtc_state
*new_crtc_state
=
2880 intel_atomic_get_new_crtc_state(state
, crtc
);
2881 struct intel_plane
*plane
;
2883 for_each_intel_plane_on_crtc(&i915
->drm
, crtc
, plane
) {
2884 struct intel_plane_state
*plane_state
;
2885 enum plane_id plane_id
= plane
->id
;
2888 * Force a full wm update for every plane on modeset.
2889 * Required because the reset value of the wm registers
2890 * is non-zero, whereas we want all disabled planes to
2891 * have zero watermarks. So if we turn off the relevant
2892 * power well the hardware state will go out of sync
2893 * with the software state.
2895 if (!intel_crtc_needs_modeset(new_crtc_state
) &&
2896 skl_plane_selected_wm_equals(plane
,
2897 &old_crtc_state
->wm
.skl
.optimal
,
2898 &new_crtc_state
->wm
.skl
.optimal
))
2901 plane_state
= intel_atomic_get_plane_state(state
, plane
);
2902 if (IS_ERR(plane_state
))
2903 return PTR_ERR(plane_state
);
2905 new_crtc_state
->update_planes
|= BIT(plane_id
);
2906 new_crtc_state
->async_flip_planes
= 0;
2907 new_crtc_state
->do_async_flip
= false;
2914 * If Fixed Refresh Rate:
2915 * Program DEEP PKG_C_LATENCY Pkg C with highest valid latency from
2916 * watermark level1 and up and above. If watermark level 1 is
2917 * invalid program it with all 1's.
2918 * Program PKG_C_LATENCY Added Wake Time = DSB execution time
2919 * If Variable Refresh Rate:
2920 * Program DEEP PKG_C_LATENCY Pkg C with all 1's.
2921 * Program PKG_C_LATENCY Added Wake Time = 0
2924 skl_program_dpkgc_latency(struct drm_i915_private
*i915
, bool vrr_enabled
)
2926 u32 max_latency
= 0;
2927 u32 clear
= 0, val
= 0;
2928 u32 added_wake_time
= 0;
2930 if (DISPLAY_VER(i915
) < 20)
2934 max_latency
= LNL_PKG_C_LATENCY_MASK
;
2935 added_wake_time
= 0;
2937 max_latency
= skl_watermark_max_latency(i915
, 1);
2938 if (max_latency
== 0)
2939 max_latency
= LNL_PKG_C_LATENCY_MASK
;
2940 added_wake_time
= DSB_EXE_TIME
+
2941 i915
->display
.sagv
.block_time_us
;
2944 clear
|= LNL_ADDED_WAKE_TIME_MASK
| LNL_PKG_C_LATENCY_MASK
;
2945 val
|= REG_FIELD_PREP(LNL_PKG_C_LATENCY_MASK
, max_latency
);
2946 val
|= REG_FIELD_PREP(LNL_ADDED_WAKE_TIME_MASK
, added_wake_time
);
2948 intel_uncore_rmw(&i915
->uncore
, LNL_PKG_C_LATENCY
, clear
, val
);
2952 skl_compute_wm(struct intel_atomic_state
*state
)
2954 struct intel_crtc
*crtc
;
2955 struct intel_crtc_state __maybe_unused
*new_crtc_state
;
2957 bool vrr_enabled
= false;
2959 for_each_new_intel_crtc_in_state(state
, crtc
, new_crtc_state
, i
) {
2960 ret
= skl_build_pipe_wm(state
, crtc
);
2965 ret
= skl_compute_ddb(state
);
2969 ret
= intel_compute_sagv_mask(state
);
2974 * skl_compute_ddb() will have adjusted the final watermarks
2975 * based on how much ddb is available. Now we can actually
2976 * check if the final watermarks changed.
2978 for_each_new_intel_crtc_in_state(state
, crtc
, new_crtc_state
, i
) {
2979 ret
= skl_wm_add_affected_planes(state
, crtc
);
2983 if (new_crtc_state
->vrr
.enable
)
2987 skl_program_dpkgc_latency(to_i915(state
->base
.dev
), vrr_enabled
);
2989 skl_print_wm_changes(state
);
2994 static void skl_wm_level_from_reg_val(u32 val
, struct skl_wm_level
*level
)
2996 level
->enable
= val
& PLANE_WM_EN
;
2997 level
->ignore_lines
= val
& PLANE_WM_IGNORE_LINES
;
2998 level
->blocks
= REG_FIELD_GET(PLANE_WM_BLOCKS_MASK
, val
);
2999 level
->lines
= REG_FIELD_GET(PLANE_WM_LINES_MASK
, val
);
3002 static void skl_pipe_wm_get_hw_state(struct intel_crtc
*crtc
,
3003 struct skl_pipe_wm
*out
)
3005 struct drm_i915_private
*i915
= to_i915(crtc
->base
.dev
);
3006 enum pipe pipe
= crtc
->pipe
;
3007 enum plane_id plane_id
;
3011 for_each_plane_id_on_crtc(crtc
, plane_id
) {
3012 struct skl_plane_wm
*wm
= &out
->planes
[plane_id
];
3014 for (level
= 0; level
< i915
->display
.wm
.num_levels
; level
++) {
3015 if (plane_id
!= PLANE_CURSOR
)
3016 val
= intel_de_read(i915
, PLANE_WM(pipe
, plane_id
, level
));
3018 val
= intel_de_read(i915
, CUR_WM(pipe
, level
));
3020 skl_wm_level_from_reg_val(val
, &wm
->wm
[level
]);
3023 if (plane_id
!= PLANE_CURSOR
)
3024 val
= intel_de_read(i915
, PLANE_WM_TRANS(pipe
, plane_id
));
3026 val
= intel_de_read(i915
, CUR_WM_TRANS(pipe
));
3028 skl_wm_level_from_reg_val(val
, &wm
->trans_wm
);
3030 if (HAS_HW_SAGV_WM(i915
)) {
3031 if (plane_id
!= PLANE_CURSOR
)
3032 val
= intel_de_read(i915
, PLANE_WM_SAGV(pipe
, plane_id
));
3034 val
= intel_de_read(i915
, CUR_WM_SAGV(pipe
));
3036 skl_wm_level_from_reg_val(val
, &wm
->sagv
.wm0
);
3038 if (plane_id
!= PLANE_CURSOR
)
3039 val
= intel_de_read(i915
, PLANE_WM_SAGV_TRANS(pipe
, plane_id
));
3041 val
= intel_de_read(i915
, CUR_WM_SAGV_TRANS(pipe
));
3043 skl_wm_level_from_reg_val(val
, &wm
->sagv
.trans_wm
);
3044 } else if (DISPLAY_VER(i915
) >= 12) {
3045 wm
->sagv
.wm0
= wm
->wm
[0];
3046 wm
->sagv
.trans_wm
= wm
->trans_wm
;
3051 static void skl_wm_get_hw_state(struct drm_i915_private
*i915
)
3053 struct intel_dbuf_state
*dbuf_state
=
3054 to_intel_dbuf_state(i915
->display
.dbuf
.obj
.state
);
3055 struct intel_crtc
*crtc
;
3057 if (HAS_MBUS_JOINING(i915
))
3058 dbuf_state
->joined_mbus
= intel_de_read(i915
, MBUS_CTL
) & MBUS_JOIN
;
3060 for_each_intel_crtc(&i915
->drm
, crtc
) {
3061 struct intel_crtc_state
*crtc_state
=
3062 to_intel_crtc_state(crtc
->base
.state
);
3063 enum pipe pipe
= crtc
->pipe
;
3064 unsigned int mbus_offset
;
3065 enum plane_id plane_id
;
3068 memset(&crtc_state
->wm
.skl
.optimal
, 0,
3069 sizeof(crtc_state
->wm
.skl
.optimal
));
3070 if (crtc_state
->hw
.active
)
3071 skl_pipe_wm_get_hw_state(crtc
, &crtc_state
->wm
.skl
.optimal
);
3072 crtc_state
->wm
.skl
.raw
= crtc_state
->wm
.skl
.optimal
;
3074 memset(&dbuf_state
->ddb
[pipe
], 0, sizeof(dbuf_state
->ddb
[pipe
]));
3076 for_each_plane_id_on_crtc(crtc
, plane_id
) {
3077 struct skl_ddb_entry
*ddb
=
3078 &crtc_state
->wm
.skl
.plane_ddb
[plane_id
];
3079 struct skl_ddb_entry
*ddb_y
=
3080 &crtc_state
->wm
.skl
.plane_ddb_y
[plane_id
];
3082 if (!crtc_state
->hw
.active
)
3085 skl_ddb_get_hw_plane_state(i915
, crtc
->pipe
,
3086 plane_id
, ddb
, ddb_y
);
3088 skl_ddb_entry_union(&dbuf_state
->ddb
[pipe
], ddb
);
3089 skl_ddb_entry_union(&dbuf_state
->ddb
[pipe
], ddb_y
);
3092 dbuf_state
->weight
[pipe
] = intel_crtc_ddb_weight(crtc_state
);
3095 * Used for checking overlaps, so we need absolute
3096 * offsets instead of MBUS relative offsets.
3098 slices
= skl_compute_dbuf_slices(crtc
, dbuf_state
->active_pipes
,
3099 dbuf_state
->joined_mbus
);
3100 mbus_offset
= mbus_ddb_offset(i915
, slices
);
3101 crtc_state
->wm
.skl
.ddb
.start
= mbus_offset
+ dbuf_state
->ddb
[pipe
].start
;
3102 crtc_state
->wm
.skl
.ddb
.end
= mbus_offset
+ dbuf_state
->ddb
[pipe
].end
;
3104 /* The slices actually used by the planes on the pipe */
3105 dbuf_state
->slices
[pipe
] =
3106 skl_ddb_dbuf_slice_mask(i915
, &crtc_state
->wm
.skl
.ddb
);
3108 drm_dbg_kms(&i915
->drm
,
3109 "[CRTC:%d:%s] dbuf slices 0x%x, ddb (%d - %d), active pipes 0x%x, mbus joined: %s\n",
3110 crtc
->base
.base
.id
, crtc
->base
.name
,
3111 dbuf_state
->slices
[pipe
], dbuf_state
->ddb
[pipe
].start
,
3112 dbuf_state
->ddb
[pipe
].end
, dbuf_state
->active_pipes
,
3113 str_yes_no(dbuf_state
->joined_mbus
));
3116 dbuf_state
->enabled_slices
= i915
->display
.dbuf
.enabled_slices
;
3119 static bool skl_dbuf_is_misconfigured(struct drm_i915_private
*i915
)
3121 const struct intel_dbuf_state
*dbuf_state
=
3122 to_intel_dbuf_state(i915
->display
.dbuf
.obj
.state
);
3123 struct skl_ddb_entry entries
[I915_MAX_PIPES
] = {};
3124 struct intel_crtc
*crtc
;
3126 for_each_intel_crtc(&i915
->drm
, crtc
) {
3127 const struct intel_crtc_state
*crtc_state
=
3128 to_intel_crtc_state(crtc
->base
.state
);
3130 entries
[crtc
->pipe
] = crtc_state
->wm
.skl
.ddb
;
3133 for_each_intel_crtc(&i915
->drm
, crtc
) {
3134 const struct intel_crtc_state
*crtc_state
=
3135 to_intel_crtc_state(crtc
->base
.state
);
3138 slices
= skl_compute_dbuf_slices(crtc
, dbuf_state
->active_pipes
,
3139 dbuf_state
->joined_mbus
);
3140 if (dbuf_state
->slices
[crtc
->pipe
] & ~slices
)
3143 if (skl_ddb_allocation_overlaps(&crtc_state
->wm
.skl
.ddb
, entries
,
3144 I915_MAX_PIPES
, crtc
->pipe
))
3151 static void skl_wm_sanitize(struct drm_i915_private
*i915
)
3153 struct intel_crtc
*crtc
;
3156 * On TGL/RKL (at least) the BIOS likes to assign the planes
3157 * to the wrong DBUF slices. This will cause an infinite loop
3158 * in skl_commit_modeset_enables() as it can't find a way to
3159 * transition between the old bogus DBUF layout to the new
3160 * proper DBUF layout without DBUF allocation overlaps between
3161 * the planes (which cannot be allowed or else the hardware
3162 * may hang). If we detect a bogus DBUF layout just turn off
3163 * all the planes so that skl_commit_modeset_enables() can
3164 * simply ignore them.
3166 if (!skl_dbuf_is_misconfigured(i915
))
3169 drm_dbg_kms(&i915
->drm
, "BIOS has misprogrammed the DBUF, disabling all planes\n");
3171 for_each_intel_crtc(&i915
->drm
, crtc
) {
3172 struct intel_plane
*plane
= to_intel_plane(crtc
->base
.primary
);
3173 const struct intel_plane_state
*plane_state
=
3174 to_intel_plane_state(plane
->base
.state
);
3175 struct intel_crtc_state
*crtc_state
=
3176 to_intel_crtc_state(crtc
->base
.state
);
3178 if (plane_state
->uapi
.visible
)
3179 intel_plane_disable_noatomic(crtc
, plane
);
3181 drm_WARN_ON(&i915
->drm
, crtc_state
->active_planes
!= 0);
3183 memset(&crtc_state
->wm
.skl
.ddb
, 0, sizeof(crtc_state
->wm
.skl
.ddb
));
3187 static void skl_wm_get_hw_state_and_sanitize(struct drm_i915_private
*i915
)
3189 skl_wm_get_hw_state(i915
);
3190 skl_wm_sanitize(i915
);
3193 void intel_wm_state_verify(struct intel_atomic_state
*state
,
3194 struct intel_crtc
*crtc
)
3196 struct drm_i915_private
*i915
= to_i915(state
->base
.dev
);
3197 const struct intel_crtc_state
*new_crtc_state
=
3198 intel_atomic_get_new_crtc_state(state
, crtc
);
3199 struct skl_hw_state
{
3200 struct skl_ddb_entry ddb
[I915_MAX_PLANES
];
3201 struct skl_ddb_entry ddb_y
[I915_MAX_PLANES
];
3202 struct skl_pipe_wm wm
;
3204 const struct skl_pipe_wm
*sw_wm
= &new_crtc_state
->wm
.skl
.optimal
;
3205 struct intel_plane
*plane
;
3206 u8 hw_enabled_slices
;
3209 if (DISPLAY_VER(i915
) < 9 || !new_crtc_state
->hw
.active
)
3212 hw
= kzalloc(sizeof(*hw
), GFP_KERNEL
);
3216 skl_pipe_wm_get_hw_state(crtc
, &hw
->wm
);
3218 skl_pipe_ddb_get_hw_state(crtc
, hw
->ddb
, hw
->ddb_y
);
3220 hw_enabled_slices
= intel_enabled_dbuf_slices_mask(i915
);
3222 if (DISPLAY_VER(i915
) >= 11 &&
3223 hw_enabled_slices
!= i915
->display
.dbuf
.enabled_slices
)
3225 "mismatch in DBUF Slices (expected 0x%x, got 0x%x)\n",
3226 i915
->display
.dbuf
.enabled_slices
,
3229 for_each_intel_plane_on_crtc(&i915
->drm
, crtc
, plane
) {
3230 const struct skl_ddb_entry
*hw_ddb_entry
, *sw_ddb_entry
;
3231 const struct skl_wm_level
*hw_wm_level
, *sw_wm_level
;
3234 for (level
= 0; level
< i915
->display
.wm
.num_levels
; level
++) {
3235 hw_wm_level
= &hw
->wm
.planes
[plane
->id
].wm
[level
];
3236 sw_wm_level
= skl_plane_wm_level(sw_wm
, plane
->id
, level
);
3238 if (skl_wm_level_equals(hw_wm_level
, sw_wm_level
))
3242 "[PLANE:%d:%s] mismatch in WM%d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
3243 plane
->base
.base
.id
, plane
->base
.name
, level
,
3244 sw_wm_level
->enable
,
3245 sw_wm_level
->blocks
,
3247 hw_wm_level
->enable
,
3248 hw_wm_level
->blocks
,
3249 hw_wm_level
->lines
);
3252 hw_wm_level
= &hw
->wm
.planes
[plane
->id
].trans_wm
;
3253 sw_wm_level
= skl_plane_trans_wm(sw_wm
, plane
->id
);
3255 if (!skl_wm_level_equals(hw_wm_level
, sw_wm_level
)) {
3257 "[PLANE:%d:%s] mismatch in trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
3258 plane
->base
.base
.id
, plane
->base
.name
,
3259 sw_wm_level
->enable
,
3260 sw_wm_level
->blocks
,
3262 hw_wm_level
->enable
,
3263 hw_wm_level
->blocks
,
3264 hw_wm_level
->lines
);
3267 hw_wm_level
= &hw
->wm
.planes
[plane
->id
].sagv
.wm0
;
3268 sw_wm_level
= &sw_wm
->planes
[plane
->id
].sagv
.wm0
;
3270 if (HAS_HW_SAGV_WM(i915
) &&
3271 !skl_wm_level_equals(hw_wm_level
, sw_wm_level
)) {
3273 "[PLANE:%d:%s] mismatch in SAGV WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
3274 plane
->base
.base
.id
, plane
->base
.name
,
3275 sw_wm_level
->enable
,
3276 sw_wm_level
->blocks
,
3278 hw_wm_level
->enable
,
3279 hw_wm_level
->blocks
,
3280 hw_wm_level
->lines
);
3283 hw_wm_level
= &hw
->wm
.planes
[plane
->id
].sagv
.trans_wm
;
3284 sw_wm_level
= &sw_wm
->planes
[plane
->id
].sagv
.trans_wm
;
3286 if (HAS_HW_SAGV_WM(i915
) &&
3287 !skl_wm_level_equals(hw_wm_level
, sw_wm_level
)) {
3289 "[PLANE:%d:%s] mismatch in SAGV trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
3290 plane
->base
.base
.id
, plane
->base
.name
,
3291 sw_wm_level
->enable
,
3292 sw_wm_level
->blocks
,
3294 hw_wm_level
->enable
,
3295 hw_wm_level
->blocks
,
3296 hw_wm_level
->lines
);
3300 hw_ddb_entry
= &hw
->ddb
[PLANE_CURSOR
];
3301 sw_ddb_entry
= &new_crtc_state
->wm
.skl
.plane_ddb
[PLANE_CURSOR
];
3303 if (!skl_ddb_entry_equal(hw_ddb_entry
, sw_ddb_entry
)) {
3305 "[PLANE:%d:%s] mismatch in DDB (expected (%u,%u), found (%u,%u))\n",
3306 plane
->base
.base
.id
, plane
->base
.name
,
3307 sw_ddb_entry
->start
, sw_ddb_entry
->end
,
3308 hw_ddb_entry
->start
, hw_ddb_entry
->end
);
3315 bool skl_watermark_ipc_enabled(struct drm_i915_private
*i915
)
3317 return i915
->display
.wm
.ipc_enabled
;
3320 void skl_watermark_ipc_update(struct drm_i915_private
*i915
)
3325 intel_de_rmw(i915
, DISP_ARB_CTL2
, DISP_IPC_ENABLE
,
3326 skl_watermark_ipc_enabled(i915
) ? DISP_IPC_ENABLE
: 0);
3329 static bool skl_watermark_ipc_can_enable(struct drm_i915_private
*i915
)
3331 /* Display WA #0477 WaDisableIPC: skl */
3332 if (IS_SKYLAKE(i915
))
3335 /* Display WA #1141: SKL:all KBL:all CFL */
3336 if (IS_KABYLAKE(i915
) ||
3337 IS_COFFEELAKE(i915
) ||
3339 return i915
->dram_info
.symmetric_memory
;
3344 void skl_watermark_ipc_init(struct drm_i915_private
*i915
)
3349 i915
->display
.wm
.ipc_enabled
= skl_watermark_ipc_can_enable(i915
);
3351 skl_watermark_ipc_update(i915
);
3355 adjust_wm_latency(struct drm_i915_private
*i915
,
3356 u16 wm
[], int num_levels
, int read_latency
)
3358 bool wm_lv_0_adjust_needed
= i915
->dram_info
.wm_lv_0_adjust_needed
;
3362 * If a level n (n > 1) has a 0us latency, all levels m (m >= n)
3363 * need to be disabled. We make sure to sanitize the values out
3364 * of the punit to satisfy this requirement.
3366 for (level
= 1; level
< num_levels
; level
++) {
3367 if (wm
[level
] == 0) {
3368 for (i
= level
+ 1; i
< num_levels
; i
++)
3377 * WaWmMemoryReadLatency
3379 * punit doesn't take into account the read latency so we need
3380 * to add proper adjustement to each valid level we retrieve
3381 * from the punit when level 0 response data is 0us.
3384 for (level
= 0; level
< num_levels
; level
++)
3385 wm
[level
] += read_latency
;
3389 * WA Level-0 adjustment for 16GB DIMMs: SKL+
3390 * If we could not get dimm info enable this WA to prevent from
3391 * any underrun. If not able to get Dimm info assume 16GB dimm
3392 * to avoid any underrun.
3394 if (wm_lv_0_adjust_needed
)
3398 static void mtl_read_wm_latency(struct drm_i915_private
*i915
, u16 wm
[])
3400 int num_levels
= i915
->display
.wm
.num_levels
;
3403 val
= intel_de_read(i915
, MTL_LATENCY_LP0_LP1
);
3404 wm
[0] = REG_FIELD_GET(MTL_LATENCY_LEVEL_EVEN_MASK
, val
);
3405 wm
[1] = REG_FIELD_GET(MTL_LATENCY_LEVEL_ODD_MASK
, val
);
3407 val
= intel_de_read(i915
, MTL_LATENCY_LP2_LP3
);
3408 wm
[2] = REG_FIELD_GET(MTL_LATENCY_LEVEL_EVEN_MASK
, val
);
3409 wm
[3] = REG_FIELD_GET(MTL_LATENCY_LEVEL_ODD_MASK
, val
);
3411 val
= intel_de_read(i915
, MTL_LATENCY_LP4_LP5
);
3412 wm
[4] = REG_FIELD_GET(MTL_LATENCY_LEVEL_EVEN_MASK
, val
);
3413 wm
[5] = REG_FIELD_GET(MTL_LATENCY_LEVEL_ODD_MASK
, val
);
3415 adjust_wm_latency(i915
, wm
, num_levels
, 6);
3418 static void skl_read_wm_latency(struct drm_i915_private
*i915
, u16 wm
[])
3420 int num_levels
= i915
->display
.wm
.num_levels
;
3421 int read_latency
= DISPLAY_VER(i915
) >= 12 ? 3 : 2;
3422 int mult
= IS_DG2(i915
) ? 2 : 1;
3426 /* read the first set of memory latencies[0:3] */
3427 val
= 0; /* data0 to be programmed to 0 for first set */
3428 ret
= snb_pcode_read(&i915
->uncore
, GEN9_PCODE_READ_MEM_LATENCY
, &val
, NULL
);
3430 drm_err(&i915
->drm
, "SKL Mailbox read error = %d\n", ret
);
3434 wm
[0] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_0_4_MASK
, val
) * mult
;
3435 wm
[1] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_1_5_MASK
, val
) * mult
;
3436 wm
[2] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_2_6_MASK
, val
) * mult
;
3437 wm
[3] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_3_7_MASK
, val
) * mult
;
3439 /* read the second set of memory latencies[4:7] */
3440 val
= 1; /* data0 to be programmed to 1 for second set */
3441 ret
= snb_pcode_read(&i915
->uncore
, GEN9_PCODE_READ_MEM_LATENCY
, &val
, NULL
);
3443 drm_err(&i915
->drm
, "SKL Mailbox read error = %d\n", ret
);
3447 wm
[4] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_0_4_MASK
, val
) * mult
;
3448 wm
[5] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_1_5_MASK
, val
) * mult
;
3449 wm
[6] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_2_6_MASK
, val
) * mult
;
3450 wm
[7] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_3_7_MASK
, val
) * mult
;
3452 adjust_wm_latency(i915
, wm
, num_levels
, read_latency
);
3455 static void skl_setup_wm_latency(struct drm_i915_private
*i915
)
3457 if (HAS_HW_SAGV_WM(i915
))
3458 i915
->display
.wm
.num_levels
= 6;
3460 i915
->display
.wm
.num_levels
= 8;
3462 if (DISPLAY_VER(i915
) >= 14)
3463 mtl_read_wm_latency(i915
, i915
->display
.wm
.skl_latency
);
3465 skl_read_wm_latency(i915
, i915
->display
.wm
.skl_latency
);
3467 intel_print_wm_latency(i915
, "Gen9 Plane", i915
->display
.wm
.skl_latency
);
3470 static const struct intel_wm_funcs skl_wm_funcs
= {
3471 .compute_global_watermarks
= skl_compute_wm
,
3472 .get_hw_state
= skl_wm_get_hw_state_and_sanitize
,
3475 void skl_wm_init(struct drm_i915_private
*i915
)
3477 intel_sagv_init(i915
);
3479 skl_setup_wm_latency(i915
);
3481 i915
->display
.funcs
.wm
= &skl_wm_funcs
;
3484 static struct intel_global_state
*intel_dbuf_duplicate_state(struct intel_global_obj
*obj
)
3486 struct intel_dbuf_state
*dbuf_state
;
3488 dbuf_state
= kmemdup(obj
->state
, sizeof(*dbuf_state
), GFP_KERNEL
);
3492 return &dbuf_state
->base
;
3495 static void intel_dbuf_destroy_state(struct intel_global_obj
*obj
,
3496 struct intel_global_state
*state
)
3501 static const struct intel_global_state_funcs intel_dbuf_funcs
= {
3502 .atomic_duplicate_state
= intel_dbuf_duplicate_state
,
3503 .atomic_destroy_state
= intel_dbuf_destroy_state
,
3506 struct intel_dbuf_state
*
3507 intel_atomic_get_dbuf_state(struct intel_atomic_state
*state
)
3509 struct drm_i915_private
*i915
= to_i915(state
->base
.dev
);
3510 struct intel_global_state
*dbuf_state
;
3512 dbuf_state
= intel_atomic_get_global_obj_state(state
, &i915
->display
.dbuf
.obj
);
3513 if (IS_ERR(dbuf_state
))
3514 return ERR_CAST(dbuf_state
);
3516 return to_intel_dbuf_state(dbuf_state
);
3519 int intel_dbuf_init(struct drm_i915_private
*i915
)
3521 struct intel_dbuf_state
*dbuf_state
;
3523 dbuf_state
= kzalloc(sizeof(*dbuf_state
), GFP_KERNEL
);
3527 intel_atomic_global_obj_init(i915
, &i915
->display
.dbuf
.obj
,
3528 &dbuf_state
->base
, &intel_dbuf_funcs
);
3534 * Configure MBUS_CTL and all DBUF_CTL_S of each slice to join_mbus state before
3535 * update the request state of all DBUS slices.
3537 static void update_mbus_pre_enable(struct intel_atomic_state
*state
)
3539 struct drm_i915_private
*i915
= to_i915(state
->base
.dev
);
3540 u32 mbus_ctl
, dbuf_min_tracker_val
;
3541 enum dbuf_slice slice
;
3542 const struct intel_dbuf_state
*dbuf_state
=
3543 intel_atomic_get_new_dbuf_state(state
);
3545 if (!HAS_MBUS_JOINING(i915
))
3549 * TODO: Implement vblank synchronized MBUS joining changes.
3550 * Must be properly coordinated with dbuf reprogramming.
3552 if (dbuf_state
->joined_mbus
) {
3553 mbus_ctl
= MBUS_HASHING_MODE_1x4
| MBUS_JOIN
|
3554 MBUS_JOIN_PIPE_SELECT_NONE
;
3555 dbuf_min_tracker_val
= DBUF_MIN_TRACKER_STATE_SERVICE(3);
3557 mbus_ctl
= MBUS_HASHING_MODE_2x2
|
3558 MBUS_JOIN_PIPE_SELECT_NONE
;
3559 dbuf_min_tracker_val
= DBUF_MIN_TRACKER_STATE_SERVICE(1);
3562 intel_de_rmw(i915
, MBUS_CTL
,
3563 MBUS_HASHING_MODE_MASK
| MBUS_JOIN
|
3564 MBUS_JOIN_PIPE_SELECT_MASK
, mbus_ctl
);
3566 for_each_dbuf_slice(i915
, slice
)
3567 intel_de_rmw(i915
, DBUF_CTL_S(slice
),
3568 DBUF_MIN_TRACKER_STATE_SERVICE_MASK
,
3569 dbuf_min_tracker_val
);
3572 void intel_dbuf_pre_plane_update(struct intel_atomic_state
*state
)
3574 struct drm_i915_private
*i915
= to_i915(state
->base
.dev
);
3575 const struct intel_dbuf_state
*new_dbuf_state
=
3576 intel_atomic_get_new_dbuf_state(state
);
3577 const struct intel_dbuf_state
*old_dbuf_state
=
3578 intel_atomic_get_old_dbuf_state(state
);
3580 if (!new_dbuf_state
||
3581 (new_dbuf_state
->enabled_slices
== old_dbuf_state
->enabled_slices
&&
3582 new_dbuf_state
->joined_mbus
== old_dbuf_state
->joined_mbus
))
3585 WARN_ON(!new_dbuf_state
->base
.changed
);
3587 update_mbus_pre_enable(state
);
3588 gen9_dbuf_slices_update(i915
,
3589 old_dbuf_state
->enabled_slices
|
3590 new_dbuf_state
->enabled_slices
);
3593 void intel_dbuf_post_plane_update(struct intel_atomic_state
*state
)
3595 struct drm_i915_private
*i915
= to_i915(state
->base
.dev
);
3596 const struct intel_dbuf_state
*new_dbuf_state
=
3597 intel_atomic_get_new_dbuf_state(state
);
3598 const struct intel_dbuf_state
*old_dbuf_state
=
3599 intel_atomic_get_old_dbuf_state(state
);
3601 if (!new_dbuf_state
||
3602 (new_dbuf_state
->enabled_slices
== old_dbuf_state
->enabled_slices
&&
3603 new_dbuf_state
->joined_mbus
== old_dbuf_state
->joined_mbus
))
3606 WARN_ON(!new_dbuf_state
->base
.changed
);
3608 gen9_dbuf_slices_update(i915
,
3609 new_dbuf_state
->enabled_slices
);
3612 static bool xelpdp_is_only_pipe_per_dbuf_bank(enum pipe pipe
, u8 active_pipes
)
3616 return !(active_pipes
& BIT(PIPE_D
));
3618 return !(active_pipes
& BIT(PIPE_A
));
3620 return !(active_pipes
& BIT(PIPE_C
));
3622 return !(active_pipes
& BIT(PIPE_B
));
3623 default: /* to suppress compiler warning */
3631 void intel_mbus_dbox_update(struct intel_atomic_state
*state
)
3633 struct drm_i915_private
*i915
= to_i915(state
->base
.dev
);
3634 const struct intel_dbuf_state
*new_dbuf_state
, *old_dbuf_state
;
3635 const struct intel_crtc_state
*new_crtc_state
;
3636 const struct intel_crtc
*crtc
;
3640 if (DISPLAY_VER(i915
) < 11)
3643 new_dbuf_state
= intel_atomic_get_new_dbuf_state(state
);
3644 old_dbuf_state
= intel_atomic_get_old_dbuf_state(state
);
3645 if (!new_dbuf_state
||
3646 (new_dbuf_state
->joined_mbus
== old_dbuf_state
->joined_mbus
&&
3647 new_dbuf_state
->active_pipes
== old_dbuf_state
->active_pipes
))
3650 if (DISPLAY_VER(i915
) >= 14)
3651 val
|= MBUS_DBOX_I_CREDIT(2);
3653 if (DISPLAY_VER(i915
) >= 12) {
3654 val
|= MBUS_DBOX_B2B_TRANSACTIONS_MAX(16);
3655 val
|= MBUS_DBOX_B2B_TRANSACTIONS_DELAY(1);
3656 val
|= MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN
;
3659 if (DISPLAY_VER(i915
) >= 14)
3660 val
|= new_dbuf_state
->joined_mbus
? MBUS_DBOX_A_CREDIT(12) :
3661 MBUS_DBOX_A_CREDIT(8);
3662 else if (IS_ALDERLAKE_P(i915
))
3663 /* Wa_22010947358:adl-p */
3664 val
|= new_dbuf_state
->joined_mbus
? MBUS_DBOX_A_CREDIT(6) :
3665 MBUS_DBOX_A_CREDIT(4);
3667 val
|= MBUS_DBOX_A_CREDIT(2);
3669 if (DISPLAY_VER(i915
) >= 14) {
3670 val
|= MBUS_DBOX_B_CREDIT(0xA);
3671 } else if (IS_ALDERLAKE_P(i915
)) {
3672 val
|= MBUS_DBOX_BW_CREDIT(2);
3673 val
|= MBUS_DBOX_B_CREDIT(8);
3674 } else if (DISPLAY_VER(i915
) >= 12) {
3675 val
|= MBUS_DBOX_BW_CREDIT(2);
3676 val
|= MBUS_DBOX_B_CREDIT(12);
3678 val
|= MBUS_DBOX_BW_CREDIT(1);
3679 val
|= MBUS_DBOX_B_CREDIT(8);
3682 for_each_new_intel_crtc_in_state(state
, crtc
, new_crtc_state
, i
) {
3685 if (!new_crtc_state
->hw
.active
)
3688 if (DISPLAY_VER(i915
) >= 14) {
3689 if (xelpdp_is_only_pipe_per_dbuf_bank(crtc
->pipe
,
3690 new_dbuf_state
->active_pipes
))
3691 pipe_val
|= MBUS_DBOX_BW_8CREDITS_MTL
;
3693 pipe_val
|= MBUS_DBOX_BW_4CREDITS_MTL
;
3696 intel_de_write(i915
, PIPE_MBUS_DBOX_CTL(crtc
->pipe
), pipe_val
);
3700 static int skl_watermark_ipc_status_show(struct seq_file
*m
, void *data
)
3702 struct drm_i915_private
*i915
= m
->private;
3704 seq_printf(m
, "Isochronous Priority Control: %s\n",
3705 str_yes_no(skl_watermark_ipc_enabled(i915
)));
3709 static int skl_watermark_ipc_status_open(struct inode
*inode
, struct file
*file
)
3711 struct drm_i915_private
*i915
= inode
->i_private
;
3713 return single_open(file
, skl_watermark_ipc_status_show
, i915
);
3716 static ssize_t
skl_watermark_ipc_status_write(struct file
*file
,
3717 const char __user
*ubuf
,
3718 size_t len
, loff_t
*offp
)
3720 struct seq_file
*m
= file
->private_data
;
3721 struct drm_i915_private
*i915
= m
->private;
3722 intel_wakeref_t wakeref
;
3726 ret
= kstrtobool_from_user(ubuf
, len
, &enable
);
3730 with_intel_runtime_pm(&i915
->runtime_pm
, wakeref
) {
3731 if (!skl_watermark_ipc_enabled(i915
) && enable
)
3732 drm_info(&i915
->drm
,
3733 "Enabling IPC: WM will be proper only after next commit\n");
3734 i915
->display
.wm
.ipc_enabled
= enable
;
3735 skl_watermark_ipc_update(i915
);
3741 static const struct file_operations skl_watermark_ipc_status_fops
= {
3742 .owner
= THIS_MODULE
,
3743 .open
= skl_watermark_ipc_status_open
,
3745 .llseek
= seq_lseek
,
3746 .release
= single_release
,
3747 .write
= skl_watermark_ipc_status_write
3750 static int intel_sagv_status_show(struct seq_file
*m
, void *unused
)
3752 struct drm_i915_private
*i915
= m
->private;
3753 static const char * const sagv_status
[] = {
3754 [I915_SAGV_UNKNOWN
] = "unknown",
3755 [I915_SAGV_DISABLED
] = "disabled",
3756 [I915_SAGV_ENABLED
] = "enabled",
3757 [I915_SAGV_NOT_CONTROLLED
] = "not controlled",
3760 seq_printf(m
, "SAGV available: %s\n", str_yes_no(intel_has_sagv(i915
)));
3761 seq_printf(m
, "SAGV modparam: %s\n",
3762 str_enabled_disabled(i915
->display
.params
.enable_sagv
));
3763 seq_printf(m
, "SAGV status: %s\n", sagv_status
[i915
->display
.sagv
.status
]);
3764 seq_printf(m
, "SAGV block time: %d usec\n", i915
->display
.sagv
.block_time_us
);
3769 DEFINE_SHOW_ATTRIBUTE(intel_sagv_status
);
3771 void skl_watermark_debugfs_register(struct drm_i915_private
*i915
)
3773 struct drm_minor
*minor
= i915
->drm
.primary
;
3776 debugfs_create_file("i915_ipc_status", 0644, minor
->debugfs_root
, i915
,
3777 &skl_watermark_ipc_status_fops
);
3780 debugfs_create_file("i915_sagv_status", 0444, minor
->debugfs_root
, i915
,
3781 &intel_sagv_status_fops
);
3784 unsigned int skl_watermark_max_latency(struct drm_i915_private
*i915
, int initial_wm_level
)
3788 for (level
= i915
->display
.wm
.num_levels
- 1; level
>= initial_wm_level
; level
--) {
3789 unsigned int latency
= skl_wm_latency(i915
, level
, NULL
);