drivers/gpu/drm/i915/gt/intel_context_types.h

   1 /*
   2  * SPDX-License-Identifier: MIT
   3  *
   4  * Copyright © 2019 Intel Corporation
   5  */
   6
   7 #ifndef __INTEL_CONTEXT_TYPES__
   8 #define __INTEL_CONTEXT_TYPES__
   9
  10 #include <linux/average.h>
  11 #include <linux/kref.h>
  12 #include <linux/list.h>
  13 #include <linux/mutex.h>
  14 #include <linux/types.h>
  15
  16 #include "i915_active_types.h"
  17 #include "i915_utils.h"
  18 #include "intel_engine_types.h"
  19 #include "intel_sseu.h"
  20
  21 #define CONTEXT_REDZONE POISON_INUSE
  22
  23 DECLARE_EWMA(runtime, 3, 8);
  24
  25 struct i915_gem_context;
  26 struct i915_vma;
  27 struct intel_context;
  28 struct intel_ring;
  29
  30 struct intel_context_ops {
  31         int (*alloc)(struct intel_context *ce);
  32
  33         int (*pin)(struct intel_context *ce);
  34         void (*unpin)(struct intel_context *ce);
  35
  36         void (*enter)(struct intel_context *ce);
  37         void (*exit)(struct intel_context *ce);
  38
  39         void (*reset)(struct intel_context *ce);
  40         void (*destroy)(struct kref *kref);
  41 };
  42
  43 struct intel_context {
  44         struct kref ref;
  45
  46         struct intel_engine_cs *engine;
  47         struct intel_engine_cs *inflight;
  48 #define intel_context_inflight(ce) ptr_mask_bits(READ_ONCE((ce)->inflight), 2)
  49 #define intel_context_inflight_count(ce) ptr_unmask_bits(READ_ONCE((ce)->inflight), 2)
  50
  51         struct i915_address_space *vm;
  52         struct i915_gem_context __rcu *gem_context;
  53
  54         struct list_head signal_link;
  55         struct list_head signals;
  56
  57         struct i915_vma *state;
  58         struct intel_ring *ring;
  59         struct intel_timeline *timeline;
  60
  61         unsigned long flags;
  62 #define CONTEXT_BARRIER_BIT             0
  63 #define CONTEXT_ALLOC_BIT               1
  64 #define CONTEXT_VALID_BIT               2
  65 #define CONTEXT_CLOSED_BIT              3
  66 #define CONTEXT_USE_SEMAPHORES          4
  67 #define CONTEXT_BANNED                  5
  68 #define CONTEXT_FORCE_SINGLE_SUBMISSION 6
  69 #define CONTEXT_NOPREEMPT               7
  70
  71         u32 *lrc_reg_state;
  72         union {
  73                 struct {
  74                         u32 lrca;
  75                         u32 ccid;
  76                 };
  77                 u64 desc;
  78         } lrc;
  79         u32 tag; /* cookie passed to HW to track this context on submission */
  80
  81         /* Time on GPU as tracked by the hw. */
  82         struct {
  83                 struct ewma_runtime avg;
  84                 u64 total;
  85                 u32 last;
  86                 I915_SELFTEST_DECLARE(u32 num_underflow);
  87                 I915_SELFTEST_DECLARE(u32 max_underflow);
  88         } runtime;
  89
  90         unsigned int active_count; /* protected by timeline->mutex */
  91
  92         atomic_t pin_count;
  93         struct mutex pin_mutex; /* guards pinning and associated on-gpuing */
  94
  95         /**
  96          * active: Active tracker for the rq activity (inc. external) on this
  97          * intel_context object.
  98          */
  99         struct i915_active active;
 100
 101         const struct intel_context_ops *ops;
 102
 103         /** sseu: Control eu/slice partitioning */
 104         struct intel_sseu sseu;
 105 };
 106
 107 #endif /* __INTEL_CONTEXT_TYPES__ */