drivers/gpu/drm/i915/gt/intel_engine_types.h

   1 /*
   2  * SPDX-License-Identifier: MIT
   3  *
   4  * Copyright © 2019 Intel Corporation
   5  */
   6
   7 #ifndef __INTEL_ENGINE_TYPES__
   8 #define __INTEL_ENGINE_TYPES__
   9
  10 #include <linux/average.h>
  11 #include <linux/hashtable.h>
  12 #include <linux/irq_work.h>
  13 #include <linux/kref.h>
  14 #include <linux/list.h>
  15 #include <linux/llist.h>
  16 #include <linux/rbtree.h>
  17 #include <linux/timer.h>
  18 #include <linux/types.h>
  19 #include <linux/workqueue.h>
  20
  21 #include "i915_gem.h"
  22 #include "i915_pmu.h"
  23 #include "i915_priolist_types.h"
  24 #include "i915_selftest.h"
  25 #include "intel_engine_pool_types.h"
  26 #include "intel_sseu.h"
  27 #include "intel_timeline_types.h"
  28 #include "intel_wakeref.h"
  29 #include "intel_workarounds_types.h"
  30
  31 /* Legacy HW Engine ID */
  32
  33 #define RCS0_HW         0
  34 #define VCS0_HW         1
  35 #define BCS0_HW         2
  36 #define VECS0_HW        3
  37 #define VCS1_HW         4
  38 #define VCS2_HW         6
  39 #define VCS3_HW         7
  40 #define VECS1_HW        12
  41
  42 /* Gen11+ HW Engine class + instance */
  43 #define RENDER_CLASS            0
  44 #define VIDEO_DECODE_CLASS      1
  45 #define VIDEO_ENHANCEMENT_CLASS 2
  46 #define COPY_ENGINE_CLASS       3
  47 #define OTHER_CLASS             4
  48 #define MAX_ENGINE_CLASS        4
  49 #define MAX_ENGINE_INSTANCE     3
  50
  51 #define I915_MAX_SLICES 3
  52 #define I915_MAX_SUBSLICES 8
  53
  54 #define I915_CMD_HASH_ORDER 9
  55
  56 struct dma_fence;
  57 struct drm_i915_gem_object;
  58 struct drm_i915_reg_table;
  59 struct i915_gem_context;
  60 struct i915_request;
  61 struct i915_sched_attr;
  62 struct intel_gt;
  63 struct intel_ring;
  64 struct intel_uncore;
  65
  66 typedef u8 intel_engine_mask_t;
  67 #define ALL_ENGINES ((intel_engine_mask_t)~0ul)
  68
  69 struct intel_hw_status_page {
  70         struct i915_vma *vma;
  71         u32 *addr;
  72 };
  73
  74 struct intel_instdone {
  75         u32 instdone;
  76         /* The following exist only in the RCS engine */
  77         u32 slice_common;
  78         u32 slice_common_extra[2];
  79         u32 sampler[I915_MAX_SLICES][I915_MAX_SUBSLICES];
  80         u32 row[I915_MAX_SLICES][I915_MAX_SUBSLICES];
  81 };
  82
  83 /*
  84  * we use a single page to load ctx workarounds so all of these
  85  * values are referred in terms of dwords
  86  *
  87  * struct i915_wa_ctx_bb:
  88  *  offset: specifies batch starting position, also helpful in case
  89  *    if we want to have multiple batches at different offsets based on
  90  *    some criteria. It is not a requirement at the moment but provides
  91  *    an option for future use.
  92  *  size: size of the batch in DWORDS
  93  */
  94 struct i915_ctx_workarounds {
  95         struct i915_wa_ctx_bb {
  96                 u32 offset;
  97                 u32 size;
  98         } indirect_ctx, per_ctx;
  99         struct i915_vma *vma;
 100 };
 101
 102 #define I915_MAX_VCS    4
 103 #define I915_MAX_VECS   2
 104
 105 /*
 106  * Engine IDs definitions.
 107  * Keep instances of the same type engine together.
 108  */
 109 enum intel_engine_id {
 110         RCS0 = 0,
 111         BCS0,
 112         VCS0,
 113         VCS1,
 114         VCS2,
 115         VCS3,
 116 #define _VCS(n) (VCS0 + (n))
 117         VECS0,
 118         VECS1,
 119 #define _VECS(n) (VECS0 + (n))
 120         I915_NUM_ENGINES
 121 #define INVALID_ENGINE ((enum intel_engine_id)-1)
 122 };
 123
 124 /* A simple estimator for the round-trip latency of an engine */
 125 DECLARE_EWMA(_engine_latency, 6, 4)
 126
 127 struct st_preempt_hang {
 128         struct completion completion;
 129         unsigned int count;
 130 };
 131
 132 /**
 133  * struct intel_engine_execlists - execlist submission queue and port state
 134  *
 135  * The struct intel_engine_execlists represents the combined logical state of
 136  * driver and the hardware state for execlist mode of submission.
 137  */
 138 struct intel_engine_execlists {
 139         /**
 140          * @tasklet: softirq tasklet for bottom handler
 141          */
 142         struct tasklet_struct tasklet;
 143
 144         /**
 145          * @timer: kick the current context if its timeslice expires
 146          */
 147         struct timer_list timer;
 148
 149         /**
 150          * @preempt: reset the current context if it fails to give way
 151          */
 152         struct timer_list preempt;
 153
 154         /**
 155          * @default_priolist: priority list for I915_PRIORITY_NORMAL
 156          */
 157         struct i915_priolist default_priolist;
 158
 159         /**
 160          * @error_interrupt: CS Master EIR
 161          *
 162          * The CS generates an interrupt when it detects an error. We capture
 163          * the first error interrupt, record the EIR and schedule the tasklet.
 164          * In the tasklet, we process the pending CS events to ensure we have
 165          * the guilty request, and then reset the engine.
 166          */
 167         u32 error_interrupt;
 168
 169         /**
 170          * @no_priolist: priority lists disabled
 171          */
 172         bool no_priolist;
 173
 174         /**
 175          * @submit_reg: gen-specific execlist submission register
 176          * set to the ExecList Submission Port (elsp) register pre-Gen11 and to
 177          * the ExecList Submission Queue Contents register array for Gen11+
 178          */
 179         u32 __iomem *submit_reg;
 180
 181         /**
 182          * @ctrl_reg: the enhanced execlists control register, used to load the
 183          * submit queue on the HW and to request preemptions to idle
 184          */
 185         u32 __iomem *ctrl_reg;
 186
 187 #define EXECLIST_MAX_PORTS 2
 188         /**
 189          * @active: the currently known context executing on HW
 190          */
 191         struct i915_request * const *active;
 192         /**
 193          * @inflight: the set of contexts submitted and acknowleged by HW
 194          *
 195          * The set of inflight contexts is managed by reading CS events
 196          * from the HW. On a context-switch event (not preemption), we
 197          * know the HW has transitioned from port0 to port1, and we
 198          * advance our inflight/active tracking accordingly.
 199          */
 200         struct i915_request *inflight[EXECLIST_MAX_PORTS + 1 /* sentinel */];
 201         /**
 202          * @pending: the next set of contexts submitted to ELSP
 203          *
 204          * We store the array of contexts that we submit to HW (via ELSP) and
 205          * promote them to the inflight array once HW has signaled the
 206          * preemption or idle-to-active event.
 207          */
 208         struct i915_request *pending[EXECLIST_MAX_PORTS + 1];
 209
 210         /**
 211          * @port_mask: number of execlist ports - 1
 212          */
 213         unsigned int port_mask;
 214
 215         /**
 216          * @switch_priority_hint: Second context priority.
 217          *
 218          * We submit multiple contexts to the HW simultaneously and would
 219          * like to occasionally switch between them to emulate timeslicing.
 220          * To know when timeslicing is suitable, we track the priority of
 221          * the context submitted second.
 222          */
 223         int switch_priority_hint;
 224
 225         /**
 226          * @queue_priority_hint: Highest pending priority.
 227          *
 228          * When we add requests into the queue, or adjust the priority of
 229          * executing requests, we compute the maximum priority of those
 230          * pending requests. We can then use this value to determine if
 231          * we need to preempt the executing requests to service the queue.
 232          * However, since the we may have recorded the priority of an inflight
 233          * request we wanted to preempt but since completed, at the time of
 234          * dequeuing the priority hint may no longer may match the highest
 235          * available request priority.
 236          */
 237         int queue_priority_hint;
 238
 239         /**
 240          * @queue: queue of requests, in priority lists
 241          */
 242         struct rb_root_cached queue;
 243         struct rb_root_cached virtual;
 244
 245         /**
 246          * @csb_write: control register for Context Switch buffer
 247          *
 248          * Note this register may be either mmio or HWSP shadow.
 249          */
 250         u32 *csb_write;
 251
 252         /**
 253          * @csb_status: status array for Context Switch buffer
 254          *
 255          * Note these register may be either mmio or HWSP shadow.
 256          */
 257         u32 *csb_status;
 258
 259         /**
 260          * @csb_size: context status buffer FIFO size
 261          */
 262         u8 csb_size;
 263
 264         /**
 265          * @csb_head: context status buffer head
 266          */
 267         u8 csb_head;
 268
 269         I915_SELFTEST_DECLARE(struct st_preempt_hang preempt_hang;)
 270 };
 271
 272 #define INTEL_ENGINE_CS_MAX_NAME 8
 273
 274 struct intel_engine_cs {
 275         struct drm_i915_private *i915;
 276         struct intel_gt *gt;
 277         struct intel_uncore *uncore;
 278         char name[INTEL_ENGINE_CS_MAX_NAME];
 279
 280         enum intel_engine_id id;
 281         enum intel_engine_id legacy_idx;
 282
 283         unsigned int hw_id;
 284         unsigned int guc_id;
 285
 286         intel_engine_mask_t mask;
 287
 288         u8 class;
 289         u8 instance;
 290
 291         u16 uabi_class;
 292         u16 uabi_instance;
 293
 294         u32 uabi_capabilities;
 295         u32 context_size;
 296         u32 mmio_base;
 297
 298         unsigned int context_tag;
 299 #define NUM_CONTEXT_TAG roundup_pow_of_two(2 * EXECLIST_MAX_PORTS)
 300
 301         struct rb_node uabi_node;
 302
 303         struct intel_sseu sseu;
 304
 305         struct {
 306                 spinlock_t lock;
 307                 struct list_head requests;
 308                 struct list_head hold; /* ready requests, but on hold */
 309         } active;
 310
 311         struct llist_head barrier_tasks;
 312
 313         struct intel_context *kernel_context; /* pinned */
 314
 315         intel_engine_mask_t saturated; /* submitting semaphores too late? */
 316
 317         struct {
 318                 struct delayed_work work;
 319                 struct i915_request *systole;
 320         } heartbeat;
 321
 322         unsigned long serial;
 323
 324         unsigned long wakeref_serial;
 325         struct intel_wakeref wakeref;
 326         struct drm_i915_gem_object *default_state;
 327         void *pinned_default_state;
 328
 329         struct {
 330                 struct intel_ring *ring;
 331                 struct intel_timeline *timeline;
 332         } legacy;
 333
 334         /*
 335          * We track the average duration of the idle pulse on parking the
 336          * engine to keep an estimate of the how the fast the engine is
 337          * under ideal conditions.
 338          */
 339         struct ewma__engine_latency latency;
 340
 341         /* Rather than have every client wait upon all user interrupts,
 342          * with the herd waking after every interrupt and each doing the
 343          * heavyweight seqno dance, we delegate the task (of being the
 344          * bottom-half of the user interrupt) to the first client. After
 345          * every interrupt, we wake up one client, who does the heavyweight
 346          * coherent seqno read and either goes back to sleep (if incomplete),
 347          * or wakes up all the completed clients in parallel, before then
 348          * transferring the bottom-half status to the next client in the queue.
 349          *
 350          * Compared to walking the entire list of waiters in a single dedicated
 351          * bottom-half, we reduce the latency of the first waiter by avoiding
 352          * a context switch, but incur additional coherent seqno reads when
 353          * following the chain of request breadcrumbs. Since it is most likely
 354          * that we have a single client waiting on each seqno, then reducing
 355          * the overhead of waking that client is much preferred.
 356          */
 357         struct intel_breadcrumbs {
 358                 spinlock_t irq_lock;
 359                 struct list_head signalers;
 360
 361                 struct irq_work irq_work; /* for use from inside irq_lock */
 362
 363                 unsigned int irq_enabled;
 364
 365                 bool irq_armed;
 366         } breadcrumbs;
 367
 368         struct intel_engine_pmu {
 369                 /**
 370                  * @enable: Bitmask of enable sample events on this engine.
 371                  *
 372                  * Bits correspond to sample event types, for instance
 373                  * I915_SAMPLE_QUEUED is bit 0 etc.
 374                  */
 375                 u32 enable;
 376                 /**
 377                  * @enable_count: Reference count for the enabled samplers.
 378                  *
 379                  * Index number corresponds to @enum drm_i915_pmu_engine_sample.
 380                  */
 381                 unsigned int enable_count[I915_ENGINE_SAMPLE_COUNT];
 382                 /**
 383                  * @sample: Counter values for sampling events.
 384                  *
 385                  * Our internal timer stores the current counters in this field.
 386                  *
 387                  * Index number corresponds to @enum drm_i915_pmu_engine_sample.
 388                  */
 389                 struct i915_pmu_sample sample[I915_ENGINE_SAMPLE_COUNT];
 390         } pmu;
 391
 392         /*
 393          * A pool of objects to use as shadow copies of client batch buffers
 394          * when the command parser is enabled. Prevents the client from
 395          * modifying the batch contents after software parsing.
 396          */
 397         struct intel_engine_pool pool;
 398
 399         struct intel_hw_status_page status_page;
 400         struct i915_ctx_workarounds wa_ctx;
 401         struct i915_wa_list ctx_wa_list;
 402         struct i915_wa_list wa_list;
 403         struct i915_wa_list whitelist;
 404
 405         u32             irq_keep_mask; /* always keep these interrupts */
 406         u32             irq_enable_mask; /* bitmask to enable ring interrupt */
 407         void            (*irq_enable)(struct intel_engine_cs *engine);
 408         void            (*irq_disable)(struct intel_engine_cs *engine);
 409
 410         int             (*resume)(struct intel_engine_cs *engine);
 411
 412         struct {
 413                 void (*prepare)(struct intel_engine_cs *engine);
 414
 415                 void (*rewind)(struct intel_engine_cs *engine, bool stalled);
 416                 void (*cancel)(struct intel_engine_cs *engine);
 417
 418                 void (*finish)(struct intel_engine_cs *engine);
 419         } reset;
 420
 421         void            (*park)(struct intel_engine_cs *engine);
 422         void            (*unpark)(struct intel_engine_cs *engine);
 423
 424         void            (*set_default_submission)(struct intel_engine_cs *engine);
 425
 426         const struct intel_context_ops *cops;
 427
 428         int             (*request_alloc)(struct i915_request *rq);
 429
 430         int             (*emit_flush)(struct i915_request *request, u32 mode);
 431 #define EMIT_INVALIDATE BIT(0)
 432 #define EMIT_FLUSH      BIT(1)
 433 #define EMIT_BARRIER    (EMIT_INVALIDATE | EMIT_FLUSH)
 434         int             (*emit_bb_start)(struct i915_request *rq,
 435                                          u64 offset, u32 length,
 436                                          unsigned int dispatch_flags);
 437 #define I915_DISPATCH_SECURE BIT(0)
 438 #define I915_DISPATCH_PINNED BIT(1)
 439         int              (*emit_init_breadcrumb)(struct i915_request *rq);
 440         u32             *(*emit_fini_breadcrumb)(struct i915_request *rq,
 441                                                  u32 *cs);
 442         unsigned int    emit_fini_breadcrumb_dw;
 443
 444         /* Pass the request to the hardware queue (e.g. directly into
 445          * the legacy ringbuffer or to the end of an execlist).
 446          *
 447          * This is called from an atomic context with irqs disabled; must
 448          * be irq safe.
 449          */
 450         void            (*submit_request)(struct i915_request *rq);
 451
 452         /*
 453          * Called on signaling of a SUBMIT_FENCE, passing along the signaling
 454          * request down to the bonded pairs.
 455          */
 456         void            (*bond_execute)(struct i915_request *rq,
 457                                         struct dma_fence *signal);
 458
 459         /*
 460          * Call when the priority on a request has changed and it and its
 461          * dependencies may need rescheduling. Note the request itself may
 462          * not be ready to run!
 463          */
 464         void            (*schedule)(struct i915_request *request,
 465                                     const struct i915_sched_attr *attr);
 466
 467         void            (*release)(struct intel_engine_cs *engine);
 468
 469         struct intel_engine_execlists execlists;
 470
 471         /*
 472          * Keep track of completed timelines on this engine for early
 473          * retirement with the goal of quickly enabling powersaving as
 474          * soon as the engine is idle.
 475          */
 476         struct intel_timeline *retire;
 477         struct work_struct retire_work;
 478
 479         /* status_notifier: list of callbacks for context-switch changes */
 480         struct atomic_notifier_head context_status_notifier;
 481
 482 #define I915_ENGINE_USING_CMD_PARSER BIT(0)
 483 #define I915_ENGINE_SUPPORTS_STATS   BIT(1)
 484 #define I915_ENGINE_HAS_PREEMPTION   BIT(2)
 485 #define I915_ENGINE_HAS_SEMAPHORES   BIT(3)
 486 #define I915_ENGINE_NEEDS_BREADCRUMB_TASKLET BIT(4)
 487 #define I915_ENGINE_IS_VIRTUAL       BIT(5)
 488 #define I915_ENGINE_HAS_RELATIVE_MMIO BIT(6)
 489 #define I915_ENGINE_REQUIRES_CMD_PARSER BIT(7)
 490         unsigned int flags;
 491
 492         /*
 493          * Table of commands the command parser needs to know about
 494          * for this engine.
 495          */
 496         DECLARE_HASHTABLE(cmd_hash, I915_CMD_HASH_ORDER);
 497
 498         /*
 499          * Table of registers allowed in commands that read/write registers.
 500          */
 501         const struct drm_i915_reg_table *reg_tables;
 502         int reg_table_count;
 503
 504         /*
 505          * Returns the bitmask for the length field of the specified command.
 506          * Return 0 for an unrecognized/invalid command.
 507          *
 508          * If the command parser finds an entry for a command in the engine's
 509          * cmd_tables, it gets the command's length based on the table entry.
 510          * If not, it calls this function to determine the per-engine length
 511          * field encoding for the command (i.e. different opcode ranges use
 512          * certain bits to encode the command length in the header).
 513          */
 514         u32 (*get_cmd_length_mask)(u32 cmd_header);
 515
 516         struct {
 517                 /**
 518                  * @lock: Lock protecting the below fields.
 519                  */
 520                 seqlock_t lock;
 521                 /**
 522                  * @enabled: Reference count indicating number of listeners.
 523                  */
 524                 unsigned int enabled;
 525                 /**
 526                  * @active: Number of contexts currently scheduled in.
 527                  */
 528                 unsigned int active;
 529                 /**
 530                  * @enabled_at: Timestamp when busy stats were enabled.
 531                  */
 532                 ktime_t enabled_at;
 533                 /**
 534                  * @start: Timestamp of the last idle to active transition.
 535                  *
 536                  * Idle is defined as active == 0, active is active > 0.
 537                  */
 538                 ktime_t start;
 539                 /**
 540                  * @total: Total time this engine was busy.
 541                  *
 542                  * Accumulated time not counting the most recent block in cases
 543                  * where engine is currently busy (active > 0).
 544                  */
 545                 ktime_t total;
 546         } stats;
 547
 548         struct {
 549                 unsigned long heartbeat_interval_ms;
 550                 unsigned long max_busywait_duration_ns;
 551                 unsigned long preempt_timeout_ms;
 552                 unsigned long stop_timeout_ms;
 553                 unsigned long timeslice_duration_ms;
 554         } props;
 555 };
 556
 557 static inline bool
 558 intel_engine_using_cmd_parser(const struct intel_engine_cs *engine)
 559 {
 560         return engine->flags & I915_ENGINE_USING_CMD_PARSER;
 561 }
 562
 563 static inline bool
 564 intel_engine_requires_cmd_parser(const struct intel_engine_cs *engine)
 565 {
 566         return engine->flags & I915_ENGINE_REQUIRES_CMD_PARSER;
 567 }
 568
 569 static inline bool
 570 intel_engine_supports_stats(const struct intel_engine_cs *engine)
 571 {
 572         return engine->flags & I915_ENGINE_SUPPORTS_STATS;
 573 }
 574
 575 static inline bool
 576 intel_engine_has_preemption(const struct intel_engine_cs *engine)
 577 {
 578         return engine->flags & I915_ENGINE_HAS_PREEMPTION;
 579 }
 580
 581 static inline bool
 582 intel_engine_has_semaphores(const struct intel_engine_cs *engine)
 583 {
 584         return engine->flags & I915_ENGINE_HAS_SEMAPHORES;
 585 }
 586
 587 static inline bool
 588 intel_engine_needs_breadcrumb_tasklet(const struct intel_engine_cs *engine)
 589 {
 590         return engine->flags & I915_ENGINE_NEEDS_BREADCRUMB_TASKLET;
 591 }
 592
 593 static inline bool
 594 intel_engine_is_virtual(const struct intel_engine_cs *engine)
 595 {
 596         return engine->flags & I915_ENGINE_IS_VIRTUAL;
 597 }
 598
 599 static inline bool
 600 intel_engine_has_relative_mmio(const struct intel_engine_cs * const engine)
 601 {
 602         return engine->flags & I915_ENGINE_HAS_RELATIVE_MMIO;
 603 }
 604
 605 #define instdone_has_slice(dev_priv___, sseu___, slice___) \
 606         ((IS_GEN(dev_priv___, 7) ? 1 : ((sseu___)->slice_mask)) & BIT(slice___))
 607
 608 #define instdone_has_subslice(dev_priv__, sseu__, slice__, subslice__) \
 609         (IS_GEN(dev_priv__, 7) ? (1 & BIT(subslice__)) : \
 610          intel_sseu_has_subslice(sseu__, 0, subslice__))
 611
 612 #define for_each_instdone_slice_subslice(dev_priv_, sseu_, slice_, subslice_) \
 613         for ((slice_) = 0, (subslice_) = 0; (slice_) < I915_MAX_SLICES; \
 614              (subslice_) = ((subslice_) + 1) % I915_MAX_SUBSLICES, \
 615              (slice_) += ((subslice_) == 0)) \
 616                 for_each_if((instdone_has_slice(dev_priv_, sseu_, slice_)) && \
 617                             (instdone_has_subslice(dev_priv_, sseu_, slice_, \
 618                                                     subslice_)))
 619 #endif /* __INTEL_ENGINE_TYPES_H__ */