2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Michel Thierry <michel.thierry@intel.com>
26 * Thomas Daniel <thomas.daniel@intel.com>
27 * Oscar Mateo <oscar.mateo@intel.com>
32 * DOC: Logical Rings, Logical Ring Contexts and Execlists
35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
36 * These expanded contexts enable a number of new abilities, especially
37 * "Execlists" (also implemented in this file).
39 * One of the main differences with the legacy HW contexts is that logical
40 * ring contexts incorporate many more things to the context's state, like
41 * PDPs or ringbuffer control registers:
43 * The reason why PDPs are included in the context is straightforward: as
44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
45 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
46 * instead, the GPU will do it for you on the context switch.
48 * But, what about the ringbuffer control registers (head, tail, etc..)?
49 * shouldn't we just need a set of those per engine command streamer? This is
50 * where the name "Logical Rings" starts to make sense: by virtualizing the
51 * rings, the engine cs shifts to a new "ring buffer" with every context
52 * switch. When you want to submit a workload to the GPU you: A) choose your
53 * context, B) find its appropriate virtualized ring, C) write commands to it
54 * and then, finally, D) tell the GPU to switch to that context.
56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
57 * to a contexts is via a context execution list, ergo "Execlists".
60 * Regarding the creation of contexts, we have:
62 * - One global default context.
63 * - One local default context for each opened fd.
64 * - One local extra context for each context create ioctl call.
66 * Now that ringbuffers belong per-context (and not per-engine, like before)
67 * and that contexts are uniquely tied to a given engine (and not reusable,
68 * like before) we need:
70 * - One ringbuffer per-engine inside each context.
71 * - One backing object per-engine inside each context.
73 * The global default context starts its life with these new objects fully
74 * allocated and populated. The local default context for each opened fd is
75 * more complex, because we don't know at creation time which engine is going
76 * to use them. To handle this, we have implemented a deferred creation of LR
79 * The local context starts its life as a hollow or blank holder, that only
80 * gets populated for a given engine once we receive an execbuffer. If later
81 * on we receive another execbuffer ioctl for the same context but a different
82 * engine, we allocate/populate a new ringbuffer and context backing object and
85 * Finally, regarding local contexts created using the ioctl call: as they are
86 * only allowed with the render ring, we can allocate & populate them right
87 * away (no need to defer anything, at least for now).
89 * Execlists implementation:
90 * Execlists are the new method by which, on gen8+ hardware, workloads are
91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
92 * This method works as follows:
94 * When a request is committed, its commands (the BB start and any leading or
95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
96 * for the appropriate context. The tail pointer in the hardware context is not
97 * updated at this time, but instead, kept by the driver in the ringbuffer
98 * structure. A structure representing this request is added to a request queue
99 * for the appropriate engine: this structure contains a copy of the context's
100 * tail after the request was written to the ring buffer and a pointer to the
103 * If the engine's request queue was empty before the request was added, the
104 * queue is processed immediately. Otherwise the queue will be processed during
105 * a context switch interrupt. In any case, elements on the queue will get sent
106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
107 * globally unique 20-bits submission ID.
109 * When execution of a request completes, the GPU updates the context status
110 * buffer with a context complete event and generates a context switch interrupt.
111 * During the interrupt handling, the driver examines the events in the buffer:
112 * for each context complete event, if the announced ID matches that on the head
113 * of the request queue, then that request is retired and removed from the queue.
115 * After processing, if any requests were retired and the queue is not empty
116 * then a new execution list can be submitted. The two requests at the front of
117 * the queue are next to be submitted but since a context may not occur twice in
118 * an execution list, if subsequent requests have the same ID as the first then
119 * the two requests must be combined. This is done simply by discarding requests
120 * at the head of the queue until either only one requests is left (in which case
121 * we use a NULL second context) or the first two requests have unique IDs.
123 * By always executing the first two requests in the queue the driver ensures
124 * that the GPU is kept as busy as possible. In the case where a single context
125 * completes but a second context is still executing, the request for this second
126 * context will be at the head of the queue when we remove the first one. This
127 * request will then be resubmitted along with a new request for a different context,
128 * which will cause the hardware to continue executing the second request and queue
129 * the new request (the GPU detects the condition of a context getting preempted
130 * with the same context and optimizes the context switch flow by not doing
131 * preemption, but just sampling the new tail pointer).
134 #include <linux/interrupt.h>
136 #include "i915_drv.h"
137 #include "i915_perf.h"
138 #include "i915_trace.h"
139 #include "i915_vgpu.h"
140 #include "intel_context.h"
141 #include "intel_engine_pm.h"
142 #include "intel_gt.h"
143 #include "intel_gt_pm.h"
144 #include "intel_gt_requests.h"
145 #include "intel_lrc_reg.h"
146 #include "intel_mocs.h"
147 #include "intel_reset.h"
148 #include "intel_ring.h"
149 #include "intel_workarounds.h"
151 #define RING_EXECLIST_QFULL (1 << 0x2)
152 #define RING_EXECLIST1_VALID (1 << 0x3)
153 #define RING_EXECLIST0_VALID (1 << 0x4)
154 #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE)
155 #define RING_EXECLIST1_ACTIVE (1 << 0x11)
156 #define RING_EXECLIST0_ACTIVE (1 << 0x12)
158 #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0)
159 #define GEN8_CTX_STATUS_PREEMPTED (1 << 1)
160 #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2)
161 #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3)
162 #define GEN8_CTX_STATUS_COMPLETE (1 << 4)
163 #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15)
165 #define GEN8_CTX_STATUS_COMPLETED_MASK \
166 (GEN8_CTX_STATUS_COMPLETE | GEN8_CTX_STATUS_PREEMPTED)
168 #define CTX_DESC_FORCE_RESTORE BIT_ULL(2)
170 #define GEN12_CTX_STATUS_SWITCHED_TO_NEW_QUEUE (0x1) /* lower csb dword */
171 #define GEN12_CTX_SWITCH_DETAIL(csb_dw) ((csb_dw) & 0xF) /* upper csb dword */
172 #define GEN12_CSB_SW_CTX_ID_MASK GENMASK(25, 15)
173 #define GEN12_IDLE_CTX_ID 0x7FF
174 #define GEN12_CSB_CTX_VALID(csb_dw) \
175 (FIELD_GET(GEN12_CSB_SW_CTX_ID_MASK, csb_dw) != GEN12_IDLE_CTX_ID)
177 /* Typical size of the average request (2 pipecontrols and a MI_BB) */
178 #define EXECLISTS_REQUEST_SIZE 64 /* bytes */
180 struct virtual_engine
{
181 struct intel_engine_cs base
;
182 struct intel_context context
;
185 * We allow only a single request through the virtual engine at a time
186 * (each request in the timeline waits for the completion fence of
187 * the previous before being submitted). By restricting ourselves to
188 * only submitting a single request, each request is placed on to a
189 * physical to maximise load spreading (by virtue of the late greedy
190 * scheduling -- each real engine takes the next available request
193 struct i915_request
*request
;
196 * We keep a rbtree of available virtual engines inside each physical
197 * engine, sorted by priority. Here we preallocate the nodes we need
198 * for the virtual engine, indexed by physical_engine->id.
203 } nodes
[I915_NUM_ENGINES
];
206 * Keep track of bonded pairs -- restrictions upon on our selection
207 * of physical engines any particular request may be submitted to.
208 * If we receive a submit-fence from a master engine, we will only
209 * use one of sibling_mask physical engines.
212 const struct intel_engine_cs
*master
;
213 intel_engine_mask_t sibling_mask
;
215 unsigned int num_bonds
;
217 /* And finally, which physical engines this virtual engine maps onto. */
218 unsigned int num_siblings
;
219 struct intel_engine_cs
*siblings
[0];
222 static struct virtual_engine
*to_virtual_engine(struct intel_engine_cs
*engine
)
224 GEM_BUG_ON(!intel_engine_is_virtual(engine
));
225 return container_of(engine
, struct virtual_engine
, base
);
228 static int __execlists_context_alloc(struct intel_context
*ce
,
229 struct intel_engine_cs
*engine
);
231 static void execlists_init_reg_state(u32
*reg_state
,
232 const struct intel_context
*ce
,
233 const struct intel_engine_cs
*engine
,
234 const struct intel_ring
*ring
,
237 __execlists_update_reg_state(const struct intel_context
*ce
,
238 const struct intel_engine_cs
*engine
,
241 static void mark_eio(struct i915_request
*rq
)
243 if (i915_request_completed(rq
))
246 GEM_BUG_ON(i915_request_signaled(rq
));
248 i915_request_set_error_once(rq
, -EIO
);
249 i915_request_mark_complete(rq
);
252 static struct i915_request
*
253 active_request(const struct intel_timeline
* const tl
, struct i915_request
*rq
)
255 struct i915_request
*active
= rq
;
258 list_for_each_entry_continue_reverse(rq
, &tl
->requests
, link
) {
259 if (i915_request_completed(rq
))
269 static inline u32
intel_hws_preempt_address(struct intel_engine_cs
*engine
)
271 return (i915_ggtt_offset(engine
->status_page
.vma
) +
272 I915_GEM_HWS_PREEMPT_ADDR
);
276 ring_set_paused(const struct intel_engine_cs
*engine
, int state
)
279 * We inspect HWS_PREEMPT with a semaphore inside
280 * engine->emit_fini_breadcrumb. If the dword is true,
281 * the ring is paused as the semaphore will busywait
282 * until the dword is false.
284 engine
->status_page
.addr
[I915_GEM_HWS_PREEMPT
] = state
;
289 static inline struct i915_priolist
*to_priolist(struct rb_node
*rb
)
291 return rb_entry(rb
, struct i915_priolist
, node
);
294 static inline int rq_prio(const struct i915_request
*rq
)
296 return READ_ONCE(rq
->sched
.attr
.priority
);
299 static int effective_prio(const struct i915_request
*rq
)
301 int prio
= rq_prio(rq
);
304 * If this request is special and must not be interrupted at any
305 * cost, so be it. Note we are only checking the most recent request
306 * in the context and so may be masking an earlier vip request. It
307 * is hoped that under the conditions where nopreempt is used, this
308 * will not matter (i.e. all requests to that context will be
309 * nopreempt for as long as desired).
311 if (i915_request_has_nopreempt(rq
))
312 prio
= I915_PRIORITY_UNPREEMPTABLE
;
315 * On unwinding the active request, we give it a priority bump
316 * if it has completed waiting on any semaphore. If we know that
317 * the request has already started, we can prevent an unwanted
318 * preempt-to-idle cycle by taking that into account now.
320 if (__i915_request_has_started(rq
))
321 prio
|= I915_PRIORITY_NOSEMAPHORE
;
323 /* Restrict mere WAIT boosts from triggering preemption */
324 BUILD_BUG_ON(__NO_PREEMPTION
& ~I915_PRIORITY_MASK
); /* only internal */
325 return prio
| __NO_PREEMPTION
;
328 static int queue_prio(const struct intel_engine_execlists
*execlists
)
330 struct i915_priolist
*p
;
333 rb
= rb_first_cached(&execlists
->queue
);
338 * As the priolist[] are inverted, with the highest priority in [0],
339 * we have to flip the index value to become priority.
342 return ((p
->priority
+ 1) << I915_USER_PRIORITY_SHIFT
) - ffs(p
->used
);
345 static inline bool need_preempt(const struct intel_engine_cs
*engine
,
346 const struct i915_request
*rq
,
351 if (!intel_engine_has_semaphores(engine
))
355 * Check if the current priority hint merits a preemption attempt.
357 * We record the highest value priority we saw during rescheduling
358 * prior to this dequeue, therefore we know that if it is strictly
359 * less than the current tail of ESLP[0], we do not need to force
360 * a preempt-to-idle cycle.
362 * However, the priority hint is a mere hint that we may need to
363 * preempt. If that hint is stale or we may be trying to preempt
364 * ourselves, ignore the request.
366 * More naturally we would write
367 * prio >= max(0, last);
368 * except that we wish to prevent triggering preemption at the same
369 * priority level: the task that is running should remain running
370 * to preserve FIFO ordering of dependencies.
372 last_prio
= max(effective_prio(rq
), I915_PRIORITY_NORMAL
- 1);
373 if (engine
->execlists
.queue_priority_hint
<= last_prio
)
377 * Check against the first request in ELSP[1], it will, thanks to the
378 * power of PI, be the highest priority of that context.
380 if (!list_is_last(&rq
->sched
.link
, &engine
->active
.requests
) &&
381 rq_prio(list_next_entry(rq
, sched
.link
)) > last_prio
)
385 struct virtual_engine
*ve
=
386 rb_entry(rb
, typeof(*ve
), nodes
[engine
->id
].rb
);
387 bool preempt
= false;
389 if (engine
== ve
->siblings
[0]) { /* only preempt one sibling */
390 struct i915_request
*next
;
393 next
= READ_ONCE(ve
->request
);
395 preempt
= rq_prio(next
) > last_prio
;
404 * If the inflight context did not trigger the preemption, then maybe
405 * it was the set of queued requests? Pick the highest priority in
406 * the queue (the first active priolist) and see if it deserves to be
407 * running instead of ELSP[0].
409 * The highest priority request in the queue can not be either
410 * ELSP[0] or ELSP[1] as, thanks again to PI, if it was the same
411 * context, it's priority would not exceed ELSP[0] aka last_prio.
413 return queue_prio(&engine
->execlists
) > last_prio
;
416 __maybe_unused
static inline bool
417 assert_priority_queue(const struct i915_request
*prev
,
418 const struct i915_request
*next
)
421 * Without preemption, the prev may refer to the still active element
422 * which we refuse to let go.
424 * Even with preemption, there are times when we think it is better not
425 * to preempt and leave an ostensibly lower priority request in flight.
427 if (i915_request_is_active(prev
))
430 return rq_prio(prev
) >= rq_prio(next
);
434 * The context descriptor encodes various attributes of a context,
435 * including its GTT address and some flags. Because it's fairly
436 * expensive to calculate, we'll just do it once and cache the result,
437 * which remains valid until the context is unpinned.
439 * This is what a descriptor looks like, from LSB to MSB::
441 * bits 0-11: flags, GEN8_CTX_* (cached in ctx->desc_template)
442 * bits 12-31: LRCA, GTT address of (the HWSP of) this context
443 * bits 32-52: ctx ID, a globally unique tag (highest bit used by GuC)
444 * bits 53-54: mbz, reserved for use by hardware
445 * bits 55-63: group ID, currently unused and set to 0
447 * Starting from Gen11, the upper dword of the descriptor has a new format:
449 * bits 32-36: reserved
450 * bits 37-47: SW context ID
451 * bits 48:53: engine instance
452 * bit 54: mbz, reserved for use by hardware
453 * bits 55-60: SW counter
454 * bits 61-63: engine class
456 * engine info, SW context ID and SW counter need to form a unique number
457 * (Context ID) per lrc.
460 lrc_descriptor(struct intel_context
*ce
, struct intel_engine_cs
*engine
)
464 desc
= INTEL_LEGACY_32B_CONTEXT
;
465 if (i915_vm_is_4lvl(ce
->vm
))
466 desc
= INTEL_LEGACY_64B_CONTEXT
;
467 desc
<<= GEN8_CTX_ADDRESSING_MODE_SHIFT
;
469 desc
|= GEN8_CTX_VALID
| GEN8_CTX_PRIVILEGE
;
470 if (IS_GEN(engine
->i915
, 8))
471 desc
|= GEN8_CTX_L3LLC_COHERENT
;
473 desc
|= i915_ggtt_offset(ce
->state
); /* bits 12-31 */
475 * The following 32bits are copied into the OA reports (dword 2).
476 * Consider updating oa_get_render_ctx_id in i915_perf.c when changing
479 if (INTEL_GEN(engine
->i915
) >= 11) {
480 desc
|= (u64
)engine
->instance
<< GEN11_ENGINE_INSTANCE_SHIFT
;
483 desc
|= (u64
)engine
->class << GEN11_ENGINE_CLASS_SHIFT
;
490 static inline unsigned int dword_in_page(void *addr
)
492 return offset_in_page(addr
) / sizeof(u32
);
495 static void set_offsets(u32
*regs
,
497 const struct intel_engine_cs
*engine
,
499 #define NOP(x) (BIT(7) | (x))
500 #define LRI(count, flags) ((flags) << 6 | (count) | BUILD_BUG_ON_ZERO(count >= BIT(6)))
501 #define POSTED BIT(0)
502 #define REG(x) (((x) >> 2) | BUILD_BUG_ON_ZERO(x >= 0x200))
504 (((x) >> 9) | BIT(7) | BUILD_BUG_ON_ZERO(x >= 0x10000)), \
506 #define END(x) 0, (x)
508 const u32 base
= engine
->mmio_base
;
513 if (*data
& BIT(7)) { /* skip */
514 count
= *data
++ & ~BIT(7);
516 memset32(regs
, MI_NOOP
, count
);
521 count
= *data
& 0x3f;
525 *regs
= MI_LOAD_REGISTER_IMM(count
);
527 *regs
|= MI_LRI_FORCE_POSTED
;
528 if (INTEL_GEN(engine
->i915
) >= 11)
529 *regs
|= MI_LRI_CS_MMIO
;
540 offset
|= v
& ~BIT(7);
541 } while (v
& BIT(7));
543 regs
[0] = base
+ (offset
<< 2);
553 /* Clear past the tail for HW access */
554 GEM_BUG_ON(dword_in_page(regs
) > count
);
555 memset32(regs
, MI_NOOP
, count
- dword_in_page(regs
));
557 /* Close the batch; used mainly by live_lrc_layout() */
558 *regs
= MI_BATCH_BUFFER_END
;
559 if (INTEL_GEN(engine
->i915
) >= 10)
564 static const u8 gen8_xcs_offsets
[] = {
599 static const u8 gen9_xcs_offsets
[] = {
683 static const u8 gen12_xcs_offsets
[] = {
715 static const u8 gen8_rcs_offsets
[] = {
752 static const u8 gen9_rcs_offsets
[] = {
836 static const u8 gen11_rcs_offsets
[] = {
877 static const u8 gen12_rcs_offsets
[] = {
924 static const u8
*reg_offsets(const struct intel_engine_cs
*engine
)
927 * The gen12+ lists only have the registers we program in the basic
928 * default state. We rely on the context image using relative
929 * addressing to automatic fixup the register state between the
930 * physical engines for virtual engine.
932 GEM_BUG_ON(INTEL_GEN(engine
->i915
) >= 12 &&
933 !intel_engine_has_relative_mmio(engine
));
935 if (engine
->class == RENDER_CLASS
) {
936 if (INTEL_GEN(engine
->i915
) >= 12)
937 return gen12_rcs_offsets
;
938 else if (INTEL_GEN(engine
->i915
) >= 11)
939 return gen11_rcs_offsets
;
940 else if (INTEL_GEN(engine
->i915
) >= 9)
941 return gen9_rcs_offsets
;
943 return gen8_rcs_offsets
;
945 if (INTEL_GEN(engine
->i915
) >= 12)
946 return gen12_xcs_offsets
;
947 else if (INTEL_GEN(engine
->i915
) >= 9)
948 return gen9_xcs_offsets
;
950 return gen8_xcs_offsets
;
954 static struct i915_request
*
955 __unwind_incomplete_requests(struct intel_engine_cs
*engine
)
957 struct i915_request
*rq
, *rn
, *active
= NULL
;
958 struct list_head
*uninitialized_var(pl
);
959 int prio
= I915_PRIORITY_INVALID
;
961 lockdep_assert_held(&engine
->active
.lock
);
963 list_for_each_entry_safe_reverse(rq
, rn
,
964 &engine
->active
.requests
,
966 if (i915_request_completed(rq
))
969 __i915_request_unsubmit(rq
);
972 * Push the request back into the queue for later resubmission.
973 * If this request is not native to this physical engine (i.e.
974 * it came from a virtual source), push it back onto the virtual
975 * engine so that it can be moved across onto another physical
976 * engine as load dictates.
978 if (likely(rq
->execution_mask
== engine
->mask
)) {
979 GEM_BUG_ON(rq_prio(rq
) == I915_PRIORITY_INVALID
);
980 if (rq_prio(rq
) != prio
) {
982 pl
= i915_sched_lookup_priolist(engine
, prio
);
984 GEM_BUG_ON(RB_EMPTY_ROOT(&engine
->execlists
.queue
.rb_root
));
986 list_move(&rq
->sched
.link
, pl
);
987 set_bit(I915_FENCE_FLAG_PQUEUE
, &rq
->fence
.flags
);
991 struct intel_engine_cs
*owner
= rq
->context
->engine
;
994 * Decouple the virtual breadcrumb before moving it
995 * back to the virtual engine -- we don't want the
996 * request to complete in the background and try
997 * and cancel the breadcrumb on the virtual engine
998 * (instead of the old engine where it is linked)!
1000 if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT
,
1001 &rq
->fence
.flags
)) {
1002 spin_lock_nested(&rq
->lock
,
1003 SINGLE_DEPTH_NESTING
);
1004 i915_request_cancel_breadcrumb(rq
);
1005 spin_unlock(&rq
->lock
);
1007 WRITE_ONCE(rq
->engine
, owner
);
1008 owner
->submit_request(rq
);
1016 struct i915_request
*
1017 execlists_unwind_incomplete_requests(struct intel_engine_execlists
*execlists
)
1019 struct intel_engine_cs
*engine
=
1020 container_of(execlists
, typeof(*engine
), execlists
);
1022 return __unwind_incomplete_requests(engine
);
1026 execlists_context_status_change(struct i915_request
*rq
, unsigned long status
)
1029 * Only used when GVT-g is enabled now. When GVT-g is disabled,
1030 * The compiler should eliminate this function as dead-code.
1032 if (!IS_ENABLED(CONFIG_DRM_I915_GVT
))
1035 atomic_notifier_call_chain(&rq
->engine
->context_status_notifier
,
1039 static void intel_engine_context_in(struct intel_engine_cs
*engine
)
1041 unsigned long flags
;
1043 if (READ_ONCE(engine
->stats
.enabled
) == 0)
1046 write_seqlock_irqsave(&engine
->stats
.lock
, flags
);
1048 if (engine
->stats
.enabled
> 0) {
1049 if (engine
->stats
.active
++ == 0)
1050 engine
->stats
.start
= ktime_get();
1051 GEM_BUG_ON(engine
->stats
.active
== 0);
1054 write_sequnlock_irqrestore(&engine
->stats
.lock
, flags
);
1057 static void intel_engine_context_out(struct intel_engine_cs
*engine
)
1059 unsigned long flags
;
1061 if (READ_ONCE(engine
->stats
.enabled
) == 0)
1064 write_seqlock_irqsave(&engine
->stats
.lock
, flags
);
1066 if (engine
->stats
.enabled
> 0) {
1069 if (engine
->stats
.active
&& --engine
->stats
.active
== 0) {
1071 * Decrement the active context count and in case GPU
1072 * is now idle add up to the running total.
1074 last
= ktime_sub(ktime_get(), engine
->stats
.start
);
1076 engine
->stats
.total
= ktime_add(engine
->stats
.total
,
1078 } else if (engine
->stats
.active
== 0) {
1080 * After turning on engine stats, context out might be
1081 * the first event in which case we account from the
1082 * time stats gathering was turned on.
1084 last
= ktime_sub(ktime_get(), engine
->stats
.enabled_at
);
1086 engine
->stats
.total
= ktime_add(engine
->stats
.total
,
1091 write_sequnlock_irqrestore(&engine
->stats
.lock
, flags
);
1094 static int lrc_ring_mi_mode(const struct intel_engine_cs
*engine
)
1096 if (INTEL_GEN(engine
->i915
) >= 12)
1098 else if (INTEL_GEN(engine
->i915
) >= 9)
1100 else if (engine
->class == RENDER_CLASS
)
1107 execlists_check_context(const struct intel_context
*ce
,
1108 const struct intel_engine_cs
*engine
)
1110 const struct intel_ring
*ring
= ce
->ring
;
1111 u32
*regs
= ce
->lrc_reg_state
;
1115 if (regs
[CTX_RING_START
] != i915_ggtt_offset(ring
->vma
)) {
1116 pr_err("%s: context submitted with incorrect RING_START [%08x], expected %08x\n",
1118 regs
[CTX_RING_START
],
1119 i915_ggtt_offset(ring
->vma
));
1120 regs
[CTX_RING_START
] = i915_ggtt_offset(ring
->vma
);
1124 if ((regs
[CTX_RING_CTL
] & ~(RING_WAIT
| RING_WAIT_SEMAPHORE
)) !=
1125 (RING_CTL_SIZE(ring
->size
) | RING_VALID
)) {
1126 pr_err("%s: context submitted with incorrect RING_CTL [%08x], expected %08x\n",
1129 (u32
)(RING_CTL_SIZE(ring
->size
) | RING_VALID
));
1130 regs
[CTX_RING_CTL
] = RING_CTL_SIZE(ring
->size
) | RING_VALID
;
1134 x
= lrc_ring_mi_mode(engine
);
1135 if (x
!= -1 && regs
[x
+ 1] & (regs
[x
+ 1] >> 16) & STOP_RING
) {
1136 pr_err("%s: context submitted with STOP_RING [%08x] in RING_MI_MODE\n",
1137 engine
->name
, regs
[x
+ 1]);
1138 regs
[x
+ 1] &= ~STOP_RING
;
1139 regs
[x
+ 1] |= STOP_RING
<< 16;
1143 WARN_ONCE(!valid
, "Invalid lrc state found before submission\n");
1146 static void restore_default_state(struct intel_context
*ce
,
1147 struct intel_engine_cs
*engine
)
1149 u32
*regs
= ce
->lrc_reg_state
;
1151 if (engine
->pinned_default_state
)
1152 memcpy(regs
, /* skip restoring the vanilla PPHWSP */
1153 engine
->pinned_default_state
+ LRC_STATE_PN
* PAGE_SIZE
,
1154 engine
->context_size
- PAGE_SIZE
);
1156 execlists_init_reg_state(regs
, ce
, engine
, ce
->ring
, false);
1159 static void reset_active(struct i915_request
*rq
,
1160 struct intel_engine_cs
*engine
)
1162 struct intel_context
* const ce
= rq
->context
;
1166 * The executing context has been cancelled. We want to prevent
1167 * further execution along this context and propagate the error on
1168 * to anything depending on its results.
1170 * In __i915_request_submit(), we apply the -EIO and remove the
1171 * requests' payloads for any banned requests. But first, we must
1172 * rewind the context back to the start of the incomplete request so
1173 * that we do not jump back into the middle of the batch.
1175 * We preserve the breadcrumbs and semaphores of the incomplete
1176 * requests so that inter-timeline dependencies (i.e other timelines)
1177 * remain correctly ordered. And we defer to __i915_request_submit()
1178 * so that all asynchronous waits are correctly handled.
1180 ENGINE_TRACE(engine
, "{ rq=%llx:%lld }\n",
1181 rq
->fence
.context
, rq
->fence
.seqno
);
1183 /* On resubmission of the active request, payload will be scrubbed */
1184 if (i915_request_completed(rq
))
1187 head
= active_request(ce
->timeline
, rq
)->head
;
1188 head
= intel_ring_wrap(ce
->ring
, head
);
1190 /* Scrub the context image to prevent replaying the previous batch */
1191 restore_default_state(ce
, engine
);
1192 __execlists_update_reg_state(ce
, engine
, head
);
1194 /* We've switched away, so this should be a no-op, but intent matters */
1195 ce
->lrc_desc
|= CTX_DESC_FORCE_RESTORE
;
1198 static u32
intel_context_get_runtime(const struct intel_context
*ce
)
1201 * We can use either ppHWSP[16] which is recorded before the context
1202 * switch (and so excludes the cost of context switches) or use the
1203 * value from the context image itself, which is saved/restored earlier
1204 * and so includes the cost of the save.
1206 return READ_ONCE(ce
->lrc_reg_state
[CTX_TIMESTAMP
]);
1209 static void st_update_runtime_underflow(struct intel_context
*ce
, s32 dt
)
1211 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1212 ce
->runtime
.num_underflow
+= dt
< 0;
1213 ce
->runtime
.max_underflow
= max_t(u32
, ce
->runtime
.max_underflow
, -dt
);
1217 static void intel_context_update_runtime(struct intel_context
*ce
)
1222 if (intel_context_is_barrier(ce
))
1225 old
= ce
->runtime
.last
;
1226 ce
->runtime
.last
= intel_context_get_runtime(ce
);
1227 dt
= ce
->runtime
.last
- old
;
1229 if (unlikely(dt
<= 0)) {
1230 CE_TRACE(ce
, "runtime underflow: last=%u, new=%u, delta=%d\n",
1231 old
, ce
->runtime
.last
, dt
);
1232 st_update_runtime_underflow(ce
, dt
);
1236 ewma_runtime_add(&ce
->runtime
.avg
, dt
);
1237 ce
->runtime
.total
+= dt
;
1240 static inline struct intel_engine_cs
*
1241 __execlists_schedule_in(struct i915_request
*rq
)
1243 struct intel_engine_cs
* const engine
= rq
->engine
;
1244 struct intel_context
* const ce
= rq
->context
;
1246 intel_context_get(ce
);
1248 if (unlikely(intel_context_is_banned(ce
)))
1249 reset_active(rq
, engine
);
1251 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM
))
1252 execlists_check_context(ce
, engine
);
1254 ce
->lrc_desc
&= ~GENMASK_ULL(47, 37);
1256 /* Use a fixed tag for OA and friends */
1257 ce
->lrc_desc
|= (u64
)ce
->tag
<< 32;
1259 /* We don't need a strict matching tag, just different values */
1261 (u64
)(++engine
->context_tag
% NUM_CONTEXT_TAG
) <<
1262 GEN11_SW_CTX_ID_SHIFT
;
1263 BUILD_BUG_ON(NUM_CONTEXT_TAG
> GEN12_MAX_CONTEXT_HW_ID
);
1266 __intel_gt_pm_get(engine
->gt
);
1267 execlists_context_status_change(rq
, INTEL_CONTEXT_SCHEDULE_IN
);
1268 intel_engine_context_in(engine
);
1273 static inline struct i915_request
*
1274 execlists_schedule_in(struct i915_request
*rq
, int idx
)
1276 struct intel_context
* const ce
= rq
->context
;
1277 struct intel_engine_cs
*old
;
1279 GEM_BUG_ON(!intel_engine_pm_is_awake(rq
->engine
));
1280 trace_i915_request_in(rq
, idx
);
1282 old
= READ_ONCE(ce
->inflight
);
1285 WRITE_ONCE(ce
->inflight
, __execlists_schedule_in(rq
));
1288 } while (!try_cmpxchg(&ce
->inflight
, &old
, ptr_inc(old
)));
1290 GEM_BUG_ON(intel_context_inflight(ce
) != rq
->engine
);
1291 return i915_request_get(rq
);
1294 static void kick_siblings(struct i915_request
*rq
, struct intel_context
*ce
)
1296 struct virtual_engine
*ve
= container_of(ce
, typeof(*ve
), context
);
1297 struct i915_request
*next
= READ_ONCE(ve
->request
);
1299 if (next
&& next
->execution_mask
& ~rq
->execution_mask
)
1300 tasklet_schedule(&ve
->base
.execlists
.tasklet
);
1304 __execlists_schedule_out(struct i915_request
*rq
,
1305 struct intel_engine_cs
* const engine
)
1307 struct intel_context
* const ce
= rq
->context
;
1310 * NB process_csb() is not under the engine->active.lock and hence
1311 * schedule_out can race with schedule_in meaning that we should
1312 * refrain from doing non-trivial work here.
1316 * If we have just completed this context, the engine may now be
1317 * idle and we want to re-enter powersaving.
1319 if (list_is_last_rcu(&rq
->link
, &ce
->timeline
->requests
) &&
1320 i915_request_completed(rq
))
1321 intel_engine_add_retire(engine
, ce
->timeline
);
1323 intel_context_update_runtime(ce
);
1324 intel_engine_context_out(engine
);
1325 execlists_context_status_change(rq
, INTEL_CONTEXT_SCHEDULE_OUT
);
1326 intel_gt_pm_put_async(engine
->gt
);
1329 * If this is part of a virtual engine, its next request may
1330 * have been blocked waiting for access to the active context.
1331 * We have to kick all the siblings again in case we need to
1332 * switch (e.g. the next request is not runnable on this
1333 * engine). Hopefully, we will already have submitted the next
1334 * request before the tasklet runs and do not need to rebuild
1335 * each virtual tree and kick everyone again.
1337 if (ce
->engine
!= engine
)
1338 kick_siblings(rq
, ce
);
1340 intel_context_put(ce
);
1344 execlists_schedule_out(struct i915_request
*rq
)
1346 struct intel_context
* const ce
= rq
->context
;
1347 struct intel_engine_cs
*cur
, *old
;
1349 trace_i915_request_out(rq
);
1351 old
= READ_ONCE(ce
->inflight
);
1353 cur
= ptr_unmask_bits(old
, 2) ? ptr_dec(old
) : NULL
;
1354 while (!try_cmpxchg(&ce
->inflight
, &old
, cur
));
1356 __execlists_schedule_out(rq
, old
);
1358 i915_request_put(rq
);
1361 static u64
execlists_update_context(struct i915_request
*rq
)
1363 struct intel_context
*ce
= rq
->context
;
1364 u64 desc
= ce
->lrc_desc
;
1368 * WaIdleLiteRestore:bdw,skl
1370 * We should never submit the context with the same RING_TAIL twice
1371 * just in case we submit an empty ring, which confuses the HW.
1373 * We append a couple of NOOPs (gen8_emit_wa_tail) after the end of
1374 * the normal request to be able to always advance the RING_TAIL on
1375 * subsequent resubmissions (for lite restore). Should that fail us,
1376 * and we try and submit the same tail again, force the context
1379 * If we need to return to a preempted context, we need to skip the
1380 * lite-restore and force it to reload the RING_TAIL. Otherwise, the
1381 * HW has a tendency to ignore us rewinding the TAIL to the end of
1382 * an earlier request.
1384 tail
= intel_ring_set_tail(rq
->ring
, rq
->tail
);
1385 prev
= ce
->lrc_reg_state
[CTX_RING_TAIL
];
1386 if (unlikely(intel_ring_direction(rq
->ring
, tail
, prev
) <= 0))
1387 desc
|= CTX_DESC_FORCE_RESTORE
;
1388 ce
->lrc_reg_state
[CTX_RING_TAIL
] = tail
;
1389 rq
->tail
= rq
->wa_tail
;
1392 * Make sure the context image is complete before we submit it to HW.
1394 * Ostensibly, writes (including the WCB) should be flushed prior to
1395 * an uncached write such as our mmio register access, the empirical
1396 * evidence (esp. on Braswell) suggests that the WC write into memory
1397 * may not be visible to the HW prior to the completion of the UC
1398 * register write and that we may begin execution from the context
1399 * before its image is complete leading to invalid PD chasing.
1403 ce
->lrc_desc
&= ~CTX_DESC_FORCE_RESTORE
;
1407 static inline void write_desc(struct intel_engine_execlists
*execlists
, u64 desc
, u32 port
)
1409 if (execlists
->ctrl_reg
) {
1410 writel(lower_32_bits(desc
), execlists
->submit_reg
+ port
* 2);
1411 writel(upper_32_bits(desc
), execlists
->submit_reg
+ port
* 2 + 1);
1413 writel(upper_32_bits(desc
), execlists
->submit_reg
);
1414 writel(lower_32_bits(desc
), execlists
->submit_reg
);
1418 static __maybe_unused
void
1419 trace_ports(const struct intel_engine_execlists
*execlists
,
1421 struct i915_request
* const *ports
)
1423 const struct intel_engine_cs
*engine
=
1424 container_of(execlists
, typeof(*engine
), execlists
);
1429 ENGINE_TRACE(engine
, "%s { %llx:%lld%s, %llx:%lld }\n", msg
,
1430 ports
[0]->fence
.context
,
1431 ports
[0]->fence
.seqno
,
1432 i915_request_completed(ports
[0]) ? "!" :
1433 i915_request_started(ports
[0]) ? "*" :
1435 ports
[1] ? ports
[1]->fence
.context
: 0,
1436 ports
[1] ? ports
[1]->fence
.seqno
: 0);
1440 reset_in_progress(const struct intel_engine_execlists
*execlists
)
1442 return unlikely(!__tasklet_is_enabled(&execlists
->tasklet
));
1445 static __maybe_unused
bool
1446 assert_pending_valid(const struct intel_engine_execlists
*execlists
,
1449 struct i915_request
* const *port
, *rq
;
1450 struct intel_context
*ce
= NULL
;
1451 bool sentinel
= false;
1453 trace_ports(execlists
, msg
, execlists
->pending
);
1455 /* We may be messing around with the lists during reset, lalala */
1456 if (reset_in_progress(execlists
))
1459 if (!execlists
->pending
[0]) {
1460 GEM_TRACE_ERR("Nothing pending for promotion!\n");
1464 if (execlists
->pending
[execlists_num_ports(execlists
)]) {
1465 GEM_TRACE_ERR("Excess pending[%d] for promotion!\n",
1466 execlists_num_ports(execlists
));
1470 for (port
= execlists
->pending
; (rq
= *port
); port
++) {
1471 unsigned long flags
;
1474 GEM_BUG_ON(!kref_read(&rq
->fence
.refcount
));
1475 GEM_BUG_ON(!i915_request_is_active(rq
));
1477 if (ce
== rq
->context
) {
1478 GEM_TRACE_ERR("Dup context:%llx in pending[%zd]\n",
1479 ce
->timeline
->fence_context
,
1480 port
- execlists
->pending
);
1486 * Sentinels are supposed to be lonely so they flush the
1487 * current exection off the HW. Check that they are the
1488 * only request in the pending submission.
1491 GEM_TRACE_ERR("context:%llx after sentinel in pending[%zd]\n",
1492 ce
->timeline
->fence_context
,
1493 port
- execlists
->pending
);
1497 sentinel
= i915_request_has_sentinel(rq
);
1498 if (sentinel
&& port
!= execlists
->pending
) {
1499 GEM_TRACE_ERR("sentinel context:%llx not in prime position[%zd]\n",
1500 ce
->timeline
->fence_context
,
1501 port
- execlists
->pending
);
1505 /* Hold tightly onto the lock to prevent concurrent retires! */
1506 if (!spin_trylock_irqsave(&rq
->lock
, flags
))
1509 if (i915_request_completed(rq
))
1512 if (i915_active_is_idle(&ce
->active
) &&
1513 !intel_context_is_barrier(ce
)) {
1514 GEM_TRACE_ERR("Inactive context:%llx in pending[%zd]\n",
1515 ce
->timeline
->fence_context
,
1516 port
- execlists
->pending
);
1521 if (!i915_vma_is_pinned(ce
->state
)) {
1522 GEM_TRACE_ERR("Unpinned context:%llx in pending[%zd]\n",
1523 ce
->timeline
->fence_context
,
1524 port
- execlists
->pending
);
1529 if (!i915_vma_is_pinned(ce
->ring
->vma
)) {
1530 GEM_TRACE_ERR("Unpinned ring:%llx in pending[%zd]\n",
1531 ce
->timeline
->fence_context
,
1532 port
- execlists
->pending
);
1538 spin_unlock_irqrestore(&rq
->lock
, flags
);
1546 static void execlists_submit_ports(struct intel_engine_cs
*engine
)
1548 struct intel_engine_execlists
*execlists
= &engine
->execlists
;
1551 GEM_BUG_ON(!assert_pending_valid(execlists
, "submit"));
1554 * We can skip acquiring intel_runtime_pm_get() here as it was taken
1555 * on our behalf by the request (see i915_gem_mark_busy()) and it will
1556 * not be relinquished until the device is idle (see
1557 * i915_gem_idle_work_handler()). As a precaution, we make sure
1558 * that all ELSP are drained i.e. we have processed the CSB,
1559 * before allowing ourselves to idle and calling intel_runtime_pm_put().
1561 GEM_BUG_ON(!intel_engine_pm_is_awake(engine
));
1564 * ELSQ note: the submit queue is not cleared after being submitted
1565 * to the HW so we need to make sure we always clean it up. This is
1566 * currently ensured by the fact that we always write the same number
1567 * of elsq entries, keep this in mind before changing the loop below.
1569 for (n
= execlists_num_ports(execlists
); n
--; ) {
1570 struct i915_request
*rq
= execlists
->pending
[n
];
1572 write_desc(execlists
,
1573 rq
? execlists_update_context(rq
) : 0,
1577 /* we need to manually load the submit queue */
1578 if (execlists
->ctrl_reg
)
1579 writel(EL_CTRL_LOAD
, execlists
->ctrl_reg
);
1582 static bool ctx_single_port_submission(const struct intel_context
*ce
)
1584 return (IS_ENABLED(CONFIG_DRM_I915_GVT
) &&
1585 intel_context_force_single_submission(ce
));
1588 static bool can_merge_ctx(const struct intel_context
*prev
,
1589 const struct intel_context
*next
)
1594 if (ctx_single_port_submission(prev
))
1600 static unsigned long i915_request_flags(const struct i915_request
*rq
)
1602 return READ_ONCE(rq
->fence
.flags
);
1605 static bool can_merge_rq(const struct i915_request
*prev
,
1606 const struct i915_request
*next
)
1608 GEM_BUG_ON(prev
== next
);
1609 GEM_BUG_ON(!assert_priority_queue(prev
, next
));
1612 * We do not submit known completed requests. Therefore if the next
1613 * request is already completed, we can pretend to merge it in
1614 * with the previous context (and we will skip updating the ELSP
1615 * and tracking). Thus hopefully keeping the ELSP full with active
1616 * contexts, despite the best efforts of preempt-to-busy to confuse
1619 if (i915_request_completed(next
))
1622 if (unlikely((i915_request_flags(prev
) ^ i915_request_flags(next
)) &
1623 (BIT(I915_FENCE_FLAG_NOPREEMPT
) |
1624 BIT(I915_FENCE_FLAG_SENTINEL
))))
1627 if (!can_merge_ctx(prev
->context
, next
->context
))
1630 GEM_BUG_ON(i915_seqno_passed(prev
->fence
.seqno
, next
->fence
.seqno
));
1634 static void virtual_update_register_offsets(u32
*regs
,
1635 struct intel_engine_cs
*engine
)
1637 set_offsets(regs
, reg_offsets(engine
), engine
, false);
1640 static bool virtual_matches(const struct virtual_engine
*ve
,
1641 const struct i915_request
*rq
,
1642 const struct intel_engine_cs
*engine
)
1644 const struct intel_engine_cs
*inflight
;
1646 if (!(rq
->execution_mask
& engine
->mask
)) /* We peeked too soon! */
1650 * We track when the HW has completed saving the context image
1651 * (i.e. when we have seen the final CS event switching out of
1652 * the context) and must not overwrite the context image before
1653 * then. This restricts us to only using the active engine
1654 * while the previous virtualized request is inflight (so
1655 * we reuse the register offsets). This is a very small
1656 * hystersis on the greedy seelction algorithm.
1658 inflight
= intel_context_inflight(&ve
->context
);
1659 if (inflight
&& inflight
!= engine
)
1665 static void virtual_xfer_breadcrumbs(struct virtual_engine
*ve
,
1666 struct i915_request
*rq
)
1668 struct intel_engine_cs
*old
= ve
->siblings
[0];
1670 /* All unattached (rq->engine == old) must already be completed */
1672 spin_lock(&old
->breadcrumbs
.irq_lock
);
1673 if (!list_empty(&ve
->context
.signal_link
)) {
1674 list_del_init(&ve
->context
.signal_link
);
1677 * We cannot acquire the new engine->breadcrumbs.irq_lock
1678 * (as we are holding a breadcrumbs.irq_lock already),
1679 * so attach this request to the signaler on submission.
1680 * The queued irq_work will occur when we finally drop
1681 * the engine->active.lock after dequeue.
1683 set_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT
, &rq
->fence
.flags
);
1685 /* Also transfer the pending irq_work for the old breadcrumb. */
1686 intel_engine_signal_breadcrumbs(rq
->engine
);
1688 spin_unlock(&old
->breadcrumbs
.irq_lock
);
1691 #define for_each_waiter(p__, rq__) \
1692 list_for_each_entry_lockless(p__, \
1693 &(rq__)->sched.waiters_list, \
1696 #define for_each_signaler(p__, rq__) \
1697 list_for_each_entry_rcu(p__, \
1698 &(rq__)->sched.signalers_list, \
1701 static void defer_request(struct i915_request
*rq
, struct list_head
* const pl
)
1706 * We want to move the interrupted request to the back of
1707 * the round-robin list (i.e. its priority level), but
1708 * in doing so, we must then move all requests that were in
1709 * flight and were waiting for the interrupted request to
1710 * be run after it again.
1713 struct i915_dependency
*p
;
1715 GEM_BUG_ON(i915_request_is_active(rq
));
1716 list_move_tail(&rq
->sched
.link
, pl
);
1718 for_each_waiter(p
, rq
) {
1719 struct i915_request
*w
=
1720 container_of(p
->waiter
, typeof(*w
), sched
);
1722 /* Leave semaphores spinning on the other engines */
1723 if (w
->engine
!= rq
->engine
)
1726 /* No waiter should start before its signaler */
1727 GEM_BUG_ON(i915_request_started(w
) &&
1728 !i915_request_completed(rq
));
1730 GEM_BUG_ON(i915_request_is_active(w
));
1731 if (!i915_request_is_ready(w
))
1734 if (rq_prio(w
) < rq_prio(rq
))
1737 GEM_BUG_ON(rq_prio(w
) > rq_prio(rq
));
1738 list_move_tail(&w
->sched
.link
, &list
);
1741 rq
= list_first_entry_or_null(&list
, typeof(*rq
), sched
.link
);
1745 static void defer_active(struct intel_engine_cs
*engine
)
1747 struct i915_request
*rq
;
1749 rq
= __unwind_incomplete_requests(engine
);
1753 defer_request(rq
, i915_sched_lookup_priolist(engine
, rq_prio(rq
)));
1757 need_timeslice(struct intel_engine_cs
*engine
, const struct i915_request
*rq
)
1761 if (!intel_engine_has_timeslices(engine
))
1764 hint
= engine
->execlists
.queue_priority_hint
;
1765 if (!list_is_last(&rq
->sched
.link
, &engine
->active
.requests
))
1766 hint
= max(hint
, rq_prio(list_next_entry(rq
, sched
.link
)));
1768 return hint
>= effective_prio(rq
);
1772 switch_prio(struct intel_engine_cs
*engine
, const struct i915_request
*rq
)
1774 if (list_is_last(&rq
->sched
.link
, &engine
->active
.requests
))
1777 return rq_prio(list_next_entry(rq
, sched
.link
));
1780 static inline unsigned long
1781 timeslice(const struct intel_engine_cs
*engine
)
1783 return READ_ONCE(engine
->props
.timeslice_duration_ms
);
1786 static unsigned long
1787 active_timeslice(const struct intel_engine_cs
*engine
)
1789 const struct intel_engine_execlists
*execlists
= &engine
->execlists
;
1790 const struct i915_request
*rq
= *execlists
->active
;
1792 if (!rq
|| i915_request_completed(rq
))
1795 if (READ_ONCE(execlists
->switch_priority_hint
) < effective_prio(rq
))
1798 return timeslice(engine
);
1801 static void set_timeslice(struct intel_engine_cs
*engine
)
1803 if (!intel_engine_has_timeslices(engine
))
1806 set_timer_ms(&engine
->execlists
.timer
, active_timeslice(engine
));
1809 static void start_timeslice(struct intel_engine_cs
*engine
)
1811 struct intel_engine_execlists
*execlists
= &engine
->execlists
;
1812 int prio
= queue_prio(execlists
);
1814 WRITE_ONCE(execlists
->switch_priority_hint
, prio
);
1815 if (prio
== INT_MIN
)
1818 if (timer_pending(&execlists
->timer
))
1821 set_timer_ms(&execlists
->timer
, timeslice(engine
));
1824 static void record_preemption(struct intel_engine_execlists
*execlists
)
1826 (void)I915_SELFTEST_ONLY(execlists
->preempt_hang
.count
++);
1829 static unsigned long active_preempt_timeout(struct intel_engine_cs
*engine
,
1830 const struct i915_request
*rq
)
1835 /* Force a fast reset for terminated contexts (ignoring sysfs!) */
1836 if (unlikely(intel_context_is_banned(rq
->context
)))
1839 return READ_ONCE(engine
->props
.preempt_timeout_ms
);
1842 static void set_preempt_timeout(struct intel_engine_cs
*engine
,
1843 const struct i915_request
*rq
)
1845 if (!intel_engine_has_preempt_reset(engine
))
1848 set_timer_ms(&engine
->execlists
.preempt
,
1849 active_preempt_timeout(engine
, rq
));
1852 static inline void clear_ports(struct i915_request
**ports
, int count
)
1854 memset_p((void **)ports
, NULL
, count
);
1857 static void execlists_dequeue(struct intel_engine_cs
*engine
)
1859 struct intel_engine_execlists
* const execlists
= &engine
->execlists
;
1860 struct i915_request
**port
= execlists
->pending
;
1861 struct i915_request
** const last_port
= port
+ execlists
->port_mask
;
1862 struct i915_request
* const *active
;
1863 struct i915_request
*last
;
1865 bool submit
= false;
1868 * Hardware submission is through 2 ports. Conceptually each port
1869 * has a (RING_START, RING_HEAD, RING_TAIL) tuple. RING_START is
1870 * static for a context, and unique to each, so we only execute
1871 * requests belonging to a single context from each ring. RING_HEAD
1872 * is maintained by the CS in the context image, it marks the place
1873 * where it got up to last time, and through RING_TAIL we tell the CS
1874 * where we want to execute up to this time.
1876 * In this list the requests are in order of execution. Consecutive
1877 * requests from the same context are adjacent in the ringbuffer. We
1878 * can combine these requests into a single RING_TAIL update:
1880 * RING_HEAD...req1...req2
1882 * since to execute req2 the CS must first execute req1.
1884 * Our goal then is to point each port to the end of a consecutive
1885 * sequence of requests as being the most optimal (fewest wake ups
1886 * and context switches) submission.
1889 for (rb
= rb_first_cached(&execlists
->virtual); rb
; ) {
1890 struct virtual_engine
*ve
=
1891 rb_entry(rb
, typeof(*ve
), nodes
[engine
->id
].rb
);
1892 struct i915_request
*rq
= READ_ONCE(ve
->request
);
1894 if (!rq
) { /* lazily cleanup after another engine handled rq */
1895 rb_erase_cached(rb
, &execlists
->virtual);
1897 rb
= rb_first_cached(&execlists
->virtual);
1901 if (!virtual_matches(ve
, rq
, engine
)) {
1910 * If the queue is higher priority than the last
1911 * request in the currently active context, submit afresh.
1912 * We will resubmit again afterwards in case we need to split
1913 * the active context to interject the preemption request,
1914 * i.e. we will retrigger preemption following the ack in case
1917 active
= READ_ONCE(execlists
->active
);
1918 while ((last
= *active
) && i915_request_completed(last
))
1922 if (need_preempt(engine
, last
, rb
)) {
1923 ENGINE_TRACE(engine
,
1924 "preempting last=%llx:%lld, prio=%d, hint=%d\n",
1925 last
->fence
.context
,
1927 last
->sched
.attr
.priority
,
1928 execlists
->queue_priority_hint
);
1929 record_preemption(execlists
);
1932 * Don't let the RING_HEAD advance past the breadcrumb
1933 * as we unwind (and until we resubmit) so that we do
1934 * not accidentally tell it to go backwards.
1936 ring_set_paused(engine
, 1);
1939 * Note that we have not stopped the GPU at this point,
1940 * so we are unwinding the incomplete requests as they
1941 * remain inflight and so by the time we do complete
1942 * the preemption, some of the unwound requests may
1945 __unwind_incomplete_requests(engine
);
1948 } else if (need_timeslice(engine
, last
) &&
1949 timer_expired(&engine
->execlists
.timer
)) {
1950 ENGINE_TRACE(engine
,
1951 "expired last=%llx:%lld, prio=%d, hint=%d\n",
1952 last
->fence
.context
,
1954 last
->sched
.attr
.priority
,
1955 execlists
->queue_priority_hint
);
1957 ring_set_paused(engine
, 1);
1958 defer_active(engine
);
1961 * Unlike for preemption, if we rewind and continue
1962 * executing the same context as previously active,
1963 * the order of execution will remain the same and
1964 * the tail will only advance. We do not need to
1965 * force a full context restore, as a lite-restore
1966 * is sufficient to resample the monotonic TAIL.
1968 * If we switch to any other context, similarly we
1969 * will not rewind TAIL of current context, and
1970 * normal save/restore will preserve state and allow
1971 * us to later continue executing the same request.
1976 * Otherwise if we already have a request pending
1977 * for execution after the current one, we can
1978 * just wait until the next CS event before
1979 * queuing more. In either case we will force a
1980 * lite-restore preemption event, but if we wait
1981 * we hopefully coalesce several updates into a single
1984 if (!list_is_last(&last
->sched
.link
,
1985 &engine
->active
.requests
)) {
1987 * Even if ELSP[1] is occupied and not worthy
1988 * of timeslices, our queue might be.
1990 start_timeslice(engine
);
1996 while (rb
) { /* XXX virtual is always taking precedence */
1997 struct virtual_engine
*ve
=
1998 rb_entry(rb
, typeof(*ve
), nodes
[engine
->id
].rb
);
1999 struct i915_request
*rq
;
2001 spin_lock(&ve
->base
.active
.lock
);
2004 if (unlikely(!rq
)) { /* lost the race to a sibling */
2005 spin_unlock(&ve
->base
.active
.lock
);
2006 rb_erase_cached(rb
, &execlists
->virtual);
2008 rb
= rb_first_cached(&execlists
->virtual);
2012 GEM_BUG_ON(rq
!= ve
->request
);
2013 GEM_BUG_ON(rq
->engine
!= &ve
->base
);
2014 GEM_BUG_ON(rq
->context
!= &ve
->context
);
2016 if (rq_prio(rq
) >= queue_prio(execlists
)) {
2017 if (!virtual_matches(ve
, rq
, engine
)) {
2018 spin_unlock(&ve
->base
.active
.lock
);
2023 if (last
&& !can_merge_rq(last
, rq
)) {
2024 spin_unlock(&ve
->base
.active
.lock
);
2025 start_timeslice(engine
);
2026 return; /* leave this for another sibling */
2029 ENGINE_TRACE(engine
,
2030 "virtual rq=%llx:%lld%s, new engine? %s\n",
2033 i915_request_completed(rq
) ? "!" :
2034 i915_request_started(rq
) ? "*" :
2036 yesno(engine
!= ve
->siblings
[0]));
2038 WRITE_ONCE(ve
->request
, NULL
);
2039 WRITE_ONCE(ve
->base
.execlists
.queue_priority_hint
,
2041 rb_erase_cached(rb
, &execlists
->virtual);
2044 GEM_BUG_ON(!(rq
->execution_mask
& engine
->mask
));
2045 WRITE_ONCE(rq
->engine
, engine
);
2047 if (engine
!= ve
->siblings
[0]) {
2048 u32
*regs
= ve
->context
.lrc_reg_state
;
2051 GEM_BUG_ON(READ_ONCE(ve
->context
.inflight
));
2053 if (!intel_engine_has_relative_mmio(engine
))
2054 virtual_update_register_offsets(regs
,
2057 if (!list_empty(&ve
->context
.signals
))
2058 virtual_xfer_breadcrumbs(ve
, rq
);
2061 * Move the bound engine to the top of the list
2062 * for future execution. We then kick this
2063 * tasklet first before checking others, so that
2064 * we preferentially reuse this set of bound
2067 for (n
= 1; n
< ve
->num_siblings
; n
++) {
2068 if (ve
->siblings
[n
] == engine
) {
2069 swap(ve
->siblings
[n
],
2075 GEM_BUG_ON(ve
->siblings
[0] != engine
);
2078 if (__i915_request_submit(rq
)) {
2082 i915_request_put(rq
);
2085 * Hmm, we have a bunch of virtual engine requests,
2086 * but the first one was already completed (thanks
2087 * preempt-to-busy!). Keep looking at the veng queue
2088 * until we have no more relevant requests (i.e.
2089 * the normal submit queue has higher priority).
2092 spin_unlock(&ve
->base
.active
.lock
);
2093 rb
= rb_first_cached(&execlists
->virtual);
2098 spin_unlock(&ve
->base
.active
.lock
);
2102 while ((rb
= rb_first_cached(&execlists
->queue
))) {
2103 struct i915_priolist
*p
= to_priolist(rb
);
2104 struct i915_request
*rq
, *rn
;
2107 priolist_for_each_request_consume(rq
, rn
, p
, i
) {
2111 * Can we combine this request with the current port?
2112 * It has to be the same context/ringbuffer and not
2113 * have any exceptions (e.g. GVT saying never to
2114 * combine contexts).
2116 * If we can combine the requests, we can execute both
2117 * by updating the RING_TAIL to point to the end of the
2118 * second request, and so we never need to tell the
2119 * hardware about the first.
2121 if (last
&& !can_merge_rq(last
, rq
)) {
2123 * If we are on the second port and cannot
2124 * combine this request with the last, then we
2127 if (port
== last_port
)
2131 * We must not populate both ELSP[] with the
2132 * same LRCA, i.e. we must submit 2 different
2133 * contexts if we submit 2 ELSP.
2135 if (last
->context
== rq
->context
)
2138 if (i915_request_has_sentinel(last
))
2142 * If GVT overrides us we only ever submit
2143 * port[0], leaving port[1] empty. Note that we
2144 * also have to be careful that we don't queue
2145 * the same context (even though a different
2146 * request) to the second port.
2148 if (ctx_single_port_submission(last
->context
) ||
2149 ctx_single_port_submission(rq
->context
))
2155 if (__i915_request_submit(rq
)) {
2157 *port
= execlists_schedule_in(last
, port
- execlists
->pending
);
2163 !can_merge_ctx(last
->context
,
2166 i915_seqno_passed(last
->fence
.seqno
,
2174 rb_erase_cached(&p
->node
, &execlists
->queue
);
2175 i915_priolist_free(p
);
2180 * Here be a bit of magic! Or sleight-of-hand, whichever you prefer.
2182 * We choose the priority hint such that if we add a request of greater
2183 * priority than this, we kick the submission tasklet to decide on
2184 * the right order of submitting the requests to hardware. We must
2185 * also be prepared to reorder requests as they are in-flight on the
2186 * HW. We derive the priority hint then as the first "hole" in
2187 * the HW submission ports and if there are no available slots,
2188 * the priority of the lowest executing request, i.e. last.
2190 * When we do receive a higher priority request ready to run from the
2191 * user, see queue_request(), the priority hint is bumped to that
2192 * request triggering preemption on the next dequeue (or subsequent
2193 * interrupt for secondary ports).
2195 execlists
->queue_priority_hint
= queue_prio(execlists
);
2198 *port
= execlists_schedule_in(last
, port
- execlists
->pending
);
2199 execlists
->switch_priority_hint
=
2200 switch_prio(engine
, *execlists
->pending
);
2203 * Skip if we ended up with exactly the same set of requests,
2204 * e.g. trying to timeslice a pair of ordered contexts
2206 if (!memcmp(active
, execlists
->pending
,
2207 (port
- execlists
->pending
+ 1) * sizeof(*port
))) {
2209 execlists_schedule_out(fetch_and_zero(port
));
2210 while (port
-- != execlists
->pending
);
2214 clear_ports(port
+ 1, last_port
- port
);
2216 execlists_submit_ports(engine
);
2217 set_preempt_timeout(engine
, *active
);
2220 ring_set_paused(engine
, 0);
2225 cancel_port_requests(struct intel_engine_execlists
* const execlists
)
2227 struct i915_request
* const *port
;
2229 for (port
= execlists
->pending
; *port
; port
++)
2230 execlists_schedule_out(*port
);
2231 clear_ports(execlists
->pending
, ARRAY_SIZE(execlists
->pending
));
2233 /* Mark the end of active before we overwrite *active */
2234 for (port
= xchg(&execlists
->active
, execlists
->pending
); *port
; port
++)
2235 execlists_schedule_out(*port
);
2236 clear_ports(execlists
->inflight
, ARRAY_SIZE(execlists
->inflight
));
2238 smp_wmb(); /* complete the seqlock for execlists_active() */
2239 WRITE_ONCE(execlists
->active
, execlists
->inflight
);
2243 invalidate_csb_entries(const u32
*first
, const u32
*last
)
2245 clflush((void *)first
);
2246 clflush((void *)last
);
2250 * Starting with Gen12, the status has a new format:
2252 * bit 0: switched to new queue
2254 * bit 2: semaphore wait mode (poll or signal), only valid when
2255 * switch detail is set to "wait on semaphore"
2256 * bits 3-5: engine class
2257 * bits 6-11: engine instance
2258 * bits 12-14: reserved
2259 * bits 15-25: sw context id of the lrc the GT switched to
2260 * bits 26-31: sw counter of the lrc the GT switched to
2261 * bits 32-35: context switch detail
2263 * - 1: wait on sync flip
2264 * - 2: wait on vblank
2265 * - 3: wait on scanline
2266 * - 4: wait on semaphore
2267 * - 5: context preempted (not on SEMAPHORE_WAIT or
2270 * bits 37-43: wait detail (for switch detail 1 to 4)
2271 * bits 44-46: reserved
2272 * bits 47-57: sw context id of the lrc the GT switched away from
2273 * bits 58-63: sw counter of the lrc the GT switched away from
2276 gen12_csb_parse(const struct intel_engine_execlists
*execlists
, const u32
*csb
)
2278 u32 lower_dw
= csb
[0];
2279 u32 upper_dw
= csb
[1];
2280 bool ctx_to_valid
= GEN12_CSB_CTX_VALID(lower_dw
);
2281 bool ctx_away_valid
= GEN12_CSB_CTX_VALID(upper_dw
);
2282 bool new_queue
= lower_dw
& GEN12_CTX_STATUS_SWITCHED_TO_NEW_QUEUE
;
2285 * The context switch detail is not guaranteed to be 5 when a preemption
2286 * occurs, so we can't just check for that. The check below works for
2287 * all the cases we care about, including preemptions of WAIT
2288 * instructions and lite-restore. Preempt-to-idle via the CTRL register
2289 * would require some extra handling, but we don't support that.
2291 if (!ctx_away_valid
|| new_queue
) {
2292 GEM_BUG_ON(!ctx_to_valid
);
2297 * switch detail = 5 is covered by the case above and we do not expect a
2298 * context switch on an unsuccessful wait instruction since we always
2301 GEM_BUG_ON(GEN12_CTX_SWITCH_DETAIL(upper_dw
));
2306 gen8_csb_parse(const struct intel_engine_execlists
*execlists
, const u32
*csb
)
2308 return *csb
& (GEN8_CTX_STATUS_IDLE_ACTIVE
| GEN8_CTX_STATUS_PREEMPTED
);
2311 static void process_csb(struct intel_engine_cs
*engine
)
2313 struct intel_engine_execlists
* const execlists
= &engine
->execlists
;
2314 const u32
* const buf
= execlists
->csb_status
;
2315 const u8 num_entries
= execlists
->csb_size
;
2319 * As we modify our execlists state tracking we require exclusive
2320 * access. Either we are inside the tasklet, or the tasklet is disabled
2321 * and we assume that is only inside the reset paths and so serialised.
2323 GEM_BUG_ON(!tasklet_is_locked(&execlists
->tasklet
) &&
2324 !reset_in_progress(execlists
));
2325 GEM_BUG_ON(!intel_engine_in_execlists_submission_mode(engine
));
2328 * Note that csb_write, csb_status may be either in HWSP or mmio.
2329 * When reading from the csb_write mmio register, we have to be
2330 * careful to only use the GEN8_CSB_WRITE_PTR portion, which is
2331 * the low 4bits. As it happens we know the next 4bits are always
2332 * zero and so we can simply masked off the low u8 of the register
2333 * and treat it identically to reading from the HWSP (without having
2334 * to use explicit shifting and masking, and probably bifurcating
2335 * the code to handle the legacy mmio read).
2337 head
= execlists
->csb_head
;
2338 tail
= READ_ONCE(*execlists
->csb_write
);
2339 if (unlikely(head
== tail
))
2343 * Hopefully paired with a wmb() in HW!
2345 * We must complete the read of the write pointer before any reads
2346 * from the CSB, so that we do not see stale values. Without an rmb
2347 * (lfence) the HW may speculatively perform the CSB[] reads *before*
2348 * we perform the READ_ONCE(*csb_write).
2352 ENGINE_TRACE(engine
, "cs-irq head=%d, tail=%d\n", head
, tail
);
2356 if (++head
== num_entries
)
2360 * We are flying near dragons again.
2362 * We hold a reference to the request in execlist_port[]
2363 * but no more than that. We are operating in softirq
2364 * context and so cannot hold any mutex or sleep. That
2365 * prevents us stopping the requests we are processing
2366 * in port[] from being retired simultaneously (the
2367 * breadcrumb will be complete before we see the
2368 * context-switch). As we only hold the reference to the
2369 * request, any pointer chasing underneath the request
2370 * is subject to a potential use-after-free. Thus we
2371 * store all of the bookkeeping within port[] as
2372 * required, and avoid using unguarded pointers beneath
2373 * request itself. The same applies to the atomic
2377 ENGINE_TRACE(engine
, "csb[%d]: status=0x%08x:0x%08x\n",
2378 head
, buf
[2 * head
+ 0], buf
[2 * head
+ 1]);
2380 if (INTEL_GEN(engine
->i915
) >= 12)
2381 promote
= gen12_csb_parse(execlists
, buf
+ 2 * head
);
2383 promote
= gen8_csb_parse(execlists
, buf
+ 2 * head
);
2385 struct i915_request
* const *old
= execlists
->active
;
2387 GEM_BUG_ON(!assert_pending_valid(execlists
, "promote"));
2389 ring_set_paused(engine
, 0);
2391 /* Point active to the new ELSP; prevent overwriting */
2392 WRITE_ONCE(execlists
->active
, execlists
->pending
);
2393 smp_wmb(); /* notify execlists_active() */
2395 /* cancel old inflight, prepare for switch */
2396 trace_ports(execlists
, "preempted", old
);
2398 execlists_schedule_out(*old
++);
2400 /* switch pending to inflight */
2401 memcpy(execlists
->inflight
,
2403 execlists_num_ports(execlists
) *
2404 sizeof(*execlists
->pending
));
2405 smp_wmb(); /* complete the seqlock */
2406 WRITE_ONCE(execlists
->active
, execlists
->inflight
);
2408 WRITE_ONCE(execlists
->pending
[0], NULL
);
2410 GEM_BUG_ON(!*execlists
->active
);
2412 /* port0 completed, advanced to port1 */
2413 trace_ports(execlists
, "completed", execlists
->active
);
2416 * We rely on the hardware being strongly
2417 * ordered, that the breadcrumb write is
2418 * coherent (visible from the CPU) before the
2419 * user interrupt and CSB is processed.
2421 if (GEM_SHOW_DEBUG() &&
2422 !i915_request_completed(*execlists
->active
) &&
2423 !reset_in_progress(execlists
)) {
2424 struct i915_request
*rq __maybe_unused
=
2426 const u32
*regs __maybe_unused
=
2427 rq
->context
->lrc_reg_state
;
2429 ENGINE_TRACE(engine
,
2430 "ring:{start:0x%08x, head:%04x, tail:%04x, ctl:%08x, mode:%08x}\n",
2431 ENGINE_READ(engine
, RING_START
),
2432 ENGINE_READ(engine
, RING_HEAD
) & HEAD_ADDR
,
2433 ENGINE_READ(engine
, RING_TAIL
) & TAIL_ADDR
,
2434 ENGINE_READ(engine
, RING_CTL
),
2435 ENGINE_READ(engine
, RING_MI_MODE
));
2436 ENGINE_TRACE(engine
,
2437 "rq:{start:%08x, head:%04x, tail:%04x, seqno:%llx:%d, hwsp:%d}, ",
2438 i915_ggtt_offset(rq
->ring
->vma
),
2441 lower_32_bits(rq
->fence
.seqno
),
2443 ENGINE_TRACE(engine
,
2444 "ctx:{start:%08x, head:%04x, tail:%04x}, ",
2445 regs
[CTX_RING_START
],
2446 regs
[CTX_RING_HEAD
],
2447 regs
[CTX_RING_TAIL
]);
2449 GEM_BUG_ON("context completed before request");
2452 execlists_schedule_out(*execlists
->active
++);
2454 GEM_BUG_ON(execlists
->active
- execlists
->inflight
>
2455 execlists_num_ports(execlists
));
2457 } while (head
!= tail
);
2459 execlists
->csb_head
= head
;
2460 set_timeslice(engine
);
2463 * Gen11 has proven to fail wrt global observation point between
2464 * entry and tail update, failing on the ordering and thus
2465 * we see an old entry in the context status buffer.
2467 * Forcibly evict out entries for the next gpu csb update,
2468 * to increase the odds that we get a fresh entries with non
2469 * working hardware. The cost for doing so comes out mostly with
2470 * the wash as hardware, working or not, will need to do the
2471 * invalidation before.
2473 invalidate_csb_entries(&buf
[0], &buf
[num_entries
- 1]);
2476 static void __execlists_submission_tasklet(struct intel_engine_cs
*const engine
)
2478 lockdep_assert_held(&engine
->active
.lock
);
2479 if (!READ_ONCE(engine
->execlists
.pending
[0])) {
2480 rcu_read_lock(); /* protect peeking at execlists->active */
2481 execlists_dequeue(engine
);
2486 static void __execlists_hold(struct i915_request
*rq
)
2491 struct i915_dependency
*p
;
2493 if (i915_request_is_active(rq
))
2494 __i915_request_unsubmit(rq
);
2496 clear_bit(I915_FENCE_FLAG_PQUEUE
, &rq
->fence
.flags
);
2497 list_move_tail(&rq
->sched
.link
, &rq
->engine
->active
.hold
);
2498 i915_request_set_hold(rq
);
2499 RQ_TRACE(rq
, "on hold\n");
2501 for_each_waiter(p
, rq
) {
2502 struct i915_request
*w
=
2503 container_of(p
->waiter
, typeof(*w
), sched
);
2505 /* Leave semaphores spinning on the other engines */
2506 if (w
->engine
!= rq
->engine
)
2509 if (!i915_request_is_ready(w
))
2512 if (i915_request_completed(w
))
2515 if (i915_request_on_hold(w
))
2518 list_move_tail(&w
->sched
.link
, &list
);
2521 rq
= list_first_entry_or_null(&list
, typeof(*rq
), sched
.link
);
2525 static bool execlists_hold(struct intel_engine_cs
*engine
,
2526 struct i915_request
*rq
)
2528 spin_lock_irq(&engine
->active
.lock
);
2530 if (i915_request_completed(rq
)) { /* too late! */
2535 if (rq
->engine
!= engine
) { /* preempted virtual engine */
2536 struct virtual_engine
*ve
= to_virtual_engine(rq
->engine
);
2539 * intel_context_inflight() is only protected by virtue
2540 * of process_csb() being called only by the tasklet (or
2541 * directly from inside reset while the tasklet is suspended).
2542 * Assert that neither of those are allowed to run while we
2543 * poke at the request queues.
2545 GEM_BUG_ON(!reset_in_progress(&engine
->execlists
));
2548 * An unsubmitted request along a virtual engine will
2549 * remain on the active (this) engine until we are able
2550 * to process the context switch away (and so mark the
2551 * context as no longer in flight). That cannot have happened
2552 * yet, otherwise we would not be hanging!
2554 spin_lock(&ve
->base
.active
.lock
);
2555 GEM_BUG_ON(intel_context_inflight(rq
->context
) != engine
);
2556 GEM_BUG_ON(ve
->request
!= rq
);
2558 spin_unlock(&ve
->base
.active
.lock
);
2559 i915_request_put(rq
);
2561 rq
->engine
= engine
;
2565 * Transfer this request onto the hold queue to prevent it
2566 * being resumbitted to HW (and potentially completed) before we have
2567 * released it. Since we may have already submitted following
2568 * requests, we need to remove those as well.
2570 GEM_BUG_ON(i915_request_on_hold(rq
));
2571 GEM_BUG_ON(rq
->engine
!= engine
);
2572 __execlists_hold(rq
);
2573 GEM_BUG_ON(list_empty(&engine
->active
.hold
));
2576 spin_unlock_irq(&engine
->active
.lock
);
2580 static bool hold_request(const struct i915_request
*rq
)
2582 struct i915_dependency
*p
;
2583 bool result
= false;
2586 * If one of our ancestors is on hold, we must also be on hold,
2587 * otherwise we will bypass it and execute before it.
2590 for_each_signaler(p
, rq
) {
2591 const struct i915_request
*s
=
2592 container_of(p
->signaler
, typeof(*s
), sched
);
2594 if (s
->engine
!= rq
->engine
)
2597 result
= i915_request_on_hold(s
);
2606 static void __execlists_unhold(struct i915_request
*rq
)
2611 struct i915_dependency
*p
;
2613 RQ_TRACE(rq
, "hold release\n");
2615 GEM_BUG_ON(!i915_request_on_hold(rq
));
2616 GEM_BUG_ON(!i915_sw_fence_signaled(&rq
->submit
));
2618 i915_request_clear_hold(rq
);
2619 list_move_tail(&rq
->sched
.link
,
2620 i915_sched_lookup_priolist(rq
->engine
,
2622 set_bit(I915_FENCE_FLAG_PQUEUE
, &rq
->fence
.flags
);
2624 /* Also release any children on this engine that are ready */
2625 for_each_waiter(p
, rq
) {
2626 struct i915_request
*w
=
2627 container_of(p
->waiter
, typeof(*w
), sched
);
2629 /* Propagate any change in error status */
2630 if (rq
->fence
.error
)
2631 i915_request_set_error_once(w
, rq
->fence
.error
);
2633 if (w
->engine
!= rq
->engine
)
2636 if (!i915_request_on_hold(w
))
2639 /* Check that no other parents are also on hold */
2640 if (hold_request(w
))
2643 list_move_tail(&w
->sched
.link
, &list
);
2646 rq
= list_first_entry_or_null(&list
, typeof(*rq
), sched
.link
);
2650 static void execlists_unhold(struct intel_engine_cs
*engine
,
2651 struct i915_request
*rq
)
2653 spin_lock_irq(&engine
->active
.lock
);
2656 * Move this request back to the priority queue, and all of its
2657 * children and grandchildren that were suspended along with it.
2659 __execlists_unhold(rq
);
2661 if (rq_prio(rq
) > engine
->execlists
.queue_priority_hint
) {
2662 engine
->execlists
.queue_priority_hint
= rq_prio(rq
);
2663 tasklet_hi_schedule(&engine
->execlists
.tasklet
);
2666 spin_unlock_irq(&engine
->active
.lock
);
2669 struct execlists_capture
{
2670 struct work_struct work
;
2671 struct i915_request
*rq
;
2672 struct i915_gpu_coredump
*error
;
2675 static void execlists_capture_work(struct work_struct
*work
)
2677 struct execlists_capture
*cap
= container_of(work
, typeof(*cap
), work
);
2678 const gfp_t gfp
= GFP_KERNEL
| __GFP_RETRY_MAYFAIL
| __GFP_NOWARN
;
2679 struct intel_engine_cs
*engine
= cap
->rq
->engine
;
2680 struct intel_gt_coredump
*gt
= cap
->error
->gt
;
2681 struct intel_engine_capture_vma
*vma
;
2683 /* Compress all the objects attached to the request, slow! */
2684 vma
= intel_engine_coredump_add_request(gt
->engine
, cap
->rq
, gfp
);
2686 struct i915_vma_compress
*compress
=
2687 i915_vma_capture_prepare(gt
);
2689 intel_engine_coredump_add_vma(gt
->engine
, vma
, compress
);
2690 i915_vma_capture_finish(gt
, compress
);
2693 gt
->simulated
= gt
->engine
->simulated
;
2694 cap
->error
->simulated
= gt
->simulated
;
2696 /* Publish the error state, and announce it to the world */
2697 i915_error_state_store(cap
->error
);
2698 i915_gpu_coredump_put(cap
->error
);
2700 /* Return this request and all that depend upon it for signaling */
2701 execlists_unhold(engine
, cap
->rq
);
2702 i915_request_put(cap
->rq
);
2707 static struct execlists_capture
*capture_regs(struct intel_engine_cs
*engine
)
2709 const gfp_t gfp
= GFP_ATOMIC
| __GFP_NOWARN
;
2710 struct execlists_capture
*cap
;
2712 cap
= kmalloc(sizeof(*cap
), gfp
);
2716 cap
->error
= i915_gpu_coredump_alloc(engine
->i915
, gfp
);
2720 cap
->error
->gt
= intel_gt_coredump_alloc(engine
->gt
, gfp
);
2721 if (!cap
->error
->gt
)
2724 cap
->error
->gt
->engine
= intel_engine_coredump_alloc(engine
, gfp
);
2725 if (!cap
->error
->gt
->engine
)
2731 kfree(cap
->error
->gt
);
2739 static bool execlists_capture(struct intel_engine_cs
*engine
)
2741 struct execlists_capture
*cap
;
2743 if (!IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR
))
2747 * We need to _quickly_ capture the engine state before we reset.
2748 * We are inside an atomic section (softirq) here and we are delaying
2749 * the forced preemption event.
2751 cap
= capture_regs(engine
);
2755 spin_lock_irq(&engine
->active
.lock
);
2756 cap
->rq
= execlists_active(&engine
->execlists
);
2758 cap
->rq
= active_request(cap
->rq
->context
->timeline
, cap
->rq
);
2759 cap
->rq
= i915_request_get_rcu(cap
->rq
);
2761 spin_unlock_irq(&engine
->active
.lock
);
2766 * Remove the request from the execlists queue, and take ownership
2767 * of the request. We pass it to our worker who will _slowly_ compress
2768 * all the pages the _user_ requested for debugging their batch, after
2769 * which we return it to the queue for signaling.
2771 * By removing them from the execlists queue, we also remove the
2772 * requests from being processed by __unwind_incomplete_requests()
2773 * during the intel_engine_reset(), and so they will *not* be replayed
2776 * Note that because we have not yet reset the engine at this point,
2777 * it is possible for the request that we have identified as being
2778 * guilty, did in fact complete and we will then hit an arbitration
2779 * point allowing the outstanding preemption to succeed. The likelihood
2780 * of that is very low (as capturing of the engine registers should be
2781 * fast enough to run inside an irq-off atomic section!), so we will
2782 * simply hold that request accountable for being non-preemptible
2783 * long enough to force the reset.
2785 if (!execlists_hold(engine
, cap
->rq
))
2788 INIT_WORK(&cap
->work
, execlists_capture_work
);
2789 schedule_work(&cap
->work
);
2793 i915_request_put(cap
->rq
);
2795 i915_gpu_coredump_put(cap
->error
);
2800 static void execlists_reset(struct intel_engine_cs
*engine
, const char *msg
)
2802 const unsigned int bit
= I915_RESET_ENGINE
+ engine
->id
;
2803 unsigned long *lock
= &engine
->gt
->reset
.flags
;
2805 if (!intel_has_reset_engine(engine
->gt
))
2808 if (test_and_set_bit(bit
, lock
))
2811 ENGINE_TRACE(engine
, "reset for %s\n", msg
);
2813 /* Mark this tasklet as disabled to avoid waiting for it to complete */
2814 tasklet_disable_nosync(&engine
->execlists
.tasklet
);
2816 ring_set_paused(engine
, 1); /* Freeze the current request in place */
2817 if (execlists_capture(engine
))
2818 intel_engine_reset(engine
, msg
);
2820 ring_set_paused(engine
, 0);
2822 tasklet_enable(&engine
->execlists
.tasklet
);
2823 clear_and_wake_up_bit(bit
, lock
);
2826 static bool preempt_timeout(const struct intel_engine_cs
*const engine
)
2828 const struct timer_list
*t
= &engine
->execlists
.preempt
;
2830 if (!CONFIG_DRM_I915_PREEMPT_TIMEOUT
)
2833 if (!timer_expired(t
))
2836 return READ_ONCE(engine
->execlists
.pending
[0]);
2840 * Check the unread Context Status Buffers and manage the submission of new
2841 * contexts to the ELSP accordingly.
2843 static void execlists_submission_tasklet(unsigned long data
)
2845 struct intel_engine_cs
* const engine
= (struct intel_engine_cs
*)data
;
2846 bool timeout
= preempt_timeout(engine
);
2848 process_csb(engine
);
2850 if (unlikely(READ_ONCE(engine
->execlists
.error_interrupt
))) {
2851 engine
->execlists
.error_interrupt
= 0;
2852 if (ENGINE_READ(engine
, RING_ESR
)) /* confirm the error */
2853 execlists_reset(engine
, "CS error");
2856 if (!READ_ONCE(engine
->execlists
.pending
[0]) || timeout
) {
2857 unsigned long flags
;
2859 spin_lock_irqsave(&engine
->active
.lock
, flags
);
2860 __execlists_submission_tasklet(engine
);
2861 spin_unlock_irqrestore(&engine
->active
.lock
, flags
);
2863 /* Recheck after serialising with direct-submission */
2864 if (unlikely(timeout
&& preempt_timeout(engine
)))
2865 execlists_reset(engine
, "preemption time out");
2869 static void __execlists_kick(struct intel_engine_execlists
*execlists
)
2871 /* Kick the tasklet for some interrupt coalescing and reset handling */
2872 tasklet_hi_schedule(&execlists
->tasklet
);
2875 #define execlists_kick(t, member) \
2876 __execlists_kick(container_of(t, struct intel_engine_execlists, member))
2878 static void execlists_timeslice(struct timer_list
*timer
)
2880 execlists_kick(timer
, timer
);
2883 static void execlists_preempt(struct timer_list
*timer
)
2885 execlists_kick(timer
, preempt
);
2888 static void queue_request(struct intel_engine_cs
*engine
,
2889 struct i915_request
*rq
)
2891 GEM_BUG_ON(!list_empty(&rq
->sched
.link
));
2892 list_add_tail(&rq
->sched
.link
,
2893 i915_sched_lookup_priolist(engine
, rq_prio(rq
)));
2894 set_bit(I915_FENCE_FLAG_PQUEUE
, &rq
->fence
.flags
);
2897 static void __submit_queue_imm(struct intel_engine_cs
*engine
)
2899 struct intel_engine_execlists
* const execlists
= &engine
->execlists
;
2901 if (reset_in_progress(execlists
))
2902 return; /* defer until we restart the engine following reset */
2904 if (execlists
->tasklet
.func
== execlists_submission_tasklet
)
2905 __execlists_submission_tasklet(engine
);
2907 tasklet_hi_schedule(&execlists
->tasklet
);
2910 static void submit_queue(struct intel_engine_cs
*engine
,
2911 const struct i915_request
*rq
)
2913 struct intel_engine_execlists
*execlists
= &engine
->execlists
;
2915 if (rq_prio(rq
) <= execlists
->queue_priority_hint
)
2918 execlists
->queue_priority_hint
= rq_prio(rq
);
2919 __submit_queue_imm(engine
);
2922 static bool ancestor_on_hold(const struct intel_engine_cs
*engine
,
2923 const struct i915_request
*rq
)
2925 GEM_BUG_ON(i915_request_on_hold(rq
));
2926 return !list_empty(&engine
->active
.hold
) && hold_request(rq
);
2929 static void execlists_submit_request(struct i915_request
*request
)
2931 struct intel_engine_cs
*engine
= request
->engine
;
2932 unsigned long flags
;
2934 /* Will be called from irq-context when using foreign fences. */
2935 spin_lock_irqsave(&engine
->active
.lock
, flags
);
2937 if (unlikely(ancestor_on_hold(engine
, request
))) {
2938 RQ_TRACE(request
, "ancestor on hold\n");
2939 list_add_tail(&request
->sched
.link
, &engine
->active
.hold
);
2940 i915_request_set_hold(request
);
2942 queue_request(engine
, request
);
2944 GEM_BUG_ON(RB_EMPTY_ROOT(&engine
->execlists
.queue
.rb_root
));
2945 GEM_BUG_ON(list_empty(&request
->sched
.link
));
2947 submit_queue(engine
, request
);
2950 spin_unlock_irqrestore(&engine
->active
.lock
, flags
);
2953 static void __execlists_context_fini(struct intel_context
*ce
)
2955 intel_ring_put(ce
->ring
);
2956 i915_vma_put(ce
->state
);
2959 static void execlists_context_destroy(struct kref
*kref
)
2961 struct intel_context
*ce
= container_of(kref
, typeof(*ce
), ref
);
2963 GEM_BUG_ON(!i915_active_is_idle(&ce
->active
));
2964 GEM_BUG_ON(intel_context_is_pinned(ce
));
2967 __execlists_context_fini(ce
);
2969 intel_context_fini(ce
);
2970 intel_context_free(ce
);
2974 set_redzone(void *vaddr
, const struct intel_engine_cs
*engine
)
2976 if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM
))
2979 vaddr
+= engine
->context_size
;
2981 memset(vaddr
, CONTEXT_REDZONE
, I915_GTT_PAGE_SIZE
);
2985 check_redzone(const void *vaddr
, const struct intel_engine_cs
*engine
)
2987 if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM
))
2990 vaddr
+= engine
->context_size
;
2992 if (memchr_inv(vaddr
, CONTEXT_REDZONE
, I915_GTT_PAGE_SIZE
))
2993 dev_err_once(engine
->i915
->drm
.dev
,
2994 "%s context redzone overwritten!\n",
2998 static void execlists_context_unpin(struct intel_context
*ce
)
3000 check_redzone((void *)ce
->lrc_reg_state
- LRC_STATE_PN
* PAGE_SIZE
,
3003 i915_gem_object_unpin_map(ce
->state
->obj
);
3007 __execlists_update_reg_state(const struct intel_context
*ce
,
3008 const struct intel_engine_cs
*engine
,
3011 struct intel_ring
*ring
= ce
->ring
;
3012 u32
*regs
= ce
->lrc_reg_state
;
3014 GEM_BUG_ON(!intel_ring_offset_valid(ring
, head
));
3015 GEM_BUG_ON(!intel_ring_offset_valid(ring
, ring
->tail
));
3017 regs
[CTX_RING_START
] = i915_ggtt_offset(ring
->vma
);
3018 regs
[CTX_RING_HEAD
] = head
;
3019 regs
[CTX_RING_TAIL
] = ring
->tail
;
3020 regs
[CTX_RING_CTL
] = RING_CTL_SIZE(ring
->size
) | RING_VALID
;
3023 if (engine
->class == RENDER_CLASS
) {
3024 regs
[CTX_R_PWR_CLK_STATE
] =
3025 intel_sseu_make_rpcs(engine
->i915
, &ce
->sseu
);
3027 i915_oa_init_reg_state(ce
, engine
);
3032 __execlists_context_pin(struct intel_context
*ce
,
3033 struct intel_engine_cs
*engine
)
3037 GEM_BUG_ON(!ce
->state
);
3038 GEM_BUG_ON(!i915_vma_is_pinned(ce
->state
));
3040 vaddr
= i915_gem_object_pin_map(ce
->state
->obj
,
3041 i915_coherent_map_type(engine
->i915
) |
3044 return PTR_ERR(vaddr
);
3046 ce
->lrc_desc
= lrc_descriptor(ce
, engine
) | CTX_DESC_FORCE_RESTORE
;
3047 ce
->lrc_reg_state
= vaddr
+ LRC_STATE_PN
* PAGE_SIZE
;
3048 __execlists_update_reg_state(ce
, engine
, ce
->ring
->tail
);
3053 static int execlists_context_pin(struct intel_context
*ce
)
3055 return __execlists_context_pin(ce
, ce
->engine
);
3058 static int execlists_context_alloc(struct intel_context
*ce
)
3060 return __execlists_context_alloc(ce
, ce
->engine
);
3063 static void execlists_context_reset(struct intel_context
*ce
)
3065 CE_TRACE(ce
, "reset\n");
3066 GEM_BUG_ON(!intel_context_is_pinned(ce
));
3068 intel_ring_reset(ce
->ring
, ce
->ring
->emit
);
3070 /* Scrub away the garbage */
3071 execlists_init_reg_state(ce
->lrc_reg_state
,
3072 ce
, ce
->engine
, ce
->ring
, true);
3073 __execlists_update_reg_state(ce
, ce
->engine
, ce
->ring
->tail
);
3075 ce
->lrc_desc
|= CTX_DESC_FORCE_RESTORE
;
3078 static const struct intel_context_ops execlists_context_ops
= {
3079 .alloc
= execlists_context_alloc
,
3081 .pin
= execlists_context_pin
,
3082 .unpin
= execlists_context_unpin
,
3084 .enter
= intel_context_enter_engine
,
3085 .exit
= intel_context_exit_engine
,
3087 .reset
= execlists_context_reset
,
3088 .destroy
= execlists_context_destroy
,
3091 static int gen8_emit_init_breadcrumb(struct i915_request
*rq
)
3095 if (!i915_request_timeline(rq
)->has_initial_breadcrumb
)
3098 cs
= intel_ring_begin(rq
, 6);
3103 * Check if we have been preempted before we even get started.
3105 * After this point i915_request_started() reports true, even if
3106 * we get preempted and so are no longer running.
3108 *cs
++ = MI_ARB_CHECK
;
3111 *cs
++ = MI_STORE_DWORD_IMM_GEN4
| MI_USE_GGTT
;
3112 *cs
++ = i915_request_timeline(rq
)->hwsp_offset
;
3114 *cs
++ = rq
->fence
.seqno
- 1;
3116 intel_ring_advance(rq
, cs
);
3118 /* Record the updated position of the request's payload */
3119 rq
->infix
= intel_ring_offset(rq
, cs
);
3124 static int execlists_request_alloc(struct i915_request
*request
)
3128 GEM_BUG_ON(!intel_context_is_pinned(request
->context
));
3131 * Flush enough space to reduce the likelihood of waiting after
3132 * we start building the request - in which case we will just
3133 * have to repeat work.
3135 request
->reserved_space
+= EXECLISTS_REQUEST_SIZE
;
3138 * Note that after this point, we have committed to using
3139 * this request as it is being used to both track the
3140 * state of engine initialisation and liveness of the
3141 * golden renderstate above. Think twice before you try
3142 * to cancel/unwind this request now.
3145 /* Unconditionally invalidate GPU caches and TLBs. */
3146 ret
= request
->engine
->emit_flush(request
, EMIT_INVALIDATE
);
3150 request
->reserved_space
-= EXECLISTS_REQUEST_SIZE
;
3155 * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after
3156 * PIPE_CONTROL instruction. This is required for the flush to happen correctly
3157 * but there is a slight complication as this is applied in WA batch where the
3158 * values are only initialized once so we cannot take register value at the
3159 * beginning and reuse it further; hence we save its value to memory, upload a
3160 * constant value with bit21 set and then we restore it back with the saved value.
3161 * To simplify the WA, a constant value is formed by using the default value
3162 * of this register. This shouldn't be a problem because we are only modifying
3163 * it for a short period and this batch in non-premptible. We can ofcourse
3164 * use additional instructions that read the actual value of the register
3165 * at that time and set our bit of interest but it makes the WA complicated.
3167 * This WA is also required for Gen9 so extracting as a function avoids
3171 gen8_emit_flush_coherentl3_wa(struct intel_engine_cs
*engine
, u32
*batch
)
3173 /* NB no one else is allowed to scribble over scratch + 256! */
3174 *batch
++ = MI_STORE_REGISTER_MEM_GEN8
| MI_SRM_LRM_GLOBAL_GTT
;
3175 *batch
++ = i915_mmio_reg_offset(GEN8_L3SQCREG4
);
3176 *batch
++ = intel_gt_scratch_offset(engine
->gt
,
3177 INTEL_GT_SCRATCH_FIELD_COHERENTL3_WA
);
3180 *batch
++ = MI_LOAD_REGISTER_IMM(1);
3181 *batch
++ = i915_mmio_reg_offset(GEN8_L3SQCREG4
);
3182 *batch
++ = 0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES
;
3184 batch
= gen8_emit_pipe_control(batch
,
3185 PIPE_CONTROL_CS_STALL
|
3186 PIPE_CONTROL_DC_FLUSH_ENABLE
,
3189 *batch
++ = MI_LOAD_REGISTER_MEM_GEN8
| MI_SRM_LRM_GLOBAL_GTT
;
3190 *batch
++ = i915_mmio_reg_offset(GEN8_L3SQCREG4
);
3191 *batch
++ = intel_gt_scratch_offset(engine
->gt
,
3192 INTEL_GT_SCRATCH_FIELD_COHERENTL3_WA
);
3199 * Typically we only have one indirect_ctx and per_ctx batch buffer which are
3200 * initialized at the beginning and shared across all contexts but this field
3201 * helps us to have multiple batches at different offsets and select them based
3202 * on a criteria. At the moment this batch always start at the beginning of the page
3203 * and at this point we don't have multiple wa_ctx batch buffers.
3205 * The number of WA applied are not known at the beginning; we use this field
3206 * to return the no of DWORDS written.
3208 * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END
3209 * so it adds NOOPs as padding to make it cacheline aligned.
3210 * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together
3211 * makes a complete batch buffer.
3213 static u32
*gen8_init_indirectctx_bb(struct intel_engine_cs
*engine
, u32
*batch
)
3215 /* WaDisableCtxRestoreArbitration:bdw,chv */
3216 *batch
++ = MI_ARB_ON_OFF
| MI_ARB_DISABLE
;
3218 /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
3219 if (IS_BROADWELL(engine
->i915
))
3220 batch
= gen8_emit_flush_coherentl3_wa(engine
, batch
);
3222 /* WaClearSlmSpaceAtContextSwitch:bdw,chv */
3223 /* Actual scratch location is at 128 bytes offset */
3224 batch
= gen8_emit_pipe_control(batch
,
3225 PIPE_CONTROL_FLUSH_L3
|
3226 PIPE_CONTROL_STORE_DATA_INDEX
|
3227 PIPE_CONTROL_CS_STALL
|
3228 PIPE_CONTROL_QW_WRITE
,
3229 LRC_PPHWSP_SCRATCH_ADDR
);
3231 *batch
++ = MI_ARB_ON_OFF
| MI_ARB_ENABLE
;
3233 /* Pad to end of cacheline */
3234 while ((unsigned long)batch
% CACHELINE_BYTES
)
3238 * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because
3239 * execution depends on the length specified in terms of cache lines
3240 * in the register CTX_RCS_INDIRECT_CTX
3251 static u32
*emit_lri(u32
*batch
, const struct lri
*lri
, unsigned int count
)
3253 GEM_BUG_ON(!count
|| count
> 63);
3255 *batch
++ = MI_LOAD_REGISTER_IMM(count
);
3257 *batch
++ = i915_mmio_reg_offset(lri
->reg
);
3258 *batch
++ = lri
->value
;
3259 } while (lri
++, --count
);
3265 static u32
*gen9_init_indirectctx_bb(struct intel_engine_cs
*engine
, u32
*batch
)
3267 static const struct lri lri
[] = {
3268 /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl,glk */
3270 COMMON_SLICE_CHICKEN2
,
3271 __MASKED_FIELD(GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE
,
3278 __MASKED_FIELD(FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX
,
3279 FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX
),
3285 __MASKED_FIELD(_3D_CHICKEN_SF_PROVOKING_VERTEX_FIX
,
3286 _3D_CHICKEN_SF_PROVOKING_VERTEX_FIX
),
3290 *batch
++ = MI_ARB_ON_OFF
| MI_ARB_DISABLE
;
3292 /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt,glk */
3293 batch
= gen8_emit_flush_coherentl3_wa(engine
, batch
);
3295 /* WaClearSlmSpaceAtContextSwitch:skl,bxt,kbl,glk,cfl */
3296 batch
= gen8_emit_pipe_control(batch
,
3297 PIPE_CONTROL_FLUSH_L3
|
3298 PIPE_CONTROL_STORE_DATA_INDEX
|
3299 PIPE_CONTROL_CS_STALL
|
3300 PIPE_CONTROL_QW_WRITE
,
3301 LRC_PPHWSP_SCRATCH_ADDR
);
3303 batch
= emit_lri(batch
, lri
, ARRAY_SIZE(lri
));
3305 /* WaMediaPoolStateCmdInWABB:bxt,glk */
3306 if (HAS_POOLED_EU(engine
->i915
)) {
3308 * EU pool configuration is setup along with golden context
3309 * during context initialization. This value depends on
3310 * device type (2x6 or 3x6) and needs to be updated based
3311 * on which subslice is disabled especially for 2x6
3312 * devices, however it is safe to load default
3313 * configuration of 3x6 device instead of masking off
3314 * corresponding bits because HW ignores bits of a disabled
3315 * subslice and drops down to appropriate config. Please
3316 * see render_state_setup() in i915_gem_render_state.c for
3317 * possible configurations, to avoid duplication they are
3318 * not shown here again.
3320 *batch
++ = GEN9_MEDIA_POOL_STATE
;
3321 *batch
++ = GEN9_MEDIA_POOL_ENABLE
;
3322 *batch
++ = 0x00777000;
3328 *batch
++ = MI_ARB_ON_OFF
| MI_ARB_ENABLE
;
3330 /* Pad to end of cacheline */
3331 while ((unsigned long)batch
% CACHELINE_BYTES
)
3338 gen10_init_indirectctx_bb(struct intel_engine_cs
*engine
, u32
*batch
)
3343 * WaPipeControlBefore3DStateSamplePattern: cnl
3345 * Ensure the engine is idle prior to programming a
3346 * 3DSTATE_SAMPLE_PATTERN during a context restore.
3348 batch
= gen8_emit_pipe_control(batch
,
3349 PIPE_CONTROL_CS_STALL
,
3352 * WaPipeControlBefore3DStateSamplePattern says we need 4 dwords for
3353 * the PIPE_CONTROL followed by 12 dwords of 0x0, so 16 dwords in
3354 * total. However, a PIPE_CONTROL is 6 dwords long, not 4, which is
3355 * confusing. Since gen8_emit_pipe_control() already advances the
3356 * batch by 6 dwords, we advance the other 10 here, completing a
3357 * cacheline. It's not clear if the workaround requires this padding
3358 * before other commands, or if it's just the regular padding we would
3359 * already have for the workaround bb, so leave it here for now.
3361 for (i
= 0; i
< 10; i
++)
3364 /* Pad to end of cacheline */
3365 while ((unsigned long)batch
% CACHELINE_BYTES
)
3371 #define CTX_WA_BB_OBJ_SIZE (PAGE_SIZE)
3373 static int lrc_setup_wa_ctx(struct intel_engine_cs
*engine
)
3375 struct drm_i915_gem_object
*obj
;
3376 struct i915_vma
*vma
;
3379 obj
= i915_gem_object_create_shmem(engine
->i915
, CTX_WA_BB_OBJ_SIZE
);
3381 return PTR_ERR(obj
);
3383 vma
= i915_vma_instance(obj
, &engine
->gt
->ggtt
->vm
, NULL
);
3389 err
= i915_ggtt_pin(vma
, 0, PIN_HIGH
);
3393 engine
->wa_ctx
.vma
= vma
;
3397 i915_gem_object_put(obj
);
3401 static void lrc_destroy_wa_ctx(struct intel_engine_cs
*engine
)
3403 i915_vma_unpin_and_release(&engine
->wa_ctx
.vma
, 0);
3406 typedef u32
*(*wa_bb_func_t
)(struct intel_engine_cs
*engine
, u32
*batch
);
3408 static int intel_init_workaround_bb(struct intel_engine_cs
*engine
)
3410 struct i915_ctx_workarounds
*wa_ctx
= &engine
->wa_ctx
;
3411 struct i915_wa_ctx_bb
*wa_bb
[2] = { &wa_ctx
->indirect_ctx
,
3413 wa_bb_func_t wa_bb_fn
[2];
3415 void *batch
, *batch_ptr
;
3419 if (engine
->class != RENDER_CLASS
)
3422 switch (INTEL_GEN(engine
->i915
)) {
3427 wa_bb_fn
[0] = gen10_init_indirectctx_bb
;
3431 wa_bb_fn
[0] = gen9_init_indirectctx_bb
;
3435 wa_bb_fn
[0] = gen8_init_indirectctx_bb
;
3439 MISSING_CASE(INTEL_GEN(engine
->i915
));
3443 ret
= lrc_setup_wa_ctx(engine
);
3445 DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret
);
3449 page
= i915_gem_object_get_dirty_page(wa_ctx
->vma
->obj
, 0);
3450 batch
= batch_ptr
= kmap_atomic(page
);
3453 * Emit the two workaround batch buffers, recording the offset from the
3454 * start of the workaround batch buffer object for each and their
3457 for (i
= 0; i
< ARRAY_SIZE(wa_bb_fn
); i
++) {
3458 wa_bb
[i
]->offset
= batch_ptr
- batch
;
3459 if (GEM_DEBUG_WARN_ON(!IS_ALIGNED(wa_bb
[i
]->offset
,
3460 CACHELINE_BYTES
))) {
3465 batch_ptr
= wa_bb_fn
[i
](engine
, batch_ptr
);
3466 wa_bb
[i
]->size
= batch_ptr
- (batch
+ wa_bb
[i
]->offset
);
3469 BUG_ON(batch_ptr
- batch
> CTX_WA_BB_OBJ_SIZE
);
3471 kunmap_atomic(batch
);
3473 lrc_destroy_wa_ctx(engine
);
3478 static void enable_error_interrupt(struct intel_engine_cs
*engine
)
3482 engine
->execlists
.error_interrupt
= 0;
3483 ENGINE_WRITE(engine
, RING_EMR
, ~0u);
3484 ENGINE_WRITE(engine
, RING_EIR
, ~0u); /* clear all existing errors */
3486 status
= ENGINE_READ(engine
, RING_ESR
);
3487 if (unlikely(status
)) {
3488 dev_err(engine
->i915
->drm
.dev
,
3489 "engine '%s' resumed still in error: %08x\n",
3490 engine
->name
, status
);
3491 __intel_gt_reset(engine
->gt
, engine
->mask
);
3495 * On current gen8+, we have 2 signals to play with
3497 * - I915_ERROR_INSTUCTION (bit 0)
3499 * Generate an error if the command parser encounters an invalid
3502 * This is a fatal error.
3506 * Generate an error on privilege violation (where the CP replaces
3507 * the instruction with a no-op). This also fires for writes into
3508 * read-only scratch pages.
3510 * This is a non-fatal error, parsing continues.
3512 * * there are a few others defined for odd HW that we do not use
3514 * Since CP_PRIV fires for cases where we have chosen to ignore the
3515 * error (as the HW is validating and suppressing the mistakes), we
3516 * only unmask the instruction error bit.
3518 ENGINE_WRITE(engine
, RING_EMR
, ~I915_ERROR_INSTRUCTION
);
3521 static void enable_execlists(struct intel_engine_cs
*engine
)
3525 assert_forcewakes_active(engine
->uncore
, FORCEWAKE_ALL
);
3527 intel_engine_set_hwsp_writemask(engine
, ~0u); /* HWSTAM */
3529 if (INTEL_GEN(engine
->i915
) >= 11)
3530 mode
= _MASKED_BIT_ENABLE(GEN11_GFX_DISABLE_LEGACY_MODE
);
3532 mode
= _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE
);
3533 ENGINE_WRITE_FW(engine
, RING_MODE_GEN7
, mode
);
3535 ENGINE_WRITE_FW(engine
, RING_MI_MODE
, _MASKED_BIT_DISABLE(STOP_RING
));
3537 ENGINE_WRITE_FW(engine
,
3539 i915_ggtt_offset(engine
->status_page
.vma
));
3540 ENGINE_POSTING_READ(engine
, RING_HWS_PGA
);
3542 enable_error_interrupt(engine
);
3544 engine
->context_tag
= 0;
3547 static bool unexpected_starting_state(struct intel_engine_cs
*engine
)
3549 bool unexpected
= false;
3551 if (ENGINE_READ_FW(engine
, RING_MI_MODE
) & STOP_RING
) {
3552 DRM_DEBUG_DRIVER("STOP_RING still set in RING_MI_MODE\n");
3559 static int execlists_resume(struct intel_engine_cs
*engine
)
3561 intel_mocs_init_engine(engine
);
3563 intel_engine_reset_breadcrumbs(engine
);
3565 if (GEM_SHOW_DEBUG() && unexpected_starting_state(engine
)) {
3566 struct drm_printer p
= drm_debug_printer(__func__
);
3568 intel_engine_dump(engine
, &p
, NULL
);
3571 enable_execlists(engine
);
3576 static void execlists_reset_prepare(struct intel_engine_cs
*engine
)
3578 struct intel_engine_execlists
* const execlists
= &engine
->execlists
;
3579 unsigned long flags
;
3581 ENGINE_TRACE(engine
, "depth<-%d\n",
3582 atomic_read(&execlists
->tasklet
.count
));
3585 * Prevent request submission to the hardware until we have
3586 * completed the reset in i915_gem_reset_finish(). If a request
3587 * is completed by one engine, it may then queue a request
3588 * to a second via its execlists->tasklet *just* as we are
3589 * calling engine->resume() and also writing the ELSP.
3590 * Turning off the execlists->tasklet until the reset is over
3591 * prevents the race.
3593 __tasklet_disable_sync_once(&execlists
->tasklet
);
3594 GEM_BUG_ON(!reset_in_progress(execlists
));
3596 /* And flush any current direct submission. */
3597 spin_lock_irqsave(&engine
->active
.lock
, flags
);
3598 spin_unlock_irqrestore(&engine
->active
.lock
, flags
);
3601 * We stop engines, otherwise we might get failed reset and a
3602 * dead gpu (on elk). Also as modern gpu as kbl can suffer
3603 * from system hang if batchbuffer is progressing when
3604 * the reset is issued, regardless of READY_TO_RESET ack.
3605 * Thus assume it is best to stop engines on all gens
3606 * where we have a gpu reset.
3608 * WaKBLVECSSemaphoreWaitPoll:kbl (on ALL_ENGINES)
3610 * FIXME: Wa for more modern gens needs to be validated
3612 intel_engine_stop_cs(engine
);
3615 static void reset_csb_pointers(struct intel_engine_cs
*engine
)
3617 struct intel_engine_execlists
* const execlists
= &engine
->execlists
;
3618 const unsigned int reset_value
= execlists
->csb_size
- 1;
3620 ring_set_paused(engine
, 0);
3623 * After a reset, the HW starts writing into CSB entry [0]. We
3624 * therefore have to set our HEAD pointer back one entry so that
3625 * the *first* entry we check is entry 0. To complicate this further,
3626 * as we don't wait for the first interrupt after reset, we have to
3627 * fake the HW write to point back to the last entry so that our
3628 * inline comparison of our cached head position against the last HW
3629 * write works even before the first interrupt.
3631 execlists
->csb_head
= reset_value
;
3632 WRITE_ONCE(*execlists
->csb_write
, reset_value
);
3633 wmb(); /* Make sure this is visible to HW (paranoia?) */
3636 * Sometimes Icelake forgets to reset its pointers on a GPU reset.
3637 * Bludgeon them with a mmio update to be sure.
3639 ENGINE_WRITE(engine
, RING_CONTEXT_STATUS_PTR
,
3640 reset_value
<< 8 | reset_value
);
3641 ENGINE_POSTING_READ(engine
, RING_CONTEXT_STATUS_PTR
);
3643 invalidate_csb_entries(&execlists
->csb_status
[0],
3644 &execlists
->csb_status
[reset_value
]);
3647 static void __reset_stop_ring(u32
*regs
, const struct intel_engine_cs
*engine
)
3651 x
= lrc_ring_mi_mode(engine
);
3653 regs
[x
+ 1] &= ~STOP_RING
;
3654 regs
[x
+ 1] |= STOP_RING
<< 16;
3658 static void __execlists_reset_reg_state(const struct intel_context
*ce
,
3659 const struct intel_engine_cs
*engine
)
3661 u32
*regs
= ce
->lrc_reg_state
;
3663 __reset_stop_ring(regs
, engine
);
3666 static void __execlists_reset(struct intel_engine_cs
*engine
, bool stalled
)
3668 struct intel_engine_execlists
* const execlists
= &engine
->execlists
;
3669 struct intel_context
*ce
;
3670 struct i915_request
*rq
;
3673 mb(); /* paranoia: read the CSB pointers from after the reset */
3674 clflush(execlists
->csb_write
);
3677 process_csb(engine
); /* drain preemption events */
3679 /* Following the reset, we need to reload the CSB read/write pointers */
3680 reset_csb_pointers(engine
);
3683 * Save the currently executing context, even if we completed
3684 * its request, it was still running at the time of the
3685 * reset and will have been clobbered.
3687 rq
= execlists_active(execlists
);
3692 GEM_BUG_ON(!i915_vma_is_pinned(ce
->state
));
3694 if (i915_request_completed(rq
)) {
3695 /* Idle context; tidy up the ring so we can restart afresh */
3696 head
= intel_ring_wrap(ce
->ring
, rq
->tail
);
3700 /* We still have requests in-flight; the engine should be active */
3701 GEM_BUG_ON(!intel_engine_pm_is_awake(engine
));
3703 /* Context has requests still in-flight; it should not be idle! */
3704 GEM_BUG_ON(i915_active_is_idle(&ce
->active
));
3706 rq
= active_request(ce
->timeline
, rq
);
3707 head
= intel_ring_wrap(ce
->ring
, rq
->head
);
3708 GEM_BUG_ON(head
== ce
->ring
->tail
);
3711 * If this request hasn't started yet, e.g. it is waiting on a
3712 * semaphore, we need to avoid skipping the request or else we
3713 * break the signaling chain. However, if the context is corrupt
3714 * the request will not restart and we will be stuck with a wedged
3715 * device. It is quite often the case that if we issue a reset
3716 * while the GPU is loading the context image, that the context
3717 * image becomes corrupt.
3719 * Otherwise, if we have not started yet, the request should replay
3720 * perfectly and we do not need to flag the result as being erroneous.
3722 if (!i915_request_started(rq
))
3726 * If the request was innocent, we leave the request in the ELSP
3727 * and will try to replay it on restarting. The context image may
3728 * have been corrupted by the reset, in which case we may have
3729 * to service a new GPU hang, but more likely we can continue on
3732 * If the request was guilty, we presume the context is corrupt
3733 * and have to at least restore the RING register in the context
3734 * image back to the expected values to skip over the guilty request.
3736 __i915_request_reset(rq
, stalled
);
3741 * We want a simple context + ring to execute the breadcrumb update.
3742 * We cannot rely on the context being intact across the GPU hang,
3743 * so clear it and rebuild just what we need for the breadcrumb.
3744 * All pending requests for this context will be zapped, and any
3745 * future request will be after userspace has had the opportunity
3746 * to recreate its own state.
3748 GEM_BUG_ON(!intel_context_is_pinned(ce
));
3749 restore_default_state(ce
, engine
);
3752 ENGINE_TRACE(engine
, "replay {head:%04x, tail:%04x}\n",
3753 head
, ce
->ring
->tail
);
3754 __execlists_reset_reg_state(ce
, engine
);
3755 __execlists_update_reg_state(ce
, engine
, head
);
3756 ce
->lrc_desc
|= CTX_DESC_FORCE_RESTORE
; /* paranoid: GPU was reset! */
3759 /* Push back any incomplete requests for replay after the reset. */
3760 cancel_port_requests(execlists
);
3761 __unwind_incomplete_requests(engine
);
3764 static void execlists_reset_rewind(struct intel_engine_cs
*engine
, bool stalled
)
3766 unsigned long flags
;
3768 ENGINE_TRACE(engine
, "\n");
3770 spin_lock_irqsave(&engine
->active
.lock
, flags
);
3772 __execlists_reset(engine
, stalled
);
3774 spin_unlock_irqrestore(&engine
->active
.lock
, flags
);
3777 static void nop_submission_tasklet(unsigned long data
)
3779 struct intel_engine_cs
* const engine
= (struct intel_engine_cs
*)data
;
3781 /* The driver is wedged; don't process any more events. */
3782 WRITE_ONCE(engine
->execlists
.queue_priority_hint
, INT_MIN
);
3785 static void execlists_reset_cancel(struct intel_engine_cs
*engine
)
3787 struct intel_engine_execlists
* const execlists
= &engine
->execlists
;
3788 struct i915_request
*rq
, *rn
;
3790 unsigned long flags
;
3792 ENGINE_TRACE(engine
, "\n");
3795 * Before we call engine->cancel_requests(), we should have exclusive
3796 * access to the submission state. This is arranged for us by the
3797 * caller disabling the interrupt generation, the tasklet and other
3798 * threads that may then access the same state, giving us a free hand
3799 * to reset state. However, we still need to let lockdep be aware that
3800 * we know this state may be accessed in hardirq context, so we
3801 * disable the irq around this manipulation and we want to keep
3802 * the spinlock focused on its duties and not accidentally conflate
3803 * coverage to the submission's irq state. (Similarly, although we
3804 * shouldn't need to disable irq around the manipulation of the
3805 * submission's irq state, we also wish to remind ourselves that
3808 spin_lock_irqsave(&engine
->active
.lock
, flags
);
3810 __execlists_reset(engine
, true);
3812 /* Mark all executing requests as skipped. */
3813 list_for_each_entry(rq
, &engine
->active
.requests
, sched
.link
)
3816 /* Flush the queued requests to the timeline list (for retiring). */
3817 while ((rb
= rb_first_cached(&execlists
->queue
))) {
3818 struct i915_priolist
*p
= to_priolist(rb
);
3821 priolist_for_each_request_consume(rq
, rn
, p
, i
) {
3823 __i915_request_submit(rq
);
3826 rb_erase_cached(&p
->node
, &execlists
->queue
);
3827 i915_priolist_free(p
);
3830 /* On-hold requests will be flushed to timeline upon their release */
3831 list_for_each_entry(rq
, &engine
->active
.hold
, sched
.link
)
3834 /* Cancel all attached virtual engines */
3835 while ((rb
= rb_first_cached(&execlists
->virtual))) {
3836 struct virtual_engine
*ve
=
3837 rb_entry(rb
, typeof(*ve
), nodes
[engine
->id
].rb
);
3839 rb_erase_cached(rb
, &execlists
->virtual);
3842 spin_lock(&ve
->base
.active
.lock
);
3843 rq
= fetch_and_zero(&ve
->request
);
3847 rq
->engine
= engine
;
3848 __i915_request_submit(rq
);
3849 i915_request_put(rq
);
3851 ve
->base
.execlists
.queue_priority_hint
= INT_MIN
;
3853 spin_unlock(&ve
->base
.active
.lock
);
3856 /* Remaining _unready_ requests will be nop'ed when submitted */
3858 execlists
->queue_priority_hint
= INT_MIN
;
3859 execlists
->queue
= RB_ROOT_CACHED
;
3861 GEM_BUG_ON(__tasklet_is_enabled(&execlists
->tasklet
));
3862 execlists
->tasklet
.func
= nop_submission_tasklet
;
3864 spin_unlock_irqrestore(&engine
->active
.lock
, flags
);
3867 static void execlists_reset_finish(struct intel_engine_cs
*engine
)
3869 struct intel_engine_execlists
* const execlists
= &engine
->execlists
;
3872 * After a GPU reset, we may have requests to replay. Do so now while
3873 * we still have the forcewake to be sure that the GPU is not allowed
3874 * to sleep before we restart and reload a context.
3876 GEM_BUG_ON(!reset_in_progress(execlists
));
3877 if (!RB_EMPTY_ROOT(&execlists
->queue
.rb_root
))
3878 execlists
->tasklet
.func(execlists
->tasklet
.data
);
3880 if (__tasklet_enable(&execlists
->tasklet
))
3881 /* And kick in case we missed a new request submission. */
3882 tasklet_hi_schedule(&execlists
->tasklet
);
3883 ENGINE_TRACE(engine
, "depth->%d\n",
3884 atomic_read(&execlists
->tasklet
.count
));
3887 static int gen8_emit_bb_start_noarb(struct i915_request
*rq
,
3888 u64 offset
, u32 len
,
3889 const unsigned int flags
)
3893 cs
= intel_ring_begin(rq
, 4);
3898 * WaDisableCtxRestoreArbitration:bdw,chv
3900 * We don't need to perform MI_ARB_ENABLE as often as we do (in
3901 * particular all the gen that do not need the w/a at all!), if we
3902 * took care to make sure that on every switch into this context
3903 * (both ordinary and for preemption) that arbitrartion was enabled
3904 * we would be fine. However, for gen8 there is another w/a that
3905 * requires us to not preempt inside GPGPU execution, so we keep
3906 * arbitration disabled for gen8 batches. Arbitration will be
3907 * re-enabled before we close the request
3908 * (engine->emit_fini_breadcrumb).
3910 *cs
++ = MI_ARB_ON_OFF
| MI_ARB_DISABLE
;
3912 /* FIXME(BDW+): Address space and security selectors. */
3913 *cs
++ = MI_BATCH_BUFFER_START_GEN8
|
3914 (flags
& I915_DISPATCH_SECURE
? 0 : BIT(8));
3915 *cs
++ = lower_32_bits(offset
);
3916 *cs
++ = upper_32_bits(offset
);
3918 intel_ring_advance(rq
, cs
);
3923 static int gen8_emit_bb_start(struct i915_request
*rq
,
3924 u64 offset
, u32 len
,
3925 const unsigned int flags
)
3929 cs
= intel_ring_begin(rq
, 6);
3933 *cs
++ = MI_ARB_ON_OFF
| MI_ARB_ENABLE
;
3935 *cs
++ = MI_BATCH_BUFFER_START_GEN8
|
3936 (flags
& I915_DISPATCH_SECURE
? 0 : BIT(8));
3937 *cs
++ = lower_32_bits(offset
);
3938 *cs
++ = upper_32_bits(offset
);
3940 *cs
++ = MI_ARB_ON_OFF
| MI_ARB_DISABLE
;
3943 intel_ring_advance(rq
, cs
);
3948 static void gen8_logical_ring_enable_irq(struct intel_engine_cs
*engine
)
3950 ENGINE_WRITE(engine
, RING_IMR
,
3951 ~(engine
->irq_enable_mask
| engine
->irq_keep_mask
));
3952 ENGINE_POSTING_READ(engine
, RING_IMR
);
3955 static void gen8_logical_ring_disable_irq(struct intel_engine_cs
*engine
)
3957 ENGINE_WRITE(engine
, RING_IMR
, ~engine
->irq_keep_mask
);
3960 static int gen8_emit_flush(struct i915_request
*request
, u32 mode
)
3964 cs
= intel_ring_begin(request
, 4);
3968 cmd
= MI_FLUSH_DW
+ 1;
3970 /* We always require a command barrier so that subsequent
3971 * commands, such as breadcrumb interrupts, are strictly ordered
3972 * wrt the contents of the write cache being flushed to memory
3973 * (and thus being coherent from the CPU).
3975 cmd
|= MI_FLUSH_DW_STORE_INDEX
| MI_FLUSH_DW_OP_STOREDW
;
3977 if (mode
& EMIT_INVALIDATE
) {
3978 cmd
|= MI_INVALIDATE_TLB
;
3979 if (request
->engine
->class == VIDEO_DECODE_CLASS
)
3980 cmd
|= MI_INVALIDATE_BSD
;
3984 *cs
++ = LRC_PPHWSP_SCRATCH_ADDR
;
3985 *cs
++ = 0; /* upper addr */
3986 *cs
++ = 0; /* value */
3987 intel_ring_advance(request
, cs
);
3992 static int gen8_emit_flush_render(struct i915_request
*request
,
3995 bool vf_flush_wa
= false, dc_flush_wa
= false;
3999 flags
|= PIPE_CONTROL_CS_STALL
;
4001 if (mode
& EMIT_FLUSH
) {
4002 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
4003 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
4004 flags
|= PIPE_CONTROL_DC_FLUSH_ENABLE
;
4005 flags
|= PIPE_CONTROL_FLUSH_ENABLE
;
4008 if (mode
& EMIT_INVALIDATE
) {
4009 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
4010 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
4011 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
4012 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
4013 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
4014 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
4015 flags
|= PIPE_CONTROL_QW_WRITE
;
4016 flags
|= PIPE_CONTROL_STORE_DATA_INDEX
;
4019 * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
4022 if (IS_GEN(request
->i915
, 9))
4025 /* WaForGAMHang:kbl */
4026 if (IS_KBL_REVID(request
->i915
, 0, KBL_REVID_B0
))
4038 cs
= intel_ring_begin(request
, len
);
4043 cs
= gen8_emit_pipe_control(cs
, 0, 0);
4046 cs
= gen8_emit_pipe_control(cs
, PIPE_CONTROL_DC_FLUSH_ENABLE
,
4049 cs
= gen8_emit_pipe_control(cs
, flags
, LRC_PPHWSP_SCRATCH_ADDR
);
4052 cs
= gen8_emit_pipe_control(cs
, PIPE_CONTROL_CS_STALL
, 0);
4054 intel_ring_advance(request
, cs
);
4059 static int gen11_emit_flush_render(struct i915_request
*request
,
4062 if (mode
& EMIT_FLUSH
) {
4066 flags
|= PIPE_CONTROL_CS_STALL
;
4068 flags
|= PIPE_CONTROL_TILE_CACHE_FLUSH
;
4069 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
4070 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
4071 flags
|= PIPE_CONTROL_DC_FLUSH_ENABLE
;
4072 flags
|= PIPE_CONTROL_FLUSH_ENABLE
;
4073 flags
|= PIPE_CONTROL_QW_WRITE
;
4074 flags
|= PIPE_CONTROL_STORE_DATA_INDEX
;
4076 cs
= intel_ring_begin(request
, 6);
4080 cs
= gen8_emit_pipe_control(cs
, flags
, LRC_PPHWSP_SCRATCH_ADDR
);
4081 intel_ring_advance(request
, cs
);
4084 if (mode
& EMIT_INVALIDATE
) {
4088 flags
|= PIPE_CONTROL_CS_STALL
;
4090 flags
|= PIPE_CONTROL_COMMAND_CACHE_INVALIDATE
;
4091 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
4092 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
4093 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
4094 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
4095 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
4096 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
4097 flags
|= PIPE_CONTROL_QW_WRITE
;
4098 flags
|= PIPE_CONTROL_STORE_DATA_INDEX
;
4100 cs
= intel_ring_begin(request
, 6);
4104 cs
= gen8_emit_pipe_control(cs
, flags
, LRC_PPHWSP_SCRATCH_ADDR
);
4105 intel_ring_advance(request
, cs
);
4111 static u32
preparser_disable(bool state
)
4113 return MI_ARB_CHECK
| 1 << 8 | state
;
4116 static int gen12_emit_flush_render(struct i915_request
*request
,
4119 if (mode
& EMIT_FLUSH
) {
4123 flags
|= PIPE_CONTROL_TILE_CACHE_FLUSH
;
4124 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
4125 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
4126 /* Wa_1409600907:tgl */
4127 flags
|= PIPE_CONTROL_DEPTH_STALL
;
4128 flags
|= PIPE_CONTROL_DC_FLUSH_ENABLE
;
4129 flags
|= PIPE_CONTROL_FLUSH_ENABLE
;
4130 flags
|= PIPE_CONTROL_HDC_PIPELINE_FLUSH
;
4132 flags
|= PIPE_CONTROL_STORE_DATA_INDEX
;
4133 flags
|= PIPE_CONTROL_QW_WRITE
;
4135 flags
|= PIPE_CONTROL_CS_STALL
;
4137 cs
= intel_ring_begin(request
, 6);
4141 cs
= gen8_emit_pipe_control(cs
, flags
, LRC_PPHWSP_SCRATCH_ADDR
);
4142 intel_ring_advance(request
, cs
);
4145 if (mode
& EMIT_INVALIDATE
) {
4149 flags
|= PIPE_CONTROL_COMMAND_CACHE_INVALIDATE
;
4150 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
4151 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
4152 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
4153 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
4154 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
4155 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
4156 flags
|= PIPE_CONTROL_L3_RO_CACHE_INVALIDATE
;
4158 flags
|= PIPE_CONTROL_STORE_DATA_INDEX
;
4159 flags
|= PIPE_CONTROL_QW_WRITE
;
4161 flags
|= PIPE_CONTROL_CS_STALL
;
4163 cs
= intel_ring_begin(request
, 8);
4168 * Prevent the pre-parser from skipping past the TLB
4169 * invalidate and loading a stale page for the batch
4170 * buffer / request payload.
4172 *cs
++ = preparser_disable(true);
4174 cs
= gen8_emit_pipe_control(cs
, flags
, LRC_PPHWSP_SCRATCH_ADDR
);
4176 *cs
++ = preparser_disable(false);
4177 intel_ring_advance(request
, cs
);
4184 * Reserve space for 2 NOOPs at the end of each request to be
4185 * used as a workaround for not being allowed to do lite
4186 * restore with HEAD==TAIL (WaIdleLiteRestore).
4188 static u32
*gen8_emit_wa_tail(struct i915_request
*request
, u32
*cs
)
4190 /* Ensure there's always at least one preemption point per-request. */
4191 *cs
++ = MI_ARB_CHECK
;
4193 request
->wa_tail
= intel_ring_offset(request
, cs
);
4198 static u32
*emit_preempt_busywait(struct i915_request
*request
, u32
*cs
)
4200 *cs
++ = MI_SEMAPHORE_WAIT
|
4201 MI_SEMAPHORE_GLOBAL_GTT
|
4203 MI_SEMAPHORE_SAD_EQ_SDD
;
4205 *cs
++ = intel_hws_preempt_address(request
->engine
);
4211 static __always_inline u32
*
4212 gen8_emit_fini_breadcrumb_footer(struct i915_request
*request
,
4215 *cs
++ = MI_USER_INTERRUPT
;
4217 *cs
++ = MI_ARB_ON_OFF
| MI_ARB_ENABLE
;
4218 if (intel_engine_has_semaphores(request
->engine
))
4219 cs
= emit_preempt_busywait(request
, cs
);
4221 request
->tail
= intel_ring_offset(request
, cs
);
4222 assert_ring_tail_valid(request
->ring
, request
->tail
);
4224 return gen8_emit_wa_tail(request
, cs
);
4227 static u32
*gen8_emit_fini_breadcrumb(struct i915_request
*request
, u32
*cs
)
4229 cs
= gen8_emit_ggtt_write(cs
,
4230 request
->fence
.seqno
,
4231 i915_request_active_timeline(request
)->hwsp_offset
,
4234 return gen8_emit_fini_breadcrumb_footer(request
, cs
);
4237 static u32
*gen8_emit_fini_breadcrumb_rcs(struct i915_request
*request
, u32
*cs
)
4239 cs
= gen8_emit_pipe_control(cs
,
4240 PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
|
4241 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
4242 PIPE_CONTROL_DC_FLUSH_ENABLE
,
4245 /* XXX flush+write+CS_STALL all in one upsets gem_concurrent_blt:kbl */
4246 cs
= gen8_emit_ggtt_write_rcs(cs
,
4247 request
->fence
.seqno
,
4248 i915_request_active_timeline(request
)->hwsp_offset
,
4249 PIPE_CONTROL_FLUSH_ENABLE
|
4250 PIPE_CONTROL_CS_STALL
);
4252 return gen8_emit_fini_breadcrumb_footer(request
, cs
);
4256 gen11_emit_fini_breadcrumb_rcs(struct i915_request
*request
, u32
*cs
)
4258 cs
= gen8_emit_ggtt_write_rcs(cs
,
4259 request
->fence
.seqno
,
4260 i915_request_active_timeline(request
)->hwsp_offset
,
4261 PIPE_CONTROL_CS_STALL
|
4262 PIPE_CONTROL_TILE_CACHE_FLUSH
|
4263 PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
|
4264 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
4265 PIPE_CONTROL_DC_FLUSH_ENABLE
|
4266 PIPE_CONTROL_FLUSH_ENABLE
);
4268 return gen8_emit_fini_breadcrumb_footer(request
, cs
);
4272 * Note that the CS instruction pre-parser will not stall on the breadcrumb
4273 * flush and will continue pre-fetching the instructions after it before the
4274 * memory sync is completed. On pre-gen12 HW, the pre-parser will stop at
4275 * BB_START/END instructions, so, even though we might pre-fetch the pre-amble
4276 * of the next request before the memory has been flushed, we're guaranteed that
4277 * we won't access the batch itself too early.
4278 * However, on gen12+ the parser can pre-fetch across the BB_START/END commands,
4279 * so, if the current request is modifying an instruction in the next request on
4280 * the same intel_context, we might pre-fetch and then execute the pre-update
4281 * instruction. To avoid this, the users of self-modifying code should either
4282 * disable the parser around the code emitting the memory writes, via a new flag
4283 * added to MI_ARB_CHECK, or emit the writes from a different intel_context. For
4284 * the in-kernel use-cases we've opted to use a separate context, see
4285 * reloc_gpu() as an example.
4286 * All the above applies only to the instructions themselves. Non-inline data
4287 * used by the instructions is not pre-fetched.
4290 static u32
*gen12_emit_preempt_busywait(struct i915_request
*request
, u32
*cs
)
4292 *cs
++ = MI_SEMAPHORE_WAIT_TOKEN
|
4293 MI_SEMAPHORE_GLOBAL_GTT
|
4295 MI_SEMAPHORE_SAD_EQ_SDD
;
4297 *cs
++ = intel_hws_preempt_address(request
->engine
);
4305 static __always_inline u32
*
4306 gen12_emit_fini_breadcrumb_footer(struct i915_request
*request
, u32
*cs
)
4308 *cs
++ = MI_USER_INTERRUPT
;
4310 *cs
++ = MI_ARB_ON_OFF
| MI_ARB_ENABLE
;
4311 if (intel_engine_has_semaphores(request
->engine
))
4312 cs
= gen12_emit_preempt_busywait(request
, cs
);
4314 request
->tail
= intel_ring_offset(request
, cs
);
4315 assert_ring_tail_valid(request
->ring
, request
->tail
);
4317 return gen8_emit_wa_tail(request
, cs
);
4320 static u32
*gen12_emit_fini_breadcrumb(struct i915_request
*request
, u32
*cs
)
4322 cs
= gen8_emit_ggtt_write(cs
,
4323 request
->fence
.seqno
,
4324 i915_request_active_timeline(request
)->hwsp_offset
,
4327 return gen12_emit_fini_breadcrumb_footer(request
, cs
);
4331 gen12_emit_fini_breadcrumb_rcs(struct i915_request
*request
, u32
*cs
)
4333 cs
= gen8_emit_ggtt_write_rcs(cs
,
4334 request
->fence
.seqno
,
4335 i915_request_active_timeline(request
)->hwsp_offset
,
4336 PIPE_CONTROL_CS_STALL
|
4337 PIPE_CONTROL_TILE_CACHE_FLUSH
|
4338 PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
|
4339 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
4340 /* Wa_1409600907:tgl */
4341 PIPE_CONTROL_DEPTH_STALL
|
4342 PIPE_CONTROL_DC_FLUSH_ENABLE
|
4343 PIPE_CONTROL_FLUSH_ENABLE
|
4344 PIPE_CONTROL_HDC_PIPELINE_FLUSH
);
4346 return gen12_emit_fini_breadcrumb_footer(request
, cs
);
4349 static void execlists_park(struct intel_engine_cs
*engine
)
4351 cancel_timer(&engine
->execlists
.timer
);
4352 cancel_timer(&engine
->execlists
.preempt
);
4355 void intel_execlists_set_default_submission(struct intel_engine_cs
*engine
)
4357 engine
->submit_request
= execlists_submit_request
;
4358 engine
->schedule
= i915_schedule
;
4359 engine
->execlists
.tasklet
.func
= execlists_submission_tasklet
;
4361 engine
->reset
.prepare
= execlists_reset_prepare
;
4362 engine
->reset
.rewind
= execlists_reset_rewind
;
4363 engine
->reset
.cancel
= execlists_reset_cancel
;
4364 engine
->reset
.finish
= execlists_reset_finish
;
4366 engine
->park
= execlists_park
;
4367 engine
->unpark
= NULL
;
4369 engine
->flags
|= I915_ENGINE_SUPPORTS_STATS
;
4370 if (!intel_vgpu_active(engine
->i915
)) {
4371 engine
->flags
|= I915_ENGINE_HAS_SEMAPHORES
;
4372 if (HAS_LOGICAL_RING_PREEMPTION(engine
->i915
))
4373 engine
->flags
|= I915_ENGINE_HAS_PREEMPTION
;
4376 if (INTEL_GEN(engine
->i915
) >= 12)
4377 engine
->flags
|= I915_ENGINE_HAS_RELATIVE_MMIO
;
4379 if (intel_engine_has_preemption(engine
))
4380 engine
->emit_bb_start
= gen8_emit_bb_start
;
4382 engine
->emit_bb_start
= gen8_emit_bb_start_noarb
;
4385 static void execlists_shutdown(struct intel_engine_cs
*engine
)
4387 /* Synchronise with residual timers and any softirq they raise */
4388 del_timer_sync(&engine
->execlists
.timer
);
4389 del_timer_sync(&engine
->execlists
.preempt
);
4390 tasklet_kill(&engine
->execlists
.tasklet
);
4393 static void execlists_release(struct intel_engine_cs
*engine
)
4395 execlists_shutdown(engine
);
4397 intel_engine_cleanup_common(engine
);
4398 lrc_destroy_wa_ctx(engine
);
4402 logical_ring_default_vfuncs(struct intel_engine_cs
*engine
)
4404 /* Default vfuncs which can be overriden by each engine. */
4406 engine
->resume
= execlists_resume
;
4408 engine
->cops
= &execlists_context_ops
;
4409 engine
->request_alloc
= execlists_request_alloc
;
4411 engine
->emit_flush
= gen8_emit_flush
;
4412 engine
->emit_init_breadcrumb
= gen8_emit_init_breadcrumb
;
4413 engine
->emit_fini_breadcrumb
= gen8_emit_fini_breadcrumb
;
4414 if (INTEL_GEN(engine
->i915
) >= 12)
4415 engine
->emit_fini_breadcrumb
= gen12_emit_fini_breadcrumb
;
4417 engine
->set_default_submission
= intel_execlists_set_default_submission
;
4419 if (INTEL_GEN(engine
->i915
) < 11) {
4420 engine
->irq_enable
= gen8_logical_ring_enable_irq
;
4421 engine
->irq_disable
= gen8_logical_ring_disable_irq
;
4424 * TODO: On Gen11 interrupt masks need to be clear
4425 * to allow C6 entry. Keep interrupts enabled at
4426 * and take the hit of generating extra interrupts
4427 * until a more refined solution exists.
4433 logical_ring_default_irqs(struct intel_engine_cs
*engine
)
4435 unsigned int shift
= 0;
4437 if (INTEL_GEN(engine
->i915
) < 11) {
4438 const u8 irq_shifts
[] = {
4439 [RCS0
] = GEN8_RCS_IRQ_SHIFT
,
4440 [BCS0
] = GEN8_BCS_IRQ_SHIFT
,
4441 [VCS0
] = GEN8_VCS0_IRQ_SHIFT
,
4442 [VCS1
] = GEN8_VCS1_IRQ_SHIFT
,
4443 [VECS0
] = GEN8_VECS_IRQ_SHIFT
,
4446 shift
= irq_shifts
[engine
->id
];
4449 engine
->irq_enable_mask
= GT_RENDER_USER_INTERRUPT
<< shift
;
4450 engine
->irq_keep_mask
= GT_CONTEXT_SWITCH_INTERRUPT
<< shift
;
4451 engine
->irq_keep_mask
|= GT_CS_MASTER_ERROR_INTERRUPT
<< shift
;
4454 static void rcs_submission_override(struct intel_engine_cs
*engine
)
4456 switch (INTEL_GEN(engine
->i915
)) {
4458 engine
->emit_flush
= gen12_emit_flush_render
;
4459 engine
->emit_fini_breadcrumb
= gen12_emit_fini_breadcrumb_rcs
;
4462 engine
->emit_flush
= gen11_emit_flush_render
;
4463 engine
->emit_fini_breadcrumb
= gen11_emit_fini_breadcrumb_rcs
;
4466 engine
->emit_flush
= gen8_emit_flush_render
;
4467 engine
->emit_fini_breadcrumb
= gen8_emit_fini_breadcrumb_rcs
;
4472 int intel_execlists_submission_setup(struct intel_engine_cs
*engine
)
4474 struct intel_engine_execlists
* const execlists
= &engine
->execlists
;
4475 struct drm_i915_private
*i915
= engine
->i915
;
4476 struct intel_uncore
*uncore
= engine
->uncore
;
4477 u32 base
= engine
->mmio_base
;
4479 tasklet_init(&engine
->execlists
.tasklet
,
4480 execlists_submission_tasklet
, (unsigned long)engine
);
4481 timer_setup(&engine
->execlists
.timer
, execlists_timeslice
, 0);
4482 timer_setup(&engine
->execlists
.preempt
, execlists_preempt
, 0);
4484 logical_ring_default_vfuncs(engine
);
4485 logical_ring_default_irqs(engine
);
4487 if (engine
->class == RENDER_CLASS
)
4488 rcs_submission_override(engine
);
4490 if (intel_init_workaround_bb(engine
))
4492 * We continue even if we fail to initialize WA batch
4493 * because we only expect rare glitches but nothing
4494 * critical to prevent us from using GPU
4496 DRM_ERROR("WA batch buffer initialization failed\n");
4498 if (HAS_LOGICAL_RING_ELSQ(i915
)) {
4499 execlists
->submit_reg
= uncore
->regs
+
4500 i915_mmio_reg_offset(RING_EXECLIST_SQ_CONTENTS(base
));
4501 execlists
->ctrl_reg
= uncore
->regs
+
4502 i915_mmio_reg_offset(RING_EXECLIST_CONTROL(base
));
4504 execlists
->submit_reg
= uncore
->regs
+
4505 i915_mmio_reg_offset(RING_ELSP(base
));
4508 execlists
->csb_status
=
4509 &engine
->status_page
.addr
[I915_HWS_CSB_BUF0_INDEX
];
4511 execlists
->csb_write
=
4512 &engine
->status_page
.addr
[intel_hws_csb_write_index(i915
)];
4514 if (INTEL_GEN(i915
) < 11)
4515 execlists
->csb_size
= GEN8_CSB_ENTRIES
;
4517 execlists
->csb_size
= GEN11_CSB_ENTRIES
;
4519 reset_csb_pointers(engine
);
4521 /* Finally, take ownership and responsibility for cleanup! */
4522 engine
->release
= execlists_release
;
4527 static u32
intel_lr_indirect_ctx_offset(const struct intel_engine_cs
*engine
)
4529 u32 indirect_ctx_offset
;
4531 switch (INTEL_GEN(engine
->i915
)) {
4533 MISSING_CASE(INTEL_GEN(engine
->i915
));
4536 indirect_ctx_offset
=
4537 GEN12_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT
;
4540 indirect_ctx_offset
=
4541 GEN11_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT
;
4544 indirect_ctx_offset
=
4545 GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT
;
4548 indirect_ctx_offset
=
4549 GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT
;
4552 indirect_ctx_offset
=
4553 GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT
;
4557 return indirect_ctx_offset
;
4561 static void init_common_reg_state(u32
* const regs
,
4562 const struct intel_engine_cs
*engine
,
4563 const struct intel_ring
*ring
,
4568 ctl
= _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH
);
4569 ctl
|= _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT
);
4571 ctl
|= CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT
;
4572 if (INTEL_GEN(engine
->i915
) < 11)
4573 ctl
|= _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT
|
4574 CTX_CTRL_RS_CTX_ENABLE
);
4575 regs
[CTX_CONTEXT_CONTROL
] = ctl
;
4577 regs
[CTX_RING_CTL
] = RING_CTL_SIZE(ring
->size
) | RING_VALID
;
4580 static void init_wa_bb_reg_state(u32
* const regs
,
4581 const struct intel_engine_cs
*engine
,
4584 const struct i915_ctx_workarounds
* const wa_ctx
= &engine
->wa_ctx
;
4586 if (wa_ctx
->per_ctx
.size
) {
4587 const u32 ggtt_offset
= i915_ggtt_offset(wa_ctx
->vma
);
4589 regs
[pos_bb_per_ctx
] =
4590 (ggtt_offset
+ wa_ctx
->per_ctx
.offset
) | 0x01;
4593 if (wa_ctx
->indirect_ctx
.size
) {
4594 const u32 ggtt_offset
= i915_ggtt_offset(wa_ctx
->vma
);
4596 regs
[pos_bb_per_ctx
+ 2] =
4597 (ggtt_offset
+ wa_ctx
->indirect_ctx
.offset
) |
4598 (wa_ctx
->indirect_ctx
.size
/ CACHELINE_BYTES
);
4600 regs
[pos_bb_per_ctx
+ 4] =
4601 intel_lr_indirect_ctx_offset(engine
) << 6;
4605 static void init_ppgtt_reg_state(u32
*regs
, const struct i915_ppgtt
*ppgtt
)
4607 if (i915_vm_is_4lvl(&ppgtt
->vm
)) {
4608 /* 64b PPGTT (48bit canonical)
4609 * PDP0_DESCRIPTOR contains the base address to PML4 and
4610 * other PDP Descriptors are ignored.
4612 ASSIGN_CTX_PML4(ppgtt
, regs
);
4614 ASSIGN_CTX_PDP(ppgtt
, regs
, 3);
4615 ASSIGN_CTX_PDP(ppgtt
, regs
, 2);
4616 ASSIGN_CTX_PDP(ppgtt
, regs
, 1);
4617 ASSIGN_CTX_PDP(ppgtt
, regs
, 0);
4621 static struct i915_ppgtt
*vm_alias(struct i915_address_space
*vm
)
4623 if (i915_is_ggtt(vm
))
4624 return i915_vm_to_ggtt(vm
)->alias
;
4626 return i915_vm_to_ppgtt(vm
);
4629 static void execlists_init_reg_state(u32
*regs
,
4630 const struct intel_context
*ce
,
4631 const struct intel_engine_cs
*engine
,
4632 const struct intel_ring
*ring
,
4636 * A context is actually a big batch buffer with several
4637 * MI_LOAD_REGISTER_IMM commands followed by (reg, value) pairs. The
4638 * values we are setting here are only for the first context restore:
4639 * on a subsequent save, the GPU will recreate this batchbuffer with new
4640 * values (including all the missing MI_LOAD_REGISTER_IMM commands that
4641 * we are not initializing here).
4643 * Must keep consistent with virtual_update_register_offsets().
4645 set_offsets(regs
, reg_offsets(engine
), engine
, inhibit
);
4647 init_common_reg_state(regs
, engine
, ring
, inhibit
);
4648 init_ppgtt_reg_state(regs
, vm_alias(ce
->vm
));
4650 init_wa_bb_reg_state(regs
, engine
,
4651 INTEL_GEN(engine
->i915
) >= 12 ?
4652 GEN12_CTX_BB_PER_CTX_PTR
:
4653 CTX_BB_PER_CTX_PTR
);
4655 __reset_stop_ring(regs
, engine
);
4659 populate_lr_context(struct intel_context
*ce
,
4660 struct drm_i915_gem_object
*ctx_obj
,
4661 struct intel_engine_cs
*engine
,
4662 struct intel_ring
*ring
)
4664 bool inhibit
= true;
4668 vaddr
= i915_gem_object_pin_map(ctx_obj
, I915_MAP_WB
);
4669 if (IS_ERR(vaddr
)) {
4670 ret
= PTR_ERR(vaddr
);
4671 DRM_DEBUG_DRIVER("Could not map object pages! (%d)\n", ret
);
4675 set_redzone(vaddr
, engine
);
4677 if (engine
->default_state
) {
4680 defaults
= i915_gem_object_pin_map(engine
->default_state
,
4682 if (IS_ERR(defaults
)) {
4683 ret
= PTR_ERR(defaults
);
4687 memcpy(vaddr
, defaults
, engine
->context_size
);
4688 i915_gem_object_unpin_map(engine
->default_state
);
4689 __set_bit(CONTEXT_VALID_BIT
, &ce
->flags
);
4693 /* Clear the ppHWSP (inc. per-context counters) */
4694 memset(vaddr
, 0, PAGE_SIZE
);
4697 * The second page of the context object contains some registers which
4698 * must be set up prior to the first execution.
4700 execlists_init_reg_state(vaddr
+ LRC_STATE_PN
* PAGE_SIZE
,
4701 ce
, engine
, ring
, inhibit
);
4705 __i915_gem_object_flush_map(ctx_obj
, 0, engine
->context_size
);
4706 i915_gem_object_unpin_map(ctx_obj
);
4710 static int __execlists_context_alloc(struct intel_context
*ce
,
4711 struct intel_engine_cs
*engine
)
4713 struct drm_i915_gem_object
*ctx_obj
;
4714 struct intel_ring
*ring
;
4715 struct i915_vma
*vma
;
4719 GEM_BUG_ON(ce
->state
);
4720 context_size
= round_up(engine
->context_size
, I915_GTT_PAGE_SIZE
);
4722 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM
))
4723 context_size
+= I915_GTT_PAGE_SIZE
; /* for redzone */
4725 ctx_obj
= i915_gem_object_create_shmem(engine
->i915
, context_size
);
4726 if (IS_ERR(ctx_obj
))
4727 return PTR_ERR(ctx_obj
);
4729 vma
= i915_vma_instance(ctx_obj
, &engine
->gt
->ggtt
->vm
, NULL
);
4732 goto error_deref_obj
;
4735 if (!ce
->timeline
) {
4736 struct intel_timeline
*tl
;
4737 struct i915_vma
*hwsp
;
4740 * Use the static global HWSP for the kernel context, and
4741 * a dynamically allocated cacheline for everyone else.
4744 if (unlikely(intel_context_is_barrier(ce
)))
4745 hwsp
= engine
->status_page
.vma
;
4747 tl
= intel_timeline_create(engine
->gt
, hwsp
);
4750 goto error_deref_obj
;
4756 ring
= intel_engine_create_ring(engine
, (unsigned long)ce
->ring
);
4758 ret
= PTR_ERR(ring
);
4759 goto error_deref_obj
;
4762 ret
= populate_lr_context(ce
, ctx_obj
, engine
, ring
);
4764 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret
);
4765 goto error_ring_free
;
4774 intel_ring_put(ring
);
4776 i915_gem_object_put(ctx_obj
);
4780 static struct list_head
*virtual_queue(struct virtual_engine
*ve
)
4782 return &ve
->base
.execlists
.default_priolist
.requests
[0];
4785 static void virtual_context_destroy(struct kref
*kref
)
4787 struct virtual_engine
*ve
=
4788 container_of(kref
, typeof(*ve
), context
.ref
);
4791 GEM_BUG_ON(!list_empty(virtual_queue(ve
)));
4792 GEM_BUG_ON(ve
->request
);
4793 GEM_BUG_ON(ve
->context
.inflight
);
4795 for (n
= 0; n
< ve
->num_siblings
; n
++) {
4796 struct intel_engine_cs
*sibling
= ve
->siblings
[n
];
4797 struct rb_node
*node
= &ve
->nodes
[sibling
->id
].rb
;
4798 unsigned long flags
;
4800 if (RB_EMPTY_NODE(node
))
4803 spin_lock_irqsave(&sibling
->active
.lock
, flags
);
4805 /* Detachment is lazily performed in the execlists tasklet */
4806 if (!RB_EMPTY_NODE(node
))
4807 rb_erase_cached(node
, &sibling
->execlists
.virtual);
4809 spin_unlock_irqrestore(&sibling
->active
.lock
, flags
);
4811 GEM_BUG_ON(__tasklet_is_scheduled(&ve
->base
.execlists
.tasklet
));
4813 if (ve
->context
.state
)
4814 __execlists_context_fini(&ve
->context
);
4815 intel_context_fini(&ve
->context
);
4821 static void virtual_engine_initial_hint(struct virtual_engine
*ve
)
4826 * Pick a random sibling on starting to help spread the load around.
4828 * New contexts are typically created with exactly the same order
4829 * of siblings, and often started in batches. Due to the way we iterate
4830 * the array of sibling when submitting requests, sibling[0] is
4831 * prioritised for dequeuing. If we make sure that sibling[0] is fairly
4832 * randomised across the system, we also help spread the load by the
4833 * first engine we inspect being different each time.
4835 * NB This does not force us to execute on this engine, it will just
4836 * typically be the first we inspect for submission.
4838 swp
= prandom_u32_max(ve
->num_siblings
);
4842 swap(ve
->siblings
[swp
], ve
->siblings
[0]);
4843 if (!intel_engine_has_relative_mmio(ve
->siblings
[0]))
4844 virtual_update_register_offsets(ve
->context
.lrc_reg_state
,
4848 static int virtual_context_alloc(struct intel_context
*ce
)
4850 struct virtual_engine
*ve
= container_of(ce
, typeof(*ve
), context
);
4852 return __execlists_context_alloc(ce
, ve
->siblings
[0]);
4855 static int virtual_context_pin(struct intel_context
*ce
)
4857 struct virtual_engine
*ve
= container_of(ce
, typeof(*ve
), context
);
4860 /* Note: we must use a real engine class for setting up reg state */
4861 err
= __execlists_context_pin(ce
, ve
->siblings
[0]);
4865 virtual_engine_initial_hint(ve
);
4869 static void virtual_context_enter(struct intel_context
*ce
)
4871 struct virtual_engine
*ve
= container_of(ce
, typeof(*ve
), context
);
4874 for (n
= 0; n
< ve
->num_siblings
; n
++)
4875 intel_engine_pm_get(ve
->siblings
[n
]);
4877 intel_timeline_enter(ce
->timeline
);
4880 static void virtual_context_exit(struct intel_context
*ce
)
4882 struct virtual_engine
*ve
= container_of(ce
, typeof(*ve
), context
);
4885 intel_timeline_exit(ce
->timeline
);
4887 for (n
= 0; n
< ve
->num_siblings
; n
++)
4888 intel_engine_pm_put(ve
->siblings
[n
]);
4891 static const struct intel_context_ops virtual_context_ops
= {
4892 .alloc
= virtual_context_alloc
,
4894 .pin
= virtual_context_pin
,
4895 .unpin
= execlists_context_unpin
,
4897 .enter
= virtual_context_enter
,
4898 .exit
= virtual_context_exit
,
4900 .destroy
= virtual_context_destroy
,
4903 static intel_engine_mask_t
virtual_submission_mask(struct virtual_engine
*ve
)
4905 struct i915_request
*rq
;
4906 intel_engine_mask_t mask
;
4908 rq
= READ_ONCE(ve
->request
);
4912 /* The rq is ready for submission; rq->execution_mask is now stable. */
4913 mask
= rq
->execution_mask
;
4914 if (unlikely(!mask
)) {
4915 /* Invalid selection, submit to a random engine in error */
4916 i915_request_set_error_once(rq
, -ENODEV
);
4917 mask
= ve
->siblings
[0]->mask
;
4920 ENGINE_TRACE(&ve
->base
, "rq=%llx:%lld, mask=%x, prio=%d\n",
4921 rq
->fence
.context
, rq
->fence
.seqno
,
4922 mask
, ve
->base
.execlists
.queue_priority_hint
);
4927 static void virtual_submission_tasklet(unsigned long data
)
4929 struct virtual_engine
* const ve
= (struct virtual_engine
*)data
;
4930 const int prio
= READ_ONCE(ve
->base
.execlists
.queue_priority_hint
);
4931 intel_engine_mask_t mask
;
4935 mask
= virtual_submission_mask(ve
);
4937 if (unlikely(!mask
))
4940 local_irq_disable();
4941 for (n
= 0; READ_ONCE(ve
->request
) && n
< ve
->num_siblings
; n
++) {
4942 struct intel_engine_cs
*sibling
= ve
->siblings
[n
];
4943 struct ve_node
* const node
= &ve
->nodes
[sibling
->id
];
4944 struct rb_node
**parent
, *rb
;
4947 if (unlikely(!(mask
& sibling
->mask
))) {
4948 if (!RB_EMPTY_NODE(&node
->rb
)) {
4949 spin_lock(&sibling
->active
.lock
);
4950 rb_erase_cached(&node
->rb
,
4951 &sibling
->execlists
.virtual);
4952 RB_CLEAR_NODE(&node
->rb
);
4953 spin_unlock(&sibling
->active
.lock
);
4958 spin_lock(&sibling
->active
.lock
);
4960 if (!RB_EMPTY_NODE(&node
->rb
)) {
4962 * Cheat and avoid rebalancing the tree if we can
4963 * reuse this node in situ.
4965 first
= rb_first_cached(&sibling
->execlists
.virtual) ==
4967 if (prio
== node
->prio
|| (prio
> node
->prio
&& first
))
4970 rb_erase_cached(&node
->rb
, &sibling
->execlists
.virtual);
4975 parent
= &sibling
->execlists
.virtual.rb_root
.rb_node
;
4977 struct ve_node
*other
;
4980 other
= rb_entry(rb
, typeof(*other
), rb
);
4981 if (prio
> other
->prio
) {
4982 parent
= &rb
->rb_left
;
4984 parent
= &rb
->rb_right
;
4989 rb_link_node(&node
->rb
, rb
, parent
);
4990 rb_insert_color_cached(&node
->rb
,
4991 &sibling
->execlists
.virtual,
4995 GEM_BUG_ON(RB_EMPTY_NODE(&node
->rb
));
4997 if (first
&& prio
> sibling
->execlists
.queue_priority_hint
) {
4998 sibling
->execlists
.queue_priority_hint
= prio
;
4999 tasklet_hi_schedule(&sibling
->execlists
.tasklet
);
5002 spin_unlock(&sibling
->active
.lock
);
5007 static void virtual_submit_request(struct i915_request
*rq
)
5009 struct virtual_engine
*ve
= to_virtual_engine(rq
->engine
);
5010 struct i915_request
*old
;
5011 unsigned long flags
;
5013 ENGINE_TRACE(&ve
->base
, "rq=%llx:%lld\n",
5017 GEM_BUG_ON(ve
->base
.submit_request
!= virtual_submit_request
);
5019 spin_lock_irqsave(&ve
->base
.active
.lock
, flags
);
5022 if (old
) { /* background completion event from preempt-to-busy */
5023 GEM_BUG_ON(!i915_request_completed(old
));
5024 __i915_request_submit(old
);
5025 i915_request_put(old
);
5028 if (i915_request_completed(rq
)) {
5029 __i915_request_submit(rq
);
5031 ve
->base
.execlists
.queue_priority_hint
= INT_MIN
;
5034 ve
->base
.execlists
.queue_priority_hint
= rq_prio(rq
);
5035 ve
->request
= i915_request_get(rq
);
5037 GEM_BUG_ON(!list_empty(virtual_queue(ve
)));
5038 list_move_tail(&rq
->sched
.link
, virtual_queue(ve
));
5040 tasklet_schedule(&ve
->base
.execlists
.tasklet
);
5043 spin_unlock_irqrestore(&ve
->base
.active
.lock
, flags
);
5046 static struct ve_bond
*
5047 virtual_find_bond(struct virtual_engine
*ve
,
5048 const struct intel_engine_cs
*master
)
5052 for (i
= 0; i
< ve
->num_bonds
; i
++) {
5053 if (ve
->bonds
[i
].master
== master
)
5054 return &ve
->bonds
[i
];
5061 virtual_bond_execute(struct i915_request
*rq
, struct dma_fence
*signal
)
5063 struct virtual_engine
*ve
= to_virtual_engine(rq
->engine
);
5064 intel_engine_mask_t allowed
, exec
;
5065 struct ve_bond
*bond
;
5067 allowed
= ~to_request(signal
)->engine
->mask
;
5069 bond
= virtual_find_bond(ve
, to_request(signal
)->engine
);
5071 allowed
&= bond
->sibling_mask
;
5073 /* Restrict the bonded request to run on only the available engines */
5074 exec
= READ_ONCE(rq
->execution_mask
);
5075 while (!try_cmpxchg(&rq
->execution_mask
, &exec
, exec
& allowed
))
5078 /* Prevent the master from being re-run on the bonded engines */
5079 to_request(signal
)->execution_mask
&= ~allowed
;
5082 struct intel_context
*
5083 intel_execlists_create_virtual(struct intel_engine_cs
**siblings
,
5086 struct virtual_engine
*ve
;
5091 return ERR_PTR(-EINVAL
);
5094 return intel_context_create(siblings
[0]);
5096 ve
= kzalloc(struct_size(ve
, siblings
, count
), GFP_KERNEL
);
5098 return ERR_PTR(-ENOMEM
);
5100 ve
->base
.i915
= siblings
[0]->i915
;
5101 ve
->base
.gt
= siblings
[0]->gt
;
5102 ve
->base
.uncore
= siblings
[0]->uncore
;
5105 ve
->base
.class = OTHER_CLASS
;
5106 ve
->base
.uabi_class
= I915_ENGINE_CLASS_INVALID
;
5107 ve
->base
.instance
= I915_ENGINE_CLASS_INVALID_VIRTUAL
;
5108 ve
->base
.uabi_instance
= I915_ENGINE_CLASS_INVALID_VIRTUAL
;
5111 * The decision on whether to submit a request using semaphores
5112 * depends on the saturated state of the engine. We only compute
5113 * this during HW submission of the request, and we need for this
5114 * state to be globally applied to all requests being submitted
5115 * to this engine. Virtual engines encompass more than one physical
5116 * engine and so we cannot accurately tell in advance if one of those
5117 * engines is already saturated and so cannot afford to use a semaphore
5118 * and be pessimized in priority for doing so -- if we are the only
5119 * context using semaphores after all other clients have stopped, we
5120 * will be starved on the saturated system. Such a global switch for
5121 * semaphores is less than ideal, but alas is the current compromise.
5123 ve
->base
.saturated
= ALL_ENGINES
;
5125 snprintf(ve
->base
.name
, sizeof(ve
->base
.name
), "virtual");
5127 intel_engine_init_active(&ve
->base
, ENGINE_VIRTUAL
);
5128 intel_engine_init_breadcrumbs(&ve
->base
);
5129 intel_engine_init_execlists(&ve
->base
);
5131 ve
->base
.cops
= &virtual_context_ops
;
5132 ve
->base
.request_alloc
= execlists_request_alloc
;
5134 ve
->base
.schedule
= i915_schedule
;
5135 ve
->base
.submit_request
= virtual_submit_request
;
5136 ve
->base
.bond_execute
= virtual_bond_execute
;
5138 INIT_LIST_HEAD(virtual_queue(ve
));
5139 ve
->base
.execlists
.queue_priority_hint
= INT_MIN
;
5140 tasklet_init(&ve
->base
.execlists
.tasklet
,
5141 virtual_submission_tasklet
,
5144 intel_context_init(&ve
->context
, &ve
->base
);
5146 for (n
= 0; n
< count
; n
++) {
5147 struct intel_engine_cs
*sibling
= siblings
[n
];
5149 GEM_BUG_ON(!is_power_of_2(sibling
->mask
));
5150 if (sibling
->mask
& ve
->base
.mask
) {
5151 DRM_DEBUG("duplicate %s entry in load balancer\n",
5158 * The virtual engine implementation is tightly coupled to
5159 * the execlists backend -- we push out request directly
5160 * into a tree inside each physical engine. We could support
5161 * layering if we handle cloning of the requests and
5162 * submitting a copy into each backend.
5164 if (sibling
->execlists
.tasklet
.func
!=
5165 execlists_submission_tasklet
) {
5170 GEM_BUG_ON(RB_EMPTY_NODE(&ve
->nodes
[sibling
->id
].rb
));
5171 RB_CLEAR_NODE(&ve
->nodes
[sibling
->id
].rb
);
5173 ve
->siblings
[ve
->num_siblings
++] = sibling
;
5174 ve
->base
.mask
|= sibling
->mask
;
5177 * All physical engines must be compatible for their emission
5178 * functions (as we build the instructions during request
5179 * construction and do not alter them before submission
5180 * on the physical engine). We use the engine class as a guide
5181 * here, although that could be refined.
5183 if (ve
->base
.class != OTHER_CLASS
) {
5184 if (ve
->base
.class != sibling
->class) {
5185 DRM_DEBUG("invalid mixing of engine class, sibling %d, already %d\n",
5186 sibling
->class, ve
->base
.class);
5193 ve
->base
.class = sibling
->class;
5194 ve
->base
.uabi_class
= sibling
->uabi_class
;
5195 snprintf(ve
->base
.name
, sizeof(ve
->base
.name
),
5196 "v%dx%d", ve
->base
.class, count
);
5197 ve
->base
.context_size
= sibling
->context_size
;
5199 ve
->base
.emit_bb_start
= sibling
->emit_bb_start
;
5200 ve
->base
.emit_flush
= sibling
->emit_flush
;
5201 ve
->base
.emit_init_breadcrumb
= sibling
->emit_init_breadcrumb
;
5202 ve
->base
.emit_fini_breadcrumb
= sibling
->emit_fini_breadcrumb
;
5203 ve
->base
.emit_fini_breadcrumb_dw
=
5204 sibling
->emit_fini_breadcrumb_dw
;
5206 ve
->base
.flags
= sibling
->flags
;
5209 ve
->base
.flags
|= I915_ENGINE_IS_VIRTUAL
;
5211 return &ve
->context
;
5214 intel_context_put(&ve
->context
);
5215 return ERR_PTR(err
);
5218 struct intel_context
*
5219 intel_execlists_clone_virtual(struct intel_engine_cs
*src
)
5221 struct virtual_engine
*se
= to_virtual_engine(src
);
5222 struct intel_context
*dst
;
5224 dst
= intel_execlists_create_virtual(se
->siblings
,
5229 if (se
->num_bonds
) {
5230 struct virtual_engine
*de
= to_virtual_engine(dst
->engine
);
5232 de
->bonds
= kmemdup(se
->bonds
,
5233 sizeof(*se
->bonds
) * se
->num_bonds
,
5236 intel_context_put(dst
);
5237 return ERR_PTR(-ENOMEM
);
5240 de
->num_bonds
= se
->num_bonds
;
5246 int intel_virtual_engine_attach_bond(struct intel_engine_cs
*engine
,
5247 const struct intel_engine_cs
*master
,
5248 const struct intel_engine_cs
*sibling
)
5250 struct virtual_engine
*ve
= to_virtual_engine(engine
);
5251 struct ve_bond
*bond
;
5254 /* Sanity check the sibling is part of the virtual engine */
5255 for (n
= 0; n
< ve
->num_siblings
; n
++)
5256 if (sibling
== ve
->siblings
[n
])
5258 if (n
== ve
->num_siblings
)
5261 bond
= virtual_find_bond(ve
, master
);
5263 bond
->sibling_mask
|= sibling
->mask
;
5267 bond
= krealloc(ve
->bonds
,
5268 sizeof(*bond
) * (ve
->num_bonds
+ 1),
5273 bond
[ve
->num_bonds
].master
= master
;
5274 bond
[ve
->num_bonds
].sibling_mask
= sibling
->mask
;
5282 struct intel_engine_cs
*
5283 intel_virtual_engine_get_sibling(struct intel_engine_cs
*engine
,
5284 unsigned int sibling
)
5286 struct virtual_engine
*ve
= to_virtual_engine(engine
);
5288 if (sibling
>= ve
->num_siblings
)
5291 return ve
->siblings
[sibling
];
5294 void intel_execlists_show_requests(struct intel_engine_cs
*engine
,
5295 struct drm_printer
*m
,
5296 void (*show_request
)(struct drm_printer
*m
,
5297 struct i915_request
*rq
,
5298 const char *prefix
),
5301 const struct intel_engine_execlists
*execlists
= &engine
->execlists
;
5302 struct i915_request
*rq
, *last
;
5303 unsigned long flags
;
5307 spin_lock_irqsave(&engine
->active
.lock
, flags
);
5311 list_for_each_entry(rq
, &engine
->active
.requests
, sched
.link
) {
5312 if (count
++ < max
- 1)
5313 show_request(m
, rq
, "\t\tE ");
5320 "\t\t...skipping %d executing requests...\n",
5323 show_request(m
, last
, "\t\tE ");
5326 if (execlists
->switch_priority_hint
!= INT_MIN
)
5327 drm_printf(m
, "\t\tSwitch priority hint: %d\n",
5328 READ_ONCE(execlists
->switch_priority_hint
));
5329 if (execlists
->queue_priority_hint
!= INT_MIN
)
5330 drm_printf(m
, "\t\tQueue priority hint: %d\n",
5331 READ_ONCE(execlists
->queue_priority_hint
));
5335 for (rb
= rb_first_cached(&execlists
->queue
); rb
; rb
= rb_next(rb
)) {
5336 struct i915_priolist
*p
= rb_entry(rb
, typeof(*p
), node
);
5339 priolist_for_each_request(rq
, p
, i
) {
5340 if (count
++ < max
- 1)
5341 show_request(m
, rq
, "\t\tQ ");
5349 "\t\t...skipping %d queued requests...\n",
5352 show_request(m
, last
, "\t\tQ ");
5357 for (rb
= rb_first_cached(&execlists
->virtual); rb
; rb
= rb_next(rb
)) {
5358 struct virtual_engine
*ve
=
5359 rb_entry(rb
, typeof(*ve
), nodes
[engine
->id
].rb
);
5360 struct i915_request
*rq
= READ_ONCE(ve
->request
);
5363 if (count
++ < max
- 1)
5364 show_request(m
, rq
, "\t\tV ");
5372 "\t\t...skipping %d virtual requests...\n",
5375 show_request(m
, last
, "\t\tV ");
5378 spin_unlock_irqrestore(&engine
->active
.lock
, flags
);
5381 void intel_lr_context_reset(struct intel_engine_cs
*engine
,
5382 struct intel_context
*ce
,
5386 GEM_BUG_ON(!intel_context_is_pinned(ce
));
5389 * We want a simple context + ring to execute the breadcrumb update.
5390 * We cannot rely on the context being intact across the GPU hang,
5391 * so clear it and rebuild just what we need for the breadcrumb.
5392 * All pending requests for this context will be zapped, and any
5393 * future request will be after userspace has had the opportunity
5394 * to recreate its own state.
5397 restore_default_state(ce
, engine
);
5399 /* Rerun the request; its payload has been neutered (if guilty). */
5400 __execlists_update_reg_state(ce
, engine
, head
);
5404 intel_engine_in_execlists_submission_mode(const struct intel_engine_cs
*engine
)
5406 return engine
->set_default_submission
==
5407 intel_execlists_set_default_submission
;
5410 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
5411 #include "selftest_lrc.c"