2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
25 * Zhiyuan Lv <zhiyuan.lv@intel.com>
28 * Terrence Xu <terrence.xu@intel.com>
29 * Changbin Du <changbin.du@intel.com>
30 * Bing Niu <bing.niu@intel.com>
31 * Zhi Wang <zhi.a.wang@intel.com>
38 static int get_edp_pipe(struct intel_vgpu
*vgpu
)
40 u32 data
= vgpu_vreg(vgpu
, _TRANS_DDI_FUNC_CTL_EDP
);
43 switch (data
& TRANS_DDI_EDP_INPUT_MASK
) {
44 case TRANS_DDI_EDP_INPUT_A_ON
:
45 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
48 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
51 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
58 static int edp_pipe_is_enabled(struct intel_vgpu
*vgpu
)
60 struct drm_i915_private
*dev_priv
= vgpu
->gvt
->gt
->i915
;
62 if (!(vgpu_vreg_t(vgpu
, PIPECONF(_PIPE_EDP
)) & PIPECONF_ENABLE
))
65 if (!(vgpu_vreg(vgpu
, _TRANS_DDI_FUNC_CTL_EDP
) & TRANS_DDI_FUNC_ENABLE
))
70 int pipe_is_enabled(struct intel_vgpu
*vgpu
, int pipe
)
72 struct drm_i915_private
*dev_priv
= vgpu
->gvt
->gt
->i915
;
74 if (drm_WARN_ON(&dev_priv
->drm
,
75 pipe
< PIPE_A
|| pipe
>= I915_MAX_PIPES
))
78 if (vgpu_vreg_t(vgpu
, PIPECONF(pipe
)) & PIPECONF_ENABLE
)
81 if (edp_pipe_is_enabled(vgpu
) &&
82 get_edp_pipe(vgpu
) == pipe
)
87 static unsigned char virtual_dp_monitor_edid
[GVT_EDID_NUM
][EDID_SIZE
] = {
89 /* EDID with 1024x768 as its resolution */
91 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
92 /* Vendor & Product Identification */
93 0x22, 0xf0, 0x54, 0x29, 0x00, 0x00, 0x00, 0x00, 0x04, 0x17,
94 /* Version & Revision */
96 /* Basic Display Parameters & Features */
97 0xa5, 0x34, 0x20, 0x78, 0x23,
98 /* Color Characteristics */
99 0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54,
100 /* Established Timings: maximum resolution is 1024x768 */
102 /* Standard Timings. All invalid */
103 0x00, 0xc0, 0x00, 0xc0, 0x00, 0x40, 0x00, 0x80, 0x00, 0x00,
104 0x00, 0x40, 0x00, 0x00, 0x00, 0x01,
105 /* 18 Byte Data Blocks 1: invalid */
106 0x00, 0x00, 0x80, 0xa0, 0x70, 0xb0,
107 0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a,
108 /* 18 Byte Data Blocks 2: invalid */
109 0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a,
110 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
111 /* 18 Byte Data Blocks 3: invalid */
112 0x00, 0x00, 0x00, 0xfc, 0x00, 0x48,
113 0x50, 0x20, 0x5a, 0x52, 0x32, 0x34, 0x34, 0x30, 0x77, 0x0a, 0x20, 0x20,
114 /* 18 Byte Data Blocks 4: invalid */
115 0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x4e, 0x34, 0x33, 0x30, 0x34, 0x30,
116 0x44, 0x58, 0x51, 0x0a, 0x20, 0x20,
117 /* Extension Block Count */
123 /* EDID with 1920x1200 as its resolution */
125 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
126 /* Vendor & Product Identification */
127 0x22, 0xf0, 0x54, 0x29, 0x00, 0x00, 0x00, 0x00, 0x04, 0x17,
128 /* Version & Revision */
130 /* Basic Display Parameters & Features */
131 0xa5, 0x34, 0x20, 0x78, 0x23,
132 /* Color Characteristics */
133 0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54,
134 /* Established Timings: maximum resolution is 1024x768 */
138 * below new resolutions can be supported:
139 * 1920x1080, 1280x720, 1280x960, 1280x1024,
140 * 1440x900, 1600x1200, 1680x1050
142 0xd1, 0xc0, 0x81, 0xc0, 0x81, 0x40, 0x81, 0x80, 0x95, 0x00,
143 0xa9, 0x40, 0xb3, 0x00, 0x01, 0x01,
144 /* 18 Byte Data Blocks 1: max resolution is 1920x1200 */
145 0x28, 0x3c, 0x80, 0xa0, 0x70, 0xb0,
146 0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a,
147 /* 18 Byte Data Blocks 2: invalid */
148 0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a,
149 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
150 /* 18 Byte Data Blocks 3: invalid */
151 0x00, 0x00, 0x00, 0xfc, 0x00, 0x48,
152 0x50, 0x20, 0x5a, 0x52, 0x32, 0x34, 0x34, 0x30, 0x77, 0x0a, 0x20, 0x20,
153 /* 18 Byte Data Blocks 4: invalid */
154 0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x4e, 0x34, 0x33, 0x30, 0x34, 0x30,
155 0x44, 0x58, 0x51, 0x0a, 0x20, 0x20,
156 /* Extension Block Count */
163 #define DPCD_HEADER_SIZE 0xb
165 /* let the virtual display supports DP1.2 */
166 static u8 dpcd_fix_data
[DPCD_HEADER_SIZE
] = {
167 0x12, 0x014, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
170 static void emulate_monitor_status_change(struct intel_vgpu
*vgpu
)
172 struct drm_i915_private
*dev_priv
= vgpu
->gvt
->gt
->i915
;
175 if (IS_BROXTON(dev_priv
)) {
176 vgpu_vreg_t(vgpu
, GEN8_DE_PORT_ISR
) &= ~(BXT_DE_PORT_HP_DDIA
|
177 BXT_DE_PORT_HP_DDIB
|
178 BXT_DE_PORT_HP_DDIC
);
180 if (intel_vgpu_has_monitor_on_port(vgpu
, PORT_A
)) {
181 vgpu_vreg_t(vgpu
, GEN8_DE_PORT_ISR
) |=
185 if (intel_vgpu_has_monitor_on_port(vgpu
, PORT_B
)) {
186 vgpu_vreg_t(vgpu
, GEN8_DE_PORT_ISR
) |=
190 if (intel_vgpu_has_monitor_on_port(vgpu
, PORT_C
)) {
191 vgpu_vreg_t(vgpu
, GEN8_DE_PORT_ISR
) |=
198 vgpu_vreg_t(vgpu
, SDEISR
) &= ~(SDE_PORTB_HOTPLUG_CPT
|
199 SDE_PORTC_HOTPLUG_CPT
|
200 SDE_PORTD_HOTPLUG_CPT
);
202 if (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
) ||
203 IS_COFFEELAKE(dev_priv
)) {
204 vgpu_vreg_t(vgpu
, SDEISR
) &= ~(SDE_PORTA_HOTPLUG_SPT
|
205 SDE_PORTE_HOTPLUG_SPT
);
206 vgpu_vreg_t(vgpu
, SKL_FUSE_STATUS
) |=
207 SKL_FUSE_DOWNLOAD_STATUS
|
208 SKL_FUSE_PG_DIST_STATUS(SKL_PG0
) |
209 SKL_FUSE_PG_DIST_STATUS(SKL_PG1
) |
210 SKL_FUSE_PG_DIST_STATUS(SKL_PG2
);
212 * Only 1 PIPE enabled in current vGPU display and PIPE_A is
213 * tied to TRANSCODER_A in HW, so it's safe to assume PIPE_A,
214 * TRANSCODER_A can be enabled. PORT_x depends on the input of
215 * setup_virtual_dp_monitor, we can bind DPLL0 to any PORT_x
216 * so we fixed to DPLL0 here.
217 * Setup DPLL0: DP link clk 1620 MHz, non SSC, DP Mode
219 vgpu_vreg_t(vgpu
, DPLL_CTRL1
) =
220 DPLL_CTRL1_OVERRIDE(DPLL_ID_SKL_DPLL0
);
221 vgpu_vreg_t(vgpu
, DPLL_CTRL1
) |=
222 DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620
, DPLL_ID_SKL_DPLL0
);
223 vgpu_vreg_t(vgpu
, LCPLL1_CTL
) =
224 LCPLL_PLL_ENABLE
| LCPLL_PLL_LOCK
;
225 vgpu_vreg_t(vgpu
, DPLL_STATUS
) = DPLL_LOCK(DPLL_ID_SKL_DPLL0
);
227 * Golden M/N are calculated based on:
228 * 24 bpp, 4 lanes, 154000 pixel clk (from virtual EDID),
229 * DP link clk 1620 MHz and non-constant_n.
230 * TODO: calculate DP link symbol clk and stream clk m/n.
232 vgpu_vreg_t(vgpu
, PIPE_DATA_M1(TRANSCODER_A
)) = 63 << TU_SIZE_SHIFT
;
233 vgpu_vreg_t(vgpu
, PIPE_DATA_M1(TRANSCODER_A
)) |= 0x5b425e;
234 vgpu_vreg_t(vgpu
, PIPE_DATA_N1(TRANSCODER_A
)) = 0x800000;
235 vgpu_vreg_t(vgpu
, PIPE_LINK_M1(TRANSCODER_A
)) = 0x3cd6e;
236 vgpu_vreg_t(vgpu
, PIPE_LINK_N1(TRANSCODER_A
)) = 0x80000;
239 if (intel_vgpu_has_monitor_on_port(vgpu
, PORT_B
)) {
240 vgpu_vreg_t(vgpu
, DPLL_CTRL2
) &=
241 ~DPLL_CTRL2_DDI_CLK_OFF(PORT_B
);
242 vgpu_vreg_t(vgpu
, DPLL_CTRL2
) |=
243 DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0
, PORT_B
);
244 vgpu_vreg_t(vgpu
, DPLL_CTRL2
) |=
245 DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_B
);
246 vgpu_vreg_t(vgpu
, SFUSE_STRAP
) |= SFUSE_STRAP_DDIB_DETECTED
;
247 vgpu_vreg_t(vgpu
, TRANS_DDI_FUNC_CTL(TRANSCODER_A
)) &=
248 ~(TRANS_DDI_BPC_MASK
| TRANS_DDI_MODE_SELECT_MASK
|
249 TRANS_DDI_PORT_MASK
);
250 vgpu_vreg_t(vgpu
, TRANS_DDI_FUNC_CTL(TRANSCODER_A
)) |=
251 (TRANS_DDI_BPC_8
| TRANS_DDI_MODE_SELECT_DP_SST
|
252 (PORT_B
<< TRANS_DDI_PORT_SHIFT
) |
253 TRANS_DDI_FUNC_ENABLE
);
254 if (IS_BROADWELL(dev_priv
)) {
255 vgpu_vreg_t(vgpu
, PORT_CLK_SEL(PORT_B
)) &=
257 vgpu_vreg_t(vgpu
, PORT_CLK_SEL(PORT_B
)) |=
258 PORT_CLK_SEL_LCPLL_810
;
260 vgpu_vreg_t(vgpu
, DDI_BUF_CTL(PORT_B
)) |= DDI_BUF_CTL_ENABLE
;
261 vgpu_vreg_t(vgpu
, DDI_BUF_CTL(PORT_B
)) &= ~DDI_BUF_IS_IDLE
;
262 vgpu_vreg_t(vgpu
, SDEISR
) |= SDE_PORTB_HOTPLUG_CPT
;
265 if (intel_vgpu_has_monitor_on_port(vgpu
, PORT_C
)) {
266 vgpu_vreg_t(vgpu
, DPLL_CTRL2
) &=
267 ~DPLL_CTRL2_DDI_CLK_OFF(PORT_C
);
268 vgpu_vreg_t(vgpu
, DPLL_CTRL2
) |=
269 DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0
, PORT_C
);
270 vgpu_vreg_t(vgpu
, DPLL_CTRL2
) |=
271 DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_C
);
272 vgpu_vreg_t(vgpu
, SDEISR
) |= SDE_PORTC_HOTPLUG_CPT
;
273 vgpu_vreg_t(vgpu
, TRANS_DDI_FUNC_CTL(TRANSCODER_A
)) &=
274 ~(TRANS_DDI_BPC_MASK
| TRANS_DDI_MODE_SELECT_MASK
|
275 TRANS_DDI_PORT_MASK
);
276 vgpu_vreg_t(vgpu
, TRANS_DDI_FUNC_CTL(TRANSCODER_A
)) |=
277 (TRANS_DDI_BPC_8
| TRANS_DDI_MODE_SELECT_DP_SST
|
278 (PORT_C
<< TRANS_DDI_PORT_SHIFT
) |
279 TRANS_DDI_FUNC_ENABLE
);
280 if (IS_BROADWELL(dev_priv
)) {
281 vgpu_vreg_t(vgpu
, PORT_CLK_SEL(PORT_C
)) &=
283 vgpu_vreg_t(vgpu
, PORT_CLK_SEL(PORT_C
)) |=
284 PORT_CLK_SEL_LCPLL_810
;
286 vgpu_vreg_t(vgpu
, DDI_BUF_CTL(PORT_C
)) |= DDI_BUF_CTL_ENABLE
;
287 vgpu_vreg_t(vgpu
, DDI_BUF_CTL(PORT_C
)) &= ~DDI_BUF_IS_IDLE
;
288 vgpu_vreg_t(vgpu
, SFUSE_STRAP
) |= SFUSE_STRAP_DDIC_DETECTED
;
291 if (intel_vgpu_has_monitor_on_port(vgpu
, PORT_D
)) {
292 vgpu_vreg_t(vgpu
, DPLL_CTRL2
) &=
293 ~DPLL_CTRL2_DDI_CLK_OFF(PORT_D
);
294 vgpu_vreg_t(vgpu
, DPLL_CTRL2
) |=
295 DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0
, PORT_D
);
296 vgpu_vreg_t(vgpu
, DPLL_CTRL2
) |=
297 DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_D
);
298 vgpu_vreg_t(vgpu
, SDEISR
) |= SDE_PORTD_HOTPLUG_CPT
;
299 vgpu_vreg_t(vgpu
, TRANS_DDI_FUNC_CTL(TRANSCODER_A
)) &=
300 ~(TRANS_DDI_BPC_MASK
| TRANS_DDI_MODE_SELECT_MASK
|
301 TRANS_DDI_PORT_MASK
);
302 vgpu_vreg_t(vgpu
, TRANS_DDI_FUNC_CTL(TRANSCODER_A
)) |=
303 (TRANS_DDI_BPC_8
| TRANS_DDI_MODE_SELECT_DP_SST
|
304 (PORT_D
<< TRANS_DDI_PORT_SHIFT
) |
305 TRANS_DDI_FUNC_ENABLE
);
306 if (IS_BROADWELL(dev_priv
)) {
307 vgpu_vreg_t(vgpu
, PORT_CLK_SEL(PORT_D
)) &=
309 vgpu_vreg_t(vgpu
, PORT_CLK_SEL(PORT_D
)) |=
310 PORT_CLK_SEL_LCPLL_810
;
312 vgpu_vreg_t(vgpu
, DDI_BUF_CTL(PORT_D
)) |= DDI_BUF_CTL_ENABLE
;
313 vgpu_vreg_t(vgpu
, DDI_BUF_CTL(PORT_D
)) &= ~DDI_BUF_IS_IDLE
;
314 vgpu_vreg_t(vgpu
, SFUSE_STRAP
) |= SFUSE_STRAP_DDID_DETECTED
;
317 if ((IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
) ||
318 IS_COFFEELAKE(dev_priv
)) &&
319 intel_vgpu_has_monitor_on_port(vgpu
, PORT_E
)) {
320 vgpu_vreg_t(vgpu
, SDEISR
) |= SDE_PORTE_HOTPLUG_SPT
;
323 if (intel_vgpu_has_monitor_on_port(vgpu
, PORT_A
)) {
324 if (IS_BROADWELL(dev_priv
))
325 vgpu_vreg_t(vgpu
, GEN8_DE_PORT_ISR
) |=
326 GEN8_PORT_DP_A_HOTPLUG
;
328 vgpu_vreg_t(vgpu
, SDEISR
) |= SDE_PORTA_HOTPLUG_SPT
;
330 vgpu_vreg_t(vgpu
, DDI_BUF_CTL(PORT_A
)) |= DDI_INIT_DISPLAY_DETECTED
;
333 /* Clear host CRT status, so guest couldn't detect this host CRT. */
334 if (IS_BROADWELL(dev_priv
))
335 vgpu_vreg_t(vgpu
, PCH_ADPA
) &= ~ADPA_CRT_HOTPLUG_MONITOR_MASK
;
337 /* Disable Primary/Sprite/Cursor plane */
338 for_each_pipe(dev_priv
, pipe
) {
339 vgpu_vreg_t(vgpu
, DSPCNTR(pipe
)) &= ~DISPLAY_PLANE_ENABLE
;
340 vgpu_vreg_t(vgpu
, SPRCTL(pipe
)) &= ~SPRITE_ENABLE
;
341 vgpu_vreg_t(vgpu
, CURCNTR(pipe
)) &= ~MCURSOR_MODE
;
342 vgpu_vreg_t(vgpu
, CURCNTR(pipe
)) |= MCURSOR_MODE_DISABLE
;
345 vgpu_vreg_t(vgpu
, PIPECONF(PIPE_A
)) |= PIPECONF_ENABLE
;
348 static void clean_virtual_dp_monitor(struct intel_vgpu
*vgpu
, int port_num
)
350 struct intel_vgpu_port
*port
= intel_vgpu_port(vgpu
, port_num
);
359 static int setup_virtual_dp_monitor(struct intel_vgpu
*vgpu
, int port_num
,
360 int type
, unsigned int resolution
)
362 struct drm_i915_private
*i915
= vgpu
->gvt
->gt
->i915
;
363 struct intel_vgpu_port
*port
= intel_vgpu_port(vgpu
, port_num
);
365 if (drm_WARN_ON(&i915
->drm
, resolution
>= GVT_EDID_NUM
))
368 port
->edid
= kzalloc(sizeof(*(port
->edid
)), GFP_KERNEL
);
372 port
->dpcd
= kzalloc(sizeof(*(port
->dpcd
)), GFP_KERNEL
);
378 memcpy(port
->edid
->edid_block
, virtual_dp_monitor_edid
[resolution
],
380 port
->edid
->data_valid
= true;
382 memcpy(port
->dpcd
->data
, dpcd_fix_data
, DPCD_HEADER_SIZE
);
383 port
->dpcd
->data_valid
= true;
384 port
->dpcd
->data
[DPCD_SINK_COUNT
] = 0x1;
386 port
->id
= resolution
;
388 emulate_monitor_status_change(vgpu
);
394 * intel_gvt_check_vblank_emulation - check if vblank emulation timer should
395 * be turned on/off when a virtual pipe is enabled/disabled.
398 * This function is used to turn on/off vblank timer according to currently
399 * enabled/disabled virtual pipes.
402 void intel_gvt_check_vblank_emulation(struct intel_gvt
*gvt
)
404 struct intel_gvt_irq
*irq
= &gvt
->irq
;
405 struct intel_vgpu
*vgpu
;
409 mutex_lock(&gvt
->lock
);
410 for_each_active_vgpu(gvt
, vgpu
, id
) {
411 for (pipe
= 0; pipe
< I915_MAX_PIPES
; pipe
++) {
412 if (pipe_is_enabled(vgpu
, pipe
)) {
421 /* all the pipes are disabled */
423 hrtimer_cancel(&irq
->vblank_timer
.timer
);
425 hrtimer_start(&irq
->vblank_timer
.timer
,
426 ktime_add_ns(ktime_get(), irq
->vblank_timer
.period
),
428 mutex_unlock(&gvt
->lock
);
431 static void emulate_vblank_on_pipe(struct intel_vgpu
*vgpu
, int pipe
)
433 struct drm_i915_private
*dev_priv
= vgpu
->gvt
->gt
->i915
;
434 struct intel_vgpu_irq
*irq
= &vgpu
->irq
;
435 int vblank_event
[] = {
436 [PIPE_A
] = PIPE_A_VBLANK
,
437 [PIPE_B
] = PIPE_B_VBLANK
,
438 [PIPE_C
] = PIPE_C_VBLANK
,
442 if (pipe
< PIPE_A
|| pipe
> PIPE_C
)
445 for_each_set_bit(event
, irq
->flip_done_event
[pipe
],
446 INTEL_GVT_EVENT_MAX
) {
447 clear_bit(event
, irq
->flip_done_event
[pipe
]);
448 if (!pipe_is_enabled(vgpu
, pipe
))
451 intel_vgpu_trigger_virtual_event(vgpu
, event
);
454 if (pipe_is_enabled(vgpu
, pipe
)) {
455 vgpu_vreg_t(vgpu
, PIPE_FRMCOUNT_G4X(pipe
))++;
456 intel_vgpu_trigger_virtual_event(vgpu
, vblank_event
[pipe
]);
460 static void emulate_vblank(struct intel_vgpu
*vgpu
)
464 mutex_lock(&vgpu
->vgpu_lock
);
465 for_each_pipe(vgpu
->gvt
->gt
->i915
, pipe
)
466 emulate_vblank_on_pipe(vgpu
, pipe
);
467 mutex_unlock(&vgpu
->vgpu_lock
);
471 * intel_gvt_emulate_vblank - trigger vblank events for vGPUs on GVT device
474 * This function is used to trigger vblank interrupts for vGPUs on GVT device
477 void intel_gvt_emulate_vblank(struct intel_gvt
*gvt
)
479 struct intel_vgpu
*vgpu
;
482 mutex_lock(&gvt
->lock
);
483 for_each_active_vgpu(gvt
, vgpu
, id
)
484 emulate_vblank(vgpu
);
485 mutex_unlock(&gvt
->lock
);
489 * intel_vgpu_emulate_hotplug - trigger hotplug event for vGPU
491 * @connected: link state
493 * This function is used to trigger hotplug interrupt for vGPU
496 void intel_vgpu_emulate_hotplug(struct intel_vgpu
*vgpu
, bool connected
)
498 struct drm_i915_private
*i915
= vgpu
->gvt
->gt
->i915
;
500 /* TODO: add more platforms support */
501 if (IS_SKYLAKE(i915
) || IS_KABYLAKE(i915
) ||
502 IS_COFFEELAKE(i915
)) {
504 vgpu_vreg_t(vgpu
, SFUSE_STRAP
) |=
505 SFUSE_STRAP_DDID_DETECTED
;
506 vgpu_vreg_t(vgpu
, SDEISR
) |= SDE_PORTD_HOTPLUG_CPT
;
508 vgpu_vreg_t(vgpu
, SFUSE_STRAP
) &=
509 ~SFUSE_STRAP_DDID_DETECTED
;
510 vgpu_vreg_t(vgpu
, SDEISR
) &= ~SDE_PORTD_HOTPLUG_CPT
;
512 vgpu_vreg_t(vgpu
, SDEIIR
) |= SDE_PORTD_HOTPLUG_CPT
;
513 vgpu_vreg_t(vgpu
, PCH_PORT_HOTPLUG
) |=
514 PORTD_HOTPLUG_STATUS_MASK
;
515 intel_vgpu_trigger_virtual_event(vgpu
, DP_D_HOTPLUG
);
520 * intel_vgpu_clean_display - clean vGPU virtual display emulation
523 * This function is used to clean vGPU virtual display emulation stuffs
526 void intel_vgpu_clean_display(struct intel_vgpu
*vgpu
)
528 struct drm_i915_private
*dev_priv
= vgpu
->gvt
->gt
->i915
;
530 if (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
) ||
531 IS_COFFEELAKE(dev_priv
))
532 clean_virtual_dp_monitor(vgpu
, PORT_D
);
534 clean_virtual_dp_monitor(vgpu
, PORT_B
);
538 * intel_vgpu_init_display- initialize vGPU virtual display emulation
540 * @resolution: resolution index for intel_vgpu_edid
542 * This function is used to initialize vGPU virtual display emulation stuffs
545 * Zero on success, negative error code if failed.
548 int intel_vgpu_init_display(struct intel_vgpu
*vgpu
, u64 resolution
)
550 struct drm_i915_private
*dev_priv
= vgpu
->gvt
->gt
->i915
;
552 intel_vgpu_init_i2c_edid(vgpu
);
554 if (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
) ||
555 IS_COFFEELAKE(dev_priv
))
556 return setup_virtual_dp_monitor(vgpu
, PORT_D
, GVT_DP_D
,
559 return setup_virtual_dp_monitor(vgpu
, PORT_B
, GVT_DP_B
,
564 * intel_vgpu_reset_display- reset vGPU virtual display emulation
567 * This function is used to reset vGPU virtual display emulation stuffs
570 void intel_vgpu_reset_display(struct intel_vgpu
*vgpu
)
572 emulate_monitor_status_change(vgpu
);