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Merge v5.0-rc7 into drm-next
[thirdparty/linux.git] / drivers / gpu / drm / i915 / gvt / handlers.c
1 /*
2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Kevin Tian <kevin.tian@intel.com>
25 * Eddie Dong <eddie.dong@intel.com>
26 * Zhiyuan Lv <zhiyuan.lv@intel.com>
27 *
28 * Contributors:
29 * Min He <min.he@intel.com>
30 * Tina Zhang <tina.zhang@intel.com>
31 * Pei Zhang <pei.zhang@intel.com>
32 * Niu Bing <bing.niu@intel.com>
33 * Ping Gao <ping.a.gao@intel.com>
34 * Zhi Wang <zhi.a.wang@intel.com>
35 *
36
37 */
38
39 #include "i915_drv.h"
40 #include "gvt.h"
41 #include "i915_pvinfo.h"
42
43 /* XXX FIXME i915 has changed PP_XXX definition */
44 #define PCH_PP_STATUS _MMIO(0xc7200)
45 #define PCH_PP_CONTROL _MMIO(0xc7204)
46 #define PCH_PP_ON_DELAYS _MMIO(0xc7208)
47 #define PCH_PP_OFF_DELAYS _MMIO(0xc720c)
48 #define PCH_PP_DIVISOR _MMIO(0xc7210)
49
50 unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt)
51 {
52 if (IS_BROADWELL(gvt->dev_priv))
53 return D_BDW;
54 else if (IS_SKYLAKE(gvt->dev_priv))
55 return D_SKL;
56 else if (IS_KABYLAKE(gvt->dev_priv))
57 return D_KBL;
58 else if (IS_BROXTON(gvt->dev_priv))
59 return D_BXT;
60 else if (IS_COFFEELAKE(gvt->dev_priv))
61 return D_CFL;
62
63 return 0;
64 }
65
66 bool intel_gvt_match_device(struct intel_gvt *gvt,
67 unsigned long device)
68 {
69 return intel_gvt_get_device_type(gvt) & device;
70 }
71
72 static void read_vreg(struct intel_vgpu *vgpu, unsigned int offset,
73 void *p_data, unsigned int bytes)
74 {
75 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
76 }
77
78 static void write_vreg(struct intel_vgpu *vgpu, unsigned int offset,
79 void *p_data, unsigned int bytes)
80 {
81 memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes);
82 }
83
84 static struct intel_gvt_mmio_info *find_mmio_info(struct intel_gvt *gvt,
85 unsigned int offset)
86 {
87 struct intel_gvt_mmio_info *e;
88
89 hash_for_each_possible(gvt->mmio.mmio_info_table, e, node, offset) {
90 if (e->offset == offset)
91 return e;
92 }
93 return NULL;
94 }
95
96 static int new_mmio_info(struct intel_gvt *gvt,
97 u32 offset, u8 flags, u32 size,
98 u32 addr_mask, u32 ro_mask, u32 device,
99 gvt_mmio_func read, gvt_mmio_func write)
100 {
101 struct intel_gvt_mmio_info *info, *p;
102 u32 start, end, i;
103
104 if (!intel_gvt_match_device(gvt, device))
105 return 0;
106
107 if (WARN_ON(!IS_ALIGNED(offset, 4)))
108 return -EINVAL;
109
110 start = offset;
111 end = offset + size;
112
113 for (i = start; i < end; i += 4) {
114 info = kzalloc(sizeof(*info), GFP_KERNEL);
115 if (!info)
116 return -ENOMEM;
117
118 info->offset = i;
119 p = find_mmio_info(gvt, info->offset);
120 if (p) {
121 WARN(1, "dup mmio definition offset %x\n",
122 info->offset);
123 kfree(info);
124
125 /* We return -EEXIST here to make GVT-g load fail.
126 * So duplicated MMIO can be found as soon as
127 * possible.
128 */
129 return -EEXIST;
130 }
131
132 info->ro_mask = ro_mask;
133 info->device = device;
134 info->read = read ? read : intel_vgpu_default_mmio_read;
135 info->write = write ? write : intel_vgpu_default_mmio_write;
136 gvt->mmio.mmio_attribute[info->offset / 4] = flags;
137 INIT_HLIST_NODE(&info->node);
138 hash_add(gvt->mmio.mmio_info_table, &info->node, info->offset);
139 gvt->mmio.num_tracked_mmio++;
140 }
141 return 0;
142 }
143
144 /**
145 * intel_gvt_render_mmio_to_ring_id - convert a mmio offset into ring id
146 * @gvt: a GVT device
147 * @offset: register offset
148 *
149 * Returns:
150 * Ring ID on success, negative error code if failed.
151 */
152 int intel_gvt_render_mmio_to_ring_id(struct intel_gvt *gvt,
153 unsigned int offset)
154 {
155 enum intel_engine_id id;
156 struct intel_engine_cs *engine;
157
158 offset &= ~GENMASK(11, 0);
159 for_each_engine(engine, gvt->dev_priv, id) {
160 if (engine->mmio_base == offset)
161 return id;
162 }
163 return -ENODEV;
164 }
165
166 #define offset_to_fence_num(offset) \
167 ((offset - i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) >> 3)
168
169 #define fence_num_to_offset(num) \
170 (num * 8 + i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0)))
171
172
173 void enter_failsafe_mode(struct intel_vgpu *vgpu, int reason)
174 {
175 switch (reason) {
176 case GVT_FAILSAFE_UNSUPPORTED_GUEST:
177 pr_err("Detected your guest driver doesn't support GVT-g.\n");
178 break;
179 case GVT_FAILSAFE_INSUFFICIENT_RESOURCE:
180 pr_err("Graphics resource is not enough for the guest\n");
181 break;
182 case GVT_FAILSAFE_GUEST_ERR:
183 pr_err("GVT Internal error for the guest\n");
184 break;
185 default:
186 break;
187 }
188 pr_err("Now vgpu %d will enter failsafe mode.\n", vgpu->id);
189 vgpu->failsafe = true;
190 }
191
192 static int sanitize_fence_mmio_access(struct intel_vgpu *vgpu,
193 unsigned int fence_num, void *p_data, unsigned int bytes)
194 {
195 unsigned int max_fence = vgpu_fence_sz(vgpu);
196
197 if (fence_num >= max_fence) {
198 gvt_vgpu_err("access oob fence reg %d/%d\n",
199 fence_num, max_fence);
200
201 /* When guest access oob fence regs without access
202 * pv_info first, we treat guest not supporting GVT,
203 * and we will let vgpu enter failsafe mode.
204 */
205 if (!vgpu->pv_notified)
206 enter_failsafe_mode(vgpu,
207 GVT_FAILSAFE_UNSUPPORTED_GUEST);
208
209 memset(p_data, 0, bytes);
210 return -EINVAL;
211 }
212 return 0;
213 }
214
215 static int gamw_echo_dev_rw_ia_write(struct intel_vgpu *vgpu,
216 unsigned int offset, void *p_data, unsigned int bytes)
217 {
218 u32 ips = (*(u32 *)p_data) & GAMW_ECO_ENABLE_64K_IPS_FIELD;
219
220 if (INTEL_GEN(vgpu->gvt->dev_priv) <= 10) {
221 if (ips == GAMW_ECO_ENABLE_64K_IPS_FIELD)
222 gvt_dbg_core("vgpu%d: ips enabled\n", vgpu->id);
223 else if (!ips)
224 gvt_dbg_core("vgpu%d: ips disabled\n", vgpu->id);
225 else {
226 /* All engines must be enabled together for vGPU,
227 * since we don't know which engine the ppgtt will
228 * bind to when shadowing.
229 */
230 gvt_vgpu_err("Unsupported IPS setting %x, cannot enable 64K gtt.\n",
231 ips);
232 return -EINVAL;
233 }
234 }
235
236 write_vreg(vgpu, offset, p_data, bytes);
237 return 0;
238 }
239
240 static int fence_mmio_read(struct intel_vgpu *vgpu, unsigned int off,
241 void *p_data, unsigned int bytes)
242 {
243 int ret;
244
245 ret = sanitize_fence_mmio_access(vgpu, offset_to_fence_num(off),
246 p_data, bytes);
247 if (ret)
248 return ret;
249 read_vreg(vgpu, off, p_data, bytes);
250 return 0;
251 }
252
253 static int fence_mmio_write(struct intel_vgpu *vgpu, unsigned int off,
254 void *p_data, unsigned int bytes)
255 {
256 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
257 unsigned int fence_num = offset_to_fence_num(off);
258 int ret;
259
260 ret = sanitize_fence_mmio_access(vgpu, fence_num, p_data, bytes);
261 if (ret)
262 return ret;
263 write_vreg(vgpu, off, p_data, bytes);
264
265 mmio_hw_access_pre(dev_priv);
266 intel_vgpu_write_fence(vgpu, fence_num,
267 vgpu_vreg64(vgpu, fence_num_to_offset(fence_num)));
268 mmio_hw_access_post(dev_priv);
269 return 0;
270 }
271
272 #define CALC_MODE_MASK_REG(old, new) \
273 (((new) & GENMASK(31, 16)) \
274 | ((((old) & GENMASK(15, 0)) & ~((new) >> 16)) \
275 | ((new) & ((new) >> 16))))
276
277 static int mul_force_wake_write(struct intel_vgpu *vgpu,
278 unsigned int offset, void *p_data, unsigned int bytes)
279 {
280 u32 old, new;
281 u32 ack_reg_offset;
282
283 old = vgpu_vreg(vgpu, offset);
284 new = CALC_MODE_MASK_REG(old, *(u32 *)p_data);
285
286 if (INTEL_GEN(vgpu->gvt->dev_priv) >= 9) {
287 switch (offset) {
288 case FORCEWAKE_RENDER_GEN9_REG:
289 ack_reg_offset = FORCEWAKE_ACK_RENDER_GEN9_REG;
290 break;
291 case FORCEWAKE_BLITTER_GEN9_REG:
292 ack_reg_offset = FORCEWAKE_ACK_BLITTER_GEN9_REG;
293 break;
294 case FORCEWAKE_MEDIA_GEN9_REG:
295 ack_reg_offset = FORCEWAKE_ACK_MEDIA_GEN9_REG;
296 break;
297 default:
298 /*should not hit here*/
299 gvt_vgpu_err("invalid forcewake offset 0x%x\n", offset);
300 return -EINVAL;
301 }
302 } else {
303 ack_reg_offset = FORCEWAKE_ACK_HSW_REG;
304 }
305
306 vgpu_vreg(vgpu, offset) = new;
307 vgpu_vreg(vgpu, ack_reg_offset) = (new & GENMASK(15, 0));
308 return 0;
309 }
310
311 static int gdrst_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
312 void *p_data, unsigned int bytes)
313 {
314 unsigned int engine_mask = 0;
315 u32 data;
316
317 write_vreg(vgpu, offset, p_data, bytes);
318 data = vgpu_vreg(vgpu, offset);
319
320 if (data & GEN6_GRDOM_FULL) {
321 gvt_dbg_mmio("vgpu%d: request full GPU reset\n", vgpu->id);
322 engine_mask = ALL_ENGINES;
323 } else {
324 if (data & GEN6_GRDOM_RENDER) {
325 gvt_dbg_mmio("vgpu%d: request RCS reset\n", vgpu->id);
326 engine_mask |= (1 << RCS);
327 }
328 if (data & GEN6_GRDOM_MEDIA) {
329 gvt_dbg_mmio("vgpu%d: request VCS reset\n", vgpu->id);
330 engine_mask |= (1 << VCS);
331 }
332 if (data & GEN6_GRDOM_BLT) {
333 gvt_dbg_mmio("vgpu%d: request BCS Reset\n", vgpu->id);
334 engine_mask |= (1 << BCS);
335 }
336 if (data & GEN6_GRDOM_VECS) {
337 gvt_dbg_mmio("vgpu%d: request VECS Reset\n", vgpu->id);
338 engine_mask |= (1 << VECS);
339 }
340 if (data & GEN8_GRDOM_MEDIA2) {
341 gvt_dbg_mmio("vgpu%d: request VCS2 Reset\n", vgpu->id);
342 if (HAS_BSD2(vgpu->gvt->dev_priv))
343 engine_mask |= (1 << VCS2);
344 }
345 }
346
347 /* vgpu_lock already hold by emulate mmio r/w */
348 intel_gvt_reset_vgpu_locked(vgpu, false, engine_mask);
349
350 /* sw will wait for the device to ack the reset request */
351 vgpu_vreg(vgpu, offset) = 0;
352
353 return 0;
354 }
355
356 static int gmbus_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
357 void *p_data, unsigned int bytes)
358 {
359 return intel_gvt_i2c_handle_gmbus_read(vgpu, offset, p_data, bytes);
360 }
361
362 static int gmbus_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
363 void *p_data, unsigned int bytes)
364 {
365 return intel_gvt_i2c_handle_gmbus_write(vgpu, offset, p_data, bytes);
366 }
367
368 static int pch_pp_control_mmio_write(struct intel_vgpu *vgpu,
369 unsigned int offset, void *p_data, unsigned int bytes)
370 {
371 write_vreg(vgpu, offset, p_data, bytes);
372
373 if (vgpu_vreg(vgpu, offset) & PANEL_POWER_ON) {
374 vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_ON;
375 vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_SEQUENCE_STATE_ON_IDLE;
376 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_SEQUENCE_POWER_DOWN;
377 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_CYCLE_DELAY_ACTIVE;
378
379 } else
380 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &=
381 ~(PP_ON | PP_SEQUENCE_POWER_DOWN
382 | PP_CYCLE_DELAY_ACTIVE);
383 return 0;
384 }
385
386 static int transconf_mmio_write(struct intel_vgpu *vgpu,
387 unsigned int offset, void *p_data, unsigned int bytes)
388 {
389 write_vreg(vgpu, offset, p_data, bytes);
390
391 if (vgpu_vreg(vgpu, offset) & TRANS_ENABLE)
392 vgpu_vreg(vgpu, offset) |= TRANS_STATE_ENABLE;
393 else
394 vgpu_vreg(vgpu, offset) &= ~TRANS_STATE_ENABLE;
395 return 0;
396 }
397
398 static int lcpll_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
399 void *p_data, unsigned int bytes)
400 {
401 write_vreg(vgpu, offset, p_data, bytes);
402
403 if (vgpu_vreg(vgpu, offset) & LCPLL_PLL_DISABLE)
404 vgpu_vreg(vgpu, offset) &= ~LCPLL_PLL_LOCK;
405 else
406 vgpu_vreg(vgpu, offset) |= LCPLL_PLL_LOCK;
407
408 if (vgpu_vreg(vgpu, offset) & LCPLL_CD_SOURCE_FCLK)
409 vgpu_vreg(vgpu, offset) |= LCPLL_CD_SOURCE_FCLK_DONE;
410 else
411 vgpu_vreg(vgpu, offset) &= ~LCPLL_CD_SOURCE_FCLK_DONE;
412
413 return 0;
414 }
415
416 static int dpy_reg_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
417 void *p_data, unsigned int bytes)
418 {
419 switch (offset) {
420 case 0xe651c:
421 case 0xe661c:
422 case 0xe671c:
423 case 0xe681c:
424 vgpu_vreg(vgpu, offset) = 1 << 17;
425 break;
426 case 0xe6c04:
427 vgpu_vreg(vgpu, offset) = 0x3;
428 break;
429 case 0xe6e1c:
430 vgpu_vreg(vgpu, offset) = 0x2f << 16;
431 break;
432 default:
433 return -EINVAL;
434 }
435
436 read_vreg(vgpu, offset, p_data, bytes);
437 return 0;
438 }
439
440 static int pipeconf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
441 void *p_data, unsigned int bytes)
442 {
443 u32 data;
444
445 write_vreg(vgpu, offset, p_data, bytes);
446 data = vgpu_vreg(vgpu, offset);
447
448 if (data & PIPECONF_ENABLE)
449 vgpu_vreg(vgpu, offset) |= I965_PIPECONF_ACTIVE;
450 else
451 vgpu_vreg(vgpu, offset) &= ~I965_PIPECONF_ACTIVE;
452 /* vgpu_lock already hold by emulate mmio r/w */
453 mutex_unlock(&vgpu->vgpu_lock);
454 intel_gvt_check_vblank_emulation(vgpu->gvt);
455 mutex_lock(&vgpu->vgpu_lock);
456 return 0;
457 }
458
459 /* ascendingly sorted */
460 static i915_reg_t force_nonpriv_white_list[] = {
461 GEN9_CS_DEBUG_MODE1, //_MMIO(0x20ec)
462 GEN9_CTX_PREEMPT_REG,//_MMIO(0x2248)
463 GEN8_CS_CHICKEN1,//_MMIO(0x2580)
464 _MMIO(0x2690),
465 _MMIO(0x2694),
466 _MMIO(0x2698),
467 _MMIO(0x4de0),
468 _MMIO(0x4de4),
469 _MMIO(0x4dfc),
470 GEN7_COMMON_SLICE_CHICKEN1,//_MMIO(0x7010)
471 _MMIO(0x7014),
472 HDC_CHICKEN0,//_MMIO(0x7300)
473 GEN8_HDC_CHICKEN1,//_MMIO(0x7304)
474 _MMIO(0x7700),
475 _MMIO(0x7704),
476 _MMIO(0x7708),
477 _MMIO(0x770c),
478 _MMIO(0x83a8),
479 _MMIO(0xb110),
480 GEN8_L3SQCREG4,//_MMIO(0xb118)
481 _MMIO(0xe100),
482 _MMIO(0xe18c),
483 _MMIO(0xe48c),
484 _MMIO(0xe5f4),
485 };
486
487 /* a simple bsearch */
488 static inline bool in_whitelist(unsigned int reg)
489 {
490 int left = 0, right = ARRAY_SIZE(force_nonpriv_white_list);
491 i915_reg_t *array = force_nonpriv_white_list;
492
493 while (left < right) {
494 int mid = (left + right)/2;
495
496 if (reg > array[mid].reg)
497 left = mid + 1;
498 else if (reg < array[mid].reg)
499 right = mid;
500 else
501 return true;
502 }
503 return false;
504 }
505
506 static int force_nonpriv_write(struct intel_vgpu *vgpu,
507 unsigned int offset, void *p_data, unsigned int bytes)
508 {
509 u32 reg_nonpriv = *(u32 *)p_data;
510 int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset);
511 u32 ring_base;
512 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
513 int ret = -EINVAL;
514
515 if ((bytes != 4) || ((offset & (bytes - 1)) != 0) || ring_id < 0) {
516 gvt_err("vgpu(%d) ring %d Invalid FORCE_NONPRIV offset %x(%dB)\n",
517 vgpu->id, ring_id, offset, bytes);
518 return ret;
519 }
520
521 ring_base = dev_priv->engine[ring_id]->mmio_base;
522
523 if (in_whitelist(reg_nonpriv) ||
524 reg_nonpriv == i915_mmio_reg_offset(RING_NOPID(ring_base))) {
525 ret = intel_vgpu_default_mmio_write(vgpu, offset, p_data,
526 bytes);
527 } else
528 gvt_err("vgpu(%d) Invalid FORCE_NONPRIV write %x at offset %x\n",
529 vgpu->id, reg_nonpriv, offset);
530
531 return 0;
532 }
533
534 static int ddi_buf_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
535 void *p_data, unsigned int bytes)
536 {
537 write_vreg(vgpu, offset, p_data, bytes);
538
539 if (vgpu_vreg(vgpu, offset) & DDI_BUF_CTL_ENABLE) {
540 vgpu_vreg(vgpu, offset) &= ~DDI_BUF_IS_IDLE;
541 } else {
542 vgpu_vreg(vgpu, offset) |= DDI_BUF_IS_IDLE;
543 if (offset == i915_mmio_reg_offset(DDI_BUF_CTL(PORT_E)))
544 vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E))
545 &= ~DP_TP_STATUS_AUTOTRAIN_DONE;
546 }
547 return 0;
548 }
549
550 static int fdi_rx_iir_mmio_write(struct intel_vgpu *vgpu,
551 unsigned int offset, void *p_data, unsigned int bytes)
552 {
553 vgpu_vreg(vgpu, offset) &= ~*(u32 *)p_data;
554 return 0;
555 }
556
557 #define FDI_LINK_TRAIN_PATTERN1 0
558 #define FDI_LINK_TRAIN_PATTERN2 1
559
560 static int fdi_auto_training_started(struct intel_vgpu *vgpu)
561 {
562 u32 ddi_buf_ctl = vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_E));
563 u32 rx_ctl = vgpu_vreg(vgpu, _FDI_RXA_CTL);
564 u32 tx_ctl = vgpu_vreg_t(vgpu, DP_TP_CTL(PORT_E));
565
566 if ((ddi_buf_ctl & DDI_BUF_CTL_ENABLE) &&
567 (rx_ctl & FDI_RX_ENABLE) &&
568 (rx_ctl & FDI_AUTO_TRAINING) &&
569 (tx_ctl & DP_TP_CTL_ENABLE) &&
570 (tx_ctl & DP_TP_CTL_FDI_AUTOTRAIN))
571 return 1;
572 else
573 return 0;
574 }
575
576 static int check_fdi_rx_train_status(struct intel_vgpu *vgpu,
577 enum pipe pipe, unsigned int train_pattern)
578 {
579 i915_reg_t fdi_rx_imr, fdi_tx_ctl, fdi_rx_ctl;
580 unsigned int fdi_rx_check_bits, fdi_tx_check_bits;
581 unsigned int fdi_rx_train_bits, fdi_tx_train_bits;
582 unsigned int fdi_iir_check_bits;
583
584 fdi_rx_imr = FDI_RX_IMR(pipe);
585 fdi_tx_ctl = FDI_TX_CTL(pipe);
586 fdi_rx_ctl = FDI_RX_CTL(pipe);
587
588 if (train_pattern == FDI_LINK_TRAIN_PATTERN1) {
589 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_1_CPT;
590 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_1;
591 fdi_iir_check_bits = FDI_RX_BIT_LOCK;
592 } else if (train_pattern == FDI_LINK_TRAIN_PATTERN2) {
593 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_2_CPT;
594 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_2;
595 fdi_iir_check_bits = FDI_RX_SYMBOL_LOCK;
596 } else {
597 gvt_vgpu_err("Invalid train pattern %d\n", train_pattern);
598 return -EINVAL;
599 }
600
601 fdi_rx_check_bits = FDI_RX_ENABLE | fdi_rx_train_bits;
602 fdi_tx_check_bits = FDI_TX_ENABLE | fdi_tx_train_bits;
603
604 /* If imr bit has been masked */
605 if (vgpu_vreg_t(vgpu, fdi_rx_imr) & fdi_iir_check_bits)
606 return 0;
607
608 if (((vgpu_vreg_t(vgpu, fdi_tx_ctl) & fdi_tx_check_bits)
609 == fdi_tx_check_bits)
610 && ((vgpu_vreg_t(vgpu, fdi_rx_ctl) & fdi_rx_check_bits)
611 == fdi_rx_check_bits))
612 return 1;
613 else
614 return 0;
615 }
616
617 #define INVALID_INDEX (~0U)
618
619 static unsigned int calc_index(unsigned int offset, unsigned int start,
620 unsigned int next, unsigned int end, i915_reg_t i915_end)
621 {
622 unsigned int range = next - start;
623
624 if (!end)
625 end = i915_mmio_reg_offset(i915_end);
626 if (offset < start || offset > end)
627 return INVALID_INDEX;
628 offset -= start;
629 return offset / range;
630 }
631
632 #define FDI_RX_CTL_TO_PIPE(offset) \
633 calc_index(offset, _FDI_RXA_CTL, _FDI_RXB_CTL, 0, FDI_RX_CTL(PIPE_C))
634
635 #define FDI_TX_CTL_TO_PIPE(offset) \
636 calc_index(offset, _FDI_TXA_CTL, _FDI_TXB_CTL, 0, FDI_TX_CTL(PIPE_C))
637
638 #define FDI_RX_IMR_TO_PIPE(offset) \
639 calc_index(offset, _FDI_RXA_IMR, _FDI_RXB_IMR, 0, FDI_RX_IMR(PIPE_C))
640
641 static int update_fdi_rx_iir_status(struct intel_vgpu *vgpu,
642 unsigned int offset, void *p_data, unsigned int bytes)
643 {
644 i915_reg_t fdi_rx_iir;
645 unsigned int index;
646 int ret;
647
648 if (FDI_RX_CTL_TO_PIPE(offset) != INVALID_INDEX)
649 index = FDI_RX_CTL_TO_PIPE(offset);
650 else if (FDI_TX_CTL_TO_PIPE(offset) != INVALID_INDEX)
651 index = FDI_TX_CTL_TO_PIPE(offset);
652 else if (FDI_RX_IMR_TO_PIPE(offset) != INVALID_INDEX)
653 index = FDI_RX_IMR_TO_PIPE(offset);
654 else {
655 gvt_vgpu_err("Unsupport registers %x\n", offset);
656 return -EINVAL;
657 }
658
659 write_vreg(vgpu, offset, p_data, bytes);
660
661 fdi_rx_iir = FDI_RX_IIR(index);
662
663 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN1);
664 if (ret < 0)
665 return ret;
666 if (ret)
667 vgpu_vreg_t(vgpu, fdi_rx_iir) |= FDI_RX_BIT_LOCK;
668
669 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN2);
670 if (ret < 0)
671 return ret;
672 if (ret)
673 vgpu_vreg_t(vgpu, fdi_rx_iir) |= FDI_RX_SYMBOL_LOCK;
674
675 if (offset == _FDI_RXA_CTL)
676 if (fdi_auto_training_started(vgpu))
677 vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E)) |=
678 DP_TP_STATUS_AUTOTRAIN_DONE;
679 return 0;
680 }
681
682 #define DP_TP_CTL_TO_PORT(offset) \
683 calc_index(offset, _DP_TP_CTL_A, _DP_TP_CTL_B, 0, DP_TP_CTL(PORT_E))
684
685 static int dp_tp_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
686 void *p_data, unsigned int bytes)
687 {
688 i915_reg_t status_reg;
689 unsigned int index;
690 u32 data;
691
692 write_vreg(vgpu, offset, p_data, bytes);
693
694 index = DP_TP_CTL_TO_PORT(offset);
695 data = (vgpu_vreg(vgpu, offset) & GENMASK(10, 8)) >> 8;
696 if (data == 0x2) {
697 status_reg = DP_TP_STATUS(index);
698 vgpu_vreg_t(vgpu, status_reg) |= (1 << 25);
699 }
700 return 0;
701 }
702
703 static int dp_tp_status_mmio_write(struct intel_vgpu *vgpu,
704 unsigned int offset, void *p_data, unsigned int bytes)
705 {
706 u32 reg_val;
707 u32 sticky_mask;
708
709 reg_val = *((u32 *)p_data);
710 sticky_mask = GENMASK(27, 26) | (1 << 24);
711
712 vgpu_vreg(vgpu, offset) = (reg_val & ~sticky_mask) |
713 (vgpu_vreg(vgpu, offset) & sticky_mask);
714 vgpu_vreg(vgpu, offset) &= ~(reg_val & sticky_mask);
715 return 0;
716 }
717
718 static int pch_adpa_mmio_write(struct intel_vgpu *vgpu,
719 unsigned int offset, void *p_data, unsigned int bytes)
720 {
721 u32 data;
722
723 write_vreg(vgpu, offset, p_data, bytes);
724 data = vgpu_vreg(vgpu, offset);
725
726 if (data & ADPA_CRT_HOTPLUG_FORCE_TRIGGER)
727 vgpu_vreg(vgpu, offset) &= ~ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
728 return 0;
729 }
730
731 static int south_chicken2_mmio_write(struct intel_vgpu *vgpu,
732 unsigned int offset, void *p_data, unsigned int bytes)
733 {
734 u32 data;
735
736 write_vreg(vgpu, offset, p_data, bytes);
737 data = vgpu_vreg(vgpu, offset);
738
739 if (data & FDI_MPHY_IOSFSB_RESET_CTL)
740 vgpu_vreg(vgpu, offset) |= FDI_MPHY_IOSFSB_RESET_STATUS;
741 else
742 vgpu_vreg(vgpu, offset) &= ~FDI_MPHY_IOSFSB_RESET_STATUS;
743 return 0;
744 }
745
746 #define DSPSURF_TO_PIPE(offset) \
747 calc_index(offset, _DSPASURF, _DSPBSURF, 0, DSPSURF(PIPE_C))
748
749 static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
750 void *p_data, unsigned int bytes)
751 {
752 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
753 unsigned int index = DSPSURF_TO_PIPE(offset);
754 i915_reg_t surflive_reg = DSPSURFLIVE(index);
755 int flip_event[] = {
756 [PIPE_A] = PRIMARY_A_FLIP_DONE,
757 [PIPE_B] = PRIMARY_B_FLIP_DONE,
758 [PIPE_C] = PRIMARY_C_FLIP_DONE,
759 };
760
761 write_vreg(vgpu, offset, p_data, bytes);
762 vgpu_vreg_t(vgpu, surflive_reg) = vgpu_vreg(vgpu, offset);
763
764 set_bit(flip_event[index], vgpu->irq.flip_done_event[index]);
765 return 0;
766 }
767
768 #define SPRSURF_TO_PIPE(offset) \
769 calc_index(offset, _SPRA_SURF, _SPRB_SURF, 0, SPRSURF(PIPE_C))
770
771 static int spr_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
772 void *p_data, unsigned int bytes)
773 {
774 unsigned int index = SPRSURF_TO_PIPE(offset);
775 i915_reg_t surflive_reg = SPRSURFLIVE(index);
776 int flip_event[] = {
777 [PIPE_A] = SPRITE_A_FLIP_DONE,
778 [PIPE_B] = SPRITE_B_FLIP_DONE,
779 [PIPE_C] = SPRITE_C_FLIP_DONE,
780 };
781
782 write_vreg(vgpu, offset, p_data, bytes);
783 vgpu_vreg_t(vgpu, surflive_reg) = vgpu_vreg(vgpu, offset);
784
785 set_bit(flip_event[index], vgpu->irq.flip_done_event[index]);
786 return 0;
787 }
788
789 static int trigger_aux_channel_interrupt(struct intel_vgpu *vgpu,
790 unsigned int reg)
791 {
792 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
793 enum intel_gvt_event_type event;
794
795 if (reg == _DPA_AUX_CH_CTL)
796 event = AUX_CHANNEL_A;
797 else if (reg == _PCH_DPB_AUX_CH_CTL || reg == _DPB_AUX_CH_CTL)
798 event = AUX_CHANNEL_B;
799 else if (reg == _PCH_DPC_AUX_CH_CTL || reg == _DPC_AUX_CH_CTL)
800 event = AUX_CHANNEL_C;
801 else if (reg == _PCH_DPD_AUX_CH_CTL || reg == _DPD_AUX_CH_CTL)
802 event = AUX_CHANNEL_D;
803 else {
804 WARN_ON(true);
805 return -EINVAL;
806 }
807
808 intel_vgpu_trigger_virtual_event(vgpu, event);
809 return 0;
810 }
811
812 static int dp_aux_ch_ctl_trans_done(struct intel_vgpu *vgpu, u32 value,
813 unsigned int reg, int len, bool data_valid)
814 {
815 /* mark transaction done */
816 value |= DP_AUX_CH_CTL_DONE;
817 value &= ~DP_AUX_CH_CTL_SEND_BUSY;
818 value &= ~DP_AUX_CH_CTL_RECEIVE_ERROR;
819
820 if (data_valid)
821 value &= ~DP_AUX_CH_CTL_TIME_OUT_ERROR;
822 else
823 value |= DP_AUX_CH_CTL_TIME_OUT_ERROR;
824
825 /* message size */
826 value &= ~(0xf << 20);
827 value |= (len << 20);
828 vgpu_vreg(vgpu, reg) = value;
829
830 if (value & DP_AUX_CH_CTL_INTERRUPT)
831 return trigger_aux_channel_interrupt(vgpu, reg);
832 return 0;
833 }
834
835 static void dp_aux_ch_ctl_link_training(struct intel_vgpu_dpcd_data *dpcd,
836 u8 t)
837 {
838 if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == DPCD_TRAINING_PATTERN_1) {
839 /* training pattern 1 for CR */
840 /* set LANE0_CR_DONE, LANE1_CR_DONE */
841 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_CR_DONE;
842 /* set LANE2_CR_DONE, LANE3_CR_DONE */
843 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_CR_DONE;
844 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) ==
845 DPCD_TRAINING_PATTERN_2) {
846 /* training pattern 2 for EQ */
847 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane0_1 */
848 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_EQ_DONE;
849 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_SYMBOL_LOCKED;
850 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane2_3 */
851 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_EQ_DONE;
852 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_SYMBOL_LOCKED;
853 /* set INTERLANE_ALIGN_DONE */
854 dpcd->data[DPCD_LANE_ALIGN_STATUS_UPDATED] |=
855 DPCD_INTERLANE_ALIGN_DONE;
856 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) ==
857 DPCD_LINK_TRAINING_DISABLED) {
858 /* finish link training */
859 /* set sink status as synchronized */
860 dpcd->data[DPCD_SINK_STATUS] = DPCD_SINK_IN_SYNC;
861 }
862 }
863
864 #define _REG_HSW_DP_AUX_CH_CTL(dp) \
865 ((dp) ? (_PCH_DPB_AUX_CH_CTL + ((dp)-1)*0x100) : 0x64010)
866
867 #define _REG_SKL_DP_AUX_CH_CTL(dp) (0x64010 + (dp) * 0x100)
868
869 #define OFFSET_TO_DP_AUX_PORT(offset) (((offset) & 0xF00) >> 8)
870
871 #define dpy_is_valid_port(port) \
872 (((port) >= PORT_A) && ((port) < I915_MAX_PORTS))
873
874 static int dp_aux_ch_ctl_mmio_write(struct intel_vgpu *vgpu,
875 unsigned int offset, void *p_data, unsigned int bytes)
876 {
877 struct intel_vgpu_display *display = &vgpu->display;
878 int msg, addr, ctrl, op, len;
879 int port_index = OFFSET_TO_DP_AUX_PORT(offset);
880 struct intel_vgpu_dpcd_data *dpcd = NULL;
881 struct intel_vgpu_port *port = NULL;
882 u32 data;
883
884 if (!dpy_is_valid_port(port_index)) {
885 gvt_vgpu_err("Unsupported DP port access!\n");
886 return 0;
887 }
888
889 write_vreg(vgpu, offset, p_data, bytes);
890 data = vgpu_vreg(vgpu, offset);
891
892 if ((INTEL_GEN(vgpu->gvt->dev_priv) >= 9)
893 && offset != _REG_SKL_DP_AUX_CH_CTL(port_index)) {
894 /* SKL DPB/C/D aux ctl register changed */
895 return 0;
896 } else if (IS_BROADWELL(vgpu->gvt->dev_priv) &&
897 offset != _REG_HSW_DP_AUX_CH_CTL(port_index)) {
898 /* write to the data registers */
899 return 0;
900 }
901
902 if (!(data & DP_AUX_CH_CTL_SEND_BUSY)) {
903 /* just want to clear the sticky bits */
904 vgpu_vreg(vgpu, offset) = 0;
905 return 0;
906 }
907
908 port = &display->ports[port_index];
909 dpcd = port->dpcd;
910
911 /* read out message from DATA1 register */
912 msg = vgpu_vreg(vgpu, offset + 4);
913 addr = (msg >> 8) & 0xffff;
914 ctrl = (msg >> 24) & 0xff;
915 len = msg & 0xff;
916 op = ctrl >> 4;
917
918 if (op == GVT_AUX_NATIVE_WRITE) {
919 int t;
920 u8 buf[16];
921
922 if ((addr + len + 1) >= DPCD_SIZE) {
923 /*
924 * Write request exceeds what we supported,
925 * DCPD spec: When a Source Device is writing a DPCD
926 * address not supported by the Sink Device, the Sink
927 * Device shall reply with AUX NACK and “M” equal to
928 * zero.
929 */
930
931 /* NAK the write */
932 vgpu_vreg(vgpu, offset + 4) = AUX_NATIVE_REPLY_NAK;
933 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 2, true);
934 return 0;
935 }
936
937 /*
938 * Write request format: Headr (command + address + size) occupies
939 * 4 bytes, followed by (len + 1) bytes of data. See details at
940 * intel_dp_aux_transfer().
941 */
942 if ((len + 1 + 4) > AUX_BURST_SIZE) {
943 gvt_vgpu_err("dp_aux_header: len %d is too large\n", len);
944 return -EINVAL;
945 }
946
947 /* unpack data from vreg to buf */
948 for (t = 0; t < 4; t++) {
949 u32 r = vgpu_vreg(vgpu, offset + 8 + t * 4);
950
951 buf[t * 4] = (r >> 24) & 0xff;
952 buf[t * 4 + 1] = (r >> 16) & 0xff;
953 buf[t * 4 + 2] = (r >> 8) & 0xff;
954 buf[t * 4 + 3] = r & 0xff;
955 }
956
957 /* write to virtual DPCD */
958 if (dpcd && dpcd->data_valid) {
959 for (t = 0; t <= len; t++) {
960 int p = addr + t;
961
962 dpcd->data[p] = buf[t];
963 /* check for link training */
964 if (p == DPCD_TRAINING_PATTERN_SET)
965 dp_aux_ch_ctl_link_training(dpcd,
966 buf[t]);
967 }
968 }
969
970 /* ACK the write */
971 vgpu_vreg(vgpu, offset + 4) = 0;
972 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 1,
973 dpcd && dpcd->data_valid);
974 return 0;
975 }
976
977 if (op == GVT_AUX_NATIVE_READ) {
978 int idx, i, ret = 0;
979
980 if ((addr + len + 1) >= DPCD_SIZE) {
981 /*
982 * read request exceeds what we supported
983 * DPCD spec: A Sink Device receiving a Native AUX CH
984 * read request for an unsupported DPCD address must
985 * reply with an AUX ACK and read data set equal to
986 * zero instead of replying with AUX NACK.
987 */
988
989 /* ACK the READ*/
990 vgpu_vreg(vgpu, offset + 4) = 0;
991 vgpu_vreg(vgpu, offset + 8) = 0;
992 vgpu_vreg(vgpu, offset + 12) = 0;
993 vgpu_vreg(vgpu, offset + 16) = 0;
994 vgpu_vreg(vgpu, offset + 20) = 0;
995
996 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2,
997 true);
998 return 0;
999 }
1000
1001 for (idx = 1; idx <= 5; idx++) {
1002 /* clear the data registers */
1003 vgpu_vreg(vgpu, offset + 4 * idx) = 0;
1004 }
1005
1006 /*
1007 * Read reply format: ACK (1 byte) plus (len + 1) bytes of data.
1008 */
1009 if ((len + 2) > AUX_BURST_SIZE) {
1010 gvt_vgpu_err("dp_aux_header: len %d is too large\n", len);
1011 return -EINVAL;
1012 }
1013
1014 /* read from virtual DPCD to vreg */
1015 /* first 4 bytes: [ACK][addr][addr+1][addr+2] */
1016 if (dpcd && dpcd->data_valid) {
1017 for (i = 1; i <= (len + 1); i++) {
1018 int t;
1019
1020 t = dpcd->data[addr + i - 1];
1021 t <<= (24 - 8 * (i % 4));
1022 ret |= t;
1023
1024 if ((i % 4 == 3) || (i == (len + 1))) {
1025 vgpu_vreg(vgpu, offset +
1026 (i / 4 + 1) * 4) = ret;
1027 ret = 0;
1028 }
1029 }
1030 }
1031 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2,
1032 dpcd && dpcd->data_valid);
1033 return 0;
1034 }
1035
1036 /* i2c transaction starts */
1037 intel_gvt_i2c_handle_aux_ch_write(vgpu, port_index, offset, p_data);
1038
1039 if (data & DP_AUX_CH_CTL_INTERRUPT)
1040 trigger_aux_channel_interrupt(vgpu, offset);
1041 return 0;
1042 }
1043
1044 static int mbctl_write(struct intel_vgpu *vgpu, unsigned int offset,
1045 void *p_data, unsigned int bytes)
1046 {
1047 *(u32 *)p_data &= (~GEN6_MBCTL_ENABLE_BOOT_FETCH);
1048 write_vreg(vgpu, offset, p_data, bytes);
1049 return 0;
1050 }
1051
1052 static int vga_control_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1053 void *p_data, unsigned int bytes)
1054 {
1055 bool vga_disable;
1056
1057 write_vreg(vgpu, offset, p_data, bytes);
1058 vga_disable = vgpu_vreg(vgpu, offset) & VGA_DISP_DISABLE;
1059
1060 gvt_dbg_core("vgpu%d: %s VGA mode\n", vgpu->id,
1061 vga_disable ? "Disable" : "Enable");
1062 return 0;
1063 }
1064
1065 static u32 read_virtual_sbi_register(struct intel_vgpu *vgpu,
1066 unsigned int sbi_offset)
1067 {
1068 struct intel_vgpu_display *display = &vgpu->display;
1069 int num = display->sbi.number;
1070 int i;
1071
1072 for (i = 0; i < num; ++i)
1073 if (display->sbi.registers[i].offset == sbi_offset)
1074 break;
1075
1076 if (i == num)
1077 return 0;
1078
1079 return display->sbi.registers[i].value;
1080 }
1081
1082 static void write_virtual_sbi_register(struct intel_vgpu *vgpu,
1083 unsigned int offset, u32 value)
1084 {
1085 struct intel_vgpu_display *display = &vgpu->display;
1086 int num = display->sbi.number;
1087 int i;
1088
1089 for (i = 0; i < num; ++i) {
1090 if (display->sbi.registers[i].offset == offset)
1091 break;
1092 }
1093
1094 if (i == num) {
1095 if (num == SBI_REG_MAX) {
1096 gvt_vgpu_err("SBI caching meets maximum limits\n");
1097 return;
1098 }
1099 display->sbi.number++;
1100 }
1101
1102 display->sbi.registers[i].offset = offset;
1103 display->sbi.registers[i].value = value;
1104 }
1105
1106 static int sbi_data_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
1107 void *p_data, unsigned int bytes)
1108 {
1109 if (((vgpu_vreg_t(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >>
1110 SBI_OPCODE_SHIFT) == SBI_CMD_CRRD) {
1111 unsigned int sbi_offset = (vgpu_vreg_t(vgpu, SBI_ADDR) &
1112 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT;
1113 vgpu_vreg(vgpu, offset) = read_virtual_sbi_register(vgpu,
1114 sbi_offset);
1115 }
1116 read_vreg(vgpu, offset, p_data, bytes);
1117 return 0;
1118 }
1119
1120 static int sbi_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1121 void *p_data, unsigned int bytes)
1122 {
1123 u32 data;
1124
1125 write_vreg(vgpu, offset, p_data, bytes);
1126 data = vgpu_vreg(vgpu, offset);
1127
1128 data &= ~(SBI_STAT_MASK << SBI_STAT_SHIFT);
1129 data |= SBI_READY;
1130
1131 data &= ~(SBI_RESPONSE_MASK << SBI_RESPONSE_SHIFT);
1132 data |= SBI_RESPONSE_SUCCESS;
1133
1134 vgpu_vreg(vgpu, offset) = data;
1135
1136 if (((vgpu_vreg_t(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >>
1137 SBI_OPCODE_SHIFT) == SBI_CMD_CRWR) {
1138 unsigned int sbi_offset = (vgpu_vreg_t(vgpu, SBI_ADDR) &
1139 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT;
1140
1141 write_virtual_sbi_register(vgpu, sbi_offset,
1142 vgpu_vreg_t(vgpu, SBI_DATA));
1143 }
1144 return 0;
1145 }
1146
1147 #define _vgtif_reg(x) \
1148 (VGT_PVINFO_PAGE + offsetof(struct vgt_if, x))
1149
1150 static int pvinfo_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
1151 void *p_data, unsigned int bytes)
1152 {
1153 bool invalid_read = false;
1154
1155 read_vreg(vgpu, offset, p_data, bytes);
1156
1157 switch (offset) {
1158 case _vgtif_reg(magic) ... _vgtif_reg(vgt_id):
1159 if (offset + bytes > _vgtif_reg(vgt_id) + 4)
1160 invalid_read = true;
1161 break;
1162 case _vgtif_reg(avail_rs.mappable_gmadr.base) ...
1163 _vgtif_reg(avail_rs.fence_num):
1164 if (offset + bytes >
1165 _vgtif_reg(avail_rs.fence_num) + 4)
1166 invalid_read = true;
1167 break;
1168 case 0x78010: /* vgt_caps */
1169 case 0x7881c:
1170 break;
1171 default:
1172 invalid_read = true;
1173 break;
1174 }
1175 if (invalid_read)
1176 gvt_vgpu_err("invalid pvinfo read: [%x:%x] = %x\n",
1177 offset, bytes, *(u32 *)p_data);
1178 vgpu->pv_notified = true;
1179 return 0;
1180 }
1181
1182 static int handle_g2v_notification(struct intel_vgpu *vgpu, int notification)
1183 {
1184 intel_gvt_gtt_type_t root_entry_type = GTT_TYPE_PPGTT_ROOT_L4_ENTRY;
1185 struct intel_vgpu_mm *mm;
1186 u64 *pdps;
1187
1188 pdps = (u64 *)&vgpu_vreg64_t(vgpu, vgtif_reg(pdp[0]));
1189
1190 switch (notification) {
1191 case VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE:
1192 root_entry_type = GTT_TYPE_PPGTT_ROOT_L3_ENTRY;
1193 /* fall through */
1194 case VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE:
1195 mm = intel_vgpu_get_ppgtt_mm(vgpu, root_entry_type, pdps);
1196 return PTR_ERR_OR_ZERO(mm);
1197 case VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY:
1198 case VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY:
1199 return intel_vgpu_put_ppgtt_mm(vgpu, pdps);
1200 case VGT_G2V_EXECLIST_CONTEXT_CREATE:
1201 case VGT_G2V_EXECLIST_CONTEXT_DESTROY:
1202 case 1: /* Remove this in guest driver. */
1203 break;
1204 default:
1205 gvt_vgpu_err("Invalid PV notification %d\n", notification);
1206 }
1207 return 0;
1208 }
1209
1210 static int send_display_ready_uevent(struct intel_vgpu *vgpu, int ready)
1211 {
1212 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
1213 struct kobject *kobj = &dev_priv->drm.primary->kdev->kobj;
1214 char *env[3] = {NULL, NULL, NULL};
1215 char vmid_str[20];
1216 char display_ready_str[20];
1217
1218 snprintf(display_ready_str, 20, "GVT_DISPLAY_READY=%d", ready);
1219 env[0] = display_ready_str;
1220
1221 snprintf(vmid_str, 20, "VMID=%d", vgpu->id);
1222 env[1] = vmid_str;
1223
1224 return kobject_uevent_env(kobj, KOBJ_ADD, env);
1225 }
1226
1227 static int pvinfo_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1228 void *p_data, unsigned int bytes)
1229 {
1230 u32 data;
1231 int ret;
1232
1233 write_vreg(vgpu, offset, p_data, bytes);
1234 data = vgpu_vreg(vgpu, offset);
1235
1236 switch (offset) {
1237 case _vgtif_reg(display_ready):
1238 send_display_ready_uevent(vgpu, data ? 1 : 0);
1239 break;
1240 case _vgtif_reg(g2v_notify):
1241 ret = handle_g2v_notification(vgpu, data);
1242 break;
1243 /* add xhot and yhot to handled list to avoid error log */
1244 case _vgtif_reg(cursor_x_hot):
1245 case _vgtif_reg(cursor_y_hot):
1246 case _vgtif_reg(pdp[0].lo):
1247 case _vgtif_reg(pdp[0].hi):
1248 case _vgtif_reg(pdp[1].lo):
1249 case _vgtif_reg(pdp[1].hi):
1250 case _vgtif_reg(pdp[2].lo):
1251 case _vgtif_reg(pdp[2].hi):
1252 case _vgtif_reg(pdp[3].lo):
1253 case _vgtif_reg(pdp[3].hi):
1254 case _vgtif_reg(execlist_context_descriptor_lo):
1255 case _vgtif_reg(execlist_context_descriptor_hi):
1256 break;
1257 case _vgtif_reg(rsv5[0])..._vgtif_reg(rsv5[3]):
1258 enter_failsafe_mode(vgpu, GVT_FAILSAFE_INSUFFICIENT_RESOURCE);
1259 break;
1260 default:
1261 gvt_vgpu_err("invalid pvinfo write offset %x bytes %x data %x\n",
1262 offset, bytes, data);
1263 break;
1264 }
1265 return 0;
1266 }
1267
1268 static int pf_write(struct intel_vgpu *vgpu,
1269 unsigned int offset, void *p_data, unsigned int bytes)
1270 {
1271 u32 val = *(u32 *)p_data;
1272
1273 if ((offset == _PS_1A_CTRL || offset == _PS_2A_CTRL ||
1274 offset == _PS_1B_CTRL || offset == _PS_2B_CTRL ||
1275 offset == _PS_1C_CTRL) && (val & PS_PLANE_SEL_MASK) != 0) {
1276 WARN_ONCE(true, "VM(%d): guest is trying to scaling a plane\n",
1277 vgpu->id);
1278 return 0;
1279 }
1280
1281 return intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes);
1282 }
1283
1284 static int power_well_ctl_mmio_write(struct intel_vgpu *vgpu,
1285 unsigned int offset, void *p_data, unsigned int bytes)
1286 {
1287 write_vreg(vgpu, offset, p_data, bytes);
1288
1289 if (vgpu_vreg(vgpu, offset) &
1290 HSW_PWR_WELL_CTL_REQ(HSW_PW_CTL_IDX_GLOBAL))
1291 vgpu_vreg(vgpu, offset) |=
1292 HSW_PWR_WELL_CTL_STATE(HSW_PW_CTL_IDX_GLOBAL);
1293 else
1294 vgpu_vreg(vgpu, offset) &=
1295 ~HSW_PWR_WELL_CTL_STATE(HSW_PW_CTL_IDX_GLOBAL);
1296 return 0;
1297 }
1298
1299 static int gen9_dbuf_ctl_mmio_write(struct intel_vgpu *vgpu,
1300 unsigned int offset, void *p_data, unsigned int bytes)
1301 {
1302 write_vreg(vgpu, offset, p_data, bytes);
1303
1304 if (vgpu_vreg(vgpu, offset) & DBUF_POWER_REQUEST)
1305 vgpu_vreg(vgpu, offset) |= DBUF_POWER_STATE;
1306 else
1307 vgpu_vreg(vgpu, offset) &= ~DBUF_POWER_STATE;
1308
1309 return 0;
1310 }
1311
1312 static int fpga_dbg_mmio_write(struct intel_vgpu *vgpu,
1313 unsigned int offset, void *p_data, unsigned int bytes)
1314 {
1315 write_vreg(vgpu, offset, p_data, bytes);
1316
1317 if (vgpu_vreg(vgpu, offset) & FPGA_DBG_RM_NOCLAIM)
1318 vgpu_vreg(vgpu, offset) &= ~FPGA_DBG_RM_NOCLAIM;
1319 return 0;
1320 }
1321
1322 static int dma_ctrl_write(struct intel_vgpu *vgpu, unsigned int offset,
1323 void *p_data, unsigned int bytes)
1324 {
1325 u32 mode;
1326
1327 write_vreg(vgpu, offset, p_data, bytes);
1328 mode = vgpu_vreg(vgpu, offset);
1329
1330 if (GFX_MODE_BIT_SET_IN_MASK(mode, START_DMA)) {
1331 WARN_ONCE(1, "VM(%d): iGVT-g doesn't support GuC\n",
1332 vgpu->id);
1333 return 0;
1334 }
1335
1336 return 0;
1337 }
1338
1339 static int gen9_trtte_write(struct intel_vgpu *vgpu, unsigned int offset,
1340 void *p_data, unsigned int bytes)
1341 {
1342 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
1343 u32 trtte = *(u32 *)p_data;
1344
1345 if ((trtte & 1) && (trtte & (1 << 1)) == 0) {
1346 WARN(1, "VM(%d): Use physical address for TRTT!\n",
1347 vgpu->id);
1348 return -EINVAL;
1349 }
1350 write_vreg(vgpu, offset, p_data, bytes);
1351 /* TRTTE is not per-context */
1352
1353 mmio_hw_access_pre(dev_priv);
1354 I915_WRITE(_MMIO(offset), vgpu_vreg(vgpu, offset));
1355 mmio_hw_access_post(dev_priv);
1356
1357 return 0;
1358 }
1359
1360 static int gen9_trtt_chicken_write(struct intel_vgpu *vgpu, unsigned int offset,
1361 void *p_data, unsigned int bytes)
1362 {
1363 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
1364 u32 val = *(u32 *)p_data;
1365
1366 if (val & 1) {
1367 /* unblock hw logic */
1368 mmio_hw_access_pre(dev_priv);
1369 I915_WRITE(_MMIO(offset), val);
1370 mmio_hw_access_post(dev_priv);
1371 }
1372 write_vreg(vgpu, offset, p_data, bytes);
1373 return 0;
1374 }
1375
1376 static int dpll_status_read(struct intel_vgpu *vgpu, unsigned int offset,
1377 void *p_data, unsigned int bytes)
1378 {
1379 u32 v = 0;
1380
1381 if (vgpu_vreg(vgpu, 0x46010) & (1 << 31))
1382 v |= (1 << 0);
1383
1384 if (vgpu_vreg(vgpu, 0x46014) & (1 << 31))
1385 v |= (1 << 8);
1386
1387 if (vgpu_vreg(vgpu, 0x46040) & (1 << 31))
1388 v |= (1 << 16);
1389
1390 if (vgpu_vreg(vgpu, 0x46060) & (1 << 31))
1391 v |= (1 << 24);
1392
1393 vgpu_vreg(vgpu, offset) = v;
1394
1395 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);
1396 }
1397
1398 static int mailbox_write(struct intel_vgpu *vgpu, unsigned int offset,
1399 void *p_data, unsigned int bytes)
1400 {
1401 u32 value = *(u32 *)p_data;
1402 u32 cmd = value & 0xff;
1403 u32 *data0 = &vgpu_vreg_t(vgpu, GEN6_PCODE_DATA);
1404
1405 switch (cmd) {
1406 case GEN9_PCODE_READ_MEM_LATENCY:
1407 if (IS_SKYLAKE(vgpu->gvt->dev_priv)
1408 || IS_KABYLAKE(vgpu->gvt->dev_priv)
1409 || IS_COFFEELAKE(vgpu->gvt->dev_priv)) {
1410 /**
1411 * "Read memory latency" command on gen9.
1412 * Below memory latency values are read
1413 * from skylake platform.
1414 */
1415 if (!*data0)
1416 *data0 = 0x1e1a1100;
1417 else
1418 *data0 = 0x61514b3d;
1419 } else if (IS_BROXTON(vgpu->gvt->dev_priv)) {
1420 /**
1421 * "Read memory latency" command on gen9.
1422 * Below memory latency values are read
1423 * from Broxton MRB.
1424 */
1425 if (!*data0)
1426 *data0 = 0x16080707;
1427 else
1428 *data0 = 0x16161616;
1429 }
1430 break;
1431 case SKL_PCODE_CDCLK_CONTROL:
1432 if (IS_SKYLAKE(vgpu->gvt->dev_priv)
1433 || IS_KABYLAKE(vgpu->gvt->dev_priv)
1434 || IS_COFFEELAKE(vgpu->gvt->dev_priv))
1435 *data0 = SKL_CDCLK_READY_FOR_CHANGE;
1436 break;
1437 case GEN6_PCODE_READ_RC6VIDS:
1438 *data0 |= 0x1;
1439 break;
1440 }
1441
1442 gvt_dbg_core("VM(%d) write %x to mailbox, return data0 %x\n",
1443 vgpu->id, value, *data0);
1444 /**
1445 * PCODE_READY clear means ready for pcode read/write,
1446 * PCODE_ERROR_MASK clear means no error happened. In GVT-g we
1447 * always emulate as pcode read/write success and ready for access
1448 * anytime, since we don't touch real physical registers here.
1449 */
1450 value &= ~(GEN6_PCODE_READY | GEN6_PCODE_ERROR_MASK);
1451 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes);
1452 }
1453
1454 static int hws_pga_write(struct intel_vgpu *vgpu, unsigned int offset,
1455 void *p_data, unsigned int bytes)
1456 {
1457 u32 value = *(u32 *)p_data;
1458 int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset);
1459
1460 if (!intel_gvt_ggtt_validate_range(vgpu, value, I915_GTT_PAGE_SIZE)) {
1461 gvt_vgpu_err("write invalid HWSP address, reg:0x%x, value:0x%x\n",
1462 offset, value);
1463 return -EINVAL;
1464 }
1465 /*
1466 * Need to emulate all the HWSP register write to ensure host can
1467 * update the VM CSB status correctly. Here listed registers can
1468 * support BDW, SKL or other platforms with same HWSP registers.
1469 */
1470 if (unlikely(ring_id < 0 || ring_id >= I915_NUM_ENGINES)) {
1471 gvt_vgpu_err("access unknown hardware status page register:0x%x\n",
1472 offset);
1473 return -EINVAL;
1474 }
1475 vgpu->hws_pga[ring_id] = value;
1476 gvt_dbg_mmio("VM(%d) write: 0x%x to HWSP: 0x%x\n",
1477 vgpu->id, value, offset);
1478
1479 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes);
1480 }
1481
1482 static int skl_power_well_ctl_write(struct intel_vgpu *vgpu,
1483 unsigned int offset, void *p_data, unsigned int bytes)
1484 {
1485 u32 v = *(u32 *)p_data;
1486
1487 if (IS_BROXTON(vgpu->gvt->dev_priv))
1488 v &= (1 << 31) | (1 << 29);
1489 else
1490 v &= (1 << 31) | (1 << 29) | (1 << 9) |
1491 (1 << 7) | (1 << 5) | (1 << 3) | (1 << 1);
1492 v |= (v >> 1);
1493
1494 return intel_vgpu_default_mmio_write(vgpu, offset, &v, bytes);
1495 }
1496
1497 static int skl_lcpll_write(struct intel_vgpu *vgpu, unsigned int offset,
1498 void *p_data, unsigned int bytes)
1499 {
1500 u32 v = *(u32 *)p_data;
1501
1502 /* other bits are MBZ. */
1503 v &= (1 << 31) | (1 << 30);
1504 v & (1 << 31) ? (v |= (1 << 30)) : (v &= ~(1 << 30));
1505
1506 vgpu_vreg(vgpu, offset) = v;
1507
1508 return 0;
1509 }
1510
1511 static int bxt_de_pll_enable_write(struct intel_vgpu *vgpu,
1512 unsigned int offset, void *p_data, unsigned int bytes)
1513 {
1514 u32 v = *(u32 *)p_data;
1515
1516 if (v & BXT_DE_PLL_PLL_ENABLE)
1517 v |= BXT_DE_PLL_LOCK;
1518
1519 vgpu_vreg(vgpu, offset) = v;
1520
1521 return 0;
1522 }
1523
1524 static int bxt_port_pll_enable_write(struct intel_vgpu *vgpu,
1525 unsigned int offset, void *p_data, unsigned int bytes)
1526 {
1527 u32 v = *(u32 *)p_data;
1528
1529 if (v & PORT_PLL_ENABLE)
1530 v |= PORT_PLL_LOCK;
1531
1532 vgpu_vreg(vgpu, offset) = v;
1533
1534 return 0;
1535 }
1536
1537 static int bxt_phy_ctl_family_write(struct intel_vgpu *vgpu,
1538 unsigned int offset, void *p_data, unsigned int bytes)
1539 {
1540 u32 v = *(u32 *)p_data;
1541 u32 data = v & COMMON_RESET_DIS ? BXT_PHY_LANE_ENABLED : 0;
1542
1543 switch (offset) {
1544 case _PHY_CTL_FAMILY_EDP:
1545 vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_A) = data;
1546 break;
1547 case _PHY_CTL_FAMILY_DDI:
1548 vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_B) = data;
1549 vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_C) = data;
1550 break;
1551 }
1552
1553 vgpu_vreg(vgpu, offset) = v;
1554
1555 return 0;
1556 }
1557
1558 static int bxt_port_tx_dw3_read(struct intel_vgpu *vgpu,
1559 unsigned int offset, void *p_data, unsigned int bytes)
1560 {
1561 u32 v = vgpu_vreg(vgpu, offset);
1562
1563 v &= ~UNIQUE_TRANGE_EN_METHOD;
1564
1565 vgpu_vreg(vgpu, offset) = v;
1566
1567 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);
1568 }
1569
1570 static int bxt_pcs_dw12_grp_write(struct intel_vgpu *vgpu,
1571 unsigned int offset, void *p_data, unsigned int bytes)
1572 {
1573 u32 v = *(u32 *)p_data;
1574
1575 if (offset == _PORT_PCS_DW12_GRP_A || offset == _PORT_PCS_DW12_GRP_B) {
1576 vgpu_vreg(vgpu, offset - 0x600) = v;
1577 vgpu_vreg(vgpu, offset - 0x800) = v;
1578 } else {
1579 vgpu_vreg(vgpu, offset - 0x400) = v;
1580 vgpu_vreg(vgpu, offset - 0x600) = v;
1581 }
1582
1583 vgpu_vreg(vgpu, offset) = v;
1584
1585 return 0;
1586 }
1587
1588 static int bxt_gt_disp_pwron_write(struct intel_vgpu *vgpu,
1589 unsigned int offset, void *p_data, unsigned int bytes)
1590 {
1591 u32 v = *(u32 *)p_data;
1592
1593 if (v & BIT(0)) {
1594 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &=
1595 ~PHY_RESERVED;
1596 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |=
1597 PHY_POWER_GOOD;
1598 }
1599
1600 if (v & BIT(1)) {
1601 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &=
1602 ~PHY_RESERVED;
1603 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) |=
1604 PHY_POWER_GOOD;
1605 }
1606
1607
1608 vgpu_vreg(vgpu, offset) = v;
1609
1610 return 0;
1611 }
1612
1613 static int edp_psr_imr_iir_write(struct intel_vgpu *vgpu,
1614 unsigned int offset, void *p_data, unsigned int bytes)
1615 {
1616 vgpu_vreg(vgpu, offset) = 0;
1617 return 0;
1618 }
1619
1620 static int mmio_read_from_hw(struct intel_vgpu *vgpu,
1621 unsigned int offset, void *p_data, unsigned int bytes)
1622 {
1623 struct intel_gvt *gvt = vgpu->gvt;
1624 struct drm_i915_private *dev_priv = gvt->dev_priv;
1625 int ring_id;
1626 u32 ring_base;
1627
1628 ring_id = intel_gvt_render_mmio_to_ring_id(gvt, offset);
1629 /**
1630 * Read HW reg in following case
1631 * a. the offset isn't a ring mmio
1632 * b. the offset's ring is running on hw.
1633 * c. the offset is ring time stamp mmio
1634 */
1635 if (ring_id >= 0)
1636 ring_base = dev_priv->engine[ring_id]->mmio_base;
1637
1638 if (ring_id < 0 || vgpu == gvt->scheduler.engine_owner[ring_id] ||
1639 offset == i915_mmio_reg_offset(RING_TIMESTAMP(ring_base)) ||
1640 offset == i915_mmio_reg_offset(RING_TIMESTAMP_UDW(ring_base))) {
1641 mmio_hw_access_pre(dev_priv);
1642 vgpu_vreg(vgpu, offset) = I915_READ(_MMIO(offset));
1643 mmio_hw_access_post(dev_priv);
1644 }
1645
1646 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);
1647 }
1648
1649 static int elsp_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1650 void *p_data, unsigned int bytes)
1651 {
1652 int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset);
1653 struct intel_vgpu_execlist *execlist;
1654 u32 data = *(u32 *)p_data;
1655 int ret = 0;
1656
1657 if (WARN_ON(ring_id < 0 || ring_id >= I915_NUM_ENGINES))
1658 return -EINVAL;
1659
1660 execlist = &vgpu->submission.execlist[ring_id];
1661
1662 execlist->elsp_dwords.data[3 - execlist->elsp_dwords.index] = data;
1663 if (execlist->elsp_dwords.index == 3) {
1664 ret = intel_vgpu_submit_execlist(vgpu, ring_id);
1665 if(ret)
1666 gvt_vgpu_err("fail submit workload on ring %d\n",
1667 ring_id);
1668 }
1669
1670 ++execlist->elsp_dwords.index;
1671 execlist->elsp_dwords.index &= 0x3;
1672 return ret;
1673 }
1674
1675 static int ring_mode_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1676 void *p_data, unsigned int bytes)
1677 {
1678 u32 data = *(u32 *)p_data;
1679 int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset);
1680 bool enable_execlist;
1681 int ret;
1682
1683 write_vreg(vgpu, offset, p_data, bytes);
1684
1685 /* when PPGTT mode enabled, we will check if guest has called
1686 * pvinfo, if not, we will treat this guest as non-gvtg-aware
1687 * guest, and stop emulating its cfg space, mmio, gtt, etc.
1688 */
1689 if (((data & _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)) ||
1690 (data & _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)))
1691 && !vgpu->pv_notified) {
1692 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST);
1693 return 0;
1694 }
1695 if ((data & _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE))
1696 || (data & _MASKED_BIT_DISABLE(GFX_RUN_LIST_ENABLE))) {
1697 enable_execlist = !!(data & GFX_RUN_LIST_ENABLE);
1698
1699 gvt_dbg_core("EXECLIST %s on ring %d\n",
1700 (enable_execlist ? "enabling" : "disabling"),
1701 ring_id);
1702
1703 if (!enable_execlist)
1704 return 0;
1705
1706 ret = intel_vgpu_select_submission_ops(vgpu,
1707 ENGINE_MASK(ring_id),
1708 INTEL_VGPU_EXECLIST_SUBMISSION);
1709 if (ret)
1710 return ret;
1711
1712 intel_vgpu_start_schedule(vgpu);
1713 }
1714 return 0;
1715 }
1716
1717 static int gvt_reg_tlb_control_handler(struct intel_vgpu *vgpu,
1718 unsigned int offset, void *p_data, unsigned int bytes)
1719 {
1720 unsigned int id = 0;
1721
1722 write_vreg(vgpu, offset, p_data, bytes);
1723 vgpu_vreg(vgpu, offset) = 0;
1724
1725 switch (offset) {
1726 case 0x4260:
1727 id = RCS;
1728 break;
1729 case 0x4264:
1730 id = VCS;
1731 break;
1732 case 0x4268:
1733 id = VCS2;
1734 break;
1735 case 0x426c:
1736 id = BCS;
1737 break;
1738 case 0x4270:
1739 id = VECS;
1740 break;
1741 default:
1742 return -EINVAL;
1743 }
1744 set_bit(id, (void *)vgpu->submission.tlb_handle_pending);
1745
1746 return 0;
1747 }
1748
1749 static int ring_reset_ctl_write(struct intel_vgpu *vgpu,
1750 unsigned int offset, void *p_data, unsigned int bytes)
1751 {
1752 u32 data;
1753
1754 write_vreg(vgpu, offset, p_data, bytes);
1755 data = vgpu_vreg(vgpu, offset);
1756
1757 if (data & _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET))
1758 data |= RESET_CTL_READY_TO_RESET;
1759 else if (data & _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET))
1760 data &= ~RESET_CTL_READY_TO_RESET;
1761
1762 vgpu_vreg(vgpu, offset) = data;
1763 return 0;
1764 }
1765
1766 #define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
1767 ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
1768 f, s, am, rm, d, r, w); \
1769 if (ret) \
1770 return ret; \
1771 } while (0)
1772
1773 #define MMIO_D(reg, d) \
1774 MMIO_F(reg, 4, 0, 0, 0, d, NULL, NULL)
1775
1776 #define MMIO_DH(reg, d, r, w) \
1777 MMIO_F(reg, 4, 0, 0, 0, d, r, w)
1778
1779 #define MMIO_DFH(reg, d, f, r, w) \
1780 MMIO_F(reg, 4, f, 0, 0, d, r, w)
1781
1782 #define MMIO_GM(reg, d, r, w) \
1783 MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w)
1784
1785 #define MMIO_GM_RDR(reg, d, r, w) \
1786 MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w)
1787
1788 #define MMIO_RO(reg, d, f, rm, r, w) \
1789 MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w)
1790
1791 #define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \
1792 MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
1793 MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \
1794 MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \
1795 MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \
1796 if (HAS_BSD2(dev_priv)) \
1797 MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \
1798 } while (0)
1799
1800 #define MMIO_RING_D(prefix, d) \
1801 MMIO_RING_F(prefix, 4, 0, 0, 0, d, NULL, NULL)
1802
1803 #define MMIO_RING_DFH(prefix, d, f, r, w) \
1804 MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
1805
1806 #define MMIO_RING_GM(prefix, d, r, w) \
1807 MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w)
1808
1809 #define MMIO_RING_GM_RDR(prefix, d, r, w) \
1810 MMIO_RING_F(prefix, 4, F_GMADR | F_CMD_ACCESS, 0xFFFF0000, 0, d, r, w)
1811
1812 #define MMIO_RING_RO(prefix, d, f, rm, r, w) \
1813 MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w)
1814
1815 static int init_generic_mmio_info(struct intel_gvt *gvt)
1816 {
1817 struct drm_i915_private *dev_priv = gvt->dev_priv;
1818 int ret;
1819
1820 MMIO_RING_DFH(RING_IMR, D_ALL, F_CMD_ACCESS, NULL,
1821 intel_vgpu_reg_imr_handler);
1822
1823 MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler);
1824 MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler);
1825 MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler);
1826 MMIO_D(SDEISR, D_ALL);
1827
1828 MMIO_RING_DFH(RING_HWSTAM, D_ALL, F_CMD_ACCESS, NULL, NULL);
1829
1830 MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL,
1831 gamw_echo_dev_rw_ia_write);
1832
1833 MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL);
1834 MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL);
1835 MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL);
1836
1837 #define RING_REG(base) _MMIO((base) + 0x28)
1838 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
1839 #undef RING_REG
1840
1841 #define RING_REG(base) _MMIO((base) + 0x134)
1842 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
1843 #undef RING_REG
1844
1845 #define RING_REG(base) _MMIO((base) + 0x6c)
1846 MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL);
1847 #undef RING_REG
1848 MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL);
1849
1850 MMIO_GM_RDR(_MMIO(0x2148), D_ALL, NULL, NULL);
1851 MMIO_GM_RDR(CCID, D_ALL, NULL, NULL);
1852 MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL);
1853 MMIO_D(GEN7_CXT_SIZE, D_ALL);
1854
1855 MMIO_RING_DFH(RING_TAIL, D_ALL, F_CMD_ACCESS, NULL, NULL);
1856 MMIO_RING_DFH(RING_HEAD, D_ALL, F_CMD_ACCESS, NULL, NULL);
1857 MMIO_RING_DFH(RING_CTL, D_ALL, F_CMD_ACCESS, NULL, NULL);
1858 MMIO_RING_DFH(RING_ACTHD, D_ALL, F_CMD_ACCESS, mmio_read_from_hw, NULL);
1859 MMIO_RING_GM_RDR(RING_START, D_ALL, NULL, NULL);
1860
1861 /* RING MODE */
1862 #define RING_REG(base) _MMIO((base) + 0x29c)
1863 MMIO_RING_DFH(RING_REG, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL,
1864 ring_mode_mmio_write);
1865 #undef RING_REG
1866
1867 MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
1868 NULL, NULL);
1869 MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
1870 NULL, NULL);
1871 MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS,
1872 mmio_read_from_hw, NULL);
1873 MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS,
1874 mmio_read_from_hw, NULL);
1875
1876 MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1877 MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
1878 NULL, NULL);
1879 MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1880 MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1881 MMIO_DFH(_MMIO(0x2124), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1882
1883 MMIO_DFH(_MMIO(0x20dc), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1884 MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1885 MMIO_DFH(_MMIO(0x2088), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1886 MMIO_DFH(_MMIO(0x20e4), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1887 MMIO_DFH(_MMIO(0x2470), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1888 MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL);
1889 MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
1890 NULL, NULL);
1891 MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
1892 NULL, NULL);
1893 MMIO_DFH(_MMIO(0x9030), D_ALL, F_CMD_ACCESS, NULL, NULL);
1894 MMIO_DFH(_MMIO(0x20a0), D_ALL, F_CMD_ACCESS, NULL, NULL);
1895 MMIO_DFH(_MMIO(0x2420), D_ALL, F_CMD_ACCESS, NULL, NULL);
1896 MMIO_DFH(_MMIO(0x2430), D_ALL, F_CMD_ACCESS, NULL, NULL);
1897 MMIO_DFH(_MMIO(0x2434), D_ALL, F_CMD_ACCESS, NULL, NULL);
1898 MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL);
1899 MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL);
1900 MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1901 MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1902 MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1903
1904 /* display */
1905 MMIO_F(_MMIO(0x60220), 0x20, 0, 0, 0, D_ALL, NULL, NULL);
1906 MMIO_D(_MMIO(0x602a0), D_ALL);
1907
1908 MMIO_D(_MMIO(0x65050), D_ALL);
1909 MMIO_D(_MMIO(0x650b4), D_ALL);
1910
1911 MMIO_D(_MMIO(0xc4040), D_ALL);
1912 MMIO_D(DERRMR, D_ALL);
1913
1914 MMIO_D(PIPEDSL(PIPE_A), D_ALL);
1915 MMIO_D(PIPEDSL(PIPE_B), D_ALL);
1916 MMIO_D(PIPEDSL(PIPE_C), D_ALL);
1917 MMIO_D(PIPEDSL(_PIPE_EDP), D_ALL);
1918
1919 MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write);
1920 MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write);
1921 MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write);
1922 MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write);
1923
1924 MMIO_D(PIPESTAT(PIPE_A), D_ALL);
1925 MMIO_D(PIPESTAT(PIPE_B), D_ALL);
1926 MMIO_D(PIPESTAT(PIPE_C), D_ALL);
1927 MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL);
1928
1929 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL);
1930 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL);
1931 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C), D_ALL);
1932 MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP), D_ALL);
1933
1934 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL);
1935 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL);
1936 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C), D_ALL);
1937 MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP), D_ALL);
1938
1939 MMIO_D(CURCNTR(PIPE_A), D_ALL);
1940 MMIO_D(CURCNTR(PIPE_B), D_ALL);
1941 MMIO_D(CURCNTR(PIPE_C), D_ALL);
1942
1943 MMIO_D(CURPOS(PIPE_A), D_ALL);
1944 MMIO_D(CURPOS(PIPE_B), D_ALL);
1945 MMIO_D(CURPOS(PIPE_C), D_ALL);
1946
1947 MMIO_D(CURBASE(PIPE_A), D_ALL);
1948 MMIO_D(CURBASE(PIPE_B), D_ALL);
1949 MMIO_D(CURBASE(PIPE_C), D_ALL);
1950
1951 MMIO_D(CUR_FBC_CTL(PIPE_A), D_ALL);
1952 MMIO_D(CUR_FBC_CTL(PIPE_B), D_ALL);
1953 MMIO_D(CUR_FBC_CTL(PIPE_C), D_ALL);
1954
1955 MMIO_D(_MMIO(0x700ac), D_ALL);
1956 MMIO_D(_MMIO(0x710ac), D_ALL);
1957 MMIO_D(_MMIO(0x720ac), D_ALL);
1958
1959 MMIO_D(_MMIO(0x70090), D_ALL);
1960 MMIO_D(_MMIO(0x70094), D_ALL);
1961 MMIO_D(_MMIO(0x70098), D_ALL);
1962 MMIO_D(_MMIO(0x7009c), D_ALL);
1963
1964 MMIO_D(DSPCNTR(PIPE_A), D_ALL);
1965 MMIO_D(DSPADDR(PIPE_A), D_ALL);
1966 MMIO_D(DSPSTRIDE(PIPE_A), D_ALL);
1967 MMIO_D(DSPPOS(PIPE_A), D_ALL);
1968 MMIO_D(DSPSIZE(PIPE_A), D_ALL);
1969 MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write);
1970 MMIO_D(DSPOFFSET(PIPE_A), D_ALL);
1971 MMIO_D(DSPSURFLIVE(PIPE_A), D_ALL);
1972
1973 MMIO_D(DSPCNTR(PIPE_B), D_ALL);
1974 MMIO_D(DSPADDR(PIPE_B), D_ALL);
1975 MMIO_D(DSPSTRIDE(PIPE_B), D_ALL);
1976 MMIO_D(DSPPOS(PIPE_B), D_ALL);
1977 MMIO_D(DSPSIZE(PIPE_B), D_ALL);
1978 MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write);
1979 MMIO_D(DSPOFFSET(PIPE_B), D_ALL);
1980 MMIO_D(DSPSURFLIVE(PIPE_B), D_ALL);
1981
1982 MMIO_D(DSPCNTR(PIPE_C), D_ALL);
1983 MMIO_D(DSPADDR(PIPE_C), D_ALL);
1984 MMIO_D(DSPSTRIDE(PIPE_C), D_ALL);
1985 MMIO_D(DSPPOS(PIPE_C), D_ALL);
1986 MMIO_D(DSPSIZE(PIPE_C), D_ALL);
1987 MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write);
1988 MMIO_D(DSPOFFSET(PIPE_C), D_ALL);
1989 MMIO_D(DSPSURFLIVE(PIPE_C), D_ALL);
1990
1991 MMIO_D(SPRCTL(PIPE_A), D_ALL);
1992 MMIO_D(SPRLINOFF(PIPE_A), D_ALL);
1993 MMIO_D(SPRSTRIDE(PIPE_A), D_ALL);
1994 MMIO_D(SPRPOS(PIPE_A), D_ALL);
1995 MMIO_D(SPRSIZE(PIPE_A), D_ALL);
1996 MMIO_D(SPRKEYVAL(PIPE_A), D_ALL);
1997 MMIO_D(SPRKEYMSK(PIPE_A), D_ALL);
1998 MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write);
1999 MMIO_D(SPRKEYMAX(PIPE_A), D_ALL);
2000 MMIO_D(SPROFFSET(PIPE_A), D_ALL);
2001 MMIO_D(SPRSCALE(PIPE_A), D_ALL);
2002 MMIO_D(SPRSURFLIVE(PIPE_A), D_ALL);
2003
2004 MMIO_D(SPRCTL(PIPE_B), D_ALL);
2005 MMIO_D(SPRLINOFF(PIPE_B), D_ALL);
2006 MMIO_D(SPRSTRIDE(PIPE_B), D_ALL);
2007 MMIO_D(SPRPOS(PIPE_B), D_ALL);
2008 MMIO_D(SPRSIZE(PIPE_B), D_ALL);
2009 MMIO_D(SPRKEYVAL(PIPE_B), D_ALL);
2010 MMIO_D(SPRKEYMSK(PIPE_B), D_ALL);
2011 MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write);
2012 MMIO_D(SPRKEYMAX(PIPE_B), D_ALL);
2013 MMIO_D(SPROFFSET(PIPE_B), D_ALL);
2014 MMIO_D(SPRSCALE(PIPE_B), D_ALL);
2015 MMIO_D(SPRSURFLIVE(PIPE_B), D_ALL);
2016
2017 MMIO_D(SPRCTL(PIPE_C), D_ALL);
2018 MMIO_D(SPRLINOFF(PIPE_C), D_ALL);
2019 MMIO_D(SPRSTRIDE(PIPE_C), D_ALL);
2020 MMIO_D(SPRPOS(PIPE_C), D_ALL);
2021 MMIO_D(SPRSIZE(PIPE_C), D_ALL);
2022 MMIO_D(SPRKEYVAL(PIPE_C), D_ALL);
2023 MMIO_D(SPRKEYMSK(PIPE_C), D_ALL);
2024 MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write);
2025 MMIO_D(SPRKEYMAX(PIPE_C), D_ALL);
2026 MMIO_D(SPROFFSET(PIPE_C), D_ALL);
2027 MMIO_D(SPRSCALE(PIPE_C), D_ALL);
2028 MMIO_D(SPRSURFLIVE(PIPE_C), D_ALL);
2029
2030 MMIO_D(HTOTAL(TRANSCODER_A), D_ALL);
2031 MMIO_D(HBLANK(TRANSCODER_A), D_ALL);
2032 MMIO_D(HSYNC(TRANSCODER_A), D_ALL);
2033 MMIO_D(VTOTAL(TRANSCODER_A), D_ALL);
2034 MMIO_D(VBLANK(TRANSCODER_A), D_ALL);
2035 MMIO_D(VSYNC(TRANSCODER_A), D_ALL);
2036 MMIO_D(BCLRPAT(TRANSCODER_A), D_ALL);
2037 MMIO_D(VSYNCSHIFT(TRANSCODER_A), D_ALL);
2038 MMIO_D(PIPESRC(TRANSCODER_A), D_ALL);
2039
2040 MMIO_D(HTOTAL(TRANSCODER_B), D_ALL);
2041 MMIO_D(HBLANK(TRANSCODER_B), D_ALL);
2042 MMIO_D(HSYNC(TRANSCODER_B), D_ALL);
2043 MMIO_D(VTOTAL(TRANSCODER_B), D_ALL);
2044 MMIO_D(VBLANK(TRANSCODER_B), D_ALL);
2045 MMIO_D(VSYNC(TRANSCODER_B), D_ALL);
2046 MMIO_D(BCLRPAT(TRANSCODER_B), D_ALL);
2047 MMIO_D(VSYNCSHIFT(TRANSCODER_B), D_ALL);
2048 MMIO_D(PIPESRC(TRANSCODER_B), D_ALL);
2049
2050 MMIO_D(HTOTAL(TRANSCODER_C), D_ALL);
2051 MMIO_D(HBLANK(TRANSCODER_C), D_ALL);
2052 MMIO_D(HSYNC(TRANSCODER_C), D_ALL);
2053 MMIO_D(VTOTAL(TRANSCODER_C), D_ALL);
2054 MMIO_D(VBLANK(TRANSCODER_C), D_ALL);
2055 MMIO_D(VSYNC(TRANSCODER_C), D_ALL);
2056 MMIO_D(BCLRPAT(TRANSCODER_C), D_ALL);
2057 MMIO_D(VSYNCSHIFT(TRANSCODER_C), D_ALL);
2058 MMIO_D(PIPESRC(TRANSCODER_C), D_ALL);
2059
2060 MMIO_D(HTOTAL(TRANSCODER_EDP), D_ALL);
2061 MMIO_D(HBLANK(TRANSCODER_EDP), D_ALL);
2062 MMIO_D(HSYNC(TRANSCODER_EDP), D_ALL);
2063 MMIO_D(VTOTAL(TRANSCODER_EDP), D_ALL);
2064 MMIO_D(VBLANK(TRANSCODER_EDP), D_ALL);
2065 MMIO_D(VSYNC(TRANSCODER_EDP), D_ALL);
2066 MMIO_D(BCLRPAT(TRANSCODER_EDP), D_ALL);
2067 MMIO_D(VSYNCSHIFT(TRANSCODER_EDP), D_ALL);
2068
2069 MMIO_D(PIPE_DATA_M1(TRANSCODER_A), D_ALL);
2070 MMIO_D(PIPE_DATA_N1(TRANSCODER_A), D_ALL);
2071 MMIO_D(PIPE_DATA_M2(TRANSCODER_A), D_ALL);
2072 MMIO_D(PIPE_DATA_N2(TRANSCODER_A), D_ALL);
2073 MMIO_D(PIPE_LINK_M1(TRANSCODER_A), D_ALL);
2074 MMIO_D(PIPE_LINK_N1(TRANSCODER_A), D_ALL);
2075 MMIO_D(PIPE_LINK_M2(TRANSCODER_A), D_ALL);
2076 MMIO_D(PIPE_LINK_N2(TRANSCODER_A), D_ALL);
2077
2078 MMIO_D(PIPE_DATA_M1(TRANSCODER_B), D_ALL);
2079 MMIO_D(PIPE_DATA_N1(TRANSCODER_B), D_ALL);
2080 MMIO_D(PIPE_DATA_M2(TRANSCODER_B), D_ALL);
2081 MMIO_D(PIPE_DATA_N2(TRANSCODER_B), D_ALL);
2082 MMIO_D(PIPE_LINK_M1(TRANSCODER_B), D_ALL);
2083 MMIO_D(PIPE_LINK_N1(TRANSCODER_B), D_ALL);
2084 MMIO_D(PIPE_LINK_M2(TRANSCODER_B), D_ALL);
2085 MMIO_D(PIPE_LINK_N2(TRANSCODER_B), D_ALL);
2086
2087 MMIO_D(PIPE_DATA_M1(TRANSCODER_C), D_ALL);
2088 MMIO_D(PIPE_DATA_N1(TRANSCODER_C), D_ALL);
2089 MMIO_D(PIPE_DATA_M2(TRANSCODER_C), D_ALL);
2090 MMIO_D(PIPE_DATA_N2(TRANSCODER_C), D_ALL);
2091 MMIO_D(PIPE_LINK_M1(TRANSCODER_C), D_ALL);
2092 MMIO_D(PIPE_LINK_N1(TRANSCODER_C), D_ALL);
2093 MMIO_D(PIPE_LINK_M2(TRANSCODER_C), D_ALL);
2094 MMIO_D(PIPE_LINK_N2(TRANSCODER_C), D_ALL);
2095
2096 MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP), D_ALL);
2097 MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP), D_ALL);
2098 MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP), D_ALL);
2099 MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP), D_ALL);
2100 MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP), D_ALL);
2101 MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP), D_ALL);
2102 MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP), D_ALL);
2103 MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP), D_ALL);
2104
2105 MMIO_D(PF_CTL(PIPE_A), D_ALL);
2106 MMIO_D(PF_WIN_SZ(PIPE_A), D_ALL);
2107 MMIO_D(PF_WIN_POS(PIPE_A), D_ALL);
2108 MMIO_D(PF_VSCALE(PIPE_A), D_ALL);
2109 MMIO_D(PF_HSCALE(PIPE_A), D_ALL);
2110
2111 MMIO_D(PF_CTL(PIPE_B), D_ALL);
2112 MMIO_D(PF_WIN_SZ(PIPE_B), D_ALL);
2113 MMIO_D(PF_WIN_POS(PIPE_B), D_ALL);
2114 MMIO_D(PF_VSCALE(PIPE_B), D_ALL);
2115 MMIO_D(PF_HSCALE(PIPE_B), D_ALL);
2116
2117 MMIO_D(PF_CTL(PIPE_C), D_ALL);
2118 MMIO_D(PF_WIN_SZ(PIPE_C), D_ALL);
2119 MMIO_D(PF_WIN_POS(PIPE_C), D_ALL);
2120 MMIO_D(PF_VSCALE(PIPE_C), D_ALL);
2121 MMIO_D(PF_HSCALE(PIPE_C), D_ALL);
2122
2123 MMIO_D(WM0_PIPEA_ILK, D_ALL);
2124 MMIO_D(WM0_PIPEB_ILK, D_ALL);
2125 MMIO_D(WM0_PIPEC_IVB, D_ALL);
2126 MMIO_D(WM1_LP_ILK, D_ALL);
2127 MMIO_D(WM2_LP_ILK, D_ALL);
2128 MMIO_D(WM3_LP_ILK, D_ALL);
2129 MMIO_D(WM1S_LP_ILK, D_ALL);
2130 MMIO_D(WM2S_LP_IVB, D_ALL);
2131 MMIO_D(WM3S_LP_IVB, D_ALL);
2132
2133 MMIO_D(BLC_PWM_CPU_CTL2, D_ALL);
2134 MMIO_D(BLC_PWM_CPU_CTL, D_ALL);
2135 MMIO_D(BLC_PWM_PCH_CTL1, D_ALL);
2136 MMIO_D(BLC_PWM_PCH_CTL2, D_ALL);
2137
2138 MMIO_D(_MMIO(0x48268), D_ALL);
2139
2140 MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
2141 gmbus_mmio_write);
2142 MMIO_F(PCH_GPIO_BASE, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
2143 MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL);
2144
2145 MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
2146 dp_aux_ch_ctl_mmio_write);
2147 MMIO_F(_MMIO(_PCH_DPC_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
2148 dp_aux_ch_ctl_mmio_write);
2149 MMIO_F(_MMIO(_PCH_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
2150 dp_aux_ch_ctl_mmio_write);
2151
2152 MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write);
2153
2154 MMIO_DH(_MMIO(_PCH_TRANSACONF), D_ALL, NULL, transconf_mmio_write);
2155 MMIO_DH(_MMIO(_PCH_TRANSBCONF), D_ALL, NULL, transconf_mmio_write);
2156
2157 MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write);
2158 MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write);
2159 MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write);
2160 MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
2161 MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
2162 MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
2163 MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
2164 MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
2165 MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
2166
2167 MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_A), D_ALL);
2168 MMIO_D(_MMIO(_PCH_TRANS_HBLANK_A), D_ALL);
2169 MMIO_D(_MMIO(_PCH_TRANS_HSYNC_A), D_ALL);
2170 MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_A), D_ALL);
2171 MMIO_D(_MMIO(_PCH_TRANS_VBLANK_A), D_ALL);
2172 MMIO_D(_MMIO(_PCH_TRANS_VSYNC_A), D_ALL);
2173 MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_A), D_ALL);
2174
2175 MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_B), D_ALL);
2176 MMIO_D(_MMIO(_PCH_TRANS_HBLANK_B), D_ALL);
2177 MMIO_D(_MMIO(_PCH_TRANS_HSYNC_B), D_ALL);
2178 MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_B), D_ALL);
2179 MMIO_D(_MMIO(_PCH_TRANS_VBLANK_B), D_ALL);
2180 MMIO_D(_MMIO(_PCH_TRANS_VSYNC_B), D_ALL);
2181 MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_B), D_ALL);
2182
2183 MMIO_D(_MMIO(_PCH_TRANSA_DATA_M1), D_ALL);
2184 MMIO_D(_MMIO(_PCH_TRANSA_DATA_N1), D_ALL);
2185 MMIO_D(_MMIO(_PCH_TRANSA_DATA_M2), D_ALL);
2186 MMIO_D(_MMIO(_PCH_TRANSA_DATA_N2), D_ALL);
2187 MMIO_D(_MMIO(_PCH_TRANSA_LINK_M1), D_ALL);
2188 MMIO_D(_MMIO(_PCH_TRANSA_LINK_N1), D_ALL);
2189 MMIO_D(_MMIO(_PCH_TRANSA_LINK_M2), D_ALL);
2190 MMIO_D(_MMIO(_PCH_TRANSA_LINK_N2), D_ALL);
2191
2192 MMIO_D(TRANS_DP_CTL(PIPE_A), D_ALL);
2193 MMIO_D(TRANS_DP_CTL(PIPE_B), D_ALL);
2194 MMIO_D(TRANS_DP_CTL(PIPE_C), D_ALL);
2195
2196 MMIO_D(TVIDEO_DIP_CTL(PIPE_A), D_ALL);
2197 MMIO_D(TVIDEO_DIP_DATA(PIPE_A), D_ALL);
2198 MMIO_D(TVIDEO_DIP_GCP(PIPE_A), D_ALL);
2199
2200 MMIO_D(TVIDEO_DIP_CTL(PIPE_B), D_ALL);
2201 MMIO_D(TVIDEO_DIP_DATA(PIPE_B), D_ALL);
2202 MMIO_D(TVIDEO_DIP_GCP(PIPE_B), D_ALL);
2203
2204 MMIO_D(TVIDEO_DIP_CTL(PIPE_C), D_ALL);
2205 MMIO_D(TVIDEO_DIP_DATA(PIPE_C), D_ALL);
2206 MMIO_D(TVIDEO_DIP_GCP(PIPE_C), D_ALL);
2207
2208 MMIO_D(_MMIO(_FDI_RXA_MISC), D_ALL);
2209 MMIO_D(_MMIO(_FDI_RXB_MISC), D_ALL);
2210 MMIO_D(_MMIO(_FDI_RXA_TUSIZE1), D_ALL);
2211 MMIO_D(_MMIO(_FDI_RXA_TUSIZE2), D_ALL);
2212 MMIO_D(_MMIO(_FDI_RXB_TUSIZE1), D_ALL);
2213 MMIO_D(_MMIO(_FDI_RXB_TUSIZE2), D_ALL);
2214
2215 MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write);
2216 MMIO_D(PCH_PP_DIVISOR, D_ALL);
2217 MMIO_D(PCH_PP_STATUS, D_ALL);
2218 MMIO_D(PCH_LVDS, D_ALL);
2219 MMIO_D(_MMIO(_PCH_DPLL_A), D_ALL);
2220 MMIO_D(_MMIO(_PCH_DPLL_B), D_ALL);
2221 MMIO_D(_MMIO(_PCH_FPA0), D_ALL);
2222 MMIO_D(_MMIO(_PCH_FPA1), D_ALL);
2223 MMIO_D(_MMIO(_PCH_FPB0), D_ALL);
2224 MMIO_D(_MMIO(_PCH_FPB1), D_ALL);
2225 MMIO_D(PCH_DREF_CONTROL, D_ALL);
2226 MMIO_D(PCH_RAWCLK_FREQ, D_ALL);
2227 MMIO_D(PCH_DPLL_SEL, D_ALL);
2228
2229 MMIO_D(_MMIO(0x61208), D_ALL);
2230 MMIO_D(_MMIO(0x6120c), D_ALL);
2231 MMIO_D(PCH_PP_ON_DELAYS, D_ALL);
2232 MMIO_D(PCH_PP_OFF_DELAYS, D_ALL);
2233
2234 MMIO_DH(_MMIO(0xe651c), D_ALL, dpy_reg_mmio_read, NULL);
2235 MMIO_DH(_MMIO(0xe661c), D_ALL, dpy_reg_mmio_read, NULL);
2236 MMIO_DH(_MMIO(0xe671c), D_ALL, dpy_reg_mmio_read, NULL);
2237 MMIO_DH(_MMIO(0xe681c), D_ALL, dpy_reg_mmio_read, NULL);
2238 MMIO_DH(_MMIO(0xe6c04), D_ALL, dpy_reg_mmio_read, NULL);
2239 MMIO_DH(_MMIO(0xe6e1c), D_ALL, dpy_reg_mmio_read, NULL);
2240
2241 MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0,
2242 PORTA_HOTPLUG_STATUS_MASK
2243 | PORTB_HOTPLUG_STATUS_MASK
2244 | PORTC_HOTPLUG_STATUS_MASK
2245 | PORTD_HOTPLUG_STATUS_MASK,
2246 NULL, NULL);
2247
2248 MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write);
2249 MMIO_D(FUSE_STRAP, D_ALL);
2250 MMIO_D(DIGITAL_PORT_HOTPLUG_CNTRL, D_ALL);
2251
2252 MMIO_D(DISP_ARB_CTL, D_ALL);
2253 MMIO_D(DISP_ARB_CTL2, D_ALL);
2254
2255 MMIO_D(ILK_DISPLAY_CHICKEN1, D_ALL);
2256 MMIO_D(ILK_DISPLAY_CHICKEN2, D_ALL);
2257 MMIO_D(ILK_DSPCLK_GATE_D, D_ALL);
2258
2259 MMIO_D(SOUTH_CHICKEN1, D_ALL);
2260 MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write);
2261 MMIO_D(_MMIO(_TRANSA_CHICKEN1), D_ALL);
2262 MMIO_D(_MMIO(_TRANSB_CHICKEN1), D_ALL);
2263 MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL);
2264 MMIO_D(_MMIO(_TRANSA_CHICKEN2), D_ALL);
2265 MMIO_D(_MMIO(_TRANSB_CHICKEN2), D_ALL);
2266
2267 MMIO_D(ILK_DPFC_CB_BASE, D_ALL);
2268 MMIO_D(ILK_DPFC_CONTROL, D_ALL);
2269 MMIO_D(ILK_DPFC_RECOMP_CTL, D_ALL);
2270 MMIO_D(ILK_DPFC_STATUS, D_ALL);
2271 MMIO_D(ILK_DPFC_FENCE_YOFF, D_ALL);
2272 MMIO_D(ILK_DPFC_CHICKEN, D_ALL);
2273 MMIO_D(ILK_FBC_RT_BASE, D_ALL);
2274
2275 MMIO_D(IPS_CTL, D_ALL);
2276
2277 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A), D_ALL);
2278 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A), D_ALL);
2279 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A), D_ALL);
2280 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A), D_ALL);
2281 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A), D_ALL);
2282 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A), D_ALL);
2283 MMIO_D(PIPE_CSC_MODE(PIPE_A), D_ALL);
2284 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A), D_ALL);
2285 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A), D_ALL);
2286 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A), D_ALL);
2287 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A), D_ALL);
2288 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A), D_ALL);
2289 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A), D_ALL);
2290
2291 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_B), D_ALL);
2292 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_B), D_ALL);
2293 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_B), D_ALL);
2294 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_B), D_ALL);
2295 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_B), D_ALL);
2296 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_B), D_ALL);
2297 MMIO_D(PIPE_CSC_MODE(PIPE_B), D_ALL);
2298 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_B), D_ALL);
2299 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_B), D_ALL);
2300 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_B), D_ALL);
2301 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_B), D_ALL);
2302 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_B), D_ALL);
2303 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_B), D_ALL);
2304
2305 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_C), D_ALL);
2306 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_C), D_ALL);
2307 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_C), D_ALL);
2308 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_C), D_ALL);
2309 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_C), D_ALL);
2310 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_C), D_ALL);
2311 MMIO_D(PIPE_CSC_MODE(PIPE_C), D_ALL);
2312 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_C), D_ALL);
2313 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_C), D_ALL);
2314 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_C), D_ALL);
2315 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_C), D_ALL);
2316 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_C), D_ALL);
2317 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_C), D_ALL);
2318
2319 MMIO_D(PREC_PAL_INDEX(PIPE_A), D_ALL);
2320 MMIO_D(PREC_PAL_DATA(PIPE_A), D_ALL);
2321 MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
2322
2323 MMIO_D(PREC_PAL_INDEX(PIPE_B), D_ALL);
2324 MMIO_D(PREC_PAL_DATA(PIPE_B), D_ALL);
2325 MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
2326
2327 MMIO_D(PREC_PAL_INDEX(PIPE_C), D_ALL);
2328 MMIO_D(PREC_PAL_DATA(PIPE_C), D_ALL);
2329 MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
2330
2331 MMIO_D(_MMIO(0x60110), D_ALL);
2332 MMIO_D(_MMIO(0x61110), D_ALL);
2333 MMIO_F(_MMIO(0x70400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
2334 MMIO_F(_MMIO(0x71400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
2335 MMIO_F(_MMIO(0x72400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
2336 MMIO_F(_MMIO(0x70440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2337 MMIO_F(_MMIO(0x71440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2338 MMIO_F(_MMIO(0x72440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2339 MMIO_F(_MMIO(0x7044c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2340 MMIO_F(_MMIO(0x7144c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2341 MMIO_F(_MMIO(0x7244c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2342
2343 MMIO_D(PIPE_WM_LINETIME(PIPE_A), D_ALL);
2344 MMIO_D(PIPE_WM_LINETIME(PIPE_B), D_ALL);
2345 MMIO_D(PIPE_WM_LINETIME(PIPE_C), D_ALL);
2346 MMIO_D(SPLL_CTL, D_ALL);
2347 MMIO_D(_MMIO(_WRPLL_CTL1), D_ALL);
2348 MMIO_D(_MMIO(_WRPLL_CTL2), D_ALL);
2349 MMIO_D(PORT_CLK_SEL(PORT_A), D_ALL);
2350 MMIO_D(PORT_CLK_SEL(PORT_B), D_ALL);
2351 MMIO_D(PORT_CLK_SEL(PORT_C), D_ALL);
2352 MMIO_D(PORT_CLK_SEL(PORT_D), D_ALL);
2353 MMIO_D(PORT_CLK_SEL(PORT_E), D_ALL);
2354 MMIO_D(TRANS_CLK_SEL(TRANSCODER_A), D_ALL);
2355 MMIO_D(TRANS_CLK_SEL(TRANSCODER_B), D_ALL);
2356 MMIO_D(TRANS_CLK_SEL(TRANSCODER_C), D_ALL);
2357
2358 MMIO_D(HSW_NDE_RSTWRN_OPT, D_ALL);
2359 MMIO_D(_MMIO(0x46508), D_ALL);
2360
2361 MMIO_D(_MMIO(0x49080), D_ALL);
2362 MMIO_D(_MMIO(0x49180), D_ALL);
2363 MMIO_D(_MMIO(0x49280), D_ALL);
2364
2365 MMIO_F(_MMIO(0x49090), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
2366 MMIO_F(_MMIO(0x49190), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
2367 MMIO_F(_MMIO(0x49290), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
2368
2369 MMIO_D(GAMMA_MODE(PIPE_A), D_ALL);
2370 MMIO_D(GAMMA_MODE(PIPE_B), D_ALL);
2371 MMIO_D(GAMMA_MODE(PIPE_C), D_ALL);
2372
2373 MMIO_D(PIPE_MULT(PIPE_A), D_ALL);
2374 MMIO_D(PIPE_MULT(PIPE_B), D_ALL);
2375 MMIO_D(PIPE_MULT(PIPE_C), D_ALL);
2376
2377 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A), D_ALL);
2378 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B), D_ALL);
2379 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C), D_ALL);
2380
2381 MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL);
2382 MMIO_D(SBI_ADDR, D_ALL);
2383 MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL);
2384 MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write);
2385 MMIO_D(PIXCLK_GATE, D_ALL);
2386
2387 MMIO_F(_MMIO(_DPA_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_ALL, NULL,
2388 dp_aux_ch_ctl_mmio_write);
2389
2390 MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2391 MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2392 MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2393 MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2394 MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2395
2396 MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write);
2397 MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write);
2398 MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write);
2399 MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write);
2400 MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write);
2401
2402 MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write);
2403 MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write);
2404 MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write);
2405 MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write);
2406 MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL);
2407
2408 MMIO_F(_MMIO(_DDI_BUF_TRANS_A), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
2409 MMIO_F(_MMIO(0x64e60), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
2410 MMIO_F(_MMIO(0x64eC0), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
2411 MMIO_F(_MMIO(0x64f20), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
2412 MMIO_F(_MMIO(0x64f80), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
2413
2414 MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL);
2415 MMIO_D(HSW_AUD_PIN_ELD_CP_VLD, D_ALL);
2416 MMIO_D(HSW_AUD_MISC_CTRL(PIPE_A), D_ALL);
2417
2418 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_A), D_ALL, NULL, NULL);
2419 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_B), D_ALL, NULL, NULL);
2420 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_C), D_ALL, NULL, NULL);
2421 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_EDP), D_ALL, NULL, NULL);
2422
2423 MMIO_D(_MMIO(_TRANSA_MSA_MISC), D_ALL);
2424 MMIO_D(_MMIO(_TRANSB_MSA_MISC), D_ALL);
2425 MMIO_D(_MMIO(_TRANSC_MSA_MISC), D_ALL);
2426 MMIO_D(_MMIO(_TRANS_EDP_MSA_MISC), D_ALL);
2427
2428 MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL);
2429 MMIO_D(FORCEWAKE_ACK, D_ALL);
2430 MMIO_D(GEN6_GT_CORE_STATUS, D_ALL);
2431 MMIO_D(GEN6_GT_THREAD_STATUS_REG, D_ALL);
2432 MMIO_DFH(GTFIFODBG, D_ALL, F_CMD_ACCESS, NULL, NULL);
2433 MMIO_DFH(GTFIFOCTL, D_ALL, F_CMD_ACCESS, NULL, NULL);
2434 MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write);
2435 MMIO_DH(FORCEWAKE_ACK_HSW, D_BDW, NULL, NULL);
2436 MMIO_D(ECOBUS, D_ALL);
2437 MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL);
2438 MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL);
2439 MMIO_D(GEN6_RPNSWREQ, D_ALL);
2440 MMIO_D(GEN6_RC_VIDEO_FREQ, D_ALL);
2441 MMIO_D(GEN6_RP_DOWN_TIMEOUT, D_ALL);
2442 MMIO_D(GEN6_RP_INTERRUPT_LIMITS, D_ALL);
2443 MMIO_D(GEN6_RPSTAT1, D_ALL);
2444 MMIO_D(GEN6_RP_CONTROL, D_ALL);
2445 MMIO_D(GEN6_RP_UP_THRESHOLD, D_ALL);
2446 MMIO_D(GEN6_RP_DOWN_THRESHOLD, D_ALL);
2447 MMIO_D(GEN6_RP_CUR_UP_EI, D_ALL);
2448 MMIO_D(GEN6_RP_CUR_UP, D_ALL);
2449 MMIO_D(GEN6_RP_PREV_UP, D_ALL);
2450 MMIO_D(GEN6_RP_CUR_DOWN_EI, D_ALL);
2451 MMIO_D(GEN6_RP_CUR_DOWN, D_ALL);
2452 MMIO_D(GEN6_RP_PREV_DOWN, D_ALL);
2453 MMIO_D(GEN6_RP_UP_EI, D_ALL);
2454 MMIO_D(GEN6_RP_DOWN_EI, D_ALL);
2455 MMIO_D(GEN6_RP_IDLE_HYSTERSIS, D_ALL);
2456 MMIO_D(GEN6_RC1_WAKE_RATE_LIMIT, D_ALL);
2457 MMIO_D(GEN6_RC6_WAKE_RATE_LIMIT, D_ALL);
2458 MMIO_D(GEN6_RC6pp_WAKE_RATE_LIMIT, D_ALL);
2459 MMIO_D(GEN6_RC_EVALUATION_INTERVAL, D_ALL);
2460 MMIO_D(GEN6_RC_IDLE_HYSTERSIS, D_ALL);
2461 MMIO_D(GEN6_RC_SLEEP, D_ALL);
2462 MMIO_D(GEN6_RC1e_THRESHOLD, D_ALL);
2463 MMIO_D(GEN6_RC6_THRESHOLD, D_ALL);
2464 MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL);
2465 MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL);
2466 MMIO_D(GEN6_PMINTRMSK, D_ALL);
2467 MMIO_DH(HSW_PWR_WELL_CTL1, D_BDW, NULL, power_well_ctl_mmio_write);
2468 MMIO_DH(HSW_PWR_WELL_CTL2, D_BDW, NULL, power_well_ctl_mmio_write);
2469 MMIO_DH(HSW_PWR_WELL_CTL3, D_BDW, NULL, power_well_ctl_mmio_write);
2470 MMIO_DH(HSW_PWR_WELL_CTL4, D_BDW, NULL, power_well_ctl_mmio_write);
2471 MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write);
2472 MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write);
2473
2474 MMIO_D(RSTDBYCTL, D_ALL);
2475
2476 MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write);
2477 MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write);
2478 MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write);
2479
2480 MMIO_D(TILECTL, D_ALL);
2481
2482 MMIO_D(GEN6_UCGCTL1, D_ALL);
2483 MMIO_D(GEN6_UCGCTL2, D_ALL);
2484
2485 MMIO_F(_MMIO(0x4f000), 0x90, 0, 0, 0, D_ALL, NULL, NULL);
2486
2487 MMIO_D(GEN6_PCODE_DATA, D_ALL);
2488 MMIO_D(_MMIO(0x13812c), D_ALL);
2489 MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL);
2490 MMIO_D(HSW_EDRAM_CAP, D_ALL);
2491 MMIO_D(HSW_IDICR, D_ALL);
2492 MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL);
2493
2494 MMIO_D(_MMIO(0x3c), D_ALL);
2495 MMIO_D(_MMIO(0x860), D_ALL);
2496 MMIO_D(ECOSKPD, D_ALL);
2497 MMIO_D(_MMIO(0x121d0), D_ALL);
2498 MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL);
2499 MMIO_D(_MMIO(0x41d0), D_ALL);
2500 MMIO_D(GAC_ECO_BITS, D_ALL);
2501 MMIO_D(_MMIO(0x6200), D_ALL);
2502 MMIO_D(_MMIO(0x6204), D_ALL);
2503 MMIO_D(_MMIO(0x6208), D_ALL);
2504 MMIO_D(_MMIO(0x7118), D_ALL);
2505 MMIO_D(_MMIO(0x7180), D_ALL);
2506 MMIO_D(_MMIO(0x7408), D_ALL);
2507 MMIO_D(_MMIO(0x7c00), D_ALL);
2508 MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write);
2509 MMIO_D(_MMIO(0x911c), D_ALL);
2510 MMIO_D(_MMIO(0x9120), D_ALL);
2511 MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL);
2512
2513 MMIO_D(GAB_CTL, D_ALL);
2514 MMIO_D(_MMIO(0x48800), D_ALL);
2515 MMIO_D(_MMIO(0xce044), D_ALL);
2516 MMIO_D(_MMIO(0xe6500), D_ALL);
2517 MMIO_D(_MMIO(0xe6504), D_ALL);
2518 MMIO_D(_MMIO(0xe6600), D_ALL);
2519 MMIO_D(_MMIO(0xe6604), D_ALL);
2520 MMIO_D(_MMIO(0xe6700), D_ALL);
2521 MMIO_D(_MMIO(0xe6704), D_ALL);
2522 MMIO_D(_MMIO(0xe6800), D_ALL);
2523 MMIO_D(_MMIO(0xe6804), D_ALL);
2524 MMIO_D(PCH_GMBUS4, D_ALL);
2525 MMIO_D(PCH_GMBUS5, D_ALL);
2526
2527 MMIO_D(_MMIO(0x902c), D_ALL);
2528 MMIO_D(_MMIO(0xec008), D_ALL);
2529 MMIO_D(_MMIO(0xec00c), D_ALL);
2530 MMIO_D(_MMIO(0xec008 + 0x18), D_ALL);
2531 MMIO_D(_MMIO(0xec00c + 0x18), D_ALL);
2532 MMIO_D(_MMIO(0xec008 + 0x18 * 2), D_ALL);
2533 MMIO_D(_MMIO(0xec00c + 0x18 * 2), D_ALL);
2534 MMIO_D(_MMIO(0xec008 + 0x18 * 3), D_ALL);
2535 MMIO_D(_MMIO(0xec00c + 0x18 * 3), D_ALL);
2536 MMIO_D(_MMIO(0xec408), D_ALL);
2537 MMIO_D(_MMIO(0xec40c), D_ALL);
2538 MMIO_D(_MMIO(0xec408 + 0x18), D_ALL);
2539 MMIO_D(_MMIO(0xec40c + 0x18), D_ALL);
2540 MMIO_D(_MMIO(0xec408 + 0x18 * 2), D_ALL);
2541 MMIO_D(_MMIO(0xec40c + 0x18 * 2), D_ALL);
2542 MMIO_D(_MMIO(0xec408 + 0x18 * 3), D_ALL);
2543 MMIO_D(_MMIO(0xec40c + 0x18 * 3), D_ALL);
2544 MMIO_D(_MMIO(0xfc810), D_ALL);
2545 MMIO_D(_MMIO(0xfc81c), D_ALL);
2546 MMIO_D(_MMIO(0xfc828), D_ALL);
2547 MMIO_D(_MMIO(0xfc834), D_ALL);
2548 MMIO_D(_MMIO(0xfcc00), D_ALL);
2549 MMIO_D(_MMIO(0xfcc0c), D_ALL);
2550 MMIO_D(_MMIO(0xfcc18), D_ALL);
2551 MMIO_D(_MMIO(0xfcc24), D_ALL);
2552 MMIO_D(_MMIO(0xfd000), D_ALL);
2553 MMIO_D(_MMIO(0xfd00c), D_ALL);
2554 MMIO_D(_MMIO(0xfd018), D_ALL);
2555 MMIO_D(_MMIO(0xfd024), D_ALL);
2556 MMIO_D(_MMIO(0xfd034), D_ALL);
2557
2558 MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write);
2559 MMIO_D(_MMIO(0x2054), D_ALL);
2560 MMIO_D(_MMIO(0x12054), D_ALL);
2561 MMIO_D(_MMIO(0x22054), D_ALL);
2562 MMIO_D(_MMIO(0x1a054), D_ALL);
2563
2564 MMIO_D(_MMIO(0x44070), D_ALL);
2565 MMIO_DFH(_MMIO(0x215c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2566 MMIO_DFH(_MMIO(0x2178), D_ALL, F_CMD_ACCESS, NULL, NULL);
2567 MMIO_DFH(_MMIO(0x217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
2568 MMIO_DFH(_MMIO(0x12178), D_ALL, F_CMD_ACCESS, NULL, NULL);
2569 MMIO_DFH(_MMIO(0x1217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
2570
2571 MMIO_F(_MMIO(0x2290), 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
2572 MMIO_D(_MMIO(0x2b00), D_BDW_PLUS);
2573 MMIO_D(_MMIO(0x2360), D_BDW_PLUS);
2574 MMIO_F(_MMIO(0x5200), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2575 MMIO_F(_MMIO(0x5240), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2576 MMIO_F(_MMIO(0x5280), 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2577
2578 MMIO_DFH(_MMIO(0x1c17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2579 MMIO_DFH(_MMIO(0x1c178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2580 MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL);
2581
2582 MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2583 MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2584 MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2585 MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2586 MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2587 MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2588 MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2589 MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2590 MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2591 MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2592 MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2593 MMIO_DH(_MMIO(0x4260), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2594 MMIO_DH(_MMIO(0x4264), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2595 MMIO_DH(_MMIO(0x4268), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2596 MMIO_DH(_MMIO(0x426c), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2597 MMIO_DH(_MMIO(0x4270), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2598 MMIO_DFH(_MMIO(0x4094), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2599
2600 MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2601 MMIO_RING_GM_RDR(RING_BBADDR, D_ALL, NULL, NULL);
2602 MMIO_DFH(_MMIO(0x2220), D_ALL, F_CMD_ACCESS, NULL, NULL);
2603 MMIO_DFH(_MMIO(0x12220), D_ALL, F_CMD_ACCESS, NULL, NULL);
2604 MMIO_DFH(_MMIO(0x22220), D_ALL, F_CMD_ACCESS, NULL, NULL);
2605 MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL);
2606 MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL);
2607 MMIO_DFH(_MMIO(0x22178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2608 MMIO_DFH(_MMIO(0x1a178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2609 MMIO_DFH(_MMIO(0x1a17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2610 MMIO_DFH(_MMIO(0x2217c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2611
2612 MMIO_DH(EDP_PSR_IMR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
2613 MMIO_DH(EDP_PSR_IIR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
2614 return 0;
2615 }
2616
2617 static int init_broadwell_mmio_info(struct intel_gvt *gvt)
2618 {
2619 struct drm_i915_private *dev_priv = gvt->dev_priv;
2620 int ret;
2621
2622 MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2623 MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2624 MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2625 MMIO_D(GEN8_GT_ISR(0), D_BDW_PLUS);
2626
2627 MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2628 MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2629 MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2630 MMIO_D(GEN8_GT_ISR(1), D_BDW_PLUS);
2631
2632 MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2633 MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2634 MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2635 MMIO_D(GEN8_GT_ISR(2), D_BDW_PLUS);
2636
2637 MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2638 MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2639 MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2640 MMIO_D(GEN8_GT_ISR(3), D_BDW_PLUS);
2641
2642 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL,
2643 intel_vgpu_reg_imr_handler);
2644 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL,
2645 intel_vgpu_reg_ier_handler);
2646 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL,
2647 intel_vgpu_reg_iir_handler);
2648 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_A), D_BDW_PLUS);
2649
2650 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL,
2651 intel_vgpu_reg_imr_handler);
2652 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL,
2653 intel_vgpu_reg_ier_handler);
2654 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL,
2655 intel_vgpu_reg_iir_handler);
2656 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_B), D_BDW_PLUS);
2657
2658 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL,
2659 intel_vgpu_reg_imr_handler);
2660 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL,
2661 intel_vgpu_reg_ier_handler);
2662 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL,
2663 intel_vgpu_reg_iir_handler);
2664 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_C), D_BDW_PLUS);
2665
2666 MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2667 MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2668 MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2669 MMIO_D(GEN8_DE_PORT_ISR, D_BDW_PLUS);
2670
2671 MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2672 MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2673 MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2674 MMIO_D(GEN8_DE_MISC_ISR, D_BDW_PLUS);
2675
2676 MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2677 MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2678 MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2679 MMIO_D(GEN8_PCU_ISR, D_BDW_PLUS);
2680
2681 MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL,
2682 intel_vgpu_reg_master_irq_handler);
2683
2684 MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, F_CMD_ACCESS,
2685 mmio_read_from_hw, NULL);
2686
2687 #define RING_REG(base) _MMIO((base) + 0xd0)
2688 MMIO_RING_F(RING_REG, 4, F_RO, 0,
2689 ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL,
2690 ring_reset_ctl_write);
2691 #undef RING_REG
2692
2693 #define RING_REG(base) _MMIO((base) + 0x230)
2694 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write);
2695 #undef RING_REG
2696
2697 #define RING_REG(base) _MMIO((base) + 0x234)
2698 MMIO_RING_F(RING_REG, 8, F_RO | F_CMD_ACCESS, 0, ~0, D_BDW_PLUS,
2699 NULL, NULL);
2700 #undef RING_REG
2701
2702 #define RING_REG(base) _MMIO((base) + 0x244)
2703 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2704 #undef RING_REG
2705
2706 #define RING_REG(base) _MMIO((base) + 0x370)
2707 MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL);
2708 #undef RING_REG
2709
2710 #define RING_REG(base) _MMIO((base) + 0x3a0)
2711 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL);
2712 #undef RING_REG
2713
2714 MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS);
2715 MMIO_D(PIPEMISC(PIPE_B), D_BDW_PLUS);
2716 MMIO_D(PIPEMISC(PIPE_C), D_BDW_PLUS);
2717 MMIO_D(_MMIO(0x1c1d0), D_BDW_PLUS);
2718 MMIO_D(GEN6_MBCUNIT_SNPCR, D_BDW_PLUS);
2719 MMIO_D(GEN7_MISCCPCTL, D_BDW_PLUS);
2720 MMIO_D(_MMIO(0x1c054), D_BDW_PLUS);
2721
2722 MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write);
2723
2724 MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS);
2725 MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS);
2726
2727 MMIO_D(GAMTARBMODE, D_BDW_PLUS);
2728
2729 #define RING_REG(base) _MMIO((base) + 0x270)
2730 MMIO_RING_F(RING_REG, 32, 0, 0, 0, D_BDW_PLUS, NULL, NULL);
2731 #undef RING_REG
2732
2733 MMIO_RING_GM_RDR(RING_HWS_PGA, D_BDW_PLUS, NULL, hws_pga_write);
2734
2735 MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2736
2737 MMIO_D(CHICKEN_PIPESL_1(PIPE_A), D_BDW_PLUS);
2738 MMIO_D(CHICKEN_PIPESL_1(PIPE_B), D_BDW_PLUS);
2739 MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW_PLUS);
2740
2741 MMIO_D(WM_MISC, D_BDW);
2742 MMIO_D(_MMIO(BDW_EDP_PSR_BASE), D_BDW);
2743
2744 MMIO_D(_MMIO(0x6671c), D_BDW_PLUS);
2745 MMIO_D(_MMIO(0x66c00), D_BDW_PLUS);
2746 MMIO_D(_MMIO(0x66c04), D_BDW_PLUS);
2747
2748 MMIO_D(HSW_GTT_CACHE_EN, D_BDW_PLUS);
2749
2750 MMIO_D(GEN8_EU_DISABLE0, D_BDW_PLUS);
2751 MMIO_D(GEN8_EU_DISABLE1, D_BDW_PLUS);
2752 MMIO_D(GEN8_EU_DISABLE2, D_BDW_PLUS);
2753
2754 MMIO_D(_MMIO(0xfdc), D_BDW_PLUS);
2755 MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
2756 NULL, NULL);
2757 MMIO_DFH(GEN7_ROW_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
2758 NULL, NULL);
2759 MMIO_DFH(GEN8_UCGCTL6, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2760
2761 MMIO_DFH(_MMIO(0xb1f0), D_BDW, F_CMD_ACCESS, NULL, NULL);
2762 MMIO_DFH(_MMIO(0xb1c0), D_BDW, F_CMD_ACCESS, NULL, NULL);
2763 MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2764 MMIO_DFH(_MMIO(0xb100), D_BDW, F_CMD_ACCESS, NULL, NULL);
2765 MMIO_DFH(_MMIO(0xb10c), D_BDW, F_CMD_ACCESS, NULL, NULL);
2766 MMIO_D(_MMIO(0xb110), D_BDW);
2767
2768 MMIO_F(_MMIO(0x24d0), 48, F_CMD_ACCESS, 0, 0, D_BDW_PLUS,
2769 NULL, force_nonpriv_write);
2770
2771 MMIO_D(_MMIO(0x44484), D_BDW_PLUS);
2772 MMIO_D(_MMIO(0x4448c), D_BDW_PLUS);
2773
2774 MMIO_DFH(_MMIO(0x83a4), D_BDW, F_CMD_ACCESS, NULL, NULL);
2775 MMIO_D(GEN8_L3_LRA_1_GPGPU, D_BDW_PLUS);
2776
2777 MMIO_DFH(_MMIO(0x8430), D_BDW, F_CMD_ACCESS, NULL, NULL);
2778
2779 MMIO_D(_MMIO(0x110000), D_BDW_PLUS);
2780
2781 MMIO_D(_MMIO(0x48400), D_BDW_PLUS);
2782
2783 MMIO_D(_MMIO(0x6e570), D_BDW_PLUS);
2784 MMIO_D(_MMIO(0x65f10), D_BDW_PLUS);
2785
2786 MMIO_DFH(_MMIO(0xe194), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2787 MMIO_DFH(_MMIO(0xe188), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2788 MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2789 MMIO_DFH(_MMIO(0x2580), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2790
2791 MMIO_DFH(_MMIO(0x2248), D_BDW, F_CMD_ACCESS, NULL, NULL);
2792
2793 MMIO_DFH(_MMIO(0xe220), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2794 MMIO_DFH(_MMIO(0xe230), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2795 MMIO_DFH(_MMIO(0xe240), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2796 MMIO_DFH(_MMIO(0xe260), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2797 MMIO_DFH(_MMIO(0xe270), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2798 MMIO_DFH(_MMIO(0xe280), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2799 MMIO_DFH(_MMIO(0xe2a0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2800 MMIO_DFH(_MMIO(0xe2b0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2801 MMIO_DFH(_MMIO(0xe2c0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2802 MMIO_DFH(_MMIO(0x21f0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2803 return 0;
2804 }
2805
2806 static int init_skl_mmio_info(struct intel_gvt *gvt)
2807 {
2808 struct drm_i915_private *dev_priv = gvt->dev_priv;
2809 int ret;
2810
2811 MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
2812 MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL);
2813 MMIO_DH(FORCEWAKE_BLITTER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
2814 MMIO_DH(FORCEWAKE_ACK_BLITTER_GEN9, D_SKL_PLUS, NULL, NULL);
2815 MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
2816 MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL);
2817
2818 MMIO_F(_MMIO(_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
2819 dp_aux_ch_ctl_mmio_write);
2820 MMIO_F(_MMIO(_DPC_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
2821 dp_aux_ch_ctl_mmio_write);
2822 MMIO_F(_MMIO(_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
2823 dp_aux_ch_ctl_mmio_write);
2824
2825 MMIO_D(HSW_PWR_WELL_CTL1, D_SKL_PLUS);
2826 MMIO_DH(HSW_PWR_WELL_CTL2, D_SKL_PLUS, NULL, skl_power_well_ctl_write);
2827
2828 MMIO_DH(DBUF_CTL, D_SKL_PLUS, NULL, gen9_dbuf_ctl_mmio_write);
2829
2830 MMIO_D(_MMIO(0xa210), D_SKL_PLUS);
2831 MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
2832 MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
2833 MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
2834 MMIO_DH(_MMIO(0x4ddc), D_SKL_PLUS, NULL, NULL);
2835 MMIO_DH(_MMIO(0x42080), D_SKL_PLUS, NULL, NULL);
2836 MMIO_D(_MMIO(0x45504), D_SKL_PLUS);
2837 MMIO_D(_MMIO(0x45520), D_SKL_PLUS);
2838 MMIO_D(_MMIO(0x46000), D_SKL_PLUS);
2839 MMIO_DH(_MMIO(0x46010), D_SKL_PLUS, NULL, skl_lcpll_write);
2840 MMIO_DH(_MMIO(0x46014), D_SKL_PLUS, NULL, skl_lcpll_write);
2841 MMIO_D(_MMIO(0x6C040), D_SKL_PLUS);
2842 MMIO_D(_MMIO(0x6C048), D_SKL_PLUS);
2843 MMIO_D(_MMIO(0x6C050), D_SKL_PLUS);
2844 MMIO_D(_MMIO(0x6C044), D_SKL_PLUS);
2845 MMIO_D(_MMIO(0x6C04C), D_SKL_PLUS);
2846 MMIO_D(_MMIO(0x6C054), D_SKL_PLUS);
2847 MMIO_D(_MMIO(0x6c058), D_SKL_PLUS);
2848 MMIO_D(_MMIO(0x6c05c), D_SKL_PLUS);
2849 MMIO_DH(_MMIO(0x6c060), D_SKL_PLUS, dpll_status_read, NULL);
2850
2851 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
2852 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
2853 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
2854 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
2855 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
2856 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
2857
2858 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
2859 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
2860 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
2861 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
2862 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
2863 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
2864
2865 MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
2866 MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
2867 MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
2868 MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
2869 MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
2870 MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
2871
2872 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
2873 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
2874 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
2875 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
2876
2877 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
2878 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
2879 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
2880 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
2881
2882 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
2883 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
2884 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
2885 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
2886
2887 MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL_PLUS, NULL, NULL);
2888 MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL_PLUS, NULL, NULL);
2889 MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL_PLUS, NULL, NULL);
2890
2891 MMIO_F(PLANE_WM(PIPE_A, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2892 MMIO_F(PLANE_WM(PIPE_A, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2893 MMIO_F(PLANE_WM(PIPE_A, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2894
2895 MMIO_F(PLANE_WM(PIPE_B, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2896 MMIO_F(PLANE_WM(PIPE_B, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2897 MMIO_F(PLANE_WM(PIPE_B, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2898
2899 MMIO_F(PLANE_WM(PIPE_C, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2900 MMIO_F(PLANE_WM(PIPE_C, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2901 MMIO_F(PLANE_WM(PIPE_C, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2902
2903 MMIO_F(CUR_WM(PIPE_A, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2904 MMIO_F(CUR_WM(PIPE_B, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2905 MMIO_F(CUR_WM(PIPE_C, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2906
2907 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
2908 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
2909 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
2910
2911 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
2912 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
2913 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
2914
2915 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
2916 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
2917 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
2918
2919 MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL_PLUS, NULL, NULL);
2920 MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL_PLUS, NULL, NULL);
2921 MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL_PLUS, NULL, NULL);
2922
2923 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
2924 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
2925 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
2926 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
2927
2928 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
2929 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
2930 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
2931 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
2932
2933 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
2934 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
2935 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
2936 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
2937
2938 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
2939 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
2940 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
2941 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
2942
2943 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
2944 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
2945 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
2946 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
2947
2948 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
2949 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
2950 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
2951 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
2952
2953 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
2954 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
2955 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
2956 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
2957
2958 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
2959 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
2960 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
2961 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
2962
2963 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
2964 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
2965 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
2966 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
2967
2968 MMIO_D(_MMIO(0x70380), D_SKL_PLUS);
2969 MMIO_D(_MMIO(0x71380), D_SKL_PLUS);
2970 MMIO_D(_MMIO(0x72380), D_SKL_PLUS);
2971 MMIO_D(_MMIO(0x7239c), D_SKL_PLUS);
2972 MMIO_D(_MMIO(0x7039c), D_SKL_PLUS);
2973
2974 MMIO_D(_MMIO(0x8f074), D_SKL_PLUS);
2975 MMIO_D(_MMIO(0x8f004), D_SKL_PLUS);
2976 MMIO_D(_MMIO(0x8f034), D_SKL_PLUS);
2977
2978 MMIO_D(_MMIO(0xb11c), D_SKL_PLUS);
2979
2980 MMIO_D(_MMIO(0x51000), D_SKL_PLUS);
2981 MMIO_D(_MMIO(0x6c00c), D_SKL_PLUS);
2982
2983 MMIO_F(_MMIO(0xc800), 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
2984 NULL, NULL);
2985 MMIO_F(_MMIO(0xb020), 0x80, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
2986 NULL, NULL);
2987
2988 MMIO_D(RPM_CONFIG0, D_SKL_PLUS);
2989 MMIO_D(_MMIO(0xd08), D_SKL_PLUS);
2990 MMIO_D(RC6_LOCATION, D_SKL_PLUS);
2991 MMIO_DFH(_MMIO(0x20e0), D_SKL_PLUS, F_MODE_MASK, NULL, NULL);
2992 MMIO_DFH(_MMIO(0x20ec), D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
2993 NULL, NULL);
2994
2995 /* TRTT */
2996 MMIO_DFH(_MMIO(0x4de0), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
2997 MMIO_DFH(_MMIO(0x4de4), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
2998 MMIO_DFH(_MMIO(0x4de8), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
2999 MMIO_DFH(_MMIO(0x4dec), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
3000 MMIO_DFH(_MMIO(0x4df0), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
3001 MMIO_DFH(_MMIO(0x4df4), D_SKL_PLUS, F_CMD_ACCESS,
3002 NULL, gen9_trtte_write);
3003 MMIO_DH(_MMIO(0x4dfc), D_SKL_PLUS, NULL, gen9_trtt_chicken_write);
3004
3005 MMIO_D(_MMIO(0x46430), D_SKL_PLUS);
3006
3007 MMIO_D(_MMIO(0x46520), D_SKL_PLUS);
3008
3009 MMIO_D(_MMIO(0xc403c), D_SKL_PLUS);
3010 MMIO_D(_MMIO(0xb004), D_SKL_PLUS);
3011 MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write);
3012
3013 MMIO_D(_MMIO(0x65900), D_SKL_PLUS);
3014 MMIO_D(_MMIO(0x1082c0), D_SKL_PLUS);
3015 MMIO_D(_MMIO(0x4068), D_SKL_PLUS);
3016 MMIO_D(_MMIO(0x67054), D_SKL_PLUS);
3017 MMIO_D(_MMIO(0x6e560), D_SKL_PLUS);
3018 MMIO_D(_MMIO(0x6e554), D_SKL_PLUS);
3019 MMIO_D(_MMIO(0x2b20), D_SKL_PLUS);
3020 MMIO_D(_MMIO(0x65f00), D_SKL_PLUS);
3021 MMIO_D(_MMIO(0x65f08), D_SKL_PLUS);
3022 MMIO_D(_MMIO(0x320f0), D_SKL_PLUS);
3023
3024 MMIO_D(_MMIO(0x70034), D_SKL_PLUS);
3025 MMIO_D(_MMIO(0x71034), D_SKL_PLUS);
3026 MMIO_D(_MMIO(0x72034), D_SKL_PLUS);
3027
3028 MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_A)), D_SKL_PLUS);
3029 MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_B)), D_SKL_PLUS);
3030 MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_C)), D_SKL_PLUS);
3031 MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_A)), D_SKL_PLUS);
3032 MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_B)), D_SKL_PLUS);
3033 MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_C)), D_SKL_PLUS);
3034 MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_A)), D_SKL_PLUS);
3035 MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_B)), D_SKL_PLUS);
3036 MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_C)), D_SKL_PLUS);
3037
3038 MMIO_D(_MMIO(0x44500), D_SKL_PLUS);
3039 MMIO_DFH(GEN9_CSFE_CHICKEN1_RCS, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
3040 MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
3041 NULL, NULL);
3042 MMIO_DFH(GEN9_WM_CHICKEN3, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
3043 NULL, NULL);
3044
3045 MMIO_D(_MMIO(0x4ab8), D_KBL | D_CFL);
3046 MMIO_D(_MMIO(0x2248), D_SKL_PLUS);
3047
3048 return 0;
3049 }
3050
3051 static int init_bxt_mmio_info(struct intel_gvt *gvt)
3052 {
3053 struct drm_i915_private *dev_priv = gvt->dev_priv;
3054 int ret;
3055
3056 MMIO_F(_MMIO(0x80000), 0x3000, 0, 0, 0, D_BXT, NULL, NULL);
3057
3058 MMIO_D(GEN7_SAMPLER_INSTDONE, D_BXT);
3059 MMIO_D(GEN7_ROW_INSTDONE, D_BXT);
3060 MMIO_D(GEN8_FAULT_TLB_DATA0, D_BXT);
3061 MMIO_D(GEN8_FAULT_TLB_DATA1, D_BXT);
3062 MMIO_D(ERROR_GEN6, D_BXT);
3063 MMIO_D(DONE_REG, D_BXT);
3064 MMIO_D(EIR, D_BXT);
3065 MMIO_D(PGTBL_ER, D_BXT);
3066 MMIO_D(_MMIO(0x4194), D_BXT);
3067 MMIO_D(_MMIO(0x4294), D_BXT);
3068 MMIO_D(_MMIO(0x4494), D_BXT);
3069
3070 MMIO_RING_D(RING_PSMI_CTL, D_BXT);
3071 MMIO_RING_D(RING_DMA_FADD, D_BXT);
3072 MMIO_RING_D(RING_DMA_FADD_UDW, D_BXT);
3073 MMIO_RING_D(RING_IPEHR, D_BXT);
3074 MMIO_RING_D(RING_INSTPS, D_BXT);
3075 MMIO_RING_D(RING_BBADDR_UDW, D_BXT);
3076 MMIO_RING_D(RING_BBSTATE, D_BXT);
3077 MMIO_RING_D(RING_IPEIR, D_BXT);
3078
3079 MMIO_F(SOFT_SCRATCH(0), 16 * 4, 0, 0, 0, D_BXT, NULL, NULL);
3080
3081 MMIO_DH(BXT_P_CR_GT_DISP_PWRON, D_BXT, NULL, bxt_gt_disp_pwron_write);
3082 MMIO_D(BXT_RP_STATE_CAP, D_BXT);
3083 MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY0), D_BXT,
3084 NULL, bxt_phy_ctl_family_write);
3085 MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY1), D_BXT,
3086 NULL, bxt_phy_ctl_family_write);
3087 MMIO_D(BXT_PHY_CTL(PORT_A), D_BXT);
3088 MMIO_D(BXT_PHY_CTL(PORT_B), D_BXT);
3089 MMIO_D(BXT_PHY_CTL(PORT_C), D_BXT);
3090 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_A), D_BXT,
3091 NULL, bxt_port_pll_enable_write);
3092 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_B), D_BXT,
3093 NULL, bxt_port_pll_enable_write);
3094 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_C), D_BXT, NULL,
3095 bxt_port_pll_enable_write);
3096
3097 MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY0), D_BXT);
3098 MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY0), D_BXT);
3099 MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY0), D_BXT);
3100 MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY0), D_BXT);
3101 MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY0), D_BXT);
3102 MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY0), D_BXT);
3103 MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY0), D_BXT);
3104 MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY0), D_BXT);
3105 MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY0), D_BXT);
3106
3107 MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY1), D_BXT);
3108 MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY1), D_BXT);
3109 MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY1), D_BXT);
3110 MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY1), D_BXT);
3111 MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY1), D_BXT);
3112 MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY1), D_BXT);
3113 MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY1), D_BXT);
3114 MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY1), D_BXT);
3115 MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY1), D_BXT);
3116
3117 MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH0), D_BXT);
3118 MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH0), D_BXT);
3119 MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
3120 MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
3121 MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
3122 MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH0), D_BXT);
3123 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0), D_BXT,
3124 NULL, bxt_pcs_dw12_grp_write);
3125 MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
3126 MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
3127 MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH0), D_BXT,
3128 bxt_port_tx_dw3_read, NULL);
3129 MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
3130 MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
3131 MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
3132 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
3133 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
3134 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
3135 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
3136 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
3137 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
3138 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
3139 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
3140 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 6), D_BXT);
3141 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 8), D_BXT);
3142 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 9), D_BXT);
3143 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 10), D_BXT);
3144
3145 MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH1), D_BXT);
3146 MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH1), D_BXT);
3147 MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
3148 MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
3149 MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
3150 MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH1), D_BXT);
3151 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH1), D_BXT,
3152 NULL, bxt_pcs_dw12_grp_write);
3153 MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
3154 MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
3155 MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH1), D_BXT,
3156 bxt_port_tx_dw3_read, NULL);
3157 MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
3158 MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
3159 MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
3160 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
3161 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
3162 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
3163 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
3164 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
3165 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
3166 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
3167 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
3168 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 6), D_BXT);
3169 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 8), D_BXT);
3170 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 9), D_BXT);
3171 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 10), D_BXT);
3172
3173 MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY1, DPIO_CH0), D_BXT);
3174 MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY1, DPIO_CH0), D_BXT);
3175 MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
3176 MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
3177 MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
3178 MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY1, DPIO_CH0), D_BXT);
3179 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY1, DPIO_CH0), D_BXT,
3180 NULL, bxt_pcs_dw12_grp_write);
3181 MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
3182 MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
3183 MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY1, DPIO_CH0), D_BXT,
3184 bxt_port_tx_dw3_read, NULL);
3185 MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
3186 MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
3187 MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
3188 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
3189 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
3190 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
3191 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
3192 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
3193 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
3194 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
3195 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
3196 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 6), D_BXT);
3197 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 8), D_BXT);
3198 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 9), D_BXT);
3199 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 10), D_BXT);
3200
3201 MMIO_D(BXT_DE_PLL_CTL, D_BXT);
3202 MMIO_DH(BXT_DE_PLL_ENABLE, D_BXT, NULL, bxt_de_pll_enable_write);
3203 MMIO_D(BXT_DSI_PLL_CTL, D_BXT);
3204 MMIO_D(BXT_DSI_PLL_ENABLE, D_BXT);
3205
3206 MMIO_D(GEN9_CLKGATE_DIS_0, D_BXT);
3207 MMIO_D(GEN9_CLKGATE_DIS_4, D_BXT);
3208
3209 MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_A), D_BXT);
3210 MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_B), D_BXT);
3211 MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_C), D_BXT);
3212
3213 MMIO_D(RC6_CTX_BASE, D_BXT);
3214
3215 MMIO_D(GEN8_PUSHBUS_CONTROL, D_BXT);
3216 MMIO_D(GEN8_PUSHBUS_ENABLE, D_BXT);
3217 MMIO_D(GEN8_PUSHBUS_SHIFT, D_BXT);
3218 MMIO_D(GEN6_GFXPAUSE, D_BXT);
3219 MMIO_D(GEN8_L3SQCREG1, D_BXT);
3220
3221 MMIO_DFH(GEN9_CTX_PREEMPT_REG, D_BXT, F_CMD_ACCESS, NULL, NULL);
3222
3223 return 0;
3224 }
3225
3226 static struct gvt_mmio_block *find_mmio_block(struct intel_gvt *gvt,
3227 unsigned int offset)
3228 {
3229 unsigned long device = intel_gvt_get_device_type(gvt);
3230 struct gvt_mmio_block *block = gvt->mmio.mmio_block;
3231 int num = gvt->mmio.num_mmio_block;
3232 int i;
3233
3234 for (i = 0; i < num; i++, block++) {
3235 if (!(device & block->device))
3236 continue;
3237 if (offset >= i915_mmio_reg_offset(block->offset) &&
3238 offset < i915_mmio_reg_offset(block->offset) + block->size)
3239 return block;
3240 }
3241 return NULL;
3242 }
3243
3244 /**
3245 * intel_gvt_clean_mmio_info - clean up MMIO information table for GVT device
3246 * @gvt: GVT device
3247 *
3248 * This function is called at the driver unloading stage, to clean up the MMIO
3249 * information table of GVT device
3250 *
3251 */
3252 void intel_gvt_clean_mmio_info(struct intel_gvt *gvt)
3253 {
3254 struct hlist_node *tmp;
3255 struct intel_gvt_mmio_info *e;
3256 int i;
3257
3258 hash_for_each_safe(gvt->mmio.mmio_info_table, i, tmp, e, node)
3259 kfree(e);
3260
3261 vfree(gvt->mmio.mmio_attribute);
3262 gvt->mmio.mmio_attribute = NULL;
3263 }
3264
3265 /* Special MMIO blocks. */
3266 static struct gvt_mmio_block mmio_blocks[] = {
3267 {D_SKL_PLUS, _MMIO(CSR_MMIO_START_RANGE), 0x3000, NULL, NULL},
3268 {D_ALL, _MMIO(MCHBAR_MIRROR_BASE_SNB), 0x40000, NULL, NULL},
3269 {D_ALL, _MMIO(VGT_PVINFO_PAGE), VGT_PVINFO_SIZE,
3270 pvinfo_mmio_read, pvinfo_mmio_write},
3271 {D_ALL, LGC_PALETTE(PIPE_A, 0), 1024, NULL, NULL},
3272 {D_ALL, LGC_PALETTE(PIPE_B, 0), 1024, NULL, NULL},
3273 {D_ALL, LGC_PALETTE(PIPE_C, 0), 1024, NULL, NULL},
3274 };
3275
3276 /**
3277 * intel_gvt_setup_mmio_info - setup MMIO information table for GVT device
3278 * @gvt: GVT device
3279 *
3280 * This function is called at the initialization stage, to setup the MMIO
3281 * information table for GVT device
3282 *
3283 * Returns:
3284 * zero on success, negative if failed.
3285 */
3286 int intel_gvt_setup_mmio_info(struct intel_gvt *gvt)
3287 {
3288 struct intel_gvt_device_info *info = &gvt->device_info;
3289 struct drm_i915_private *dev_priv = gvt->dev_priv;
3290 int size = info->mmio_size / 4 * sizeof(*gvt->mmio.mmio_attribute);
3291 int ret;
3292
3293 gvt->mmio.mmio_attribute = vzalloc(size);
3294 if (!gvt->mmio.mmio_attribute)
3295 return -ENOMEM;
3296
3297 ret = init_generic_mmio_info(gvt);
3298 if (ret)
3299 goto err;
3300
3301 if (IS_BROADWELL(dev_priv)) {
3302 ret = init_broadwell_mmio_info(gvt);
3303 if (ret)
3304 goto err;
3305 } else if (IS_SKYLAKE(dev_priv)
3306 || IS_KABYLAKE(dev_priv)
3307 || IS_COFFEELAKE(dev_priv)) {
3308 ret = init_broadwell_mmio_info(gvt);
3309 if (ret)
3310 goto err;
3311 ret = init_skl_mmio_info(gvt);
3312 if (ret)
3313 goto err;
3314 } else if (IS_BROXTON(dev_priv)) {
3315 ret = init_broadwell_mmio_info(gvt);
3316 if (ret)
3317 goto err;
3318 ret = init_skl_mmio_info(gvt);
3319 if (ret)
3320 goto err;
3321 ret = init_bxt_mmio_info(gvt);
3322 if (ret)
3323 goto err;
3324 }
3325
3326 gvt->mmio.mmio_block = mmio_blocks;
3327 gvt->mmio.num_mmio_block = ARRAY_SIZE(mmio_blocks);
3328
3329 return 0;
3330 err:
3331 intel_gvt_clean_mmio_info(gvt);
3332 return ret;
3333 }
3334
3335 /**
3336 * intel_gvt_for_each_tracked_mmio - iterate each tracked mmio
3337 * @gvt: a GVT device
3338 * @handler: the handler
3339 * @data: private data given to handler
3340 *
3341 * Returns:
3342 * Zero on success, negative error code if failed.
3343 */
3344 int intel_gvt_for_each_tracked_mmio(struct intel_gvt *gvt,
3345 int (*handler)(struct intel_gvt *gvt, u32 offset, void *data),
3346 void *data)
3347 {
3348 struct gvt_mmio_block *block = gvt->mmio.mmio_block;
3349 struct intel_gvt_mmio_info *e;
3350 int i, j, ret;
3351
3352 hash_for_each(gvt->mmio.mmio_info_table, i, e, node) {
3353 ret = handler(gvt, e->offset, data);
3354 if (ret)
3355 return ret;
3356 }
3357
3358 for (i = 0; i < gvt->mmio.num_mmio_block; i++, block++) {
3359 for (j = 0; j < block->size; j += 4) {
3360 ret = handler(gvt,
3361 i915_mmio_reg_offset(block->offset) + j,
3362 data);
3363 if (ret)
3364 return ret;
3365 }
3366 }
3367 return 0;
3368 }
3369
3370 /**
3371 * intel_vgpu_default_mmio_read - default MMIO read handler
3372 * @vgpu: a vGPU
3373 * @offset: access offset
3374 * @p_data: data return buffer
3375 * @bytes: access data length
3376 *
3377 * Returns:
3378 * Zero on success, negative error code if failed.
3379 */
3380 int intel_vgpu_default_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
3381 void *p_data, unsigned int bytes)
3382 {
3383 read_vreg(vgpu, offset, p_data, bytes);
3384 return 0;
3385 }
3386
3387 /**
3388 * intel_t_default_mmio_write - default MMIO write handler
3389 * @vgpu: a vGPU
3390 * @offset: access offset
3391 * @p_data: write data buffer
3392 * @bytes: access data length
3393 *
3394 * Returns:
3395 * Zero on success, negative error code if failed.
3396 */
3397 int intel_vgpu_default_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
3398 void *p_data, unsigned int bytes)
3399 {
3400 write_vreg(vgpu, offset, p_data, bytes);
3401 return 0;
3402 }
3403
3404 /**
3405 * intel_vgpu_mask_mmio_write - write mask register
3406 * @vgpu: a vGPU
3407 * @offset: access offset
3408 * @p_data: write data buffer
3409 * @bytes: access data length
3410 *
3411 * Returns:
3412 * Zero on success, negative error code if failed.
3413 */
3414 int intel_vgpu_mask_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
3415 void *p_data, unsigned int bytes)
3416 {
3417 u32 mask, old_vreg;
3418
3419 old_vreg = vgpu_vreg(vgpu, offset);
3420 write_vreg(vgpu, offset, p_data, bytes);
3421 mask = vgpu_vreg(vgpu, offset) >> 16;
3422 vgpu_vreg(vgpu, offset) = (old_vreg & ~mask) |
3423 (vgpu_vreg(vgpu, offset) & mask);
3424
3425 return 0;
3426 }
3427
3428 /**
3429 * intel_gvt_in_force_nonpriv_whitelist - if a mmio is in whitelist to be
3430 * force-nopriv register
3431 *
3432 * @gvt: a GVT device
3433 * @offset: register offset
3434 *
3435 * Returns:
3436 * True if the register is in force-nonpriv whitelist;
3437 * False if outside;
3438 */
3439 bool intel_gvt_in_force_nonpriv_whitelist(struct intel_gvt *gvt,
3440 unsigned int offset)
3441 {
3442 return in_whitelist(offset);
3443 }
3444
3445 /**
3446 * intel_vgpu_mmio_reg_rw - emulate tracked mmio registers
3447 * @vgpu: a vGPU
3448 * @offset: register offset
3449 * @pdata: data buffer
3450 * @bytes: data length
3451 * @is_read: read or write
3452 *
3453 * Returns:
3454 * Zero on success, negative error code if failed.
3455 */
3456 int intel_vgpu_mmio_reg_rw(struct intel_vgpu *vgpu, unsigned int offset,
3457 void *pdata, unsigned int bytes, bool is_read)
3458 {
3459 struct intel_gvt *gvt = vgpu->gvt;
3460 struct intel_gvt_mmio_info *mmio_info;
3461 struct gvt_mmio_block *mmio_block;
3462 gvt_mmio_func func;
3463 int ret;
3464
3465 if (WARN_ON(bytes > 8))
3466 return -EINVAL;
3467
3468 /*
3469 * Handle special MMIO blocks.
3470 */
3471 mmio_block = find_mmio_block(gvt, offset);
3472 if (mmio_block) {
3473 func = is_read ? mmio_block->read : mmio_block->write;
3474 if (func)
3475 return func(vgpu, offset, pdata, bytes);
3476 goto default_rw;
3477 }
3478
3479 /*
3480 * Normal tracked MMIOs.
3481 */
3482 mmio_info = find_mmio_info(gvt, offset);
3483 if (!mmio_info) {
3484 gvt_dbg_mmio("untracked MMIO %08x len %d\n", offset, bytes);
3485 goto default_rw;
3486 }
3487
3488 if (is_read)
3489 return mmio_info->read(vgpu, offset, pdata, bytes);
3490 else {
3491 u64 ro_mask = mmio_info->ro_mask;
3492 u32 old_vreg = 0, old_sreg = 0;
3493 u64 data = 0;
3494
3495 if (intel_gvt_mmio_has_mode_mask(gvt, mmio_info->offset)) {
3496 old_vreg = vgpu_vreg(vgpu, offset);
3497 old_sreg = vgpu_sreg(vgpu, offset);
3498 }
3499
3500 if (likely(!ro_mask))
3501 ret = mmio_info->write(vgpu, offset, pdata, bytes);
3502 else if (!~ro_mask) {
3503 gvt_vgpu_err("try to write RO reg %x\n", offset);
3504 return 0;
3505 } else {
3506 /* keep the RO bits in the virtual register */
3507 memcpy(&data, pdata, bytes);
3508 data &= ~ro_mask;
3509 data |= vgpu_vreg(vgpu, offset) & ro_mask;
3510 ret = mmio_info->write(vgpu, offset, &data, bytes);
3511 }
3512
3513 /* higher 16bits of mode ctl regs are mask bits for change */
3514 if (intel_gvt_mmio_has_mode_mask(gvt, mmio_info->offset)) {
3515 u32 mask = vgpu_vreg(vgpu, offset) >> 16;
3516
3517 vgpu_vreg(vgpu, offset) = (old_vreg & ~mask)
3518 | (vgpu_vreg(vgpu, offset) & mask);
3519 vgpu_sreg(vgpu, offset) = (old_sreg & ~mask)
3520 | (vgpu_sreg(vgpu, offset) & mask);
3521 }
3522 }
3523
3524 return ret;
3525
3526 default_rw:
3527 return is_read ?
3528 intel_vgpu_default_mmio_read(vgpu, offset, pdata, bytes) :
3529 intel_vgpu_default_mmio_write(vgpu, offset, pdata, bytes);
3530 }
A mirror of Linus' kernel repository