drivers/gpu/drm/i915/gvt/reg.h

   1 /*
   2  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  */
  23
  24 #ifndef _GVT_REG_H
  25 #define _GVT_REG_H
  26
  27 #define INTEL_GVT_PCI_CLASS_VGA_OTHER   0x80
  28
  29 #define INTEL_GVT_PCI_GMCH_CONTROL      0x50
  30 #define   BDW_GMCH_GMS_SHIFT            8
  31 #define   BDW_GMCH_GMS_MASK             0xff
  32
  33 #define INTEL_GVT_PCI_SWSCI             0xe8
  34 #define   SWSCI_SCI_SELECT              (1 << 15)
  35 #define   SWSCI_SCI_TRIGGER             1
  36
  37 #define INTEL_GVT_PCI_OPREGION          0xfc
  38
  39 #define INTEL_GVT_OPREGION_CLID         0x1AC
  40 #define INTEL_GVT_OPREGION_SCIC         0x200
  41 #define   OPREGION_SCIC_FUNC_MASK       0x1E
  42 #define   OPREGION_SCIC_FUNC_SHIFT      1
  43 #define   OPREGION_SCIC_SUBFUNC_MASK    0xFF00
  44 #define   OPREGION_SCIC_SUBFUNC_SHIFT   8
  45 #define   OPREGION_SCIC_EXIT_MASK       0xE0
  46 #define INTEL_GVT_OPREGION_SCIC_F_GETBIOSDATA         4
  47 #define INTEL_GVT_OPREGION_SCIC_F_GETBIOSCALLBACKS    6
  48 #define INTEL_GVT_OPREGION_SCIC_SF_SUPPRTEDCALLS      0
  49 #define INTEL_GVT_OPREGION_SCIC_SF_REQEUSTEDCALLBACKS 1
  50 #define INTEL_GVT_OPREGION_PARM                   0x204
  51
  52 #define INTEL_GVT_OPREGION_PAGES        2
  53 #define INTEL_GVT_OPREGION_SIZE         (INTEL_GVT_OPREGION_PAGES * PAGE_SIZE)
  54 #define INTEL_GVT_OPREGION_VBT_OFFSET   0x400
  55 #define INTEL_GVT_OPREGION_VBT_SIZE     \
  56                 (INTEL_GVT_OPREGION_SIZE - INTEL_GVT_OPREGION_VBT_OFFSET)
  57
  58 #define VGT_SPRSTRIDE(pipe)     _PIPE(pipe, _SPRA_STRIDE, _PLANE_STRIDE_2_B)
  59
  60 #define _REG_701C0(pipe, plane) (0x701c0 + pipe * 0x1000 + (plane - 1) * 0x100)
  61 #define _REG_701C4(pipe, plane) (0x701c4 + pipe * 0x1000 + (plane - 1) * 0x100)
  62
  63 #define GFX_MODE_BIT_SET_IN_MASK(val, bit) \
  64                 ((((bit) & 0xffff0000) == 0) && !!((val) & (((bit) << 16))))
  65
  66 #define FORCEWAKE_RENDER_GEN9_REG 0xa278
  67 #define FORCEWAKE_ACK_RENDER_GEN9_REG 0x0D84
  68 #define FORCEWAKE_BLITTER_GEN9_REG 0xa188
  69 #define FORCEWAKE_ACK_BLITTER_GEN9_REG 0x130044
  70 #define FORCEWAKE_MEDIA_GEN9_REG 0xa270
  71 #define FORCEWAKE_ACK_MEDIA_GEN9_REG 0x0D88
  72 #define FORCEWAKE_ACK_HSW_REG 0x130044
  73
  74 #define RB_HEAD_OFF_MASK        ((1U << 21) - (1U << 2))
  75 #define RB_TAIL_OFF_MASK        ((1U << 21) - (1U << 3))
  76 #define RB_TAIL_SIZE_MASK       ((1U << 21) - (1U << 12))
  77 #define _RING_CTL_BUF_SIZE(ctl) (((ctl) & RB_TAIL_SIZE_MASK) + \
  78                 I915_GTT_PAGE_SIZE)
  79
  80 #define PCH_GPIO_BASE   _MMIO(0xc5010)
  81
  82 #define PCH_GMBUS0      _MMIO(0xc5100)
  83 #define PCH_GMBUS1      _MMIO(0xc5104)
  84 #define PCH_GMBUS2      _MMIO(0xc5108)
  85 #define PCH_GMBUS3      _MMIO(0xc510c)
  86 #define PCH_GMBUS4      _MMIO(0xc5110)
  87 #define PCH_GMBUS5      _MMIO(0xc5120)
  88
  89 #define TRVATTL3PTRDW(i)        _MMIO(0x4de0 + (i) * 4)
  90 #define TRNULLDETCT             _MMIO(0x4de8)
  91 #define TRINVTILEDETCT          _MMIO(0x4dec)
  92 #define TRVADR                  _MMIO(0x4df0)
  93 #define TRTTE                   _MMIO(0x4df4)
  94 #define RING_EXCC(base)         _MMIO((base) + 0x28)
  95 #define RING_GFX_MODE(base)     _MMIO((base) + 0x29c)
  96 #define VF_GUARDBAND            _MMIO(0x83a4)
  97
  98 #endif