1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #include <linux/acpi.h>
31 #include <linux/device.h>
32 #include <linux/module.h>
33 #include <linux/oom.h>
34 #include <linux/pci.h>
36 #include <linux/pm_runtime.h>
37 #include <linux/slab.h>
38 #include <linux/string_helpers.h>
39 #include <linux/vga_switcheroo.h>
42 #include <drm/drm_aperture.h>
43 #include <drm/drm_atomic_helper.h>
44 #include <drm/drm_ioctl.h>
45 #include <drm/drm_managed.h>
46 #include <drm/drm_probe_helper.h>
48 #include "display/intel_acpi.h"
49 #include "display/intel_bw.h"
50 #include "display/intel_cdclk.h"
51 #include "display/intel_display_driver.h"
52 #include "display/intel_display_types.h"
53 #include "display/intel_dmc.h"
54 #include "display/intel_dp.h"
55 #include "display/intel_dpt.h"
56 #include "display/intel_fbdev.h"
57 #include "display/intel_hotplug.h"
58 #include "display/intel_overlay.h"
59 #include "display/intel_pch_refclk.h"
60 #include "display/intel_pipe_crc.h"
61 #include "display/intel_pps.h"
62 #include "display/intel_sprite.h"
63 #include "display/intel_vga.h"
64 #include "display/skl_watermark.h"
66 #include "gem/i915_gem_context.h"
67 #include "gem/i915_gem_create.h"
68 #include "gem/i915_gem_dmabuf.h"
69 #include "gem/i915_gem_ioctls.h"
70 #include "gem/i915_gem_mman.h"
71 #include "gem/i915_gem_pm.h"
72 #include "gt/intel_gt.h"
73 #include "gt/intel_gt_pm.h"
74 #include "gt/intel_gt_print.h"
75 #include "gt/intel_rc6.h"
77 #include "pxp/intel_pxp.h"
78 #include "pxp/intel_pxp_debugfs.h"
79 #include "pxp/intel_pxp_pm.h"
81 #include "soc/intel_dram.h"
82 #include "soc/intel_gmch.h"
84 #include "i915_debugfs.h"
85 #include "i915_driver.h"
86 #include "i915_drm_client.h"
88 #include "i915_file_private.h"
89 #include "i915_getparam.h"
90 #include "i915_hwmon.h"
91 #include "i915_ioc32.h"
92 #include "i915_ioctl.h"
94 #include "i915_memcpy.h"
95 #include "i915_perf.h"
96 #include "i915_query.h"
97 #include "i915_suspend.h"
98 #include "i915_switcheroo.h"
99 #include "i915_sysfs.h"
100 #include "i915_utils.h"
101 #include "i915_vgpu.h"
102 #include "intel_clock_gating.h"
103 #include "intel_gvt.h"
104 #include "intel_memory_region.h"
105 #include "intel_pci_config.h"
106 #include "intel_pcode.h"
107 #include "intel_region_ttm.h"
108 #include "vlv_suspend.h"
110 static const struct drm_driver i915_drm_driver
;
112 static int i915_workqueues_init(struct drm_i915_private
*dev_priv
)
115 * The i915 workqueue is primarily used for batched retirement of
116 * requests (and thus managing bo) once the task has been completed
117 * by the GPU. i915_retire_requests() is called directly when we
118 * need high-priority retirement, such as waiting for an explicit
121 * It is also used for periodic low-priority events, such as
122 * idle-timers and recording error state.
124 * All tasks on the workqueue are expected to acquire the dev mutex
125 * so there is no point in running more than one instance of the
126 * workqueue at any time. Use an ordered one.
128 dev_priv
->wq
= alloc_ordered_workqueue("i915", 0);
129 if (dev_priv
->wq
== NULL
)
132 dev_priv
->display
.hotplug
.dp_wq
= alloc_ordered_workqueue("i915-dp", 0);
133 if (dev_priv
->display
.hotplug
.dp_wq
== NULL
)
137 * The unordered i915 workqueue should be used for all work
138 * scheduling that do not require running in order, which used
139 * to be scheduled on the system_wq before moving to a driver
140 * instance due deprecation of flush_scheduled_work().
142 dev_priv
->unordered_wq
= alloc_workqueue("i915-unordered", 0, 0);
143 if (dev_priv
->unordered_wq
== NULL
)
149 destroy_workqueue(dev_priv
->display
.hotplug
.dp_wq
);
151 destroy_workqueue(dev_priv
->wq
);
153 drm_err(&dev_priv
->drm
, "Failed to allocate workqueues.\n");
158 static void i915_workqueues_cleanup(struct drm_i915_private
*dev_priv
)
160 destroy_workqueue(dev_priv
->unordered_wq
);
161 destroy_workqueue(dev_priv
->display
.hotplug
.dp_wq
);
162 destroy_workqueue(dev_priv
->wq
);
166 * We don't keep the workarounds for pre-production hardware, so we expect our
167 * driver to fail on these machines in one way or another. A little warning on
168 * dmesg may help both the user and the bug triagers.
170 * Our policy for removing pre-production workarounds is to keep the
171 * current gen workarounds as a guide to the bring-up of the next gen
172 * (workarounds have a habit of persisting!). Anything older than that
173 * should be removed along with the complications they introduce.
175 static void intel_detect_preproduction_hw(struct drm_i915_private
*dev_priv
)
179 pre
|= IS_HASWELL_EARLY_SDV(dev_priv
);
180 pre
|= IS_SKYLAKE(dev_priv
) && INTEL_REVID(dev_priv
) < 0x6;
181 pre
|= IS_BROXTON(dev_priv
) && INTEL_REVID(dev_priv
) < 0xA;
182 pre
|= IS_KABYLAKE(dev_priv
) && INTEL_REVID(dev_priv
) < 0x1;
183 pre
|= IS_GEMINILAKE(dev_priv
) && INTEL_REVID(dev_priv
) < 0x3;
184 pre
|= IS_ICELAKE(dev_priv
) && INTEL_REVID(dev_priv
) < 0x7;
185 pre
|= IS_TIGERLAKE(dev_priv
) && INTEL_REVID(dev_priv
) < 0x1;
186 pre
|= IS_DG1(dev_priv
) && INTEL_REVID(dev_priv
) < 0x1;
187 pre
|= IS_DG2_G10(dev_priv
) && INTEL_REVID(dev_priv
) < 0x8;
188 pre
|= IS_DG2_G11(dev_priv
) && INTEL_REVID(dev_priv
) < 0x5;
189 pre
|= IS_DG2_G12(dev_priv
) && INTEL_REVID(dev_priv
) < 0x1;
192 drm_err(&dev_priv
->drm
, "This is a pre-production stepping. "
193 "It may not be fully functional.\n");
194 add_taint(TAINT_MACHINE_CHECK
, LOCKDEP_STILL_OK
);
198 static void sanitize_gpu(struct drm_i915_private
*i915
)
200 if (!INTEL_INFO(i915
)->gpu_reset_clobbers_display
) {
204 for_each_gt(gt
, i915
, i
)
205 __intel_gt_reset(gt
, ALL_ENGINES
);
210 * i915_driver_early_probe - setup state not requiring device access
211 * @dev_priv: device private
213 * Initialize everything that is a "SW-only" state, that is state not
214 * requiring accessing the device or exposing the driver via kernel internal
215 * or userspace interfaces. Example steps belonging here: lock initialization,
216 * system memory allocation, setting up device specific attributes and
217 * function hooks not requiring accessing the device.
219 static int i915_driver_early_probe(struct drm_i915_private
*dev_priv
)
223 if (i915_inject_probe_failure(dev_priv
))
226 intel_device_info_runtime_init_early(dev_priv
);
228 intel_step_init(dev_priv
);
230 intel_uncore_mmio_debug_init_early(dev_priv
);
232 spin_lock_init(&dev_priv
->irq_lock
);
233 spin_lock_init(&dev_priv
->gpu_error
.lock
);
235 mutex_init(&dev_priv
->sb_lock
);
236 cpu_latency_qos_add_request(&dev_priv
->sb_qos
, PM_QOS_DEFAULT_VALUE
);
238 i915_memcpy_init_early(dev_priv
);
239 intel_runtime_pm_init_early(&dev_priv
->runtime_pm
);
241 ret
= i915_workqueues_init(dev_priv
);
245 ret
= vlv_suspend_init(dev_priv
);
249 ret
= intel_region_ttm_device_init(dev_priv
);
253 ret
= intel_root_gt_init_early(dev_priv
);
257 i915_gem_init_early(dev_priv
);
259 /* This must be called before any calls to HAS_PCH_* */
260 intel_detect_pch(dev_priv
);
262 intel_irq_init(dev_priv
);
263 intel_display_driver_early_probe(dev_priv
);
264 intel_clock_gating_hooks_init(dev_priv
);
266 intel_detect_preproduction_hw(dev_priv
);
271 intel_region_ttm_device_fini(dev_priv
);
273 vlv_suspend_cleanup(dev_priv
);
275 i915_workqueues_cleanup(dev_priv
);
280 * i915_driver_late_release - cleanup the setup done in
281 * i915_driver_early_probe()
282 * @dev_priv: device private
284 static void i915_driver_late_release(struct drm_i915_private
*dev_priv
)
286 intel_irq_fini(dev_priv
);
287 intel_power_domains_cleanup(dev_priv
);
288 i915_gem_cleanup_early(dev_priv
);
289 intel_gt_driver_late_release_all(dev_priv
);
290 intel_region_ttm_device_fini(dev_priv
);
291 vlv_suspend_cleanup(dev_priv
);
292 i915_workqueues_cleanup(dev_priv
);
294 cpu_latency_qos_remove_request(&dev_priv
->sb_qos
);
295 mutex_destroy(&dev_priv
->sb_lock
);
297 i915_params_free(&dev_priv
->params
);
301 * i915_driver_mmio_probe - setup device MMIO
302 * @dev_priv: device private
304 * Setup minimal device state necessary for MMIO accesses later in the
305 * initialization sequence. The setup here should avoid any other device-wide
306 * side effects or exposing the driver via kernel internal or user space
309 static int i915_driver_mmio_probe(struct drm_i915_private
*dev_priv
)
314 if (i915_inject_probe_failure(dev_priv
))
317 ret
= intel_gmch_bridge_setup(dev_priv
);
321 for_each_gt(gt
, dev_priv
, i
) {
322 ret
= intel_uncore_init_mmio(gt
->uncore
);
326 ret
= drmm_add_action_or_reset(&dev_priv
->drm
,
327 intel_uncore_fini_mmio
,
333 /* Try to make sure MCHBAR is enabled before poking at it */
334 intel_gmch_bar_setup(dev_priv
);
335 intel_device_info_runtime_init(dev_priv
);
336 intel_display_device_info_runtime_init(dev_priv
);
338 for_each_gt(gt
, dev_priv
, i
) {
339 ret
= intel_gt_init_mmio(gt
);
344 /* As early as possible, scrub existing GPU state before clobbering */
345 sanitize_gpu(dev_priv
);
350 intel_gmch_bar_teardown(dev_priv
);
356 * i915_driver_mmio_release - cleanup the setup done in i915_driver_mmio_probe()
357 * @dev_priv: device private
359 static void i915_driver_mmio_release(struct drm_i915_private
*dev_priv
)
361 intel_gmch_bar_teardown(dev_priv
);
365 * i915_set_dma_info - set all relevant PCI dma info as configured for the
367 * @i915: valid i915 instance
369 * Set the dma max segment size, device and coherent masks. The dma mask set
370 * needs to occur before i915_ggtt_probe_hw.
372 * A couple of platforms have special needs. Address them as well.
375 static int i915_set_dma_info(struct drm_i915_private
*i915
)
377 unsigned int mask_size
= INTEL_INFO(i915
)->dma_mask_size
;
380 GEM_BUG_ON(!mask_size
);
383 * We don't have a max segment size, so set it to the max so sg's
384 * debugging layer doesn't complain
386 dma_set_max_seg_size(i915
->drm
.dev
, UINT_MAX
);
388 ret
= dma_set_mask(i915
->drm
.dev
, DMA_BIT_MASK(mask_size
));
392 /* overlay on gen2 is broken and can't address above 1G */
393 if (GRAPHICS_VER(i915
) == 2)
397 * 965GM sometimes incorrectly writes to hardware status page (HWS)
398 * using 32bit addressing, overwriting memory if HWS is located
401 * The documentation also mentions an issue with undefined
402 * behaviour if any general state is accessed within a page above 4GB,
403 * which also needs to be handled carefully.
405 if (IS_I965G(i915
) || IS_I965GM(i915
))
408 ret
= dma_set_coherent_mask(i915
->drm
.dev
, DMA_BIT_MASK(mask_size
));
415 drm_err(&i915
->drm
, "Can't set DMA mask/consistent mask (%d)\n", ret
);
419 static int i915_pcode_init(struct drm_i915_private
*i915
)
424 for_each_gt(gt
, i915
, id
) {
425 ret
= intel_pcode_init(gt
->uncore
);
427 gt_err(gt
, "intel_pcode_init failed %d\n", ret
);
436 * i915_driver_hw_probe - setup state requiring device access
437 * @dev_priv: device private
439 * Setup state that requires accessing the device, but doesn't require
440 * exposing the driver via kernel internal or userspace interfaces.
442 static int i915_driver_hw_probe(struct drm_i915_private
*dev_priv
)
444 struct pci_dev
*pdev
= to_pci_dev(dev_priv
->drm
.dev
);
447 if (i915_inject_probe_failure(dev_priv
))
450 if (HAS_PPGTT(dev_priv
)) {
451 if (intel_vgpu_active(dev_priv
) &&
452 !intel_vgpu_has_full_ppgtt(dev_priv
)) {
453 i915_report_error(dev_priv
,
454 "incompatible vGPU found, support for isolated ppGTT required\n");
459 if (HAS_EXECLISTS(dev_priv
)) {
461 * Older GVT emulation depends upon intercepting CSB mmio,
462 * which we no longer use, preferring to use the HWSP cache
465 if (intel_vgpu_active(dev_priv
) &&
466 !intel_vgpu_has_hwsp_emulation(dev_priv
)) {
467 i915_report_error(dev_priv
,
468 "old vGPU host found, support for HWSP emulation required\n");
473 /* needs to be done before ggtt probe */
474 intel_dram_edram_detect(dev_priv
);
476 ret
= i915_set_dma_info(dev_priv
);
480 ret
= i915_perf_init(dev_priv
);
484 ret
= i915_ggtt_probe_hw(dev_priv
);
488 ret
= drm_aperture_remove_conflicting_pci_framebuffers(pdev
, dev_priv
->drm
.driver
);
492 ret
= i915_ggtt_init_hw(dev_priv
);
497 * Make sure we probe lmem before we probe stolen-lmem. The BAR size
498 * might be different due to bar resizing.
500 ret
= intel_gt_tiles_init(dev_priv
);
504 ret
= intel_memory_regions_hw_probe(dev_priv
);
508 ret
= i915_ggtt_enable_hw(dev_priv
);
510 drm_err(&dev_priv
->drm
, "failed to enable GGTT\n");
511 goto err_mem_regions
;
514 pci_set_master(pdev
);
516 /* On the 945G/GM, the chipset reports the MSI capability on the
517 * integrated graphics even though the support isn't actually there
518 * according to the published specs. It doesn't appear to function
519 * correctly in testing on 945G.
520 * This may be a side effect of MSI having been made available for PEG
521 * and the registers being closely associated.
523 * According to chipset errata, on the 965GM, MSI interrupts may
524 * be lost or delayed, and was defeatured. MSI interrupts seem to
525 * get lost on g4x as well, and interrupt delivery seems to stay
526 * properly dead afterwards. So we'll just disable them for all
529 * dp aux and gmbus irq on gen4 seems to be able to generate legacy
530 * interrupts even when in MSI mode. This results in spurious
531 * interrupt warnings if the legacy irq no. is shared with another
532 * device. The kernel then disables that interrupt source and so
533 * prevents the other device from working properly.
535 if (GRAPHICS_VER(dev_priv
) >= 5) {
536 if (pci_enable_msi(pdev
) < 0)
537 drm_dbg(&dev_priv
->drm
, "can't enable MSI");
540 ret
= intel_gvt_init(dev_priv
);
544 intel_opregion_setup(dev_priv
);
546 ret
= i915_pcode_init(dev_priv
);
551 * Fill the dram structure to get the system dram info. This will be
552 * used for memory latency calculation.
554 intel_dram_detect(dev_priv
);
556 intel_bw_init_hw(dev_priv
);
561 intel_opregion_cleanup(dev_priv
);
563 if (pdev
->msi_enabled
)
564 pci_disable_msi(pdev
);
566 intel_memory_regions_driver_release(dev_priv
);
568 i915_ggtt_driver_release(dev_priv
);
569 i915_gem_drain_freed_objects(dev_priv
);
570 i915_ggtt_driver_late_release(dev_priv
);
572 i915_perf_fini(dev_priv
);
577 * i915_driver_hw_remove - cleanup the setup done in i915_driver_hw_probe()
578 * @dev_priv: device private
580 static void i915_driver_hw_remove(struct drm_i915_private
*dev_priv
)
582 struct pci_dev
*pdev
= to_pci_dev(dev_priv
->drm
.dev
);
584 i915_perf_fini(dev_priv
);
586 intel_opregion_cleanup(dev_priv
);
588 if (pdev
->msi_enabled
)
589 pci_disable_msi(pdev
);
593 * i915_driver_register - register the driver with the rest of the system
594 * @dev_priv: device private
596 * Perform any steps necessary to make the driver available via kernel
597 * internal or userspace interfaces.
599 static void i915_driver_register(struct drm_i915_private
*dev_priv
)
604 i915_gem_driver_register(dev_priv
);
605 i915_pmu_register(dev_priv
);
607 intel_vgpu_register(dev_priv
);
609 /* Reveal our presence to userspace */
610 if (drm_dev_register(&dev_priv
->drm
, 0)) {
611 drm_err(&dev_priv
->drm
,
612 "Failed to register driver for userspace access!\n");
616 i915_debugfs_register(dev_priv
);
617 i915_setup_sysfs(dev_priv
);
619 /* Depends on sysfs having been initialized */
620 i915_perf_register(dev_priv
);
622 for_each_gt(gt
, dev_priv
, i
)
623 intel_gt_driver_register(gt
);
625 intel_pxp_debugfs_register(dev_priv
->pxp
);
627 i915_hwmon_register(dev_priv
);
629 intel_display_driver_register(dev_priv
);
631 intel_power_domains_enable(dev_priv
);
632 intel_runtime_pm_enable(&dev_priv
->runtime_pm
);
634 intel_register_dsm_handler();
636 if (i915_switcheroo_register(dev_priv
))
637 drm_err(&dev_priv
->drm
, "Failed to register vga switcheroo!\n");
641 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
642 * @dev_priv: device private
644 static void i915_driver_unregister(struct drm_i915_private
*dev_priv
)
649 i915_switcheroo_unregister(dev_priv
);
651 intel_unregister_dsm_handler();
653 intel_runtime_pm_disable(&dev_priv
->runtime_pm
);
654 intel_power_domains_disable(dev_priv
);
656 intel_display_driver_unregister(dev_priv
);
658 intel_pxp_fini(dev_priv
);
660 for_each_gt(gt
, dev_priv
, i
)
661 intel_gt_driver_unregister(gt
);
663 i915_hwmon_unregister(dev_priv
);
665 i915_perf_unregister(dev_priv
);
666 i915_pmu_unregister(dev_priv
);
668 i915_teardown_sysfs(dev_priv
);
669 drm_dev_unplug(&dev_priv
->drm
);
671 i915_gem_driver_unregister(dev_priv
);
675 i915_print_iommu_status(struct drm_i915_private
*i915
, struct drm_printer
*p
)
677 drm_printf(p
, "iommu: %s\n",
678 str_enabled_disabled(i915_vtd_active(i915
)));
681 static void i915_welcome_messages(struct drm_i915_private
*dev_priv
)
683 if (drm_debug_enabled(DRM_UT_DRIVER
)) {
684 struct drm_printer p
= drm_debug_printer("i915 device info:");
688 drm_printf(&p
, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n",
689 INTEL_DEVID(dev_priv
),
690 INTEL_REVID(dev_priv
),
691 intel_platform_name(INTEL_INFO(dev_priv
)->platform
),
692 intel_subplatform(RUNTIME_INFO(dev_priv
),
693 INTEL_INFO(dev_priv
)->platform
),
694 GRAPHICS_VER(dev_priv
));
696 intel_device_info_print(INTEL_INFO(dev_priv
),
697 RUNTIME_INFO(dev_priv
), &p
);
698 i915_print_iommu_status(dev_priv
, &p
);
699 for_each_gt(gt
, dev_priv
, i
)
700 intel_gt_info_print(>
->info
, &p
);
703 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG
))
704 drm_info(&dev_priv
->drm
, "DRM_I915_DEBUG enabled\n");
705 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM
))
706 drm_info(&dev_priv
->drm
, "DRM_I915_DEBUG_GEM enabled\n");
707 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM
))
708 drm_info(&dev_priv
->drm
,
709 "DRM_I915_DEBUG_RUNTIME_PM enabled\n");
712 static struct drm_i915_private
*
713 i915_driver_create(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
715 const struct intel_device_info
*match_info
=
716 (struct intel_device_info
*)ent
->driver_data
;
717 struct drm_i915_private
*i915
;
719 i915
= devm_drm_dev_alloc(&pdev
->dev
, &i915_drm_driver
,
720 struct drm_i915_private
, drm
);
724 pci_set_drvdata(pdev
, i915
);
726 /* Device parameters start as a copy of module parameters. */
727 i915_params_copy(&i915
->params
, &i915_modparams
);
729 /* Set up device info and initial runtime info. */
730 intel_device_info_driver_create(i915
, pdev
->device
, match_info
);
732 intel_display_device_probe(i915
);
738 * i915_driver_probe - setup chip and create an initial config
740 * @ent: matching PCI ID entry
742 * The driver probe routine has to do several things:
743 * - drive output discovery via intel_display_driver_probe()
744 * - initialize the memory manager
745 * - allocate initial config memory
746 * - setup the DRM framebuffer with the allocated memory
748 int i915_driver_probe(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
750 struct drm_i915_private
*i915
;
753 ret
= pci_enable_device(pdev
);
755 pr_err("Failed to enable graphics device: %pe\n", ERR_PTR(ret
));
759 i915
= i915_driver_create(pdev
, ent
);
761 pci_disable_device(pdev
);
762 return PTR_ERR(i915
);
765 ret
= i915_driver_early_probe(i915
);
767 goto out_pci_disable
;
769 disable_rpm_wakeref_asserts(&i915
->runtime_pm
);
771 intel_vgpu_detect(i915
);
773 ret
= intel_gt_probe_all(i915
);
775 goto out_runtime_pm_put
;
777 ret
= i915_driver_mmio_probe(i915
);
779 goto out_runtime_pm_put
;
781 ret
= i915_driver_hw_probe(i915
);
783 goto out_cleanup_mmio
;
785 ret
= intel_display_driver_probe_noirq(i915
);
789 ret
= intel_irq_install(i915
);
791 goto out_cleanup_modeset
;
793 ret
= intel_display_driver_probe_nogem(i915
);
795 goto out_cleanup_irq
;
797 ret
= i915_gem_init(i915
);
799 goto out_cleanup_modeset2
;
801 ret
= intel_pxp_init(i915
);
803 drm_dbg(&i915
->drm
, "pxp init failed with %d\n", ret
);
805 ret
= intel_display_driver_probe(i915
);
807 goto out_cleanup_gem
;
809 i915_driver_register(i915
);
811 enable_rpm_wakeref_asserts(&i915
->runtime_pm
);
813 i915_welcome_messages(i915
);
815 i915
->do_release
= true;
820 i915_gem_suspend(i915
);
821 i915_gem_driver_remove(i915
);
822 i915_gem_driver_release(i915
);
823 out_cleanup_modeset2
:
824 /* FIXME clean up the error path */
825 intel_display_driver_remove(i915
);
826 intel_irq_uninstall(i915
);
827 intel_display_driver_remove_noirq(i915
);
828 goto out_cleanup_modeset
;
830 intel_irq_uninstall(i915
);
832 intel_display_driver_remove_nogem(i915
);
834 i915_driver_hw_remove(i915
);
835 intel_memory_regions_driver_release(i915
);
836 i915_ggtt_driver_release(i915
);
837 i915_gem_drain_freed_objects(i915
);
838 i915_ggtt_driver_late_release(i915
);
840 i915_driver_mmio_release(i915
);
842 enable_rpm_wakeref_asserts(&i915
->runtime_pm
);
843 i915_driver_late_release(i915
);
845 pci_disable_device(pdev
);
846 i915_probe_error(i915
, "Device initialization failed (%d)\n", ret
);
850 void i915_driver_remove(struct drm_i915_private
*i915
)
852 intel_wakeref_t wakeref
;
854 wakeref
= intel_runtime_pm_get(&i915
->runtime_pm
);
856 i915_driver_unregister(i915
);
858 /* Flush any external code that still may be under the RCU lock */
861 i915_gem_suspend(i915
);
863 intel_gvt_driver_remove(i915
);
865 intel_display_driver_remove(i915
);
867 intel_irq_uninstall(i915
);
869 intel_display_driver_remove_noirq(i915
);
871 i915_reset_error_state(i915
);
872 i915_gem_driver_remove(i915
);
874 intel_display_driver_remove_nogem(i915
);
876 i915_driver_hw_remove(i915
);
878 intel_runtime_pm_put(&i915
->runtime_pm
, wakeref
);
881 static void i915_driver_release(struct drm_device
*dev
)
883 struct drm_i915_private
*dev_priv
= to_i915(dev
);
884 struct intel_runtime_pm
*rpm
= &dev_priv
->runtime_pm
;
885 intel_wakeref_t wakeref
;
887 if (!dev_priv
->do_release
)
890 wakeref
= intel_runtime_pm_get(rpm
);
892 i915_gem_driver_release(dev_priv
);
894 intel_memory_regions_driver_release(dev_priv
);
895 i915_ggtt_driver_release(dev_priv
);
896 i915_gem_drain_freed_objects(dev_priv
);
897 i915_ggtt_driver_late_release(dev_priv
);
899 i915_driver_mmio_release(dev_priv
);
901 intel_runtime_pm_put(rpm
, wakeref
);
903 intel_runtime_pm_driver_release(rpm
);
905 i915_driver_late_release(dev_priv
);
907 intel_display_device_remove(dev_priv
);
910 static int i915_driver_open(struct drm_device
*dev
, struct drm_file
*file
)
912 struct drm_i915_private
*i915
= to_i915(dev
);
915 ret
= i915_gem_open(i915
, file
);
923 * i915_driver_lastclose - clean up after all DRM clients have exited
926 * Take care of cleaning up after all DRM clients have exited. In the
927 * mode setting case, we want to restore the kernel's initial mode (just
928 * in case the last client left us in a bad state).
930 * Additionally, in the non-mode setting case, we'll tear down the GTT
931 * and DMA structures, since the kernel won't be using them, and clea
934 static void i915_driver_lastclose(struct drm_device
*dev
)
936 struct drm_i915_private
*i915
= to_i915(dev
);
938 intel_fbdev_restore_mode(i915
);
940 vga_switcheroo_process_delayed_switch();
943 static void i915_driver_postclose(struct drm_device
*dev
, struct drm_file
*file
)
945 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
947 i915_gem_context_close(file
);
948 i915_drm_client_put(file_priv
->client
);
950 kfree_rcu(file_priv
, rcu
);
952 /* Catch up with all the deferred frees from "this" client */
953 i915_gem_flush_free_objects(to_i915(dev
));
956 static void intel_suspend_encoders(struct drm_i915_private
*dev_priv
)
958 struct intel_encoder
*encoder
;
960 if (!HAS_DISPLAY(dev_priv
))
964 * TODO: check and remove holding the modeset locks if none of
965 * the encoders depends on this.
967 drm_modeset_lock_all(&dev_priv
->drm
);
968 for_each_intel_encoder(&dev_priv
->drm
, encoder
)
969 if (encoder
->suspend
)
970 encoder
->suspend(encoder
);
971 drm_modeset_unlock_all(&dev_priv
->drm
);
973 for_each_intel_encoder(&dev_priv
->drm
, encoder
)
974 if (encoder
->suspend_complete
)
975 encoder
->suspend_complete(encoder
);
978 static void intel_shutdown_encoders(struct drm_i915_private
*dev_priv
)
980 struct intel_encoder
*encoder
;
982 if (!HAS_DISPLAY(dev_priv
))
986 * TODO: check and remove holding the modeset locks if none of
987 * the encoders depends on this.
989 drm_modeset_lock_all(&dev_priv
->drm
);
990 for_each_intel_encoder(&dev_priv
->drm
, encoder
)
991 if (encoder
->shutdown
)
992 encoder
->shutdown(encoder
);
993 drm_modeset_unlock_all(&dev_priv
->drm
);
995 for_each_intel_encoder(&dev_priv
->drm
, encoder
)
996 if (encoder
->shutdown_complete
)
997 encoder
->shutdown_complete(encoder
);
1000 void i915_driver_shutdown(struct drm_i915_private
*i915
)
1002 disable_rpm_wakeref_asserts(&i915
->runtime_pm
);
1003 intel_runtime_pm_disable(&i915
->runtime_pm
);
1004 intel_power_domains_disable(i915
);
1006 intel_fbdev_set_suspend(&i915
->drm
, FBINFO_STATE_SUSPENDED
, true);
1007 if (HAS_DISPLAY(i915
)) {
1008 drm_kms_helper_poll_disable(&i915
->drm
);
1009 intel_display_driver_disable_user_access(i915
);
1011 drm_atomic_helper_shutdown(&i915
->drm
);
1014 intel_dp_mst_suspend(i915
);
1016 intel_runtime_pm_disable_interrupts(i915
);
1017 intel_hpd_cancel_work(i915
);
1019 if (HAS_DISPLAY(i915
))
1020 intel_display_driver_suspend_access(i915
);
1022 intel_suspend_encoders(i915
);
1023 intel_shutdown_encoders(i915
);
1025 intel_dmc_suspend(i915
);
1027 i915_gem_suspend(i915
);
1030 * The only requirement is to reboot with display DC states disabled,
1031 * for now leaving all display power wells in the INIT power domain
1035 * - unify the pci_driver::shutdown sequence here with the
1036 * pci_driver.driver.pm.poweroff,poweroff_late sequence.
1037 * - unify the driver remove and system/runtime suspend sequences with
1038 * the above unified shutdown/poweroff sequence.
1040 intel_power_domains_driver_remove(i915
);
1041 enable_rpm_wakeref_asserts(&i915
->runtime_pm
);
1043 intel_runtime_pm_driver_last_release(&i915
->runtime_pm
);
1046 static bool suspend_to_idle(struct drm_i915_private
*dev_priv
)
1048 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1049 if (acpi_target_system_state() < ACPI_STATE_S3
)
1055 static void i915_drm_complete(struct drm_device
*dev
)
1057 struct drm_i915_private
*i915
= to_i915(dev
);
1059 intel_pxp_resume_complete(i915
->pxp
);
1062 static int i915_drm_prepare(struct drm_device
*dev
)
1064 struct drm_i915_private
*i915
= to_i915(dev
);
1066 intel_pxp_suspend_prepare(i915
->pxp
);
1069 * NB intel_display_driver_suspend() may issue new requests after we've
1070 * ostensibly marked the GPU as ready-to-sleep here. We need to
1071 * split out that work and pull it forward so that after point,
1072 * the GPU is not woken again.
1074 return i915_gem_backup_suspend(i915
);
1077 static int i915_drm_suspend(struct drm_device
*dev
)
1079 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1080 struct pci_dev
*pdev
= to_pci_dev(dev_priv
->drm
.dev
);
1081 pci_power_t opregion_target_state
;
1083 disable_rpm_wakeref_asserts(&dev_priv
->runtime_pm
);
1085 /* We do a lot of poking in a lot of registers, make sure they work
1087 intel_power_domains_disable(dev_priv
);
1088 intel_fbdev_set_suspend(dev
, FBINFO_STATE_SUSPENDED
, true);
1089 if (HAS_DISPLAY(dev_priv
)) {
1090 drm_kms_helper_poll_disable(dev
);
1091 intel_display_driver_disable_user_access(dev_priv
);
1094 pci_save_state(pdev
);
1096 intel_display_driver_suspend(dev_priv
);
1098 intel_dp_mst_suspend(dev_priv
);
1100 intel_runtime_pm_disable_interrupts(dev_priv
);
1101 intel_hpd_cancel_work(dev_priv
);
1103 if (HAS_DISPLAY(dev_priv
))
1104 intel_display_driver_suspend_access(dev_priv
);
1106 intel_suspend_encoders(dev_priv
);
1108 /* Must be called before GGTT is suspended. */
1109 intel_dpt_suspend(dev_priv
);
1110 i915_ggtt_suspend(to_gt(dev_priv
)->ggtt
);
1112 i915_save_display(dev_priv
);
1114 opregion_target_state
= suspend_to_idle(dev_priv
) ? PCI_D1
: PCI_D3cold
;
1115 intel_opregion_suspend(dev_priv
, opregion_target_state
);
1117 dev_priv
->suspend_count
++;
1119 intel_dmc_suspend(dev_priv
);
1121 enable_rpm_wakeref_asserts(&dev_priv
->runtime_pm
);
1123 i915_gem_drain_freed_objects(dev_priv
);
1128 static int i915_drm_suspend_late(struct drm_device
*dev
, bool hibernation
)
1130 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1131 struct pci_dev
*pdev
= to_pci_dev(dev_priv
->drm
.dev
);
1132 struct intel_runtime_pm
*rpm
= &dev_priv
->runtime_pm
;
1133 struct intel_gt
*gt
;
1135 bool s2idle
= !hibernation
&& suspend_to_idle(dev_priv
);
1137 disable_rpm_wakeref_asserts(rpm
);
1139 intel_pxp_suspend(dev_priv
->pxp
);
1141 i915_gem_suspend_late(dev_priv
);
1143 for_each_gt(gt
, dev_priv
, i
)
1144 intel_uncore_suspend(gt
->uncore
);
1146 intel_power_domains_suspend(dev_priv
, s2idle
);
1148 intel_display_power_suspend_late(dev_priv
);
1150 ret
= vlv_suspend_complete(dev_priv
);
1152 drm_err(&dev_priv
->drm
, "Suspend complete failed: %d\n", ret
);
1153 intel_power_domains_resume(dev_priv
);
1158 pci_disable_device(pdev
);
1160 * During hibernation on some platforms the BIOS may try to access
1161 * the device even though it's already in D3 and hang the machine. So
1162 * leave the device in D0 on those platforms and hope the BIOS will
1163 * power down the device properly. The issue was seen on multiple old
1164 * GENs with different BIOS vendors, so having an explicit blacklist
1165 * is inpractical; apply the workaround on everything pre GEN6. The
1166 * platforms where the issue was seen:
1167 * Lenovo Thinkpad X301, X61s, X60, T60, X41
1171 if (!(hibernation
&& GRAPHICS_VER(dev_priv
) < 6))
1172 pci_set_power_state(pdev
, PCI_D3hot
);
1175 enable_rpm_wakeref_asserts(rpm
);
1176 if (!dev_priv
->uncore
.user_forcewake_count
)
1177 intel_runtime_pm_driver_release(rpm
);
1182 int i915_driver_suspend_switcheroo(struct drm_i915_private
*i915
,
1187 if (drm_WARN_ON_ONCE(&i915
->drm
, state
.event
!= PM_EVENT_SUSPEND
&&
1188 state
.event
!= PM_EVENT_FREEZE
))
1191 if (i915
->drm
.switch_power_state
== DRM_SWITCH_POWER_OFF
)
1194 error
= i915_drm_suspend(&i915
->drm
);
1198 return i915_drm_suspend_late(&i915
->drm
, false);
1201 static int i915_drm_resume(struct drm_device
*dev
)
1203 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1204 struct intel_gt
*gt
;
1207 disable_rpm_wakeref_asserts(&dev_priv
->runtime_pm
);
1209 ret
= i915_pcode_init(dev_priv
);
1213 sanitize_gpu(dev_priv
);
1215 ret
= i915_ggtt_enable_hw(dev_priv
);
1217 drm_err(&dev_priv
->drm
, "failed to re-enable GGTT\n");
1219 i915_ggtt_resume(to_gt(dev_priv
)->ggtt
);
1221 for_each_gt(gt
, dev_priv
, i
)
1222 if (GRAPHICS_VER(gt
->i915
) >= 8)
1223 setup_private_pat(gt
);
1225 /* Must be called after GGTT is resumed. */
1226 intel_dpt_resume(dev_priv
);
1228 intel_dmc_resume(dev_priv
);
1230 i915_restore_display(dev_priv
);
1231 intel_pps_unlock_regs_wa(dev_priv
);
1233 intel_init_pch_refclk(dev_priv
);
1236 * Interrupts have to be enabled before any batches are run. If not the
1237 * GPU will hang. i915_gem_init_hw() will initiate batches to
1238 * update/restore the context.
1240 * drm_mode_config_reset() needs AUX interrupts.
1242 * Modeset enabling in intel_display_driver_init_hw() also needs working
1245 intel_runtime_pm_enable_interrupts(dev_priv
);
1247 if (HAS_DISPLAY(dev_priv
))
1248 drm_mode_config_reset(dev
);
1250 i915_gem_resume(dev_priv
);
1252 intel_display_driver_init_hw(dev_priv
);
1254 intel_clock_gating_init(dev_priv
);
1256 if (HAS_DISPLAY(dev_priv
))
1257 intel_display_driver_resume_access(dev_priv
);
1259 intel_hpd_init(dev_priv
);
1261 /* MST sideband requires HPD interrupts enabled */
1262 intel_dp_mst_resume(dev_priv
);
1263 intel_display_driver_resume(dev_priv
);
1265 if (HAS_DISPLAY(dev_priv
)) {
1266 intel_display_driver_enable_user_access(dev_priv
);
1267 drm_kms_helper_poll_enable(dev
);
1269 intel_hpd_poll_disable(dev_priv
);
1271 intel_opregion_resume(dev_priv
);
1273 intel_fbdev_set_suspend(dev
, FBINFO_STATE_RUNNING
, false);
1275 intel_power_domains_enable(dev_priv
);
1277 intel_gvt_resume(dev_priv
);
1279 enable_rpm_wakeref_asserts(&dev_priv
->runtime_pm
);
1284 static int i915_drm_resume_early(struct drm_device
*dev
)
1286 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1287 struct pci_dev
*pdev
= to_pci_dev(dev_priv
->drm
.dev
);
1288 struct intel_gt
*gt
;
1292 * We have a resume ordering issue with the snd-hda driver also
1293 * requiring our device to be power up. Due to the lack of a
1294 * parent/child relationship we currently solve this with an early
1297 * FIXME: This should be solved with a special hdmi sink device or
1298 * similar so that power domains can be employed.
1302 * Note that we need to set the power state explicitly, since we
1303 * powered off the device during freeze and the PCI core won't power
1304 * it back up for us during thaw. Powering off the device during
1305 * freeze is not a hard requirement though, and during the
1306 * suspend/resume phases the PCI core makes sure we get here with the
1307 * device powered on. So in case we change our freeze logic and keep
1308 * the device powered we can also remove the following set power state
1311 ret
= pci_set_power_state(pdev
, PCI_D0
);
1313 drm_err(&dev_priv
->drm
,
1314 "failed to set PCI D0 power state (%d)\n", ret
);
1319 * Note that pci_enable_device() first enables any parent bridge
1320 * device and only then sets the power state for this device. The
1321 * bridge enabling is a nop though, since bridge devices are resumed
1322 * first. The order of enabling power and enabling the device is
1323 * imposed by the PCI core as described above, so here we preserve the
1324 * same order for the freeze/thaw phases.
1326 * TODO: eventually we should remove pci_disable_device() /
1327 * pci_enable_enable_device() from suspend/resume. Due to how they
1328 * depend on the device enable refcount we can't anyway depend on them
1329 * disabling/enabling the device.
1331 if (pci_enable_device(pdev
))
1334 pci_set_master(pdev
);
1336 disable_rpm_wakeref_asserts(&dev_priv
->runtime_pm
);
1338 ret
= vlv_resume_prepare(dev_priv
, false);
1340 drm_err(&dev_priv
->drm
,
1341 "Resume prepare failed: %d, continuing anyway\n", ret
);
1343 for_each_gt(gt
, dev_priv
, i
)
1344 intel_gt_resume_early(gt
);
1346 intel_display_power_resume_early(dev_priv
);
1348 intel_power_domains_resume(dev_priv
);
1350 enable_rpm_wakeref_asserts(&dev_priv
->runtime_pm
);
1355 int i915_driver_resume_switcheroo(struct drm_i915_private
*i915
)
1359 if (i915
->drm
.switch_power_state
== DRM_SWITCH_POWER_OFF
)
1362 ret
= i915_drm_resume_early(&i915
->drm
);
1366 return i915_drm_resume(&i915
->drm
);
1369 static int i915_pm_prepare(struct device
*kdev
)
1371 struct drm_i915_private
*i915
= kdev_to_i915(kdev
);
1374 dev_err(kdev
, "DRM not initialized, aborting suspend.\n");
1378 if (i915
->drm
.switch_power_state
== DRM_SWITCH_POWER_OFF
)
1381 return i915_drm_prepare(&i915
->drm
);
1384 static int i915_pm_suspend(struct device
*kdev
)
1386 struct drm_i915_private
*i915
= kdev_to_i915(kdev
);
1389 dev_err(kdev
, "DRM not initialized, aborting suspend.\n");
1393 if (i915
->drm
.switch_power_state
== DRM_SWITCH_POWER_OFF
)
1396 return i915_drm_suspend(&i915
->drm
);
1399 static int i915_pm_suspend_late(struct device
*kdev
)
1401 struct drm_i915_private
*i915
= kdev_to_i915(kdev
);
1404 * We have a suspend ordering issue with the snd-hda driver also
1405 * requiring our device to be power up. Due to the lack of a
1406 * parent/child relationship we currently solve this with an late
1409 * FIXME: This should be solved with a special hdmi sink device or
1410 * similar so that power domains can be employed.
1412 if (i915
->drm
.switch_power_state
== DRM_SWITCH_POWER_OFF
)
1415 return i915_drm_suspend_late(&i915
->drm
, false);
1418 static int i915_pm_poweroff_late(struct device
*kdev
)
1420 struct drm_i915_private
*i915
= kdev_to_i915(kdev
);
1422 if (i915
->drm
.switch_power_state
== DRM_SWITCH_POWER_OFF
)
1425 return i915_drm_suspend_late(&i915
->drm
, true);
1428 static int i915_pm_resume_early(struct device
*kdev
)
1430 struct drm_i915_private
*i915
= kdev_to_i915(kdev
);
1432 if (i915
->drm
.switch_power_state
== DRM_SWITCH_POWER_OFF
)
1435 return i915_drm_resume_early(&i915
->drm
);
1438 static int i915_pm_resume(struct device
*kdev
)
1440 struct drm_i915_private
*i915
= kdev_to_i915(kdev
);
1442 if (i915
->drm
.switch_power_state
== DRM_SWITCH_POWER_OFF
)
1445 return i915_drm_resume(&i915
->drm
);
1448 static void i915_pm_complete(struct device
*kdev
)
1450 struct drm_i915_private
*i915
= kdev_to_i915(kdev
);
1452 if (i915
->drm
.switch_power_state
== DRM_SWITCH_POWER_OFF
)
1455 i915_drm_complete(&i915
->drm
);
1458 /* freeze: before creating the hibernation_image */
1459 static int i915_pm_freeze(struct device
*kdev
)
1461 struct drm_i915_private
*i915
= kdev_to_i915(kdev
);
1464 if (i915
->drm
.switch_power_state
!= DRM_SWITCH_POWER_OFF
) {
1465 ret
= i915_drm_suspend(&i915
->drm
);
1470 ret
= i915_gem_freeze(i915
);
1477 static int i915_pm_freeze_late(struct device
*kdev
)
1479 struct drm_i915_private
*i915
= kdev_to_i915(kdev
);
1482 if (i915
->drm
.switch_power_state
!= DRM_SWITCH_POWER_OFF
) {
1483 ret
= i915_drm_suspend_late(&i915
->drm
, true);
1488 ret
= i915_gem_freeze_late(i915
);
1495 /* thaw: called after creating the hibernation image, but before turning off. */
1496 static int i915_pm_thaw_early(struct device
*kdev
)
1498 return i915_pm_resume_early(kdev
);
1501 static int i915_pm_thaw(struct device
*kdev
)
1503 return i915_pm_resume(kdev
);
1506 /* restore: called after loading the hibernation image. */
1507 static int i915_pm_restore_early(struct device
*kdev
)
1509 return i915_pm_resume_early(kdev
);
1512 static int i915_pm_restore(struct device
*kdev
)
1514 return i915_pm_resume(kdev
);
1517 static int intel_runtime_suspend(struct device
*kdev
)
1519 struct drm_i915_private
*dev_priv
= kdev_to_i915(kdev
);
1520 struct intel_runtime_pm
*rpm
= &dev_priv
->runtime_pm
;
1521 struct pci_dev
*pdev
= to_pci_dev(dev_priv
->drm
.dev
);
1522 struct pci_dev
*root_pdev
;
1523 struct intel_gt
*gt
;
1526 if (drm_WARN_ON_ONCE(&dev_priv
->drm
, !HAS_RUNTIME_PM(dev_priv
)))
1529 drm_dbg(&dev_priv
->drm
, "Suspending device\n");
1531 disable_rpm_wakeref_asserts(rpm
);
1534 * We are safe here against re-faults, since the fault handler takes
1537 i915_gem_runtime_suspend(dev_priv
);
1539 intel_pxp_runtime_suspend(dev_priv
->pxp
);
1541 for_each_gt(gt
, dev_priv
, i
)
1542 intel_gt_runtime_suspend(gt
);
1544 intel_runtime_pm_disable_interrupts(dev_priv
);
1546 for_each_gt(gt
, dev_priv
, i
)
1547 intel_uncore_suspend(gt
->uncore
);
1549 intel_display_power_suspend(dev_priv
);
1551 ret
= vlv_suspend_complete(dev_priv
);
1553 drm_err(&dev_priv
->drm
,
1554 "Runtime suspend failed, disabling it (%d)\n", ret
);
1555 intel_uncore_runtime_resume(&dev_priv
->uncore
);
1557 intel_runtime_pm_enable_interrupts(dev_priv
);
1559 for_each_gt(gt
, dev_priv
, i
)
1560 intel_gt_runtime_resume(gt
);
1562 enable_rpm_wakeref_asserts(rpm
);
1567 enable_rpm_wakeref_asserts(rpm
);
1568 intel_runtime_pm_driver_release(rpm
);
1570 if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv
->uncore
))
1571 drm_err(&dev_priv
->drm
,
1572 "Unclaimed access detected prior to suspending\n");
1575 * FIXME: Temporary hammer to avoid freezing the machine on our DGFX
1576 * This should be totally removed when we handle the pci states properly
1579 root_pdev
= pcie_find_root_port(pdev
);
1581 pci_d3cold_disable(root_pdev
);
1584 * FIXME: We really should find a document that references the arguments
1587 if (IS_BROADWELL(dev_priv
)) {
1589 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
1590 * being detected, and the call we do at intel_runtime_resume()
1591 * won't be able to restore them. Since PCI_D3hot matches the
1592 * actual specification and appears to be working, use it.
1594 intel_opregion_notify_adapter(dev_priv
, PCI_D3hot
);
1597 * current versions of firmware which depend on this opregion
1598 * notification have repurposed the D1 definition to mean
1599 * "runtime suspended" vs. what you would normally expect (D3)
1600 * to distinguish it from notifications that might be sent via
1603 intel_opregion_notify_adapter(dev_priv
, PCI_D1
);
1606 assert_forcewakes_inactive(&dev_priv
->uncore
);
1608 if (!IS_VALLEYVIEW(dev_priv
) && !IS_CHERRYVIEW(dev_priv
))
1609 intel_hpd_poll_enable(dev_priv
);
1611 drm_dbg(&dev_priv
->drm
, "Device suspended\n");
1615 static int intel_runtime_resume(struct device
*kdev
)
1617 struct drm_i915_private
*dev_priv
= kdev_to_i915(kdev
);
1618 struct intel_runtime_pm
*rpm
= &dev_priv
->runtime_pm
;
1619 struct pci_dev
*pdev
= to_pci_dev(dev_priv
->drm
.dev
);
1620 struct pci_dev
*root_pdev
;
1621 struct intel_gt
*gt
;
1624 if (drm_WARN_ON_ONCE(&dev_priv
->drm
, !HAS_RUNTIME_PM(dev_priv
)))
1627 drm_dbg(&dev_priv
->drm
, "Resuming device\n");
1629 drm_WARN_ON_ONCE(&dev_priv
->drm
, atomic_read(&rpm
->wakeref_count
));
1630 disable_rpm_wakeref_asserts(rpm
);
1632 intel_opregion_notify_adapter(dev_priv
, PCI_D0
);
1634 root_pdev
= pcie_find_root_port(pdev
);
1636 pci_d3cold_enable(root_pdev
);
1638 if (intel_uncore_unclaimed_mmio(&dev_priv
->uncore
))
1639 drm_dbg(&dev_priv
->drm
,
1640 "Unclaimed access during suspend, bios?\n");
1642 intel_display_power_resume(dev_priv
);
1644 ret
= vlv_resume_prepare(dev_priv
, true);
1646 for_each_gt(gt
, dev_priv
, i
)
1647 intel_uncore_runtime_resume(gt
->uncore
);
1649 intel_runtime_pm_enable_interrupts(dev_priv
);
1652 * No point of rolling back things in case of an error, as the best
1653 * we can do is to hope that things will still work (and disable RPM).
1655 for_each_gt(gt
, dev_priv
, i
)
1656 intel_gt_runtime_resume(gt
);
1658 intel_pxp_runtime_resume(dev_priv
->pxp
);
1661 * On VLV/CHV display interrupts are part of the display
1662 * power well, so hpd is reinitialized from there. For
1663 * everyone else do it here.
1665 if (!IS_VALLEYVIEW(dev_priv
) && !IS_CHERRYVIEW(dev_priv
)) {
1666 intel_hpd_init(dev_priv
);
1667 intel_hpd_poll_disable(dev_priv
);
1670 skl_watermark_ipc_update(dev_priv
);
1672 enable_rpm_wakeref_asserts(rpm
);
1675 drm_err(&dev_priv
->drm
,
1676 "Runtime resume failed, disabling it (%d)\n", ret
);
1678 drm_dbg(&dev_priv
->drm
, "Device resumed\n");
1683 const struct dev_pm_ops i915_pm_ops
= {
1685 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
1688 .prepare
= i915_pm_prepare
,
1689 .suspend
= i915_pm_suspend
,
1690 .suspend_late
= i915_pm_suspend_late
,
1691 .resume_early
= i915_pm_resume_early
,
1692 .resume
= i915_pm_resume
,
1693 .complete
= i915_pm_complete
,
1697 * @freeze, @freeze_late : called (1) before creating the
1698 * hibernation image [PMSG_FREEZE] and
1699 * (2) after rebooting, before restoring
1700 * the image [PMSG_QUIESCE]
1701 * @thaw, @thaw_early : called (1) after creating the hibernation
1702 * image, before writing it [PMSG_THAW]
1703 * and (2) after failing to create or
1704 * restore the image [PMSG_RECOVER]
1705 * @poweroff, @poweroff_late: called after writing the hibernation
1706 * image, before rebooting [PMSG_HIBERNATE]
1707 * @restore, @restore_early : called after rebooting and restoring the
1708 * hibernation image [PMSG_RESTORE]
1710 .freeze
= i915_pm_freeze
,
1711 .freeze_late
= i915_pm_freeze_late
,
1712 .thaw_early
= i915_pm_thaw_early
,
1713 .thaw
= i915_pm_thaw
,
1714 .poweroff
= i915_pm_suspend
,
1715 .poweroff_late
= i915_pm_poweroff_late
,
1716 .restore_early
= i915_pm_restore_early
,
1717 .restore
= i915_pm_restore
,
1719 /* S0ix (via runtime suspend) event handlers */
1720 .runtime_suspend
= intel_runtime_suspend
,
1721 .runtime_resume
= intel_runtime_resume
,
1724 static const struct file_operations i915_driver_fops
= {
1725 .owner
= THIS_MODULE
,
1727 .release
= drm_release_noglobal
,
1728 .unlocked_ioctl
= drm_ioctl
,
1729 .mmap
= i915_gem_mmap
,
1732 .compat_ioctl
= i915_ioc32_compat_ioctl
,
1733 .llseek
= noop_llseek
,
1734 #ifdef CONFIG_PROC_FS
1735 .show_fdinfo
= drm_show_fdinfo
,
1740 i915_gem_reject_pin_ioctl(struct drm_device
*dev
, void *data
,
1741 struct drm_file
*file
)
1746 static const struct drm_ioctl_desc i915_ioctls
[] = {
1747 DRM_IOCTL_DEF_DRV(I915_INIT
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
1748 DRM_IOCTL_DEF_DRV(I915_FLUSH
, drm_noop
, DRM_AUTH
),
1749 DRM_IOCTL_DEF_DRV(I915_FLIP
, drm_noop
, DRM_AUTH
),
1750 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER
, drm_noop
, DRM_AUTH
),
1751 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT
, drm_noop
, DRM_AUTH
),
1752 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT
, drm_noop
, DRM_AUTH
),
1753 DRM_IOCTL_DEF_DRV(I915_GETPARAM
, i915_getparam_ioctl
, DRM_RENDER_ALLOW
),
1754 DRM_IOCTL_DEF_DRV(I915_SETPARAM
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
1755 DRM_IOCTL_DEF_DRV(I915_ALLOC
, drm_noop
, DRM_AUTH
),
1756 DRM_IOCTL_DEF_DRV(I915_FREE
, drm_noop
, DRM_AUTH
),
1757 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
1758 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER
, drm_noop
, DRM_AUTH
),
1759 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
1760 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
1761 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE
, drm_noop
, DRM_AUTH
),
1762 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP
, drm_noop
, DRM_AUTH
),
1763 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
1764 DRM_IOCTL_DEF_DRV(I915_GEM_INIT
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
1765 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER
, drm_invalid_op
, DRM_AUTH
),
1766 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR
, i915_gem_execbuffer2_ioctl
, DRM_RENDER_ALLOW
),
1767 DRM_IOCTL_DEF_DRV(I915_GEM_PIN
, i915_gem_reject_pin_ioctl
, DRM_AUTH
|DRM_ROOT_ONLY
),
1768 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN
, i915_gem_reject_pin_ioctl
, DRM_AUTH
|DRM_ROOT_ONLY
),
1769 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY
, i915_gem_busy_ioctl
, DRM_RENDER_ALLOW
),
1770 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING
, i915_gem_set_caching_ioctl
, DRM_RENDER_ALLOW
),
1771 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING
, i915_gem_get_caching_ioctl
, DRM_RENDER_ALLOW
),
1772 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE
, i915_gem_throttle_ioctl
, DRM_RENDER_ALLOW
),
1773 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
1774 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
1775 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE
, i915_gem_create_ioctl
, DRM_RENDER_ALLOW
),
1776 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE_EXT
, i915_gem_create_ext_ioctl
, DRM_RENDER_ALLOW
),
1777 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD
, i915_gem_pread_ioctl
, DRM_RENDER_ALLOW
),
1778 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE
, i915_gem_pwrite_ioctl
, DRM_RENDER_ALLOW
),
1779 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP
, i915_gem_mmap_ioctl
, DRM_RENDER_ALLOW
),
1780 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_OFFSET
, i915_gem_mmap_offset_ioctl
, DRM_RENDER_ALLOW
),
1781 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN
, i915_gem_set_domain_ioctl
, DRM_RENDER_ALLOW
),
1782 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH
, i915_gem_sw_finish_ioctl
, DRM_RENDER_ALLOW
),
1783 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING
, i915_gem_set_tiling_ioctl
, DRM_RENDER_ALLOW
),
1784 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING
, i915_gem_get_tiling_ioctl
, DRM_RENDER_ALLOW
),
1785 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE
, i915_gem_get_aperture_ioctl
, DRM_RENDER_ALLOW
),
1786 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID
, intel_get_pipe_from_crtc_id_ioctl
, 0),
1787 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE
, i915_gem_madvise_ioctl
, DRM_RENDER_ALLOW
),
1788 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE
, intel_overlay_put_image_ioctl
, DRM_MASTER
),
1789 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS
, intel_overlay_attrs_ioctl
, DRM_MASTER
),
1790 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY
, intel_sprite_set_colorkey_ioctl
, DRM_MASTER
),
1791 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY
, drm_noop
, DRM_MASTER
),
1792 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT
, i915_gem_wait_ioctl
, DRM_RENDER_ALLOW
),
1793 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE_EXT
, i915_gem_context_create_ioctl
, DRM_RENDER_ALLOW
),
1794 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY
, i915_gem_context_destroy_ioctl
, DRM_RENDER_ALLOW
),
1795 DRM_IOCTL_DEF_DRV(I915_REG_READ
, i915_reg_read_ioctl
, DRM_RENDER_ALLOW
),
1796 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS
, i915_gem_context_reset_stats_ioctl
, DRM_RENDER_ALLOW
),
1797 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR
, i915_gem_userptr_ioctl
, DRM_RENDER_ALLOW
),
1798 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM
, i915_gem_context_getparam_ioctl
, DRM_RENDER_ALLOW
),
1799 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM
, i915_gem_context_setparam_ioctl
, DRM_RENDER_ALLOW
),
1800 DRM_IOCTL_DEF_DRV(I915_PERF_OPEN
, i915_perf_open_ioctl
, DRM_RENDER_ALLOW
),
1801 DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG
, i915_perf_add_config_ioctl
, DRM_RENDER_ALLOW
),
1802 DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG
, i915_perf_remove_config_ioctl
, DRM_RENDER_ALLOW
),
1803 DRM_IOCTL_DEF_DRV(I915_QUERY
, i915_query_ioctl
, DRM_RENDER_ALLOW
),
1804 DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE
, i915_gem_vm_create_ioctl
, DRM_RENDER_ALLOW
),
1805 DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY
, i915_gem_vm_destroy_ioctl
, DRM_RENDER_ALLOW
),
1809 * Interface history:
1812 * 1.2: Add Power Management
1813 * 1.3: Add vblank support
1814 * 1.4: Fix cmdbuffer path, add heap destroy
1815 * 1.5: Add vblank pipe configuration
1816 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
1817 * - Support vertical blank on secondary display pipe
1819 #define DRIVER_MAJOR 1
1820 #define DRIVER_MINOR 6
1821 #define DRIVER_PATCHLEVEL 0
1823 static const struct drm_driver i915_drm_driver
= {
1824 /* Don't use MTRRs here; the Xserver or userspace app should
1825 * deal with them for Intel hardware.
1829 DRIVER_RENDER
| DRIVER_MODESET
| DRIVER_ATOMIC
| DRIVER_SYNCOBJ
|
1830 DRIVER_SYNCOBJ_TIMELINE
,
1831 .release
= i915_driver_release
,
1832 .open
= i915_driver_open
,
1833 .lastclose
= i915_driver_lastclose
,
1834 .postclose
= i915_driver_postclose
,
1835 .show_fdinfo
= PTR_IF(IS_ENABLED(CONFIG_PROC_FS
), i915_drm_client_fdinfo
),
1837 .gem_prime_import
= i915_gem_prime_import
,
1839 .dumb_create
= i915_gem_dumb_create
,
1840 .dumb_map_offset
= i915_gem_dumb_mmap_offset
,
1842 .ioctls
= i915_ioctls
,
1843 .num_ioctls
= ARRAY_SIZE(i915_ioctls
),
1844 .fops
= &i915_driver_fops
,
1845 .name
= DRIVER_NAME
,
1846 .desc
= DRIVER_DESC
,
1847 .date
= DRIVER_DATE
,
1848 .major
= DRIVER_MAJOR
,
1849 .minor
= DRIVER_MINOR
,
1850 .patchlevel
= DRIVER_PATCHLEVEL
,