1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #include <linux/acpi.h>
31 #include <linux/device.h>
32 #include <linux/oom.h>
33 #include <linux/module.h>
34 #include <linux/pci.h>
36 #include <linux/pm_runtime.h>
37 #include <linux/pnp.h>
38 #include <linux/slab.h>
39 #include <linux/vgaarb.h>
40 #include <linux/vga_switcheroo.h>
42 #include <acpi/video.h>
45 #include <drm/drm_crtc_helper.h>
46 #include <drm/i915_drm.h>
49 #include "i915_trace.h"
50 #include "i915_vgpu.h"
51 #include "intel_drv.h"
53 static drm_driver_no_const driver
;
55 static unsigned int i915_load_fail_count
;
57 bool __i915_inject_load_failure(const char *func
, int line
)
59 if (i915_load_fail_count
>= i915
.inject_load_failure
)
62 if (++i915_load_fail_count
== i915
.inject_load_failure
) {
63 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
64 i915
.inject_load_failure
, func
, line
);
71 #define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
72 #define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
73 "providing the dmesg log by booting with drm.debug=0xf"
76 __i915_printk(struct drm_i915_private
*dev_priv
, const char *level
,
79 static bool shown_bug_once
;
80 struct device
*kdev
= dev_priv
->drm
.dev
;
81 bool is_error
= level
[1] <= KERN_ERR
[1];
82 bool is_debug
= level
[1] == KERN_DEBUG
[1];
86 if (is_debug
&& !(drm_debug
& DRM_UT_DRIVER
))
94 dev_printk(level
, kdev
, "[" DRM_NAME
":%ps] %pV",
95 __builtin_return_address(0), &vaf
);
97 if (is_error
&& !shown_bug_once
) {
98 dev_notice(kdev
, "%s", FDO_BUG_MSG
);
99 shown_bug_once
= true;
105 static bool i915_error_injected(struct drm_i915_private
*dev_priv
)
107 return i915
.inject_load_failure
&&
108 i915_load_fail_count
== i915
.inject_load_failure
;
111 #define i915_load_error(dev_priv, fmt, ...) \
112 __i915_printk(dev_priv, \
113 i915_error_injected(dev_priv) ? KERN_DEBUG : KERN_ERR, \
117 static enum intel_pch
intel_virt_detect_pch(struct drm_device
*dev
)
119 enum intel_pch ret
= PCH_NOP
;
122 * In a virtualized passthrough environment we can be in a
123 * setup where the ISA bridge is not able to be passed through.
124 * In this case, a south bridge can be emulated and we have to
125 * make an educated guess as to which PCH is really there.
130 DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
131 } else if (IS_GEN6(dev
) || IS_IVYBRIDGE(dev
)) {
133 DRM_DEBUG_KMS("Assuming CouarPoint PCH\n");
134 } else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
136 DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
137 } else if (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
)) {
139 DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
145 static void intel_detect_pch(struct drm_device
*dev
)
147 struct drm_i915_private
*dev_priv
= to_i915(dev
);
148 struct pci_dev
*pch
= NULL
;
150 /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
151 * (which really amounts to a PCH but no South Display).
153 if (INTEL_INFO(dev
)->num_pipes
== 0) {
154 dev_priv
->pch_type
= PCH_NOP
;
159 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
160 * make graphics device passthrough work easy for VMM, that only
161 * need to expose ISA bridge to let driver know the real hardware
162 * underneath. This is a requirement from virtualization team.
164 * In some virtualized environments (e.g. XEN), there is irrelevant
165 * ISA bridge in the system. To work reliably, we should scan trhough
166 * all the ISA bridge devices and check for the first match, instead
167 * of only checking the first one.
169 while ((pch
= pci_get_class(PCI_CLASS_BRIDGE_ISA
<< 8, pch
))) {
170 if (pch
->vendor
== PCI_VENDOR_ID_INTEL
) {
171 unsigned short id
= pch
->device
& INTEL_PCH_DEVICE_ID_MASK
;
172 dev_priv
->pch_id
= id
;
174 if (id
== INTEL_PCH_IBX_DEVICE_ID_TYPE
) {
175 dev_priv
->pch_type
= PCH_IBX
;
176 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
177 WARN_ON(!IS_GEN5(dev
));
178 } else if (id
== INTEL_PCH_CPT_DEVICE_ID_TYPE
) {
179 dev_priv
->pch_type
= PCH_CPT
;
180 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
181 WARN_ON(!(IS_GEN6(dev
) || IS_IVYBRIDGE(dev
)));
182 } else if (id
== INTEL_PCH_PPT_DEVICE_ID_TYPE
) {
183 /* PantherPoint is CPT compatible */
184 dev_priv
->pch_type
= PCH_CPT
;
185 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
186 WARN_ON(!(IS_GEN6(dev
) || IS_IVYBRIDGE(dev
)));
187 } else if (id
== INTEL_PCH_LPT_DEVICE_ID_TYPE
) {
188 dev_priv
->pch_type
= PCH_LPT
;
189 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
190 WARN_ON(!IS_HASWELL(dev
) && !IS_BROADWELL(dev
));
191 WARN_ON(IS_HSW_ULT(dev
) || IS_BDW_ULT(dev
));
192 } else if (id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
193 dev_priv
->pch_type
= PCH_LPT
;
194 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
195 WARN_ON(!IS_HASWELL(dev
) && !IS_BROADWELL(dev
));
196 WARN_ON(!IS_HSW_ULT(dev
) && !IS_BDW_ULT(dev
));
197 } else if (id
== INTEL_PCH_SPT_DEVICE_ID_TYPE
) {
198 dev_priv
->pch_type
= PCH_SPT
;
199 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
200 WARN_ON(!IS_SKYLAKE(dev
) &&
202 } else if (id
== INTEL_PCH_SPT_LP_DEVICE_ID_TYPE
) {
203 dev_priv
->pch_type
= PCH_SPT
;
204 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
205 WARN_ON(!IS_SKYLAKE(dev
) &&
207 } else if (id
== INTEL_PCH_KBP_DEVICE_ID_TYPE
) {
208 dev_priv
->pch_type
= PCH_KBP
;
209 DRM_DEBUG_KMS("Found KabyPoint PCH\n");
210 WARN_ON(!IS_KABYLAKE(dev
));
211 } else if ((id
== INTEL_PCH_P2X_DEVICE_ID_TYPE
) ||
212 (id
== INTEL_PCH_P3X_DEVICE_ID_TYPE
) ||
213 ((id
== INTEL_PCH_QEMU_DEVICE_ID_TYPE
) &&
214 pch
->subsystem_vendor
==
215 PCI_SUBVENDOR_ID_REDHAT_QUMRANET
&&
216 pch
->subsystem_device
==
217 PCI_SUBDEVICE_ID_QEMU
)) {
218 dev_priv
->pch_type
= intel_virt_detect_pch(dev
);
226 DRM_DEBUG_KMS("No PCH found.\n");
231 static int i915_getparam(struct drm_device
*dev
, void *data
,
232 struct drm_file
*file_priv
)
234 struct drm_i915_private
*dev_priv
= to_i915(dev
);
235 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
236 drm_i915_getparam_t
*param
= data
;
239 switch (param
->param
) {
240 case I915_PARAM_IRQ_ACTIVE
:
241 case I915_PARAM_ALLOW_BATCHBUFFER
:
242 case I915_PARAM_LAST_DISPATCH
:
243 case I915_PARAM_HAS_EXEC_CONSTANTS
:
244 /* Reject all old ums/dri params. */
246 case I915_PARAM_CHIPSET_ID
:
247 value
= pdev
->device
;
249 case I915_PARAM_REVISION
:
250 value
= pdev
->revision
;
252 case I915_PARAM_NUM_FENCES_AVAIL
:
253 value
= dev_priv
->num_fence_regs
;
255 case I915_PARAM_HAS_OVERLAY
:
256 value
= dev_priv
->overlay
? 1 : 0;
258 case I915_PARAM_HAS_BSD
:
259 value
= intel_engine_initialized(&dev_priv
->engine
[VCS
]);
261 case I915_PARAM_HAS_BLT
:
262 value
= intel_engine_initialized(&dev_priv
->engine
[BCS
]);
264 case I915_PARAM_HAS_VEBOX
:
265 value
= intel_engine_initialized(&dev_priv
->engine
[VECS
]);
267 case I915_PARAM_HAS_BSD2
:
268 value
= intel_engine_initialized(&dev_priv
->engine
[VCS2
]);
270 case I915_PARAM_HAS_LLC
:
271 value
= HAS_LLC(dev_priv
);
273 case I915_PARAM_HAS_WT
:
274 value
= HAS_WT(dev_priv
);
276 case I915_PARAM_HAS_ALIASING_PPGTT
:
277 value
= USES_PPGTT(dev_priv
);
279 case I915_PARAM_HAS_SEMAPHORES
:
280 value
= i915
.semaphores
;
282 case I915_PARAM_HAS_SECURE_BATCHES
:
283 value
= capable(CAP_SYS_ADMIN
);
285 case I915_PARAM_CMD_PARSER_VERSION
:
286 value
= i915_cmd_parser_get_version(dev_priv
);
288 case I915_PARAM_SUBSLICE_TOTAL
:
289 value
= sseu_subslice_total(&INTEL_INFO(dev_priv
)->sseu
);
293 case I915_PARAM_EU_TOTAL
:
294 value
= INTEL_INFO(dev_priv
)->sseu
.eu_total
;
298 case I915_PARAM_HAS_GPU_RESET
:
299 value
= i915
.enable_hangcheck
&& intel_has_gpu_reset(dev_priv
);
301 case I915_PARAM_HAS_RESOURCE_STREAMER
:
302 value
= HAS_RESOURCE_STREAMER(dev_priv
);
304 case I915_PARAM_HAS_POOLED_EU
:
305 value
= HAS_POOLED_EU(dev_priv
);
307 case I915_PARAM_MIN_EU_IN_POOL
:
308 value
= INTEL_INFO(dev_priv
)->sseu
.min_eu_in_pool
;
310 case I915_PARAM_MMAP_GTT_VERSION
:
311 /* Though we've started our numbering from 1, and so class all
312 * earlier versions as 0, in effect their value is undefined as
313 * the ioctl will report EINVAL for the unknown param!
315 value
= i915_gem_mmap_gtt_version();
317 case I915_PARAM_MMAP_VERSION
:
318 /* Remember to bump this if the version changes! */
319 case I915_PARAM_HAS_GEM
:
320 case I915_PARAM_HAS_PAGEFLIPPING
:
321 case I915_PARAM_HAS_EXECBUF2
: /* depends on GEM */
322 case I915_PARAM_HAS_RELAXED_FENCING
:
323 case I915_PARAM_HAS_COHERENT_RINGS
:
324 case I915_PARAM_HAS_RELAXED_DELTA
:
325 case I915_PARAM_HAS_GEN7_SOL_RESET
:
326 case I915_PARAM_HAS_WAIT_TIMEOUT
:
327 case I915_PARAM_HAS_PRIME_VMAP_FLUSH
:
328 case I915_PARAM_HAS_PINNED_BATCHES
:
329 case I915_PARAM_HAS_EXEC_NO_RELOC
:
330 case I915_PARAM_HAS_EXEC_HANDLE_LUT
:
331 case I915_PARAM_HAS_COHERENT_PHYS_GTT
:
332 case I915_PARAM_HAS_EXEC_SOFTPIN
:
333 /* For the time being all of these are always true;
334 * if some supported hardware does not have one of these
335 * features this value needs to be provided from
336 * INTEL_INFO(), a feature macro, or similar.
341 DRM_DEBUG("Unknown parameter %d\n", param
->param
);
345 if (put_user(value
, param
->value
))
351 static int i915_get_bridge_dev(struct drm_device
*dev
)
353 struct drm_i915_private
*dev_priv
= to_i915(dev
);
355 dev_priv
->bridge_dev
= pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
356 if (!dev_priv
->bridge_dev
) {
357 DRM_ERROR("bridge device not found\n");
363 /* Allocate space for the MCH regs if needed, return nonzero on error */
365 intel_alloc_mchbar_resource(struct drm_device
*dev
)
367 struct drm_i915_private
*dev_priv
= to_i915(dev
);
368 int reg
= INTEL_INFO(dev
)->gen
>= 4 ? MCHBAR_I965
: MCHBAR_I915
;
369 u32 temp_lo
, temp_hi
= 0;
373 if (INTEL_INFO(dev
)->gen
>= 4)
374 pci_read_config_dword(dev_priv
->bridge_dev
, reg
+ 4, &temp_hi
);
375 pci_read_config_dword(dev_priv
->bridge_dev
, reg
, &temp_lo
);
376 mchbar_addr
= ((u64
)temp_hi
<< 32) | temp_lo
;
378 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
381 pnp_range_reserved(mchbar_addr
, mchbar_addr
+ MCHBAR_SIZE
))
385 /* Get some space for it */
386 dev_priv
->mch_res
.name
= "i915 MCHBAR";
387 dev_priv
->mch_res
.flags
= IORESOURCE_MEM
;
388 ret
= pci_bus_alloc_resource(dev_priv
->bridge_dev
->bus
,
390 MCHBAR_SIZE
, MCHBAR_SIZE
,
392 0, pcibios_align_resource
,
393 dev_priv
->bridge_dev
);
395 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret
);
396 dev_priv
->mch_res
.start
= 0;
400 if (INTEL_INFO(dev
)->gen
>= 4)
401 pci_write_config_dword(dev_priv
->bridge_dev
, reg
+ 4,
402 upper_32_bits(dev_priv
->mch_res
.start
));
404 pci_write_config_dword(dev_priv
->bridge_dev
, reg
,
405 lower_32_bits(dev_priv
->mch_res
.start
));
409 /* Setup MCHBAR if possible, return true if we should disable it again */
411 intel_setup_mchbar(struct drm_device
*dev
)
413 struct drm_i915_private
*dev_priv
= to_i915(dev
);
414 int mchbar_reg
= INTEL_INFO(dev
)->gen
>= 4 ? MCHBAR_I965
: MCHBAR_I915
;
418 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
421 dev_priv
->mchbar_need_disable
= false;
423 if (IS_I915G(dev
) || IS_I915GM(dev
)) {
424 pci_read_config_dword(dev_priv
->bridge_dev
, DEVEN
, &temp
);
425 enabled
= !!(temp
& DEVEN_MCHBAR_EN
);
427 pci_read_config_dword(dev_priv
->bridge_dev
, mchbar_reg
, &temp
);
431 /* If it's already enabled, don't have to do anything */
435 if (intel_alloc_mchbar_resource(dev
))
438 dev_priv
->mchbar_need_disable
= true;
440 /* Space is allocated or reserved, so enable it. */
441 if (IS_I915G(dev
) || IS_I915GM(dev
)) {
442 pci_write_config_dword(dev_priv
->bridge_dev
, DEVEN
,
443 temp
| DEVEN_MCHBAR_EN
);
445 pci_read_config_dword(dev_priv
->bridge_dev
, mchbar_reg
, &temp
);
446 pci_write_config_dword(dev_priv
->bridge_dev
, mchbar_reg
, temp
| 1);
451 intel_teardown_mchbar(struct drm_device
*dev
)
453 struct drm_i915_private
*dev_priv
= to_i915(dev
);
454 int mchbar_reg
= INTEL_INFO(dev
)->gen
>= 4 ? MCHBAR_I965
: MCHBAR_I915
;
456 if (dev_priv
->mchbar_need_disable
) {
457 if (IS_I915G(dev
) || IS_I915GM(dev
)) {
460 pci_read_config_dword(dev_priv
->bridge_dev
, DEVEN
,
462 deven_val
&= ~DEVEN_MCHBAR_EN
;
463 pci_write_config_dword(dev_priv
->bridge_dev
, DEVEN
,
468 pci_read_config_dword(dev_priv
->bridge_dev
, mchbar_reg
,
471 pci_write_config_dword(dev_priv
->bridge_dev
, mchbar_reg
,
476 if (dev_priv
->mch_res
.start
)
477 release_resource(&dev_priv
->mch_res
);
480 /* true = enable decode, false = disable decoder */
481 static unsigned int i915_vga_set_decode(void *cookie
, bool state
)
483 struct drm_device
*dev
= cookie
;
485 intel_modeset_vga_set_state(dev
, state
);
487 return VGA_RSRC_LEGACY_IO
| VGA_RSRC_LEGACY_MEM
|
488 VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
490 return VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
493 static void i915_switcheroo_set_state(struct pci_dev
*pdev
, enum vga_switcheroo_state state
)
495 struct drm_device
*dev
= pci_get_drvdata(pdev
);
496 pm_message_t pmm
= { .event
= PM_EVENT_SUSPEND
};
498 if (state
== VGA_SWITCHEROO_ON
) {
499 pr_info("switched on\n");
500 dev
->switch_power_state
= DRM_SWITCH_POWER_CHANGING
;
501 /* i915 resume handler doesn't set to D0 */
502 pci_set_power_state(pdev
, PCI_D0
);
503 i915_resume_switcheroo(dev
);
504 dev
->switch_power_state
= DRM_SWITCH_POWER_ON
;
506 pr_info("switched off\n");
507 dev
->switch_power_state
= DRM_SWITCH_POWER_CHANGING
;
508 i915_suspend_switcheroo(dev
, pmm
);
509 dev
->switch_power_state
= DRM_SWITCH_POWER_OFF
;
513 static bool i915_switcheroo_can_switch(struct pci_dev
*pdev
)
515 struct drm_device
*dev
= pci_get_drvdata(pdev
);
518 * FIXME: open_count is protected by drm_global_mutex but that would lead to
519 * locking inversion with the driver load path. And the access here is
520 * completely racy anyway. So don't bother with locking for now.
522 return local_read(&dev
->open_count
) == 0;
525 static const struct vga_switcheroo_client_ops i915_switcheroo_ops
= {
526 .set_gpu_state
= i915_switcheroo_set_state
,
528 .can_switch
= i915_switcheroo_can_switch
,
531 static void i915_gem_fini(struct drm_device
*dev
)
533 struct drm_i915_private
*dev_priv
= to_i915(dev
);
536 * Neither the BIOS, ourselves or any other kernel
537 * expects the system to be in execlists mode on startup,
538 * so we need to reset the GPU back to legacy mode. And the only
539 * known way to disable logical contexts is through a GPU reset.
541 * So in order to leave the system in a known default configuration,
542 * always reset the GPU upon unload. Afterwards we then clean up the
543 * GEM state tracking, flushing off the requests and leaving the
544 * system in a known idle state.
546 * Note that is of the upmost importance that the GPU is idle and
547 * all stray writes are flushed *before* we dismantle the backing
548 * storage for the pinned objects.
550 * However, since we are uncertain that reseting the GPU on older
551 * machines is a good idea, we don't - just in case it leaves the
552 * machine in an unusable condition.
554 if (HAS_HW_CONTEXTS(dev
)) {
555 int reset
= intel_gpu_reset(dev_priv
, ALL_ENGINES
);
556 WARN_ON(reset
&& reset
!= -ENODEV
);
559 mutex_lock(&dev
->struct_mutex
);
560 i915_gem_cleanup_engines(dev
);
561 i915_gem_context_fini(dev
);
562 mutex_unlock(&dev
->struct_mutex
);
564 WARN_ON(!list_empty(&to_i915(dev
)->context_list
));
567 static int i915_load_modeset_init(struct drm_device
*dev
)
569 struct drm_i915_private
*dev_priv
= to_i915(dev
);
570 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
573 if (i915_inject_load_failure())
576 intel_bios_init(dev_priv
);
578 /* If we have > 1 VGA cards, then we need to arbitrate access
579 * to the common VGA resources.
581 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
582 * then we do not take part in VGA arbitration and the
583 * vga_client_register() fails with -ENODEV.
585 ret
= vga_client_register(pdev
, dev
, NULL
, i915_vga_set_decode
);
586 if (ret
&& ret
!= -ENODEV
)
589 intel_register_dsm_handler();
591 ret
= vga_switcheroo_register_client(pdev
, &i915_switcheroo_ops
, false);
593 goto cleanup_vga_client
;
595 /* must happen before intel_power_domains_init_hw() on VLV/CHV */
596 intel_update_rawclk(dev_priv
);
598 intel_power_domains_init_hw(dev_priv
, false);
600 intel_csr_ucode_init(dev_priv
);
602 ret
= intel_irq_install(dev_priv
);
606 intel_setup_gmbus(dev
);
608 /* Important: The output setup functions called by modeset_init need
609 * working irqs for e.g. gmbus and dp aux transfers. */
610 intel_modeset_init(dev
);
614 ret
= i915_gem_init(dev
);
618 intel_modeset_gem_init(dev
);
620 if (INTEL_INFO(dev
)->num_pipes
== 0)
623 ret
= intel_fbdev_init(dev
);
627 /* Only enable hotplug handling once the fbdev is fully set up. */
628 intel_hpd_init(dev_priv
);
630 drm_kms_helper_poll_init(dev
);
638 drm_irq_uninstall(dev
);
639 intel_teardown_gmbus(dev
);
641 intel_csr_ucode_fini(dev_priv
);
642 intel_power_domains_fini(dev_priv
);
643 vga_switcheroo_unregister_client(pdev
);
645 vga_client_register(pdev
, NULL
, NULL
, NULL
);
650 #if IS_ENABLED(CONFIG_FB)
651 static int i915_kick_out_firmware_fb(struct drm_i915_private
*dev_priv
)
653 struct apertures_struct
*ap
;
654 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
655 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
659 ap
= alloc_apertures(1);
663 ap
->ranges
[0].base
= ggtt
->mappable_base
;
664 ap
->ranges
[0].size
= ggtt
->mappable_end
;
667 pdev
->resource
[PCI_ROM_RESOURCE
].flags
& IORESOURCE_ROM_SHADOW
;
669 ret
= drm_fb_helper_remove_conflicting_framebuffers(ap
, "inteldrmfb", primary
);
676 static int i915_kick_out_firmware_fb(struct drm_i915_private
*dev_priv
)
682 #if !defined(CONFIG_VGA_CONSOLE)
683 static int i915_kick_out_vgacon(struct drm_i915_private
*dev_priv
)
687 #elif !defined(CONFIG_DUMMY_CONSOLE)
688 static int i915_kick_out_vgacon(struct drm_i915_private
*dev_priv
)
693 static int i915_kick_out_vgacon(struct drm_i915_private
*dev_priv
)
697 DRM_INFO("Replacing VGA console driver\n");
700 if (con_is_bound(&vga_con
))
701 ret
= do_take_over_console(&dummy_con
, 0, MAX_NR_CONSOLES
- 1, 1);
703 ret
= do_unregister_con_driver(&vga_con
);
705 /* Ignore "already unregistered". */
715 static void intel_init_dpio(struct drm_i915_private
*dev_priv
)
718 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
719 * CHV x1 PHY (DP/HDMI D)
720 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
722 if (IS_CHERRYVIEW(dev_priv
)) {
723 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO_2
;
724 DPIO_PHY_IOSF_PORT(DPIO_PHY1
) = IOSF_PORT_DPIO
;
725 } else if (IS_VALLEYVIEW(dev_priv
)) {
726 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO
;
730 static int i915_workqueues_init(struct drm_i915_private
*dev_priv
)
733 * The i915 workqueue is primarily used for batched retirement of
734 * requests (and thus managing bo) once the task has been completed
735 * by the GPU. i915_gem_retire_requests() is called directly when we
736 * need high-priority retirement, such as waiting for an explicit
739 * It is also used for periodic low-priority events, such as
740 * idle-timers and recording error state.
742 * All tasks on the workqueue are expected to acquire the dev mutex
743 * so there is no point in running more than one instance of the
744 * workqueue at any time. Use an ordered one.
746 dev_priv
->wq
= alloc_ordered_workqueue("i915", 0);
747 if (dev_priv
->wq
== NULL
)
750 dev_priv
->hotplug
.dp_wq
= alloc_ordered_workqueue("i915-dp", 0);
751 if (dev_priv
->hotplug
.dp_wq
== NULL
)
757 destroy_workqueue(dev_priv
->wq
);
759 DRM_ERROR("Failed to allocate workqueues.\n");
764 static void i915_workqueues_cleanup(struct drm_i915_private
*dev_priv
)
766 destroy_workqueue(dev_priv
->hotplug
.dp_wq
);
767 destroy_workqueue(dev_priv
->wq
);
771 * i915_driver_init_early - setup state not requiring device access
772 * @dev_priv: device private
774 * Initialize everything that is a "SW-only" state, that is state not
775 * requiring accessing the device or exposing the driver via kernel internal
776 * or userspace interfaces. Example steps belonging here: lock initialization,
777 * system memory allocation, setting up device specific attributes and
778 * function hooks not requiring accessing the device.
780 static int i915_driver_init_early(struct drm_i915_private
*dev_priv
,
781 const struct pci_device_id
*ent
)
783 const struct intel_device_info
*match_info
=
784 (struct intel_device_info
*)ent
->driver_data
;
785 struct intel_device_info
*device_info
;
788 if (i915_inject_load_failure())
791 /* Setup the write-once "constant" device info */
792 device_info
= mkwrite_device_info(dev_priv
);
793 memcpy(device_info
, match_info
, sizeof(*device_info
));
794 device_info
->device_id
= dev_priv
->drm
.pdev
->device
;
796 BUG_ON(device_info
->gen
> sizeof(device_info
->gen_mask
) * BITS_PER_BYTE
);
797 device_info
->gen_mask
= BIT(device_info
->gen
- 1);
799 spin_lock_init(&dev_priv
->irq_lock
);
800 spin_lock_init(&dev_priv
->gpu_error
.lock
);
801 mutex_init(&dev_priv
->backlight_lock
);
802 spin_lock_init(&dev_priv
->uncore
.lock
);
803 spin_lock_init(&dev_priv
->mm
.object_stat_lock
);
804 spin_lock_init(&dev_priv
->mmio_flip_lock
);
805 mutex_init(&dev_priv
->sb_lock
);
806 mutex_init(&dev_priv
->modeset_restore_lock
);
807 mutex_init(&dev_priv
->av_mutex
);
808 mutex_init(&dev_priv
->wm
.wm_mutex
);
809 mutex_init(&dev_priv
->pps_mutex
);
811 i915_memcpy_init_early(dev_priv
);
813 ret
= i915_workqueues_init(dev_priv
);
817 ret
= intel_gvt_init(dev_priv
);
821 /* This must be called before any calls to HAS_PCH_* */
822 intel_detect_pch(&dev_priv
->drm
);
824 intel_pm_setup(&dev_priv
->drm
);
825 intel_init_dpio(dev_priv
);
826 intel_power_domains_init(dev_priv
);
827 intel_irq_init(dev_priv
);
828 intel_init_display_hooks(dev_priv
);
829 intel_init_clock_gating_hooks(dev_priv
);
830 intel_init_audio_hooks(dev_priv
);
831 i915_gem_load_init(&dev_priv
->drm
);
833 intel_display_crc_init(dev_priv
);
835 intel_device_info_dump(dev_priv
);
837 /* Not all pre-production machines fall into this category, only the
838 * very first ones. Almost everything should work, except for maybe
839 * suspend/resume. And we don't implement workarounds that affect only
840 * pre-production machines. */
841 if (IS_HSW_EARLY_SDV(dev_priv
))
842 DRM_INFO("This is an early pre-production Haswell machine. "
843 "It may not be fully functional.\n");
848 i915_workqueues_cleanup(dev_priv
);
853 * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
854 * @dev_priv: device private
856 static void i915_driver_cleanup_early(struct drm_i915_private
*dev_priv
)
858 i915_gem_load_cleanup(&dev_priv
->drm
);
859 i915_workqueues_cleanup(dev_priv
);
862 static int i915_mmio_setup(struct drm_device
*dev
)
864 struct drm_i915_private
*dev_priv
= to_i915(dev
);
865 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
869 mmio_bar
= IS_GEN2(dev
) ? 1 : 0;
871 * Before gen4, the registers and the GTT are behind different BARs.
872 * However, from gen4 onwards, the registers and the GTT are shared
873 * in the same BAR, so we want to restrict this ioremap from
874 * clobbering the GTT which we want ioremap_wc instead. Fortunately,
875 * the register BAR remains the same size for all the earlier
876 * generations up to Ironlake.
878 if (INTEL_INFO(dev
)->gen
< 5)
879 mmio_size
= 512 * 1024;
881 mmio_size
= 2 * 1024 * 1024;
882 dev_priv
->regs
= pci_iomap(pdev
, mmio_bar
, mmio_size
);
883 if (dev_priv
->regs
== NULL
) {
884 DRM_ERROR("failed to map registers\n");
889 /* Try to make sure MCHBAR is enabled before poking at it */
890 intel_setup_mchbar(dev
);
895 static void i915_mmio_cleanup(struct drm_device
*dev
)
897 struct drm_i915_private
*dev_priv
= to_i915(dev
);
898 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
900 intel_teardown_mchbar(dev
);
901 pci_iounmap(pdev
, dev_priv
->regs
);
905 * i915_driver_init_mmio - setup device MMIO
906 * @dev_priv: device private
908 * Setup minimal device state necessary for MMIO accesses later in the
909 * initialization sequence. The setup here should avoid any other device-wide
910 * side effects or exposing the driver via kernel internal or user space
913 static int i915_driver_init_mmio(struct drm_i915_private
*dev_priv
)
915 struct drm_device
*dev
= &dev_priv
->drm
;
918 if (i915_inject_load_failure())
921 if (i915_get_bridge_dev(dev
))
924 ret
= i915_mmio_setup(dev
);
928 intel_uncore_init(dev_priv
);
933 pci_dev_put(dev_priv
->bridge_dev
);
939 * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
940 * @dev_priv: device private
942 static void i915_driver_cleanup_mmio(struct drm_i915_private
*dev_priv
)
944 struct drm_device
*dev
= &dev_priv
->drm
;
946 intel_uncore_fini(dev_priv
);
947 i915_mmio_cleanup(dev
);
948 pci_dev_put(dev_priv
->bridge_dev
);
951 static void intel_sanitize_options(struct drm_i915_private
*dev_priv
)
953 i915
.enable_execlists
=
954 intel_sanitize_enable_execlists(dev_priv
,
955 i915
.enable_execlists
);
958 * i915.enable_ppgtt is read-only, so do an early pass to validate the
959 * user's requested state against the hardware/driver capabilities. We
960 * do this now so that we can print out any log messages once rather
961 * than every time we check intel_enable_ppgtt().
964 intel_sanitize_enable_ppgtt(dev_priv
, i915
.enable_ppgtt
);
965 DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915
.enable_ppgtt
);
967 i915
.semaphores
= intel_sanitize_semaphores(dev_priv
, i915
.semaphores
);
968 DRM_DEBUG_DRIVER("use GPU sempahores? %s\n", yesno(i915
.semaphores
));
972 * i915_driver_init_hw - setup state requiring device access
973 * @dev_priv: device private
975 * Setup state that requires accessing the device, but doesn't require
976 * exposing the driver via kernel internal or userspace interfaces.
978 static int i915_driver_init_hw(struct drm_i915_private
*dev_priv
)
980 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
981 struct drm_device
*dev
= &dev_priv
->drm
;
984 if (i915_inject_load_failure())
987 intel_device_info_runtime_init(dev_priv
);
989 intel_sanitize_options(dev_priv
);
991 ret
= i915_ggtt_probe_hw(dev_priv
);
995 /* WARNING: Apparently we must kick fbdev drivers before vgacon,
996 * otherwise the vga fbdev driver falls over. */
997 ret
= i915_kick_out_firmware_fb(dev_priv
);
999 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1003 ret
= i915_kick_out_vgacon(dev_priv
);
1005 DRM_ERROR("failed to remove conflicting VGA console\n");
1009 ret
= i915_ggtt_init_hw(dev_priv
);
1013 ret
= i915_ggtt_enable_hw(dev_priv
);
1015 DRM_ERROR("failed to enable GGTT\n");
1019 pci_set_master(pdev
);
1021 /* overlay on gen2 is broken and can't address above 1G */
1023 ret
= dma_set_coherent_mask(&pdev
->dev
, DMA_BIT_MASK(30));
1025 DRM_ERROR("failed to set DMA mask\n");
1031 /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1032 * using 32bit addressing, overwriting memory if HWS is located
1035 * The documentation also mentions an issue with undefined
1036 * behaviour if any general state is accessed within a page above 4GB,
1037 * which also needs to be handled carefully.
1039 if (IS_BROADWATER(dev
) || IS_CRESTLINE(dev
)) {
1040 ret
= dma_set_coherent_mask(&pdev
->dev
, DMA_BIT_MASK(32));
1043 DRM_ERROR("failed to set DMA mask\n");
1049 pm_qos_add_request(&dev_priv
->pm_qos
, PM_QOS_CPU_DMA_LATENCY
,
1050 PM_QOS_DEFAULT_VALUE
);
1052 intel_uncore_sanitize(dev_priv
);
1054 intel_opregion_setup(dev_priv
);
1056 i915_gem_load_init_fences(dev_priv
);
1058 /* On the 945G/GM, the chipset reports the MSI capability on the
1059 * integrated graphics even though the support isn't actually there
1060 * according to the published specs. It doesn't appear to function
1061 * correctly in testing on 945G.
1062 * This may be a side effect of MSI having been made available for PEG
1063 * and the registers being closely associated.
1065 * According to chipset errata, on the 965GM, MSI interrupts may
1066 * be lost or delayed, but we use them anyways to avoid
1067 * stuck interrupts on some machines.
1069 if (!IS_I945G(dev
) && !IS_I945GM(dev
)) {
1070 if (pci_enable_msi(pdev
) < 0)
1071 DRM_DEBUG_DRIVER("can't enable MSI");
1077 i915_ggtt_cleanup_hw(dev_priv
);
1083 * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1084 * @dev_priv: device private
1086 static void i915_driver_cleanup_hw(struct drm_i915_private
*dev_priv
)
1088 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
1090 if (pdev
->msi_enabled
)
1091 pci_disable_msi(pdev
);
1093 pm_qos_remove_request(&dev_priv
->pm_qos
);
1094 i915_ggtt_cleanup_hw(dev_priv
);
1098 * i915_driver_register - register the driver with the rest of the system
1099 * @dev_priv: device private
1101 * Perform any steps necessary to make the driver available via kernel
1102 * internal or userspace interfaces.
1104 static void i915_driver_register(struct drm_i915_private
*dev_priv
)
1106 struct drm_device
*dev
= &dev_priv
->drm
;
1108 i915_gem_shrinker_init(dev_priv
);
1111 * Notify a valid surface after modesetting,
1112 * when running inside a VM.
1114 if (intel_vgpu_active(dev_priv
))
1115 I915_WRITE(vgtif_reg(display_ready
), VGT_DRV_DISPLAY_READY
);
1117 /* Reveal our presence to userspace */
1118 if (drm_dev_register(dev
, 0) == 0) {
1119 i915_debugfs_register(dev_priv
);
1120 i915_setup_sysfs(dev_priv
);
1122 DRM_ERROR("Failed to register driver for userspace access!\n");
1124 if (INTEL_INFO(dev_priv
)->num_pipes
) {
1125 /* Must be done after probing outputs */
1126 intel_opregion_register(dev_priv
);
1127 acpi_video_register();
1130 if (IS_GEN5(dev_priv
))
1131 intel_gpu_ips_init(dev_priv
);
1133 i915_audio_component_init(dev_priv
);
1136 * Some ports require correctly set-up hpd registers for detection to
1137 * work properly (leading to ghost connected connector status), e.g. VGA
1138 * on gm45. Hence we can only set up the initial fbdev config after hpd
1139 * irqs are fully enabled. We do it last so that the async config
1140 * cannot run before the connectors are registered.
1142 intel_fbdev_initial_config_async(dev
);
1146 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1147 * @dev_priv: device private
1149 static void i915_driver_unregister(struct drm_i915_private
*dev_priv
)
1151 i915_audio_component_cleanup(dev_priv
);
1153 intel_gpu_ips_teardown();
1154 acpi_video_unregister();
1155 intel_opregion_unregister(dev_priv
);
1157 i915_teardown_sysfs(dev_priv
);
1158 i915_debugfs_unregister(dev_priv
);
1159 drm_dev_unregister(&dev_priv
->drm
);
1161 i915_gem_shrinker_cleanup(dev_priv
);
1165 * i915_driver_load - setup chip and create an initial config
1167 * @flags: startup flags
1169 * The driver load routine has to do several things:
1170 * - drive output discovery via intel_modeset_init()
1171 * - initialize the memory manager
1172 * - allocate initial config memory
1173 * - setup the DRM framebuffer with the allocated memory
1175 int i915_driver_load(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
1177 struct drm_i915_private
*dev_priv
;
1180 if (i915
.nuclear_pageflip
) {
1182 driver
.driver_features
|= DRIVER_ATOMIC
;
1187 dev_priv
= kzalloc(sizeof(*dev_priv
), GFP_KERNEL
);
1189 ret
= drm_dev_init(&dev_priv
->drm
, &driver
, &pdev
->dev
);
1191 dev_printk(KERN_ERR
, &pdev
->dev
,
1192 "[" DRM_NAME
":%s] allocation failed\n", __func__
);
1197 dev_priv
->drm
.pdev
= pdev
;
1198 dev_priv
->drm
.dev_private
= dev_priv
;
1200 ret
= pci_enable_device(pdev
);
1204 pci_set_drvdata(pdev
, &dev_priv
->drm
);
1206 ret
= i915_driver_init_early(dev_priv
, ent
);
1208 goto out_pci_disable
;
1210 intel_runtime_pm_get(dev_priv
);
1212 ret
= i915_driver_init_mmio(dev_priv
);
1214 goto out_runtime_pm_put
;
1216 ret
= i915_driver_init_hw(dev_priv
);
1218 goto out_cleanup_mmio
;
1221 * TODO: move the vblank init and parts of modeset init steps into one
1222 * of the i915_driver_init_/i915_driver_register functions according
1223 * to the role/effect of the given init step.
1225 if (INTEL_INFO(dev_priv
)->num_pipes
) {
1226 ret
= drm_vblank_init(&dev_priv
->drm
,
1227 INTEL_INFO(dev_priv
)->num_pipes
);
1229 goto out_cleanup_hw
;
1232 ret
= i915_load_modeset_init(&dev_priv
->drm
);
1234 goto out_cleanup_vblank
;
1236 i915_driver_register(dev_priv
);
1238 intel_runtime_pm_enable(dev_priv
);
1240 /* Everything is in place, we can now relax! */
1241 DRM_INFO("Initialized %s %d.%d.%d %s for %s on minor %d\n",
1242 driver
.name
, driver
.major
, driver
.minor
, driver
.patchlevel
,
1243 driver
.date
, pci_name(pdev
), dev_priv
->drm
.primary
->index
);
1245 intel_runtime_pm_put(dev_priv
);
1250 drm_vblank_cleanup(&dev_priv
->drm
);
1252 i915_driver_cleanup_hw(dev_priv
);
1254 i915_driver_cleanup_mmio(dev_priv
);
1256 intel_runtime_pm_put(dev_priv
);
1257 i915_driver_cleanup_early(dev_priv
);
1259 pci_disable_device(pdev
);
1261 i915_load_error(dev_priv
, "Device initialization failed (%d)\n", ret
);
1262 drm_dev_unref(&dev_priv
->drm
);
1266 void i915_driver_unload(struct drm_device
*dev
)
1268 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1269 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
1271 intel_fbdev_fini(dev
);
1273 if (i915_gem_suspend(dev
))
1274 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
1276 intel_display_power_get(dev_priv
, POWER_DOMAIN_INIT
);
1278 i915_driver_unregister(dev_priv
);
1280 drm_vblank_cleanup(dev
);
1282 intel_modeset_cleanup(dev
);
1285 * free the memory space allocated for the child device
1286 * config parsed from VBT
1288 if (dev_priv
->vbt
.child_dev
&& dev_priv
->vbt
.child_dev_num
) {
1289 kfree(dev_priv
->vbt
.child_dev
);
1290 dev_priv
->vbt
.child_dev
= NULL
;
1291 dev_priv
->vbt
.child_dev_num
= 0;
1293 kfree(dev_priv
->vbt
.sdvo_lvds_vbt_mode
);
1294 dev_priv
->vbt
.sdvo_lvds_vbt_mode
= NULL
;
1295 kfree(dev_priv
->vbt
.lfp_lvds_vbt_mode
);
1296 dev_priv
->vbt
.lfp_lvds_vbt_mode
= NULL
;
1298 vga_switcheroo_unregister_client(pdev
);
1299 vga_client_register(pdev
, NULL
, NULL
, NULL
);
1301 intel_csr_ucode_fini(dev_priv
);
1303 /* Free error state after interrupts are fully disabled. */
1304 cancel_delayed_work_sync(&dev_priv
->gpu_error
.hangcheck_work
);
1305 i915_destroy_error_state(dev
);
1307 /* Flush any outstanding unpin_work. */
1308 drain_workqueue(dev_priv
->wq
);
1310 intel_guc_fini(dev
);
1312 intel_fbc_cleanup_cfb(dev_priv
);
1314 intel_power_domains_fini(dev_priv
);
1316 i915_driver_cleanup_hw(dev_priv
);
1317 i915_driver_cleanup_mmio(dev_priv
);
1319 intel_display_power_put(dev_priv
, POWER_DOMAIN_INIT
);
1321 i915_driver_cleanup_early(dev_priv
);
1324 static int i915_driver_open(struct drm_device
*dev
, struct drm_file
*file
)
1328 ret
= i915_gem_open(dev
, file
);
1336 * i915_driver_lastclose - clean up after all DRM clients have exited
1339 * Take care of cleaning up after all DRM clients have exited. In the
1340 * mode setting case, we want to restore the kernel's initial mode (just
1341 * in case the last client left us in a bad state).
1343 * Additionally, in the non-mode setting case, we'll tear down the GTT
1344 * and DMA structures, since the kernel won't be using them, and clea
1347 static void i915_driver_lastclose(struct drm_device
*dev
)
1349 intel_fbdev_restore_mode(dev
);
1350 vga_switcheroo_process_delayed_switch();
1353 static void i915_driver_preclose(struct drm_device
*dev
, struct drm_file
*file
)
1355 mutex_lock(&dev
->struct_mutex
);
1356 i915_gem_context_close(dev
, file
);
1357 i915_gem_release(dev
, file
);
1358 mutex_unlock(&dev
->struct_mutex
);
1361 static void i915_driver_postclose(struct drm_device
*dev
, struct drm_file
*file
)
1363 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
1368 static void intel_suspend_encoders(struct drm_i915_private
*dev_priv
)
1370 struct drm_device
*dev
= &dev_priv
->drm
;
1371 struct intel_encoder
*encoder
;
1373 drm_modeset_lock_all(dev
);
1374 for_each_intel_encoder(dev
, encoder
)
1375 if (encoder
->suspend
)
1376 encoder
->suspend(encoder
);
1377 drm_modeset_unlock_all(dev
);
1380 static int vlv_resume_prepare(struct drm_i915_private
*dev_priv
,
1382 static int vlv_suspend_complete(struct drm_i915_private
*dev_priv
);
1384 static bool suspend_to_idle(struct drm_i915_private
*dev_priv
)
1386 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1387 if (acpi_target_system_state() < ACPI_STATE_S3
)
1393 static int i915_drm_suspend(struct drm_device
*dev
)
1395 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1396 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
1397 pci_power_t opregion_target_state
;
1400 /* ignore lid events during suspend */
1401 mutex_lock(&dev_priv
->modeset_restore_lock
);
1402 dev_priv
->modeset_restore
= MODESET_SUSPENDED
;
1403 mutex_unlock(&dev_priv
->modeset_restore_lock
);
1405 disable_rpm_wakeref_asserts(dev_priv
);
1407 /* We do a lot of poking in a lot of registers, make sure they work
1409 intel_display_set_init_power(dev_priv
, true);
1411 drm_kms_helper_poll_disable(dev
);
1413 pci_save_state(pdev
);
1415 error
= i915_gem_suspend(dev
);
1418 "GEM idle failed, resume might fail\n");
1422 intel_guc_suspend(dev
);
1424 intel_display_suspend(dev
);
1426 intel_dp_mst_suspend(dev
);
1428 intel_runtime_pm_disable_interrupts(dev_priv
);
1429 intel_hpd_cancel_work(dev_priv
);
1431 intel_suspend_encoders(dev_priv
);
1433 intel_suspend_hw(dev
);
1435 i915_gem_suspend_gtt_mappings(dev
);
1437 i915_save_state(dev
);
1439 opregion_target_state
= suspend_to_idle(dev_priv
) ? PCI_D1
: PCI_D3cold
;
1440 intel_opregion_notify_adapter(dev_priv
, opregion_target_state
);
1442 intel_uncore_forcewake_reset(dev_priv
, false);
1443 intel_opregion_unregister(dev_priv
);
1445 intel_fbdev_set_suspend(dev
, FBINFO_STATE_SUSPENDED
, true);
1447 dev_priv
->suspend_count
++;
1449 intel_csr_ucode_suspend(dev_priv
);
1452 enable_rpm_wakeref_asserts(dev_priv
);
1457 static int i915_drm_suspend_late(struct drm_device
*dev
, bool hibernation
)
1459 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1460 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
1464 disable_rpm_wakeref_asserts(dev_priv
);
1466 intel_display_set_init_power(dev_priv
, false);
1468 fw_csr
= !IS_BROXTON(dev_priv
) &&
1469 suspend_to_idle(dev_priv
) && dev_priv
->csr
.dmc_payload
;
1471 * In case of firmware assisted context save/restore don't manually
1472 * deinit the power domains. This also means the CSR/DMC firmware will
1473 * stay active, it will power down any HW resources as required and
1474 * also enable deeper system power states that would be blocked if the
1475 * firmware was inactive.
1478 intel_power_domains_suspend(dev_priv
);
1481 if (IS_BROXTON(dev_priv
))
1482 bxt_enable_dc9(dev_priv
);
1483 else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
1484 hsw_enable_pc8(dev_priv
);
1485 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
1486 ret
= vlv_suspend_complete(dev_priv
);
1489 DRM_ERROR("Suspend complete failed: %d\n", ret
);
1491 intel_power_domains_init_hw(dev_priv
, true);
1496 pci_disable_device(pdev
);
1498 * During hibernation on some platforms the BIOS may try to access
1499 * the device even though it's already in D3 and hang the machine. So
1500 * leave the device in D0 on those platforms and hope the BIOS will
1501 * power down the device properly. The issue was seen on multiple old
1502 * GENs with different BIOS vendors, so having an explicit blacklist
1503 * is inpractical; apply the workaround on everything pre GEN6. The
1504 * platforms where the issue was seen:
1505 * Lenovo Thinkpad X301, X61s, X60, T60, X41
1509 if (!(hibernation
&& INTEL_INFO(dev_priv
)->gen
< 6))
1510 pci_set_power_state(pdev
, PCI_D3hot
);
1512 dev_priv
->suspended_to_idle
= suspend_to_idle(dev_priv
);
1515 enable_rpm_wakeref_asserts(dev_priv
);
1520 int i915_suspend_switcheroo(struct drm_device
*dev
, pm_message_t state
)
1525 DRM_ERROR("dev: %p\n", dev
);
1526 DRM_ERROR("DRM not initialized, aborting suspend.\n");
1530 if (WARN_ON_ONCE(state
.event
!= PM_EVENT_SUSPEND
&&
1531 state
.event
!= PM_EVENT_FREEZE
))
1534 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1537 error
= i915_drm_suspend(dev
);
1541 return i915_drm_suspend_late(dev
, false);
1544 static int i915_drm_resume(struct drm_device
*dev
)
1546 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1549 disable_rpm_wakeref_asserts(dev_priv
);
1550 intel_sanitize_gt_powersave(dev_priv
);
1552 ret
= i915_ggtt_enable_hw(dev_priv
);
1554 DRM_ERROR("failed to re-enable GGTT\n");
1556 intel_csr_ucode_resume(dev_priv
);
1558 i915_gem_resume(dev
);
1560 i915_restore_state(dev
);
1561 intel_pps_unlock_regs_wa(dev_priv
);
1562 intel_opregion_setup(dev_priv
);
1564 intel_init_pch_refclk(dev
);
1565 drm_mode_config_reset(dev
);
1568 * Interrupts have to be enabled before any batches are run. If not the
1569 * GPU will hang. i915_gem_init_hw() will initiate batches to
1570 * update/restore the context.
1572 * Modeset enabling in intel_modeset_init_hw() also needs working
1575 intel_runtime_pm_enable_interrupts(dev_priv
);
1577 mutex_lock(&dev
->struct_mutex
);
1578 if (i915_gem_init_hw(dev
)) {
1579 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
1580 i915_gem_set_wedged(dev_priv
);
1582 mutex_unlock(&dev
->struct_mutex
);
1584 intel_guc_resume(dev
);
1586 intel_modeset_init_hw(dev
);
1588 spin_lock_irq(&dev_priv
->irq_lock
);
1589 if (dev_priv
->display
.hpd_irq_setup
)
1590 dev_priv
->display
.hpd_irq_setup(dev_priv
);
1591 spin_unlock_irq(&dev_priv
->irq_lock
);
1593 intel_dp_mst_resume(dev
);
1595 intel_display_resume(dev
);
1598 * ... but also need to make sure that hotplug processing
1599 * doesn't cause havoc. Like in the driver load code we don't
1600 * bother with the tiny race here where we might loose hotplug
1603 intel_hpd_init(dev_priv
);
1604 /* Config may have changed between suspend and resume */
1605 drm_helper_hpd_irq_event(dev
);
1607 intel_opregion_register(dev_priv
);
1609 intel_fbdev_set_suspend(dev
, FBINFO_STATE_RUNNING
, false);
1611 mutex_lock(&dev_priv
->modeset_restore_lock
);
1612 dev_priv
->modeset_restore
= MODESET_DONE
;
1613 mutex_unlock(&dev_priv
->modeset_restore_lock
);
1615 intel_opregion_notify_adapter(dev_priv
, PCI_D0
);
1617 intel_autoenable_gt_powersave(dev_priv
);
1618 drm_kms_helper_poll_enable(dev
);
1620 enable_rpm_wakeref_asserts(dev_priv
);
1625 static int i915_drm_resume_early(struct drm_device
*dev
)
1627 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1628 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
1632 * We have a resume ordering issue with the snd-hda driver also
1633 * requiring our device to be power up. Due to the lack of a
1634 * parent/child relationship we currently solve this with an early
1637 * FIXME: This should be solved with a special hdmi sink device or
1638 * similar so that power domains can be employed.
1642 * Note that we need to set the power state explicitly, since we
1643 * powered off the device during freeze and the PCI core won't power
1644 * it back up for us during thaw. Powering off the device during
1645 * freeze is not a hard requirement though, and during the
1646 * suspend/resume phases the PCI core makes sure we get here with the
1647 * device powered on. So in case we change our freeze logic and keep
1648 * the device powered we can also remove the following set power state
1651 ret
= pci_set_power_state(pdev
, PCI_D0
);
1653 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret
);
1658 * Note that pci_enable_device() first enables any parent bridge
1659 * device and only then sets the power state for this device. The
1660 * bridge enabling is a nop though, since bridge devices are resumed
1661 * first. The order of enabling power and enabling the device is
1662 * imposed by the PCI core as described above, so here we preserve the
1663 * same order for the freeze/thaw phases.
1665 * TODO: eventually we should remove pci_disable_device() /
1666 * pci_enable_enable_device() from suspend/resume. Due to how they
1667 * depend on the device enable refcount we can't anyway depend on them
1668 * disabling/enabling the device.
1670 if (pci_enable_device(pdev
)) {
1675 pci_set_master(pdev
);
1677 disable_rpm_wakeref_asserts(dev_priv
);
1679 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
1680 ret
= vlv_resume_prepare(dev_priv
, false);
1682 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
1685 intel_uncore_early_sanitize(dev_priv
, true);
1687 if (IS_BROXTON(dev_priv
)) {
1688 if (!dev_priv
->suspended_to_idle
)
1689 gen9_sanitize_dc_state(dev_priv
);
1690 bxt_disable_dc9(dev_priv
);
1691 } else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
1692 hsw_disable_pc8(dev_priv
);
1695 intel_uncore_sanitize(dev_priv
);
1697 if (IS_BROXTON(dev_priv
) ||
1698 !(dev_priv
->suspended_to_idle
&& dev_priv
->csr
.dmc_payload
))
1699 intel_power_domains_init_hw(dev_priv
, true);
1701 enable_rpm_wakeref_asserts(dev_priv
);
1704 dev_priv
->suspended_to_idle
= false;
1709 int i915_resume_switcheroo(struct drm_device
*dev
)
1713 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1716 ret
= i915_drm_resume_early(dev
);
1720 return i915_drm_resume(dev
);
1724 * i915_reset - reset chip after a hang
1725 * @dev: drm device to reset
1727 * Reset the chip. Useful if a hang is detected. Marks the device as wedged
1730 * Caller must hold the struct_mutex.
1732 * Procedure is fairly simple:
1733 * - reset the chip using the reset reg
1734 * - re-init context state
1735 * - re-init hardware status page
1736 * - re-init ring buffer
1737 * - re-init interrupt state
1740 void i915_reset(struct drm_i915_private
*dev_priv
)
1742 struct drm_device
*dev
= &dev_priv
->drm
;
1743 struct i915_gpu_error
*error
= &dev_priv
->gpu_error
;
1746 lockdep_assert_held(&dev
->struct_mutex
);
1748 if (!test_and_clear_bit(I915_RESET_IN_PROGRESS
, &error
->flags
))
1751 /* Clear any previous failed attempts at recovery. Time to try again. */
1752 __clear_bit(I915_WEDGED
, &error
->flags
);
1753 error
->reset_count
++;
1755 pr_notice("drm/i915: Resetting chip after gpu hang\n");
1756 ret
= intel_gpu_reset(dev_priv
, ALL_ENGINES
);
1759 DRM_ERROR("Failed to reset chip: %i\n", ret
);
1761 DRM_DEBUG_DRIVER("GPU reset disabled\n");
1765 i915_gem_reset(dev_priv
);
1766 intel_overlay_reset(dev_priv
);
1768 /* Ok, now get things going again... */
1771 * Everything depends on having the GTT running, so we need to start
1772 * there. Fortunately we don't need to do this unless we reset the
1773 * chip at a PCI level.
1775 * Next we need to restore the context, but we don't use those
1778 * Ring buffer needs to be re-initialized in the KMS case, or if X
1779 * was running at the time of the reset (i.e. we weren't VT
1782 ret
= i915_gem_init_hw(dev
);
1784 DRM_ERROR("Failed hw init on reset %d\n", ret
);
1789 wake_up_bit(&error
->flags
, I915_RESET_IN_PROGRESS
);
1793 i915_gem_set_wedged(dev_priv
);
1797 static int i915_pm_suspend(struct device
*kdev
)
1799 struct pci_dev
*pdev
= to_pci_dev(kdev
);
1800 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1803 dev_err(kdev
, "DRM not initialized, aborting suspend.\n");
1807 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1810 return i915_drm_suspend(dev
);
1813 static int i915_pm_suspend_late(struct device
*kdev
)
1815 struct drm_device
*dev
= &kdev_to_i915(kdev
)->drm
;
1818 * We have a suspend ordering issue with the snd-hda driver also
1819 * requiring our device to be power up. Due to the lack of a
1820 * parent/child relationship we currently solve this with an late
1823 * FIXME: This should be solved with a special hdmi sink device or
1824 * similar so that power domains can be employed.
1826 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1829 return i915_drm_suspend_late(dev
, false);
1832 static int i915_pm_poweroff_late(struct device
*kdev
)
1834 struct drm_device
*dev
= &kdev_to_i915(kdev
)->drm
;
1836 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1839 return i915_drm_suspend_late(dev
, true);
1842 static int i915_pm_resume_early(struct device
*kdev
)
1844 struct drm_device
*dev
= &kdev_to_i915(kdev
)->drm
;
1846 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1849 return i915_drm_resume_early(dev
);
1852 static int i915_pm_resume(struct device
*kdev
)
1854 struct drm_device
*dev
= &kdev_to_i915(kdev
)->drm
;
1856 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1859 return i915_drm_resume(dev
);
1862 /* freeze: before creating the hibernation_image */
1863 static int i915_pm_freeze(struct device
*kdev
)
1867 ret
= i915_pm_suspend(kdev
);
1871 ret
= i915_gem_freeze(kdev_to_i915(kdev
));
1878 static int i915_pm_freeze_late(struct device
*kdev
)
1882 ret
= i915_pm_suspend_late(kdev
);
1886 ret
= i915_gem_freeze_late(kdev_to_i915(kdev
));
1893 /* thaw: called after creating the hibernation image, but before turning off. */
1894 static int i915_pm_thaw_early(struct device
*kdev
)
1896 return i915_pm_resume_early(kdev
);
1899 static int i915_pm_thaw(struct device
*kdev
)
1901 return i915_pm_resume(kdev
);
1904 /* restore: called after loading the hibernation image. */
1905 static int i915_pm_restore_early(struct device
*kdev
)
1907 return i915_pm_resume_early(kdev
);
1910 static int i915_pm_restore(struct device
*kdev
)
1912 return i915_pm_resume(kdev
);
1916 * Save all Gunit registers that may be lost after a D3 and a subsequent
1917 * S0i[R123] transition. The list of registers needing a save/restore is
1918 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
1919 * registers in the following way:
1920 * - Driver: saved/restored by the driver
1921 * - Punit : saved/restored by the Punit firmware
1922 * - No, w/o marking: no need to save/restore, since the register is R/O or
1923 * used internally by the HW in a way that doesn't depend
1924 * keeping the content across a suspend/resume.
1925 * - Debug : used for debugging
1927 * We save/restore all registers marked with 'Driver', with the following
1929 * - Registers out of use, including also registers marked with 'Debug'.
1930 * These have no effect on the driver's operation, so we don't save/restore
1931 * them to reduce the overhead.
1932 * - Registers that are fully setup by an initialization function called from
1933 * the resume path. For example many clock gating and RPS/RC6 registers.
1934 * - Registers that provide the right functionality with their reset defaults.
1936 * TODO: Except for registers that based on the above 3 criteria can be safely
1937 * ignored, we save/restore all others, practically treating the HW context as
1938 * a black-box for the driver. Further investigation is needed to reduce the
1939 * saved/restored registers even further, by following the same 3 criteria.
1941 static void vlv_save_gunit_s0ix_state(struct drm_i915_private
*dev_priv
)
1943 struct vlv_s0ix_state
*s
= &dev_priv
->vlv_s0ix_state
;
1946 /* GAM 0x4000-0x4770 */
1947 s
->wr_watermark
= I915_READ(GEN7_WR_WATERMARK
);
1948 s
->gfx_prio_ctrl
= I915_READ(GEN7_GFX_PRIO_CTRL
);
1949 s
->arb_mode
= I915_READ(ARB_MODE
);
1950 s
->gfx_pend_tlb0
= I915_READ(GEN7_GFX_PEND_TLB0
);
1951 s
->gfx_pend_tlb1
= I915_READ(GEN7_GFX_PEND_TLB1
);
1953 for (i
= 0; i
< ARRAY_SIZE(s
->lra_limits
); i
++)
1954 s
->lra_limits
[i
] = I915_READ(GEN7_LRA_LIMITS(i
));
1956 s
->media_max_req_count
= I915_READ(GEN7_MEDIA_MAX_REQ_COUNT
);
1957 s
->gfx_max_req_count
= I915_READ(GEN7_GFX_MAX_REQ_COUNT
);
1959 s
->render_hwsp
= I915_READ(RENDER_HWS_PGA_GEN7
);
1960 s
->ecochk
= I915_READ(GAM_ECOCHK
);
1961 s
->bsd_hwsp
= I915_READ(BSD_HWS_PGA_GEN7
);
1962 s
->blt_hwsp
= I915_READ(BLT_HWS_PGA_GEN7
);
1964 s
->tlb_rd_addr
= I915_READ(GEN7_TLB_RD_ADDR
);
1966 /* MBC 0x9024-0x91D0, 0x8500 */
1967 s
->g3dctl
= I915_READ(VLV_G3DCTL
);
1968 s
->gsckgctl
= I915_READ(VLV_GSCKGCTL
);
1969 s
->mbctl
= I915_READ(GEN6_MBCTL
);
1971 /* GCP 0x9400-0x9424, 0x8100-0x810C */
1972 s
->ucgctl1
= I915_READ(GEN6_UCGCTL1
);
1973 s
->ucgctl3
= I915_READ(GEN6_UCGCTL3
);
1974 s
->rcgctl1
= I915_READ(GEN6_RCGCTL1
);
1975 s
->rcgctl2
= I915_READ(GEN6_RCGCTL2
);
1976 s
->rstctl
= I915_READ(GEN6_RSTCTL
);
1977 s
->misccpctl
= I915_READ(GEN7_MISCCPCTL
);
1979 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1980 s
->gfxpause
= I915_READ(GEN6_GFXPAUSE
);
1981 s
->rpdeuhwtc
= I915_READ(GEN6_RPDEUHWTC
);
1982 s
->rpdeuc
= I915_READ(GEN6_RPDEUC
);
1983 s
->ecobus
= I915_READ(ECOBUS
);
1984 s
->pwrdwnupctl
= I915_READ(VLV_PWRDWNUPCTL
);
1985 s
->rp_down_timeout
= I915_READ(GEN6_RP_DOWN_TIMEOUT
);
1986 s
->rp_deucsw
= I915_READ(GEN6_RPDEUCSW
);
1987 s
->rcubmabdtmr
= I915_READ(GEN6_RCUBMABDTMR
);
1988 s
->rcedata
= I915_READ(VLV_RCEDATA
);
1989 s
->spare2gh
= I915_READ(VLV_SPAREG2H
);
1991 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1992 s
->gt_imr
= I915_READ(GTIMR
);
1993 s
->gt_ier
= I915_READ(GTIER
);
1994 s
->pm_imr
= I915_READ(GEN6_PMIMR
);
1995 s
->pm_ier
= I915_READ(GEN6_PMIER
);
1997 for (i
= 0; i
< ARRAY_SIZE(s
->gt_scratch
); i
++)
1998 s
->gt_scratch
[i
] = I915_READ(GEN7_GT_SCRATCH(i
));
2000 /* GT SA CZ domain, 0x100000-0x138124 */
2001 s
->tilectl
= I915_READ(TILECTL
);
2002 s
->gt_fifoctl
= I915_READ(GTFIFOCTL
);
2003 s
->gtlc_wake_ctrl
= I915_READ(VLV_GTLC_WAKE_CTRL
);
2004 s
->gtlc_survive
= I915_READ(VLV_GTLC_SURVIVABILITY_REG
);
2005 s
->pmwgicz
= I915_READ(VLV_PMWGICZ
);
2007 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2008 s
->gu_ctl0
= I915_READ(VLV_GU_CTL0
);
2009 s
->gu_ctl1
= I915_READ(VLV_GU_CTL1
);
2010 s
->pcbr
= I915_READ(VLV_PCBR
);
2011 s
->clock_gate_dis2
= I915_READ(VLV_GUNIT_CLOCK_GATE2
);
2014 * Not saving any of:
2015 * DFT, 0x9800-0x9EC0
2016 * SARB, 0xB000-0xB1FC
2017 * GAC, 0x5208-0x524C, 0x14000-0x14C000
2022 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private
*dev_priv
)
2024 struct vlv_s0ix_state
*s
= &dev_priv
->vlv_s0ix_state
;
2028 /* GAM 0x4000-0x4770 */
2029 I915_WRITE(GEN7_WR_WATERMARK
, s
->wr_watermark
);
2030 I915_WRITE(GEN7_GFX_PRIO_CTRL
, s
->gfx_prio_ctrl
);
2031 I915_WRITE(ARB_MODE
, s
->arb_mode
| (0xffff << 16));
2032 I915_WRITE(GEN7_GFX_PEND_TLB0
, s
->gfx_pend_tlb0
);
2033 I915_WRITE(GEN7_GFX_PEND_TLB1
, s
->gfx_pend_tlb1
);
2035 for (i
= 0; i
< ARRAY_SIZE(s
->lra_limits
); i
++)
2036 I915_WRITE(GEN7_LRA_LIMITS(i
), s
->lra_limits
[i
]);
2038 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT
, s
->media_max_req_count
);
2039 I915_WRITE(GEN7_GFX_MAX_REQ_COUNT
, s
->gfx_max_req_count
);
2041 I915_WRITE(RENDER_HWS_PGA_GEN7
, s
->render_hwsp
);
2042 I915_WRITE(GAM_ECOCHK
, s
->ecochk
);
2043 I915_WRITE(BSD_HWS_PGA_GEN7
, s
->bsd_hwsp
);
2044 I915_WRITE(BLT_HWS_PGA_GEN7
, s
->blt_hwsp
);
2046 I915_WRITE(GEN7_TLB_RD_ADDR
, s
->tlb_rd_addr
);
2048 /* MBC 0x9024-0x91D0, 0x8500 */
2049 I915_WRITE(VLV_G3DCTL
, s
->g3dctl
);
2050 I915_WRITE(VLV_GSCKGCTL
, s
->gsckgctl
);
2051 I915_WRITE(GEN6_MBCTL
, s
->mbctl
);
2053 /* GCP 0x9400-0x9424, 0x8100-0x810C */
2054 I915_WRITE(GEN6_UCGCTL1
, s
->ucgctl1
);
2055 I915_WRITE(GEN6_UCGCTL3
, s
->ucgctl3
);
2056 I915_WRITE(GEN6_RCGCTL1
, s
->rcgctl1
);
2057 I915_WRITE(GEN6_RCGCTL2
, s
->rcgctl2
);
2058 I915_WRITE(GEN6_RSTCTL
, s
->rstctl
);
2059 I915_WRITE(GEN7_MISCCPCTL
, s
->misccpctl
);
2061 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2062 I915_WRITE(GEN6_GFXPAUSE
, s
->gfxpause
);
2063 I915_WRITE(GEN6_RPDEUHWTC
, s
->rpdeuhwtc
);
2064 I915_WRITE(GEN6_RPDEUC
, s
->rpdeuc
);
2065 I915_WRITE(ECOBUS
, s
->ecobus
);
2066 I915_WRITE(VLV_PWRDWNUPCTL
, s
->pwrdwnupctl
);
2067 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
,s
->rp_down_timeout
);
2068 I915_WRITE(GEN6_RPDEUCSW
, s
->rp_deucsw
);
2069 I915_WRITE(GEN6_RCUBMABDTMR
, s
->rcubmabdtmr
);
2070 I915_WRITE(VLV_RCEDATA
, s
->rcedata
);
2071 I915_WRITE(VLV_SPAREG2H
, s
->spare2gh
);
2073 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2074 I915_WRITE(GTIMR
, s
->gt_imr
);
2075 I915_WRITE(GTIER
, s
->gt_ier
);
2076 I915_WRITE(GEN6_PMIMR
, s
->pm_imr
);
2077 I915_WRITE(GEN6_PMIER
, s
->pm_ier
);
2079 for (i
= 0; i
< ARRAY_SIZE(s
->gt_scratch
); i
++)
2080 I915_WRITE(GEN7_GT_SCRATCH(i
), s
->gt_scratch
[i
]);
2082 /* GT SA CZ domain, 0x100000-0x138124 */
2083 I915_WRITE(TILECTL
, s
->tilectl
);
2084 I915_WRITE(GTFIFOCTL
, s
->gt_fifoctl
);
2086 * Preserve the GT allow wake and GFX force clock bit, they are not
2087 * be restored, as they are used to control the s0ix suspend/resume
2088 * sequence by the caller.
2090 val
= I915_READ(VLV_GTLC_WAKE_CTRL
);
2091 val
&= VLV_GTLC_ALLOWWAKEREQ
;
2092 val
|= s
->gtlc_wake_ctrl
& ~VLV_GTLC_ALLOWWAKEREQ
;
2093 I915_WRITE(VLV_GTLC_WAKE_CTRL
, val
);
2095 val
= I915_READ(VLV_GTLC_SURVIVABILITY_REG
);
2096 val
&= VLV_GFX_CLK_FORCE_ON_BIT
;
2097 val
|= s
->gtlc_survive
& ~VLV_GFX_CLK_FORCE_ON_BIT
;
2098 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG
, val
);
2100 I915_WRITE(VLV_PMWGICZ
, s
->pmwgicz
);
2102 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2103 I915_WRITE(VLV_GU_CTL0
, s
->gu_ctl0
);
2104 I915_WRITE(VLV_GU_CTL1
, s
->gu_ctl1
);
2105 I915_WRITE(VLV_PCBR
, s
->pcbr
);
2106 I915_WRITE(VLV_GUNIT_CLOCK_GATE2
, s
->clock_gate_dis2
);
2109 int vlv_force_gfx_clock(struct drm_i915_private
*dev_priv
, bool force_on
)
2114 val
= I915_READ(VLV_GTLC_SURVIVABILITY_REG
);
2115 val
&= ~VLV_GFX_CLK_FORCE_ON_BIT
;
2117 val
|= VLV_GFX_CLK_FORCE_ON_BIT
;
2118 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG
, val
);
2123 err
= intel_wait_for_register(dev_priv
,
2124 VLV_GTLC_SURVIVABILITY_REG
,
2125 VLV_GFX_CLK_STATUS_BIT
,
2126 VLV_GFX_CLK_STATUS_BIT
,
2129 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2130 I915_READ(VLV_GTLC_SURVIVABILITY_REG
));
2135 static int vlv_allow_gt_wake(struct drm_i915_private
*dev_priv
, bool allow
)
2140 val
= I915_READ(VLV_GTLC_WAKE_CTRL
);
2141 val
&= ~VLV_GTLC_ALLOWWAKEREQ
;
2143 val
|= VLV_GTLC_ALLOWWAKEREQ
;
2144 I915_WRITE(VLV_GTLC_WAKE_CTRL
, val
);
2145 POSTING_READ(VLV_GTLC_WAKE_CTRL
);
2147 err
= intel_wait_for_register(dev_priv
,
2149 VLV_GTLC_ALLOWWAKEACK
,
2153 DRM_ERROR("timeout disabling GT waking\n");
2158 static int vlv_wait_for_gt_wells(struct drm_i915_private
*dev_priv
,
2165 mask
= VLV_GTLC_PW_MEDIA_STATUS_MASK
| VLV_GTLC_PW_RENDER_STATUS_MASK
;
2166 val
= wait_for_on
? mask
: 0;
2167 if ((I915_READ(VLV_GTLC_PW_STATUS
) & mask
) == val
)
2170 DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
2172 I915_READ(VLV_GTLC_PW_STATUS
));
2175 * RC6 transitioning can be delayed up to 2 msec (see
2176 * valleyview_enable_rps), use 3 msec for safety.
2178 err
= intel_wait_for_register(dev_priv
,
2179 VLV_GTLC_PW_STATUS
, mask
, val
,
2182 DRM_ERROR("timeout waiting for GT wells to go %s\n",
2183 onoff(wait_for_on
));
2188 static void vlv_check_no_gt_access(struct drm_i915_private
*dev_priv
)
2190 if (!(I915_READ(VLV_GTLC_PW_STATUS
) & VLV_GTLC_ALLOWWAKEERR
))
2193 DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
2194 I915_WRITE(VLV_GTLC_PW_STATUS
, VLV_GTLC_ALLOWWAKEERR
);
2197 static int vlv_suspend_complete(struct drm_i915_private
*dev_priv
)
2203 * Bspec defines the following GT well on flags as debug only, so
2204 * don't treat them as hard failures.
2206 (void)vlv_wait_for_gt_wells(dev_priv
, false);
2208 mask
= VLV_GTLC_RENDER_CTX_EXISTS
| VLV_GTLC_MEDIA_CTX_EXISTS
;
2209 WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL
) & mask
) != mask
);
2211 vlv_check_no_gt_access(dev_priv
);
2213 err
= vlv_force_gfx_clock(dev_priv
, true);
2217 err
= vlv_allow_gt_wake(dev_priv
, false);
2221 if (!IS_CHERRYVIEW(dev_priv
))
2222 vlv_save_gunit_s0ix_state(dev_priv
);
2224 err
= vlv_force_gfx_clock(dev_priv
, false);
2231 /* For safety always re-enable waking and disable gfx clock forcing */
2232 vlv_allow_gt_wake(dev_priv
, true);
2234 vlv_force_gfx_clock(dev_priv
, false);
2239 static int vlv_resume_prepare(struct drm_i915_private
*dev_priv
,
2242 struct drm_device
*dev
= &dev_priv
->drm
;
2247 * If any of the steps fail just try to continue, that's the best we
2248 * can do at this point. Return the first error code (which will also
2249 * leave RPM permanently disabled).
2251 ret
= vlv_force_gfx_clock(dev_priv
, true);
2253 if (!IS_CHERRYVIEW(dev_priv
))
2254 vlv_restore_gunit_s0ix_state(dev_priv
);
2256 err
= vlv_allow_gt_wake(dev_priv
, true);
2260 err
= vlv_force_gfx_clock(dev_priv
, false);
2264 vlv_check_no_gt_access(dev_priv
);
2267 intel_init_clock_gating(dev
);
2268 i915_gem_restore_fences(dev
);
2274 static int intel_runtime_suspend(struct device
*kdev
)
2276 struct pci_dev
*pdev
= to_pci_dev(kdev
);
2277 struct drm_device
*dev
= pci_get_drvdata(pdev
);
2278 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2281 if (WARN_ON_ONCE(!(dev_priv
->rps
.enabled
&& intel_enable_rc6())))
2284 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev
)))
2287 DRM_DEBUG_KMS("Suspending device\n");
2290 * We could deadlock here in case another thread holding struct_mutex
2291 * calls RPM suspend concurrently, since the RPM suspend will wait
2292 * first for this RPM suspend to finish. In this case the concurrent
2293 * RPM resume will be followed by its RPM suspend counterpart. Still
2294 * for consistency return -EAGAIN, which will reschedule this suspend.
2296 if (!mutex_trylock(&dev
->struct_mutex
)) {
2297 DRM_DEBUG_KMS("device lock contention, deffering suspend\n");
2299 * Bump the expiration timestamp, otherwise the suspend won't
2302 pm_runtime_mark_last_busy(kdev
);
2307 disable_rpm_wakeref_asserts(dev_priv
);
2310 * We are safe here against re-faults, since the fault handler takes
2313 i915_gem_release_all_mmaps(dev_priv
);
2314 mutex_unlock(&dev
->struct_mutex
);
2316 intel_guc_suspend(dev
);
2318 intel_runtime_pm_disable_interrupts(dev_priv
);
2321 if (IS_BROXTON(dev_priv
)) {
2322 bxt_display_core_uninit(dev_priv
);
2323 bxt_enable_dc9(dev_priv
);
2324 } else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
2325 hsw_enable_pc8(dev_priv
);
2326 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
2327 ret
= vlv_suspend_complete(dev_priv
);
2331 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret
);
2332 intel_runtime_pm_enable_interrupts(dev_priv
);
2334 enable_rpm_wakeref_asserts(dev_priv
);
2339 intel_uncore_forcewake_reset(dev_priv
, false);
2341 enable_rpm_wakeref_asserts(dev_priv
);
2342 WARN_ON_ONCE(atomic_read(&dev_priv
->pm
.wakeref_count
));
2344 if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv
))
2345 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2347 dev_priv
->pm
.suspended
= true;
2350 * FIXME: We really should find a document that references the arguments
2353 if (IS_BROADWELL(dev_priv
)) {
2355 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2356 * being detected, and the call we do at intel_runtime_resume()
2357 * won't be able to restore them. Since PCI_D3hot matches the
2358 * actual specification and appears to be working, use it.
2360 intel_opregion_notify_adapter(dev_priv
, PCI_D3hot
);
2363 * current versions of firmware which depend on this opregion
2364 * notification have repurposed the D1 definition to mean
2365 * "runtime suspended" vs. what you would normally expect (D3)
2366 * to distinguish it from notifications that might be sent via
2369 intel_opregion_notify_adapter(dev_priv
, PCI_D1
);
2372 assert_forcewakes_inactive(dev_priv
);
2374 if (!IS_VALLEYVIEW(dev_priv
) && !IS_CHERRYVIEW(dev_priv
))
2375 intel_hpd_poll_init(dev_priv
);
2377 DRM_DEBUG_KMS("Device suspended\n");
2381 static int intel_runtime_resume(struct device
*kdev
)
2383 struct pci_dev
*pdev
= to_pci_dev(kdev
);
2384 struct drm_device
*dev
= pci_get_drvdata(pdev
);
2385 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2388 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev
)))
2391 DRM_DEBUG_KMS("Resuming device\n");
2393 WARN_ON_ONCE(atomic_read(&dev_priv
->pm
.wakeref_count
));
2394 disable_rpm_wakeref_asserts(dev_priv
);
2396 intel_opregion_notify_adapter(dev_priv
, PCI_D0
);
2397 dev_priv
->pm
.suspended
= false;
2398 if (intel_uncore_unclaimed_mmio(dev_priv
))
2399 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
2401 intel_guc_resume(dev
);
2403 if (IS_GEN6(dev_priv
))
2404 intel_init_pch_refclk(dev
);
2406 if (IS_BROXTON(dev
)) {
2407 bxt_disable_dc9(dev_priv
);
2408 bxt_display_core_init(dev_priv
, true);
2409 if (dev_priv
->csr
.dmc_payload
&&
2410 (dev_priv
->csr
.allowed_dc_mask
& DC_STATE_EN_UPTO_DC5
))
2411 gen9_enable_dc5(dev_priv
);
2412 } else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
2413 hsw_disable_pc8(dev_priv
);
2414 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
2415 ret
= vlv_resume_prepare(dev_priv
, true);
2419 * No point of rolling back things in case of an error, as the best
2420 * we can do is to hope that things will still work (and disable RPM).
2422 i915_gem_init_swizzling(dev
);
2424 intel_runtime_pm_enable_interrupts(dev_priv
);
2427 * On VLV/CHV display interrupts are part of the display
2428 * power well, so hpd is reinitialized from there. For
2429 * everyone else do it here.
2431 if (!IS_VALLEYVIEW(dev_priv
) && !IS_CHERRYVIEW(dev_priv
))
2432 intel_hpd_init(dev_priv
);
2434 enable_rpm_wakeref_asserts(dev_priv
);
2437 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret
);
2439 DRM_DEBUG_KMS("Device resumed\n");
2444 const struct dev_pm_ops i915_pm_ops
= {
2446 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
2449 .suspend
= i915_pm_suspend
,
2450 .suspend_late
= i915_pm_suspend_late
,
2451 .resume_early
= i915_pm_resume_early
,
2452 .resume
= i915_pm_resume
,
2456 * @freeze, @freeze_late : called (1) before creating the
2457 * hibernation image [PMSG_FREEZE] and
2458 * (2) after rebooting, before restoring
2459 * the image [PMSG_QUIESCE]
2460 * @thaw, @thaw_early : called (1) after creating the hibernation
2461 * image, before writing it [PMSG_THAW]
2462 * and (2) after failing to create or
2463 * restore the image [PMSG_RECOVER]
2464 * @poweroff, @poweroff_late: called after writing the hibernation
2465 * image, before rebooting [PMSG_HIBERNATE]
2466 * @restore, @restore_early : called after rebooting and restoring the
2467 * hibernation image [PMSG_RESTORE]
2469 .freeze
= i915_pm_freeze
,
2470 .freeze_late
= i915_pm_freeze_late
,
2471 .thaw_early
= i915_pm_thaw_early
,
2472 .thaw
= i915_pm_thaw
,
2473 .poweroff
= i915_pm_suspend
,
2474 .poweroff_late
= i915_pm_poweroff_late
,
2475 .restore_early
= i915_pm_restore_early
,
2476 .restore
= i915_pm_restore
,
2478 /* S0ix (via runtime suspend) event handlers */
2479 .runtime_suspend
= intel_runtime_suspend
,
2480 .runtime_resume
= intel_runtime_resume
,
2483 static const struct vm_operations_struct i915_gem_vm_ops
= {
2484 .fault
= i915_gem_fault
,
2485 .open
= drm_gem_vm_open
,
2486 .close
= drm_gem_vm_close
,
2489 static const struct file_operations i915_driver_fops
= {
2490 .owner
= THIS_MODULE
,
2492 .release
= drm_release
,
2493 .unlocked_ioctl
= drm_ioctl
,
2494 .mmap
= drm_gem_mmap
,
2497 #ifdef CONFIG_COMPAT
2498 .compat_ioctl
= i915_compat_ioctl
,
2500 .llseek
= noop_llseek
,
2504 i915_gem_reject_pin_ioctl(struct drm_device
*dev
, void *data
,
2505 struct drm_file
*file
)
2510 static const struct drm_ioctl_desc i915_ioctls
[] = {
2511 DRM_IOCTL_DEF_DRV(I915_INIT
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2512 DRM_IOCTL_DEF_DRV(I915_FLUSH
, drm_noop
, DRM_AUTH
),
2513 DRM_IOCTL_DEF_DRV(I915_FLIP
, drm_noop
, DRM_AUTH
),
2514 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER
, drm_noop
, DRM_AUTH
),
2515 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT
, drm_noop
, DRM_AUTH
),
2516 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT
, drm_noop
, DRM_AUTH
),
2517 DRM_IOCTL_DEF_DRV(I915_GETPARAM
, i915_getparam
, DRM_AUTH
|DRM_RENDER_ALLOW
),
2518 DRM_IOCTL_DEF_DRV(I915_SETPARAM
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2519 DRM_IOCTL_DEF_DRV(I915_ALLOC
, drm_noop
, DRM_AUTH
),
2520 DRM_IOCTL_DEF_DRV(I915_FREE
, drm_noop
, DRM_AUTH
),
2521 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2522 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER
, drm_noop
, DRM_AUTH
),
2523 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2524 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2525 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE
, drm_noop
, DRM_AUTH
),
2526 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP
, drm_noop
, DRM_AUTH
),
2527 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2528 DRM_IOCTL_DEF_DRV(I915_GEM_INIT
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2529 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER
, i915_gem_execbuffer
, DRM_AUTH
),
2530 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2
, i915_gem_execbuffer2
, DRM_AUTH
|DRM_RENDER_ALLOW
),
2531 DRM_IOCTL_DEF_DRV(I915_GEM_PIN
, i915_gem_reject_pin_ioctl
, DRM_AUTH
|DRM_ROOT_ONLY
),
2532 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN
, i915_gem_reject_pin_ioctl
, DRM_AUTH
|DRM_ROOT_ONLY
),
2533 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY
, i915_gem_busy_ioctl
, DRM_AUTH
|DRM_RENDER_ALLOW
),
2534 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING
, i915_gem_set_caching_ioctl
, DRM_RENDER_ALLOW
),
2535 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING
, i915_gem_get_caching_ioctl
, DRM_RENDER_ALLOW
),
2536 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE
, i915_gem_throttle_ioctl
, DRM_AUTH
|DRM_RENDER_ALLOW
),
2537 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2538 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2539 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE
, i915_gem_create_ioctl
, DRM_RENDER_ALLOW
),
2540 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD
, i915_gem_pread_ioctl
, DRM_RENDER_ALLOW
),
2541 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE
, i915_gem_pwrite_ioctl
, DRM_RENDER_ALLOW
),
2542 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP
, i915_gem_mmap_ioctl
, DRM_RENDER_ALLOW
),
2543 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT
, i915_gem_mmap_gtt_ioctl
, DRM_RENDER_ALLOW
),
2544 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN
, i915_gem_set_domain_ioctl
, DRM_RENDER_ALLOW
),
2545 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH
, i915_gem_sw_finish_ioctl
, DRM_RENDER_ALLOW
),
2546 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING
, i915_gem_set_tiling
, DRM_RENDER_ALLOW
),
2547 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING
, i915_gem_get_tiling
, DRM_RENDER_ALLOW
),
2548 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE
, i915_gem_get_aperture_ioctl
, DRM_RENDER_ALLOW
),
2549 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID
, intel_get_pipe_from_crtc_id
, 0),
2550 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE
, i915_gem_madvise_ioctl
, DRM_RENDER_ALLOW
),
2551 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE
, intel_overlay_put_image_ioctl
, DRM_MASTER
|DRM_CONTROL_ALLOW
),
2552 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS
, intel_overlay_attrs_ioctl
, DRM_MASTER
|DRM_CONTROL_ALLOW
),
2553 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY
, intel_sprite_set_colorkey
, DRM_MASTER
|DRM_CONTROL_ALLOW
),
2554 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY
, drm_noop
, DRM_MASTER
|DRM_CONTROL_ALLOW
),
2555 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT
, i915_gem_wait_ioctl
, DRM_AUTH
|DRM_RENDER_ALLOW
),
2556 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE
, i915_gem_context_create_ioctl
, DRM_RENDER_ALLOW
),
2557 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY
, i915_gem_context_destroy_ioctl
, DRM_RENDER_ALLOW
),
2558 DRM_IOCTL_DEF_DRV(I915_REG_READ
, i915_reg_read_ioctl
, DRM_RENDER_ALLOW
),
2559 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS
, i915_gem_context_reset_stats_ioctl
, DRM_RENDER_ALLOW
),
2560 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR
, i915_gem_userptr_ioctl
, DRM_RENDER_ALLOW
),
2561 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM
, i915_gem_context_getparam_ioctl
, DRM_RENDER_ALLOW
),
2562 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM
, i915_gem_context_setparam_ioctl
, DRM_RENDER_ALLOW
),
2565 static drm_driver_no_const driver __read_only
= {
2566 /* Don't use MTRRs here; the Xserver or userspace app should
2567 * deal with them for Intel hardware.
2570 DRIVER_HAVE_IRQ
| DRIVER_IRQ_SHARED
| DRIVER_GEM
| DRIVER_PRIME
|
2571 DRIVER_RENDER
| DRIVER_MODESET
,
2572 .open
= i915_driver_open
,
2573 .lastclose
= i915_driver_lastclose
,
2574 .preclose
= i915_driver_preclose
,
2575 .postclose
= i915_driver_postclose
,
2576 .set_busid
= drm_pci_set_busid
,
2578 .gem_close_object
= i915_gem_close_object
,
2579 .gem_free_object
= i915_gem_free_object
,
2580 .gem_vm_ops
= &i915_gem_vm_ops
,
2582 .prime_handle_to_fd
= drm_gem_prime_handle_to_fd
,
2583 .prime_fd_to_handle
= drm_gem_prime_fd_to_handle
,
2584 .gem_prime_export
= i915_gem_prime_export
,
2585 .gem_prime_import
= i915_gem_prime_import
,
2587 .dumb_create
= i915_gem_dumb_create
,
2588 .dumb_map_offset
= i915_gem_mmap_gtt
,
2589 .dumb_destroy
= drm_gem_dumb_destroy
,
2590 .ioctls
= i915_ioctls
,
2591 .num_ioctls
= ARRAY_SIZE(i915_ioctls
),
2592 .fops
= &i915_driver_fops
,
2593 .name
= DRIVER_NAME
,
2594 .desc
= DRIVER_DESC
,
2595 .date
= DRIVER_DATE
,
2596 .major
= DRIVER_MAJOR
,
2597 .minor
= DRIVER_MINOR
,
2598 .patchlevel
= DRIVER_PATCHLEVEL
,