1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-algo-bit.h>
39 #include <linux/backlight.h>
40 #include <linux/hash.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/kref.h>
43 #include <linux/mm_types.h>
44 #include <linux/perf_event.h>
45 #include <linux/pm_qos.h>
46 #include <linux/reservation.h>
47 #include <linux/shmem_fs.h>
50 #include <drm/intel-gtt.h>
51 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
52 #include <drm/drm_gem.h>
53 #include <drm/drm_auth.h>
54 #include <drm/drm_cache.h>
55 #include <drm/drm_util.h>
56 #include <drm/drm_dsc.h>
58 #include "i915_fixed.h"
59 #include "i915_params.h"
61 #include "i915_utils.h"
63 #include "intel_bios.h"
64 #include "intel_device_info.h"
65 #include "intel_display.h"
66 #include "intel_dpll_mgr.h"
67 #include "intel_lrc.h"
68 #include "intel_opregion.h"
69 #include "intel_ringbuffer.h"
70 #include "intel_uncore.h"
71 #include "intel_wopcm.h"
72 #include "intel_workarounds.h"
76 #include "i915_gem_context.h"
77 #include "i915_gem_fence_reg.h"
78 #include "i915_gem_object.h"
79 #include "i915_gem_gtt.h"
80 #include "i915_gpu_error.h"
81 #include "i915_request.h"
82 #include "i915_scheduler.h"
83 #include "i915_timeline.h"
86 #include "intel_gvt.h"
88 /* General customization:
91 #define DRIVER_NAME "i915"
92 #define DRIVER_DESC "Intel Graphics"
93 #define DRIVER_DATE "20181204"
94 #define DRIVER_TIMESTAMP 1543944377
96 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
97 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
98 * which may not necessarily be a user visible problem. This will either
99 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
100 * enable distros and users to tailor their preferred amount of i915 abrt
103 #define I915_STATE_WARN(condition, format...) ({ \
104 int __ret_warn_on = !!(condition); \
105 if (unlikely(__ret_warn_on)) \
106 if (!WARN(i915_modparams.verbose_state_checks, format)) \
108 unlikely(__ret_warn_on); \
111 #define I915_STATE_WARN_ON(x) \
112 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
114 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
116 bool __i915_inject_load_failure(const char *func
, int line
);
117 #define i915_inject_load_failure() \
118 __i915_inject_load_failure(__func__, __LINE__)
120 bool i915_error_injected(void);
124 #define i915_inject_load_failure() false
125 #define i915_error_injected() false
129 #define i915_load_error(i915, fmt, ...) \
130 __i915_printk(i915, i915_error_injected() ? KERN_DEBUG : KERN_ERR, \
135 HPD_TV
= HPD_NONE
, /* TV is known to be unreliable */
148 #define for_each_hpd_pin(__pin) \
149 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
151 /* Threshold == 5 for long IRQs, 50 for short */
152 #define HPD_STORM_DEFAULT_THRESHOLD 50
154 struct i915_hotplug
{
155 struct work_struct hotplug_work
;
158 unsigned long last_jiffies
;
163 HPD_MARK_DISABLED
= 2
165 } stats
[HPD_NUM_PINS
];
167 struct delayed_work reenable_work
;
171 struct work_struct dig_port_work
;
173 struct work_struct poll_init_work
;
176 unsigned int hpd_storm_threshold
;
177 /* Whether or not to count short HPD IRQs in HPD storms */
178 u8 hpd_short_storm_enabled
;
181 * if we get a HPD irq from DP and a HPD irq from non-DP
182 * the non-DP HPD could block the workqueue on a mode config
183 * mutex getting, that userspace may have taken. However
184 * userspace is waiting on the DP workqueue to run which is
185 * blocked behind the non-DP one.
187 struct workqueue_struct
*dp_wq
;
190 #define I915_GEM_GPU_DOMAINS \
191 (I915_GEM_DOMAIN_RENDER | \
192 I915_GEM_DOMAIN_SAMPLER | \
193 I915_GEM_DOMAIN_COMMAND | \
194 I915_GEM_DOMAIN_INSTRUCTION | \
195 I915_GEM_DOMAIN_VERTEX)
197 struct drm_i915_private
;
198 struct i915_mm_struct
;
199 struct i915_mmu_object
;
201 struct drm_i915_file_private
{
202 struct drm_i915_private
*dev_priv
;
203 struct drm_file
*file
;
207 struct list_head request_list
;
208 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
209 * chosen to prevent the CPU getting more than a frame ahead of the GPU
210 * (when using lax throttling for the frontbuffer). We also use it to
211 * offer free GPU waitboosts for severely congested workloads.
213 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
215 struct idr context_idr
;
217 struct intel_rps_client
{
221 unsigned int bsd_engine
;
224 * Every context ban increments per client ban score. Also
225 * hangs in short succession increments ban score. If ban threshold
226 * is reached, client is considered banned and submitting more work
227 * will fail. This is a stop gap measure to limit the badly behaving
228 * clients access to gpu. Note that unbannable contexts never increment
229 * the client ban score.
231 #define I915_CLIENT_SCORE_HANG_FAST 1
232 #define I915_CLIENT_FAST_HANG_JIFFIES (60 * HZ)
233 #define I915_CLIENT_SCORE_CONTEXT_BAN 3
234 #define I915_CLIENT_SCORE_BANNED 9
235 /** ban_score: Accumulated score of all ctx bans and fast hangs. */
237 unsigned long hang_timestamp
;
240 /* Interface history:
243 * 1.2: Add Power Management
244 * 1.3: Add vblank support
245 * 1.4: Fix cmdbuffer path, add heap destroy
246 * 1.5: Add vblank pipe configuration
247 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
248 * - Support vertical blank on secondary display pipe
250 #define DRIVER_MAJOR 1
251 #define DRIVER_MINOR 6
252 #define DRIVER_PATCHLEVEL 0
254 struct intel_overlay
;
255 struct intel_overlay_error_state
;
257 struct sdvo_device_mapping
{
266 struct intel_connector
;
267 struct intel_encoder
;
268 struct intel_atomic_state
;
269 struct intel_crtc_state
;
270 struct intel_initial_plane_config
;
274 struct intel_cdclk_state
;
276 struct drm_i915_display_funcs
{
277 void (*get_cdclk
)(struct drm_i915_private
*dev_priv
,
278 struct intel_cdclk_state
*cdclk_state
);
279 void (*set_cdclk
)(struct drm_i915_private
*dev_priv
,
280 const struct intel_cdclk_state
*cdclk_state
);
281 int (*get_fifo_size
)(struct drm_i915_private
*dev_priv
,
282 enum i9xx_plane_id i9xx_plane
);
283 int (*compute_pipe_wm
)(struct intel_crtc_state
*cstate
);
284 int (*compute_intermediate_wm
)(struct drm_device
*dev
,
285 struct intel_crtc
*intel_crtc
,
286 struct intel_crtc_state
*newstate
);
287 void (*initial_watermarks
)(struct intel_atomic_state
*state
,
288 struct intel_crtc_state
*cstate
);
289 void (*atomic_update_watermarks
)(struct intel_atomic_state
*state
,
290 struct intel_crtc_state
*cstate
);
291 void (*optimize_watermarks
)(struct intel_atomic_state
*state
,
292 struct intel_crtc_state
*cstate
);
293 int (*compute_global_watermarks
)(struct drm_atomic_state
*state
);
294 void (*update_wm
)(struct intel_crtc
*crtc
);
295 int (*modeset_calc_cdclk
)(struct drm_atomic_state
*state
);
296 /* Returns the active state of the crtc, and if the crtc is active,
297 * fills out the pipe-config with the hw state. */
298 bool (*get_pipe_config
)(struct intel_crtc
*,
299 struct intel_crtc_state
*);
300 void (*get_initial_plane_config
)(struct intel_crtc
*,
301 struct intel_initial_plane_config
*);
302 int (*crtc_compute_clock
)(struct intel_crtc
*crtc
,
303 struct intel_crtc_state
*crtc_state
);
304 void (*crtc_enable
)(struct intel_crtc_state
*pipe_config
,
305 struct drm_atomic_state
*old_state
);
306 void (*crtc_disable
)(struct intel_crtc_state
*old_crtc_state
,
307 struct drm_atomic_state
*old_state
);
308 void (*update_crtcs
)(struct drm_atomic_state
*state
);
309 void (*audio_codec_enable
)(struct intel_encoder
*encoder
,
310 const struct intel_crtc_state
*crtc_state
,
311 const struct drm_connector_state
*conn_state
);
312 void (*audio_codec_disable
)(struct intel_encoder
*encoder
,
313 const struct intel_crtc_state
*old_crtc_state
,
314 const struct drm_connector_state
*old_conn_state
);
315 void (*fdi_link_train
)(struct intel_crtc
*crtc
,
316 const struct intel_crtc_state
*crtc_state
);
317 void (*init_clock_gating
)(struct drm_i915_private
*dev_priv
);
318 void (*hpd_irq_setup
)(struct drm_i915_private
*dev_priv
);
319 /* clock updates for mode set */
321 /* render clock increase/decrease */
322 /* display clock increase/decrease */
323 /* pll clock increase/decrease */
325 void (*load_csc_matrix
)(struct drm_crtc_state
*crtc_state
);
326 void (*load_luts
)(struct drm_crtc_state
*crtc_state
);
329 #define CSR_VERSION(major, minor) ((major) << 16 | (minor))
330 #define CSR_VERSION_MAJOR(version) ((version) >> 16)
331 #define CSR_VERSION_MINOR(version) ((version) & 0xffff)
334 struct work_struct work
;
336 uint32_t required_version
;
337 uint32_t max_fw_size
; /* bytes */
338 uint32_t *dmc_payload
;
339 uint32_t dmc_fw_size
; /* dwords */
342 i915_reg_t mmioaddr
[8];
343 uint32_t mmiodata
[8];
345 uint32_t allowed_dc_mask
;
348 enum i915_cache_level
{
350 I915_CACHE_LLC
, /* also used for snoopable memory on non-LLC */
351 I915_CACHE_L3_LLC
, /* gen7+, L3 sits between the domain specifc
352 caches, eg sampler/render caches, and the
353 large Last-Level-Cache. LLC is coherent with
354 the CPU, but L3 is only visible to the GPU. */
355 I915_CACHE_WT
, /* hsw:gt3e WriteThrough for scanouts */
358 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
369 /* This is always the inner lock when overlapping with struct_mutex and
370 * it's the outer lock when overlapping with stolen_lock. */
373 unsigned int possible_framebuffer_bits
;
374 unsigned int busy_bits
;
375 unsigned int visible_pipes_mask
;
376 struct intel_crtc
*crtc
;
378 struct drm_mm_node compressed_fb
;
379 struct drm_mm_node
*compressed_llb
;
387 bool underrun_detected
;
388 struct work_struct underrun_work
;
391 * Due to the atomic rules we can't access some structures without the
392 * appropriate locking, so we cache information here in order to avoid
395 struct intel_fbc_state_cache
{
396 struct i915_vma
*vma
;
400 unsigned int mode_flags
;
401 uint32_t hsw_bdw_pixel_rate
;
405 unsigned int rotation
;
410 * Display surface base address adjustement for
411 * pageflips. Note that on gen4+ this only adjusts up
412 * to a tile, offsets within a tile are handled in
413 * the hw itself (with the TILEOFF register).
420 uint16_t pixel_blend_mode
;
424 const struct drm_format_info
*format
;
430 * This structure contains everything that's relevant to program the
431 * hardware registers. When we want to figure out if we need to disable
432 * and re-enable FBC for a new configuration we just check if there's
433 * something different in the struct. The genx_fbc_activate functions
434 * are supposed to read from it in order to program the registers.
436 struct intel_fbc_reg_params
{
437 struct i915_vma
*vma
;
442 enum i9xx_plane_id i9xx_plane
;
443 unsigned int fence_y_offset
;
447 const struct drm_format_info
*format
;
452 unsigned int gen9_wa_cfb_stride
;
455 const char *no_fbc_reason
;
459 * HIGH_RR is the highest eDP panel refresh rate read from EDID
460 * LOW_RR is the lowest eDP panel refresh rate found from EDID
461 * parsing for same resolution.
463 enum drrs_refresh_rate_type
{
466 DRRS_MAX_RR
, /* RR count */
469 enum drrs_support_type
{
470 DRRS_NOT_SUPPORTED
= 0,
471 STATIC_DRRS_SUPPORT
= 1,
472 SEAMLESS_DRRS_SUPPORT
= 2
478 struct delayed_work work
;
480 unsigned busy_frontbuffer_bits
;
481 enum drrs_refresh_rate_type refresh_rate_type
;
482 enum drrs_support_type type
;
488 #define I915_PSR_DEBUG_MODE_MASK 0x0f
489 #define I915_PSR_DEBUG_DEFAULT 0x00
490 #define I915_PSR_DEBUG_DISABLE 0x01
491 #define I915_PSR_DEBUG_ENABLE 0x02
492 #define I915_PSR_DEBUG_FORCE_PSR1 0x03
493 #define I915_PSR_DEBUG_IRQ 0x10
497 bool prepared
, enabled
;
501 struct work_struct work
;
502 unsigned busy_frontbuffer_bits
;
503 bool sink_psr2_support
;
505 bool colorimetry_support
;
507 u8 sink_sync_latency
;
508 ktime_t last_entry_attempt
;
510 bool sink_not_reliable
;
515 PCH_NONE
= 0, /* No PCH present */
516 PCH_IBX
, /* Ibexpeak PCH */
517 PCH_CPT
, /* Cougarpoint/Pantherpoint PCH */
518 PCH_LPT
, /* Lynxpoint/Wildcatpoint PCH */
519 PCH_SPT
, /* Sunrisepoint PCH */
520 PCH_KBP
, /* Kaby Lake PCH */
521 PCH_CNP
, /* Cannon Lake PCH */
522 PCH_ICP
, /* Ice Lake PCH */
523 PCH_NOP
, /* PCH without south display */
526 enum intel_sbi_destination
{
531 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
532 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
533 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
534 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
535 #define QUIRK_INCREASE_T12_DELAY (1<<6)
536 #define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7)
539 struct intel_fbc_work
;
542 struct i2c_adapter adapter
;
543 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
547 struct i2c_algo_bit_data bit_algo
;
548 struct drm_i915_private
*dev_priv
;
551 struct i915_suspend_saved_registers
{
554 u32 saveCACHE_MODE_0
;
555 u32 saveMI_ARB_STATE
;
559 uint64_t saveFENCE
[I915_MAX_NUM_FENCES
];
560 u32 savePCH_PORT_HOTPLUG
;
564 struct vlv_s0ix_state
{
571 u32 lra_limits
[GEN7_LRA_LIMITS_REG_NUM
];
572 u32 media_max_req_count
;
573 u32 gfx_max_req_count
;
605 /* Display 1 CZ domain */
610 u32 gt_scratch
[GEN7_GT_SCRATCH_REG_NUM
];
612 /* GT SA CZ domain */
619 /* Display 2 CZ domain */
626 struct intel_rps_ei
{
634 * work, interrupts_enabled and pm_iir are protected by
637 struct work_struct work
;
638 bool interrupts_enabled
;
641 /* PM interrupt bits that should never be masked */
644 /* Frequencies are stored in potentially platform dependent multiples.
645 * In other words, *_freq needs to be multiplied by X to be interesting.
646 * Soft limits are those which are used for the dynamic reclocking done
647 * by the driver (raise frequencies under heavy loads, and lower for
648 * lighter loads). Hard limits are those imposed by the hardware.
650 * A distinction is made for overclocking, which is never enabled by
651 * default, and is considered to be above the hard limit if it's
654 u8 cur_freq
; /* Current frequency (cached, may not == HW) */
655 u8 min_freq_softlimit
; /* Minimum frequency permitted by the driver */
656 u8 max_freq_softlimit
; /* Max frequency permitted by the driver */
657 u8 max_freq
; /* Maximum frequency, RP0 if not overclocking */
658 u8 min_freq
; /* AKA RPn. Minimum frequency */
659 u8 boost_freq
; /* Frequency to request when wait boosting */
660 u8 idle_freq
; /* Frequency to request when we are idle */
661 u8 efficient_freq
; /* AKA RPe. Pre-determined balanced frequency */
662 u8 rp1_freq
; /* "less than" RP0 power/freqency */
663 u8 rp0_freq
; /* Non-overclocked max frequency. */
664 u16 gpll_ref_freq
; /* vlv/chv GPLL reference frequency */
671 enum { LOW_POWER
, BETWEEN
, HIGH_POWER
} mode
;
672 unsigned int interactive
;
674 u8 up_threshold
; /* Current %busy required to uplock */
675 u8 down_threshold
; /* Current %busy required to downclock */
679 atomic_t num_waiters
;
682 /* manual wa residency calculations */
683 struct intel_rps_ei ei
;
688 u64 prev_hw_residency
[4];
689 u64 cur_residency
[4];
692 struct intel_llc_pstate
{
696 struct intel_gen6_power_mgmt
{
697 struct intel_rps rps
;
698 struct intel_rc6 rc6
;
699 struct intel_llc_pstate llc_pstate
;
702 /* defined intel_pm.c */
703 extern spinlock_t mchdev_lock
;
705 struct intel_ilk_power_mgmt
{
713 unsigned long last_time1
;
714 unsigned long chipset_power
;
717 unsigned long gfx_power
;
724 struct drm_i915_private
;
725 struct i915_power_well
;
727 struct i915_power_well_ops
{
729 * Synchronize the well's hw state to match the current sw state, for
730 * example enable/disable it based on the current refcount. Called
731 * during driver init and resume time, possibly after first calling
732 * the enable/disable handlers.
734 void (*sync_hw
)(struct drm_i915_private
*dev_priv
,
735 struct i915_power_well
*power_well
);
737 * Enable the well and resources that depend on it (for example
738 * interrupts located on the well). Called after the 0->1 refcount
741 void (*enable
)(struct drm_i915_private
*dev_priv
,
742 struct i915_power_well
*power_well
);
744 * Disable the well and resources that depend on it. Called after
745 * the 1->0 refcount transition.
747 void (*disable
)(struct drm_i915_private
*dev_priv
,
748 struct i915_power_well
*power_well
);
749 /* Returns the hw enabled state. */
750 bool (*is_enabled
)(struct drm_i915_private
*dev_priv
,
751 struct i915_power_well
*power_well
);
754 struct i915_power_well_regs
{
761 /* Power well structure for haswell */
762 struct i915_power_well_desc
{
766 /* unique identifier for this power well */
767 enum i915_power_well_id id
;
769 * Arbitraty data associated with this power well. Platform and power
775 * request/status flag index in the PUNIT power well
776 * control/status registers.
784 const struct i915_power_well_regs
*regs
;
786 * request/status flag index in the power well
787 * constrol/status registers.
790 /* Mask of pipes whose IRQ logic is backed by the pw */
792 /* The pw is backing the VGA functionality */
796 * The pw is for an ICL+ TypeC PHY port in
802 const struct i915_power_well_ops
*ops
;
805 struct i915_power_well
{
806 const struct i915_power_well_desc
*desc
;
807 /* power well enable/disable usage count */
809 /* cached hw enabled state */
813 struct i915_power_domains
{
815 * Power wells needed for initialization at driver init and suspend
816 * time are on. They are kept on until after the first modeset.
819 bool display_core_suspended
;
820 int power_well_count
;
823 int domain_use_count
[POWER_DOMAIN_NUM
];
824 struct i915_power_well
*power_wells
;
827 #define MAX_L3_SLICES 2
828 struct intel_l3_parity
{
829 u32
*remap_info
[MAX_L3_SLICES
];
830 struct work_struct error_work
;
835 /** Memory allocator for GTT stolen memory */
836 struct drm_mm stolen
;
837 /** Protects the usage of the GTT stolen memory allocator. This is
838 * always the inner lock when overlapping with struct_mutex. */
839 struct mutex stolen_lock
;
841 /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */
844 /** List of all objects in gtt_space. Used to restore gtt
845 * mappings on resume */
846 struct list_head bound_list
;
848 * List of objects which are not bound to the GTT (thus
849 * are idle and not used by the GPU). These objects may or may
850 * not actually have any pages attached.
852 struct list_head unbound_list
;
854 /** List of all objects in gtt_space, currently mmaped by userspace.
855 * All objects within this list must also be on bound_list.
857 struct list_head userfault_list
;
860 * List of objects which are pending destruction.
862 struct llist_head free_list
;
863 struct work_struct free_work
;
864 spinlock_t free_lock
;
866 * Count of objects pending destructions. Used to skip needlessly
867 * waiting on an RCU barrier if no objects are waiting to be freed.
872 * Small stash of WC pages
874 struct pagestash wc_stash
;
877 * tmpfs instance used for shmem backed objects
879 struct vfsmount
*gemfs
;
881 /** PPGTT used for aliasing the PPGTT with the GTT */
882 struct i915_hw_ppgtt
*aliasing_ppgtt
;
884 struct notifier_block oom_notifier
;
885 struct notifier_block vmap_notifier
;
886 struct shrinker shrinker
;
888 /** LRU list of objects with fence regs on them. */
889 struct list_head fence_list
;
892 * Workqueue to fault in userptr pages, flushed by the execbuf
893 * when required but otherwise left to userspace to try again
896 struct workqueue_struct
*userptr_wq
;
898 u64 unordered_timeline
;
900 /* the indicator for dispatch video commands on two BSD rings */
901 atomic_t bsd_engine_dispatch_index
;
903 /** Bit 6 swizzling required for X tiling */
904 uint32_t bit_6_swizzle_x
;
905 /** Bit 6 swizzling required for Y tiling */
906 uint32_t bit_6_swizzle_y
;
908 /* accounting, useful for userland debugging */
909 spinlock_t object_stat_lock
;
914 #define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */
916 #define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
917 #define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */
919 #define I915_ENGINE_DEAD_TIMEOUT (4 * HZ) /* Seqno, head and subunits dead */
920 #define I915_SEQNO_DEAD_TIMEOUT (12 * HZ) /* Seqno dead with active head */
922 #define I915_ENGINE_WEDGED_TIMEOUT (60 * HZ) /* Reset but no recovery? */
924 struct ddi_vbt_port_info
{
928 * This is an index in the HDMI/DVI DDI buffer translation table.
929 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
930 * populate this field.
932 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
933 uint8_t hdmi_level_shift
;
935 uint8_t supports_dvi
:1;
936 uint8_t supports_hdmi
:1;
937 uint8_t supports_dp
:1;
938 uint8_t supports_edp
:1;
940 uint8_t alternate_aux_channel
;
941 uint8_t alternate_ddc_pin
;
943 uint8_t dp_boost_level
;
944 uint8_t hdmi_boost_level
;
945 int dp_max_link_rate
; /* 0 for not limited by VBT */
948 enum psr_lines_to_wait
{
949 PSR_0_LINES_TO_WAIT
= 0,
955 struct intel_vbt_data
{
956 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
957 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
960 unsigned int int_tv_support
:1;
961 unsigned int lvds_dither
:1;
962 unsigned int int_crt_support
:1;
963 unsigned int lvds_use_ssc
:1;
964 unsigned int int_lvds_support
:1;
965 unsigned int display_clock_mode
:1;
966 unsigned int fdi_rx_polarity_inverted
:1;
967 unsigned int panel_type
:4;
969 unsigned int bios_lvds_val
; /* initial [PCH_]LVDS reg val in VBIOS */
970 enum drm_panel_orientation orientation
;
972 enum drrs_support_type drrs_type
;
982 struct edp_power_seq pps
;
988 bool require_aux_wakeup
;
990 enum psr_lines_to_wait lines_to_wait
;
991 int tp1_wakeup_time_us
;
992 int tp2_tp3_wakeup_time_us
;
999 u8 min_brightness
; /* min_brightness/255 of max */
1000 u8 controller
; /* brightness controller number */
1001 enum intel_backlight_type type
;
1007 struct mipi_config
*config
;
1008 struct mipi_pps_data
*pps
;
1014 const u8
*sequence
[MIPI_SEQ_MAX
];
1015 u8
*deassert_seq
; /* Used by fixup_mipi_sequences() */
1016 enum drm_panel_orientation orientation
;
1022 struct child_device_config
*child_dev
;
1024 struct ddi_vbt_port_info ddi_port_info
[I915_MAX_PORTS
];
1025 struct sdvo_device_mapping sdvo_mappings
[2];
1028 enum intel_ddb_partitioning
{
1030 INTEL_DDB_PART_5_6
, /* IVB+ */
1033 struct intel_wm_level
{
1041 struct ilk_wm_values
{
1042 uint32_t wm_pipe
[3];
1044 uint32_t wm_lp_spr
[3];
1045 uint32_t wm_linetime
[3];
1047 enum intel_ddb_partitioning partitioning
;
1050 struct g4x_pipe_wm
{
1051 uint16_t plane
[I915_MAX_PLANES
];
1061 struct vlv_wm_ddl_values
{
1062 uint8_t plane
[I915_MAX_PLANES
];
1065 struct vlv_wm_values
{
1066 struct g4x_pipe_wm pipe
[3];
1067 struct g4x_sr_wm sr
;
1068 struct vlv_wm_ddl_values ddl
[3];
1073 struct g4x_wm_values
{
1074 struct g4x_pipe_wm pipe
[2];
1075 struct g4x_sr_wm sr
;
1076 struct g4x_sr_wm hpll
;
1082 struct skl_ddb_entry
{
1083 uint16_t start
, end
; /* in number of blocks, 'end' is exclusive */
1086 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry
*entry
)
1088 return entry
->end
- entry
->start
;
1091 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry
*e1
,
1092 const struct skl_ddb_entry
*e2
)
1094 if (e1
->start
== e2
->start
&& e1
->end
== e2
->end
)
1100 struct skl_ddb_allocation
{
1101 u8 enabled_slices
; /* GEN11 has configurable 2 slices */
1104 struct skl_ddb_values
{
1105 unsigned dirty_pipes
;
1106 struct skl_ddb_allocation ddb
;
1109 struct skl_wm_level
{
1110 uint16_t plane_res_b
;
1111 uint8_t plane_res_l
;
1115 /* Stores plane specific WM parameters */
1116 struct skl_wm_params
{
1117 bool x_tiled
, y_tiled
;
1122 uint32_t plane_pixel_rate
;
1123 uint32_t y_min_scanlines
;
1124 uint32_t plane_bytes_per_line
;
1125 uint_fixed_16_16_t plane_blocks_per_line
;
1126 uint_fixed_16_16_t y_tile_minimum
;
1127 uint32_t linetime_us
;
1128 uint32_t dbuf_block_size
;
1132 * This struct helps tracking the state needed for runtime PM, which puts the
1133 * device in PCI D3 state. Notice that when this happens, nothing on the
1134 * graphics device works, even register access, so we don't get interrupts nor
1137 * Every piece of our code that needs to actually touch the hardware needs to
1138 * either call intel_runtime_pm_get or call intel_display_power_get with the
1139 * appropriate power domain.
1141 * Our driver uses the autosuspend delay feature, which means we'll only really
1142 * suspend if we stay with zero refcount for a certain amount of time. The
1143 * default value is currently very conservative (see intel_runtime_pm_enable), but
1144 * it can be changed with the standard runtime PM files from sysfs.
1146 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1147 * goes back to false exactly before we reenable the IRQs. We use this variable
1148 * to check if someone is trying to enable/disable IRQs while they're supposed
1149 * to be disabled. This shouldn't happen and we'll print some error messages in
1152 * For more, read the Documentation/power/runtime_pm.txt.
1154 struct i915_runtime_pm
{
1155 atomic_t wakeref_count
;
1160 enum intel_pipe_crc_source
{
1161 INTEL_PIPE_CRC_SOURCE_NONE
,
1162 INTEL_PIPE_CRC_SOURCE_PLANE1
,
1163 INTEL_PIPE_CRC_SOURCE_PLANE2
,
1164 INTEL_PIPE_CRC_SOURCE_PF
,
1165 INTEL_PIPE_CRC_SOURCE_PIPE
,
1166 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1167 INTEL_PIPE_CRC_SOURCE_TV
,
1168 INTEL_PIPE_CRC_SOURCE_DP_B
,
1169 INTEL_PIPE_CRC_SOURCE_DP_C
,
1170 INTEL_PIPE_CRC_SOURCE_DP_D
,
1171 INTEL_PIPE_CRC_SOURCE_AUTO
,
1172 INTEL_PIPE_CRC_SOURCE_MAX
,
1175 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1176 struct intel_pipe_crc
{
1179 enum intel_pipe_crc_source source
;
1182 struct i915_frontbuffer_tracking
{
1186 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1193 struct i915_virtual_gpu
{
1198 /* used in computing the new watermarks state */
1199 struct intel_wm_config
{
1200 unsigned int num_pipes_active
;
1201 bool sprites_enabled
;
1202 bool sprites_scaled
;
1205 struct i915_oa_format
{
1210 struct i915_oa_reg
{
1215 struct i915_oa_config
{
1216 char uuid
[UUID_STRING_LEN
+ 1];
1219 const struct i915_oa_reg
*mux_regs
;
1221 const struct i915_oa_reg
*b_counter_regs
;
1222 u32 b_counter_regs_len
;
1223 const struct i915_oa_reg
*flex_regs
;
1226 struct attribute_group sysfs_metric
;
1227 struct attribute
*attrs
[2];
1228 struct device_attribute sysfs_metric_id
;
1233 struct i915_perf_stream
;
1236 * struct i915_perf_stream_ops - the OPs to support a specific stream type
1238 struct i915_perf_stream_ops
{
1240 * @enable: Enables the collection of HW samples, either in response to
1241 * `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is opened
1242 * without `I915_PERF_FLAG_DISABLED`.
1244 void (*enable
)(struct i915_perf_stream
*stream
);
1247 * @disable: Disables the collection of HW samples, either in response
1248 * to `I915_PERF_IOCTL_DISABLE` or implicitly called before destroying
1251 void (*disable
)(struct i915_perf_stream
*stream
);
1254 * @poll_wait: Call poll_wait, passing a wait queue that will be woken
1255 * once there is something ready to read() for the stream
1257 void (*poll_wait
)(struct i915_perf_stream
*stream
,
1262 * @wait_unlocked: For handling a blocking read, wait until there is
1263 * something to ready to read() for the stream. E.g. wait on the same
1264 * wait queue that would be passed to poll_wait().
1266 int (*wait_unlocked
)(struct i915_perf_stream
*stream
);
1269 * @read: Copy buffered metrics as records to userspace
1270 * **buf**: the userspace, destination buffer
1271 * **count**: the number of bytes to copy, requested by userspace
1272 * **offset**: zero at the start of the read, updated as the read
1273 * proceeds, it represents how many bytes have been copied so far and
1274 * the buffer offset for copying the next record.
1276 * Copy as many buffered i915 perf samples and records for this stream
1277 * to userspace as will fit in the given buffer.
1279 * Only write complete records; returning -%ENOSPC if there isn't room
1280 * for a complete record.
1282 * Return any error condition that results in a short read such as
1283 * -%ENOSPC or -%EFAULT, even though these may be squashed before
1284 * returning to userspace.
1286 int (*read
)(struct i915_perf_stream
*stream
,
1292 * @destroy: Cleanup any stream specific resources.
1294 * The stream will always be disabled before this is called.
1296 void (*destroy
)(struct i915_perf_stream
*stream
);
1300 * struct i915_perf_stream - state for a single open stream FD
1302 struct i915_perf_stream
{
1304 * @dev_priv: i915 drm device
1306 struct drm_i915_private
*dev_priv
;
1309 * @link: Links the stream into ``&drm_i915_private->streams``
1311 struct list_head link
;
1314 * @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
1315 * properties given when opening a stream, representing the contents
1316 * of a single sample as read() by userspace.
1321 * @sample_size: Considering the configured contents of a sample
1322 * combined with the required header size, this is the total size
1323 * of a single sample record.
1328 * @ctx: %NULL if measuring system-wide across all contexts or a
1329 * specific context that is being monitored.
1331 struct i915_gem_context
*ctx
;
1334 * @enabled: Whether the stream is currently enabled, considering
1335 * whether the stream was opened in a disabled state and based
1336 * on `I915_PERF_IOCTL_ENABLE` and `I915_PERF_IOCTL_DISABLE` calls.
1341 * @ops: The callbacks providing the implementation of this specific
1342 * type of configured stream.
1344 const struct i915_perf_stream_ops
*ops
;
1347 * @oa_config: The OA configuration used by the stream.
1349 struct i915_oa_config
*oa_config
;
1353 * struct i915_oa_ops - Gen specific implementation of an OA unit stream
1355 struct i915_oa_ops
{
1357 * @is_valid_b_counter_reg: Validates register's address for
1358 * programming boolean counters for a particular platform.
1360 bool (*is_valid_b_counter_reg
)(struct drm_i915_private
*dev_priv
,
1364 * @is_valid_mux_reg: Validates register's address for programming mux
1365 * for a particular platform.
1367 bool (*is_valid_mux_reg
)(struct drm_i915_private
*dev_priv
, u32 addr
);
1370 * @is_valid_flex_reg: Validates register's address for programming
1371 * flex EU filtering for a particular platform.
1373 bool (*is_valid_flex_reg
)(struct drm_i915_private
*dev_priv
, u32 addr
);
1376 * @enable_metric_set: Selects and applies any MUX configuration to set
1377 * up the Boolean and Custom (B/C) counters that are part of the
1378 * counter reports being sampled. May apply system constraints such as
1379 * disabling EU clock gating as required.
1381 int (*enable_metric_set
)(struct i915_perf_stream
*stream
);
1384 * @disable_metric_set: Remove system constraints associated with using
1387 void (*disable_metric_set
)(struct drm_i915_private
*dev_priv
);
1390 * @oa_enable: Enable periodic sampling
1392 void (*oa_enable
)(struct i915_perf_stream
*stream
);
1395 * @oa_disable: Disable periodic sampling
1397 void (*oa_disable
)(struct i915_perf_stream
*stream
);
1400 * @read: Copy data from the circular OA buffer into a given userspace
1403 int (*read
)(struct i915_perf_stream
*stream
,
1409 * @oa_hw_tail_read: read the OA tail pointer register
1411 * In particular this enables us to share all the fiddly code for
1412 * handling the OA unit tail pointer race that affects multiple
1415 u32 (*oa_hw_tail_read
)(struct drm_i915_private
*dev_priv
);
1418 struct intel_cdclk_state
{
1419 unsigned int cdclk
, vco
, ref
, bypass
;
1423 struct drm_i915_private
{
1424 struct drm_device drm
;
1426 struct kmem_cache
*objects
;
1427 struct kmem_cache
*vmas
;
1428 struct kmem_cache
*luts
;
1429 struct kmem_cache
*requests
;
1430 struct kmem_cache
*dependencies
;
1431 struct kmem_cache
*priorities
;
1433 const struct intel_device_info info
;
1434 struct intel_driver_caps caps
;
1437 * Data Stolen Memory - aka "i915 stolen memory" gives us the start and
1438 * end of stolen which we can optionally use to create GEM objects
1439 * backed by stolen memory. Note that stolen_usable_size tells us
1440 * exactly how much of this we are actually allowed to use, given that
1441 * some portion of it is in fact reserved for use by hardware functions.
1443 struct resource dsm
;
1445 * Reseved portion of Data Stolen Memory
1447 struct resource dsm_reserved
;
1450 * Stolen memory is segmented in hardware with different portions
1451 * offlimits to certain functions.
1453 * The drm_mm is initialised to the total accessible range, as found
1454 * from the PCI config. On Broadwell+, this is further restricted to
1455 * avoid the first page! The upper end of stolen memory is reserved for
1456 * hardware functions and similarly removed from the accessible range.
1458 resource_size_t stolen_usable_size
; /* Total size minus reserved ranges */
1462 struct intel_uncore uncore
;
1464 struct i915_virtual_gpu vgpu
;
1466 struct intel_gvt
*gvt
;
1468 struct intel_wopcm wopcm
;
1470 struct intel_huc huc
;
1471 struct intel_guc guc
;
1473 struct intel_csr csr
;
1475 struct intel_gmbus gmbus
[GMBUS_NUM_PINS
];
1477 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1478 * controller on different i2c buses. */
1479 struct mutex gmbus_mutex
;
1482 * Base address of where the gmbus and gpio blocks are located (either
1483 * on PCH or on SoC for platforms without PCH).
1485 uint32_t gpio_mmio_base
;
1487 /* MMIO base address for MIPI regs */
1488 uint32_t mipi_mmio_base
;
1490 uint32_t psr_mmio_base
;
1492 uint32_t pps_mmio_base
;
1494 wait_queue_head_t gmbus_wait_queue
;
1496 struct pci_dev
*bridge_dev
;
1497 struct intel_engine_cs
*engine
[I915_NUM_ENGINES
];
1498 /* Context used internally to idle the GPU and setup initial state */
1499 struct i915_gem_context
*kernel_context
;
1500 /* Context only to be used for injecting preemption commands */
1501 struct i915_gem_context
*preempt_context
;
1502 struct intel_engine_cs
*engine_class
[MAX_ENGINE_CLASS
+ 1]
1503 [MAX_ENGINE_INSTANCE
+ 1];
1505 struct resource mch_res
;
1507 /* protects the irq masks */
1508 spinlock_t irq_lock
;
1510 bool display_irqs_enabled
;
1512 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1513 struct pm_qos_request pm_qos
;
1515 /* Sideband mailbox protection */
1516 struct mutex sb_lock
;
1518 /** Cached value of IMR to avoid reads in updating the bitfield */
1521 u32 de_irq_mask
[I915_MAX_PIPES
];
1528 u32 pipestat_irq_mask
[I915_MAX_PIPES
];
1530 struct i915_hotplug hotplug
;
1531 struct intel_fbc fbc
;
1532 struct i915_drrs drrs
;
1533 struct intel_opregion opregion
;
1534 struct intel_vbt_data vbt
;
1536 bool preserve_bios_swizzle
;
1539 struct intel_overlay
*overlay
;
1541 /* backlight registers and fields in struct intel_panel */
1542 struct mutex backlight_lock
;
1545 bool no_aux_handshake
;
1547 /* protects panel power sequencer state */
1548 struct mutex pps_mutex
;
1550 struct drm_i915_fence_reg fence_regs
[I915_MAX_NUM_FENCES
]; /* assume 965 */
1551 int num_fence_regs
; /* 8 on pre-965, 16 otherwise */
1553 unsigned int fsb_freq
, mem_freq
, is_ddr3
;
1554 unsigned int skl_preferred_vco_freq
;
1555 unsigned int max_cdclk_freq
;
1557 unsigned int max_dotclk_freq
;
1558 unsigned int rawclk_freq
;
1559 unsigned int hpll_freq
;
1560 unsigned int fdi_pll_freq
;
1561 unsigned int czclk_freq
;
1565 * The current logical cdclk state.
1566 * See intel_atomic_state.cdclk.logical
1568 * For reading holding any crtc lock is sufficient,
1569 * for writing must hold all of them.
1571 struct intel_cdclk_state logical
;
1573 * The current actual cdclk state.
1574 * See intel_atomic_state.cdclk.actual
1576 struct intel_cdclk_state actual
;
1577 /* The current hardware cdclk state */
1578 struct intel_cdclk_state hw
;
1582 * wq - Driver workqueue for GEM.
1584 * NOTE: Work items scheduled here are not allowed to grab any modeset
1585 * locks, for otherwise the flushing done in the pageflip code will
1586 * result in deadlocks.
1588 struct workqueue_struct
*wq
;
1590 /* ordered wq for modesets */
1591 struct workqueue_struct
*modeset_wq
;
1593 /* Display functions */
1594 struct drm_i915_display_funcs display
;
1596 /* PCH chipset type */
1597 enum intel_pch pch_type
;
1598 unsigned short pch_id
;
1600 unsigned long quirks
;
1602 struct drm_atomic_state
*modeset_restore_state
;
1603 struct drm_modeset_acquire_ctx reset_ctx
;
1605 struct i915_ggtt ggtt
; /* VM representing the global address space */
1607 struct i915_gem_mm mm
;
1608 DECLARE_HASHTABLE(mm_structs
, 7);
1609 struct mutex mm_lock
;
1611 struct intel_ppat ppat
;
1613 /* Kernel Modesetting */
1615 struct intel_crtc
*plane_to_crtc_mapping
[I915_MAX_PIPES
];
1616 struct intel_crtc
*pipe_to_crtc_mapping
[I915_MAX_PIPES
];
1618 #ifdef CONFIG_DEBUG_FS
1619 struct intel_pipe_crc pipe_crc
[I915_MAX_PIPES
];
1622 /* dpll and cdclk state is protected by connection_mutex */
1623 int num_shared_dpll
;
1624 struct intel_shared_dpll shared_dplls
[I915_NUM_PLLS
];
1625 const struct intel_dpll_mgr
*dpll_mgr
;
1628 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
1629 * Must be global rather than per dpll, because on some platforms
1630 * plls share registers.
1632 struct mutex dpll_lock
;
1634 unsigned int active_crtcs
;
1635 /* minimum acceptable cdclk for each pipe */
1636 int min_cdclk
[I915_MAX_PIPES
];
1637 /* minimum acceptable voltage level for each pipe */
1638 u8 min_voltage_level
[I915_MAX_PIPES
];
1640 int dpio_phy_iosf_port
[I915_NUM_PHYS_VLV
];
1642 struct i915_wa_list gt_wa_list
;
1644 struct i915_frontbuffer_tracking fb_tracking
;
1646 struct intel_atomic_helper
{
1647 struct llist_head free_list
;
1648 struct work_struct free_work
;
1653 bool mchbar_need_disable
;
1655 struct intel_l3_parity l3_parity
;
1657 /* Cannot be determined by PCIID. You must always read a register. */
1661 * Protects RPS/RC6 register access and PCU communication.
1662 * Must be taken after struct_mutex if nested. Note that
1663 * this lock may be held for long periods of time when
1664 * talking to hw - so only take it when talking to hw!
1666 struct mutex pcu_lock
;
1668 /* gen6+ GT PM state */
1669 struct intel_gen6_power_mgmt gt_pm
;
1671 /* ilk-only ips/rps state. Everything in here is protected by the global
1672 * mchdev_lock in intel_pm.c */
1673 struct intel_ilk_power_mgmt ips
;
1675 struct i915_power_domains power_domains
;
1677 struct i915_psr psr
;
1679 struct i915_gpu_error gpu_error
;
1681 struct drm_i915_gem_object
*vlv_pctx
;
1683 /* list of fbdev register on this device */
1684 struct intel_fbdev
*fbdev
;
1685 struct work_struct fbdev_suspend_work
;
1687 struct drm_property
*broadcast_rgb_property
;
1688 struct drm_property
*force_audio_property
;
1690 /* hda/i915 audio component */
1691 struct i915_audio_component
*audio_component
;
1692 bool audio_component_registered
;
1694 * av_mutex - mutex for audio/video sync
1697 struct mutex av_mutex
;
1701 struct list_head list
;
1702 struct llist_head free_list
;
1703 struct work_struct free_work
;
1705 /* The hw wants to have a stable context identifier for the
1706 * lifetime of the context (for OA, PASID, faults, etc).
1707 * This is limited in execlists to 21 bits.
1710 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
1711 #define MAX_GUC_CONTEXT_HW_ID (1 << 20) /* exclusive */
1712 #define GEN11_MAX_CONTEXT_HW_ID (1<<11) /* exclusive */
1713 struct list_head hw_id_list
;
1718 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
1719 u32 chv_phy_control
;
1721 * Shadows for CHV DPLL_MD regs to keep the state
1722 * checker somewhat working in the presence hardware
1723 * crappiness (can't read out DPLL_MD for pipes B & C).
1725 u32 chv_dpll_md
[I915_MAX_PIPES
];
1729 bool power_domains_suspended
;
1730 struct i915_suspend_saved_registers regfile
;
1731 struct vlv_s0ix_state vlv_s0ix_state
;
1734 I915_SAGV_UNKNOWN
= 0,
1737 I915_SAGV_NOT_CONTROLLED
1742 * Raw watermark latency values:
1743 * in 0.1us units for WM0,
1744 * in 0.5us units for WM1+.
1747 uint16_t pri_latency
[5];
1749 uint16_t spr_latency
[5];
1751 uint16_t cur_latency
[5];
1753 * Raw watermark memory latency values
1754 * for SKL for all 8 levels
1757 uint16_t skl_latency
[8];
1759 /* current hardware state */
1761 struct ilk_wm_values hw
;
1762 struct skl_ddb_values skl_hw
;
1763 struct vlv_wm_values vlv
;
1764 struct g4x_wm_values g4x
;
1770 * Should be held around atomic WM register writing; also
1771 * protects * intel_crtc->wm.active and
1772 * cstate->wm.need_postvbl_update.
1774 struct mutex wm_mutex
;
1777 * Set during HW readout of watermarks/DDB. Some platforms
1778 * need to know when we're still using BIOS-provided values
1779 * (which we don't fully trust).
1781 bool distrust_bios_wm
;
1789 I915_DRAM_RANK_INVALID
= 0,
1790 I915_DRAM_RANK_SINGLE
,
1794 bool symmetric_memory
;
1797 struct i915_runtime_pm runtime_pm
;
1802 struct kobject
*metrics_kobj
;
1803 struct ctl_table_header
*sysctl_header
;
1806 * Lock associated with adding/modifying/removing OA configs
1807 * in dev_priv->perf.metrics_idr.
1809 struct mutex metrics_lock
;
1812 * List of dynamic configurations, you need to hold
1813 * dev_priv->perf.metrics_lock to access it.
1815 struct idr metrics_idr
;
1818 * Lock associated with anything below within this structure
1819 * except exclusive_stream.
1822 struct list_head streams
;
1826 * The stream currently using the OA unit. If accessed
1827 * outside a syscall associated to its file
1828 * descriptor, you need to hold
1829 * dev_priv->drm.struct_mutex.
1831 struct i915_perf_stream
*exclusive_stream
;
1833 struct intel_context
*pinned_ctx
;
1834 u32 specific_ctx_id
;
1835 u32 specific_ctx_id_mask
;
1837 struct hrtimer poll_check_timer
;
1838 wait_queue_head_t poll_wq
;
1842 * For rate limiting any notifications of spurious
1843 * invalid OA reports
1845 struct ratelimit_state spurious_report_rs
;
1848 int period_exponent
;
1850 struct i915_oa_config test_config
;
1853 struct i915_vma
*vma
;
1860 * Locks reads and writes to all head/tail state
1862 * Consider: the head and tail pointer state
1863 * needs to be read consistently from a hrtimer
1864 * callback (atomic context) and read() fop
1865 * (user context) with tail pointer updates
1866 * happening in atomic context and head updates
1867 * in user context and the (unlikely)
1868 * possibility of read() errors needing to
1869 * reset all head/tail state.
1871 * Note: Contention or performance aren't
1872 * currently a significant concern here
1873 * considering the relatively low frequency of
1874 * hrtimer callbacks (5ms period) and that
1875 * reads typically only happen in response to a
1876 * hrtimer event and likely complete before the
1879 * Note: This lock is not held *while* reading
1880 * and copying data to userspace so the value
1881 * of head observed in htrimer callbacks won't
1882 * represent any partial consumption of data.
1884 spinlock_t ptr_lock
;
1887 * One 'aging' tail pointer and one 'aged'
1888 * tail pointer ready to used for reading.
1890 * Initial values of 0xffffffff are invalid
1891 * and imply that an update is required
1892 * (and should be ignored by an attempted
1900 * Index for the aged tail ready to read()
1903 unsigned int aged_tail_idx
;
1906 * A monotonic timestamp for when the current
1907 * aging tail pointer was read; used to
1908 * determine when it is old enough to trust.
1910 u64 aging_timestamp
;
1913 * Although we can always read back the head
1914 * pointer register, we prefer to avoid
1915 * trusting the HW state, just to avoid any
1916 * risk that some hardware condition could
1917 * somehow bump the head pointer unpredictably
1918 * and cause us to forward the wrong OA buffer
1919 * data to userspace.
1924 u32 gen7_latched_oastatus1
;
1925 u32 ctx_oactxctrl_offset
;
1926 u32 ctx_flexeu0_offset
;
1929 * The RPT_ID/reason field for Gen8+ includes a bit
1930 * to determine if the CTX ID in the report is valid
1931 * but the specific bit differs between Gen 8 and 9
1933 u32 gen8_valid_ctx_bit
;
1935 struct i915_oa_ops ops
;
1936 const struct i915_oa_format
*oa_formats
;
1940 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1942 void (*resume
)(struct drm_i915_private
*);
1943 void (*cleanup_engine
)(struct intel_engine_cs
*engine
);
1945 struct list_head timelines
;
1947 struct list_head active_rings
;
1948 struct list_head closed_vma
;
1949 u32 active_requests
;
1953 * Is the GPU currently considered idle, or busy executing
1954 * userspace requests? Whilst idle, we allow runtime power
1955 * management to power down the hardware and display clocks.
1956 * In order to reduce the effect on performance, there
1957 * is a slight delay before we do so.
1962 * The number of times we have woken up.
1965 #define I915_EPOCH_INVALID 0
1968 * We leave the user IRQ off as much as possible,
1969 * but this means that requests will finish and never
1970 * be retired once the system goes idle. Set a timer to
1971 * fire periodically while the ring is running. When it
1972 * fires, go retire requests.
1974 struct delayed_work retire_work
;
1977 * When we detect an idle GPU, we want to turn on
1978 * powersaving features. So once we see that there
1979 * are no more requests outstanding and no more
1980 * arrive within a small period of time, we fire
1981 * off the idle_work.
1983 struct delayed_work idle_work
;
1985 ktime_t last_init_time
;
1987 struct i915_vma
*scratch
;
1990 /* perform PHY state sanity checks? */
1991 bool chv_phy_assert
[2];
1995 /* Used to save the pipe-to-encoder mapping for audio */
1996 struct intel_encoder
*av_enc_map
[I915_MAX_PIPES
];
1998 /* necessary resource sharing with HDMI LPE audio driver. */
2000 struct platform_device
*platdev
;
2004 struct i915_pmu pmu
;
2007 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
2008 * will be rejected. Instead look for a better place.
2012 struct dram_channel_info
{
2015 enum dram_rank rank
;
2017 enum dram_rank rank
;
2021 static inline struct drm_i915_private
*to_i915(const struct drm_device
*dev
)
2023 return container_of(dev
, struct drm_i915_private
, drm
);
2026 static inline struct drm_i915_private
*kdev_to_i915(struct device
*kdev
)
2028 return to_i915(dev_get_drvdata(kdev
));
2031 static inline struct drm_i915_private
*wopcm_to_i915(struct intel_wopcm
*wopcm
)
2033 return container_of(wopcm
, struct drm_i915_private
, wopcm
);
2036 static inline struct drm_i915_private
*guc_to_i915(struct intel_guc
*guc
)
2038 return container_of(guc
, struct drm_i915_private
, guc
);
2041 static inline struct drm_i915_private
*huc_to_i915(struct intel_huc
*huc
)
2043 return container_of(huc
, struct drm_i915_private
, huc
);
2046 /* Simple iterator over all initialised engines */
2047 #define for_each_engine(engine__, dev_priv__, id__) \
2049 (id__) < I915_NUM_ENGINES; \
2051 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
2053 /* Iterator over subset of engines selected by mask */
2054 #define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
2055 for ((tmp__) = (mask__) & INTEL_INFO(dev_priv__)->ring_mask; \
2057 ((engine__) = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : \
2060 enum hdmi_force_audio
{
2061 HDMI_AUDIO_OFF_DVI
= -2, /* no aux data for HDMI-DVI converter */
2062 HDMI_AUDIO_OFF
, /* force turn off HDMI audio */
2063 HDMI_AUDIO_AUTO
, /* trust EDID */
2064 HDMI_AUDIO_ON
, /* force turn on HDMI audio */
2067 #define I915_GTT_OFFSET_NONE ((u32)-1)
2070 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2071 * considered to be the frontbuffer for the given plane interface-wise. This
2072 * doesn't mean that the hw necessarily already scans it out, but that any
2073 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2075 * We have one bit per pipe and per scanout plane type.
2077 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2078 #define INTEL_FRONTBUFFER(pipe, plane_id) ({ \
2079 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32); \
2080 BUILD_BUG_ON(I915_MAX_PLANES > INTEL_FRONTBUFFER_BITS_PER_PIPE); \
2081 BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)); \
2083 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2084 BIT(INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
2085 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2086 GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \
2087 INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
2090 * Optimised SGL iterator for GEM objects
2092 static __always_inline
struct sgt_iter
{
2093 struct scatterlist
*sgp
;
2100 } __sgt_iter(struct scatterlist
*sgl
, bool dma
) {
2101 struct sgt_iter s
= { .sgp
= sgl
};
2104 s
.max
= s
.curr
= s
.sgp
->offset
;
2105 s
.max
+= s
.sgp
->length
;
2107 s
.dma
= sg_dma_address(s
.sgp
);
2109 s
.pfn
= page_to_pfn(sg_page(s
.sgp
));
2115 static inline struct scatterlist
*____sg_next(struct scatterlist
*sg
)
2118 if (unlikely(sg_is_chain(sg
)))
2119 sg
= sg_chain_ptr(sg
);
2124 * __sg_next - return the next scatterlist entry in a list
2125 * @sg: The current sg entry
2128 * If the entry is the last, return NULL; otherwise, step to the next
2129 * element in the array (@sg@+1). If that's a chain pointer, follow it;
2130 * otherwise just return the pointer to the current element.
2132 static inline struct scatterlist
*__sg_next(struct scatterlist
*sg
)
2134 return sg_is_last(sg
) ? NULL
: ____sg_next(sg
);
2138 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
2139 * @__dmap: DMA address (output)
2140 * @__iter: 'struct sgt_iter' (iterator state, internal)
2141 * @__sgt: sg_table to iterate over (input)
2143 #define for_each_sgt_dma(__dmap, __iter, __sgt) \
2144 for ((__iter) = __sgt_iter((__sgt)->sgl, true); \
2145 ((__dmap) = (__iter).dma + (__iter).curr); \
2146 (((__iter).curr += I915_GTT_PAGE_SIZE) >= (__iter).max) ? \
2147 (__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0 : 0)
2150 * for_each_sgt_page - iterate over the pages of the given sg_table
2151 * @__pp: page pointer (output)
2152 * @__iter: 'struct sgt_iter' (iterator state, internal)
2153 * @__sgt: sg_table to iterate over (input)
2155 #define for_each_sgt_page(__pp, __iter, __sgt) \
2156 for ((__iter) = __sgt_iter((__sgt)->sgl, false); \
2157 ((__pp) = (__iter).pfn == 0 ? NULL : \
2158 pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
2159 (((__iter).curr += PAGE_SIZE) >= (__iter).max) ? \
2160 (__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0 : 0)
2162 bool i915_sg_trim(struct sg_table
*orig_st
);
2164 static inline unsigned int i915_sg_page_sizes(struct scatterlist
*sg
)
2166 unsigned int page_sizes
;
2170 GEM_BUG_ON(sg
->offset
);
2171 GEM_BUG_ON(!IS_ALIGNED(sg
->length
, PAGE_SIZE
));
2172 page_sizes
|= sg
->length
;
2179 static inline unsigned int i915_sg_segment_size(void)
2181 unsigned int size
= swiotlb_max_segment();
2184 return SCATTERLIST_MAX_SEGMENT
;
2186 size
= rounddown(size
, PAGE_SIZE
);
2187 /* swiotlb_max_segment_size can return 1 byte when it means one page. */
2188 if (size
< PAGE_SIZE
)
2194 static inline const struct intel_device_info
*
2195 intel_info(const struct drm_i915_private
*dev_priv
)
2197 return &dev_priv
->info
;
2200 #define INTEL_INFO(dev_priv) intel_info((dev_priv))
2201 #define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps)
2203 #define INTEL_GEN(dev_priv) ((dev_priv)->info.gen)
2204 #define INTEL_DEVID(dev_priv) ((dev_priv)->info.device_id)
2206 #define REVID_FOREVER 0xff
2207 #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision)
2209 #define INTEL_GEN_MASK(s, e) ( \
2210 BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \
2211 BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \
2212 GENMASK((e) - 1, (s) - 1))
2214 /* Returns true if Gen is in inclusive range [Start, End] */
2215 #define IS_GEN(dev_priv, s, e) \
2216 (!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e))))
2219 * Return true if revision is in range [since,until] inclusive.
2221 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2223 #define IS_REVID(p, since, until) \
2224 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2226 #define IS_PLATFORM(dev_priv, p) ((dev_priv)->info.platform_mask & BIT(p))
2228 #define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830)
2229 #define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G)
2230 #define IS_I85X(dev_priv) IS_PLATFORM(dev_priv, INTEL_I85X)
2231 #define IS_I865G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I865G)
2232 #define IS_I915G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915G)
2233 #define IS_I915GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915GM)
2234 #define IS_I945G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945G)
2235 #define IS_I945GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945GM)
2236 #define IS_I965G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965G)
2237 #define IS_I965GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965GM)
2238 #define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45)
2239 #define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45)
2240 #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv))
2241 #define IS_PINEVIEW_G(dev_priv) (INTEL_DEVID(dev_priv) == 0xa001)
2242 #define IS_PINEVIEW_M(dev_priv) (INTEL_DEVID(dev_priv) == 0xa011)
2243 #define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
2244 #define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33)
2245 #define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046)
2246 #define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
2247 #define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \
2248 (dev_priv)->info.gt == 1)
2249 #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
2250 #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
2251 #define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL)
2252 #define IS_BROADWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROADWELL)
2253 #define IS_SKYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
2254 #define IS_BROXTON(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROXTON)
2255 #define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
2256 #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
2257 #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
2258 #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
2259 #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE)
2260 #define IS_MOBILE(dev_priv) ((dev_priv)->info.is_mobile)
2261 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
2262 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
2263 #define IS_BDW_ULT(dev_priv) (IS_BROADWELL(dev_priv) && \
2264 ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 || \
2265 (INTEL_DEVID(dev_priv) & 0xf) == 0xb || \
2266 (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
2267 /* ULX machines are also considered ULT. */
2268 #define IS_BDW_ULX(dev_priv) (IS_BROADWELL(dev_priv) && \
2269 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
2270 #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
2271 (dev_priv)->info.gt == 3)
2272 #define IS_HSW_ULT(dev_priv) (IS_HASWELL(dev_priv) && \
2273 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
2274 #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
2275 (dev_priv)->info.gt == 3)
2276 /* ULX machines are also considered ULT. */
2277 #define IS_HSW_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x0A0E || \
2278 INTEL_DEVID(dev_priv) == 0x0A1E)
2279 #define IS_SKL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x1906 || \
2280 INTEL_DEVID(dev_priv) == 0x1913 || \
2281 INTEL_DEVID(dev_priv) == 0x1916 || \
2282 INTEL_DEVID(dev_priv) == 0x1921 || \
2283 INTEL_DEVID(dev_priv) == 0x1926)
2284 #define IS_SKL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x190E || \
2285 INTEL_DEVID(dev_priv) == 0x1915 || \
2286 INTEL_DEVID(dev_priv) == 0x191E)
2287 #define IS_KBL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x5906 || \
2288 INTEL_DEVID(dev_priv) == 0x5913 || \
2289 INTEL_DEVID(dev_priv) == 0x5916 || \
2290 INTEL_DEVID(dev_priv) == 0x5921 || \
2291 INTEL_DEVID(dev_priv) == 0x5926)
2292 #define IS_KBL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x590E || \
2293 INTEL_DEVID(dev_priv) == 0x5915 || \
2294 INTEL_DEVID(dev_priv) == 0x591E)
2295 #define IS_AML_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x591C || \
2296 INTEL_DEVID(dev_priv) == 0x87C0)
2297 #define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \
2298 (dev_priv)->info.gt == 2)
2299 #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
2300 (dev_priv)->info.gt == 3)
2301 #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
2302 (dev_priv)->info.gt == 4)
2303 #define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \
2304 (dev_priv)->info.gt == 2)
2305 #define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \
2306 (dev_priv)->info.gt == 3)
2307 #define IS_CFL_ULT(dev_priv) (IS_COFFEELAKE(dev_priv) && \
2308 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
2309 #define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \
2310 (dev_priv)->info.gt == 2)
2311 #define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \
2312 (dev_priv)->info.gt == 3)
2313 #define IS_CNL_WITH_PORT_F(dev_priv) (IS_CANNONLAKE(dev_priv) && \
2314 (INTEL_DEVID(dev_priv) & 0x0004) == 0x0004)
2316 #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
2318 #define SKL_REVID_A0 0x0
2319 #define SKL_REVID_B0 0x1
2320 #define SKL_REVID_C0 0x2
2321 #define SKL_REVID_D0 0x3
2322 #define SKL_REVID_E0 0x4
2323 #define SKL_REVID_F0 0x5
2324 #define SKL_REVID_G0 0x6
2325 #define SKL_REVID_H0 0x7
2327 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2329 #define BXT_REVID_A0 0x0
2330 #define BXT_REVID_A1 0x1
2331 #define BXT_REVID_B0 0x3
2332 #define BXT_REVID_B_LAST 0x8
2333 #define BXT_REVID_C0 0x9
2335 #define IS_BXT_REVID(dev_priv, since, until) \
2336 (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
2338 #define KBL_REVID_A0 0x0
2339 #define KBL_REVID_B0 0x1
2340 #define KBL_REVID_C0 0x2
2341 #define KBL_REVID_D0 0x3
2342 #define KBL_REVID_E0 0x4
2344 #define IS_KBL_REVID(dev_priv, since, until) \
2345 (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2347 #define GLK_REVID_A0 0x0
2348 #define GLK_REVID_A1 0x1
2350 #define IS_GLK_REVID(dev_priv, since, until) \
2351 (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2353 #define CNL_REVID_A0 0x0
2354 #define CNL_REVID_B0 0x1
2355 #define CNL_REVID_C0 0x2
2357 #define IS_CNL_REVID(p, since, until) \
2358 (IS_CANNONLAKE(p) && IS_REVID(p, since, until))
2360 #define ICL_REVID_A0 0x0
2361 #define ICL_REVID_A2 0x1
2362 #define ICL_REVID_B0 0x3
2363 #define ICL_REVID_B2 0x4
2364 #define ICL_REVID_C0 0x5
2366 #define IS_ICL_REVID(p, since, until) \
2367 (IS_ICELAKE(p) && IS_REVID(p, since, until))
2370 * The genX designation typically refers to the render engine, so render
2371 * capability related checks should use IS_GEN, while display and other checks
2372 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2375 #define IS_GEN2(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(1)))
2376 #define IS_GEN3(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(2)))
2377 #define IS_GEN4(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(3)))
2378 #define IS_GEN5(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(4)))
2379 #define IS_GEN6(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(5)))
2380 #define IS_GEN7(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(6)))
2381 #define IS_GEN8(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(7)))
2382 #define IS_GEN9(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(8)))
2383 #define IS_GEN10(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(9)))
2384 #define IS_GEN11(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(10)))
2386 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
2387 #define IS_GEN9_LP(dev_priv) (IS_GEN9(dev_priv) && IS_LP(dev_priv))
2388 #define IS_GEN9_BC(dev_priv) (IS_GEN9(dev_priv) && !IS_LP(dev_priv))
2390 #define ENGINE_MASK(id) BIT(id)
2391 #define RENDER_RING ENGINE_MASK(RCS)
2392 #define BSD_RING ENGINE_MASK(VCS)
2393 #define BLT_RING ENGINE_MASK(BCS)
2394 #define VEBOX_RING ENGINE_MASK(VECS)
2395 #define BSD2_RING ENGINE_MASK(VCS2)
2396 #define BSD3_RING ENGINE_MASK(VCS3)
2397 #define BSD4_RING ENGINE_MASK(VCS4)
2398 #define VEBOX2_RING ENGINE_MASK(VECS2)
2399 #define ALL_ENGINES (~0)
2401 #define HAS_ENGINE(dev_priv, id) \
2402 (!!((dev_priv)->info.ring_mask & ENGINE_MASK(id)))
2404 #define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS)
2405 #define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2)
2406 #define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS)
2407 #define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS)
2409 #define HAS_LEGACY_SEMAPHORES(dev_priv) IS_GEN7(dev_priv)
2411 #define HAS_LLC(dev_priv) ((dev_priv)->info.has_llc)
2412 #define HAS_SNOOP(dev_priv) ((dev_priv)->info.has_snoop)
2413 #define HAS_EDRAM(dev_priv) (!!((dev_priv)->edram_cap & EDRAM_ENABLED))
2414 #define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \
2415 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
2417 #define HWS_NEEDS_PHYSICAL(dev_priv) ((dev_priv)->info.hws_needs_physical)
2419 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
2420 ((dev_priv)->info.has_logical_ring_contexts)
2421 #define HAS_LOGICAL_RING_ELSQ(dev_priv) \
2422 ((dev_priv)->info.has_logical_ring_elsq)
2423 #define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \
2424 ((dev_priv)->info.has_logical_ring_preemption)
2426 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
2428 #define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt)
2429 #define HAS_PPGTT(dev_priv) \
2430 (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
2431 #define HAS_FULL_PPGTT(dev_priv) \
2432 (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
2433 #define HAS_FULL_48BIT_PPGTT(dev_priv) \
2434 (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL_4LVL)
2436 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
2437 GEM_BUG_ON((sizes) == 0); \
2438 ((sizes) & ~(dev_priv)->info.page_sizes) == 0; \
2441 #define HAS_OVERLAY(dev_priv) ((dev_priv)->info.display.has_overlay)
2442 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
2443 ((dev_priv)->info.display.overlay_needs_physical)
2445 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2446 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv))
2448 /* WaRsDisableCoarsePowerGating:skl,cnl */
2449 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
2450 (IS_CANNONLAKE(dev_priv) || \
2451 IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
2453 #define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4)
2454 #define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \
2455 IS_GEMINILAKE(dev_priv) || \
2456 IS_KABYLAKE(dev_priv))
2458 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2459 * rows, which changed the alignment requirements and fence programming.
2461 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \
2462 !(IS_I915G(dev_priv) || \
2463 IS_I915GM(dev_priv)))
2464 #define SUPPORTS_TV(dev_priv) ((dev_priv)->info.display.supports_tv)
2465 #define I915_HAS_HOTPLUG(dev_priv) ((dev_priv)->info.display.has_hotplug)
2467 #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
2468 #define HAS_FBC(dev_priv) ((dev_priv)->info.display.has_fbc)
2469 #define HAS_CUR_FBC(dev_priv) (!HAS_GMCH_DISPLAY(dev_priv) && INTEL_GEN(dev_priv) >= 7)
2471 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
2473 #define HAS_DP_MST(dev_priv) ((dev_priv)->info.display.has_dp_mst)
2475 #define HAS_DDI(dev_priv) ((dev_priv)->info.display.has_ddi)
2476 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg)
2477 #define HAS_PSR(dev_priv) ((dev_priv)->info.display.has_psr)
2479 #define HAS_RC6(dev_priv) ((dev_priv)->info.has_rc6)
2480 #define HAS_RC6p(dev_priv) ((dev_priv)->info.has_rc6p)
2481 #define HAS_RC6pp(dev_priv) (false) /* HW was never validated */
2483 #define HAS_CSR(dev_priv) ((dev_priv)->info.display.has_csr)
2485 #define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
2486 #define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc)
2488 #define HAS_IPC(dev_priv) ((dev_priv)->info.display.has_ipc)
2491 * For now, anything with a GuC requires uCode loading, and then supports
2492 * command submission once loaded. But these are logically independent
2493 * properties, so we have separate macros to test them.
2495 #define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc)
2496 #define HAS_GUC_CT(dev_priv) ((dev_priv)->info.has_guc_ct)
2497 #define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2498 #define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv))
2500 /* For now, anything with a GuC has also HuC */
2501 #define HAS_HUC(dev_priv) (HAS_GUC(dev_priv))
2502 #define HAS_HUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2504 /* Having a GuC is not the same as using a GuC */
2505 #define USES_GUC(dev_priv) intel_uc_is_using_guc()
2506 #define USES_GUC_SUBMISSION(dev_priv) intel_uc_is_using_guc_submission()
2507 #define USES_HUC(dev_priv) intel_uc_is_using_huc()
2509 #define HAS_POOLED_EU(dev_priv) ((dev_priv)->info.has_pooled_eu)
2511 #define INTEL_PCH_DEVICE_ID_MASK 0xff80
2512 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2513 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2514 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2515 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2516 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2517 #define INTEL_PCH_WPT_DEVICE_ID_TYPE 0x8c80
2518 #define INTEL_PCH_WPT_LP_DEVICE_ID_TYPE 0x9c80
2519 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2520 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2521 #define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA280
2522 #define INTEL_PCH_CNP_DEVICE_ID_TYPE 0xA300
2523 #define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE 0x9D80
2524 #define INTEL_PCH_ICP_DEVICE_ID_TYPE 0x3480
2525 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
2526 #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
2527 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
2529 #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
2530 #define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id)
2531 #define HAS_PCH_ICP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ICP)
2532 #define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP)
2533 #define HAS_PCH_CNP_LP(dev_priv) \
2534 (INTEL_PCH_ID(dev_priv) == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE)
2535 #define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP)
2536 #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
2537 #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
2538 #define HAS_PCH_LPT_LP(dev_priv) \
2539 (INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE || \
2540 INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE)
2541 #define HAS_PCH_LPT_H(dev_priv) \
2542 (INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_DEVICE_ID_TYPE || \
2543 INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_DEVICE_ID_TYPE)
2544 #define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
2545 #define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
2546 #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
2547 #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
2549 #define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.display.has_gmch_display)
2551 #define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9)
2553 /* DPF == dynamic parity feature */
2554 #define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf)
2555 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
2556 2 : HAS_L3_DPF(dev_priv))
2558 #define GT_FREQUENCY_MULTIPLIER 50
2559 #define GEN9_FREQ_SCALER 3
2561 #define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->num_pipes > 0)
2563 #include "i915_trace.h"
2565 static inline bool intel_vtd_active(void)
2567 #ifdef CONFIG_INTEL_IOMMU
2568 if (intel_iommu_gfx_mapped
)
2574 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private
*dev_priv
)
2576 return INTEL_GEN(dev_priv
) >= 6 && intel_vtd_active();
2580 intel_ggtt_update_needs_vtd_wa(struct drm_i915_private
*dev_priv
)
2582 return IS_BROXTON(dev_priv
) && intel_vtd_active();
2587 __i915_printk(struct drm_i915_private
*dev_priv
, const char *level
,
2588 const char *fmt
, ...);
2590 #define i915_report_error(dev_priv, fmt, ...) \
2591 __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
2593 #ifdef CONFIG_COMPAT
2594 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
2597 #define i915_compat_ioctl NULL
2599 extern const struct dev_pm_ops i915_pm_ops
;
2601 extern int i915_driver_load(struct pci_dev
*pdev
,
2602 const struct pci_device_id
*ent
);
2603 extern void i915_driver_unload(struct drm_device
*dev
);
2604 extern int intel_gpu_reset(struct drm_i915_private
*dev_priv
, u32 engine_mask
);
2605 extern bool intel_has_gpu_reset(struct drm_i915_private
*dev_priv
);
2607 extern void i915_reset(struct drm_i915_private
*i915
,
2608 unsigned int stalled_mask
,
2609 const char *reason
);
2610 extern int i915_reset_engine(struct intel_engine_cs
*engine
,
2611 const char *reason
);
2613 extern bool intel_has_reset_engine(struct drm_i915_private
*dev_priv
);
2614 extern int intel_reset_guc(struct drm_i915_private
*dev_priv
);
2615 extern int intel_guc_reset_engine(struct intel_guc
*guc
,
2616 struct intel_engine_cs
*engine
);
2617 extern void intel_engine_init_hangcheck(struct intel_engine_cs
*engine
);
2618 extern void intel_hangcheck_init(struct drm_i915_private
*dev_priv
);
2619 extern unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
);
2620 extern unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
);
2621 extern unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
);
2622 extern void i915_update_gfx_val(struct drm_i915_private
*dev_priv
);
2623 int vlv_force_gfx_clock(struct drm_i915_private
*dev_priv
, bool on
);
2625 int intel_engines_init_mmio(struct drm_i915_private
*dev_priv
);
2626 int intel_engines_init(struct drm_i915_private
*dev_priv
);
2628 u32
intel_calculate_mcr_s_ss_select(struct drm_i915_private
*dev_priv
);
2630 /* intel_hotplug.c */
2631 void intel_hpd_irq_handler(struct drm_i915_private
*dev_priv
,
2632 u32 pin_mask
, u32 long_mask
);
2633 void intel_hpd_init(struct drm_i915_private
*dev_priv
);
2634 void intel_hpd_init_work(struct drm_i915_private
*dev_priv
);
2635 void intel_hpd_cancel_work(struct drm_i915_private
*dev_priv
);
2636 enum hpd_pin
intel_hpd_pin_default(struct drm_i915_private
*dev_priv
,
2638 bool intel_hpd_disable(struct drm_i915_private
*dev_priv
, enum hpd_pin pin
);
2639 void intel_hpd_enable(struct drm_i915_private
*dev_priv
, enum hpd_pin pin
);
2642 static inline void i915_queue_hangcheck(struct drm_i915_private
*dev_priv
)
2644 unsigned long delay
;
2646 if (unlikely(!i915_modparams
.enable_hangcheck
))
2649 /* Don't continually defer the hangcheck so that it is always run at
2650 * least once after work has been scheduled on any ring. Otherwise,
2651 * we will ignore a hung ring if a second ring is kept busy.
2654 delay
= round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES
);
2655 queue_delayed_work(system_long_wq
,
2656 &dev_priv
->gpu_error
.hangcheck_work
, delay
);
2660 void i915_handle_error(struct drm_i915_private
*dev_priv
,
2662 unsigned long flags
,
2663 const char *fmt
, ...);
2664 #define I915_ERROR_CAPTURE BIT(0)
2666 extern void intel_irq_init(struct drm_i915_private
*dev_priv
);
2667 extern void intel_irq_fini(struct drm_i915_private
*dev_priv
);
2668 int intel_irq_install(struct drm_i915_private
*dev_priv
);
2669 void intel_irq_uninstall(struct drm_i915_private
*dev_priv
);
2671 void i915_clear_error_registers(struct drm_i915_private
*dev_priv
);
2673 static inline bool intel_gvt_active(struct drm_i915_private
*dev_priv
)
2675 return dev_priv
->gvt
;
2678 static inline bool intel_vgpu_active(struct drm_i915_private
*dev_priv
)
2680 return dev_priv
->vgpu
.active
;
2683 u32
i915_pipestat_enable_mask(struct drm_i915_private
*dev_priv
,
2686 i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
2690 i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
2693 void valleyview_enable_display_irqs(struct drm_i915_private
*dev_priv
);
2694 void valleyview_disable_display_irqs(struct drm_i915_private
*dev_priv
);
2695 void i915_hotplug_interrupt_update(struct drm_i915_private
*dev_priv
,
2698 void ilk_update_display_irq(struct drm_i915_private
*dev_priv
,
2699 uint32_t interrupt_mask
,
2700 uint32_t enabled_irq_mask
);
2702 ilk_enable_display_irq(struct drm_i915_private
*dev_priv
, uint32_t bits
)
2704 ilk_update_display_irq(dev_priv
, bits
, bits
);
2707 ilk_disable_display_irq(struct drm_i915_private
*dev_priv
, uint32_t bits
)
2709 ilk_update_display_irq(dev_priv
, bits
, 0);
2711 void bdw_update_pipe_irq(struct drm_i915_private
*dev_priv
,
2713 uint32_t interrupt_mask
,
2714 uint32_t enabled_irq_mask
);
2715 static inline void bdw_enable_pipe_irq(struct drm_i915_private
*dev_priv
,
2716 enum pipe pipe
, uint32_t bits
)
2718 bdw_update_pipe_irq(dev_priv
, pipe
, bits
, bits
);
2720 static inline void bdw_disable_pipe_irq(struct drm_i915_private
*dev_priv
,
2721 enum pipe pipe
, uint32_t bits
)
2723 bdw_update_pipe_irq(dev_priv
, pipe
, bits
, 0);
2725 void ibx_display_interrupt_update(struct drm_i915_private
*dev_priv
,
2726 uint32_t interrupt_mask
,
2727 uint32_t enabled_irq_mask
);
2729 ibx_enable_display_interrupt(struct drm_i915_private
*dev_priv
, uint32_t bits
)
2731 ibx_display_interrupt_update(dev_priv
, bits
, bits
);
2734 ibx_disable_display_interrupt(struct drm_i915_private
*dev_priv
, uint32_t bits
)
2736 ibx_display_interrupt_update(dev_priv
, bits
, 0);
2740 int i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
2741 struct drm_file
*file_priv
);
2742 int i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
2743 struct drm_file
*file_priv
);
2744 int i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
2745 struct drm_file
*file_priv
);
2746 int i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
2747 struct drm_file
*file_priv
);
2748 int i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
2749 struct drm_file
*file_priv
);
2750 int i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
2751 struct drm_file
*file_priv
);
2752 int i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
2753 struct drm_file
*file_priv
);
2754 int i915_gem_execbuffer_ioctl(struct drm_device
*dev
, void *data
,
2755 struct drm_file
*file_priv
);
2756 int i915_gem_execbuffer2_ioctl(struct drm_device
*dev
, void *data
,
2757 struct drm_file
*file_priv
);
2758 int i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
2759 struct drm_file
*file_priv
);
2760 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
2761 struct drm_file
*file
);
2762 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
2763 struct drm_file
*file
);
2764 int i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
2765 struct drm_file
*file_priv
);
2766 int i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
2767 struct drm_file
*file_priv
);
2768 int i915_gem_set_tiling_ioctl(struct drm_device
*dev
, void *data
,
2769 struct drm_file
*file_priv
);
2770 int i915_gem_get_tiling_ioctl(struct drm_device
*dev
, void *data
,
2771 struct drm_file
*file_priv
);
2772 int i915_gem_init_userptr(struct drm_i915_private
*dev_priv
);
2773 void i915_gem_cleanup_userptr(struct drm_i915_private
*dev_priv
);
2774 int i915_gem_userptr_ioctl(struct drm_device
*dev
, void *data
,
2775 struct drm_file
*file
);
2776 int i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
2777 struct drm_file
*file_priv
);
2778 int i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
,
2779 struct drm_file
*file_priv
);
2780 void i915_gem_sanitize(struct drm_i915_private
*i915
);
2781 int i915_gem_init_early(struct drm_i915_private
*dev_priv
);
2782 void i915_gem_cleanup_early(struct drm_i915_private
*dev_priv
);
2783 void i915_gem_load_init_fences(struct drm_i915_private
*dev_priv
);
2784 int i915_gem_freeze(struct drm_i915_private
*dev_priv
);
2785 int i915_gem_freeze_late(struct drm_i915_private
*dev_priv
);
2787 void *i915_gem_object_alloc(struct drm_i915_private
*dev_priv
);
2788 void i915_gem_object_free(struct drm_i915_gem_object
*obj
);
2789 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
2790 const struct drm_i915_gem_object_ops
*ops
);
2791 struct drm_i915_gem_object
*
2792 i915_gem_object_create(struct drm_i915_private
*dev_priv
, u64 size
);
2793 struct drm_i915_gem_object
*
2794 i915_gem_object_create_from_data(struct drm_i915_private
*dev_priv
,
2795 const void *data
, size_t size
);
2796 void i915_gem_close_object(struct drm_gem_object
*gem
, struct drm_file
*file
);
2797 void i915_gem_free_object(struct drm_gem_object
*obj
);
2799 static inline void i915_gem_drain_freed_objects(struct drm_i915_private
*i915
)
2801 if (!atomic_read(&i915
->mm
.free_count
))
2804 /* A single pass should suffice to release all the freed objects (along
2805 * most call paths) , but be a little more paranoid in that freeing
2806 * the objects does take a little amount of time, during which the rcu
2807 * callbacks could have added new objects into the freed list, and
2808 * armed the work again.
2812 } while (flush_work(&i915
->mm
.free_work
));
2815 static inline void i915_gem_drain_workqueue(struct drm_i915_private
*i915
)
2818 * Similar to objects above (see i915_gem_drain_freed-objects), in
2819 * general we have workers that are armed by RCU and then rearm
2820 * themselves in their callbacks. To be paranoid, we need to
2821 * drain the workqueue a second time after waiting for the RCU
2822 * grace period so that we catch work queued via RCU from the first
2823 * pass. As neither drain_workqueue() nor flush_workqueue() report
2824 * a result, we make an assumption that we only don't require more
2825 * than 2 passes to catch all recursive RCU delayed work.
2831 drain_workqueue(i915
->wq
);
2835 struct i915_vma
* __must_check
2836 i915_gem_object_ggtt_pin(struct drm_i915_gem_object
*obj
,
2837 const struct i915_ggtt_view
*view
,
2842 int i915_gem_object_unbind(struct drm_i915_gem_object
*obj
);
2843 void i915_gem_release_mmap(struct drm_i915_gem_object
*obj
);
2845 void i915_gem_runtime_suspend(struct drm_i915_private
*dev_priv
);
2847 static inline int __sg_page_count(const struct scatterlist
*sg
)
2849 return sg
->length
>> PAGE_SHIFT
;
2852 struct scatterlist
*
2853 i915_gem_object_get_sg(struct drm_i915_gem_object
*obj
,
2854 unsigned int n
, unsigned int *offset
);
2857 i915_gem_object_get_page(struct drm_i915_gem_object
*obj
,
2861 i915_gem_object_get_dirty_page(struct drm_i915_gem_object
*obj
,
2865 i915_gem_object_get_dma_address(struct drm_i915_gem_object
*obj
,
2868 void __i915_gem_object_set_pages(struct drm_i915_gem_object
*obj
,
2869 struct sg_table
*pages
,
2870 unsigned int sg_page_sizes
);
2871 int __i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
);
2873 static inline int __must_check
2874 i915_gem_object_pin_pages(struct drm_i915_gem_object
*obj
)
2876 might_lock(&obj
->mm
.lock
);
2878 if (atomic_inc_not_zero(&obj
->mm
.pages_pin_count
))
2881 return __i915_gem_object_get_pages(obj
);
2885 i915_gem_object_has_pages(struct drm_i915_gem_object
*obj
)
2887 return !IS_ERR_OR_NULL(READ_ONCE(obj
->mm
.pages
));
2891 __i915_gem_object_pin_pages(struct drm_i915_gem_object
*obj
)
2893 GEM_BUG_ON(!i915_gem_object_has_pages(obj
));
2895 atomic_inc(&obj
->mm
.pages_pin_count
);
2899 i915_gem_object_has_pinned_pages(struct drm_i915_gem_object
*obj
)
2901 return atomic_read(&obj
->mm
.pages_pin_count
);
2905 __i915_gem_object_unpin_pages(struct drm_i915_gem_object
*obj
)
2907 GEM_BUG_ON(!i915_gem_object_has_pages(obj
));
2908 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj
));
2910 atomic_dec(&obj
->mm
.pages_pin_count
);
2914 i915_gem_object_unpin_pages(struct drm_i915_gem_object
*obj
)
2916 __i915_gem_object_unpin_pages(obj
);
2919 enum i915_mm_subclass
{ /* lockdep subclass for obj->mm.lock */
2924 void __i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
,
2925 enum i915_mm_subclass subclass
);
2926 void __i915_gem_object_invalidate(struct drm_i915_gem_object
*obj
);
2928 enum i915_map_type
{
2931 #define I915_MAP_OVERRIDE BIT(31)
2932 I915_MAP_FORCE_WB
= I915_MAP_WB
| I915_MAP_OVERRIDE
,
2933 I915_MAP_FORCE_WC
= I915_MAP_WC
| I915_MAP_OVERRIDE
,
2936 static inline enum i915_map_type
2937 i915_coherent_map_type(struct drm_i915_private
*i915
)
2939 return HAS_LLC(i915
) ? I915_MAP_WB
: I915_MAP_WC
;
2943 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
2944 * @obj: the object to map into kernel address space
2945 * @type: the type of mapping, used to select pgprot_t
2947 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
2948 * pages and then returns a contiguous mapping of the backing storage into
2949 * the kernel address space. Based on the @type of mapping, the PTE will be
2950 * set to either WriteBack or WriteCombine (via pgprot_t).
2952 * The caller is responsible for calling i915_gem_object_unpin_map() when the
2953 * mapping is no longer required.
2955 * Returns the pointer through which to access the mapped object, or an
2956 * ERR_PTR() on error.
2958 void *__must_check
i915_gem_object_pin_map(struct drm_i915_gem_object
*obj
,
2959 enum i915_map_type type
);
2962 * i915_gem_object_unpin_map - releases an earlier mapping
2963 * @obj: the object to unmap
2965 * After pinning the object and mapping its pages, once you are finished
2966 * with your access, call i915_gem_object_unpin_map() to release the pin
2967 * upon the mapping. Once the pin count reaches zero, that mapping may be
2970 static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object
*obj
)
2972 i915_gem_object_unpin_pages(obj
);
2975 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
2976 unsigned int *needs_clflush
);
2977 int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object
*obj
,
2978 unsigned int *needs_clflush
);
2979 #define CLFLUSH_BEFORE BIT(0)
2980 #define CLFLUSH_AFTER BIT(1)
2981 #define CLFLUSH_FLAGS (CLFLUSH_BEFORE | CLFLUSH_AFTER)
2984 i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object
*obj
)
2986 i915_gem_object_unpin_pages(obj
);
2989 int __must_check
i915_mutex_lock_interruptible(struct drm_device
*dev
);
2990 int i915_gem_dumb_create(struct drm_file
*file_priv
,
2991 struct drm_device
*dev
,
2992 struct drm_mode_create_dumb
*args
);
2993 int i915_gem_mmap_gtt(struct drm_file
*file_priv
, struct drm_device
*dev
,
2994 uint32_t handle
, uint64_t *offset
);
2995 int i915_gem_mmap_gtt_version(void);
2997 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
2998 struct drm_i915_gem_object
*new,
2999 unsigned frontbuffer_bits
);
3001 int __must_check
i915_gem_set_global_seqno(struct drm_device
*dev
, u32 seqno
);
3003 struct i915_request
*
3004 i915_gem_find_active_request(struct intel_engine_cs
*engine
);
3006 static inline bool i915_reset_backoff(struct i915_gpu_error
*error
)
3008 return unlikely(test_bit(I915_RESET_BACKOFF
, &error
->flags
));
3011 static inline bool i915_reset_handoff(struct i915_gpu_error
*error
)
3013 return unlikely(test_bit(I915_RESET_HANDOFF
, &error
->flags
));
3016 static inline bool i915_terminally_wedged(struct i915_gpu_error
*error
)
3018 return unlikely(test_bit(I915_WEDGED
, &error
->flags
));
3021 static inline bool i915_reset_backoff_or_wedged(struct i915_gpu_error
*error
)
3023 return i915_reset_backoff(error
) | i915_terminally_wedged(error
);
3026 static inline u32
i915_reset_count(struct i915_gpu_error
*error
)
3028 return READ_ONCE(error
->reset_count
);
3031 static inline u32
i915_reset_engine_count(struct i915_gpu_error
*error
,
3032 struct intel_engine_cs
*engine
)
3034 return READ_ONCE(error
->reset_engine_count
[engine
->id
]);
3037 struct i915_request
*
3038 i915_gem_reset_prepare_engine(struct intel_engine_cs
*engine
);
3039 int i915_gem_reset_prepare(struct drm_i915_private
*dev_priv
);
3040 void i915_gem_reset(struct drm_i915_private
*dev_priv
,
3041 unsigned int stalled_mask
);
3042 void i915_gem_reset_finish_engine(struct intel_engine_cs
*engine
);
3043 void i915_gem_reset_finish(struct drm_i915_private
*dev_priv
);
3044 void i915_gem_set_wedged(struct drm_i915_private
*dev_priv
);
3045 bool i915_gem_unset_wedged(struct drm_i915_private
*dev_priv
);
3046 void i915_gem_reset_engine(struct intel_engine_cs
*engine
,
3047 struct i915_request
*request
,
3050 void i915_gem_init_mmio(struct drm_i915_private
*i915
);
3051 int __must_check
i915_gem_init(struct drm_i915_private
*dev_priv
);
3052 int __must_check
i915_gem_init_hw(struct drm_i915_private
*dev_priv
);
3053 void i915_gem_init_swizzling(struct drm_i915_private
*dev_priv
);
3054 void i915_gem_fini(struct drm_i915_private
*dev_priv
);
3055 void i915_gem_cleanup_engines(struct drm_i915_private
*dev_priv
);
3056 int i915_gem_wait_for_idle(struct drm_i915_private
*dev_priv
,
3057 unsigned int flags
, long timeout
);
3058 int __must_check
i915_gem_suspend(struct drm_i915_private
*dev_priv
);
3059 void i915_gem_suspend_late(struct drm_i915_private
*dev_priv
);
3060 void i915_gem_resume(struct drm_i915_private
*dev_priv
);
3061 vm_fault_t
i915_gem_fault(struct vm_fault
*vmf
);
3062 int i915_gem_object_wait(struct drm_i915_gem_object
*obj
,
3065 struct intel_rps_client
*rps
);
3066 int i915_gem_object_wait_priority(struct drm_i915_gem_object
*obj
,
3068 const struct i915_sched_attr
*attr
);
3069 #define I915_PRIORITY_DISPLAY I915_USER_PRIORITY(I915_PRIORITY_MAX)
3072 i915_gem_object_set_to_wc_domain(struct drm_i915_gem_object
*obj
, bool write
);
3074 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
, bool write
);
3076 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
);
3077 struct i915_vma
* __must_check
3078 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
3080 const struct i915_ggtt_view
*view
,
3081 unsigned int flags
);
3082 void i915_gem_object_unpin_from_display_plane(struct i915_vma
*vma
);
3083 int i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
3085 int i915_gem_open(struct drm_i915_private
*i915
, struct drm_file
*file
);
3086 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
);
3088 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
3089 enum i915_cache_level cache_level
);
3091 struct drm_gem_object
*i915_gem_prime_import(struct drm_device
*dev
,
3092 struct dma_buf
*dma_buf
);
3094 struct dma_buf
*i915_gem_prime_export(struct drm_device
*dev
,
3095 struct drm_gem_object
*gem_obj
, int flags
);
3097 static inline struct i915_hw_ppgtt
*
3098 i915_vm_to_ppgtt(struct i915_address_space
*vm
)
3100 return container_of(vm
, struct i915_hw_ppgtt
, vm
);
3103 /* i915_gem_fence_reg.c */
3104 struct drm_i915_fence_reg
*
3105 i915_reserve_fence(struct drm_i915_private
*dev_priv
);
3106 void i915_unreserve_fence(struct drm_i915_fence_reg
*fence
);
3108 void i915_gem_revoke_fences(struct drm_i915_private
*dev_priv
);
3109 void i915_gem_restore_fences(struct drm_i915_private
*dev_priv
);
3111 void i915_gem_detect_bit_6_swizzle(struct drm_i915_private
*dev_priv
);
3112 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object
*obj
,
3113 struct sg_table
*pages
);
3114 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object
*obj
,
3115 struct sg_table
*pages
);
3117 static inline struct i915_gem_context
*
3118 __i915_gem_context_lookup_rcu(struct drm_i915_file_private
*file_priv
, u32 id
)
3120 return idr_find(&file_priv
->context_idr
, id
);
3123 static inline struct i915_gem_context
*
3124 i915_gem_context_lookup(struct drm_i915_file_private
*file_priv
, u32 id
)
3126 struct i915_gem_context
*ctx
;
3129 ctx
= __i915_gem_context_lookup_rcu(file_priv
, id
);
3130 if (ctx
&& !kref_get_unless_zero(&ctx
->ref
))
3137 int i915_perf_open_ioctl(struct drm_device
*dev
, void *data
,
3138 struct drm_file
*file
);
3139 int i915_perf_add_config_ioctl(struct drm_device
*dev
, void *data
,
3140 struct drm_file
*file
);
3141 int i915_perf_remove_config_ioctl(struct drm_device
*dev
, void *data
,
3142 struct drm_file
*file
);
3143 void i915_oa_init_reg_state(struct intel_engine_cs
*engine
,
3144 struct i915_gem_context
*ctx
,
3145 uint32_t *reg_state
);
3147 /* i915_gem_evict.c */
3148 int __must_check
i915_gem_evict_something(struct i915_address_space
*vm
,
3149 u64 min_size
, u64 alignment
,
3150 unsigned cache_level
,
3153 int __must_check
i915_gem_evict_for_node(struct i915_address_space
*vm
,
3154 struct drm_mm_node
*node
,
3155 unsigned int flags
);
3156 int i915_gem_evict_vm(struct i915_address_space
*vm
);
3158 void i915_gem_flush_ggtt_writes(struct drm_i915_private
*dev_priv
);
3160 /* belongs in i915_gem_gtt.h */
3161 static inline void i915_gem_chipset_flush(struct drm_i915_private
*dev_priv
)
3164 if (INTEL_GEN(dev_priv
) < 6)
3165 intel_gtt_chipset_flush();
3168 /* i915_gem_stolen.c */
3169 int i915_gem_stolen_insert_node(struct drm_i915_private
*dev_priv
,
3170 struct drm_mm_node
*node
, u64 size
,
3171 unsigned alignment
);
3172 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private
*dev_priv
,
3173 struct drm_mm_node
*node
, u64 size
,
3174 unsigned alignment
, u64 start
,
3176 void i915_gem_stolen_remove_node(struct drm_i915_private
*dev_priv
,
3177 struct drm_mm_node
*node
);
3178 int i915_gem_init_stolen(struct drm_i915_private
*dev_priv
);
3179 void i915_gem_cleanup_stolen(struct drm_i915_private
*dev_priv
);
3180 struct drm_i915_gem_object
*
3181 i915_gem_object_create_stolen(struct drm_i915_private
*dev_priv
,
3182 resource_size_t size
);
3183 struct drm_i915_gem_object
*
3184 i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private
*dev_priv
,
3185 resource_size_t stolen_offset
,
3186 resource_size_t gtt_offset
,
3187 resource_size_t size
);
3189 /* i915_gem_internal.c */
3190 struct drm_i915_gem_object
*
3191 i915_gem_object_create_internal(struct drm_i915_private
*dev_priv
,
3194 /* i915_gem_shrinker.c */
3195 unsigned long i915_gem_shrink(struct drm_i915_private
*i915
,
3196 unsigned long target
,
3197 unsigned long *nr_scanned
,
3199 #define I915_SHRINK_PURGEABLE 0x1
3200 #define I915_SHRINK_UNBOUND 0x2
3201 #define I915_SHRINK_BOUND 0x4
3202 #define I915_SHRINK_ACTIVE 0x8
3203 #define I915_SHRINK_VMAPS 0x10
3204 unsigned long i915_gem_shrink_all(struct drm_i915_private
*i915
);
3205 void i915_gem_shrinker_register(struct drm_i915_private
*i915
);
3206 void i915_gem_shrinker_unregister(struct drm_i915_private
*i915
);
3207 void i915_gem_shrinker_taints_mutex(struct mutex
*mutex
);
3209 /* i915_gem_tiling.c */
3210 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object
*obj
)
3212 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
3214 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
3215 i915_gem_object_is_tiled(obj
);
3218 u32
i915_gem_fence_size(struct drm_i915_private
*dev_priv
, u32 size
,
3219 unsigned int tiling
, unsigned int stride
);
3220 u32
i915_gem_fence_alignment(struct drm_i915_private
*dev_priv
, u32 size
,
3221 unsigned int tiling
, unsigned int stride
);
3223 /* i915_debugfs.c */
3224 #ifdef CONFIG_DEBUG_FS
3225 int i915_debugfs_register(struct drm_i915_private
*dev_priv
);
3226 int i915_debugfs_connector_add(struct drm_connector
*connector
);
3227 void intel_display_crc_init(struct drm_i915_private
*dev_priv
);
3229 static inline int i915_debugfs_register(struct drm_i915_private
*dev_priv
) {return 0;}
3230 static inline int i915_debugfs_connector_add(struct drm_connector
*connector
)
3232 static inline void intel_display_crc_init(struct drm_i915_private
*dev_priv
) {}
3235 const char *i915_cache_level_str(struct drm_i915_private
*i915
, int type
);
3237 /* i915_cmd_parser.c */
3238 int i915_cmd_parser_get_version(struct drm_i915_private
*dev_priv
);
3239 void intel_engine_init_cmd_parser(struct intel_engine_cs
*engine
);
3240 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs
*engine
);
3241 int intel_engine_cmd_parser(struct intel_engine_cs
*engine
,
3242 struct drm_i915_gem_object
*batch_obj
,
3243 struct drm_i915_gem_object
*shadow_batch_obj
,
3244 u32 batch_start_offset
,
3249 extern void i915_perf_init(struct drm_i915_private
*dev_priv
);
3250 extern void i915_perf_fini(struct drm_i915_private
*dev_priv
);
3251 extern void i915_perf_register(struct drm_i915_private
*dev_priv
);
3252 extern void i915_perf_unregister(struct drm_i915_private
*dev_priv
);
3254 /* i915_suspend.c */
3255 extern int i915_save_state(struct drm_i915_private
*dev_priv
);
3256 extern int i915_restore_state(struct drm_i915_private
*dev_priv
);
3259 void i915_setup_sysfs(struct drm_i915_private
*dev_priv
);
3260 void i915_teardown_sysfs(struct drm_i915_private
*dev_priv
);
3262 /* intel_lpe_audio.c */
3263 int intel_lpe_audio_init(struct drm_i915_private
*dev_priv
);
3264 void intel_lpe_audio_teardown(struct drm_i915_private
*dev_priv
);
3265 void intel_lpe_audio_irq_handler(struct drm_i915_private
*dev_priv
);
3266 void intel_lpe_audio_notify(struct drm_i915_private
*dev_priv
,
3267 enum pipe pipe
, enum port port
,
3268 const void *eld
, int ls_clock
, bool dp_output
);
3271 extern int intel_setup_gmbus(struct drm_i915_private
*dev_priv
);
3272 extern void intel_teardown_gmbus(struct drm_i915_private
*dev_priv
);
3273 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private
*dev_priv
,
3275 extern int intel_gmbus_output_aksv(struct i2c_adapter
*adapter
);
3277 extern struct i2c_adapter
*
3278 intel_gmbus_get_adapter(struct drm_i915_private
*dev_priv
, unsigned int pin
);
3279 extern void intel_gmbus_set_speed(struct i2c_adapter
*adapter
, int speed
);
3280 extern void intel_gmbus_force_bit(struct i2c_adapter
*adapter
, bool force_bit
);
3281 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter
*adapter
)
3283 return container_of(adapter
, struct intel_gmbus
, adapter
)->force_bit
;
3285 extern void intel_i2c_reset(struct drm_i915_private
*dev_priv
);
3288 void intel_bios_init(struct drm_i915_private
*dev_priv
);
3289 void intel_bios_cleanup(struct drm_i915_private
*dev_priv
);
3290 bool intel_bios_is_valid_vbt(const void *buf
, size_t size
);
3291 bool intel_bios_is_tv_present(struct drm_i915_private
*dev_priv
);
3292 bool intel_bios_is_lvds_present(struct drm_i915_private
*dev_priv
, u8
*i2c_pin
);
3293 bool intel_bios_is_port_present(struct drm_i915_private
*dev_priv
, enum port port
);
3294 bool intel_bios_is_port_edp(struct drm_i915_private
*dev_priv
, enum port port
);
3295 bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private
*dev_priv
, enum port port
);
3296 bool intel_bios_is_dsi_present(struct drm_i915_private
*dev_priv
, enum port
*port
);
3297 bool intel_bios_is_port_hpd_inverted(struct drm_i915_private
*dev_priv
,
3299 bool intel_bios_is_lspcon_present(struct drm_i915_private
*dev_priv
,
3301 enum aux_ch
intel_bios_port_aux_ch(struct drm_i915_private
*dev_priv
, enum port port
);
3305 extern void intel_register_dsm_handler(void);
3306 extern void intel_unregister_dsm_handler(void);
3308 static inline void intel_register_dsm_handler(void) { return; }
3309 static inline void intel_unregister_dsm_handler(void) { return; }
3310 #endif /* CONFIG_ACPI */
3312 /* intel_device_info.c */
3313 static inline struct intel_device_info
*
3314 mkwrite_device_info(struct drm_i915_private
*dev_priv
)
3316 return (struct intel_device_info
*)&dev_priv
->info
;
3320 extern void intel_modeset_init_hw(struct drm_device
*dev
);
3321 extern int intel_modeset_init(struct drm_device
*dev
);
3322 extern void intel_modeset_cleanup(struct drm_device
*dev
);
3323 extern int intel_modeset_vga_set_state(struct drm_i915_private
*dev_priv
,
3325 extern void intel_display_resume(struct drm_device
*dev
);
3326 extern void i915_redisable_vga(struct drm_i915_private
*dev_priv
);
3327 extern void i915_redisable_vga_power_on(struct drm_i915_private
*dev_priv
);
3328 extern bool ironlake_set_drps(struct drm_i915_private
*dev_priv
, u8 val
);
3329 extern void intel_init_pch_refclk(struct drm_i915_private
*dev_priv
);
3330 extern int intel_set_rps(struct drm_i915_private
*dev_priv
, u8 val
);
3331 extern void intel_rps_mark_interactive(struct drm_i915_private
*i915
,
3333 extern bool intel_set_memory_cxsr(struct drm_i915_private
*dev_priv
,
3335 void intel_dsc_enable(struct intel_encoder
*encoder
,
3336 const struct intel_crtc_state
*crtc_state
);
3337 void intel_dsc_disable(const struct intel_crtc_state
*crtc_state
);
3339 int i915_reg_read_ioctl(struct drm_device
*dev
, void *data
,
3340 struct drm_file
*file
);
3343 extern struct intel_overlay_error_state
*
3344 intel_overlay_capture_error_state(struct drm_i915_private
*dev_priv
);
3345 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf
*e
,
3346 struct intel_overlay_error_state
*error
);
3348 extern struct intel_display_error_state
*
3349 intel_display_capture_error_state(struct drm_i915_private
*dev_priv
);
3350 extern void intel_display_print_error_state(struct drm_i915_error_state_buf
*e
,
3351 struct intel_display_error_state
*error
);
3353 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u32 mbox
, u32
*val
);
3354 int sandybridge_pcode_write_timeout(struct drm_i915_private
*dev_priv
, u32 mbox
,
3355 u32 val
, int fast_timeout_us
,
3356 int slow_timeout_ms
);
3357 #define sandybridge_pcode_write(dev_priv, mbox, val) \
3358 sandybridge_pcode_write_timeout(dev_priv, mbox, val, 500, 0)
3360 int skl_pcode_request(struct drm_i915_private
*dev_priv
, u32 mbox
, u32 request
,
3361 u32 reply_mask
, u32 reply
, int timeout_base_ms
);
3363 /* intel_sideband.c */
3364 u32
vlv_punit_read(struct drm_i915_private
*dev_priv
, u32 addr
);
3365 int vlv_punit_write(struct drm_i915_private
*dev_priv
, u32 addr
, u32 val
);
3366 u32
vlv_nc_read(struct drm_i915_private
*dev_priv
, u8 addr
);
3367 u32
vlv_iosf_sb_read(struct drm_i915_private
*dev_priv
, u8 port
, u32 reg
);
3368 void vlv_iosf_sb_write(struct drm_i915_private
*dev_priv
, u8 port
, u32 reg
, u32 val
);
3369 u32
vlv_cck_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3370 void vlv_cck_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3371 u32
vlv_ccu_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3372 void vlv_ccu_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3373 u32
vlv_bunit_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3374 void vlv_bunit_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3375 u32
vlv_dpio_read(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
);
3376 void vlv_dpio_write(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
, u32 val
);
3377 u32
intel_sbi_read(struct drm_i915_private
*dev_priv
, u16 reg
,
3378 enum intel_sbi_destination destination
);
3379 void intel_sbi_write(struct drm_i915_private
*dev_priv
, u16 reg
, u32 value
,
3380 enum intel_sbi_destination destination
);
3381 u32
vlv_flisdsi_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3382 void vlv_flisdsi_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3384 /* intel_dpio_phy.c */
3385 void bxt_port_to_phy_channel(struct drm_i915_private
*dev_priv
, enum port port
,
3386 enum dpio_phy
*phy
, enum dpio_channel
*ch
);
3387 void bxt_ddi_phy_set_signal_level(struct drm_i915_private
*dev_priv
,
3388 enum port port
, u32 margin
, u32 scale
,
3389 u32 enable
, u32 deemphasis
);
3390 void bxt_ddi_phy_init(struct drm_i915_private
*dev_priv
, enum dpio_phy phy
);
3391 void bxt_ddi_phy_uninit(struct drm_i915_private
*dev_priv
, enum dpio_phy phy
);
3392 bool bxt_ddi_phy_is_enabled(struct drm_i915_private
*dev_priv
,
3394 bool bxt_ddi_phy_verify_state(struct drm_i915_private
*dev_priv
,
3396 uint8_t bxt_ddi_phy_calc_lane_lat_optim_mask(uint8_t lane_count
);
3397 void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder
*encoder
,
3398 uint8_t lane_lat_optim_mask
);
3399 uint8_t bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder
*encoder
);
3401 void chv_set_phy_signal_level(struct intel_encoder
*encoder
,
3402 u32 deemph_reg_value
, u32 margin_reg_value
,
3403 bool uniq_trans_scale
);
3404 void chv_data_lane_soft_reset(struct intel_encoder
*encoder
,
3405 const struct intel_crtc_state
*crtc_state
,
3407 void chv_phy_pre_pll_enable(struct intel_encoder
*encoder
,
3408 const struct intel_crtc_state
*crtc_state
);
3409 void chv_phy_pre_encoder_enable(struct intel_encoder
*encoder
,
3410 const struct intel_crtc_state
*crtc_state
);
3411 void chv_phy_release_cl2_override(struct intel_encoder
*encoder
);
3412 void chv_phy_post_pll_disable(struct intel_encoder
*encoder
,
3413 const struct intel_crtc_state
*old_crtc_state
);
3415 void vlv_set_phy_signal_level(struct intel_encoder
*encoder
,
3416 u32 demph_reg_value
, u32 preemph_reg_value
,
3417 u32 uniqtranscale_reg_value
, u32 tx3_demph
);
3418 void vlv_phy_pre_pll_enable(struct intel_encoder
*encoder
,
3419 const struct intel_crtc_state
*crtc_state
);
3420 void vlv_phy_pre_encoder_enable(struct intel_encoder
*encoder
,
3421 const struct intel_crtc_state
*crtc_state
);
3422 void vlv_phy_reset_lanes(struct intel_encoder
*encoder
,
3423 const struct intel_crtc_state
*old_crtc_state
);
3425 /* intel_combo_phy.c */
3426 void icl_combo_phys_init(struct drm_i915_private
*dev_priv
);
3427 void icl_combo_phys_uninit(struct drm_i915_private
*dev_priv
);
3428 void cnl_combo_phys_init(struct drm_i915_private
*dev_priv
);
3429 void cnl_combo_phys_uninit(struct drm_i915_private
*dev_priv
);
3431 int intel_gpu_freq(struct drm_i915_private
*dev_priv
, int val
);
3432 int intel_freq_opcode(struct drm_i915_private
*dev_priv
, int val
);
3433 u64
intel_rc6_residency_ns(struct drm_i915_private
*dev_priv
,
3434 const i915_reg_t reg
);
3436 u32
intel_get_cagf(struct drm_i915_private
*dev_priv
, u32 rpstat1
);
3438 static inline u64
intel_rc6_residency_us(struct drm_i915_private
*dev_priv
,
3439 const i915_reg_t reg
)
3441 return DIV_ROUND_UP_ULL(intel_rc6_residency_ns(dev_priv
, reg
), 1000);
3444 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3445 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3447 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3448 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3449 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3450 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3452 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3453 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3454 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3455 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3457 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3458 * will be implemented using 2 32-bit writes in an arbitrary order with
3459 * an arbitrary delay between them. This can cause the hardware to
3460 * act upon the intermediate value, possibly leading to corruption and
3461 * machine death. For this reason we do not support I915_WRITE64, or
3462 * dev_priv->uncore.funcs.mmio_writeq.
3464 * When reading a 64-bit value as two 32-bit values, the delay may cause
3465 * the two reads to mismatch, e.g. a timestamp overflowing. Also note that
3466 * occasionally a 64-bit register does not actualy support a full readq
3467 * and must be read using two 32-bit reads.
3469 * You have been warned.
3471 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3473 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3474 u32 upper, lower, old_upper, loop = 0; \
3475 upper = I915_READ(upper_reg); \
3477 old_upper = upper; \
3478 lower = I915_READ(lower_reg); \
3479 upper = I915_READ(upper_reg); \
3480 } while (upper != old_upper && loop++ < 2); \
3481 (u64)upper << 32 | lower; })
3483 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3484 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3486 #define __raw_read(x, s) \
3487 static inline uint##x##_t __raw_i915_read##x(const struct drm_i915_private *dev_priv, \
3490 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3493 #define __raw_write(x, s) \
3494 static inline void __raw_i915_write##x(const struct drm_i915_private *dev_priv, \
3495 i915_reg_t reg, uint##x##_t val) \
3497 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3512 /* These are untraced mmio-accessors that are only valid to be used inside
3513 * critical sections, such as inside IRQ handlers, where forcewake is explicitly
3516 * Think twice, and think again, before using these.
3518 * As an example, these accessors can possibly be used between:
3520 * spin_lock_irq(&dev_priv->uncore.lock);
3521 * intel_uncore_forcewake_get__locked();
3525 * intel_uncore_forcewake_put__locked();
3526 * spin_unlock_irq(&dev_priv->uncore.lock);
3529 * Note: some registers may not need forcewake held, so
3530 * intel_uncore_forcewake_{get,put} can be omitted, see
3531 * intel_uncore_forcewake_for_reg().
3533 * Certain architectures will die if the same cacheline is concurrently accessed
3534 * by different clients (e.g. on Ivybridge). Access to registers should
3535 * therefore generally be serialised, by either the dev_priv->uncore.lock or
3536 * a more localised lock guarding all access to that bank of registers.
3538 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
3539 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3540 #define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
3541 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3543 /* "Broadcast RGB" property */
3544 #define INTEL_BROADCAST_RGB_AUTO 0
3545 #define INTEL_BROADCAST_RGB_FULL 1
3546 #define INTEL_BROADCAST_RGB_LIMITED 2
3548 static inline i915_reg_t
i915_vgacntrl_reg(struct drm_i915_private
*dev_priv
)
3550 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
3551 return VLV_VGACNTRL
;
3552 else if (INTEL_GEN(dev_priv
) >= 5)
3553 return CPU_VGACNTRL
;
3558 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m
)
3560 unsigned long j
= msecs_to_jiffies(m
);
3562 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
3565 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n
)
3567 /* nsecs_to_jiffies64() does not guard against overflow */
3568 if (NSEC_PER_SEC
% HZ
&&
3569 div_u64(n
, NSEC_PER_SEC
) >= MAX_JIFFY_OFFSET
/ HZ
)
3570 return MAX_JIFFY_OFFSET
;
3572 return min_t(u64
, MAX_JIFFY_OFFSET
, nsecs_to_jiffies64(n
) + 1);
3576 * If you need to wait X milliseconds between events A and B, but event B
3577 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3578 * when event A happened, then just before event B you call this function and
3579 * pass the timestamp as the first argument, and X as the second argument.
3582 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies
, int to_wait_ms
)
3584 unsigned long target_jiffies
, tmp_jiffies
, remaining_jiffies
;
3587 * Don't re-read the value of "jiffies" every time since it may change
3588 * behind our back and break the math.
3590 tmp_jiffies
= jiffies
;
3591 target_jiffies
= timestamp_jiffies
+
3592 msecs_to_jiffies_timeout(to_wait_ms
);
3594 if (time_after(target_jiffies
, tmp_jiffies
)) {
3595 remaining_jiffies
= target_jiffies
- tmp_jiffies
;
3596 while (remaining_jiffies
)
3598 schedule_timeout_uninterruptible(remaining_jiffies
);
3603 __i915_request_irq_complete(const struct i915_request
*rq
)
3605 struct intel_engine_cs
*engine
= rq
->engine
;
3608 /* Note that the engine may have wrapped around the seqno, and
3609 * so our request->global_seqno will be ahead of the hardware,
3610 * even though it completed the request before wrapping. We catch
3611 * this by kicking all the waiters before resetting the seqno
3612 * in hardware, and also signal the fence.
3614 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT
, &rq
->fence
.flags
))
3617 /* The request was dequeued before we were awoken. We check after
3618 * inspecting the hw to confirm that this was the same request
3619 * that generated the HWS update. The memory barriers within
3620 * the request execution are sufficient to ensure that a check
3621 * after reading the value from hw matches this request.
3623 seqno
= i915_request_global_seqno(rq
);
3627 /* Before we do the heavier coherent read of the seqno,
3628 * check the value (hopefully) in the CPU cacheline.
3630 if (__i915_request_completed(rq
, seqno
))
3633 /* Ensure our read of the seqno is coherent so that we
3634 * do not "miss an interrupt" (i.e. if this is the last
3635 * request and the seqno write from the GPU is not visible
3636 * by the time the interrupt fires, we will see that the
3637 * request is incomplete and go back to sleep awaiting
3638 * another interrupt that will never come.)
3640 * Strictly, we only need to do this once after an interrupt,
3641 * but it is easier and safer to do it every time the waiter
3644 if (engine
->irq_seqno_barrier
&&
3645 test_and_clear_bit(ENGINE_IRQ_BREADCRUMB
, &engine
->irq_posted
)) {
3646 struct intel_breadcrumbs
*b
= &engine
->breadcrumbs
;
3648 /* The ordering of irq_posted versus applying the barrier
3649 * is crucial. The clearing of the current irq_posted must
3650 * be visible before we perform the barrier operation,
3651 * such that if a subsequent interrupt arrives, irq_posted
3652 * is reasserted and our task rewoken (which causes us to
3653 * do another __i915_request_irq_complete() immediately
3654 * and reapply the barrier). Conversely, if the clear
3655 * occurs after the barrier, then an interrupt that arrived
3656 * whilst we waited on the barrier would not trigger a
3657 * barrier on the next pass, and the read may not see the
3660 engine
->irq_seqno_barrier(engine
);
3662 /* If we consume the irq, but we are no longer the bottom-half,
3663 * the real bottom-half may not have serialised their own
3664 * seqno check with the irq-barrier (i.e. may have inspected
3665 * the seqno before we believe it coherent since they see
3666 * irq_posted == false but we are still running).
3668 spin_lock_irq(&b
->irq_lock
);
3669 if (b
->irq_wait
&& b
->irq_wait
->tsk
!= current
)
3670 /* Note that if the bottom-half is changed as we
3671 * are sending the wake-up, the new bottom-half will
3672 * be woken by whomever made the change. We only have
3673 * to worry about when we steal the irq-posted for
3676 wake_up_process(b
->irq_wait
->tsk
);
3677 spin_unlock_irq(&b
->irq_lock
);
3679 if (__i915_request_completed(rq
, seqno
))
3686 void i915_memcpy_init_early(struct drm_i915_private
*dev_priv
);
3687 bool i915_memcpy_from_wc(void *dst
, const void *src
, unsigned long len
);
3689 /* The movntdqa instructions used for memcpy-from-wc require 16-byte alignment,
3690 * as well as SSE4.1 support. i915_memcpy_from_wc() will report if it cannot
3691 * perform the operation. To check beforehand, pass in the parameters to
3692 * to i915_can_memcpy_from_wc() - since we only care about the low 4 bits,
3693 * you only need to pass in the minor offsets, page-aligned pointers are
3696 * For just checking for SSE4.1, in the foreknowledge that the future use
3697 * will be correctly aligned, just use i915_has_memcpy_from_wc().
3699 #define i915_can_memcpy_from_wc(dst, src, len) \
3700 i915_memcpy_from_wc((void *)((unsigned long)(dst) | (unsigned long)(src) | (len)), NULL, 0)
3702 #define i915_has_memcpy_from_wc() \
3703 i915_memcpy_from_wc(NULL, NULL, 0)
3706 int remap_io_mapping(struct vm_area_struct
*vma
,
3707 unsigned long addr
, unsigned long pfn
, unsigned long size
,
3708 struct io_mapping
*iomap
);
3710 static inline int intel_hws_csb_write_index(struct drm_i915_private
*i915
)
3712 if (INTEL_GEN(i915
) >= 10)
3713 return CNL_HWS_CSB_WRITE_INDEX
;
3715 return I915_HWS_CSB_WRITE_INDEX
;
3718 static inline u32
i915_scratch_offset(const struct drm_i915_private
*i915
)
3720 return i915_ggtt_offset(i915
->gt
.scratch
);