2 * Copyright © 2008,2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Chris Wilson <chris@chris-wilson.co.uk>
29 #include <linux/dma_remapping.h>
30 #include <linux/reservation.h>
31 #include <linux/uaccess.h>
34 #include <drm/i915_drm.h>
37 #include "i915_gem_dmabuf.h"
38 #include "i915_trace.h"
39 #include "intel_drv.h"
40 #include "intel_frontbuffer.h"
42 #define DBG_USE_CPU_RELOC 0 /* -1 force GTT relocs; 1 force CPU relocs */
44 #define __EXEC_OBJECT_HAS_PIN (1<<31)
45 #define __EXEC_OBJECT_HAS_FENCE (1<<30)
46 #define __EXEC_OBJECT_NEEDS_MAP (1<<29)
47 #define __EXEC_OBJECT_NEEDS_BIAS (1<<28)
48 #define __EXEC_OBJECT_INTERNAL_FLAGS (0xf<<28) /* all of the above */
50 #define BATCH_OFFSET_BIAS (256*1024)
52 struct i915_execbuffer_params
{
53 struct drm_device
*dev
;
54 struct drm_file
*file
;
55 struct i915_vma
*batch
;
57 u32 args_batch_start_offset
;
58 struct intel_engine_cs
*engine
;
59 struct i915_gem_context
*ctx
;
60 struct drm_i915_gem_request
*request
;
64 struct drm_i915_private
*i915
;
65 struct list_head vmas
;
68 struct i915_vma
*lut
[0];
69 struct hlist_head buckets
[0];
73 static struct eb_vmas
*
74 eb_create(struct drm_i915_private
*i915
,
75 struct drm_i915_gem_execbuffer2
*args
)
77 struct eb_vmas
*eb
= NULL
;
79 if (args
->flags
& I915_EXEC_HANDLE_LUT
) {
80 unsigned size
= args
->buffer_count
;
81 size
*= sizeof(struct i915_vma
*);
82 size
+= sizeof(struct eb_vmas
);
83 eb
= kmalloc(size
, GFP_TEMPORARY
| __GFP_NOWARN
| __GFP_NORETRY
);
87 unsigned size
= args
->buffer_count
;
88 unsigned count
= PAGE_SIZE
/ sizeof(struct hlist_head
) / 2;
89 BUILD_BUG_ON_NOT_POWER_OF_2(PAGE_SIZE
/ sizeof(struct hlist_head
));
90 while (count
> 2*size
)
92 eb
= kzalloc(count
*sizeof(struct hlist_head
) +
93 sizeof(struct eb_vmas
),
100 eb
->and = -args
->buffer_count
;
103 INIT_LIST_HEAD(&eb
->vmas
);
108 eb_reset(struct eb_vmas
*eb
)
111 memset(eb
->buckets
, 0, (eb
->and+1)*sizeof(struct hlist_head
));
114 static struct i915_vma
*
115 eb_get_batch(struct eb_vmas
*eb
)
117 struct i915_vma
*vma
= list_entry(eb
->vmas
.prev
, typeof(*vma
), exec_list
);
120 * SNA is doing fancy tricks with compressing batch buffers, which leads
121 * to negative relocation deltas. Usually that works out ok since the
122 * relocate address is still positive, except when the batch is placed
123 * very low in the GTT. Ensure this doesn't happen.
125 * Note that actual hangs have only been observed on gen7, but for
126 * paranoia do it everywhere.
128 if ((vma
->exec_entry
->flags
& EXEC_OBJECT_PINNED
) == 0)
129 vma
->exec_entry
->flags
|= __EXEC_OBJECT_NEEDS_BIAS
;
135 eb_lookup_vmas(struct eb_vmas
*eb
,
136 struct drm_i915_gem_exec_object2
*exec
,
137 const struct drm_i915_gem_execbuffer2
*args
,
138 struct i915_address_space
*vm
,
139 struct drm_file
*file
)
141 struct drm_i915_gem_object
*obj
;
142 struct list_head objects
;
145 INIT_LIST_HEAD(&objects
);
146 spin_lock(&file
->table_lock
);
147 /* Grab a reference to the object and release the lock so we can lookup
148 * or create the VMA without using GFP_ATOMIC */
149 for (i
= 0; i
< args
->buffer_count
; i
++) {
150 obj
= to_intel_bo(idr_find(&file
->object_idr
, exec
[i
].handle
));
152 spin_unlock(&file
->table_lock
);
153 DRM_DEBUG("Invalid object handle %d at index %d\n",
159 if (!list_empty(&obj
->obj_exec_link
)) {
160 spin_unlock(&file
->table_lock
);
161 DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n",
162 obj
, exec
[i
].handle
, i
);
167 i915_gem_object_get(obj
);
168 list_add_tail(&obj
->obj_exec_link
, &objects
);
170 spin_unlock(&file
->table_lock
);
173 while (!list_empty(&objects
)) {
174 struct i915_vma
*vma
;
176 obj
= list_first_entry(&objects
,
177 struct drm_i915_gem_object
,
181 * NOTE: We can leak any vmas created here when something fails
182 * later on. But that's no issue since vma_unbind can deal with
183 * vmas which are not actually bound. And since only
184 * lookup_or_create exists as an interface to get at the vma
185 * from the (obj, vm) we don't run the risk of creating
186 * duplicated vmas for the same vm.
188 vma
= i915_gem_obj_lookup_or_create_vma(obj
, vm
, NULL
);
189 if (unlikely(IS_ERR(vma
))) {
190 DRM_DEBUG("Failed to lookup VMA\n");
195 /* Transfer ownership from the objects list to the vmas list. */
196 list_add_tail(&vma
->exec_list
, &eb
->vmas
);
197 list_del_init(&obj
->obj_exec_link
);
199 vma
->exec_entry
= &exec
[i
];
203 uint32_t handle
= args
->flags
& I915_EXEC_HANDLE_LUT
? i
: exec
[i
].handle
;
204 vma
->exec_handle
= handle
;
205 hlist_add_head(&vma
->exec_node
,
206 &eb
->buckets
[handle
& eb
->and]);
215 while (!list_empty(&objects
)) {
216 obj
= list_first_entry(&objects
,
217 struct drm_i915_gem_object
,
219 list_del_init(&obj
->obj_exec_link
);
220 i915_gem_object_put(obj
);
223 * Objects already transfered to the vmas list will be unreferenced by
230 static struct i915_vma
*eb_get_vma(struct eb_vmas
*eb
, unsigned long handle
)
233 if (handle
>= -eb
->and)
235 return eb
->lut
[handle
];
237 struct hlist_head
*head
;
238 struct i915_vma
*vma
;
240 head
= &eb
->buckets
[handle
& eb
->and];
241 hlist_for_each_entry(vma
, head
, exec_node
) {
242 if (vma
->exec_handle
== handle
)
250 i915_gem_execbuffer_unreserve_vma(struct i915_vma
*vma
)
252 struct drm_i915_gem_exec_object2
*entry
;
254 if (!drm_mm_node_allocated(&vma
->node
))
257 entry
= vma
->exec_entry
;
259 if (entry
->flags
& __EXEC_OBJECT_HAS_FENCE
)
260 i915_vma_unpin_fence(vma
);
262 if (entry
->flags
& __EXEC_OBJECT_HAS_PIN
)
263 __i915_vma_unpin(vma
);
265 entry
->flags
&= ~(__EXEC_OBJECT_HAS_FENCE
| __EXEC_OBJECT_HAS_PIN
);
268 static void eb_destroy(struct eb_vmas
*eb
)
270 while (!list_empty(&eb
->vmas
)) {
271 struct i915_vma
*vma
;
273 vma
= list_first_entry(&eb
->vmas
,
276 list_del_init(&vma
->exec_list
);
277 i915_gem_execbuffer_unreserve_vma(vma
);
283 static inline int use_cpu_reloc(struct drm_i915_gem_object
*obj
)
285 if (!i915_gem_object_has_struct_page(obj
))
288 if (DBG_USE_CPU_RELOC
)
289 return DBG_USE_CPU_RELOC
> 0;
291 return (HAS_LLC(obj
->base
.dev
) ||
292 obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
||
293 obj
->cache_level
!= I915_CACHE_NONE
);
296 /* Used to convert any address to canonical form.
297 * Starting from gen8, some commands (e.g. STATE_BASE_ADDRESS,
298 * MI_LOAD_REGISTER_MEM and others, see Broadwell PRM Vol2a) require the
299 * addresses to be in a canonical form:
300 * "GraphicsAddress[63:48] are ignored by the HW and assumed to be in correct
301 * canonical form [63:48] == [47]."
303 #define GEN8_HIGH_ADDRESS_BIT 47
304 static inline uint64_t gen8_canonical_addr(uint64_t address
)
306 return sign_extend64(address
, GEN8_HIGH_ADDRESS_BIT
);
309 static inline uint64_t gen8_noncanonical_addr(uint64_t address
)
311 return address
& ((1ULL << (GEN8_HIGH_ADDRESS_BIT
+ 1)) - 1);
314 static inline uint64_t
315 relocation_target(const struct drm_i915_gem_relocation_entry
*reloc
,
316 uint64_t target_offset
)
318 return gen8_canonical_addr((int)reloc
->delta
+ target_offset
);
322 struct drm_i915_private
*i915
;
323 struct drm_mm_node node
;
326 bool use_64bit_reloc
;
329 static void reloc_cache_init(struct reloc_cache
*cache
,
330 struct drm_i915_private
*i915
)
335 cache
->use_64bit_reloc
= INTEL_GEN(cache
->i915
) >= 8;
336 cache
->node
.allocated
= false;
339 static inline void *unmask_page(unsigned long p
)
341 return (void *)(uintptr_t)(p
& PAGE_MASK
);
344 static inline unsigned int unmask_flags(unsigned long p
)
346 return p
& ~PAGE_MASK
;
349 #define KMAP 0x4 /* after CLFLUSH_FLAGS */
351 static void reloc_cache_fini(struct reloc_cache
*cache
)
358 vaddr
= unmask_page(cache
->vaddr
);
359 if (cache
->vaddr
& KMAP
) {
360 if (cache
->vaddr
& CLFLUSH_AFTER
)
363 kunmap_atomic(vaddr
);
364 i915_gem_obj_finish_shmem_access((struct drm_i915_gem_object
*)cache
->node
.mm
);
367 io_mapping_unmap_atomic((void __iomem
*)vaddr
);
368 if (cache
->node
.allocated
) {
369 struct i915_ggtt
*ggtt
= &cache
->i915
->ggtt
;
371 ggtt
->base
.clear_range(&ggtt
->base
,
374 drm_mm_remove_node(&cache
->node
);
376 i915_vma_unpin((struct i915_vma
*)cache
->node
.mm
);
381 static void *reloc_kmap(struct drm_i915_gem_object
*obj
,
382 struct reloc_cache
*cache
,
388 kunmap_atomic(unmask_page(cache
->vaddr
));
390 unsigned int flushes
;
393 ret
= i915_gem_obj_prepare_shmem_write(obj
, &flushes
);
397 BUILD_BUG_ON(KMAP
& CLFLUSH_FLAGS
);
398 BUILD_BUG_ON((KMAP
| CLFLUSH_FLAGS
) & PAGE_MASK
);
400 cache
->vaddr
= flushes
| KMAP
;
401 cache
->node
.mm
= (void *)obj
;
406 vaddr
= kmap_atomic(i915_gem_object_get_dirty_page(obj
, page
));
407 cache
->vaddr
= unmask_flags(cache
->vaddr
) | (unsigned long)vaddr
;
413 static void *reloc_iomap(struct drm_i915_gem_object
*obj
,
414 struct reloc_cache
*cache
,
417 struct i915_ggtt
*ggtt
= &cache
->i915
->ggtt
;
418 unsigned long offset
;
421 if (cache
->node
.allocated
) {
423 ggtt
->base
.insert_page(&ggtt
->base
,
424 i915_gem_object_get_dma_address(obj
, page
),
425 cache
->node
.start
, I915_CACHE_NONE
, 0);
427 return unmask_page(cache
->vaddr
);
431 io_mapping_unmap_atomic((void __force __iomem
*) unmask_page(cache
->vaddr
));
433 struct i915_vma
*vma
;
436 if (use_cpu_reloc(obj
))
439 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
443 vma
= i915_gem_object_ggtt_pin(obj
, NULL
, 0, 0,
444 PIN_MAPPABLE
| PIN_NONBLOCK
);
446 memset(&cache
->node
, 0, sizeof(cache
->node
));
447 ret
= drm_mm_insert_node_in_range_generic
448 (&ggtt
->base
.mm
, &cache
->node
,
450 0, ggtt
->mappable_end
,
451 DRM_MM_SEARCH_DEFAULT
,
452 DRM_MM_CREATE_DEFAULT
);
453 if (ret
) /* no inactive aperture space, use cpu reloc */
456 ret
= i915_vma_put_fence(vma
);
462 cache
->node
.start
= vma
->node
.start
;
463 cache
->node
.mm
= (void *)vma
;
467 offset
= cache
->node
.start
;
468 if (cache
->node
.allocated
) {
469 ggtt
->base
.insert_page(&ggtt
->base
,
470 i915_gem_object_get_dma_address(obj
, page
),
471 offset
, I915_CACHE_NONE
, 0);
473 offset
+= page
<< PAGE_SHIFT
;
476 vaddr
= (void __force
*) io_mapping_map_atomic_wc(&cache
->i915
->ggtt
.mappable
, offset
);
478 cache
->vaddr
= (unsigned long)vaddr
;
483 static void *reloc_vaddr(struct drm_i915_gem_object
*obj
,
484 struct reloc_cache
*cache
,
489 if (cache
->page
== page
) {
490 vaddr
= unmask_page(cache
->vaddr
);
493 if ((cache
->vaddr
& KMAP
) == 0)
494 vaddr
= reloc_iomap(obj
, cache
, page
);
496 vaddr
= reloc_kmap(obj
, cache
, page
);
502 static void clflush_write32(u32
*addr
, u32 value
, unsigned int flushes
)
504 if (unlikely(flushes
& (CLFLUSH_BEFORE
| CLFLUSH_AFTER
))) {
505 if (flushes
& CLFLUSH_BEFORE
) {
512 /* Writes to the same cacheline are serialised by the CPU
513 * (including clflush). On the write path, we only require
514 * that it hits memory in an orderly fashion and place
515 * mb barriers at the start and end of the relocation phase
516 * to ensure ordering of clflush wrt to the system.
518 if (flushes
& CLFLUSH_AFTER
)
525 relocate_entry(struct drm_i915_gem_object
*obj
,
526 const struct drm_i915_gem_relocation_entry
*reloc
,
527 struct reloc_cache
*cache
,
530 u64 offset
= reloc
->offset
;
531 bool wide
= cache
->use_64bit_reloc
;
534 target_offset
= relocation_target(reloc
, target_offset
);
536 vaddr
= reloc_vaddr(obj
, cache
, offset
>> PAGE_SHIFT
);
538 return PTR_ERR(vaddr
);
540 clflush_write32(vaddr
+ offset_in_page(offset
),
541 lower_32_bits(target_offset
),
545 offset
+= sizeof(u32
);
546 target_offset
>>= 32;
555 i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object
*obj
,
557 struct drm_i915_gem_relocation_entry
*reloc
,
558 struct reloc_cache
*cache
)
560 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
561 struct drm_gem_object
*target_obj
;
562 struct drm_i915_gem_object
*target_i915_obj
;
563 struct i915_vma
*target_vma
;
564 uint64_t target_offset
;
567 /* we've already hold a reference to all valid objects */
568 target_vma
= eb_get_vma(eb
, reloc
->target_handle
);
569 if (unlikely(target_vma
== NULL
))
571 target_i915_obj
= target_vma
->obj
;
572 target_obj
= &target_vma
->obj
->base
;
574 target_offset
= gen8_canonical_addr(target_vma
->node
.start
);
576 /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and
577 * pipe_control writes because the gpu doesn't properly redirect them
578 * through the ppgtt for non_secure batchbuffers. */
579 if (unlikely(IS_GEN6(dev_priv
) &&
580 reloc
->write_domain
== I915_GEM_DOMAIN_INSTRUCTION
)) {
581 ret
= i915_vma_bind(target_vma
, target_i915_obj
->cache_level
,
583 if (WARN_ONCE(ret
, "Unexpected failure to bind target VMA!"))
587 /* Validate that the target is in a valid r/w GPU domain */
588 if (unlikely(reloc
->write_domain
& (reloc
->write_domain
- 1))) {
589 DRM_DEBUG("reloc with multiple write domains: "
590 "obj %p target %d offset %d "
591 "read %08x write %08x",
592 obj
, reloc
->target_handle
,
595 reloc
->write_domain
);
598 if (unlikely((reloc
->write_domain
| reloc
->read_domains
)
599 & ~I915_GEM_GPU_DOMAINS
)) {
600 DRM_DEBUG("reloc with read/write non-GPU domains: "
601 "obj %p target %d offset %d "
602 "read %08x write %08x",
603 obj
, reloc
->target_handle
,
606 reloc
->write_domain
);
610 target_obj
->pending_read_domains
|= reloc
->read_domains
;
611 target_obj
->pending_write_domain
|= reloc
->write_domain
;
613 /* If the relocation already has the right value in it, no
614 * more work needs to be done.
616 if (target_offset
== reloc
->presumed_offset
)
619 /* Check that the relocation address is valid... */
620 if (unlikely(reloc
->offset
>
621 obj
->base
.size
- (cache
->use_64bit_reloc
? 8 : 4))) {
622 DRM_DEBUG("Relocation beyond object bounds: "
623 "obj %p target %d offset %d size %d.\n",
624 obj
, reloc
->target_handle
,
626 (int) obj
->base
.size
);
629 if (unlikely(reloc
->offset
& 3)) {
630 DRM_DEBUG("Relocation not 4-byte aligned: "
631 "obj %p target %d offset %d.\n",
632 obj
, reloc
->target_handle
,
633 (int) reloc
->offset
);
637 ret
= relocate_entry(obj
, reloc
, cache
, target_offset
);
641 /* and update the user's relocation entry */
642 reloc
->presumed_offset
= target_offset
;
647 i915_gem_execbuffer_relocate_vma(struct i915_vma
*vma
,
650 #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry))
651 struct drm_i915_gem_relocation_entry stack_reloc
[N_RELOC(512)];
652 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
653 struct drm_i915_gem_exec_object2
*entry
= vma
->exec_entry
;
654 struct reloc_cache cache
;
657 user_relocs
= u64_to_user_ptr(entry
->relocs_ptr
);
658 reloc_cache_init(&cache
, eb
->i915
);
660 remain
= entry
->relocation_count
;
662 struct drm_i915_gem_relocation_entry
*r
= stack_reloc
;
663 unsigned long unwritten
;
666 count
= min_t(unsigned int, remain
, ARRAY_SIZE(stack_reloc
));
669 /* This is the fast path and we cannot handle a pagefault
670 * whilst holding the struct mutex lest the user pass in the
671 * relocations contained within a mmaped bo. For in such a case
672 * we, the page fault handler would call i915_gem_fault() and
673 * we would try to acquire the struct mutex again. Obviously
674 * this is bad and so lockdep complains vehemently.
677 unwritten
= __copy_from_user_inatomic(r
, user_relocs
, count
*sizeof(r
[0]));
679 if (unlikely(unwritten
)) {
685 u64 offset
= r
->presumed_offset
;
687 ret
= i915_gem_execbuffer_relocate_entry(vma
->obj
, eb
, r
, &cache
);
691 if (r
->presumed_offset
!= offset
) {
693 unwritten
= __put_user(r
->presumed_offset
,
694 &user_relocs
->presumed_offset
);
696 if (unlikely(unwritten
)) {
697 /* Note that reporting an error now
698 * leaves everything in an inconsistent
699 * state as we have *already* changed
700 * the relocation value inside the
701 * object. As we have not changed the
702 * reloc.presumed_offset or will not
703 * change the execobject.offset, on the
704 * call we may not rewrite the value
705 * inside the object, leaving it
706 * dangling and causing a GPU hang.
719 reloc_cache_fini(&cache
);
725 i915_gem_execbuffer_relocate_vma_slow(struct i915_vma
*vma
,
727 struct drm_i915_gem_relocation_entry
*relocs
)
729 const struct drm_i915_gem_exec_object2
*entry
= vma
->exec_entry
;
730 struct reloc_cache cache
;
733 reloc_cache_init(&cache
, eb
->i915
);
734 for (i
= 0; i
< entry
->relocation_count
; i
++) {
735 ret
= i915_gem_execbuffer_relocate_entry(vma
->obj
, eb
, &relocs
[i
], &cache
);
739 reloc_cache_fini(&cache
);
745 i915_gem_execbuffer_relocate(struct eb_vmas
*eb
)
747 struct i915_vma
*vma
;
750 list_for_each_entry(vma
, &eb
->vmas
, exec_list
) {
751 ret
= i915_gem_execbuffer_relocate_vma(vma
, eb
);
759 static bool only_mappable_for_reloc(unsigned int flags
)
761 return (flags
& (EXEC_OBJECT_NEEDS_FENCE
| __EXEC_OBJECT_NEEDS_MAP
)) ==
762 __EXEC_OBJECT_NEEDS_MAP
;
766 i915_gem_execbuffer_reserve_vma(struct i915_vma
*vma
,
767 struct intel_engine_cs
*engine
,
770 struct drm_i915_gem_object
*obj
= vma
->obj
;
771 struct drm_i915_gem_exec_object2
*entry
= vma
->exec_entry
;
776 if (entry
->flags
& EXEC_OBJECT_NEEDS_GTT
)
779 if (!drm_mm_node_allocated(&vma
->node
)) {
780 /* Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset,
781 * limit address to the first 4GBs for unflagged objects.
783 if ((entry
->flags
& EXEC_OBJECT_SUPPORTS_48B_ADDRESS
) == 0)
784 flags
|= PIN_ZONE_4G
;
785 if (entry
->flags
& __EXEC_OBJECT_NEEDS_MAP
)
786 flags
|= PIN_GLOBAL
| PIN_MAPPABLE
;
787 if (entry
->flags
& __EXEC_OBJECT_NEEDS_BIAS
)
788 flags
|= BATCH_OFFSET_BIAS
| PIN_OFFSET_BIAS
;
789 if (entry
->flags
& EXEC_OBJECT_PINNED
)
790 flags
|= entry
->offset
| PIN_OFFSET_FIXED
;
791 if ((flags
& PIN_MAPPABLE
) == 0)
795 ret
= i915_vma_pin(vma
,
799 if ((ret
== -ENOSPC
|| ret
== -E2BIG
) &&
800 only_mappable_for_reloc(entry
->flags
))
801 ret
= i915_vma_pin(vma
,
804 flags
& ~PIN_MAPPABLE
);
808 entry
->flags
|= __EXEC_OBJECT_HAS_PIN
;
810 if (entry
->flags
& EXEC_OBJECT_NEEDS_FENCE
) {
811 ret
= i915_vma_get_fence(vma
);
815 if (i915_vma_pin_fence(vma
))
816 entry
->flags
|= __EXEC_OBJECT_HAS_FENCE
;
819 if (entry
->offset
!= vma
->node
.start
) {
820 entry
->offset
= vma
->node
.start
;
824 if (entry
->flags
& EXEC_OBJECT_WRITE
) {
825 obj
->base
.pending_read_domains
= I915_GEM_DOMAIN_RENDER
;
826 obj
->base
.pending_write_domain
= I915_GEM_DOMAIN_RENDER
;
833 need_reloc_mappable(struct i915_vma
*vma
)
835 struct drm_i915_gem_exec_object2
*entry
= vma
->exec_entry
;
837 if (entry
->relocation_count
== 0)
840 if (!i915_vma_is_ggtt(vma
))
843 /* See also use_cpu_reloc() */
844 if (HAS_LLC(vma
->obj
->base
.dev
))
847 if (vma
->obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
)
854 eb_vma_misplaced(struct i915_vma
*vma
)
856 struct drm_i915_gem_exec_object2
*entry
= vma
->exec_entry
;
858 WARN_ON(entry
->flags
& __EXEC_OBJECT_NEEDS_MAP
&&
859 !i915_vma_is_ggtt(vma
));
861 if (entry
->alignment
&&
862 vma
->node
.start
& (entry
->alignment
- 1))
865 if (vma
->node
.size
< entry
->pad_to_size
)
868 if (entry
->flags
& EXEC_OBJECT_PINNED
&&
869 vma
->node
.start
!= entry
->offset
)
872 if (entry
->flags
& __EXEC_OBJECT_NEEDS_BIAS
&&
873 vma
->node
.start
< BATCH_OFFSET_BIAS
)
876 /* avoid costly ping-pong once a batch bo ended up non-mappable */
877 if (entry
->flags
& __EXEC_OBJECT_NEEDS_MAP
&&
878 !i915_vma_is_map_and_fenceable(vma
))
879 return !only_mappable_for_reloc(entry
->flags
);
881 if ((entry
->flags
& EXEC_OBJECT_SUPPORTS_48B_ADDRESS
) == 0 &&
882 (vma
->node
.start
+ vma
->node
.size
- 1) >> 32)
889 i915_gem_execbuffer_reserve(struct intel_engine_cs
*engine
,
890 struct list_head
*vmas
,
891 struct i915_gem_context
*ctx
,
894 struct drm_i915_gem_object
*obj
;
895 struct i915_vma
*vma
;
896 struct i915_address_space
*vm
;
897 struct list_head ordered_vmas
;
898 struct list_head pinned_vmas
;
899 bool has_fenced_gpu_access
= INTEL_GEN(engine
->i915
) < 4;
902 vm
= list_first_entry(vmas
, struct i915_vma
, exec_list
)->vm
;
904 INIT_LIST_HEAD(&ordered_vmas
);
905 INIT_LIST_HEAD(&pinned_vmas
);
906 while (!list_empty(vmas
)) {
907 struct drm_i915_gem_exec_object2
*entry
;
908 bool need_fence
, need_mappable
;
910 vma
= list_first_entry(vmas
, struct i915_vma
, exec_list
);
912 entry
= vma
->exec_entry
;
914 if (ctx
->flags
& CONTEXT_NO_ZEROMAP
)
915 entry
->flags
|= __EXEC_OBJECT_NEEDS_BIAS
;
917 if (!has_fenced_gpu_access
)
918 entry
->flags
&= ~EXEC_OBJECT_NEEDS_FENCE
;
920 entry
->flags
& EXEC_OBJECT_NEEDS_FENCE
&&
921 i915_gem_object_is_tiled(obj
);
922 need_mappable
= need_fence
|| need_reloc_mappable(vma
);
924 if (entry
->flags
& EXEC_OBJECT_PINNED
)
925 list_move_tail(&vma
->exec_list
, &pinned_vmas
);
926 else if (need_mappable
) {
927 entry
->flags
|= __EXEC_OBJECT_NEEDS_MAP
;
928 list_move(&vma
->exec_list
, &ordered_vmas
);
930 list_move_tail(&vma
->exec_list
, &ordered_vmas
);
932 obj
->base
.pending_read_domains
= I915_GEM_GPU_DOMAINS
& ~I915_GEM_DOMAIN_COMMAND
;
933 obj
->base
.pending_write_domain
= 0;
935 list_splice(&ordered_vmas
, vmas
);
936 list_splice(&pinned_vmas
, vmas
);
938 /* Attempt to pin all of the buffers into the GTT.
939 * This is done in 3 phases:
941 * 1a. Unbind all objects that do not match the GTT constraints for
942 * the execbuffer (fenceable, mappable, alignment etc).
943 * 1b. Increment pin count for already bound objects.
944 * 2. Bind new objects.
945 * 3. Decrement pin count.
947 * This avoid unnecessary unbinding of later objects in order to make
948 * room for the earlier objects *unless* we need to defragment.
954 /* Unbind any ill-fitting objects or pin. */
955 list_for_each_entry(vma
, vmas
, exec_list
) {
956 if (!drm_mm_node_allocated(&vma
->node
))
959 if (eb_vma_misplaced(vma
))
960 ret
= i915_vma_unbind(vma
);
962 ret
= i915_gem_execbuffer_reserve_vma(vma
,
969 /* Bind fresh objects */
970 list_for_each_entry(vma
, vmas
, exec_list
) {
971 if (drm_mm_node_allocated(&vma
->node
))
974 ret
= i915_gem_execbuffer_reserve_vma(vma
, engine
,
981 if (ret
!= -ENOSPC
|| retry
++)
984 /* Decrement pin count for bound objects */
985 list_for_each_entry(vma
, vmas
, exec_list
)
986 i915_gem_execbuffer_unreserve_vma(vma
);
988 ret
= i915_gem_evict_vm(vm
, true);
995 i915_gem_execbuffer_relocate_slow(struct drm_device
*dev
,
996 struct drm_i915_gem_execbuffer2
*args
,
997 struct drm_file
*file
,
998 struct intel_engine_cs
*engine
,
1000 struct drm_i915_gem_exec_object2
*exec
,
1001 struct i915_gem_context
*ctx
)
1003 struct drm_i915_gem_relocation_entry
*reloc
;
1004 struct i915_address_space
*vm
;
1005 struct i915_vma
*vma
;
1009 unsigned count
= args
->buffer_count
;
1011 vm
= list_first_entry(&eb
->vmas
, struct i915_vma
, exec_list
)->vm
;
1013 /* We may process another execbuffer during the unlock... */
1014 while (!list_empty(&eb
->vmas
)) {
1015 vma
= list_first_entry(&eb
->vmas
, struct i915_vma
, exec_list
);
1016 list_del_init(&vma
->exec_list
);
1017 i915_gem_execbuffer_unreserve_vma(vma
);
1021 mutex_unlock(&dev
->struct_mutex
);
1024 for (i
= 0; i
< count
; i
++)
1025 total
+= exec
[i
].relocation_count
;
1027 reloc_offset
= drm_malloc_ab(count
, sizeof(*reloc_offset
));
1028 reloc
= drm_malloc_ab(total
, sizeof(*reloc
));
1029 if (reloc
== NULL
|| reloc_offset
== NULL
) {
1030 drm_free_large(reloc
);
1031 drm_free_large(reloc_offset
);
1032 mutex_lock(&dev
->struct_mutex
);
1037 for (i
= 0; i
< count
; i
++) {
1038 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
1039 u64 invalid_offset
= (u64
)-1;
1042 user_relocs
= u64_to_user_ptr(exec
[i
].relocs_ptr
);
1044 if (copy_from_user(reloc
+total
, user_relocs
,
1045 exec
[i
].relocation_count
* sizeof(*reloc
))) {
1047 mutex_lock(&dev
->struct_mutex
);
1051 /* As we do not update the known relocation offsets after
1052 * relocating (due to the complexities in lock handling),
1053 * we need to mark them as invalid now so that we force the
1054 * relocation processing next time. Just in case the target
1055 * object is evicted and then rebound into its old
1056 * presumed_offset before the next execbuffer - if that
1057 * happened we would make the mistake of assuming that the
1058 * relocations were valid.
1060 for (j
= 0; j
< exec
[i
].relocation_count
; j
++) {
1061 if (__copy_to_user(&user_relocs
[j
].presumed_offset
,
1063 sizeof(invalid_offset
))) {
1065 mutex_lock(&dev
->struct_mutex
);
1070 reloc_offset
[i
] = total
;
1071 total
+= exec
[i
].relocation_count
;
1074 ret
= i915_mutex_lock_interruptible(dev
);
1076 mutex_lock(&dev
->struct_mutex
);
1080 /* reacquire the objects */
1082 ret
= eb_lookup_vmas(eb
, exec
, args
, vm
, file
);
1086 need_relocs
= (args
->flags
& I915_EXEC_NO_RELOC
) == 0;
1087 ret
= i915_gem_execbuffer_reserve(engine
, &eb
->vmas
, ctx
,
1092 list_for_each_entry(vma
, &eb
->vmas
, exec_list
) {
1093 int offset
= vma
->exec_entry
- exec
;
1094 ret
= i915_gem_execbuffer_relocate_vma_slow(vma
, eb
,
1095 reloc
+ reloc_offset
[offset
]);
1100 /* Leave the user relocations as are, this is the painfully slow path,
1101 * and we want to avoid the complication of dropping the lock whilst
1102 * having buffers reserved in the aperture and so causing spurious
1103 * ENOSPC for random operations.
1107 drm_free_large(reloc
);
1108 drm_free_large(reloc_offset
);
1112 static unsigned int eb_other_engines(struct drm_i915_gem_request
*req
)
1116 mask
= ~intel_engine_flag(req
->engine
) & I915_BO_ACTIVE_MASK
;
1117 mask
<<= I915_BO_ACTIVE_SHIFT
;
1123 i915_gem_execbuffer_move_to_gpu(struct drm_i915_gem_request
*req
,
1124 struct list_head
*vmas
)
1126 const unsigned int other_rings
= eb_other_engines(req
);
1127 struct i915_vma
*vma
;
1130 list_for_each_entry(vma
, vmas
, exec_list
) {
1131 struct drm_i915_gem_object
*obj
= vma
->obj
;
1132 struct reservation_object
*resv
;
1134 if (obj
->flags
& other_rings
) {
1135 ret
= i915_gem_request_await_object
1136 (req
, obj
, obj
->base
.pending_write_domain
);
1141 resv
= i915_gem_object_get_dmabuf_resv(obj
);
1143 ret
= i915_sw_fence_await_reservation
1144 (&req
->submit
, resv
, &i915_fence_ops
,
1145 obj
->base
.pending_write_domain
, 10*HZ
,
1146 GFP_KERNEL
| __GFP_NOWARN
);
1151 if (obj
->base
.write_domain
& I915_GEM_DOMAIN_CPU
)
1152 i915_gem_clflush_object(obj
, false);
1155 /* Unconditionally flush any chipset caches (for streaming writes). */
1156 i915_gem_chipset_flush(req
->engine
->i915
);
1158 /* Unconditionally invalidate GPU caches and TLBs. */
1159 return req
->engine
->emit_flush(req
, EMIT_INVALIDATE
);
1163 i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2
*exec
)
1165 if (exec
->flags
& __I915_EXEC_UNKNOWN_FLAGS
)
1168 /* Kernel clipping was a DRI1 misfeature */
1169 if (exec
->num_cliprects
|| exec
->cliprects_ptr
)
1172 if (exec
->DR4
== 0xffffffff) {
1173 DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
1176 if (exec
->DR1
|| exec
->DR4
)
1179 if ((exec
->batch_start_offset
| exec
->batch_len
) & 0x7)
1186 validate_exec_list(struct drm_device
*dev
,
1187 struct drm_i915_gem_exec_object2
*exec
,
1190 unsigned relocs_total
= 0;
1191 unsigned relocs_max
= UINT_MAX
/ sizeof(struct drm_i915_gem_relocation_entry
);
1192 unsigned invalid_flags
;
1195 /* INTERNAL flags must not overlap with external ones */
1196 BUILD_BUG_ON(__EXEC_OBJECT_INTERNAL_FLAGS
& ~__EXEC_OBJECT_UNKNOWN_FLAGS
);
1198 invalid_flags
= __EXEC_OBJECT_UNKNOWN_FLAGS
;
1199 if (USES_FULL_PPGTT(dev
))
1200 invalid_flags
|= EXEC_OBJECT_NEEDS_GTT
;
1202 for (i
= 0; i
< count
; i
++) {
1203 char __user
*ptr
= u64_to_user_ptr(exec
[i
].relocs_ptr
);
1204 int length
; /* limited by fault_in_pages_readable() */
1206 if (exec
[i
].flags
& invalid_flags
)
1209 /* Offset can be used as input (EXEC_OBJECT_PINNED), reject
1210 * any non-page-aligned or non-canonical addresses.
1212 if (exec
[i
].flags
& EXEC_OBJECT_PINNED
) {
1213 if (exec
[i
].offset
!=
1214 gen8_canonical_addr(exec
[i
].offset
& PAGE_MASK
))
1217 /* From drm_mm perspective address space is continuous,
1218 * so from this point we're always using non-canonical
1221 exec
[i
].offset
= gen8_noncanonical_addr(exec
[i
].offset
);
1224 if (exec
[i
].alignment
&& !is_power_of_2(exec
[i
].alignment
))
1227 /* pad_to_size was once a reserved field, so sanitize it */
1228 if (exec
[i
].flags
& EXEC_OBJECT_PAD_TO_SIZE
) {
1229 if (offset_in_page(exec
[i
].pad_to_size
))
1232 exec
[i
].pad_to_size
= 0;
1235 /* First check for malicious input causing overflow in
1236 * the worst case where we need to allocate the entire
1237 * relocation tree as a single array.
1239 if (exec
[i
].relocation_count
> relocs_max
- relocs_total
)
1241 relocs_total
+= exec
[i
].relocation_count
;
1243 length
= exec
[i
].relocation_count
*
1244 sizeof(struct drm_i915_gem_relocation_entry
);
1246 * We must check that the entire relocation array is safe
1247 * to read, but since we may need to update the presumed
1248 * offsets during execution, check for full write access.
1250 if (!access_ok(VERIFY_WRITE
, ptr
, length
))
1253 if (likely(!i915
.prefault_disable
)) {
1254 if (fault_in_pages_readable(ptr
, length
))
1262 static struct i915_gem_context
*
1263 i915_gem_validate_context(struct drm_device
*dev
, struct drm_file
*file
,
1264 struct intel_engine_cs
*engine
, const u32 ctx_id
)
1266 struct i915_gem_context
*ctx
;
1267 struct i915_ctx_hang_stats
*hs
;
1269 ctx
= i915_gem_context_lookup(file
->driver_priv
, ctx_id
);
1273 hs
= &ctx
->hang_stats
;
1275 DRM_DEBUG("Context %u tried to submit while banned\n", ctx_id
);
1276 return ERR_PTR(-EIO
);
1282 void i915_vma_move_to_active(struct i915_vma
*vma
,
1283 struct drm_i915_gem_request
*req
,
1286 struct drm_i915_gem_object
*obj
= vma
->obj
;
1287 const unsigned int idx
= req
->engine
->id
;
1289 GEM_BUG_ON(!drm_mm_node_allocated(&vma
->node
));
1291 obj
->dirty
= 1; /* be paranoid */
1293 /* Add a reference if we're newly entering the active list.
1294 * The order in which we add operations to the retirement queue is
1295 * vital here: mark_active adds to the start of the callback list,
1296 * such that subsequent callbacks are called first. Therefore we
1297 * add the active reference first and queue for it to be dropped
1300 if (!i915_gem_object_is_active(obj
))
1301 i915_gem_object_get(obj
);
1302 i915_gem_object_set_active(obj
, idx
);
1303 i915_gem_active_set(&obj
->last_read
[idx
], req
);
1305 if (flags
& EXEC_OBJECT_WRITE
) {
1306 i915_gem_active_set(&obj
->last_write
, req
);
1308 intel_fb_obj_invalidate(obj
, ORIGIN_CS
);
1310 /* update for the implicit flush after a batch */
1311 obj
->base
.write_domain
&= ~I915_GEM_GPU_DOMAINS
;
1314 if (flags
& EXEC_OBJECT_NEEDS_FENCE
)
1315 i915_gem_active_set(&vma
->last_fence
, req
);
1317 i915_vma_set_active(vma
, idx
);
1318 i915_gem_active_set(&vma
->last_read
[idx
], req
);
1319 list_move_tail(&vma
->vm_link
, &vma
->vm
->active_list
);
1322 static void eb_export_fence(struct drm_i915_gem_object
*obj
,
1323 struct drm_i915_gem_request
*req
,
1326 struct reservation_object
*resv
;
1328 resv
= i915_gem_object_get_dmabuf_resv(obj
);
1332 /* Ignore errors from failing to allocate the new fence, we can't
1333 * handle an error right now. Worst case should be missed
1334 * synchronisation leading to rendering corruption.
1336 ww_mutex_lock(&resv
->lock
, NULL
);
1337 if (flags
& EXEC_OBJECT_WRITE
)
1338 reservation_object_add_excl_fence(resv
, &req
->fence
);
1339 else if (reservation_object_reserve_shared(resv
) == 0)
1340 reservation_object_add_shared_fence(resv
, &req
->fence
);
1341 ww_mutex_unlock(&resv
->lock
);
1345 i915_gem_execbuffer_move_to_active(struct list_head
*vmas
,
1346 struct drm_i915_gem_request
*req
)
1348 struct i915_vma
*vma
;
1350 list_for_each_entry(vma
, vmas
, exec_list
) {
1351 struct drm_i915_gem_object
*obj
= vma
->obj
;
1352 u32 old_read
= obj
->base
.read_domains
;
1353 u32 old_write
= obj
->base
.write_domain
;
1355 obj
->base
.write_domain
= obj
->base
.pending_write_domain
;
1356 if (obj
->base
.write_domain
)
1357 vma
->exec_entry
->flags
|= EXEC_OBJECT_WRITE
;
1359 obj
->base
.pending_read_domains
|= obj
->base
.read_domains
;
1360 obj
->base
.read_domains
= obj
->base
.pending_read_domains
;
1362 i915_vma_move_to_active(vma
, req
, vma
->exec_entry
->flags
);
1363 eb_export_fence(obj
, req
, vma
->exec_entry
->flags
);
1364 trace_i915_gem_object_change_domain(obj
, old_read
, old_write
);
1369 i915_reset_gen7_sol_offsets(struct drm_i915_gem_request
*req
)
1371 struct intel_ring
*ring
= req
->ring
;
1374 if (!IS_GEN7(req
->i915
) || req
->engine
->id
!= RCS
) {
1375 DRM_DEBUG("sol reset is gen7/rcs only\n");
1379 ret
= intel_ring_begin(req
, 4 * 3);
1383 for (i
= 0; i
< 4; i
++) {
1384 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
1385 intel_ring_emit_reg(ring
, GEN7_SO_WRITE_OFFSET(i
));
1386 intel_ring_emit(ring
, 0);
1389 intel_ring_advance(ring
);
1394 static struct i915_vma
*
1395 i915_gem_execbuffer_parse(struct intel_engine_cs
*engine
,
1396 struct drm_i915_gem_exec_object2
*shadow_exec_entry
,
1397 struct drm_i915_gem_object
*batch_obj
,
1399 u32 batch_start_offset
,
1403 struct drm_i915_gem_object
*shadow_batch_obj
;
1404 struct i915_vma
*vma
;
1407 shadow_batch_obj
= i915_gem_batch_pool_get(&engine
->batch_pool
,
1408 PAGE_ALIGN(batch_len
));
1409 if (IS_ERR(shadow_batch_obj
))
1410 return ERR_CAST(shadow_batch_obj
);
1412 ret
= intel_engine_cmd_parser(engine
,
1419 if (ret
== -EACCES
) /* unhandled chained batch */
1426 vma
= i915_gem_object_ggtt_pin(shadow_batch_obj
, NULL
, 0, 0, 0);
1430 memset(shadow_exec_entry
, 0, sizeof(*shadow_exec_entry
));
1432 vma
->exec_entry
= shadow_exec_entry
;
1433 vma
->exec_entry
->flags
= __EXEC_OBJECT_HAS_PIN
;
1434 i915_gem_object_get(shadow_batch_obj
);
1435 list_add_tail(&vma
->exec_list
, &eb
->vmas
);
1438 i915_gem_object_unpin_pages(shadow_batch_obj
);
1443 execbuf_submit(struct i915_execbuffer_params
*params
,
1444 struct drm_i915_gem_execbuffer2
*args
,
1445 struct list_head
*vmas
)
1447 struct drm_i915_private
*dev_priv
= params
->request
->i915
;
1448 u64 exec_start
, exec_len
;
1453 ret
= i915_gem_execbuffer_move_to_gpu(params
->request
, vmas
);
1457 ret
= i915_switch_context(params
->request
);
1461 instp_mode
= args
->flags
& I915_EXEC_CONSTANTS_MASK
;
1462 instp_mask
= I915_EXEC_CONSTANTS_MASK
;
1463 switch (instp_mode
) {
1464 case I915_EXEC_CONSTANTS_REL_GENERAL
:
1465 case I915_EXEC_CONSTANTS_ABSOLUTE
:
1466 case I915_EXEC_CONSTANTS_REL_SURFACE
:
1467 if (instp_mode
!= 0 && params
->engine
->id
!= RCS
) {
1468 DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
1472 if (instp_mode
!= dev_priv
->relative_constants_mode
) {
1473 if (INTEL_INFO(dev_priv
)->gen
< 4) {
1474 DRM_DEBUG("no rel constants on pre-gen4\n");
1478 if (INTEL_INFO(dev_priv
)->gen
> 5 &&
1479 instp_mode
== I915_EXEC_CONSTANTS_REL_SURFACE
) {
1480 DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
1484 /* The HW changed the meaning on this bit on gen6 */
1485 if (INTEL_INFO(dev_priv
)->gen
>= 6)
1486 instp_mask
&= ~I915_EXEC_CONSTANTS_REL_SURFACE
;
1490 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode
);
1494 if (params
->engine
->id
== RCS
&&
1495 instp_mode
!= dev_priv
->relative_constants_mode
) {
1496 struct intel_ring
*ring
= params
->request
->ring
;
1498 ret
= intel_ring_begin(params
->request
, 4);
1502 intel_ring_emit(ring
, MI_NOOP
);
1503 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
1504 intel_ring_emit_reg(ring
, INSTPM
);
1505 intel_ring_emit(ring
, instp_mask
<< 16 | instp_mode
);
1506 intel_ring_advance(ring
);
1508 dev_priv
->relative_constants_mode
= instp_mode
;
1511 if (args
->flags
& I915_EXEC_GEN7_SOL_RESET
) {
1512 ret
= i915_reset_gen7_sol_offsets(params
->request
);
1517 exec_len
= args
->batch_len
;
1518 exec_start
= params
->batch
->node
.start
+
1519 params
->args_batch_start_offset
;
1522 exec_len
= params
->batch
->size
- params
->args_batch_start_offset
;
1524 ret
= params
->engine
->emit_bb_start(params
->request
,
1525 exec_start
, exec_len
,
1526 params
->dispatch_flags
);
1530 trace_i915_gem_ring_dispatch(params
->request
, params
->dispatch_flags
);
1532 i915_gem_execbuffer_move_to_active(vmas
, params
->request
);
1538 * Find one BSD ring to dispatch the corresponding BSD command.
1539 * The engine index is returned.
1542 gen8_dispatch_bsd_engine(struct drm_i915_private
*dev_priv
,
1543 struct drm_file
*file
)
1545 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
1547 /* Check whether the file_priv has already selected one ring. */
1548 if ((int)file_priv
->bsd_engine
< 0)
1549 file_priv
->bsd_engine
= atomic_fetch_xor(1,
1550 &dev_priv
->mm
.bsd_engine_dispatch_index
);
1552 return file_priv
->bsd_engine
;
1555 #define I915_USER_RINGS (4)
1557 static const enum intel_engine_id user_ring_map
[I915_USER_RINGS
+ 1] = {
1558 [I915_EXEC_DEFAULT
] = RCS
,
1559 [I915_EXEC_RENDER
] = RCS
,
1560 [I915_EXEC_BLT
] = BCS
,
1561 [I915_EXEC_BSD
] = VCS
,
1562 [I915_EXEC_VEBOX
] = VECS
1565 static struct intel_engine_cs
*
1566 eb_select_engine(struct drm_i915_private
*dev_priv
,
1567 struct drm_file
*file
,
1568 struct drm_i915_gem_execbuffer2
*args
)
1570 unsigned int user_ring_id
= args
->flags
& I915_EXEC_RING_MASK
;
1571 struct intel_engine_cs
*engine
;
1573 if (user_ring_id
> I915_USER_RINGS
) {
1574 DRM_DEBUG("execbuf with unknown ring: %u\n", user_ring_id
);
1578 if ((user_ring_id
!= I915_EXEC_BSD
) &&
1579 ((args
->flags
& I915_EXEC_BSD_MASK
) != 0)) {
1580 DRM_DEBUG("execbuf with non bsd ring but with invalid "
1581 "bsd dispatch flags: %d\n", (int)(args
->flags
));
1585 if (user_ring_id
== I915_EXEC_BSD
&& HAS_BSD2(dev_priv
)) {
1586 unsigned int bsd_idx
= args
->flags
& I915_EXEC_BSD_MASK
;
1588 if (bsd_idx
== I915_EXEC_BSD_DEFAULT
) {
1589 bsd_idx
= gen8_dispatch_bsd_engine(dev_priv
, file
);
1590 } else if (bsd_idx
>= I915_EXEC_BSD_RING1
&&
1591 bsd_idx
<= I915_EXEC_BSD_RING2
) {
1592 bsd_idx
>>= I915_EXEC_BSD_SHIFT
;
1595 DRM_DEBUG("execbuf with unknown bsd ring: %u\n",
1600 engine
= dev_priv
->engine
[_VCS(bsd_idx
)];
1602 engine
= dev_priv
->engine
[user_ring_map
[user_ring_id
]];
1606 DRM_DEBUG("execbuf with invalid ring: %u\n", user_ring_id
);
1614 i915_gem_do_execbuffer(struct drm_device
*dev
, void *data
,
1615 struct drm_file
*file
,
1616 struct drm_i915_gem_execbuffer2
*args
,
1617 struct drm_i915_gem_exec_object2
*exec
)
1619 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1620 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
1622 struct drm_i915_gem_exec_object2 shadow_exec_entry
;
1623 struct intel_engine_cs
*engine
;
1624 struct i915_gem_context
*ctx
;
1625 struct i915_address_space
*vm
;
1626 struct i915_execbuffer_params params_master
; /* XXX: will be removed later */
1627 struct i915_execbuffer_params
*params
= ¶ms_master
;
1628 const u32 ctx_id
= i915_execbuffer2_get_context_id(*args
);
1633 if (!i915_gem_check_execbuffer(args
))
1636 ret
= validate_exec_list(dev
, exec
, args
->buffer_count
);
1641 if (args
->flags
& I915_EXEC_SECURE
) {
1642 if (!drm_is_current_master(file
) || !capable(CAP_SYS_ADMIN
))
1645 dispatch_flags
|= I915_DISPATCH_SECURE
;
1647 if (args
->flags
& I915_EXEC_IS_PINNED
)
1648 dispatch_flags
|= I915_DISPATCH_PINNED
;
1650 engine
= eb_select_engine(dev_priv
, file
, args
);
1654 if (args
->buffer_count
< 1) {
1655 DRM_DEBUG("execbuf with %d buffers\n", args
->buffer_count
);
1659 if (args
->flags
& I915_EXEC_RESOURCE_STREAMER
) {
1660 if (!HAS_RESOURCE_STREAMER(dev
)) {
1661 DRM_DEBUG("RS is only allowed for Haswell, Gen8 and above\n");
1664 if (engine
->id
!= RCS
) {
1665 DRM_DEBUG("RS is not available on %s\n",
1670 dispatch_flags
|= I915_DISPATCH_RS
;
1673 /* Take a local wakeref for preparing to dispatch the execbuf as
1674 * we expect to access the hardware fairly frequently in the
1675 * process. Upon first dispatch, we acquire another prolonged
1676 * wakeref that we hold until the GPU has been idle for at least
1679 intel_runtime_pm_get(dev_priv
);
1681 ret
= i915_mutex_lock_interruptible(dev
);
1685 ctx
= i915_gem_validate_context(dev
, file
, engine
, ctx_id
);
1687 mutex_unlock(&dev
->struct_mutex
);
1692 i915_gem_context_get(ctx
);
1695 vm
= &ctx
->ppgtt
->base
;
1699 memset(¶ms_master
, 0x00, sizeof(params_master
));
1701 eb
= eb_create(dev_priv
, args
);
1703 i915_gem_context_put(ctx
);
1704 mutex_unlock(&dev
->struct_mutex
);
1709 /* Look up object handles */
1710 ret
= eb_lookup_vmas(eb
, exec
, args
, vm
, file
);
1714 /* take note of the batch buffer before we might reorder the lists */
1715 params
->batch
= eb_get_batch(eb
);
1717 /* Move the objects en-masse into the GTT, evicting if necessary. */
1718 need_relocs
= (args
->flags
& I915_EXEC_NO_RELOC
) == 0;
1719 ret
= i915_gem_execbuffer_reserve(engine
, &eb
->vmas
, ctx
,
1724 /* The objects are in their final locations, apply the relocations. */
1726 ret
= i915_gem_execbuffer_relocate(eb
);
1728 if (ret
== -EFAULT
) {
1729 ret
= i915_gem_execbuffer_relocate_slow(dev
, args
, file
,
1732 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1738 /* Set the pending read domains for the batch buffer to COMMAND */
1739 if (params
->batch
->obj
->base
.pending_write_domain
) {
1740 DRM_DEBUG("Attempting to use self-modifying batch buffer\n");
1744 if (args
->batch_start_offset
> params
->batch
->size
||
1745 args
->batch_len
> params
->batch
->size
- args
->batch_start_offset
) {
1746 DRM_DEBUG("Attempting to use out-of-bounds batch\n");
1751 params
->args_batch_start_offset
= args
->batch_start_offset
;
1752 if (intel_engine_needs_cmd_parser(engine
) && args
->batch_len
) {
1753 struct i915_vma
*vma
;
1755 vma
= i915_gem_execbuffer_parse(engine
, &shadow_exec_entry
,
1758 args
->batch_start_offset
,
1760 drm_is_current_master(file
));
1768 * Batch parsed and accepted:
1770 * Set the DISPATCH_SECURE bit to remove the NON_SECURE
1771 * bit from MI_BATCH_BUFFER_START commands issued in
1772 * the dispatch_execbuffer implementations. We
1773 * specifically don't want that set on batches the
1774 * command parser has accepted.
1776 dispatch_flags
|= I915_DISPATCH_SECURE
;
1777 params
->args_batch_start_offset
= 0;
1778 params
->batch
= vma
;
1782 params
->batch
->obj
->base
.pending_read_domains
|= I915_GEM_DOMAIN_COMMAND
;
1784 /* snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure
1785 * batch" bit. Hence we need to pin secure batches into the global gtt.
1786 * hsw should have this fixed, but bdw mucks it up again. */
1787 if (dispatch_flags
& I915_DISPATCH_SECURE
) {
1788 struct drm_i915_gem_object
*obj
= params
->batch
->obj
;
1789 struct i915_vma
*vma
;
1792 * So on first glance it looks freaky that we pin the batch here
1793 * outside of the reservation loop. But:
1794 * - The batch is already pinned into the relevant ppgtt, so we
1795 * already have the backing storage fully allocated.
1796 * - No other BO uses the global gtt (well contexts, but meh),
1797 * so we don't really have issues with multiple objects not
1798 * fitting due to fragmentation.
1799 * So this is actually safe.
1801 vma
= i915_gem_object_ggtt_pin(obj
, NULL
, 0, 0, 0);
1807 params
->batch
= vma
;
1810 /* Allocate a request for this batch buffer nice and early. */
1811 params
->request
= i915_gem_request_alloc(engine
, ctx
);
1812 if (IS_ERR(params
->request
)) {
1813 ret
= PTR_ERR(params
->request
);
1814 goto err_batch_unpin
;
1817 /* Whilst this request exists, batch_obj will be on the
1818 * active_list, and so will hold the active reference. Only when this
1819 * request is retired will the the batch_obj be moved onto the
1820 * inactive_list and lose its active reference. Hence we do not need
1821 * to explicitly hold another reference here.
1823 params
->request
->batch
= params
->batch
;
1825 ret
= i915_gem_request_add_to_client(params
->request
, file
);
1830 * Save assorted stuff away to pass through to *_submission().
1831 * NB: This data should be 'persistent' and not local as it will
1832 * kept around beyond the duration of the IOCTL once the GPU
1833 * scheduler arrives.
1836 params
->file
= file
;
1837 params
->engine
= engine
;
1838 params
->dispatch_flags
= dispatch_flags
;
1841 ret
= execbuf_submit(params
, args
, &eb
->vmas
);
1843 __i915_add_request(params
->request
, ret
== 0);
1847 * FIXME: We crucially rely upon the active tracking for the (ppgtt)
1848 * batch vma for correctness. For less ugly and less fragility this
1849 * needs to be adjusted to also track the ggtt batch vma properly as
1852 if (dispatch_flags
& I915_DISPATCH_SECURE
)
1853 i915_vma_unpin(params
->batch
);
1855 /* the request owns the ref now */
1856 i915_gem_context_put(ctx
);
1859 mutex_unlock(&dev
->struct_mutex
);
1862 /* intel_gpu_busy should also get a ref, so it will free when the device
1863 * is really idle. */
1864 intel_runtime_pm_put(dev_priv
);
1869 * Legacy execbuffer just creates an exec2 list from the original exec object
1870 * list array and passes it to the real function.
1873 i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
1874 struct drm_file
*file
)
1876 struct drm_i915_gem_execbuffer
*args
= data
;
1877 struct drm_i915_gem_execbuffer2 exec2
;
1878 struct drm_i915_gem_exec_object
*exec_list
= NULL
;
1879 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
1882 if (args
->buffer_count
< 1) {
1883 DRM_DEBUG("execbuf with %d buffers\n", args
->buffer_count
);
1887 /* Copy in the exec list from userland */
1888 exec_list
= drm_malloc_ab(sizeof(*exec_list
), args
->buffer_count
);
1889 exec2_list
= drm_malloc_ab(sizeof(*exec2_list
), args
->buffer_count
);
1890 if (exec_list
== NULL
|| exec2_list
== NULL
) {
1891 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1892 args
->buffer_count
);
1893 drm_free_large(exec_list
);
1894 drm_free_large(exec2_list
);
1897 ret
= copy_from_user(exec_list
,
1898 u64_to_user_ptr(args
->buffers_ptr
),
1899 sizeof(*exec_list
) * args
->buffer_count
);
1901 DRM_DEBUG("copy %d exec entries failed %d\n",
1902 args
->buffer_count
, ret
);
1903 drm_free_large(exec_list
);
1904 drm_free_large(exec2_list
);
1908 for (i
= 0; i
< args
->buffer_count
; i
++) {
1909 exec2_list
[i
].handle
= exec_list
[i
].handle
;
1910 exec2_list
[i
].relocation_count
= exec_list
[i
].relocation_count
;
1911 exec2_list
[i
].relocs_ptr
= exec_list
[i
].relocs_ptr
;
1912 exec2_list
[i
].alignment
= exec_list
[i
].alignment
;
1913 exec2_list
[i
].offset
= exec_list
[i
].offset
;
1914 if (INTEL_INFO(dev
)->gen
< 4)
1915 exec2_list
[i
].flags
= EXEC_OBJECT_NEEDS_FENCE
;
1917 exec2_list
[i
].flags
= 0;
1920 exec2
.buffers_ptr
= args
->buffers_ptr
;
1921 exec2
.buffer_count
= args
->buffer_count
;
1922 exec2
.batch_start_offset
= args
->batch_start_offset
;
1923 exec2
.batch_len
= args
->batch_len
;
1924 exec2
.DR1
= args
->DR1
;
1925 exec2
.DR4
= args
->DR4
;
1926 exec2
.num_cliprects
= args
->num_cliprects
;
1927 exec2
.cliprects_ptr
= args
->cliprects_ptr
;
1928 exec2
.flags
= I915_EXEC_RENDER
;
1929 i915_execbuffer2_set_context_id(exec2
, 0);
1931 ret
= i915_gem_do_execbuffer(dev
, data
, file
, &exec2
, exec2_list
);
1933 struct drm_i915_gem_exec_object __user
*user_exec_list
=
1934 u64_to_user_ptr(args
->buffers_ptr
);
1936 /* Copy the new buffer offsets back to the user's exec list. */
1937 for (i
= 0; i
< args
->buffer_count
; i
++) {
1938 exec2_list
[i
].offset
=
1939 gen8_canonical_addr(exec2_list
[i
].offset
);
1940 ret
= __copy_to_user(&user_exec_list
[i
].offset
,
1941 &exec2_list
[i
].offset
,
1942 sizeof(user_exec_list
[i
].offset
));
1945 DRM_DEBUG("failed to copy %d exec entries "
1946 "back to user (%d)\n",
1947 args
->buffer_count
, ret
);
1953 drm_free_large(exec_list
);
1954 drm_free_large(exec2_list
);
1959 i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
1960 struct drm_file
*file
)
1962 struct drm_i915_gem_execbuffer2
*args
= data
;
1963 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
1966 if (args
->buffer_count
< 1 ||
1967 args
->buffer_count
> UINT_MAX
/ sizeof(*exec2_list
)) {
1968 DRM_DEBUG("execbuf2 with %d buffers\n", args
->buffer_count
);
1972 if (args
->rsvd2
!= 0) {
1973 DRM_DEBUG("dirty rvsd2 field\n");
1977 exec2_list
= drm_malloc_gfp(args
->buffer_count
,
1978 sizeof(*exec2_list
),
1980 if (exec2_list
== NULL
) {
1981 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1982 args
->buffer_count
);
1985 ret
= copy_from_user(exec2_list
,
1986 u64_to_user_ptr(args
->buffers_ptr
),
1987 sizeof(*exec2_list
) * args
->buffer_count
);
1989 DRM_DEBUG("copy %d exec entries failed %d\n",
1990 args
->buffer_count
, ret
);
1991 drm_free_large(exec2_list
);
1995 ret
= i915_gem_do_execbuffer(dev
, data
, file
, args
, exec2_list
);
1997 /* Copy the new buffer offsets back to the user's exec list. */
1998 struct drm_i915_gem_exec_object2 __user
*user_exec_list
=
1999 u64_to_user_ptr(args
->buffers_ptr
);
2002 for (i
= 0; i
< args
->buffer_count
; i
++) {
2003 exec2_list
[i
].offset
=
2004 gen8_canonical_addr(exec2_list
[i
].offset
);
2005 ret
= __copy_to_user(&user_exec_list
[i
].offset
,
2006 &exec2_list
[i
].offset
,
2007 sizeof(user_exec_list
[i
].offset
));
2010 DRM_DEBUG("failed to copy %d exec entries "
2012 args
->buffer_count
);
2018 drm_free_large(exec2_list
);