drivers/gpu/drm/i915/i915_gem_tiling.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include <linux/string.h>
  29 #include <linux/bitops.h>
  30 #include <drm/i915_drm.h>
  31 #include "i915_drv.h"
  32
  33 /**
  34  * DOC: buffer object tiling
  35  *
  36  * i915_gem_set_tiling_ioctl() and i915_gem_get_tiling_ioctl() is the userspace
  37  * interface to declare fence register requirements.
  38  *
  39  * In principle GEM doesn't care at all about the internal data layout of an
  40  * object, and hence it also doesn't care about tiling or swizzling. There's two
  41  * exceptions:
  42  *
  43  * - For X and Y tiling the hardware provides detilers for CPU access, so called
  44  *   fences. Since there's only a limited amount of them the kernel must manage
  45  *   these, and therefore userspace must tell the kernel the object tiling if it
  46  *   wants to use fences for detiling.
  47  * - On gen3 and gen4 platforms have a swizzling pattern for tiled objects which
  48  *   depends upon the physical page frame number. When swapping such objects the
  49  *   page frame number might change and the kernel must be able to fix this up
  50  *   and hence now the tiling. Note that on a subset of platforms with
  51  *   asymmetric memory channel population the swizzling pattern changes in an
  52  *   unknown way, and for those the kernel simply forbids swapping completely.
  53  *
  54  * Since neither of this applies for new tiling layouts on modern platforms like
  55  * W, Ys and Yf tiling GEM only allows object tiling to be set to X or Y tiled.
  56  * Anything else can be handled in userspace entirely without the kernel's
  57  * invovlement.
  58  */
  59
  60 /**
  61  * i915_gem_fence_size - required global GTT size for a fence
  62  * @i915: i915 device
  63  * @size: object size
  64  * @tiling: tiling mode
  65  * @stride: tiling stride
  66  *
  67  * Return the required global GTT size for a fence (view of a tiled object),
  68  * taking into account potential fence register mapping.
  69  */
  70 u32 i915_gem_fence_size(struct drm_i915_private *i915,
  71                         u32 size, unsigned int tiling, unsigned int stride)
  72 {
  73         u32 ggtt_size;
  74
  75         GEM_BUG_ON(!size);
  76
  77         if (tiling == I915_TILING_NONE)
  78                 return size;
  79
  80         GEM_BUG_ON(!stride);
  81
  82         if (INTEL_GEN(i915) >= 4) {
  83                 stride *= i915_gem_tile_height(tiling);
  84                 GEM_BUG_ON(!IS_ALIGNED(stride, I965_FENCE_PAGE));
  85                 return roundup(size, stride);
  86         }
  87
  88         /* Previous chips need a power-of-two fence region when tiling */
  89         if (IS_GEN(i915, 3))
  90                 ggtt_size = 1024*1024;
  91         else
  92                 ggtt_size = 512*1024;
  93
  94         while (ggtt_size < size)
  95                 ggtt_size <<= 1;
  96
  97         return ggtt_size;
  98 }
  99
 100 /**
 101  * i915_gem_fence_alignment - required global GTT alignment for a fence
 102  * @i915: i915 device
 103  * @size: object size
 104  * @tiling: tiling mode
 105  * @stride: tiling stride
 106  *
 107  * Return the required global GTT alignment for a fence (a view of a tiled
 108  * object), taking into account potential fence register mapping.
 109  */
 110 u32 i915_gem_fence_alignment(struct drm_i915_private *i915, u32 size,
 111                              unsigned int tiling, unsigned int stride)
 112 {
 113         GEM_BUG_ON(!size);
 114
 115         /*
 116          * Minimum alignment is 4k (GTT page size), but might be greater
 117          * if a fence register is needed for the object.
 118          */
 119         if (tiling == I915_TILING_NONE)
 120                 return I915_GTT_MIN_ALIGNMENT;
 121
 122         if (INTEL_GEN(i915) >= 4)
 123                 return I965_FENCE_PAGE;
 124
 125         /*
 126          * Previous chips need to be aligned to the size of the smallest
 127          * fence register that can contain the object.
 128          */
 129         return i915_gem_fence_size(i915, size, tiling, stride);
 130 }
 131
 132 /* Check pitch constriants for all chips & tiling formats */
 133 static bool
 134 i915_tiling_ok(struct drm_i915_gem_object *obj,
 135                unsigned int tiling, unsigned int stride)
 136 {
 137         struct drm_i915_private *i915 = to_i915(obj->base.dev);
 138         unsigned int tile_width;
 139
 140         /* Linear is always fine */
 141         if (tiling == I915_TILING_NONE)
 142                 return true;
 143
 144         if (tiling > I915_TILING_LAST)
 145                 return false;
 146
 147         /* check maximum stride & object size */
 148         /* i965+ stores the end address of the gtt mapping in the fence
 149          * reg, so dont bother to check the size */
 150         if (INTEL_GEN(i915) >= 7) {
 151                 if (stride / 128 > GEN7_FENCE_MAX_PITCH_VAL)
 152                         return false;
 153         } else if (INTEL_GEN(i915) >= 4) {
 154                 if (stride / 128 > I965_FENCE_MAX_PITCH_VAL)
 155                         return false;
 156         } else {
 157                 if (stride > 8192)
 158                         return false;
 159
 160                 if (!is_power_of_2(stride))
 161                         return false;
 162         }
 163
 164         if (IS_GEN(i915, 2) ||
 165             (tiling == I915_TILING_Y && HAS_128_BYTE_Y_TILING(i915)))
 166                 tile_width = 128;
 167         else
 168                 tile_width = 512;
 169
 170         if (!stride || !IS_ALIGNED(stride, tile_width))
 171                 return false;
 172
 173         return true;
 174 }
 175
 176 static bool i915_vma_fence_prepare(struct i915_vma *vma,
 177                                    int tiling_mode, unsigned int stride)
 178 {
 179         struct drm_i915_private *i915 = vma->vm->i915;
 180         u32 size, alignment;
 181
 182         if (!i915_vma_is_map_and_fenceable(vma))
 183                 return true;
 184
 185         size = i915_gem_fence_size(i915, vma->size, tiling_mode, stride);
 186         if (vma->node.size < size)
 187                 return false;
 188
 189         alignment = i915_gem_fence_alignment(i915, vma->size, tiling_mode, stride);
 190         if (!IS_ALIGNED(vma->node.start, alignment))
 191                 return false;
 192
 193         return true;
 194 }
 195
 196 /* Make the current GTT allocation valid for the change in tiling. */
 197 static int
 198 i915_gem_object_fence_prepare(struct drm_i915_gem_object *obj,
 199                               int tiling_mode, unsigned int stride)
 200 {
 201         struct i915_vma *vma;
 202         int ret;
 203
 204         if (tiling_mode == I915_TILING_NONE)
 205                 return 0;
 206
 207         for_each_ggtt_vma(vma, obj) {
 208                 if (i915_vma_fence_prepare(vma, tiling_mode, stride))
 209                         continue;
 210
 211                 ret = i915_vma_unbind(vma);
 212                 if (ret)
 213                         return ret;
 214         }
 215
 216         return 0;
 217 }
 218
 219 int
 220 i915_gem_object_set_tiling(struct drm_i915_gem_object *obj,
 221                            unsigned int tiling, unsigned int stride)
 222 {
 223         struct drm_i915_private *i915 = to_i915(obj->base.dev);
 224         struct i915_vma *vma;
 225         int err;
 226
 227         /* Make sure we don't cross-contaminate obj->tiling_and_stride */
 228         BUILD_BUG_ON(I915_TILING_LAST & STRIDE_MASK);
 229
 230         GEM_BUG_ON(!i915_tiling_ok(obj, tiling, stride));
 231         GEM_BUG_ON(!stride ^ (tiling == I915_TILING_NONE));
 232         lockdep_assert_held(&i915->drm.struct_mutex);
 233
 234         if ((tiling | stride) == obj->tiling_and_stride)
 235                 return 0;
 236
 237         if (i915_gem_object_is_framebuffer(obj))
 238                 return -EBUSY;
 239
 240         /* We need to rebind the object if its current allocation
 241          * no longer meets the alignment restrictions for its new
 242          * tiling mode. Otherwise we can just leave it alone, but
 243          * need to ensure that any fence register is updated before
 244          * the next fenced (either through the GTT or by the BLT unit
 245          * on older GPUs) access.
 246          *
 247          * After updating the tiling parameters, we then flag whether
 248          * we need to update an associated fence register. Note this
 249          * has to also include the unfenced register the GPU uses
 250          * whilst executing a fenced command for an untiled object.
 251          */
 252
 253         err = i915_gem_object_fence_prepare(obj, tiling, stride);
 254         if (err)
 255                 return err;
 256
 257         i915_gem_object_lock(obj);
 258         if (i915_gem_object_is_framebuffer(obj)) {
 259                 i915_gem_object_unlock(obj);
 260                 return -EBUSY;
 261         }
 262
 263         /* If the memory has unknown (i.e. varying) swizzling, we pin the
 264          * pages to prevent them being swapped out and causing corruption
 265          * due to the change in swizzling.
 266          */
 267         mutex_lock(&obj->mm.lock);
 268         if (i915_gem_object_has_pages(obj) &&
 269             obj->mm.madv == I915_MADV_WILLNEED &&
 270             i915->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
 271                 if (tiling == I915_TILING_NONE) {
 272                         GEM_BUG_ON(!obj->mm.quirked);
 273                         __i915_gem_object_unpin_pages(obj);
 274                         obj->mm.quirked = false;
 275                 }
 276                 if (!i915_gem_object_is_tiled(obj)) {
 277                         GEM_BUG_ON(obj->mm.quirked);
 278                         __i915_gem_object_pin_pages(obj);
 279                         obj->mm.quirked = true;
 280                 }
 281         }
 282         mutex_unlock(&obj->mm.lock);
 283
 284         for_each_ggtt_vma(vma, obj) {
 285                 vma->fence_size =
 286                         i915_gem_fence_size(i915, vma->size, tiling, stride);
 287                 vma->fence_alignment =
 288                         i915_gem_fence_alignment(i915,
 289                                                  vma->size, tiling, stride);
 290
 291                 if (vma->fence)
 292                         vma->fence->dirty = true;
 293         }
 294
 295         obj->tiling_and_stride = tiling | stride;
 296         i915_gem_object_unlock(obj);
 297
 298         /* Force the fence to be reacquired for GTT access */
 299         i915_gem_release_mmap(obj);
 300
 301         /* Try to preallocate memory required to save swizzling on put-pages */
 302         if (i915_gem_object_needs_bit17_swizzle(obj)) {
 303                 if (!obj->bit_17) {
 304                         obj->bit_17 = kcalloc(BITS_TO_LONGS(obj->base.size >> PAGE_SHIFT),
 305                                               sizeof(long), GFP_KERNEL);
 306                 }
 307         } else {
 308                 kfree(obj->bit_17);
 309                 obj->bit_17 = NULL;
 310         }
 311
 312         return 0;
 313 }
 314
 315 /**
 316  * i915_gem_set_tiling_ioctl - IOCTL handler to set tiling mode
 317  * @dev: DRM device
 318  * @data: data pointer for the ioctl
 319  * @file: DRM file for the ioctl call
 320  *
 321  * Sets the tiling mode of an object, returning the required swizzling of
 322  * bit 6 of addresses in the object.
 323  *
 324  * Called by the user via ioctl.
 325  *
 326  * Returns:
 327  * Zero on success, negative errno on failure.
 328  */
 329 int
 330 i915_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
 331                           struct drm_file *file)
 332 {
 333         struct drm_i915_gem_set_tiling *args = data;
 334         struct drm_i915_gem_object *obj;
 335         int err;
 336
 337         obj = i915_gem_object_lookup(file, args->handle);
 338         if (!obj)
 339                 return -ENOENT;
 340
 341         /*
 342          * The tiling mode of proxy objects is handled by its generator, and
 343          * not allowed to be changed by userspace.
 344          */
 345         if (i915_gem_object_is_proxy(obj)) {
 346                 err = -ENXIO;
 347                 goto err;
 348         }
 349
 350         if (!i915_tiling_ok(obj, args->tiling_mode, args->stride)) {
 351                 err = -EINVAL;
 352                 goto err;
 353         }
 354
 355         if (args->tiling_mode == I915_TILING_NONE) {
 356                 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
 357                 args->stride = 0;
 358         } else {
 359                 if (args->tiling_mode == I915_TILING_X)
 360                         args->swizzle_mode = to_i915(dev)->mm.bit_6_swizzle_x;
 361                 else
 362                         args->swizzle_mode = to_i915(dev)->mm.bit_6_swizzle_y;
 363
 364                 /* Hide bit 17 swizzling from the user.  This prevents old Mesa
 365                  * from aborting the application on sw fallbacks to bit 17,
 366                  * and we use the pread/pwrite bit17 paths to swizzle for it.
 367                  * If there was a user that was relying on the swizzle
 368                  * information for drm_intel_bo_map()ed reads/writes this would
 369                  * break it, but we don't have any of those.
 370                  */
 371                 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
 372                         args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
 373                 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
 374                         args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;
 375
 376                 /* If we can't handle the swizzling, make it untiled. */
 377                 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_UNKNOWN) {
 378                         args->tiling_mode = I915_TILING_NONE;
 379                         args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
 380                         args->stride = 0;
 381                 }
 382         }
 383
 384         err = mutex_lock_interruptible(&dev->struct_mutex);
 385         if (err)
 386                 goto err;
 387
 388         err = i915_gem_object_set_tiling(obj, args->tiling_mode, args->stride);
 389         mutex_unlock(&dev->struct_mutex);
 390
 391         /* We have to maintain this existing ABI... */
 392         args->stride = i915_gem_object_get_stride(obj);
 393         args->tiling_mode = i915_gem_object_get_tiling(obj);
 394
 395 err:
 396         i915_gem_object_put(obj);
 397         return err;
 398 }
 399
 400 /**
 401  * i915_gem_get_tiling_ioctl - IOCTL handler to get tiling mode
 402  * @dev: DRM device
 403  * @data: data pointer for the ioctl
 404  * @file: DRM file for the ioctl call
 405  *
 406  * Returns the current tiling mode and required bit 6 swizzling for the object.
 407  *
 408  * Called by the user via ioctl.
 409  *
 410  * Returns:
 411  * Zero on success, negative errno on failure.
 412  */
 413 int
 414 i915_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
 415                           struct drm_file *file)
 416 {
 417         struct drm_i915_gem_get_tiling *args = data;
 418         struct drm_i915_private *dev_priv = to_i915(dev);
 419         struct drm_i915_gem_object *obj;
 420         int err = -ENOENT;
 421
 422         rcu_read_lock();
 423         obj = i915_gem_object_lookup_rcu(file, args->handle);
 424         if (obj) {
 425                 args->tiling_mode =
 426                         READ_ONCE(obj->tiling_and_stride) & TILING_MASK;
 427                 err = 0;
 428         }
 429         rcu_read_unlock();
 430         if (unlikely(err))
 431                 return err;
 432
 433         switch (args->tiling_mode) {
 434         case I915_TILING_X:
 435                 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
 436                 break;
 437         case I915_TILING_Y:
 438                 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
 439                 break;
 440         default:
 441         case I915_TILING_NONE:
 442                 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
 443                 break;
 444         }
 445
 446         /* Hide bit 17 from the user -- see comment in i915_gem_set_tiling */
 447         if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
 448                 args->phys_swizzle_mode = I915_BIT_6_SWIZZLE_UNKNOWN;
 449         else
 450                 args->phys_swizzle_mode = args->swizzle_mode;
 451         if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
 452                 args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
 453         if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
 454                 args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;
 455
 456         return 0;
 457 }