2 * Copyright (c) 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 * Mika Kuoppala <mika.kuoppala@intel.com>
30 #include <linux/ascii85.h>
31 #include <linux/nmi.h>
32 #include <linux/pagevec.h>
33 #include <linux/scatterlist.h>
34 #include <linux/utsname.h>
35 #include <linux/zlib.h>
37 #include <drm/drm_print.h>
39 #include "display/intel_atomic.h"
40 #include "display/intel_csr.h"
41 #include "display/intel_overlay.h"
43 #include "gem/i915_gem_context.h"
44 #include "gem/i915_gem_lmem.h"
45 #include "gt/intel_gt_pm.h"
48 #include "i915_gpu_error.h"
49 #include "i915_memcpy.h"
50 #include "i915_scatterlist.h"
52 #define ALLOW_FAIL (GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_NOWARN)
53 #define ATOMIC_MAYFAIL (GFP_ATOMIC | __GFP_NOWARN)
55 static void __sg_set_buf(struct scatterlist
*sg
,
56 void *addr
, unsigned int len
, loff_t it
)
58 sg
->page_link
= (unsigned long)virt_to_page(addr
);
59 sg
->offset
= offset_in_page(addr
);
64 static bool __i915_error_grow(struct drm_i915_error_state_buf
*e
, size_t len
)
69 if (e
->bytes
+ len
+ 1 <= e
->size
)
73 __sg_set_buf(e
->cur
++, e
->buf
, e
->bytes
, e
->iter
);
79 if (e
->cur
== e
->end
) {
80 struct scatterlist
*sgl
;
82 sgl
= (typeof(sgl
))__get_free_page(ALLOW_FAIL
);
92 (unsigned long)sgl
| SG_CHAIN
;
98 e
->end
= sgl
+ SG_MAX_SINGLE_ALLOC
- 1;
101 e
->size
= ALIGN(len
+ 1, SZ_64K
);
102 e
->buf
= kmalloc(e
->size
, ALLOW_FAIL
);
104 e
->size
= PAGE_ALIGN(len
+ 1);
105 e
->buf
= kmalloc(e
->size
, GFP_KERNEL
);
116 static void i915_error_vprintf(struct drm_i915_error_state_buf
*e
,
117 const char *fmt
, va_list args
)
126 len
= vsnprintf(NULL
, 0, fmt
, ap
);
133 if (!__i915_error_grow(e
, len
))
136 GEM_BUG_ON(e
->bytes
>= e
->size
);
137 len
= vscnprintf(e
->buf
+ e
->bytes
, e
->size
- e
->bytes
, fmt
, args
);
145 static void i915_error_puts(struct drm_i915_error_state_buf
*e
, const char *str
)
153 if (!__i915_error_grow(e
, len
))
156 GEM_BUG_ON(e
->bytes
+ len
> e
->size
);
157 memcpy(e
->buf
+ e
->bytes
, str
, len
);
161 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
162 #define err_puts(e, s) i915_error_puts(e, s)
164 static void __i915_printfn_error(struct drm_printer
*p
, struct va_format
*vaf
)
166 i915_error_vprintf(p
->arg
, vaf
->fmt
, *vaf
->va
);
169 static inline struct drm_printer
170 i915_error_printer(struct drm_i915_error_state_buf
*e
)
172 struct drm_printer p
= {
173 .printfn
= __i915_printfn_error
,
179 /* single threaded page allocator with a reserved stash for emergencies */
180 static void pool_fini(struct pagevec
*pv
)
185 static int pool_refill(struct pagevec
*pv
, gfp_t gfp
)
187 while (pagevec_space(pv
)) {
200 static int pool_init(struct pagevec
*pv
, gfp_t gfp
)
206 err
= pool_refill(pv
, gfp
);
213 static void *pool_alloc(struct pagevec
*pv
, gfp_t gfp
)
218 if (!p
&& pagevec_count(pv
))
219 p
= pv
->pages
[--pv
->nr
];
221 return p
? page_address(p
) : NULL
;
224 static void pool_free(struct pagevec
*pv
, void *addr
)
226 struct page
*p
= virt_to_page(addr
);
228 if (pagevec_space(pv
))
234 #ifdef CONFIG_DRM_I915_COMPRESS_ERROR
236 struct i915_vma_compress
{
238 struct z_stream_s zstream
;
242 static bool compress_init(struct i915_vma_compress
*c
)
244 struct z_stream_s
*zstream
= &c
->zstream
;
246 if (pool_init(&c
->pool
, ALLOW_FAIL
))
250 kmalloc(zlib_deflate_workspacesize(MAX_WBITS
, MAX_MEM_LEVEL
),
252 if (!zstream
->workspace
) {
258 if (i915_has_memcpy_from_wc())
259 c
->tmp
= pool_alloc(&c
->pool
, ALLOW_FAIL
);
264 static bool compress_start(struct i915_vma_compress
*c
)
266 struct z_stream_s
*zstream
= &c
->zstream
;
267 void *workspace
= zstream
->workspace
;
269 memset(zstream
, 0, sizeof(*zstream
));
270 zstream
->workspace
= workspace
;
272 return zlib_deflateInit(zstream
, Z_DEFAULT_COMPRESSION
) == Z_OK
;
275 static void *compress_next_page(struct i915_vma_compress
*c
,
276 struct i915_vma_coredump
*dst
)
280 if (dst
->page_count
>= dst
->num_pages
)
281 return ERR_PTR(-ENOSPC
);
283 page
= pool_alloc(&c
->pool
, ALLOW_FAIL
);
285 return ERR_PTR(-ENOMEM
);
287 return dst
->pages
[dst
->page_count
++] = page
;
290 static int compress_page(struct i915_vma_compress
*c
,
292 struct i915_vma_coredump
*dst
,
295 struct z_stream_s
*zstream
= &c
->zstream
;
297 zstream
->next_in
= src
;
298 if (wc
&& c
->tmp
&& i915_memcpy_from_wc(c
->tmp
, src
, PAGE_SIZE
))
299 zstream
->next_in
= c
->tmp
;
300 zstream
->avail_in
= PAGE_SIZE
;
303 if (zstream
->avail_out
== 0) {
304 zstream
->next_out
= compress_next_page(c
, dst
);
305 if (IS_ERR(zstream
->next_out
))
306 return PTR_ERR(zstream
->next_out
);
308 zstream
->avail_out
= PAGE_SIZE
;
311 if (zlib_deflate(zstream
, Z_NO_FLUSH
) != Z_OK
)
313 } while (zstream
->avail_in
);
315 /* Fallback to uncompressed if we increase size? */
316 if (0 && zstream
->total_out
> zstream
->total_in
)
322 static int compress_flush(struct i915_vma_compress
*c
,
323 struct i915_vma_coredump
*dst
)
325 struct z_stream_s
*zstream
= &c
->zstream
;
328 switch (zlib_deflate(zstream
, Z_FINISH
)) {
329 case Z_OK
: /* more space requested */
330 zstream
->next_out
= compress_next_page(c
, dst
);
331 if (IS_ERR(zstream
->next_out
))
332 return PTR_ERR(zstream
->next_out
);
334 zstream
->avail_out
= PAGE_SIZE
;
340 default: /* any error */
346 memset(zstream
->next_out
, 0, zstream
->avail_out
);
347 dst
->unused
= zstream
->avail_out
;
351 static void compress_finish(struct i915_vma_compress
*c
)
353 zlib_deflateEnd(&c
->zstream
);
356 static void compress_fini(struct i915_vma_compress
*c
)
358 kfree(c
->zstream
.workspace
);
360 pool_free(&c
->pool
, c
->tmp
);
364 static void err_compression_marker(struct drm_i915_error_state_buf
*m
)
371 struct i915_vma_compress
{
375 static bool compress_init(struct i915_vma_compress
*c
)
377 return pool_init(&c
->pool
, ALLOW_FAIL
) == 0;
380 static bool compress_start(struct i915_vma_compress
*c
)
385 static int compress_page(struct i915_vma_compress
*c
,
387 struct i915_vma_coredump
*dst
,
392 ptr
= pool_alloc(&c
->pool
, ALLOW_FAIL
);
396 if (!(wc
&& i915_memcpy_from_wc(ptr
, src
, PAGE_SIZE
)))
397 memcpy(ptr
, src
, PAGE_SIZE
);
398 dst
->pages
[dst
->page_count
++] = ptr
;
403 static int compress_flush(struct i915_vma_compress
*c
,
404 struct i915_vma_coredump
*dst
)
409 static void compress_finish(struct i915_vma_compress
*c
)
413 static void compress_fini(struct i915_vma_compress
*c
)
418 static void err_compression_marker(struct drm_i915_error_state_buf
*m
)
425 static void error_print_instdone(struct drm_i915_error_state_buf
*m
,
426 const struct intel_engine_coredump
*ee
)
428 const struct sseu_dev_info
*sseu
= &RUNTIME_INFO(m
->i915
)->sseu
;
432 err_printf(m
, " INSTDONE: 0x%08x\n",
433 ee
->instdone
.instdone
);
435 if (ee
->engine
->class != RENDER_CLASS
|| INTEL_GEN(m
->i915
) <= 3)
438 err_printf(m
, " SC_INSTDONE: 0x%08x\n",
439 ee
->instdone
.slice_common
);
441 if (INTEL_GEN(m
->i915
) <= 6)
444 for_each_instdone_slice_subslice(m
->i915
, sseu
, slice
, subslice
)
445 err_printf(m
, " SAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
447 ee
->instdone
.sampler
[slice
][subslice
]);
449 for_each_instdone_slice_subslice(m
->i915
, sseu
, slice
, subslice
)
450 err_printf(m
, " ROW_INSTDONE[%d][%d]: 0x%08x\n",
452 ee
->instdone
.row
[slice
][subslice
]);
454 if (INTEL_GEN(m
->i915
) < 12)
457 err_printf(m
, " SC_INSTDONE_EXTRA: 0x%08x\n",
458 ee
->instdone
.slice_common_extra
[0]);
459 err_printf(m
, " SC_INSTDONE_EXTRA2: 0x%08x\n",
460 ee
->instdone
.slice_common_extra
[1]);
463 static void error_print_request(struct drm_i915_error_state_buf
*m
,
465 const struct i915_request_coredump
*erq
)
470 err_printf(m
, "%s pid %d, seqno %8x:%08x%s%s, prio %d, start %08x, head %08x, tail %08x\n",
471 prefix
, erq
->pid
, erq
->context
, erq
->seqno
,
472 test_bit(DMA_FENCE_FLAG_SIGNALED_BIT
,
473 &erq
->flags
) ? "!" : "",
474 test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT
,
475 &erq
->flags
) ? "+" : "",
476 erq
->sched_attr
.priority
,
477 erq
->start
, erq
->head
, erq
->tail
);
480 static void error_print_context(struct drm_i915_error_state_buf
*m
,
482 const struct i915_gem_context_coredump
*ctx
)
484 const u32 period
= RUNTIME_INFO(m
->i915
)->cs_timestamp_period_ns
;
486 err_printf(m
, "%s%s[%d] prio %d, guilty %d active %d, runtime total %lluns, avg %lluns\n",
487 header
, ctx
->comm
, ctx
->pid
, ctx
->sched_attr
.priority
,
488 ctx
->guilty
, ctx
->active
,
489 ctx
->total_runtime
* period
,
490 mul_u32_u32(ctx
->avg_runtime
, period
));
493 static struct i915_vma_coredump
*
494 __find_vma(struct i915_vma_coredump
*vma
, const char *name
)
497 if (strcmp(vma
->name
, name
) == 0)
505 static struct i915_vma_coredump
*
506 find_batch(const struct intel_engine_coredump
*ee
)
508 return __find_vma(ee
->vma
, "batch");
511 static void error_print_engine(struct drm_i915_error_state_buf
*m
,
512 const struct intel_engine_coredump
*ee
)
514 struct i915_vma_coredump
*batch
;
517 err_printf(m
, "%s command stream:\n", ee
->engine
->name
);
518 err_printf(m
, " CCID: 0x%08x\n", ee
->ccid
);
519 err_printf(m
, " START: 0x%08x\n", ee
->start
);
520 err_printf(m
, " HEAD: 0x%08x [0x%08x]\n", ee
->head
, ee
->rq_head
);
521 err_printf(m
, " TAIL: 0x%08x [0x%08x, 0x%08x]\n",
522 ee
->tail
, ee
->rq_post
, ee
->rq_tail
);
523 err_printf(m
, " CTL: 0x%08x\n", ee
->ctl
);
524 err_printf(m
, " MODE: 0x%08x\n", ee
->mode
);
525 err_printf(m
, " HWS: 0x%08x\n", ee
->hws
);
526 err_printf(m
, " ACTHD: 0x%08x %08x\n",
527 (u32
)(ee
->acthd
>>32), (u32
)ee
->acthd
);
528 err_printf(m
, " IPEIR: 0x%08x\n", ee
->ipeir
);
529 err_printf(m
, " IPEHR: 0x%08x\n", ee
->ipehr
);
530 err_printf(m
, " ESR: 0x%08x\n", ee
->esr
);
532 error_print_instdone(m
, ee
);
534 batch
= find_batch(ee
);
536 u64 start
= batch
->gtt_offset
;
537 u64 end
= start
+ batch
->gtt_size
;
539 err_printf(m
, " batch: [0x%08x_%08x, 0x%08x_%08x]\n",
540 upper_32_bits(start
), lower_32_bits(start
),
541 upper_32_bits(end
), lower_32_bits(end
));
543 if (INTEL_GEN(m
->i915
) >= 4) {
544 err_printf(m
, " BBADDR: 0x%08x_%08x\n",
545 (u32
)(ee
->bbaddr
>>32), (u32
)ee
->bbaddr
);
546 err_printf(m
, " BB_STATE: 0x%08x\n", ee
->bbstate
);
547 err_printf(m
, " INSTPS: 0x%08x\n", ee
->instps
);
549 err_printf(m
, " INSTPM: 0x%08x\n", ee
->instpm
);
550 err_printf(m
, " FADDR: 0x%08x %08x\n", upper_32_bits(ee
->faddr
),
551 lower_32_bits(ee
->faddr
));
552 if (INTEL_GEN(m
->i915
) >= 6) {
553 err_printf(m
, " RC PSMI: 0x%08x\n", ee
->rc_psmi
);
554 err_printf(m
, " FAULT_REG: 0x%08x\n", ee
->fault_reg
);
556 if (HAS_PPGTT(m
->i915
)) {
557 err_printf(m
, " GFX_MODE: 0x%08x\n", ee
->vm_info
.gfx_mode
);
559 if (INTEL_GEN(m
->i915
) >= 8) {
561 for (i
= 0; i
< 4; i
++)
562 err_printf(m
, " PDP%d: 0x%016llx\n",
563 i
, ee
->vm_info
.pdp
[i
]);
565 err_printf(m
, " PP_DIR_BASE: 0x%08x\n",
566 ee
->vm_info
.pp_dir_base
);
569 err_printf(m
, " engine reset count: %u\n", ee
->reset_count
);
571 for (n
= 0; n
< ee
->num_ports
; n
++) {
572 err_printf(m
, " ELSP[%d]:", n
);
573 error_print_request(m
, " ", &ee
->execlist
[n
]);
576 error_print_context(m
, " Active context: ", &ee
->context
);
579 void i915_error_printf(struct drm_i915_error_state_buf
*e
, const char *f
, ...)
584 i915_error_vprintf(e
, f
, args
);
588 static void print_error_vma(struct drm_i915_error_state_buf
*m
,
589 const struct intel_engine_cs
*engine
,
590 const struct i915_vma_coredump
*vma
)
592 char out
[ASCII85_BUFSZ
];
598 err_printf(m
, "%s --- %s = 0x%08x %08x\n",
599 engine
? engine
->name
: "global", vma
->name
,
600 upper_32_bits(vma
->gtt_offset
),
601 lower_32_bits(vma
->gtt_offset
));
603 if (vma
->gtt_page_sizes
> I915_GTT_PAGE_SIZE_4K
)
604 err_printf(m
, "gtt_page_sizes = 0x%08x\n", vma
->gtt_page_sizes
);
606 err_compression_marker(m
);
607 for (page
= 0; page
< vma
->page_count
; page
++) {
611 if (page
== vma
->page_count
- 1)
613 len
= ascii85_encode_len(len
);
615 for (i
= 0; i
< len
; i
++)
616 err_puts(m
, ascii85_encode(vma
->pages
[page
][i
], out
));
621 static void err_print_capabilities(struct drm_i915_error_state_buf
*m
,
622 const struct intel_device_info
*info
,
623 const struct intel_runtime_info
*runtime
,
624 const struct intel_driver_caps
*caps
)
626 struct drm_printer p
= i915_error_printer(m
);
628 intel_device_info_print_static(info
, &p
);
629 intel_device_info_print_runtime(runtime
, &p
);
630 intel_device_info_print_topology(&runtime
->sseu
, &p
);
631 intel_driver_caps_print(caps
, &p
);
634 static void err_print_params(struct drm_i915_error_state_buf
*m
,
635 const struct i915_params
*params
)
637 struct drm_printer p
= i915_error_printer(m
);
639 i915_params_dump(params
, &p
);
642 static void err_print_pciid(struct drm_i915_error_state_buf
*m
,
643 struct drm_i915_private
*i915
)
645 struct pci_dev
*pdev
= i915
->drm
.pdev
;
647 err_printf(m
, "PCI ID: 0x%04x\n", pdev
->device
);
648 err_printf(m
, "PCI Revision: 0x%02x\n", pdev
->revision
);
649 err_printf(m
, "PCI Subsystem: %04x:%04x\n",
650 pdev
->subsystem_vendor
,
651 pdev
->subsystem_device
);
654 static void err_print_uc(struct drm_i915_error_state_buf
*m
,
655 const struct intel_uc_coredump
*error_uc
)
657 struct drm_printer p
= i915_error_printer(m
);
659 intel_uc_fw_dump(&error_uc
->guc_fw
, &p
);
660 intel_uc_fw_dump(&error_uc
->huc_fw
, &p
);
661 print_error_vma(m
, NULL
, error_uc
->guc_log
);
664 static void err_free_sgl(struct scatterlist
*sgl
)
667 struct scatterlist
*sg
;
669 for (sg
= sgl
; !sg_is_chain(sg
); sg
++) {
675 sg
= sg_is_last(sg
) ? NULL
: sg_chain_ptr(sg
);
676 free_page((unsigned long)sgl
);
681 static void err_print_gt(struct drm_i915_error_state_buf
*m
,
682 struct intel_gt_coredump
*gt
)
684 const struct intel_engine_coredump
*ee
;
687 err_printf(m
, "GT awake: %s\n", yesno(gt
->awake
));
688 err_printf(m
, "EIR: 0x%08x\n", gt
->eir
);
689 err_printf(m
, "IER: 0x%08x\n", gt
->ier
);
690 for (i
= 0; i
< gt
->ngtier
; i
++)
691 err_printf(m
, "GTIER[%d]: 0x%08x\n", i
, gt
->gtier
[i
]);
692 err_printf(m
, "PGTBL_ER: 0x%08x\n", gt
->pgtbl_er
);
693 err_printf(m
, "FORCEWAKE: 0x%08x\n", gt
->forcewake
);
694 err_printf(m
, "DERRMR: 0x%08x\n", gt
->derrmr
);
696 for (i
= 0; i
< gt
->nfence
; i
++)
697 err_printf(m
, " fence[%d] = %08llx\n", i
, gt
->fence
[i
]);
699 if (IS_GEN_RANGE(m
->i915
, 6, 11)) {
700 err_printf(m
, "ERROR: 0x%08x\n", gt
->error
);
701 err_printf(m
, "DONE_REG: 0x%08x\n", gt
->done_reg
);
704 if (INTEL_GEN(m
->i915
) >= 8)
705 err_printf(m
, "FAULT_TLB_DATA: 0x%08x 0x%08x\n",
706 gt
->fault_data1
, gt
->fault_data0
);
708 if (IS_GEN(m
->i915
, 7))
709 err_printf(m
, "ERR_INT: 0x%08x\n", gt
->err_int
);
711 if (IS_GEN_RANGE(m
->i915
, 8, 11))
712 err_printf(m
, "GTT_CACHE_EN: 0x%08x\n", gt
->gtt_cache
);
714 if (IS_GEN(m
->i915
, 12))
715 err_printf(m
, "AUX_ERR_DBG: 0x%08x\n", gt
->aux_err
);
717 if (INTEL_GEN(m
->i915
) >= 12) {
720 for (i
= 0; i
< GEN12_SFC_DONE_MAX
; i
++)
721 err_printf(m
, " SFC_DONE[%d]: 0x%08x\n", i
,
724 err_printf(m
, " GAM_DONE: 0x%08x\n", gt
->gam_done
);
727 for (ee
= gt
->engine
; ee
; ee
= ee
->next
) {
728 const struct i915_vma_coredump
*vma
;
730 error_print_engine(m
, ee
);
731 for (vma
= ee
->vma
; vma
; vma
= vma
->next
)
732 print_error_vma(m
, ee
->engine
, vma
);
736 err_print_uc(m
, gt
->uc
);
739 static void __err_print_to_sgl(struct drm_i915_error_state_buf
*m
,
740 struct i915_gpu_coredump
*error
)
742 const struct intel_engine_coredump
*ee
;
743 struct timespec64 ts
;
745 if (*error
->error_msg
)
746 err_printf(m
, "%s\n", error
->error_msg
);
747 err_printf(m
, "Kernel: %s %s\n",
748 init_utsname()->release
,
749 init_utsname()->machine
);
750 err_printf(m
, "Driver: %s\n", DRIVER_DATE
);
751 ts
= ktime_to_timespec64(error
->time
);
752 err_printf(m
, "Time: %lld s %ld us\n",
753 (s64
)ts
.tv_sec
, ts
.tv_nsec
/ NSEC_PER_USEC
);
754 ts
= ktime_to_timespec64(error
->boottime
);
755 err_printf(m
, "Boottime: %lld s %ld us\n",
756 (s64
)ts
.tv_sec
, ts
.tv_nsec
/ NSEC_PER_USEC
);
757 ts
= ktime_to_timespec64(error
->uptime
);
758 err_printf(m
, "Uptime: %lld s %ld us\n",
759 (s64
)ts
.tv_sec
, ts
.tv_nsec
/ NSEC_PER_USEC
);
760 err_printf(m
, "Capture: %lu jiffies; %d ms ago\n",
761 error
->capture
, jiffies_to_msecs(jiffies
- error
->capture
));
763 for (ee
= error
->gt
? error
->gt
->engine
: NULL
; ee
; ee
= ee
->next
)
764 err_printf(m
, "Active process (on ring %s): %s [%d]\n",
769 err_printf(m
, "Reset count: %u\n", error
->reset_count
);
770 err_printf(m
, "Suspend count: %u\n", error
->suspend_count
);
771 err_printf(m
, "Platform: %s\n", intel_platform_name(error
->device_info
.platform
));
772 err_printf(m
, "Subplatform: 0x%x\n",
773 intel_subplatform(&error
->runtime_info
,
774 error
->device_info
.platform
));
775 err_print_pciid(m
, m
->i915
);
777 err_printf(m
, "IOMMU enabled?: %d\n", error
->iommu
);
779 if (HAS_CSR(m
->i915
)) {
780 struct intel_csr
*csr
= &m
->i915
->csr
;
782 err_printf(m
, "DMC loaded: %s\n",
783 yesno(csr
->dmc_payload
!= NULL
));
784 err_printf(m
, "DMC fw version: %d.%d\n",
785 CSR_VERSION_MAJOR(csr
->version
),
786 CSR_VERSION_MINOR(csr
->version
));
789 err_printf(m
, "RPM wakelock: %s\n", yesno(error
->wakelock
));
790 err_printf(m
, "PM suspended: %s\n", yesno(error
->suspended
));
793 err_print_gt(m
, error
->gt
);
796 intel_overlay_print_error_state(m
, error
->overlay
);
799 intel_display_print_error_state(m
, error
->display
);
801 err_print_capabilities(m
, &error
->device_info
, &error
->runtime_info
,
802 &error
->driver_caps
);
803 err_print_params(m
, &error
->params
);
806 static int err_print_to_sgl(struct i915_gpu_coredump
*error
)
808 struct drm_i915_error_state_buf m
;
811 return PTR_ERR(error
);
813 if (READ_ONCE(error
->sgl
))
816 memset(&m
, 0, sizeof(m
));
817 m
.i915
= error
->i915
;
819 __err_print_to_sgl(&m
, error
);
822 __sg_set_buf(m
.cur
++, m
.buf
, m
.bytes
, m
.iter
);
827 GEM_BUG_ON(m
.end
< m
.cur
);
828 sg_mark_end(m
.cur
- 1);
830 GEM_BUG_ON(m
.sgl
&& !m
.cur
);
837 if (cmpxchg(&error
->sgl
, NULL
, m
.sgl
))
843 ssize_t
i915_gpu_coredump_copy_to_buffer(struct i915_gpu_coredump
*error
,
844 char *buf
, loff_t off
, size_t rem
)
846 struct scatterlist
*sg
;
854 err
= err_print_to_sgl(error
);
858 sg
= READ_ONCE(error
->fit
);
859 if (!sg
|| off
< sg
->dma_address
)
864 pos
= sg
->dma_address
;
869 if (sg_is_chain(sg
)) {
870 sg
= sg_chain_ptr(sg
);
871 GEM_BUG_ON(sg_is_chain(sg
));
875 if (pos
+ len
<= off
) {
882 GEM_BUG_ON(off
- pos
> len
);
889 GEM_BUG_ON(!len
|| len
> sg
->length
);
891 memcpy(buf
, page_address(sg_page(sg
)) + start
, len
);
899 WRITE_ONCE(error
->fit
, sg
);
902 } while (!sg_is_last(sg
++));
907 static void i915_vma_coredump_free(struct i915_vma_coredump
*vma
)
910 struct i915_vma_coredump
*next
= vma
->next
;
913 for (page
= 0; page
< vma
->page_count
; page
++)
914 free_page((unsigned long)vma
->pages
[page
]);
921 static void cleanup_params(struct i915_gpu_coredump
*error
)
923 i915_params_free(&error
->params
);
926 static void cleanup_uc(struct intel_uc_coredump
*uc
)
928 kfree(uc
->guc_fw
.path
);
929 kfree(uc
->huc_fw
.path
);
930 i915_vma_coredump_free(uc
->guc_log
);
935 static void cleanup_gt(struct intel_gt_coredump
*gt
)
938 struct intel_engine_coredump
*ee
= gt
->engine
;
940 gt
->engine
= ee
->next
;
942 i915_vma_coredump_free(ee
->vma
);
952 void __i915_gpu_coredump_free(struct kref
*error_ref
)
954 struct i915_gpu_coredump
*error
=
955 container_of(error_ref
, typeof(*error
), ref
);
958 struct intel_gt_coredump
*gt
= error
->gt
;
960 error
->gt
= gt
->next
;
964 kfree(error
->overlay
);
965 kfree(error
->display
);
967 cleanup_params(error
);
969 err_free_sgl(error
->sgl
);
973 static struct i915_vma_coredump
*
974 i915_vma_coredump_create(const struct intel_gt
*gt
,
975 const struct i915_vma
*vma
,
977 struct i915_vma_compress
*compress
)
979 struct i915_ggtt
*ggtt
= gt
->ggtt
;
980 const u64 slot
= ggtt
->error_capture
.start
;
981 struct i915_vma_coredump
*dst
;
982 unsigned long num_pages
;
983 struct sgt_iter iter
;
988 if (!vma
|| !vma
->pages
|| !compress
)
991 num_pages
= min_t(u64
, vma
->size
, vma
->obj
->base
.size
) >> PAGE_SHIFT
;
992 num_pages
= DIV_ROUND_UP(10 * num_pages
, 8); /* worstcase zlib growth */
993 dst
= kmalloc(sizeof(*dst
) + num_pages
* sizeof(u32
*), ALLOW_FAIL
);
997 if (!compress_start(compress
)) {
1002 strcpy(dst
->name
, name
);
1005 dst
->gtt_offset
= vma
->node
.start
;
1006 dst
->gtt_size
= vma
->node
.size
;
1007 dst
->gtt_page_sizes
= vma
->page_sizes
.gtt
;
1008 dst
->num_pages
= num_pages
;
1009 dst
->page_count
= 0;
1013 if (drm_mm_node_allocated(&ggtt
->error_capture
)) {
1017 for_each_sgt_daddr(dma
, iter
, vma
->pages
) {
1018 ggtt
->vm
.insert_page(&ggtt
->vm
, dma
, slot
,
1019 I915_CACHE_NONE
, 0);
1022 s
= io_mapping_map_wc(&ggtt
->iomap
, slot
, PAGE_SIZE
);
1023 ret
= compress_page(compress
,
1024 (void __force
*)s
, dst
,
1026 io_mapping_unmap(s
);
1030 } else if (i915_gem_object_is_lmem(vma
->obj
)) {
1031 struct intel_memory_region
*mem
= vma
->obj
->mm
.region
;
1034 for_each_sgt_daddr(dma
, iter
, vma
->pages
) {
1037 s
= io_mapping_map_wc(&mem
->iomap
, dma
, PAGE_SIZE
);
1038 ret
= compress_page(compress
,
1039 (void __force
*)s
, dst
,
1041 io_mapping_unmap(s
);
1048 for_each_sgt_page(page
, iter
, vma
->pages
) {
1051 drm_clflush_pages(&page
, 1);
1054 ret
= compress_page(compress
, s
, dst
, false);
1057 drm_clflush_pages(&page
, 1);
1064 if (ret
|| compress_flush(compress
, dst
)) {
1065 while (dst
->page_count
--)
1066 pool_free(&compress
->pool
, dst
->pages
[dst
->page_count
]);
1070 compress_finish(compress
);
1075 static void gt_record_fences(struct intel_gt_coredump
*gt
)
1077 struct i915_ggtt
*ggtt
= gt
->_gt
->ggtt
;
1078 struct intel_uncore
*uncore
= gt
->_gt
->uncore
;
1081 if (INTEL_GEN(uncore
->i915
) >= 6) {
1082 for (i
= 0; i
< ggtt
->num_fences
; i
++)
1084 intel_uncore_read64(uncore
,
1085 FENCE_REG_GEN6_LO(i
));
1086 } else if (INTEL_GEN(uncore
->i915
) >= 4) {
1087 for (i
= 0; i
< ggtt
->num_fences
; i
++)
1089 intel_uncore_read64(uncore
,
1090 FENCE_REG_965_LO(i
));
1092 for (i
= 0; i
< ggtt
->num_fences
; i
++)
1094 intel_uncore_read(uncore
, FENCE_REG(i
));
1099 static void engine_record_registers(struct intel_engine_coredump
*ee
)
1101 const struct intel_engine_cs
*engine
= ee
->engine
;
1102 struct drm_i915_private
*i915
= engine
->i915
;
1104 if (INTEL_GEN(i915
) >= 6) {
1105 ee
->rc_psmi
= ENGINE_READ(engine
, RING_PSMI_CTL
);
1107 if (INTEL_GEN(i915
) >= 12)
1108 ee
->fault_reg
= intel_uncore_read(engine
->uncore
,
1109 GEN12_RING_FAULT_REG
);
1110 else if (INTEL_GEN(i915
) >= 8)
1111 ee
->fault_reg
= intel_uncore_read(engine
->uncore
,
1112 GEN8_RING_FAULT_REG
);
1114 ee
->fault_reg
= GEN6_RING_FAULT_REG_READ(engine
);
1117 if (INTEL_GEN(i915
) >= 4) {
1118 ee
->esr
= ENGINE_READ(engine
, RING_ESR
);
1119 ee
->faddr
= ENGINE_READ(engine
, RING_DMA_FADD
);
1120 ee
->ipeir
= ENGINE_READ(engine
, RING_IPEIR
);
1121 ee
->ipehr
= ENGINE_READ(engine
, RING_IPEHR
);
1122 ee
->instps
= ENGINE_READ(engine
, RING_INSTPS
);
1123 ee
->bbaddr
= ENGINE_READ(engine
, RING_BBADDR
);
1124 ee
->ccid
= ENGINE_READ(engine
, CCID
);
1125 if (INTEL_GEN(i915
) >= 8) {
1126 ee
->faddr
|= (u64
)ENGINE_READ(engine
, RING_DMA_FADD_UDW
) << 32;
1127 ee
->bbaddr
|= (u64
)ENGINE_READ(engine
, RING_BBADDR_UDW
) << 32;
1129 ee
->bbstate
= ENGINE_READ(engine
, RING_BBSTATE
);
1131 ee
->faddr
= ENGINE_READ(engine
, DMA_FADD_I8XX
);
1132 ee
->ipeir
= ENGINE_READ(engine
, IPEIR
);
1133 ee
->ipehr
= ENGINE_READ(engine
, IPEHR
);
1136 intel_engine_get_instdone(engine
, &ee
->instdone
);
1138 ee
->instpm
= ENGINE_READ(engine
, RING_INSTPM
);
1139 ee
->acthd
= intel_engine_get_active_head(engine
);
1140 ee
->start
= ENGINE_READ(engine
, RING_START
);
1141 ee
->head
= ENGINE_READ(engine
, RING_HEAD
);
1142 ee
->tail
= ENGINE_READ(engine
, RING_TAIL
);
1143 ee
->ctl
= ENGINE_READ(engine
, RING_CTL
);
1144 if (INTEL_GEN(i915
) > 2)
1145 ee
->mode
= ENGINE_READ(engine
, RING_MI_MODE
);
1147 if (!HWS_NEEDS_PHYSICAL(i915
)) {
1150 if (IS_GEN(i915
, 7)) {
1151 switch (engine
->id
) {
1153 MISSING_CASE(engine
->id
);
1156 mmio
= RENDER_HWS_PGA_GEN7
;
1159 mmio
= BLT_HWS_PGA_GEN7
;
1162 mmio
= BSD_HWS_PGA_GEN7
;
1165 mmio
= VEBOX_HWS_PGA_GEN7
;
1168 } else if (IS_GEN(engine
->i915
, 6)) {
1169 mmio
= RING_HWS_PGA_GEN6(engine
->mmio_base
);
1171 /* XXX: gen8 returns to sanity */
1172 mmio
= RING_HWS_PGA(engine
->mmio_base
);
1175 ee
->hws
= intel_uncore_read(engine
->uncore
, mmio
);
1178 ee
->reset_count
= i915_reset_engine_count(&i915
->gpu_error
, engine
);
1180 if (HAS_PPGTT(i915
)) {
1183 ee
->vm_info
.gfx_mode
= ENGINE_READ(engine
, RING_MODE_GEN7
);
1185 if (IS_GEN(i915
, 6)) {
1186 ee
->vm_info
.pp_dir_base
=
1187 ENGINE_READ(engine
, RING_PP_DIR_BASE_READ
);
1188 } else if (IS_GEN(i915
, 7)) {
1189 ee
->vm_info
.pp_dir_base
=
1190 ENGINE_READ(engine
, RING_PP_DIR_BASE
);
1191 } else if (INTEL_GEN(i915
) >= 8) {
1192 u32 base
= engine
->mmio_base
;
1194 for (i
= 0; i
< 4; i
++) {
1195 ee
->vm_info
.pdp
[i
] =
1196 intel_uncore_read(engine
->uncore
,
1197 GEN8_RING_PDP_UDW(base
, i
));
1198 ee
->vm_info
.pdp
[i
] <<= 32;
1199 ee
->vm_info
.pdp
[i
] |=
1200 intel_uncore_read(engine
->uncore
,
1201 GEN8_RING_PDP_LDW(base
, i
));
1207 static void record_request(const struct i915_request
*request
,
1208 struct i915_request_coredump
*erq
)
1210 const struct i915_gem_context
*ctx
;
1212 erq
->flags
= request
->fence
.flags
;
1213 erq
->context
= request
->fence
.context
;
1214 erq
->seqno
= request
->fence
.seqno
;
1215 erq
->sched_attr
= request
->sched
.attr
;
1216 erq
->start
= i915_ggtt_offset(request
->ring
->vma
);
1217 erq
->head
= request
->head
;
1218 erq
->tail
= request
->tail
;
1222 ctx
= rcu_dereference(request
->context
->gem_context
);
1224 erq
->pid
= pid_nr(ctx
->pid
);
1228 static void engine_record_execlists(struct intel_engine_coredump
*ee
)
1230 const struct intel_engine_execlists
* const el
= &ee
->engine
->execlists
;
1231 struct i915_request
* const *port
= el
->active
;
1235 record_request(*port
++, &ee
->execlist
[n
++]);
1240 static bool record_context(struct i915_gem_context_coredump
*e
,
1241 const struct i915_request
*rq
)
1243 struct i915_gem_context
*ctx
;
1244 struct task_struct
*task
;
1248 ctx
= rcu_dereference(rq
->context
->gem_context
);
1249 if (ctx
&& !kref_get_unless_zero(&ctx
->ref
))
1256 task
= pid_task(ctx
->pid
, PIDTYPE_PID
);
1258 strcpy(e
->comm
, task
->comm
);
1263 e
->sched_attr
= ctx
->sched
;
1264 e
->guilty
= atomic_read(&ctx
->guilty_count
);
1265 e
->active
= atomic_read(&ctx
->active_count
);
1267 e
->total_runtime
= rq
->context
->runtime
.total
;
1268 e
->avg_runtime
= ewma_runtime_read(&rq
->context
->runtime
.avg
);
1270 simulated
= i915_gem_context_no_error_capture(ctx
);
1272 i915_gem_context_put(ctx
);
1276 struct intel_engine_capture_vma
{
1277 struct intel_engine_capture_vma
*next
;
1278 struct i915_vma
*vma
;
1282 static struct intel_engine_capture_vma
*
1283 capture_vma(struct intel_engine_capture_vma
*next
,
1284 struct i915_vma
*vma
,
1288 struct intel_engine_capture_vma
*c
;
1293 c
= kmalloc(sizeof(*c
), gfp
);
1297 if (!i915_active_acquire_if_busy(&vma
->active
)) {
1302 strcpy(c
->name
, name
);
1303 c
->vma
= i915_vma_get(vma
);
1309 static struct intel_engine_capture_vma
*
1310 capture_user(struct intel_engine_capture_vma
*capture
,
1311 const struct i915_request
*rq
,
1314 struct i915_capture_list
*c
;
1316 for (c
= rq
->capture_list
; c
; c
= c
->next
)
1317 capture
= capture_vma(capture
, c
->vma
, "user", gfp
);
1322 static struct i915_vma_coredump
*
1323 capture_object(const struct intel_gt
*gt
,
1324 struct drm_i915_gem_object
*obj
,
1326 struct i915_vma_compress
*compress
)
1328 if (obj
&& i915_gem_object_has_pages(obj
)) {
1329 struct i915_vma fake
= {
1330 .node
= { .start
= U64_MAX
, .size
= obj
->base
.size
},
1331 .size
= obj
->base
.size
,
1332 .pages
= obj
->mm
.pages
,
1336 return i915_vma_coredump_create(gt
, &fake
, name
, compress
);
1342 static void add_vma(struct intel_engine_coredump
*ee
,
1343 struct i915_vma_coredump
*vma
)
1346 vma
->next
= ee
->vma
;
1351 struct intel_engine_coredump
*
1352 intel_engine_coredump_alloc(struct intel_engine_cs
*engine
, gfp_t gfp
)
1354 struct intel_engine_coredump
*ee
;
1356 ee
= kzalloc(sizeof(*ee
), gfp
);
1360 ee
->engine
= engine
;
1362 engine_record_registers(ee
);
1363 engine_record_execlists(ee
);
1368 struct intel_engine_capture_vma
*
1369 intel_engine_coredump_add_request(struct intel_engine_coredump
*ee
,
1370 struct i915_request
*rq
,
1373 struct intel_engine_capture_vma
*vma
= NULL
;
1375 ee
->simulated
|= record_context(&ee
->context
, rq
);
1380 * We need to copy these to an anonymous buffer
1381 * as the simplest method to avoid being overwritten
1384 vma
= capture_vma(vma
, rq
->batch
, "batch", gfp
);
1385 vma
= capture_user(vma
, rq
, gfp
);
1386 vma
= capture_vma(vma
, rq
->ring
->vma
, "ring", gfp
);
1387 vma
= capture_vma(vma
, rq
->context
->state
, "HW context", gfp
);
1389 ee
->rq_head
= rq
->head
;
1390 ee
->rq_post
= rq
->postfix
;
1391 ee
->rq_tail
= rq
->tail
;
1397 intel_engine_coredump_add_vma(struct intel_engine_coredump
*ee
,
1398 struct intel_engine_capture_vma
*capture
,
1399 struct i915_vma_compress
*compress
)
1401 const struct intel_engine_cs
*engine
= ee
->engine
;
1404 struct intel_engine_capture_vma
*this = capture
;
1405 struct i915_vma
*vma
= this->vma
;
1408 i915_vma_coredump_create(engine
->gt
,
1412 i915_active_release(&vma
->active
);
1415 capture
= this->next
;
1420 i915_vma_coredump_create(engine
->gt
,
1421 engine
->status_page
.vma
,
1426 i915_vma_coredump_create(engine
->gt
,
1432 capture_object(engine
->gt
,
1433 engine
->default_state
,
1438 static struct intel_engine_coredump
*
1439 capture_engine(struct intel_engine_cs
*engine
,
1440 struct i915_vma_compress
*compress
)
1442 struct intel_engine_capture_vma
*capture
= NULL
;
1443 struct intel_engine_coredump
*ee
;
1444 struct i915_request
*rq
;
1445 unsigned long flags
;
1447 ee
= intel_engine_coredump_alloc(engine
, GFP_KERNEL
);
1451 spin_lock_irqsave(&engine
->active
.lock
, flags
);
1452 rq
= intel_engine_find_active_request(engine
);
1454 capture
= intel_engine_coredump_add_request(ee
, rq
,
1456 spin_unlock_irqrestore(&engine
->active
.lock
, flags
);
1462 intel_engine_coredump_add_vma(ee
, capture
, compress
);
1468 gt_record_engines(struct intel_gt_coredump
*gt
,
1469 struct i915_vma_compress
*compress
)
1471 struct intel_engine_cs
*engine
;
1472 enum intel_engine_id id
;
1474 for_each_engine(engine
, gt
->_gt
, id
) {
1475 struct intel_engine_coredump
*ee
;
1477 /* Refill our page pool before entering atomic section */
1478 pool_refill(&compress
->pool
, ALLOW_FAIL
);
1480 ee
= capture_engine(engine
, compress
);
1484 gt
->simulated
|= ee
->simulated
;
1485 if (ee
->simulated
) {
1490 ee
->next
= gt
->engine
;
1495 static struct intel_uc_coredump
*
1496 gt_record_uc(struct intel_gt_coredump
*gt
,
1497 struct i915_vma_compress
*compress
)
1499 const struct intel_uc
*uc
= >
->_gt
->uc
;
1500 struct intel_uc_coredump
*error_uc
;
1502 error_uc
= kzalloc(sizeof(*error_uc
), ALLOW_FAIL
);
1506 memcpy(&error_uc
->guc_fw
, &uc
->guc
.fw
, sizeof(uc
->guc
.fw
));
1507 memcpy(&error_uc
->huc_fw
, &uc
->huc
.fw
, sizeof(uc
->huc
.fw
));
1509 /* Non-default firmware paths will be specified by the modparam.
1510 * As modparams are generally accesible from the userspace make
1511 * explicit copies of the firmware paths.
1513 error_uc
->guc_fw
.path
= kstrdup(uc
->guc
.fw
.path
, ALLOW_FAIL
);
1514 error_uc
->huc_fw
.path
= kstrdup(uc
->huc
.fw
.path
, ALLOW_FAIL
);
1516 i915_vma_coredump_create(gt
->_gt
,
1517 uc
->guc
.log
.vma
, "GuC log buffer",
1523 static void gt_capture_prepare(struct intel_gt_coredump
*gt
)
1525 struct i915_ggtt
*ggtt
= gt
->_gt
->ggtt
;
1527 mutex_lock(&ggtt
->error_mutex
);
1530 static void gt_capture_finish(struct intel_gt_coredump
*gt
)
1532 struct i915_ggtt
*ggtt
= gt
->_gt
->ggtt
;
1534 if (drm_mm_node_allocated(&ggtt
->error_capture
))
1535 ggtt
->vm
.clear_range(&ggtt
->vm
,
1536 ggtt
->error_capture
.start
,
1539 mutex_unlock(&ggtt
->error_mutex
);
1542 /* Capture all registers which don't fit into another category. */
1543 static void gt_record_regs(struct intel_gt_coredump
*gt
)
1545 struct intel_uncore
*uncore
= gt
->_gt
->uncore
;
1546 struct drm_i915_private
*i915
= uncore
->i915
;
1550 * General organization
1551 * 1. Registers specific to a single generation
1552 * 2. Registers which belong to multiple generations
1553 * 3. Feature specific registers.
1554 * 4. Everything else
1555 * Please try to follow the order.
1558 /* 1: Registers specific to a single generation */
1559 if (IS_VALLEYVIEW(i915
)) {
1560 gt
->gtier
[0] = intel_uncore_read(uncore
, GTIER
);
1561 gt
->ier
= intel_uncore_read(uncore
, VLV_IER
);
1562 gt
->forcewake
= intel_uncore_read_fw(uncore
, FORCEWAKE_VLV
);
1565 if (IS_GEN(i915
, 7))
1566 gt
->err_int
= intel_uncore_read(uncore
, GEN7_ERR_INT
);
1568 if (INTEL_GEN(i915
) >= 12) {
1569 gt
->fault_data0
= intel_uncore_read(uncore
,
1570 GEN12_FAULT_TLB_DATA0
);
1571 gt
->fault_data1
= intel_uncore_read(uncore
,
1572 GEN12_FAULT_TLB_DATA1
);
1573 } else if (INTEL_GEN(i915
) >= 8) {
1574 gt
->fault_data0
= intel_uncore_read(uncore
,
1575 GEN8_FAULT_TLB_DATA0
);
1576 gt
->fault_data1
= intel_uncore_read(uncore
,
1577 GEN8_FAULT_TLB_DATA1
);
1580 if (IS_GEN(i915
, 6)) {
1581 gt
->forcewake
= intel_uncore_read_fw(uncore
, FORCEWAKE
);
1582 gt
->gab_ctl
= intel_uncore_read(uncore
, GAB_CTL
);
1583 gt
->gfx_mode
= intel_uncore_read(uncore
, GFX_MODE
);
1586 /* 2: Registers which belong to multiple generations */
1587 if (INTEL_GEN(i915
) >= 7)
1588 gt
->forcewake
= intel_uncore_read_fw(uncore
, FORCEWAKE_MT
);
1590 if (INTEL_GEN(i915
) >= 6) {
1591 gt
->derrmr
= intel_uncore_read(uncore
, DERRMR
);
1592 if (INTEL_GEN(i915
) < 12) {
1593 gt
->error
= intel_uncore_read(uncore
, ERROR_GEN6
);
1594 gt
->done_reg
= intel_uncore_read(uncore
, DONE_REG
);
1598 /* 3: Feature specific registers */
1599 if (IS_GEN_RANGE(i915
, 6, 7)) {
1600 gt
->gam_ecochk
= intel_uncore_read(uncore
, GAM_ECOCHK
);
1601 gt
->gac_eco
= intel_uncore_read(uncore
, GAC_ECO_BITS
);
1604 if (IS_GEN_RANGE(i915
, 8, 11))
1605 gt
->gtt_cache
= intel_uncore_read(uncore
, HSW_GTT_CACHE_EN
);
1607 if (IS_GEN(i915
, 12))
1608 gt
->aux_err
= intel_uncore_read(uncore
, GEN12_AUX_ERR_DBG
);
1610 if (INTEL_GEN(i915
) >= 12) {
1611 for (i
= 0; i
< GEN12_SFC_DONE_MAX
; i
++) {
1613 intel_uncore_read(uncore
, GEN12_SFC_DONE(i
));
1616 gt
->gam_done
= intel_uncore_read(uncore
, GEN12_GAM_DONE
);
1619 /* 4: Everything else */
1620 if (INTEL_GEN(i915
) >= 11) {
1621 gt
->ier
= intel_uncore_read(uncore
, GEN8_DE_MISC_IER
);
1623 intel_uncore_read(uncore
,
1624 GEN11_RENDER_COPY_INTR_ENABLE
);
1626 intel_uncore_read(uncore
, GEN11_VCS_VECS_INTR_ENABLE
);
1628 intel_uncore_read(uncore
, GEN11_GUC_SG_INTR_ENABLE
);
1630 intel_uncore_read(uncore
,
1631 GEN11_GPM_WGBOXPERF_INTR_ENABLE
);
1633 intel_uncore_read(uncore
,
1634 GEN11_CRYPTO_RSVD_INTR_ENABLE
);
1636 intel_uncore_read(uncore
,
1637 GEN11_GUNIT_CSME_INTR_ENABLE
);
1639 } else if (INTEL_GEN(i915
) >= 8) {
1640 gt
->ier
= intel_uncore_read(uncore
, GEN8_DE_MISC_IER
);
1641 for (i
= 0; i
< 4; i
++)
1643 intel_uncore_read(uncore
, GEN8_GT_IER(i
));
1645 } else if (HAS_PCH_SPLIT(i915
)) {
1646 gt
->ier
= intel_uncore_read(uncore
, DEIER
);
1647 gt
->gtier
[0] = intel_uncore_read(uncore
, GTIER
);
1649 } else if (IS_GEN(i915
, 2)) {
1650 gt
->ier
= intel_uncore_read16(uncore
, GEN2_IER
);
1651 } else if (!IS_VALLEYVIEW(i915
)) {
1652 gt
->ier
= intel_uncore_read(uncore
, GEN2_IER
);
1654 gt
->eir
= intel_uncore_read(uncore
, EIR
);
1655 gt
->pgtbl_er
= intel_uncore_read(uncore
, PGTBL_ER
);
1659 * Generate a semi-unique error code. The code is not meant to have meaning, The
1660 * code's only purpose is to try to prevent false duplicated bug reports by
1661 * grossly estimating a GPU error state.
1663 * TODO Ideally, hashing the batchbuffer would be a very nice way to determine
1664 * the hang if we could strip the GTT offset information from it.
1666 * It's only a small step better than a random number in its current form.
1668 static u32
generate_ecode(const struct intel_engine_coredump
*ee
)
1671 * IPEHR would be an ideal way to detect errors, as it's the gross
1672 * measure of "the command that hung." However, has some very common
1673 * synchronization commands which almost always appear in the case
1674 * strictly a client bug. Use instdone to differentiate those some.
1676 return ee
? ee
->ipehr
^ ee
->instdone
.instdone
: 0;
1679 static const char *error_msg(struct i915_gpu_coredump
*error
)
1681 struct intel_engine_coredump
*first
= NULL
;
1682 struct intel_gt_coredump
*gt
;
1683 intel_engine_mask_t engines
;
1687 for (gt
= error
->gt
; gt
; gt
= gt
->next
) {
1688 struct intel_engine_coredump
*cs
;
1690 if (gt
->engine
&& !first
)
1693 for (cs
= gt
->engine
; cs
; cs
= cs
->next
)
1694 engines
|= cs
->engine
->mask
;
1697 len
= scnprintf(error
->error_msg
, sizeof(error
->error_msg
),
1698 "GPU HANG: ecode %d:%x:%08x",
1699 INTEL_GEN(error
->i915
), engines
,
1700 generate_ecode(first
));
1701 if (first
&& first
->context
.pid
) {
1702 /* Just show the first executing process, more is confusing */
1703 len
+= scnprintf(error
->error_msg
+ len
,
1704 sizeof(error
->error_msg
) - len
,
1706 first
->context
.comm
, first
->context
.pid
);
1709 return error
->error_msg
;
1712 static void capture_gen(struct i915_gpu_coredump
*error
)
1714 struct drm_i915_private
*i915
= error
->i915
;
1716 error
->wakelock
= atomic_read(&i915
->runtime_pm
.wakeref_count
);
1717 error
->suspended
= i915
->runtime_pm
.suspended
;
1720 #ifdef CONFIG_INTEL_IOMMU
1721 error
->iommu
= intel_iommu_gfx_mapped
;
1723 error
->reset_count
= i915_reset_count(&i915
->gpu_error
);
1724 error
->suspend_count
= i915
->suspend_count
;
1726 i915_params_copy(&error
->params
, &i915_modparams
);
1727 memcpy(&error
->device_info
,
1729 sizeof(error
->device_info
));
1730 memcpy(&error
->runtime_info
,
1732 sizeof(error
->runtime_info
));
1733 error
->driver_caps
= i915
->caps
;
1736 struct i915_gpu_coredump
*
1737 i915_gpu_coredump_alloc(struct drm_i915_private
*i915
, gfp_t gfp
)
1739 struct i915_gpu_coredump
*error
;
1741 if (!i915_modparams
.error_capture
)
1744 error
= kzalloc(sizeof(*error
), gfp
);
1748 kref_init(&error
->ref
);
1751 error
->time
= ktime_get_real();
1752 error
->boottime
= ktime_get_boottime();
1753 error
->uptime
= ktime_sub(ktime_get(), i915
->gt
.last_init_time
);
1754 error
->capture
= jiffies
;
1761 #define DAY_AS_SECONDS(x) (24 * 60 * 60 * (x))
1763 struct intel_gt_coredump
*
1764 intel_gt_coredump_alloc(struct intel_gt
*gt
, gfp_t gfp
)
1766 struct intel_gt_coredump
*gc
;
1768 gc
= kzalloc(sizeof(*gc
), gfp
);
1773 gc
->awake
= intel_gt_pm_is_awake(gt
);
1776 gt_record_fences(gc
);
1781 struct i915_vma_compress
*
1782 i915_vma_capture_prepare(struct intel_gt_coredump
*gt
)
1784 struct i915_vma_compress
*compress
;
1786 compress
= kmalloc(sizeof(*compress
), ALLOW_FAIL
);
1790 if (!compress_init(compress
)) {
1795 gt_capture_prepare(gt
);
1800 void i915_vma_capture_finish(struct intel_gt_coredump
*gt
,
1801 struct i915_vma_compress
*compress
)
1806 gt_capture_finish(gt
);
1808 compress_fini(compress
);
1812 struct i915_gpu_coredump
*i915_gpu_coredump(struct drm_i915_private
*i915
)
1814 struct i915_gpu_coredump
*error
;
1816 /* Check if GPU capture has been disabled */
1817 error
= READ_ONCE(i915
->gpu_error
.first_error
);
1821 error
= i915_gpu_coredump_alloc(i915
, ALLOW_FAIL
);
1823 return ERR_PTR(-ENOMEM
);
1825 error
->gt
= intel_gt_coredump_alloc(&i915
->gt
, ALLOW_FAIL
);
1827 struct i915_vma_compress
*compress
;
1829 compress
= i915_vma_capture_prepare(error
->gt
);
1833 return ERR_PTR(-ENOMEM
);
1836 gt_record_engines(error
->gt
, compress
);
1838 if (INTEL_INFO(i915
)->has_gt_uc
)
1839 error
->gt
->uc
= gt_record_uc(error
->gt
, compress
);
1841 i915_vma_capture_finish(error
->gt
, compress
);
1843 error
->simulated
|= error
->gt
->simulated
;
1846 error
->overlay
= intel_overlay_capture_error_state(i915
);
1847 error
->display
= intel_display_capture_error_state(i915
);
1852 void i915_error_state_store(struct i915_gpu_coredump
*error
)
1854 struct drm_i915_private
*i915
;
1857 if (IS_ERR_OR_NULL(error
))
1861 dev_info(i915
->drm
.dev
, "%s\n", error_msg(error
));
1863 if (error
->simulated
||
1864 cmpxchg(&i915
->gpu_error
.first_error
, NULL
, error
))
1867 i915_gpu_coredump_get(error
);
1869 if (!xchg(&warned
, true) &&
1870 ktime_get_real_seconds() - DRIVER_TIMESTAMP
< DAY_AS_SECONDS(180)) {
1871 pr_info("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n");
1872 pr_info("Please file a _new_ bug report at https://gitlab.freedesktop.org/drm/intel/issues/new.\n");
1873 pr_info("Please see https://gitlab.freedesktop.org/drm/intel/-/wikis/How-to-file-i915-bugs for details.\n");
1874 pr_info("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n");
1875 pr_info("The GPU crash dump is required to analyze GPU hangs, so please always attach it.\n");
1876 pr_info("GPU crash dump saved to /sys/class/drm/card%d/error\n",
1877 i915
->drm
.primary
->index
);
1882 * i915_capture_error_state - capture an error record for later analysis
1883 * @i915: i915 device
1885 * Should be called when an error is detected (either a hang or an error
1886 * interrupt) to capture error state from the time of the error. Fills
1887 * out a structure which becomes available in debugfs for user level tools
1890 void i915_capture_error_state(struct drm_i915_private
*i915
)
1892 struct i915_gpu_coredump
*error
;
1894 error
= i915_gpu_coredump(i915
);
1895 if (IS_ERR(error
)) {
1896 cmpxchg(&i915
->gpu_error
.first_error
, NULL
, error
);
1900 i915_error_state_store(error
);
1901 i915_gpu_coredump_put(error
);
1904 struct i915_gpu_coredump
*
1905 i915_first_error_state(struct drm_i915_private
*i915
)
1907 struct i915_gpu_coredump
*error
;
1909 spin_lock_irq(&i915
->gpu_error
.lock
);
1910 error
= i915
->gpu_error
.first_error
;
1911 if (!IS_ERR_OR_NULL(error
))
1912 i915_gpu_coredump_get(error
);
1913 spin_unlock_irq(&i915
->gpu_error
.lock
);
1918 void i915_reset_error_state(struct drm_i915_private
*i915
)
1920 struct i915_gpu_coredump
*error
;
1922 spin_lock_irq(&i915
->gpu_error
.lock
);
1923 error
= i915
->gpu_error
.first_error
;
1924 if (error
!= ERR_PTR(-ENODEV
)) /* if disabled, always disabled */
1925 i915
->gpu_error
.first_error
= NULL
;
1926 spin_unlock_irq(&i915
->gpu_error
.lock
);
1928 if (!IS_ERR_OR_NULL(error
))
1929 i915_gpu_coredump_put(error
);
1932 void i915_disable_error_state(struct drm_i915_private
*i915
, int err
)
1934 spin_lock_irq(&i915
->gpu_error
.lock
);
1935 if (!i915
->gpu_error
.first_error
)
1936 i915
->gpu_error
.first_error
= ERR_PTR(err
);
1937 spin_unlock_irq(&i915
->gpu_error
.lock
);