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Merge tag 'pm-5.1-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm
[thirdparty/linux.git] / drivers / gpu / drm / i915 / i915_gpu_error.c
1 /*
2 * Copyright (c) 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 * Mika Kuoppala <mika.kuoppala@intel.com>
27 *
28 */
29
30 #include <linux/ascii85.h>
31 #include <linux/nmi.h>
32 #include <linux/scatterlist.h>
33 #include <linux/stop_machine.h>
34 #include <linux/utsname.h>
35 #include <linux/zlib.h>
36
37 #include <drm/drm_print.h>
38
39 #include "i915_gpu_error.h"
40 #include "i915_drv.h"
41
42 static inline const struct intel_engine_cs *
43 engine_lookup(const struct drm_i915_private *i915, unsigned int id)
44 {
45 if (id >= I915_NUM_ENGINES)
46 return NULL;
47
48 return i915->engine[id];
49 }
50
51 static inline const char *
52 __engine_name(const struct intel_engine_cs *engine)
53 {
54 return engine ? engine->name : "";
55 }
56
57 static const char *
58 engine_name(const struct drm_i915_private *i915, unsigned int id)
59 {
60 return __engine_name(engine_lookup(i915, id));
61 }
62
63 static const char *tiling_flag(int tiling)
64 {
65 switch (tiling) {
66 default:
67 case I915_TILING_NONE: return "";
68 case I915_TILING_X: return " X";
69 case I915_TILING_Y: return " Y";
70 }
71 }
72
73 static const char *dirty_flag(int dirty)
74 {
75 return dirty ? " dirty" : "";
76 }
77
78 static const char *purgeable_flag(int purgeable)
79 {
80 return purgeable ? " purgeable" : "";
81 }
82
83 static void __sg_set_buf(struct scatterlist *sg,
84 void *addr, unsigned int len, loff_t it)
85 {
86 sg->page_link = (unsigned long)virt_to_page(addr);
87 sg->offset = offset_in_page(addr);
88 sg->length = len;
89 sg->dma_address = it;
90 }
91
92 static bool __i915_error_grow(struct drm_i915_error_state_buf *e, size_t len)
93 {
94 if (!len)
95 return false;
96
97 if (e->bytes + len + 1 <= e->size)
98 return true;
99
100 if (e->bytes) {
101 __sg_set_buf(e->cur++, e->buf, e->bytes, e->iter);
102 e->iter += e->bytes;
103 e->buf = NULL;
104 e->bytes = 0;
105 }
106
107 if (e->cur == e->end) {
108 struct scatterlist *sgl;
109
110 sgl = (typeof(sgl))__get_free_page(GFP_KERNEL);
111 if (!sgl) {
112 e->err = -ENOMEM;
113 return false;
114 }
115
116 if (e->cur) {
117 e->cur->offset = 0;
118 e->cur->length = 0;
119 e->cur->page_link =
120 (unsigned long)sgl | SG_CHAIN;
121 } else {
122 e->sgl = sgl;
123 }
124
125 e->cur = sgl;
126 e->end = sgl + SG_MAX_SINGLE_ALLOC - 1;
127 }
128
129 e->size = ALIGN(len + 1, SZ_64K);
130 e->buf = kmalloc(e->size, GFP_KERNEL | __GFP_NOWARN | __GFP_NORETRY);
131 if (!e->buf) {
132 e->size = PAGE_ALIGN(len + 1);
133 e->buf = kmalloc(e->size, GFP_KERNEL);
134 }
135 if (!e->buf) {
136 e->err = -ENOMEM;
137 return false;
138 }
139
140 return true;
141 }
142
143 __printf(2, 0)
144 static void i915_error_vprintf(struct drm_i915_error_state_buf *e,
145 const char *fmt, va_list args)
146 {
147 va_list ap;
148 int len;
149
150 if (e->err)
151 return;
152
153 va_copy(ap, args);
154 len = vsnprintf(NULL, 0, fmt, ap);
155 va_end(ap);
156 if (len <= 0) {
157 e->err = len;
158 return;
159 }
160
161 if (!__i915_error_grow(e, len))
162 return;
163
164 GEM_BUG_ON(e->bytes >= e->size);
165 len = vscnprintf(e->buf + e->bytes, e->size - e->bytes, fmt, args);
166 if (len < 0) {
167 e->err = len;
168 return;
169 }
170 e->bytes += len;
171 }
172
173 static void i915_error_puts(struct drm_i915_error_state_buf *e, const char *str)
174 {
175 unsigned len;
176
177 if (e->err || !str)
178 return;
179
180 len = strlen(str);
181 if (!__i915_error_grow(e, len))
182 return;
183
184 GEM_BUG_ON(e->bytes + len > e->size);
185 memcpy(e->buf + e->bytes, str, len);
186 e->bytes += len;
187 }
188
189 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
190 #define err_puts(e, s) i915_error_puts(e, s)
191
192 static void __i915_printfn_error(struct drm_printer *p, struct va_format *vaf)
193 {
194 i915_error_vprintf(p->arg, vaf->fmt, *vaf->va);
195 }
196
197 static inline struct drm_printer
198 i915_error_printer(struct drm_i915_error_state_buf *e)
199 {
200 struct drm_printer p = {
201 .printfn = __i915_printfn_error,
202 .arg = e,
203 };
204 return p;
205 }
206
207 #ifdef CONFIG_DRM_I915_COMPRESS_ERROR
208
209 struct compress {
210 struct z_stream_s zstream;
211 void *tmp;
212 };
213
214 static bool compress_init(struct compress *c)
215 {
216 struct z_stream_s *zstream = memset(&c->zstream, 0, sizeof(c->zstream));
217
218 zstream->workspace =
219 kmalloc(zlib_deflate_workspacesize(MAX_WBITS, MAX_MEM_LEVEL),
220 GFP_ATOMIC | __GFP_NOWARN);
221 if (!zstream->workspace)
222 return false;
223
224 if (zlib_deflateInit(zstream, Z_DEFAULT_COMPRESSION) != Z_OK) {
225 kfree(zstream->workspace);
226 return false;
227 }
228
229 c->tmp = NULL;
230 if (i915_has_memcpy_from_wc())
231 c->tmp = (void *)__get_free_page(GFP_ATOMIC | __GFP_NOWARN);
232
233 return true;
234 }
235
236 static void *compress_next_page(struct drm_i915_error_object *dst)
237 {
238 unsigned long page;
239
240 if (dst->page_count >= dst->num_pages)
241 return ERR_PTR(-ENOSPC);
242
243 page = __get_free_page(GFP_ATOMIC | __GFP_NOWARN);
244 if (!page)
245 return ERR_PTR(-ENOMEM);
246
247 return dst->pages[dst->page_count++] = (void *)page;
248 }
249
250 static int compress_page(struct compress *c,
251 void *src,
252 struct drm_i915_error_object *dst)
253 {
254 struct z_stream_s *zstream = &c->zstream;
255
256 zstream->next_in = src;
257 if (c->tmp && i915_memcpy_from_wc(c->tmp, src, PAGE_SIZE))
258 zstream->next_in = c->tmp;
259 zstream->avail_in = PAGE_SIZE;
260
261 do {
262 if (zstream->avail_out == 0) {
263 zstream->next_out = compress_next_page(dst);
264 if (IS_ERR(zstream->next_out))
265 return PTR_ERR(zstream->next_out);
266
267 zstream->avail_out = PAGE_SIZE;
268 }
269
270 if (zlib_deflate(zstream, Z_NO_FLUSH) != Z_OK)
271 return -EIO;
272
273 touch_nmi_watchdog();
274 } while (zstream->avail_in);
275
276 /* Fallback to uncompressed if we increase size? */
277 if (0 && zstream->total_out > zstream->total_in)
278 return -E2BIG;
279
280 return 0;
281 }
282
283 static int compress_flush(struct compress *c,
284 struct drm_i915_error_object *dst)
285 {
286 struct z_stream_s *zstream = &c->zstream;
287
288 do {
289 switch (zlib_deflate(zstream, Z_FINISH)) {
290 case Z_OK: /* more space requested */
291 zstream->next_out = compress_next_page(dst);
292 if (IS_ERR(zstream->next_out))
293 return PTR_ERR(zstream->next_out);
294
295 zstream->avail_out = PAGE_SIZE;
296 break;
297
298 case Z_STREAM_END:
299 goto end;
300
301 default: /* any error */
302 return -EIO;
303 }
304 } while (1);
305
306 end:
307 memset(zstream->next_out, 0, zstream->avail_out);
308 dst->unused = zstream->avail_out;
309 return 0;
310 }
311
312 static void compress_fini(struct compress *c,
313 struct drm_i915_error_object *dst)
314 {
315 struct z_stream_s *zstream = &c->zstream;
316
317 zlib_deflateEnd(zstream);
318 kfree(zstream->workspace);
319 if (c->tmp)
320 free_page((unsigned long)c->tmp);
321 }
322
323 static void err_compression_marker(struct drm_i915_error_state_buf *m)
324 {
325 err_puts(m, ":");
326 }
327
328 #else
329
330 struct compress {
331 };
332
333 static bool compress_init(struct compress *c)
334 {
335 return true;
336 }
337
338 static int compress_page(struct compress *c,
339 void *src,
340 struct drm_i915_error_object *dst)
341 {
342 unsigned long page;
343 void *ptr;
344
345 page = __get_free_page(GFP_ATOMIC | __GFP_NOWARN);
346 if (!page)
347 return -ENOMEM;
348
349 ptr = (void *)page;
350 if (!i915_memcpy_from_wc(ptr, src, PAGE_SIZE))
351 memcpy(ptr, src, PAGE_SIZE);
352 dst->pages[dst->page_count++] = ptr;
353
354 return 0;
355 }
356
357 static int compress_flush(struct compress *c,
358 struct drm_i915_error_object *dst)
359 {
360 return 0;
361 }
362
363 static void compress_fini(struct compress *c,
364 struct drm_i915_error_object *dst)
365 {
366 }
367
368 static void err_compression_marker(struct drm_i915_error_state_buf *m)
369 {
370 err_puts(m, "~");
371 }
372
373 #endif
374
375 static void print_error_buffers(struct drm_i915_error_state_buf *m,
376 const char *name,
377 struct drm_i915_error_buffer *err,
378 int count)
379 {
380 err_printf(m, "%s [%d]:\n", name, count);
381
382 while (count--) {
383 err_printf(m, " %08x_%08x %8u %02x %02x %02x",
384 upper_32_bits(err->gtt_offset),
385 lower_32_bits(err->gtt_offset),
386 err->size,
387 err->read_domains,
388 err->write_domain,
389 err->wseqno);
390 err_puts(m, tiling_flag(err->tiling));
391 err_puts(m, dirty_flag(err->dirty));
392 err_puts(m, purgeable_flag(err->purgeable));
393 err_puts(m, err->userptr ? " userptr" : "");
394 err_puts(m, err->engine != -1 ? " " : "");
395 err_puts(m, engine_name(m->i915, err->engine));
396 err_puts(m, i915_cache_level_str(m->i915, err->cache_level));
397
398 if (err->name)
399 err_printf(m, " (name: %d)", err->name);
400 if (err->fence_reg != I915_FENCE_REG_NONE)
401 err_printf(m, " (fence: %d)", err->fence_reg);
402
403 err_puts(m, "\n");
404 err++;
405 }
406 }
407
408 static void error_print_instdone(struct drm_i915_error_state_buf *m,
409 const struct drm_i915_error_engine *ee)
410 {
411 int slice;
412 int subslice;
413
414 err_printf(m, " INSTDONE: 0x%08x\n",
415 ee->instdone.instdone);
416
417 if (ee->engine_id != RCS || INTEL_GEN(m->i915) <= 3)
418 return;
419
420 err_printf(m, " SC_INSTDONE: 0x%08x\n",
421 ee->instdone.slice_common);
422
423 if (INTEL_GEN(m->i915) <= 6)
424 return;
425
426 for_each_instdone_slice_subslice(m->i915, slice, subslice)
427 err_printf(m, " SAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
428 slice, subslice,
429 ee->instdone.sampler[slice][subslice]);
430
431 for_each_instdone_slice_subslice(m->i915, slice, subslice)
432 err_printf(m, " ROW_INSTDONE[%d][%d]: 0x%08x\n",
433 slice, subslice,
434 ee->instdone.row[slice][subslice]);
435 }
436
437 static const char *bannable(const struct drm_i915_error_context *ctx)
438 {
439 return ctx->bannable ? "" : " (unbannable)";
440 }
441
442 static void error_print_request(struct drm_i915_error_state_buf *m,
443 const char *prefix,
444 const struct drm_i915_error_request *erq,
445 const unsigned long epoch)
446 {
447 if (!erq->seqno)
448 return;
449
450 err_printf(m, "%s pid %d, ban score %d, seqno %8x:%08x%s%s, prio %d, emitted %dms, start %08x, head %08x, tail %08x\n",
451 prefix, erq->pid, erq->ban_score,
452 erq->context, erq->seqno,
453 test_bit(DMA_FENCE_FLAG_SIGNALED_BIT,
454 &erq->flags) ? "!" : "",
455 test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT,
456 &erq->flags) ? "+" : "",
457 erq->sched_attr.priority,
458 jiffies_to_msecs(erq->jiffies - epoch),
459 erq->start, erq->head, erq->tail);
460 }
461
462 static void error_print_context(struct drm_i915_error_state_buf *m,
463 const char *header,
464 const struct drm_i915_error_context *ctx)
465 {
466 err_printf(m, "%s%s[%d] user_handle %d hw_id %d, prio %d, ban score %d%s guilty %d active %d\n",
467 header, ctx->comm, ctx->pid, ctx->handle, ctx->hw_id,
468 ctx->sched_attr.priority, ctx->ban_score, bannable(ctx),
469 ctx->guilty, ctx->active);
470 }
471
472 static void error_print_engine(struct drm_i915_error_state_buf *m,
473 const struct drm_i915_error_engine *ee,
474 const unsigned long epoch)
475 {
476 int n;
477
478 err_printf(m, "%s command stream:\n",
479 engine_name(m->i915, ee->engine_id));
480 err_printf(m, " IDLE?: %s\n", yesno(ee->idle));
481 err_printf(m, " START: 0x%08x\n", ee->start);
482 err_printf(m, " HEAD: 0x%08x [0x%08x]\n", ee->head, ee->rq_head);
483 err_printf(m, " TAIL: 0x%08x [0x%08x, 0x%08x]\n",
484 ee->tail, ee->rq_post, ee->rq_tail);
485 err_printf(m, " CTL: 0x%08x\n", ee->ctl);
486 err_printf(m, " MODE: 0x%08x\n", ee->mode);
487 err_printf(m, " HWS: 0x%08x\n", ee->hws);
488 err_printf(m, " ACTHD: 0x%08x %08x\n",
489 (u32)(ee->acthd>>32), (u32)ee->acthd);
490 err_printf(m, " IPEIR: 0x%08x\n", ee->ipeir);
491 err_printf(m, " IPEHR: 0x%08x\n", ee->ipehr);
492
493 error_print_instdone(m, ee);
494
495 if (ee->batchbuffer) {
496 u64 start = ee->batchbuffer->gtt_offset;
497 u64 end = start + ee->batchbuffer->gtt_size;
498
499 err_printf(m, " batch: [0x%08x_%08x, 0x%08x_%08x]\n",
500 upper_32_bits(start), lower_32_bits(start),
501 upper_32_bits(end), lower_32_bits(end));
502 }
503 if (INTEL_GEN(m->i915) >= 4) {
504 err_printf(m, " BBADDR: 0x%08x_%08x\n",
505 (u32)(ee->bbaddr>>32), (u32)ee->bbaddr);
506 err_printf(m, " BB_STATE: 0x%08x\n", ee->bbstate);
507 err_printf(m, " INSTPS: 0x%08x\n", ee->instps);
508 }
509 err_printf(m, " INSTPM: 0x%08x\n", ee->instpm);
510 err_printf(m, " FADDR: 0x%08x %08x\n", upper_32_bits(ee->faddr),
511 lower_32_bits(ee->faddr));
512 if (INTEL_GEN(m->i915) >= 6) {
513 err_printf(m, " RC PSMI: 0x%08x\n", ee->rc_psmi);
514 err_printf(m, " FAULT_REG: 0x%08x\n", ee->fault_reg);
515 err_printf(m, " SYNC_0: 0x%08x\n",
516 ee->semaphore_mboxes[0]);
517 err_printf(m, " SYNC_1: 0x%08x\n",
518 ee->semaphore_mboxes[1]);
519 if (HAS_VEBOX(m->i915))
520 err_printf(m, " SYNC_2: 0x%08x\n",
521 ee->semaphore_mboxes[2]);
522 }
523 if (HAS_PPGTT(m->i915)) {
524 err_printf(m, " GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode);
525
526 if (INTEL_GEN(m->i915) >= 8) {
527 int i;
528 for (i = 0; i < 4; i++)
529 err_printf(m, " PDP%d: 0x%016llx\n",
530 i, ee->vm_info.pdp[i]);
531 } else {
532 err_printf(m, " PP_DIR_BASE: 0x%08x\n",
533 ee->vm_info.pp_dir_base);
534 }
535 }
536 err_printf(m, " seqno: 0x%08x\n", ee->seqno);
537 err_printf(m, " last_seqno: 0x%08x\n", ee->last_seqno);
538 err_printf(m, " ring->head: 0x%08x\n", ee->cpu_ring_head);
539 err_printf(m, " ring->tail: 0x%08x\n", ee->cpu_ring_tail);
540 err_printf(m, " hangcheck timestamp: %dms (%lu%s)\n",
541 jiffies_to_msecs(ee->hangcheck_timestamp - epoch),
542 ee->hangcheck_timestamp,
543 ee->hangcheck_timestamp == epoch ? "; epoch" : "");
544 err_printf(m, " engine reset count: %u\n", ee->reset_count);
545
546 for (n = 0; n < ee->num_ports; n++) {
547 err_printf(m, " ELSP[%d]:", n);
548 error_print_request(m, " ", &ee->execlist[n], epoch);
549 }
550
551 error_print_context(m, " Active context: ", &ee->context);
552 }
553
554 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
555 {
556 va_list args;
557
558 va_start(args, f);
559 i915_error_vprintf(e, f, args);
560 va_end(args);
561 }
562
563 static void print_error_obj(struct drm_i915_error_state_buf *m,
564 struct intel_engine_cs *engine,
565 const char *name,
566 struct drm_i915_error_object *obj)
567 {
568 char out[ASCII85_BUFSZ];
569 int page;
570
571 if (!obj)
572 return;
573
574 if (name) {
575 err_printf(m, "%s --- %s = 0x%08x %08x\n",
576 engine ? engine->name : "global", name,
577 upper_32_bits(obj->gtt_offset),
578 lower_32_bits(obj->gtt_offset));
579 }
580
581 err_compression_marker(m);
582 for (page = 0; page < obj->page_count; page++) {
583 int i, len;
584
585 len = PAGE_SIZE;
586 if (page == obj->page_count - 1)
587 len -= obj->unused;
588 len = ascii85_encode_len(len);
589
590 for (i = 0; i < len; i++)
591 err_puts(m, ascii85_encode(obj->pages[page][i], out));
592 }
593 err_puts(m, "\n");
594 }
595
596 static void err_print_capabilities(struct drm_i915_error_state_buf *m,
597 const struct intel_device_info *info,
598 const struct intel_runtime_info *runtime,
599 const struct intel_driver_caps *caps)
600 {
601 struct drm_printer p = i915_error_printer(m);
602
603 intel_device_info_dump_flags(info, &p);
604 intel_driver_caps_print(caps, &p);
605 intel_device_info_dump_topology(&runtime->sseu, &p);
606 }
607
608 static void err_print_params(struct drm_i915_error_state_buf *m,
609 const struct i915_params *params)
610 {
611 struct drm_printer p = i915_error_printer(m);
612
613 i915_params_dump(params, &p);
614 }
615
616 static void err_print_pciid(struct drm_i915_error_state_buf *m,
617 struct drm_i915_private *i915)
618 {
619 struct pci_dev *pdev = i915->drm.pdev;
620
621 err_printf(m, "PCI ID: 0x%04x\n", pdev->device);
622 err_printf(m, "PCI Revision: 0x%02x\n", pdev->revision);
623 err_printf(m, "PCI Subsystem: %04x:%04x\n",
624 pdev->subsystem_vendor,
625 pdev->subsystem_device);
626 }
627
628 static void err_print_uc(struct drm_i915_error_state_buf *m,
629 const struct i915_error_uc *error_uc)
630 {
631 struct drm_printer p = i915_error_printer(m);
632 const struct i915_gpu_state *error =
633 container_of(error_uc, typeof(*error), uc);
634
635 if (!error->device_info.has_guc)
636 return;
637
638 intel_uc_fw_dump(&error_uc->guc_fw, &p);
639 intel_uc_fw_dump(&error_uc->huc_fw, &p);
640 print_error_obj(m, NULL, "GuC log buffer", error_uc->guc_log);
641 }
642
643 static void err_free_sgl(struct scatterlist *sgl)
644 {
645 while (sgl) {
646 struct scatterlist *sg;
647
648 for (sg = sgl; !sg_is_chain(sg); sg++) {
649 kfree(sg_virt(sg));
650 if (sg_is_last(sg))
651 break;
652 }
653
654 sg = sg_is_last(sg) ? NULL : sg_chain_ptr(sg);
655 free_page((unsigned long)sgl);
656 sgl = sg;
657 }
658 }
659
660 static void __err_print_to_sgl(struct drm_i915_error_state_buf *m,
661 struct i915_gpu_state *error)
662 {
663 struct drm_i915_error_object *obj;
664 struct timespec64 ts;
665 int i, j;
666
667 if (*error->error_msg)
668 err_printf(m, "%s\n", error->error_msg);
669 err_printf(m, "Kernel: %s %s\n",
670 init_utsname()->release,
671 init_utsname()->machine);
672 ts = ktime_to_timespec64(error->time);
673 err_printf(m, "Time: %lld s %ld us\n",
674 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC);
675 ts = ktime_to_timespec64(error->boottime);
676 err_printf(m, "Boottime: %lld s %ld us\n",
677 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC);
678 ts = ktime_to_timespec64(error->uptime);
679 err_printf(m, "Uptime: %lld s %ld us\n",
680 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC);
681 err_printf(m, "Epoch: %lu jiffies (%u HZ)\n", error->epoch, HZ);
682 err_printf(m, "Capture: %lu jiffies; %d ms ago, %d ms after epoch\n",
683 error->capture,
684 jiffies_to_msecs(jiffies - error->capture),
685 jiffies_to_msecs(error->capture - error->epoch));
686
687 for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
688 if (!error->engine[i].context.pid)
689 continue;
690
691 err_printf(m, "Active process (on ring %s): %s [%d], score %d%s\n",
692 engine_name(m->i915, i),
693 error->engine[i].context.comm,
694 error->engine[i].context.pid,
695 error->engine[i].context.ban_score,
696 bannable(&error->engine[i].context));
697 }
698 err_printf(m, "Reset count: %u\n", error->reset_count);
699 err_printf(m, "Suspend count: %u\n", error->suspend_count);
700 err_printf(m, "Platform: %s\n", intel_platform_name(error->device_info.platform));
701 err_print_pciid(m, m->i915);
702
703 err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
704
705 if (HAS_CSR(m->i915)) {
706 struct intel_csr *csr = &m->i915->csr;
707
708 err_printf(m, "DMC loaded: %s\n",
709 yesno(csr->dmc_payload != NULL));
710 err_printf(m, "DMC fw version: %d.%d\n",
711 CSR_VERSION_MAJOR(csr->version),
712 CSR_VERSION_MINOR(csr->version));
713 }
714
715 err_printf(m, "GT awake: %s\n", yesno(error->awake));
716 err_printf(m, "RPM wakelock: %s\n", yesno(error->wakelock));
717 err_printf(m, "PM suspended: %s\n", yesno(error->suspended));
718 err_printf(m, "EIR: 0x%08x\n", error->eir);
719 err_printf(m, "IER: 0x%08x\n", error->ier);
720 for (i = 0; i < error->ngtier; i++)
721 err_printf(m, "GTIER[%d]: 0x%08x\n", i, error->gtier[i]);
722 err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
723 err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake);
724 err_printf(m, "DERRMR: 0x%08x\n", error->derrmr);
725 err_printf(m, "CCID: 0x%08x\n", error->ccid);
726
727 for (i = 0; i < error->nfence; i++)
728 err_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]);
729
730 if (INTEL_GEN(m->i915) >= 6) {
731 err_printf(m, "ERROR: 0x%08x\n", error->error);
732
733 if (INTEL_GEN(m->i915) >= 8)
734 err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n",
735 error->fault_data1, error->fault_data0);
736
737 err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
738 }
739
740 if (IS_GEN(m->i915, 7))
741 err_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
742
743 for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
744 if (error->engine[i].engine_id != -1)
745 error_print_engine(m, &error->engine[i], error->epoch);
746 }
747
748 for (i = 0; i < ARRAY_SIZE(error->active_vm); i++) {
749 char buf[128];
750 int len, first = 1;
751
752 if (!error->active_vm[i])
753 break;
754
755 len = scnprintf(buf, sizeof(buf), "Active (");
756 for (j = 0; j < ARRAY_SIZE(error->engine); j++) {
757 if (error->engine[j].vm != error->active_vm[i])
758 continue;
759
760 len += scnprintf(buf + len, sizeof(buf), "%s%s",
761 first ? "" : ", ",
762 m->i915->engine[j]->name);
763 first = 0;
764 }
765 scnprintf(buf + len, sizeof(buf), ")");
766 print_error_buffers(m, buf,
767 error->active_bo[i],
768 error->active_bo_count[i]);
769 }
770
771 print_error_buffers(m, "Pinned (global)",
772 error->pinned_bo,
773 error->pinned_bo_count);
774
775 for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
776 const struct drm_i915_error_engine *ee = &error->engine[i];
777
778 obj = ee->batchbuffer;
779 if (obj) {
780 err_puts(m, m->i915->engine[i]->name);
781 if (ee->context.pid)
782 err_printf(m, " (submitted by %s [%d], ctx %d [%d], score %d%s)",
783 ee->context.comm,
784 ee->context.pid,
785 ee->context.handle,
786 ee->context.hw_id,
787 ee->context.ban_score,
788 bannable(&ee->context));
789 err_printf(m, " --- gtt_offset = 0x%08x %08x\n",
790 upper_32_bits(obj->gtt_offset),
791 lower_32_bits(obj->gtt_offset));
792 print_error_obj(m, m->i915->engine[i], NULL, obj);
793 }
794
795 for (j = 0; j < ee->user_bo_count; j++)
796 print_error_obj(m, m->i915->engine[i],
797 "user", ee->user_bo[j]);
798
799 if (ee->num_requests) {
800 err_printf(m, "%s --- %d requests\n",
801 m->i915->engine[i]->name,
802 ee->num_requests);
803 for (j = 0; j < ee->num_requests; j++)
804 error_print_request(m, " ",
805 &ee->requests[j],
806 error->epoch);
807 }
808
809 print_error_obj(m, m->i915->engine[i],
810 "ringbuffer", ee->ringbuffer);
811
812 print_error_obj(m, m->i915->engine[i],
813 "HW Status", ee->hws_page);
814
815 print_error_obj(m, m->i915->engine[i],
816 "HW context", ee->ctx);
817
818 print_error_obj(m, m->i915->engine[i],
819 "WA context", ee->wa_ctx);
820
821 print_error_obj(m, m->i915->engine[i],
822 "WA batchbuffer", ee->wa_batchbuffer);
823
824 print_error_obj(m, m->i915->engine[i],
825 "NULL context", ee->default_state);
826 }
827
828 if (error->overlay)
829 intel_overlay_print_error_state(m, error->overlay);
830
831 if (error->display)
832 intel_display_print_error_state(m, error->display);
833
834 err_print_capabilities(m, &error->device_info, &error->runtime_info,
835 &error->driver_caps);
836 err_print_params(m, &error->params);
837 err_print_uc(m, &error->uc);
838 }
839
840 static int err_print_to_sgl(struct i915_gpu_state *error)
841 {
842 struct drm_i915_error_state_buf m;
843
844 if (IS_ERR(error))
845 return PTR_ERR(error);
846
847 if (READ_ONCE(error->sgl))
848 return 0;
849
850 memset(&m, 0, sizeof(m));
851 m.i915 = error->i915;
852
853 __err_print_to_sgl(&m, error);
854
855 if (m.buf) {
856 __sg_set_buf(m.cur++, m.buf, m.bytes, m.iter);
857 m.bytes = 0;
858 m.buf = NULL;
859 }
860 if (m.cur) {
861 GEM_BUG_ON(m.end < m.cur);
862 sg_mark_end(m.cur - 1);
863 }
864 GEM_BUG_ON(m.sgl && !m.cur);
865
866 if (m.err) {
867 err_free_sgl(m.sgl);
868 return m.err;
869 }
870
871 if (cmpxchg(&error->sgl, NULL, m.sgl))
872 err_free_sgl(m.sgl);
873
874 return 0;
875 }
876
877 ssize_t i915_gpu_state_copy_to_buffer(struct i915_gpu_state *error,
878 char *buf, loff_t off, size_t rem)
879 {
880 struct scatterlist *sg;
881 size_t count;
882 loff_t pos;
883 int err;
884
885 if (!error || !rem)
886 return 0;
887
888 err = err_print_to_sgl(error);
889 if (err)
890 return err;
891
892 sg = READ_ONCE(error->fit);
893 if (!sg || off < sg->dma_address)
894 sg = error->sgl;
895 if (!sg)
896 return 0;
897
898 pos = sg->dma_address;
899 count = 0;
900 do {
901 size_t len, start;
902
903 if (sg_is_chain(sg)) {
904 sg = sg_chain_ptr(sg);
905 GEM_BUG_ON(sg_is_chain(sg));
906 }
907
908 len = sg->length;
909 if (pos + len <= off) {
910 pos += len;
911 continue;
912 }
913
914 start = sg->offset;
915 if (pos < off) {
916 GEM_BUG_ON(off - pos > len);
917 len -= off - pos;
918 start += off - pos;
919 pos = off;
920 }
921
922 len = min(len, rem);
923 GEM_BUG_ON(!len || len > sg->length);
924
925 memcpy(buf, page_address(sg_page(sg)) + start, len);
926
927 count += len;
928 pos += len;
929
930 buf += len;
931 rem -= len;
932 if (!rem) {
933 WRITE_ONCE(error->fit, sg);
934 break;
935 }
936 } while (!sg_is_last(sg++));
937
938 return count;
939 }
940
941 static void i915_error_object_free(struct drm_i915_error_object *obj)
942 {
943 int page;
944
945 if (obj == NULL)
946 return;
947
948 for (page = 0; page < obj->page_count; page++)
949 free_page((unsigned long)obj->pages[page]);
950
951 kfree(obj);
952 }
953
954
955 static void cleanup_params(struct i915_gpu_state *error)
956 {
957 i915_params_free(&error->params);
958 }
959
960 static void cleanup_uc_state(struct i915_gpu_state *error)
961 {
962 struct i915_error_uc *error_uc = &error->uc;
963
964 kfree(error_uc->guc_fw.path);
965 kfree(error_uc->huc_fw.path);
966 i915_error_object_free(error_uc->guc_log);
967 }
968
969 void __i915_gpu_state_free(struct kref *error_ref)
970 {
971 struct i915_gpu_state *error =
972 container_of(error_ref, typeof(*error), ref);
973 long i, j;
974
975 for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
976 struct drm_i915_error_engine *ee = &error->engine[i];
977
978 for (j = 0; j < ee->user_bo_count; j++)
979 i915_error_object_free(ee->user_bo[j]);
980 kfree(ee->user_bo);
981
982 i915_error_object_free(ee->batchbuffer);
983 i915_error_object_free(ee->wa_batchbuffer);
984 i915_error_object_free(ee->ringbuffer);
985 i915_error_object_free(ee->hws_page);
986 i915_error_object_free(ee->ctx);
987 i915_error_object_free(ee->wa_ctx);
988
989 kfree(ee->requests);
990 }
991
992 for (i = 0; i < ARRAY_SIZE(error->active_bo); i++)
993 kfree(error->active_bo[i]);
994 kfree(error->pinned_bo);
995
996 kfree(error->overlay);
997 kfree(error->display);
998
999 cleanup_params(error);
1000 cleanup_uc_state(error);
1001
1002 err_free_sgl(error->sgl);
1003 kfree(error);
1004 }
1005
1006 static struct drm_i915_error_object *
1007 i915_error_object_create(struct drm_i915_private *i915,
1008 struct i915_vma *vma)
1009 {
1010 struct i915_ggtt *ggtt = &i915->ggtt;
1011 const u64 slot = ggtt->error_capture.start;
1012 struct drm_i915_error_object *dst;
1013 struct compress compress;
1014 unsigned long num_pages;
1015 struct sgt_iter iter;
1016 dma_addr_t dma;
1017 int ret;
1018
1019 if (!vma || !vma->pages)
1020 return NULL;
1021
1022 num_pages = min_t(u64, vma->size, vma->obj->base.size) >> PAGE_SHIFT;
1023 num_pages = DIV_ROUND_UP(10 * num_pages, 8); /* worstcase zlib growth */
1024 dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *),
1025 GFP_ATOMIC | __GFP_NOWARN);
1026 if (!dst)
1027 return NULL;
1028
1029 dst->gtt_offset = vma->node.start;
1030 dst->gtt_size = vma->node.size;
1031 dst->num_pages = num_pages;
1032 dst->page_count = 0;
1033 dst->unused = 0;
1034
1035 if (!compress_init(&compress)) {
1036 kfree(dst);
1037 return NULL;
1038 }
1039
1040 ret = -EINVAL;
1041 for_each_sgt_dma(dma, iter, vma->pages) {
1042 void __iomem *s;
1043
1044 ggtt->vm.insert_page(&ggtt->vm, dma, slot, I915_CACHE_NONE, 0);
1045
1046 s = io_mapping_map_atomic_wc(&ggtt->iomap, slot);
1047 ret = compress_page(&compress, (void __force *)s, dst);
1048 io_mapping_unmap_atomic(s);
1049 if (ret)
1050 break;
1051 }
1052
1053 if (ret || compress_flush(&compress, dst)) {
1054 while (dst->page_count--)
1055 free_page((unsigned long)dst->pages[dst->page_count]);
1056 kfree(dst);
1057 dst = NULL;
1058 }
1059
1060 compress_fini(&compress, dst);
1061 return dst;
1062 }
1063
1064 /* The error capture is special as tries to run underneath the normal
1065 * locking rules - so we use the raw version of the i915_active_request lookup.
1066 */
1067 static inline u32
1068 __active_get_seqno(struct i915_active_request *active)
1069 {
1070 struct i915_request *request;
1071
1072 request = __i915_active_request_peek(active);
1073 return request ? request->global_seqno : 0;
1074 }
1075
1076 static inline int
1077 __active_get_engine_id(struct i915_active_request *active)
1078 {
1079 struct i915_request *request;
1080
1081 request = __i915_active_request_peek(active);
1082 return request ? request->engine->id : -1;
1083 }
1084
1085 static void capture_bo(struct drm_i915_error_buffer *err,
1086 struct i915_vma *vma)
1087 {
1088 struct drm_i915_gem_object *obj = vma->obj;
1089
1090 err->size = obj->base.size;
1091 err->name = obj->base.name;
1092
1093 err->wseqno = __active_get_seqno(&obj->frontbuffer_write);
1094 err->engine = __active_get_engine_id(&obj->frontbuffer_write);
1095
1096 err->gtt_offset = vma->node.start;
1097 err->read_domains = obj->read_domains;
1098 err->write_domain = obj->write_domain;
1099 err->fence_reg = vma->fence ? vma->fence->id : -1;
1100 err->tiling = i915_gem_object_get_tiling(obj);
1101 err->dirty = obj->mm.dirty;
1102 err->purgeable = obj->mm.madv != I915_MADV_WILLNEED;
1103 err->userptr = obj->userptr.mm != NULL;
1104 err->cache_level = obj->cache_level;
1105 }
1106
1107 static u32 capture_error_bo(struct drm_i915_error_buffer *err,
1108 int count, struct list_head *head,
1109 unsigned int flags)
1110 #define ACTIVE_ONLY BIT(0)
1111 #define PINNED_ONLY BIT(1)
1112 {
1113 struct i915_vma *vma;
1114 int i = 0;
1115
1116 list_for_each_entry(vma, head, vm_link) {
1117 if (!vma->obj)
1118 continue;
1119
1120 if (flags & ACTIVE_ONLY && !i915_vma_is_active(vma))
1121 continue;
1122
1123 if (flags & PINNED_ONLY && !i915_vma_is_pinned(vma))
1124 continue;
1125
1126 capture_bo(err++, vma);
1127 if (++i == count)
1128 break;
1129 }
1130
1131 return i;
1132 }
1133
1134 /*
1135 * Generate a semi-unique error code. The code is not meant to have meaning, The
1136 * code's only purpose is to try to prevent false duplicated bug reports by
1137 * grossly estimating a GPU error state.
1138 *
1139 * TODO Ideally, hashing the batchbuffer would be a very nice way to determine
1140 * the hang if we could strip the GTT offset information from it.
1141 *
1142 * It's only a small step better than a random number in its current form.
1143 */
1144 static u32 i915_error_generate_code(struct i915_gpu_state *error,
1145 unsigned long engine_mask)
1146 {
1147 /*
1148 * IPEHR would be an ideal way to detect errors, as it's the gross
1149 * measure of "the command that hung." However, has some very common
1150 * synchronization commands which almost always appear in the case
1151 * strictly a client bug. Use instdone to differentiate those some.
1152 */
1153 if (engine_mask) {
1154 struct drm_i915_error_engine *ee =
1155 &error->engine[ffs(engine_mask)];
1156
1157 return ee->ipehr ^ ee->instdone.instdone;
1158 }
1159
1160 return 0;
1161 }
1162
1163 static void gem_record_fences(struct i915_gpu_state *error)
1164 {
1165 struct drm_i915_private *dev_priv = error->i915;
1166 int i;
1167
1168 if (INTEL_GEN(dev_priv) >= 6) {
1169 for (i = 0; i < dev_priv->num_fence_regs; i++)
1170 error->fence[i] = I915_READ64(FENCE_REG_GEN6_LO(i));
1171 } else if (INTEL_GEN(dev_priv) >= 4) {
1172 for (i = 0; i < dev_priv->num_fence_regs; i++)
1173 error->fence[i] = I915_READ64(FENCE_REG_965_LO(i));
1174 } else {
1175 for (i = 0; i < dev_priv->num_fence_regs; i++)
1176 error->fence[i] = I915_READ(FENCE_REG(i));
1177 }
1178 error->nfence = i;
1179 }
1180
1181 static void gen6_record_semaphore_state(struct intel_engine_cs *engine,
1182 struct drm_i915_error_engine *ee)
1183 {
1184 struct drm_i915_private *dev_priv = engine->i915;
1185
1186 ee->semaphore_mboxes[0] = I915_READ(RING_SYNC_0(engine->mmio_base));
1187 ee->semaphore_mboxes[1] = I915_READ(RING_SYNC_1(engine->mmio_base));
1188 if (HAS_VEBOX(dev_priv))
1189 ee->semaphore_mboxes[2] =
1190 I915_READ(RING_SYNC_2(engine->mmio_base));
1191 }
1192
1193 static void error_record_engine_registers(struct i915_gpu_state *error,
1194 struct intel_engine_cs *engine,
1195 struct drm_i915_error_engine *ee)
1196 {
1197 struct drm_i915_private *dev_priv = engine->i915;
1198
1199 if (INTEL_GEN(dev_priv) >= 6) {
1200 ee->rc_psmi = I915_READ(RING_PSMI_CTL(engine->mmio_base));
1201 if (INTEL_GEN(dev_priv) >= 8) {
1202 ee->fault_reg = I915_READ(GEN8_RING_FAULT_REG);
1203 } else {
1204 gen6_record_semaphore_state(engine, ee);
1205 ee->fault_reg = I915_READ(RING_FAULT_REG(engine));
1206 }
1207 }
1208
1209 if (INTEL_GEN(dev_priv) >= 4) {
1210 ee->faddr = I915_READ(RING_DMA_FADD(engine->mmio_base));
1211 ee->ipeir = I915_READ(RING_IPEIR(engine->mmio_base));
1212 ee->ipehr = I915_READ(RING_IPEHR(engine->mmio_base));
1213 ee->instps = I915_READ(RING_INSTPS(engine->mmio_base));
1214 ee->bbaddr = I915_READ(RING_BBADDR(engine->mmio_base));
1215 if (INTEL_GEN(dev_priv) >= 8) {
1216 ee->faddr |= (u64) I915_READ(RING_DMA_FADD_UDW(engine->mmio_base)) << 32;
1217 ee->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(engine->mmio_base)) << 32;
1218 }
1219 ee->bbstate = I915_READ(RING_BBSTATE(engine->mmio_base));
1220 } else {
1221 ee->faddr = I915_READ(DMA_FADD_I8XX);
1222 ee->ipeir = I915_READ(IPEIR);
1223 ee->ipehr = I915_READ(IPEHR);
1224 }
1225
1226 intel_engine_get_instdone(engine, &ee->instdone);
1227
1228 ee->instpm = I915_READ(RING_INSTPM(engine->mmio_base));
1229 ee->acthd = intel_engine_get_active_head(engine);
1230 ee->seqno = intel_engine_get_seqno(engine);
1231 ee->last_seqno = intel_engine_last_submit(engine);
1232 ee->start = I915_READ_START(engine);
1233 ee->head = I915_READ_HEAD(engine);
1234 ee->tail = I915_READ_TAIL(engine);
1235 ee->ctl = I915_READ_CTL(engine);
1236 if (INTEL_GEN(dev_priv) > 2)
1237 ee->mode = I915_READ_MODE(engine);
1238
1239 if (!HWS_NEEDS_PHYSICAL(dev_priv)) {
1240 i915_reg_t mmio;
1241
1242 if (IS_GEN(dev_priv, 7)) {
1243 switch (engine->id) {
1244 default:
1245 case RCS:
1246 mmio = RENDER_HWS_PGA_GEN7;
1247 break;
1248 case BCS:
1249 mmio = BLT_HWS_PGA_GEN7;
1250 break;
1251 case VCS:
1252 mmio = BSD_HWS_PGA_GEN7;
1253 break;
1254 case VECS:
1255 mmio = VEBOX_HWS_PGA_GEN7;
1256 break;
1257 }
1258 } else if (IS_GEN(engine->i915, 6)) {
1259 mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
1260 } else {
1261 /* XXX: gen8 returns to sanity */
1262 mmio = RING_HWS_PGA(engine->mmio_base);
1263 }
1264
1265 ee->hws = I915_READ(mmio);
1266 }
1267
1268 ee->idle = intel_engine_is_idle(engine);
1269 if (!ee->idle)
1270 ee->hangcheck_timestamp = engine->hangcheck.action_timestamp;
1271 ee->reset_count = i915_reset_engine_count(&dev_priv->gpu_error,
1272 engine);
1273
1274 if (HAS_PPGTT(dev_priv)) {
1275 int i;
1276
1277 ee->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(engine));
1278
1279 if (IS_GEN(dev_priv, 6))
1280 ee->vm_info.pp_dir_base =
1281 I915_READ(RING_PP_DIR_BASE_READ(engine));
1282 else if (IS_GEN(dev_priv, 7))
1283 ee->vm_info.pp_dir_base =
1284 I915_READ(RING_PP_DIR_BASE(engine));
1285 else if (INTEL_GEN(dev_priv) >= 8)
1286 for (i = 0; i < 4; i++) {
1287 ee->vm_info.pdp[i] =
1288 I915_READ(GEN8_RING_PDP_UDW(engine, i));
1289 ee->vm_info.pdp[i] <<= 32;
1290 ee->vm_info.pdp[i] |=
1291 I915_READ(GEN8_RING_PDP_LDW(engine, i));
1292 }
1293 }
1294 }
1295
1296 static void record_request(struct i915_request *request,
1297 struct drm_i915_error_request *erq)
1298 {
1299 struct i915_gem_context *ctx = request->gem_context;
1300
1301 erq->flags = request->fence.flags;
1302 erq->context = ctx->hw_id;
1303 erq->sched_attr = request->sched.attr;
1304 erq->ban_score = atomic_read(&ctx->ban_score);
1305 erq->seqno = request->global_seqno;
1306 erq->jiffies = request->emitted_jiffies;
1307 erq->start = i915_ggtt_offset(request->ring->vma);
1308 erq->head = request->head;
1309 erq->tail = request->tail;
1310
1311 rcu_read_lock();
1312 erq->pid = ctx->pid ? pid_nr(ctx->pid) : 0;
1313 rcu_read_unlock();
1314 }
1315
1316 static void engine_record_requests(struct intel_engine_cs *engine,
1317 struct i915_request *first,
1318 struct drm_i915_error_engine *ee)
1319 {
1320 struct i915_request *request;
1321 int count;
1322
1323 count = 0;
1324 request = first;
1325 list_for_each_entry_from(request, &engine->timeline.requests, link)
1326 count++;
1327 if (!count)
1328 return;
1329
1330 ee->requests = kcalloc(count, sizeof(*ee->requests), GFP_ATOMIC);
1331 if (!ee->requests)
1332 return;
1333
1334 ee->num_requests = count;
1335
1336 count = 0;
1337 request = first;
1338 list_for_each_entry_from(request, &engine->timeline.requests, link) {
1339 if (count >= ee->num_requests) {
1340 /*
1341 * If the ring request list was changed in
1342 * between the point where the error request
1343 * list was created and dimensioned and this
1344 * point then just exit early to avoid crashes.
1345 *
1346 * We don't need to communicate that the
1347 * request list changed state during error
1348 * state capture and that the error state is
1349 * slightly incorrect as a consequence since we
1350 * are typically only interested in the request
1351 * list state at the point of error state
1352 * capture, not in any changes happening during
1353 * the capture.
1354 */
1355 break;
1356 }
1357
1358 record_request(request, &ee->requests[count++]);
1359 }
1360 ee->num_requests = count;
1361 }
1362
1363 static void error_record_engine_execlists(struct intel_engine_cs *engine,
1364 struct drm_i915_error_engine *ee)
1365 {
1366 const struct intel_engine_execlists * const execlists = &engine->execlists;
1367 unsigned int n;
1368
1369 for (n = 0; n < execlists_num_ports(execlists); n++) {
1370 struct i915_request *rq = port_request(&execlists->port[n]);
1371
1372 if (!rq)
1373 break;
1374
1375 record_request(rq, &ee->execlist[n]);
1376 }
1377
1378 ee->num_ports = n;
1379 }
1380
1381 static void record_context(struct drm_i915_error_context *e,
1382 struct i915_gem_context *ctx)
1383 {
1384 if (ctx->pid) {
1385 struct task_struct *task;
1386
1387 rcu_read_lock();
1388 task = pid_task(ctx->pid, PIDTYPE_PID);
1389 if (task) {
1390 strcpy(e->comm, task->comm);
1391 e->pid = task->pid;
1392 }
1393 rcu_read_unlock();
1394 }
1395
1396 e->handle = ctx->user_handle;
1397 e->hw_id = ctx->hw_id;
1398 e->sched_attr = ctx->sched;
1399 e->ban_score = atomic_read(&ctx->ban_score);
1400 e->bannable = i915_gem_context_is_bannable(ctx);
1401 e->guilty = atomic_read(&ctx->guilty_count);
1402 e->active = atomic_read(&ctx->active_count);
1403 }
1404
1405 static void request_record_user_bo(struct i915_request *request,
1406 struct drm_i915_error_engine *ee)
1407 {
1408 struct i915_capture_list *c;
1409 struct drm_i915_error_object **bo;
1410 long count, max;
1411
1412 max = 0;
1413 for (c = request->capture_list; c; c = c->next)
1414 max++;
1415 if (!max)
1416 return;
1417
1418 bo = kmalloc_array(max, sizeof(*bo), GFP_ATOMIC);
1419 if (!bo) {
1420 /* If we can't capture everything, try to capture something. */
1421 max = min_t(long, max, PAGE_SIZE / sizeof(*bo));
1422 bo = kmalloc_array(max, sizeof(*bo), GFP_ATOMIC);
1423 }
1424 if (!bo)
1425 return;
1426
1427 count = 0;
1428 for (c = request->capture_list; c; c = c->next) {
1429 bo[count] = i915_error_object_create(request->i915, c->vma);
1430 if (!bo[count])
1431 break;
1432 if (++count == max)
1433 break;
1434 }
1435
1436 ee->user_bo = bo;
1437 ee->user_bo_count = count;
1438 }
1439
1440 static struct drm_i915_error_object *
1441 capture_object(struct drm_i915_private *dev_priv,
1442 struct drm_i915_gem_object *obj)
1443 {
1444 if (obj && i915_gem_object_has_pages(obj)) {
1445 struct i915_vma fake = {
1446 .node = { .start = U64_MAX, .size = obj->base.size },
1447 .size = obj->base.size,
1448 .pages = obj->mm.pages,
1449 .obj = obj,
1450 };
1451
1452 return i915_error_object_create(dev_priv, &fake);
1453 } else {
1454 return NULL;
1455 }
1456 }
1457
1458 static void gem_record_rings(struct i915_gpu_state *error)
1459 {
1460 struct drm_i915_private *i915 = error->i915;
1461 struct i915_ggtt *ggtt = &i915->ggtt;
1462 int i;
1463
1464 for (i = 0; i < I915_NUM_ENGINES; i++) {
1465 struct intel_engine_cs *engine = i915->engine[i];
1466 struct drm_i915_error_engine *ee = &error->engine[i];
1467 struct i915_request *request;
1468
1469 ee->engine_id = -1;
1470
1471 if (!engine)
1472 continue;
1473
1474 ee->engine_id = i;
1475
1476 error_record_engine_registers(error, engine, ee);
1477 error_record_engine_execlists(engine, ee);
1478
1479 request = i915_gem_find_active_request(engine);
1480 if (request) {
1481 struct i915_gem_context *ctx = request->gem_context;
1482 struct intel_ring *ring;
1483
1484 ee->vm = ctx->ppgtt ? &ctx->ppgtt->vm : &ggtt->vm;
1485
1486 record_context(&ee->context, ctx);
1487
1488 /* We need to copy these to an anonymous buffer
1489 * as the simplest method to avoid being overwritten
1490 * by userspace.
1491 */
1492 ee->batchbuffer =
1493 i915_error_object_create(i915, request->batch);
1494
1495 if (HAS_BROKEN_CS_TLB(i915))
1496 ee->wa_batchbuffer =
1497 i915_error_object_create(i915,
1498 i915->gt.scratch);
1499 request_record_user_bo(request, ee);
1500
1501 ee->ctx =
1502 i915_error_object_create(i915,
1503 request->hw_context->state);
1504
1505 error->simulated |=
1506 i915_gem_context_no_error_capture(ctx);
1507
1508 ee->rq_head = request->head;
1509 ee->rq_post = request->postfix;
1510 ee->rq_tail = request->tail;
1511
1512 ring = request->ring;
1513 ee->cpu_ring_head = ring->head;
1514 ee->cpu_ring_tail = ring->tail;
1515 ee->ringbuffer =
1516 i915_error_object_create(i915, ring->vma);
1517
1518 engine_record_requests(engine, request, ee);
1519 }
1520
1521 ee->hws_page =
1522 i915_error_object_create(i915,
1523 engine->status_page.vma);
1524
1525 ee->wa_ctx = i915_error_object_create(i915, engine->wa_ctx.vma);
1526
1527 ee->default_state = capture_object(i915, engine->default_state);
1528 }
1529 }
1530
1531 static void gem_capture_vm(struct i915_gpu_state *error,
1532 struct i915_address_space *vm,
1533 int idx)
1534 {
1535 struct drm_i915_error_buffer *active_bo;
1536 struct i915_vma *vma;
1537 int count;
1538
1539 count = 0;
1540 list_for_each_entry(vma, &vm->bound_list, vm_link)
1541 if (i915_vma_is_active(vma))
1542 count++;
1543
1544 active_bo = NULL;
1545 if (count)
1546 active_bo = kcalloc(count, sizeof(*active_bo), GFP_ATOMIC);
1547 if (active_bo)
1548 count = capture_error_bo(active_bo,
1549 count, &vm->bound_list,
1550 ACTIVE_ONLY);
1551 else
1552 count = 0;
1553
1554 error->active_vm[idx] = vm;
1555 error->active_bo[idx] = active_bo;
1556 error->active_bo_count[idx] = count;
1557 }
1558
1559 static void capture_active_buffers(struct i915_gpu_state *error)
1560 {
1561 int cnt = 0, i, j;
1562
1563 BUILD_BUG_ON(ARRAY_SIZE(error->engine) > ARRAY_SIZE(error->active_bo));
1564 BUILD_BUG_ON(ARRAY_SIZE(error->active_bo) != ARRAY_SIZE(error->active_vm));
1565 BUILD_BUG_ON(ARRAY_SIZE(error->active_bo) != ARRAY_SIZE(error->active_bo_count));
1566
1567 /* Scan each engine looking for unique active contexts/vm */
1568 for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
1569 struct drm_i915_error_engine *ee = &error->engine[i];
1570 bool found;
1571
1572 if (!ee->vm)
1573 continue;
1574
1575 found = false;
1576 for (j = 0; j < i && !found; j++)
1577 found = error->engine[j].vm == ee->vm;
1578 if (!found)
1579 gem_capture_vm(error, ee->vm, cnt++);
1580 }
1581 }
1582
1583 static void capture_pinned_buffers(struct i915_gpu_state *error)
1584 {
1585 struct i915_address_space *vm = &error->i915->ggtt.vm;
1586 struct drm_i915_error_buffer *bo;
1587 struct i915_vma *vma;
1588 int count;
1589
1590 count = 0;
1591 list_for_each_entry(vma, &vm->bound_list, vm_link)
1592 count++;
1593
1594 bo = NULL;
1595 if (count)
1596 bo = kcalloc(count, sizeof(*bo), GFP_ATOMIC);
1597 if (!bo)
1598 return;
1599
1600 error->pinned_bo_count =
1601 capture_error_bo(bo, count, &vm->bound_list, PINNED_ONLY);
1602 error->pinned_bo = bo;
1603 }
1604
1605 static void capture_uc_state(struct i915_gpu_state *error)
1606 {
1607 struct drm_i915_private *i915 = error->i915;
1608 struct i915_error_uc *error_uc = &error->uc;
1609
1610 /* Capturing uC state won't be useful if there is no GuC */
1611 if (!error->device_info.has_guc)
1612 return;
1613
1614 error_uc->guc_fw = i915->guc.fw;
1615 error_uc->huc_fw = i915->huc.fw;
1616
1617 /* Non-default firmware paths will be specified by the modparam.
1618 * As modparams are generally accesible from the userspace make
1619 * explicit copies of the firmware paths.
1620 */
1621 error_uc->guc_fw.path = kstrdup(i915->guc.fw.path, GFP_ATOMIC);
1622 error_uc->huc_fw.path = kstrdup(i915->huc.fw.path, GFP_ATOMIC);
1623 error_uc->guc_log = i915_error_object_create(i915, i915->guc.log.vma);
1624 }
1625
1626 /* Capture all registers which don't fit into another category. */
1627 static void capture_reg_state(struct i915_gpu_state *error)
1628 {
1629 struct drm_i915_private *dev_priv = error->i915;
1630 int i;
1631
1632 /* General organization
1633 * 1. Registers specific to a single generation
1634 * 2. Registers which belong to multiple generations
1635 * 3. Feature specific registers.
1636 * 4. Everything else
1637 * Please try to follow the order.
1638 */
1639
1640 /* 1: Registers specific to a single generation */
1641 if (IS_VALLEYVIEW(dev_priv)) {
1642 error->gtier[0] = I915_READ(GTIER);
1643 error->ier = I915_READ(VLV_IER);
1644 error->forcewake = I915_READ_FW(FORCEWAKE_VLV);
1645 }
1646
1647 if (IS_GEN(dev_priv, 7))
1648 error->err_int = I915_READ(GEN7_ERR_INT);
1649
1650 if (INTEL_GEN(dev_priv) >= 8) {
1651 error->fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0);
1652 error->fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1);
1653 }
1654
1655 if (IS_GEN(dev_priv, 6)) {
1656 error->forcewake = I915_READ_FW(FORCEWAKE);
1657 error->gab_ctl = I915_READ(GAB_CTL);
1658 error->gfx_mode = I915_READ(GFX_MODE);
1659 }
1660
1661 /* 2: Registers which belong to multiple generations */
1662 if (INTEL_GEN(dev_priv) >= 7)
1663 error->forcewake = I915_READ_FW(FORCEWAKE_MT);
1664
1665 if (INTEL_GEN(dev_priv) >= 6) {
1666 error->derrmr = I915_READ(DERRMR);
1667 error->error = I915_READ(ERROR_GEN6);
1668 error->done_reg = I915_READ(DONE_REG);
1669 }
1670
1671 if (INTEL_GEN(dev_priv) >= 5)
1672 error->ccid = I915_READ(CCID);
1673
1674 /* 3: Feature specific registers */
1675 if (IS_GEN_RANGE(dev_priv, 6, 7)) {
1676 error->gam_ecochk = I915_READ(GAM_ECOCHK);
1677 error->gac_eco = I915_READ(GAC_ECO_BITS);
1678 }
1679
1680 /* 4: Everything else */
1681 if (INTEL_GEN(dev_priv) >= 11) {
1682 error->ier = I915_READ(GEN8_DE_MISC_IER);
1683 error->gtier[0] = I915_READ(GEN11_RENDER_COPY_INTR_ENABLE);
1684 error->gtier[1] = I915_READ(GEN11_VCS_VECS_INTR_ENABLE);
1685 error->gtier[2] = I915_READ(GEN11_GUC_SG_INTR_ENABLE);
1686 error->gtier[3] = I915_READ(GEN11_GPM_WGBOXPERF_INTR_ENABLE);
1687 error->gtier[4] = I915_READ(GEN11_CRYPTO_RSVD_INTR_ENABLE);
1688 error->gtier[5] = I915_READ(GEN11_GUNIT_CSME_INTR_ENABLE);
1689 error->ngtier = 6;
1690 } else if (INTEL_GEN(dev_priv) >= 8) {
1691 error->ier = I915_READ(GEN8_DE_MISC_IER);
1692 for (i = 0; i < 4; i++)
1693 error->gtier[i] = I915_READ(GEN8_GT_IER(i));
1694 error->ngtier = 4;
1695 } else if (HAS_PCH_SPLIT(dev_priv)) {
1696 error->ier = I915_READ(DEIER);
1697 error->gtier[0] = I915_READ(GTIER);
1698 error->ngtier = 1;
1699 } else if (IS_GEN(dev_priv, 2)) {
1700 error->ier = I915_READ16(IER);
1701 } else if (!IS_VALLEYVIEW(dev_priv)) {
1702 error->ier = I915_READ(IER);
1703 }
1704 error->eir = I915_READ(EIR);
1705 error->pgtbl_er = I915_READ(PGTBL_ER);
1706 }
1707
1708 static const char *
1709 error_msg(struct i915_gpu_state *error, unsigned long engines, const char *msg)
1710 {
1711 int len;
1712 int i;
1713
1714 for (i = 0; i < ARRAY_SIZE(error->engine); i++)
1715 if (!error->engine[i].context.pid)
1716 engines &= ~BIT(i);
1717
1718 len = scnprintf(error->error_msg, sizeof(error->error_msg),
1719 "GPU HANG: ecode %d:%lx:0x%08x",
1720 INTEL_GEN(error->i915), engines,
1721 i915_error_generate_code(error, engines));
1722 if (engines) {
1723 /* Just show the first executing process, more is confusing */
1724 i = __ffs(engines);
1725 len += scnprintf(error->error_msg + len,
1726 sizeof(error->error_msg) - len,
1727 ", in %s [%d]",
1728 error->engine[i].context.comm,
1729 error->engine[i].context.pid);
1730 }
1731 if (msg)
1732 len += scnprintf(error->error_msg + len,
1733 sizeof(error->error_msg) - len,
1734 ", %s", msg);
1735
1736 return error->error_msg;
1737 }
1738
1739 static void capture_gen_state(struct i915_gpu_state *error)
1740 {
1741 struct drm_i915_private *i915 = error->i915;
1742
1743 error->awake = i915->gt.awake;
1744 error->wakelock = atomic_read(&i915->runtime_pm.wakeref_count);
1745 error->suspended = i915->runtime_pm.suspended;
1746
1747 error->iommu = -1;
1748 #ifdef CONFIG_INTEL_IOMMU
1749 error->iommu = intel_iommu_gfx_mapped;
1750 #endif
1751 error->reset_count = i915_reset_count(&i915->gpu_error);
1752 error->suspend_count = i915->suspend_count;
1753
1754 memcpy(&error->device_info,
1755 INTEL_INFO(i915),
1756 sizeof(error->device_info));
1757 memcpy(&error->runtime_info,
1758 RUNTIME_INFO(i915),
1759 sizeof(error->runtime_info));
1760 error->driver_caps = i915->caps;
1761 }
1762
1763 static void capture_params(struct i915_gpu_state *error)
1764 {
1765 i915_params_copy(&error->params, &i915_modparams);
1766 }
1767
1768 static unsigned long capture_find_epoch(const struct i915_gpu_state *error)
1769 {
1770 unsigned long epoch = error->capture;
1771 int i;
1772
1773 for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
1774 const struct drm_i915_error_engine *ee = &error->engine[i];
1775
1776 if (ee->hangcheck_timestamp &&
1777 time_before(ee->hangcheck_timestamp, epoch))
1778 epoch = ee->hangcheck_timestamp;
1779 }
1780
1781 return epoch;
1782 }
1783
1784 static void capture_finish(struct i915_gpu_state *error)
1785 {
1786 struct i915_ggtt *ggtt = &error->i915->ggtt;
1787 const u64 slot = ggtt->error_capture.start;
1788
1789 ggtt->vm.clear_range(&ggtt->vm, slot, PAGE_SIZE);
1790 }
1791
1792 static int capture(void *data)
1793 {
1794 struct i915_gpu_state *error = data;
1795
1796 error->time = ktime_get_real();
1797 error->boottime = ktime_get_boottime();
1798 error->uptime = ktime_sub(ktime_get(),
1799 error->i915->gt.last_init_time);
1800 error->capture = jiffies;
1801
1802 capture_params(error);
1803 capture_gen_state(error);
1804 capture_uc_state(error);
1805 capture_reg_state(error);
1806 gem_record_fences(error);
1807 gem_record_rings(error);
1808 capture_active_buffers(error);
1809 capture_pinned_buffers(error);
1810
1811 error->overlay = intel_overlay_capture_error_state(error->i915);
1812 error->display = intel_display_capture_error_state(error->i915);
1813
1814 error->epoch = capture_find_epoch(error);
1815
1816 capture_finish(error);
1817 return 0;
1818 }
1819
1820 #define DAY_AS_SECONDS(x) (24 * 60 * 60 * (x))
1821
1822 struct i915_gpu_state *
1823 i915_capture_gpu_state(struct drm_i915_private *i915)
1824 {
1825 struct i915_gpu_state *error;
1826
1827 /* Check if GPU capture has been disabled */
1828 error = READ_ONCE(i915->gpu_error.first_error);
1829 if (IS_ERR(error))
1830 return error;
1831
1832 error = kzalloc(sizeof(*error), GFP_ATOMIC);
1833 if (!error) {
1834 i915_disable_error_state(i915, -ENOMEM);
1835 return ERR_PTR(-ENOMEM);
1836 }
1837
1838 kref_init(&error->ref);
1839 error->i915 = i915;
1840
1841 stop_machine(capture, error, NULL);
1842
1843 return error;
1844 }
1845
1846 /**
1847 * i915_capture_error_state - capture an error record for later analysis
1848 * @i915: i915 device
1849 * @engine_mask: the mask of engines triggering the hang
1850 * @msg: a message to insert into the error capture header
1851 *
1852 * Should be called when an error is detected (either a hang or an error
1853 * interrupt) to capture error state from the time of the error. Fills
1854 * out a structure which becomes available in debugfs for user level tools
1855 * to pick up.
1856 */
1857 void i915_capture_error_state(struct drm_i915_private *i915,
1858 unsigned long engine_mask,
1859 const char *msg)
1860 {
1861 static bool warned;
1862 struct i915_gpu_state *error;
1863 unsigned long flags;
1864
1865 if (!i915_modparams.error_capture)
1866 return;
1867
1868 if (READ_ONCE(i915->gpu_error.first_error))
1869 return;
1870
1871 error = i915_capture_gpu_state(i915);
1872 if (IS_ERR(error))
1873 return;
1874
1875 dev_info(i915->drm.dev, "%s\n", error_msg(error, engine_mask, msg));
1876
1877 if (!error->simulated) {
1878 spin_lock_irqsave(&i915->gpu_error.lock, flags);
1879 if (!i915->gpu_error.first_error) {
1880 i915->gpu_error.first_error = error;
1881 error = NULL;
1882 }
1883 spin_unlock_irqrestore(&i915->gpu_error.lock, flags);
1884 }
1885
1886 if (error) {
1887 __i915_gpu_state_free(&error->ref);
1888 return;
1889 }
1890
1891 if (!warned &&
1892 ktime_get_real_seconds() - DRIVER_TIMESTAMP < DAY_AS_SECONDS(180)) {
1893 DRM_INFO("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n");
1894 DRM_INFO("Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel\n");
1895 DRM_INFO("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n");
1896 DRM_INFO("The gpu crash dump is required to analyze gpu hangs, so please always attach it.\n");
1897 DRM_INFO("GPU crash dump saved to /sys/class/drm/card%d/error\n",
1898 i915->drm.primary->index);
1899 warned = true;
1900 }
1901 }
1902
1903 struct i915_gpu_state *
1904 i915_first_error_state(struct drm_i915_private *i915)
1905 {
1906 struct i915_gpu_state *error;
1907
1908 spin_lock_irq(&i915->gpu_error.lock);
1909 error = i915->gpu_error.first_error;
1910 if (!IS_ERR_OR_NULL(error))
1911 i915_gpu_state_get(error);
1912 spin_unlock_irq(&i915->gpu_error.lock);
1913
1914 return error;
1915 }
1916
1917 void i915_reset_error_state(struct drm_i915_private *i915)
1918 {
1919 struct i915_gpu_state *error;
1920
1921 spin_lock_irq(&i915->gpu_error.lock);
1922 error = i915->gpu_error.first_error;
1923 if (error != ERR_PTR(-ENODEV)) /* if disabled, always disabled */
1924 i915->gpu_error.first_error = NULL;
1925 spin_unlock_irq(&i915->gpu_error.lock);
1926
1927 if (!IS_ERR_OR_NULL(error))
1928 i915_gpu_state_put(error);
1929 }
1930
1931 void i915_disable_error_state(struct drm_i915_private *i915, int err)
1932 {
1933 spin_lock_irq(&i915->gpu_error.lock);
1934 if (!i915->gpu_error.first_error)
1935 i915->gpu_error.first_error = ERR_PTR(err);
1936 spin_unlock_irq(&i915->gpu_error.lock);
1937 }
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