2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include <linux/firmware.h>
29 * DOC: csr support for dmc
31 * Display Context Save and Restore (CSR) firmware support added from gen9
32 * onwards to drive newly added DMC (Display microcontroller) in display
33 * engine to save and restore the state of display engine when it enter into
34 * low-power state and comes back to normal.
37 #define GEN12_CSR_MAX_FW_SIZE ICL_CSR_MAX_FW_SIZE
39 #define ICL_CSR_PATH "i915/icl_dmc_ver1_07.bin"
40 #define ICL_CSR_VERSION_REQUIRED CSR_VERSION(1, 7)
41 #define ICL_CSR_MAX_FW_SIZE 0x6000
42 MODULE_FIRMWARE(ICL_CSR_PATH
);
44 #define CNL_CSR_PATH "i915/cnl_dmc_ver1_07.bin"
45 #define CNL_CSR_VERSION_REQUIRED CSR_VERSION(1, 7)
46 #define CNL_CSR_MAX_FW_SIZE GLK_CSR_MAX_FW_SIZE
47 MODULE_FIRMWARE(CNL_CSR_PATH
);
49 #define GLK_CSR_PATH "i915/glk_dmc_ver1_04.bin"
50 #define GLK_CSR_VERSION_REQUIRED CSR_VERSION(1, 4)
51 #define GLK_CSR_MAX_FW_SIZE 0x4000
52 MODULE_FIRMWARE(GLK_CSR_PATH
);
54 #define KBL_CSR_PATH "i915/kbl_dmc_ver1_04.bin"
55 #define KBL_CSR_VERSION_REQUIRED CSR_VERSION(1, 4)
56 #define KBL_CSR_MAX_FW_SIZE BXT_CSR_MAX_FW_SIZE
57 MODULE_FIRMWARE(KBL_CSR_PATH
);
59 #define SKL_CSR_PATH "i915/skl_dmc_ver1_27.bin"
60 #define SKL_CSR_VERSION_REQUIRED CSR_VERSION(1, 27)
61 #define SKL_CSR_MAX_FW_SIZE BXT_CSR_MAX_FW_SIZE
62 MODULE_FIRMWARE(SKL_CSR_PATH
);
64 #define BXT_CSR_PATH "i915/bxt_dmc_ver1_07.bin"
65 #define BXT_CSR_VERSION_REQUIRED CSR_VERSION(1, 7)
66 #define BXT_CSR_MAX_FW_SIZE 0x3000
67 MODULE_FIRMWARE(BXT_CSR_PATH
);
69 #define CSR_DEFAULT_FW_OFFSET 0xFFFFFFFF
71 struct intel_css_header
{
75 /* Includes the DMC specific header in dwords */
78 /* always value would be 0x10000 */
87 /* in YYYYMMDD format */
90 /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */
112 u32 kernel_header_info
;
115 struct intel_fw_info
{
118 /* Stepping (A, B, C, ..., *). * is a wildcard */
121 /* Sub-stepping (0, 1, ..., *). * is a wildcard */
128 struct intel_package_header
{
129 /* DMC container header length in dwords */
130 unsigned char header_len
;
132 /* always value would be 0x01 */
133 unsigned char header_ver
;
135 unsigned char reserved
[10];
137 /* Number of valid entries in the FWInfo array below */
140 struct intel_fw_info fw_info
[20];
143 struct intel_dmc_header
{
144 /* always value would be 0x40403E3E */
147 /* DMC binary header length */
148 unsigned char header_len
;
151 unsigned char header_ver
;
159 /* Firmware program size (excluding header) in dwords */
162 /* Major Minor version */
165 /* Number of valid MMIO cycles present. */
175 unsigned char dfile
[32];
180 struct stepping_info
{
185 static const struct stepping_info skl_stepping_info
[] = {
186 {'A', '0'}, {'B', '0'}, {'C', '0'},
187 {'D', '0'}, {'E', '0'}, {'F', '0'},
188 {'G', '0'}, {'H', '0'}, {'I', '0'},
189 {'J', '0'}, {'K', '0'}
192 static const struct stepping_info bxt_stepping_info
[] = {
193 {'A', '0'}, {'A', '1'}, {'A', '2'},
194 {'B', '0'}, {'B', '1'}, {'B', '2'}
197 static const struct stepping_info icl_stepping_info
[] = {
198 {'A', '0'}, {'A', '1'}, {'A', '2'},
199 {'B', '0'}, {'B', '2'},
203 static const struct stepping_info no_stepping_info
= { '*', '*' };
205 static const struct stepping_info
*
206 intel_get_stepping_info(struct drm_i915_private
*dev_priv
)
208 const struct stepping_info
*si
;
211 if (IS_ICELAKE(dev_priv
)) {
212 size
= ARRAY_SIZE(icl_stepping_info
);
213 si
= icl_stepping_info
;
214 } else if (IS_SKYLAKE(dev_priv
)) {
215 size
= ARRAY_SIZE(skl_stepping_info
);
216 si
= skl_stepping_info
;
217 } else if (IS_BROXTON(dev_priv
)) {
218 size
= ARRAY_SIZE(bxt_stepping_info
);
219 si
= bxt_stepping_info
;
225 if (INTEL_REVID(dev_priv
) < size
)
226 return si
+ INTEL_REVID(dev_priv
);
228 return &no_stepping_info
;
231 static void gen9_set_dc_state_debugmask(struct drm_i915_private
*dev_priv
)
235 mask
= DC_STATE_DEBUG_MASK_MEMORY_UP
;
237 if (IS_GEN9_LP(dev_priv
))
238 mask
|= DC_STATE_DEBUG_MASK_CORES
;
240 /* The below bit doesn't need to be cleared ever afterwards */
241 val
= I915_READ(DC_STATE_DEBUG
);
242 if ((val
& mask
) != mask
) {
244 I915_WRITE(DC_STATE_DEBUG
, val
);
245 POSTING_READ(DC_STATE_DEBUG
);
250 * intel_csr_load_program() - write the firmware from memory to register.
251 * @dev_priv: i915 drm device.
253 * CSR firmware is read from a .bin file and kept in internal memory one time.
254 * Everytime display comes back from low power state this function is called to
255 * copy the firmware from internal memory to registers.
257 void intel_csr_load_program(struct drm_i915_private
*dev_priv
)
259 u32
*payload
= dev_priv
->csr
.dmc_payload
;
262 if (!HAS_CSR(dev_priv
)) {
263 DRM_ERROR("No CSR support available for this platform\n");
267 if (!dev_priv
->csr
.dmc_payload
) {
268 DRM_ERROR("Tried to program CSR with empty payload\n");
272 fw_size
= dev_priv
->csr
.dmc_fw_size
;
273 assert_rpm_wakelock_held(dev_priv
);
277 for (i
= 0; i
< fw_size
; i
++)
278 I915_WRITE_FW(CSR_PROGRAM(i
), payload
[i
]);
282 for (i
= 0; i
< dev_priv
->csr
.mmio_count
; i
++) {
283 I915_WRITE(dev_priv
->csr
.mmioaddr
[i
],
284 dev_priv
->csr
.mmiodata
[i
]);
287 dev_priv
->csr
.dc_state
= 0;
289 gen9_set_dc_state_debugmask(dev_priv
);
292 static u32
*parse_csr_fw(struct drm_i915_private
*dev_priv
,
293 const struct firmware
*fw
)
295 struct intel_css_header
*css_header
;
296 struct intel_package_header
*package_header
;
297 struct intel_dmc_header
*dmc_header
;
298 struct intel_csr
*csr
= &dev_priv
->csr
;
299 const struct stepping_info
*si
= intel_get_stepping_info(dev_priv
);
300 u32 dmc_offset
= CSR_DEFAULT_FW_OFFSET
, readcount
= 0, nbytes
;
307 /* Extract CSS Header information*/
308 css_header
= (struct intel_css_header
*)fw
->data
;
309 if (sizeof(struct intel_css_header
) !=
310 (css_header
->header_len
* 4)) {
311 DRM_ERROR("DMC firmware has wrong CSS header length "
313 (css_header
->header_len
* 4));
317 if (csr
->required_version
&&
318 css_header
->version
!= csr
->required_version
) {
319 DRM_INFO("Refusing to load DMC firmware v%u.%u,"
320 " please use v%u.%u\n",
321 CSR_VERSION_MAJOR(css_header
->version
),
322 CSR_VERSION_MINOR(css_header
->version
),
323 CSR_VERSION_MAJOR(csr
->required_version
),
324 CSR_VERSION_MINOR(csr
->required_version
));
328 csr
->version
= css_header
->version
;
330 readcount
+= sizeof(struct intel_css_header
);
332 /* Extract Package Header information*/
333 package_header
= (struct intel_package_header
*)
334 &fw
->data
[readcount
];
335 if (sizeof(struct intel_package_header
) !=
336 (package_header
->header_len
* 4)) {
337 DRM_ERROR("DMC firmware has wrong package header length "
339 (package_header
->header_len
* 4));
342 readcount
+= sizeof(struct intel_package_header
);
344 /* Search for dmc_offset to find firware binary. */
345 for (i
= 0; i
< package_header
->num_entries
; i
++) {
346 if (package_header
->fw_info
[i
].substepping
== '*' &&
347 si
->stepping
== package_header
->fw_info
[i
].stepping
) {
348 dmc_offset
= package_header
->fw_info
[i
].offset
;
350 } else if (si
->stepping
== package_header
->fw_info
[i
].stepping
&&
351 si
->substepping
== package_header
->fw_info
[i
].substepping
) {
352 dmc_offset
= package_header
->fw_info
[i
].offset
;
354 } else if (package_header
->fw_info
[i
].stepping
== '*' &&
355 package_header
->fw_info
[i
].substepping
== '*')
356 dmc_offset
= package_header
->fw_info
[i
].offset
;
358 if (dmc_offset
== CSR_DEFAULT_FW_OFFSET
) {
359 DRM_ERROR("DMC firmware not supported for %c stepping\n",
363 /* Convert dmc_offset into number of bytes. By default it is in dwords*/
365 readcount
+= dmc_offset
;
367 /* Extract dmc_header information. */
368 dmc_header
= (struct intel_dmc_header
*)&fw
->data
[readcount
];
369 if (sizeof(struct intel_dmc_header
) != (dmc_header
->header_len
)) {
370 DRM_ERROR("DMC firmware has wrong dmc header length "
372 (dmc_header
->header_len
));
375 readcount
+= sizeof(struct intel_dmc_header
);
377 /* Cache the dmc header info. */
378 if (dmc_header
->mmio_count
> ARRAY_SIZE(csr
->mmioaddr
)) {
379 DRM_ERROR("DMC firmware has wrong mmio count %u\n",
380 dmc_header
->mmio_count
);
383 csr
->mmio_count
= dmc_header
->mmio_count
;
384 for (i
= 0; i
< dmc_header
->mmio_count
; i
++) {
385 if (dmc_header
->mmioaddr
[i
] < CSR_MMIO_START_RANGE
||
386 dmc_header
->mmioaddr
[i
] > CSR_MMIO_END_RANGE
) {
387 DRM_ERROR("DMC firmware has wrong mmio address 0x%x\n",
388 dmc_header
->mmioaddr
[i
]);
391 csr
->mmioaddr
[i
] = _MMIO(dmc_header
->mmioaddr
[i
]);
392 csr
->mmiodata
[i
] = dmc_header
->mmiodata
[i
];
395 /* fw_size is in dwords, so multiplied by 4 to convert into bytes. */
396 nbytes
= dmc_header
->fw_size
* 4;
397 if (nbytes
> csr
->max_fw_size
) {
398 DRM_ERROR("DMC FW too big (%u bytes)\n", nbytes
);
401 csr
->dmc_fw_size
= dmc_header
->fw_size
;
403 dmc_payload
= kmalloc(nbytes
, GFP_KERNEL
);
405 DRM_ERROR("Memory allocation failed for dmc payload\n");
409 return memcpy(dmc_payload
, &fw
->data
[readcount
], nbytes
);
412 static void intel_csr_runtime_pm_get(struct drm_i915_private
*dev_priv
)
414 WARN_ON(dev_priv
->csr
.wakeref
);
415 dev_priv
->csr
.wakeref
=
416 intel_display_power_get(dev_priv
, POWER_DOMAIN_INIT
);
419 static void intel_csr_runtime_pm_put(struct drm_i915_private
*dev_priv
)
421 intel_wakeref_t wakeref __maybe_unused
=
422 fetch_and_zero(&dev_priv
->csr
.wakeref
);
424 intel_display_power_put(dev_priv
, POWER_DOMAIN_INIT
, wakeref
);
427 static void csr_load_work_fn(struct work_struct
*work
)
429 struct drm_i915_private
*dev_priv
;
430 struct intel_csr
*csr
;
431 const struct firmware
*fw
= NULL
;
433 dev_priv
= container_of(work
, typeof(*dev_priv
), csr
.work
);
434 csr
= &dev_priv
->csr
;
436 request_firmware(&fw
, dev_priv
->csr
.fw_path
, &dev_priv
->drm
.pdev
->dev
);
438 dev_priv
->csr
.dmc_payload
= parse_csr_fw(dev_priv
, fw
);
440 if (dev_priv
->csr
.dmc_payload
) {
441 intel_csr_load_program(dev_priv
);
442 intel_csr_runtime_pm_put(dev_priv
);
444 DRM_INFO("Finished loading DMC firmware %s (v%u.%u)\n",
445 dev_priv
->csr
.fw_path
,
446 CSR_VERSION_MAJOR(csr
->version
),
447 CSR_VERSION_MINOR(csr
->version
));
449 dev_notice(dev_priv
->drm
.dev
,
450 "Failed to load DMC firmware %s."
451 " Disabling runtime power management.\n",
453 dev_notice(dev_priv
->drm
.dev
, "DMC firmware homepage: %s",
454 INTEL_UC_FIRMWARE_URL
);
457 release_firmware(fw
);
461 * intel_csr_ucode_init() - initialize the firmware loading.
462 * @dev_priv: i915 drm device.
464 * This function is called at the time of loading the display driver to read
465 * firmware from a .bin file and copied into a internal memory.
467 void intel_csr_ucode_init(struct drm_i915_private
*dev_priv
)
469 struct intel_csr
*csr
= &dev_priv
->csr
;
471 INIT_WORK(&dev_priv
->csr
.work
, csr_load_work_fn
);
473 if (!HAS_CSR(dev_priv
))
477 * Obtain a runtime pm reference, until CSR is loaded, to avoid entering
480 * On error, we return with the rpm wakeref held to prevent runtime
481 * suspend as runtime suspend *requires* a working CSR for whatever
484 intel_csr_runtime_pm_get(dev_priv
);
486 if (INTEL_GEN(dev_priv
) >= 12) {
487 /* Allow to load fw via parameter using the last known size */
488 csr
->max_fw_size
= GEN12_CSR_MAX_FW_SIZE
;
489 } else if (IS_ICELAKE(dev_priv
)) {
490 csr
->fw_path
= ICL_CSR_PATH
;
491 csr
->required_version
= ICL_CSR_VERSION_REQUIRED
;
492 csr
->max_fw_size
= ICL_CSR_MAX_FW_SIZE
;
493 } else if (IS_CANNONLAKE(dev_priv
)) {
494 csr
->fw_path
= CNL_CSR_PATH
;
495 csr
->required_version
= CNL_CSR_VERSION_REQUIRED
;
496 csr
->max_fw_size
= CNL_CSR_MAX_FW_SIZE
;
497 } else if (IS_GEMINILAKE(dev_priv
)) {
498 csr
->fw_path
= GLK_CSR_PATH
;
499 csr
->required_version
= GLK_CSR_VERSION_REQUIRED
;
500 csr
->max_fw_size
= GLK_CSR_MAX_FW_SIZE
;
501 } else if (IS_KABYLAKE(dev_priv
) || IS_COFFEELAKE(dev_priv
)) {
502 csr
->fw_path
= KBL_CSR_PATH
;
503 csr
->required_version
= KBL_CSR_VERSION_REQUIRED
;
504 csr
->max_fw_size
= KBL_CSR_MAX_FW_SIZE
;
505 } else if (IS_SKYLAKE(dev_priv
)) {
506 csr
->fw_path
= SKL_CSR_PATH
;
507 csr
->required_version
= SKL_CSR_VERSION_REQUIRED
;
508 csr
->max_fw_size
= SKL_CSR_MAX_FW_SIZE
;
509 } else if (IS_BROXTON(dev_priv
)) {
510 csr
->fw_path
= BXT_CSR_PATH
;
511 csr
->required_version
= BXT_CSR_VERSION_REQUIRED
;
512 csr
->max_fw_size
= BXT_CSR_MAX_FW_SIZE
;
515 if (i915_modparams
.dmc_firmware_path
) {
516 if (strlen(i915_modparams
.dmc_firmware_path
) == 0) {
518 DRM_INFO("Disabling CSR firmware and runtime PM\n");
522 csr
->fw_path
= i915_modparams
.dmc_firmware_path
;
523 /* Bypass version check for firmware override. */
524 csr
->required_version
= 0;
527 if (csr
->fw_path
== NULL
) {
528 DRM_DEBUG_KMS("No known CSR firmware for platform, disabling runtime PM\n");
529 WARN_ON(!IS_ALPHA_SUPPORT(INTEL_INFO(dev_priv
)));
534 DRM_DEBUG_KMS("Loading %s\n", csr
->fw_path
);
535 schedule_work(&dev_priv
->csr
.work
);
539 * intel_csr_ucode_suspend() - prepare CSR firmware before system suspend
540 * @dev_priv: i915 drm device
542 * Prepare the DMC firmware before entering system suspend. This includes
543 * flushing pending work items and releasing any resources acquired during
546 void intel_csr_ucode_suspend(struct drm_i915_private
*dev_priv
)
548 if (!HAS_CSR(dev_priv
))
551 flush_work(&dev_priv
->csr
.work
);
553 /* Drop the reference held in case DMC isn't loaded. */
554 if (!dev_priv
->csr
.dmc_payload
)
555 intel_csr_runtime_pm_put(dev_priv
);
559 * intel_csr_ucode_resume() - init CSR firmware during system resume
560 * @dev_priv: i915 drm device
562 * Reinitialize the DMC firmware during system resume, reacquiring any
563 * resources released in intel_csr_ucode_suspend().
565 void intel_csr_ucode_resume(struct drm_i915_private
*dev_priv
)
567 if (!HAS_CSR(dev_priv
))
571 * Reacquire the reference to keep RPM disabled in case DMC isn't
574 if (!dev_priv
->csr
.dmc_payload
)
575 intel_csr_runtime_pm_get(dev_priv
);
579 * intel_csr_ucode_fini() - unload the CSR firmware.
580 * @dev_priv: i915 drm device.
582 * Firmmware unloading includes freeing the internal memory and reset the
583 * firmware loading status.
585 void intel_csr_ucode_fini(struct drm_i915_private
*dev_priv
)
587 if (!HAS_CSR(dev_priv
))
590 intel_csr_ucode_suspend(dev_priv
);
591 WARN_ON(dev_priv
->csr
.wakeref
);
593 kfree(dev_priv
->csr
.dmc_payload
);