drivers/gpu/drm/i915/intel_csr.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include <linux/firmware.h>
  26
  27 #include "i915_drv.h"
  28 #include "i915_reg.h"
  29 #include "intel_csr.h"
  30
  31 /**
  32  * DOC: csr support for dmc
  33  *
  34  * Display Context Save and Restore (CSR) firmware support added from gen9
  35  * onwards to drive newly added DMC (Display microcontroller) in display
  36  * engine to save and restore the state of display engine when it enter into
  37  * low-power state and comes back to normal.
  38  */
  39
  40 #define GEN12_CSR_MAX_FW_SIZE           ICL_CSR_MAX_FW_SIZE
  41
  42 #define ICL_CSR_PATH                    "i915/icl_dmc_ver1_07.bin"
  43 #define ICL_CSR_VERSION_REQUIRED        CSR_VERSION(1, 7)
  44 #define ICL_CSR_MAX_FW_SIZE             0x6000
  45 MODULE_FIRMWARE(ICL_CSR_PATH);
  46
  47 #define CNL_CSR_PATH                    "i915/cnl_dmc_ver1_07.bin"
  48 #define CNL_CSR_VERSION_REQUIRED        CSR_VERSION(1, 7)
  49 #define CNL_CSR_MAX_FW_SIZE             GLK_CSR_MAX_FW_SIZE
  50 MODULE_FIRMWARE(CNL_CSR_PATH);
  51
  52 #define GLK_CSR_PATH                    "i915/glk_dmc_ver1_04.bin"
  53 #define GLK_CSR_VERSION_REQUIRED        CSR_VERSION(1, 4)
  54 #define GLK_CSR_MAX_FW_SIZE             0x4000
  55 MODULE_FIRMWARE(GLK_CSR_PATH);
  56
  57 #define KBL_CSR_PATH                    "i915/kbl_dmc_ver1_04.bin"
  58 #define KBL_CSR_VERSION_REQUIRED        CSR_VERSION(1, 4)
  59 #define KBL_CSR_MAX_FW_SIZE             BXT_CSR_MAX_FW_SIZE
  60 MODULE_FIRMWARE(KBL_CSR_PATH);
  61
  62 #define SKL_CSR_PATH                    "i915/skl_dmc_ver1_27.bin"
  63 #define SKL_CSR_VERSION_REQUIRED        CSR_VERSION(1, 27)
  64 #define SKL_CSR_MAX_FW_SIZE             BXT_CSR_MAX_FW_SIZE
  65 MODULE_FIRMWARE(SKL_CSR_PATH);
  66
  67 #define BXT_CSR_PATH                    "i915/bxt_dmc_ver1_07.bin"
  68 #define BXT_CSR_VERSION_REQUIRED        CSR_VERSION(1, 7)
  69 #define BXT_CSR_MAX_FW_SIZE             0x3000
  70 MODULE_FIRMWARE(BXT_CSR_PATH);
  71
  72 #define CSR_DEFAULT_FW_OFFSET           0xFFFFFFFF
  73
  74 struct intel_css_header {
  75         /* 0x09 for DMC */
  76         u32 module_type;
  77
  78         /* Includes the DMC specific header in dwords */
  79         u32 header_len;
  80
  81         /* always value would be 0x10000 */
  82         u32 header_ver;
  83
  84         /* Not used */
  85         u32 module_id;
  86
  87         /* Not used */
  88         u32 module_vendor;
  89
  90         /* in YYYYMMDD format */
  91         u32 date;
  92
  93         /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */
  94         u32 size;
  95
  96         /* Not used */
  97         u32 key_size;
  98
  99         /* Not used */
 100         u32 modulus_size;
 101
 102         /* Not used */
 103         u32 exponent_size;
 104
 105         /* Not used */
 106         u32 reserved1[12];
 107
 108         /* Major Minor */
 109         u32 version;
 110
 111         /* Not used */
 112         u32 reserved2[8];
 113
 114         /* Not used */
 115         u32 kernel_header_info;
 116 } __packed;
 117
 118 struct intel_fw_info {
 119         u16 reserved1;
 120
 121         /* Stepping (A, B, C, ..., *). * is a wildcard */
 122         char stepping;
 123
 124         /* Sub-stepping (0, 1, ..., *). * is a wildcard */
 125         char substepping;
 126
 127         u32 offset;
 128         u32 reserved2;
 129 } __packed;
 130
 131 struct intel_package_header {
 132         /* DMC container header length in dwords */
 133         unsigned char header_len;
 134
 135         /* always value would be 0x01 */
 136         unsigned char header_ver;
 137
 138         unsigned char reserved[10];
 139
 140         /* Number of valid entries in the FWInfo array below */
 141         u32 num_entries;
 142
 143         struct intel_fw_info fw_info[20];
 144 } __packed;
 145
 146 struct intel_dmc_header {
 147         /* always value would be 0x40403E3E */
 148         u32 signature;
 149
 150         /* DMC binary header length */
 151         unsigned char header_len;
 152
 153         /* 0x01 */
 154         unsigned char header_ver;
 155
 156         /* Reserved */
 157         u16 dmcc_ver;
 158
 159         /* Major, Minor */
 160         u32 project;
 161
 162         /* Firmware program size (excluding header) in dwords */
 163         u32 fw_size;
 164
 165         /* Major Minor version */
 166         u32 fw_version;
 167
 168         /* Number of valid MMIO cycles present. */
 169         u32 mmio_count;
 170
 171         /* MMIO address */
 172         u32 mmioaddr[8];
 173
 174         /* MMIO data */
 175         u32 mmiodata[8];
 176
 177         /* FW filename  */
 178         unsigned char dfile[32];
 179
 180         u32 reserved1[2];
 181 } __packed;
 182
 183 struct stepping_info {
 184         char stepping;
 185         char substepping;
 186 };
 187
 188 static const struct stepping_info skl_stepping_info[] = {
 189         {'A', '0'}, {'B', '0'}, {'C', '0'},
 190         {'D', '0'}, {'E', '0'}, {'F', '0'},
 191         {'G', '0'}, {'H', '0'}, {'I', '0'},
 192         {'J', '0'}, {'K', '0'}
 193 };
 194
 195 static const struct stepping_info bxt_stepping_info[] = {
 196         {'A', '0'}, {'A', '1'}, {'A', '2'},
 197         {'B', '0'}, {'B', '1'}, {'B', '2'}
 198 };
 199
 200 static const struct stepping_info icl_stepping_info[] = {
 201         {'A', '0'}, {'A', '1'}, {'A', '2'},
 202         {'B', '0'}, {'B', '2'},
 203         {'C', '0'}
 204 };
 205
 206 static const struct stepping_info no_stepping_info = { '*', '*' };
 207
 208 static const struct stepping_info *
 209 intel_get_stepping_info(struct drm_i915_private *dev_priv)
 210 {
 211         const struct stepping_info *si;
 212         unsigned int size;
 213
 214         if (IS_ICELAKE(dev_priv)) {
 215                 size = ARRAY_SIZE(icl_stepping_info);
 216                 si = icl_stepping_info;
 217         } else if (IS_SKYLAKE(dev_priv)) {
 218                 size = ARRAY_SIZE(skl_stepping_info);
 219                 si = skl_stepping_info;
 220         } else if (IS_BROXTON(dev_priv)) {
 221                 size = ARRAY_SIZE(bxt_stepping_info);
 222                 si = bxt_stepping_info;
 223         } else {
 224                 size = 0;
 225                 si = NULL;
 226         }
 227
 228         if (INTEL_REVID(dev_priv) < size)
 229                 return si + INTEL_REVID(dev_priv);
 230
 231         return &no_stepping_info;
 232 }
 233
 234 static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
 235 {
 236         u32 val, mask;
 237
 238         mask = DC_STATE_DEBUG_MASK_MEMORY_UP;
 239
 240         if (IS_GEN9_LP(dev_priv))
 241                 mask |= DC_STATE_DEBUG_MASK_CORES;
 242
 243         /* The below bit doesn't need to be cleared ever afterwards */
 244         val = I915_READ(DC_STATE_DEBUG);
 245         if ((val & mask) != mask) {
 246                 val |= mask;
 247                 I915_WRITE(DC_STATE_DEBUG, val);
 248                 POSTING_READ(DC_STATE_DEBUG);
 249         }
 250 }
 251
 252 /**
 253  * intel_csr_load_program() - write the firmware from memory to register.
 254  * @dev_priv: i915 drm device.
 255  *
 256  * CSR firmware is read from a .bin file and kept in internal memory one time.
 257  * Everytime display comes back from low power state this function is called to
 258  * copy the firmware from internal memory to registers.
 259  */
 260 void intel_csr_load_program(struct drm_i915_private *dev_priv)
 261 {
 262         u32 *payload = dev_priv->csr.dmc_payload;
 263         u32 i, fw_size;
 264
 265         if (!HAS_CSR(dev_priv)) {
 266                 DRM_ERROR("No CSR support available for this platform\n");
 267                 return;
 268         }
 269
 270         if (!dev_priv->csr.dmc_payload) {
 271                 DRM_ERROR("Tried to program CSR with empty payload\n");
 272                 return;
 273         }
 274
 275         fw_size = dev_priv->csr.dmc_fw_size;
 276         assert_rpm_wakelock_held(dev_priv);
 277
 278         preempt_disable();
 279
 280         for (i = 0; i < fw_size; i++)
 281                 I915_WRITE_FW(CSR_PROGRAM(i), payload[i]);
 282
 283         preempt_enable();
 284
 285         for (i = 0; i < dev_priv->csr.mmio_count; i++) {
 286                 I915_WRITE(dev_priv->csr.mmioaddr[i],
 287                            dev_priv->csr.mmiodata[i]);
 288         }
 289
 290         dev_priv->csr.dc_state = 0;
 291
 292         gen9_set_dc_state_debugmask(dev_priv);
 293 }
 294
 295 static u32 *parse_csr_fw(struct drm_i915_private *dev_priv,
 296                          const struct firmware *fw)
 297 {
 298         struct intel_css_header *css_header;
 299         struct intel_package_header *package_header;
 300         struct intel_dmc_header *dmc_header;
 301         struct intel_csr *csr = &dev_priv->csr;
 302         const struct stepping_info *si = intel_get_stepping_info(dev_priv);
 303         u32 dmc_offset = CSR_DEFAULT_FW_OFFSET, readcount = 0, nbytes;
 304         u32 i;
 305         u32 *dmc_payload;
 306
 307         if (!fw)
 308                 return NULL;
 309
 310         /* Extract CSS Header information*/
 311         css_header = (struct intel_css_header *)fw->data;
 312         if (sizeof(struct intel_css_header) !=
 313             (css_header->header_len * 4)) {
 314                 DRM_ERROR("DMC firmware has wrong CSS header length "
 315                           "(%u bytes)\n",
 316                           (css_header->header_len * 4));
 317                 return NULL;
 318         }
 319
 320         if (csr->required_version &&
 321             css_header->version != csr->required_version) {
 322                 DRM_INFO("Refusing to load DMC firmware v%u.%u,"
 323                          " please use v%u.%u\n",
 324                          CSR_VERSION_MAJOR(css_header->version),
 325                          CSR_VERSION_MINOR(css_header->version),
 326                          CSR_VERSION_MAJOR(csr->required_version),
 327                          CSR_VERSION_MINOR(csr->required_version));
 328                 return NULL;
 329         }
 330
 331         csr->version = css_header->version;
 332
 333         readcount += sizeof(struct intel_css_header);
 334
 335         /* Extract Package Header information*/
 336         package_header = (struct intel_package_header *)
 337                 &fw->data[readcount];
 338         if (sizeof(struct intel_package_header) !=
 339             (package_header->header_len * 4)) {
 340                 DRM_ERROR("DMC firmware has wrong package header length "
 341                           "(%u bytes)\n",
 342                           (package_header->header_len * 4));
 343                 return NULL;
 344         }
 345         readcount += sizeof(struct intel_package_header);
 346
 347         /* Search for dmc_offset to find firware binary. */
 348         for (i = 0; i < package_header->num_entries; i++) {
 349                 if (package_header->fw_info[i].substepping == '*' &&
 350                     si->stepping == package_header->fw_info[i].stepping) {
 351                         dmc_offset = package_header->fw_info[i].offset;
 352                         break;
 353                 } else if (si->stepping == package_header->fw_info[i].stepping &&
 354                            si->substepping == package_header->fw_info[i].substepping) {
 355                         dmc_offset = package_header->fw_info[i].offset;
 356                         break;
 357                 } else if (package_header->fw_info[i].stepping == '*' &&
 358                            package_header->fw_info[i].substepping == '*')
 359                         dmc_offset = package_header->fw_info[i].offset;
 360         }
 361         if (dmc_offset == CSR_DEFAULT_FW_OFFSET) {
 362                 DRM_ERROR("DMC firmware not supported for %c stepping\n",
 363                           si->stepping);
 364                 return NULL;
 365         }
 366         /* Convert dmc_offset into number of bytes. By default it is in dwords*/
 367         dmc_offset *= 4;
 368         readcount += dmc_offset;
 369
 370         /* Extract dmc_header information. */
 371         dmc_header = (struct intel_dmc_header *)&fw->data[readcount];
 372         if (sizeof(struct intel_dmc_header) != (dmc_header->header_len)) {
 373                 DRM_ERROR("DMC firmware has wrong dmc header length "
 374                           "(%u bytes)\n",
 375                           (dmc_header->header_len));
 376                 return NULL;
 377         }
 378         readcount += sizeof(struct intel_dmc_header);
 379
 380         /* Cache the dmc header info. */
 381         if (dmc_header->mmio_count > ARRAY_SIZE(csr->mmioaddr)) {
 382                 DRM_ERROR("DMC firmware has wrong mmio count %u\n",
 383                           dmc_header->mmio_count);
 384                 return NULL;
 385         }
 386         csr->mmio_count = dmc_header->mmio_count;
 387         for (i = 0; i < dmc_header->mmio_count; i++) {
 388                 if (dmc_header->mmioaddr[i] < CSR_MMIO_START_RANGE ||
 389                     dmc_header->mmioaddr[i] > CSR_MMIO_END_RANGE) {
 390                         DRM_ERROR("DMC firmware has wrong mmio address 0x%x\n",
 391                                   dmc_header->mmioaddr[i]);
 392                         return NULL;
 393                 }
 394                 csr->mmioaddr[i] = _MMIO(dmc_header->mmioaddr[i]);
 395                 csr->mmiodata[i] = dmc_header->mmiodata[i];
 396         }
 397
 398         /* fw_size is in dwords, so multiplied by 4 to convert into bytes. */
 399         nbytes = dmc_header->fw_size * 4;
 400         if (nbytes > csr->max_fw_size) {
 401                 DRM_ERROR("DMC FW too big (%u bytes)\n", nbytes);
 402                 return NULL;
 403         }
 404         csr->dmc_fw_size = dmc_header->fw_size;
 405
 406         dmc_payload = kmalloc(nbytes, GFP_KERNEL);
 407         if (!dmc_payload) {
 408                 DRM_ERROR("Memory allocation failed for dmc payload\n");
 409                 return NULL;
 410         }
 411
 412         return memcpy(dmc_payload, &fw->data[readcount], nbytes);
 413 }
 414
 415 static void intel_csr_runtime_pm_get(struct drm_i915_private *dev_priv)
 416 {
 417         WARN_ON(dev_priv->csr.wakeref);
 418         dev_priv->csr.wakeref =
 419                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 420 }
 421
 422 static void intel_csr_runtime_pm_put(struct drm_i915_private *dev_priv)
 423 {
 424         intel_wakeref_t wakeref __maybe_unused =
 425                 fetch_and_zero(&dev_priv->csr.wakeref);
 426
 427         intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref);
 428 }
 429
 430 static void csr_load_work_fn(struct work_struct *work)
 431 {
 432         struct drm_i915_private *dev_priv;
 433         struct intel_csr *csr;
 434         const struct firmware *fw = NULL;
 435
 436         dev_priv = container_of(work, typeof(*dev_priv), csr.work);
 437         csr = &dev_priv->csr;
 438
 439         request_firmware(&fw, dev_priv->csr.fw_path, &dev_priv->drm.pdev->dev);
 440         if (fw)
 441                 dev_priv->csr.dmc_payload = parse_csr_fw(dev_priv, fw);
 442
 443         if (dev_priv->csr.dmc_payload) {
 444                 intel_csr_load_program(dev_priv);
 445                 intel_csr_runtime_pm_put(dev_priv);
 446
 447                 DRM_INFO("Finished loading DMC firmware %s (v%u.%u)\n",
 448                          dev_priv->csr.fw_path,
 449                          CSR_VERSION_MAJOR(csr->version),
 450                          CSR_VERSION_MINOR(csr->version));
 451         } else {
 452                 dev_notice(dev_priv->drm.dev,
 453                            "Failed to load DMC firmware %s."
 454                            " Disabling runtime power management.\n",
 455                            csr->fw_path);
 456                 dev_notice(dev_priv->drm.dev, "DMC firmware homepage: %s",
 457                            INTEL_UC_FIRMWARE_URL);
 458         }
 459
 460         release_firmware(fw);
 461 }
 462
 463 /**
 464  * intel_csr_ucode_init() - initialize the firmware loading.
 465  * @dev_priv: i915 drm device.
 466  *
 467  * This function is called at the time of loading the display driver to read
 468  * firmware from a .bin file and copied into a internal memory.
 469  */
 470 void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
 471 {
 472         struct intel_csr *csr = &dev_priv->csr;
 473
 474         INIT_WORK(&dev_priv->csr.work, csr_load_work_fn);
 475
 476         if (!HAS_CSR(dev_priv))
 477                 return;
 478
 479         /*
 480          * Obtain a runtime pm reference, until CSR is loaded, to avoid entering
 481          * runtime-suspend.
 482          *
 483          * On error, we return with the rpm wakeref held to prevent runtime
 484          * suspend as runtime suspend *requires* a working CSR for whatever
 485          * reason.
 486          */
 487         intel_csr_runtime_pm_get(dev_priv);
 488
 489         if (INTEL_GEN(dev_priv) >= 12) {
 490                 /* Allow to load fw via parameter using the last known size */
 491                 csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
 492         } else if (IS_GEN(dev_priv, 11)) {
 493                 csr->fw_path = ICL_CSR_PATH;
 494                 csr->required_version = ICL_CSR_VERSION_REQUIRED;
 495                 csr->max_fw_size = ICL_CSR_MAX_FW_SIZE;
 496         } else if (IS_CANNONLAKE(dev_priv)) {
 497                 csr->fw_path = CNL_CSR_PATH;
 498                 csr->required_version = CNL_CSR_VERSION_REQUIRED;
 499                 csr->max_fw_size = CNL_CSR_MAX_FW_SIZE;
 500         } else if (IS_GEMINILAKE(dev_priv)) {
 501                 csr->fw_path = GLK_CSR_PATH;
 502                 csr->required_version = GLK_CSR_VERSION_REQUIRED;
 503                 csr->max_fw_size = GLK_CSR_MAX_FW_SIZE;
 504         } else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
 505                 csr->fw_path = KBL_CSR_PATH;
 506                 csr->required_version = KBL_CSR_VERSION_REQUIRED;
 507                 csr->max_fw_size = KBL_CSR_MAX_FW_SIZE;
 508         } else if (IS_SKYLAKE(dev_priv)) {
 509                 csr->fw_path = SKL_CSR_PATH;
 510                 csr->required_version = SKL_CSR_VERSION_REQUIRED;
 511                 csr->max_fw_size = SKL_CSR_MAX_FW_SIZE;
 512         } else if (IS_BROXTON(dev_priv)) {
 513                 csr->fw_path = BXT_CSR_PATH;
 514                 csr->required_version = BXT_CSR_VERSION_REQUIRED;
 515                 csr->max_fw_size = BXT_CSR_MAX_FW_SIZE;
 516         }
 517
 518         if (i915_modparams.dmc_firmware_path) {
 519                 if (strlen(i915_modparams.dmc_firmware_path) == 0) {
 520                         csr->fw_path = NULL;
 521                         DRM_INFO("Disabling CSR firmware and runtime PM\n");
 522                         return;
 523                 }
 524
 525                 csr->fw_path = i915_modparams.dmc_firmware_path;
 526                 /* Bypass version check for firmware override. */
 527                 csr->required_version = 0;
 528         }
 529
 530         if (csr->fw_path == NULL) {
 531                 DRM_DEBUG_KMS("No known CSR firmware for platform, disabling runtime PM\n");
 532                 WARN_ON(!IS_ALPHA_SUPPORT(INTEL_INFO(dev_priv)));
 533
 534                 return;
 535         }
 536
 537         DRM_DEBUG_KMS("Loading %s\n", csr->fw_path);
 538         schedule_work(&dev_priv->csr.work);
 539 }
 540
 541 /**
 542  * intel_csr_ucode_suspend() - prepare CSR firmware before system suspend
 543  * @dev_priv: i915 drm device
 544  *
 545  * Prepare the DMC firmware before entering system suspend. This includes
 546  * flushing pending work items and releasing any resources acquired during
 547  * init.
 548  */
 549 void intel_csr_ucode_suspend(struct drm_i915_private *dev_priv)
 550 {
 551         if (!HAS_CSR(dev_priv))
 552                 return;
 553
 554         flush_work(&dev_priv->csr.work);
 555
 556         /* Drop the reference held in case DMC isn't loaded. */
 557         if (!dev_priv->csr.dmc_payload)
 558                 intel_csr_runtime_pm_put(dev_priv);
 559 }
 560
 561 /**
 562  * intel_csr_ucode_resume() - init CSR firmware during system resume
 563  * @dev_priv: i915 drm device
 564  *
 565  * Reinitialize the DMC firmware during system resume, reacquiring any
 566  * resources released in intel_csr_ucode_suspend().
 567  */
 568 void intel_csr_ucode_resume(struct drm_i915_private *dev_priv)
 569 {
 570         if (!HAS_CSR(dev_priv))
 571                 return;
 572
 573         /*
 574          * Reacquire the reference to keep RPM disabled in case DMC isn't
 575          * loaded.
 576          */
 577         if (!dev_priv->csr.dmc_payload)
 578                 intel_csr_runtime_pm_get(dev_priv);
 579 }
 580
 581 /**
 582  * intel_csr_ucode_fini() - unload the CSR firmware.
 583  * @dev_priv: i915 drm device.
 584  *
 585  * Firmmware unloading includes freeing the internal memory and reset the
 586  * firmware loading status.
 587  */
 588 void intel_csr_ucode_fini(struct drm_i915_private *dev_priv)
 589 {
 590         if (!HAS_CSR(dev_priv))
 591                 return;
 592
 593         intel_csr_ucode_suspend(dev_priv);
 594         WARN_ON(dev_priv->csr.wakeref);
 595
 596         kfree(dev_priv->csr.dmc_payload);
 597 }