2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/i2c.h>
28 #include <linux/input.h>
29 #include <linux/intel-iommu.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/reservation.h>
33 #include <linux/slab.h>
34 #include <linux/vgaarb.h>
36 #include <drm/drm_atomic.h>
37 #include <drm/drm_atomic_helper.h>
38 #include <drm/drm_atomic_uapi.h>
39 #include <drm/drm_dp_helper.h>
40 #include <drm/drm_edid.h>
41 #include <drm/drm_fourcc.h>
42 #include <drm/drm_plane_helper.h>
43 #include <drm/drm_probe_helper.h>
44 #include <drm/drm_rect.h>
45 #include <drm/i915_drm.h>
48 #include "i915_gem_clflush.h"
49 #include "i915_trace.h"
50 #include "intel_acpi.h"
51 #include "intel_atomic.h"
52 #include "intel_atomic_plane.h"
53 #include "intel_color.h"
54 #include "intel_cdclk.h"
55 #include "intel_crt.h"
56 #include "intel_ddi.h"
58 #include "intel_drv.h"
59 #include "intel_dsi.h"
60 #include "intel_dvo.h"
61 #include "intel_fbc.h"
62 #include "intel_fbdev.h"
63 #include "intel_fifo_underrun.h"
64 #include "intel_frontbuffer.h"
65 #include "intel_gmbus.h"
66 #include "intel_hdcp.h"
67 #include "intel_hdmi.h"
68 #include "intel_hotplug.h"
69 #include "intel_lvds.h"
70 #include "intel_overlay.h"
71 #include "intel_pipe_crc.h"
73 #include "intel_psr.h"
74 #include "intel_quirks.h"
75 #include "intel_sdvo.h"
76 #include "intel_sideband.h"
77 #include "intel_sprite.h"
79 #include "intel_vdsc.h"
81 /* Primary plane formats for gen <= 3 */
82 static const u32 i8xx_primary_formats
[] = {
89 /* Primary plane formats for gen >= 4 */
90 static const u32 i965_primary_formats
[] = {
95 DRM_FORMAT_XRGB2101010
,
96 DRM_FORMAT_XBGR2101010
,
99 static const u64 i9xx_format_modifiers
[] = {
100 I915_FORMAT_MOD_X_TILED
,
101 DRM_FORMAT_MOD_LINEAR
,
102 DRM_FORMAT_MOD_INVALID
106 static const u32 intel_cursor_formats
[] = {
110 static const u64 cursor_format_modifiers
[] = {
111 DRM_FORMAT_MOD_LINEAR
,
112 DRM_FORMAT_MOD_INVALID
115 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
116 struct intel_crtc_state
*pipe_config
);
117 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
118 struct intel_crtc_state
*pipe_config
);
120 static int intel_framebuffer_init(struct intel_framebuffer
*ifb
,
121 struct drm_i915_gem_object
*obj
,
122 struct drm_mode_fb_cmd2
*mode_cmd
);
123 static void intel_set_pipe_timings(const struct intel_crtc_state
*crtc_state
);
124 static void intel_set_pipe_src_size(const struct intel_crtc_state
*crtc_state
);
125 static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state
*crtc_state
,
126 const struct intel_link_m_n
*m_n
,
127 const struct intel_link_m_n
*m2_n2
);
128 static void i9xx_set_pipeconf(const struct intel_crtc_state
*crtc_state
);
129 static void ironlake_set_pipeconf(const struct intel_crtc_state
*crtc_state
);
130 static void haswell_set_pipeconf(const struct intel_crtc_state
*crtc_state
);
131 static void bdw_set_pipemisc(const struct intel_crtc_state
*crtc_state
);
132 static void vlv_prepare_pll(struct intel_crtc
*crtc
,
133 const struct intel_crtc_state
*pipe_config
);
134 static void chv_prepare_pll(struct intel_crtc
*crtc
,
135 const struct intel_crtc_state
*pipe_config
);
136 static void intel_begin_crtc_commit(struct intel_atomic_state
*, struct intel_crtc
*);
137 static void intel_finish_crtc_commit(struct intel_atomic_state
*, struct intel_crtc
*);
138 static void intel_crtc_init_scalers(struct intel_crtc
*crtc
,
139 struct intel_crtc_state
*crtc_state
);
140 static void skylake_pfit_enable(const struct intel_crtc_state
*crtc_state
);
141 static void ironlake_pfit_disable(const struct intel_crtc_state
*old_crtc_state
);
142 static void ironlake_pfit_enable(const struct intel_crtc_state
*crtc_state
);
143 static void intel_modeset_setup_hw_state(struct drm_device
*dev
,
144 struct drm_modeset_acquire_ctx
*ctx
);
145 static void intel_pre_disable_primary_noatomic(struct drm_crtc
*crtc
);
150 } dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
154 int p2_slow
, p2_fast
;
158 /* returns HPLL frequency in kHz */
159 int vlv_get_hpll_vco(struct drm_i915_private
*dev_priv
)
161 int hpll_freq
, vco_freq
[] = { 800, 1600, 2000, 2400 };
163 /* Obtain SKU information */
164 hpll_freq
= vlv_cck_read(dev_priv
, CCK_FUSE_REG
) &
165 CCK_FUSE_HPLL_FREQ_MASK
;
167 return vco_freq
[hpll_freq
] * 1000;
170 int vlv_get_cck_clock(struct drm_i915_private
*dev_priv
,
171 const char *name
, u32 reg
, int ref_freq
)
176 val
= vlv_cck_read(dev_priv
, reg
);
177 divider
= val
& CCK_FREQUENCY_VALUES
;
179 WARN((val
& CCK_FREQUENCY_STATUS
) !=
180 (divider
<< CCK_FREQUENCY_STATUS_SHIFT
),
181 "%s change in progress\n", name
);
183 return DIV_ROUND_CLOSEST(ref_freq
<< 1, divider
+ 1);
186 int vlv_get_cck_clock_hpll(struct drm_i915_private
*dev_priv
,
187 const char *name
, u32 reg
)
191 vlv_cck_get(dev_priv
);
193 if (dev_priv
->hpll_freq
== 0)
194 dev_priv
->hpll_freq
= vlv_get_hpll_vco(dev_priv
);
196 hpll
= vlv_get_cck_clock(dev_priv
, name
, reg
, dev_priv
->hpll_freq
);
198 vlv_cck_put(dev_priv
);
203 static void intel_update_czclk(struct drm_i915_private
*dev_priv
)
205 if (!(IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)))
208 dev_priv
->czclk_freq
= vlv_get_cck_clock_hpll(dev_priv
, "czclk",
209 CCK_CZ_CLOCK_CONTROL
);
211 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv
->czclk_freq
);
214 static inline u32
/* units of 100MHz */
215 intel_fdi_link_freq(struct drm_i915_private
*dev_priv
,
216 const struct intel_crtc_state
*pipe_config
)
218 if (HAS_DDI(dev_priv
))
219 return pipe_config
->port_clock
; /* SPLL */
221 return dev_priv
->fdi_pll_freq
;
224 static const struct intel_limit intel_limits_i8xx_dac
= {
225 .dot
= { .min
= 25000, .max
= 350000 },
226 .vco
= { .min
= 908000, .max
= 1512000 },
227 .n
= { .min
= 2, .max
= 16 },
228 .m
= { .min
= 96, .max
= 140 },
229 .m1
= { .min
= 18, .max
= 26 },
230 .m2
= { .min
= 6, .max
= 16 },
231 .p
= { .min
= 4, .max
= 128 },
232 .p1
= { .min
= 2, .max
= 33 },
233 .p2
= { .dot_limit
= 165000,
234 .p2_slow
= 4, .p2_fast
= 2 },
237 static const struct intel_limit intel_limits_i8xx_dvo
= {
238 .dot
= { .min
= 25000, .max
= 350000 },
239 .vco
= { .min
= 908000, .max
= 1512000 },
240 .n
= { .min
= 2, .max
= 16 },
241 .m
= { .min
= 96, .max
= 140 },
242 .m1
= { .min
= 18, .max
= 26 },
243 .m2
= { .min
= 6, .max
= 16 },
244 .p
= { .min
= 4, .max
= 128 },
245 .p1
= { .min
= 2, .max
= 33 },
246 .p2
= { .dot_limit
= 165000,
247 .p2_slow
= 4, .p2_fast
= 4 },
250 static const struct intel_limit intel_limits_i8xx_lvds
= {
251 .dot
= { .min
= 25000, .max
= 350000 },
252 .vco
= { .min
= 908000, .max
= 1512000 },
253 .n
= { .min
= 2, .max
= 16 },
254 .m
= { .min
= 96, .max
= 140 },
255 .m1
= { .min
= 18, .max
= 26 },
256 .m2
= { .min
= 6, .max
= 16 },
257 .p
= { .min
= 4, .max
= 128 },
258 .p1
= { .min
= 1, .max
= 6 },
259 .p2
= { .dot_limit
= 165000,
260 .p2_slow
= 14, .p2_fast
= 7 },
263 static const struct intel_limit intel_limits_i9xx_sdvo
= {
264 .dot
= { .min
= 20000, .max
= 400000 },
265 .vco
= { .min
= 1400000, .max
= 2800000 },
266 .n
= { .min
= 1, .max
= 6 },
267 .m
= { .min
= 70, .max
= 120 },
268 .m1
= { .min
= 8, .max
= 18 },
269 .m2
= { .min
= 3, .max
= 7 },
270 .p
= { .min
= 5, .max
= 80 },
271 .p1
= { .min
= 1, .max
= 8 },
272 .p2
= { .dot_limit
= 200000,
273 .p2_slow
= 10, .p2_fast
= 5 },
276 static const struct intel_limit intel_limits_i9xx_lvds
= {
277 .dot
= { .min
= 20000, .max
= 400000 },
278 .vco
= { .min
= 1400000, .max
= 2800000 },
279 .n
= { .min
= 1, .max
= 6 },
280 .m
= { .min
= 70, .max
= 120 },
281 .m1
= { .min
= 8, .max
= 18 },
282 .m2
= { .min
= 3, .max
= 7 },
283 .p
= { .min
= 7, .max
= 98 },
284 .p1
= { .min
= 1, .max
= 8 },
285 .p2
= { .dot_limit
= 112000,
286 .p2_slow
= 14, .p2_fast
= 7 },
290 static const struct intel_limit intel_limits_g4x_sdvo
= {
291 .dot
= { .min
= 25000, .max
= 270000 },
292 .vco
= { .min
= 1750000, .max
= 3500000},
293 .n
= { .min
= 1, .max
= 4 },
294 .m
= { .min
= 104, .max
= 138 },
295 .m1
= { .min
= 17, .max
= 23 },
296 .m2
= { .min
= 5, .max
= 11 },
297 .p
= { .min
= 10, .max
= 30 },
298 .p1
= { .min
= 1, .max
= 3},
299 .p2
= { .dot_limit
= 270000,
305 static const struct intel_limit intel_limits_g4x_hdmi
= {
306 .dot
= { .min
= 22000, .max
= 400000 },
307 .vco
= { .min
= 1750000, .max
= 3500000},
308 .n
= { .min
= 1, .max
= 4 },
309 .m
= { .min
= 104, .max
= 138 },
310 .m1
= { .min
= 16, .max
= 23 },
311 .m2
= { .min
= 5, .max
= 11 },
312 .p
= { .min
= 5, .max
= 80 },
313 .p1
= { .min
= 1, .max
= 8},
314 .p2
= { .dot_limit
= 165000,
315 .p2_slow
= 10, .p2_fast
= 5 },
318 static const struct intel_limit intel_limits_g4x_single_channel_lvds
= {
319 .dot
= { .min
= 20000, .max
= 115000 },
320 .vco
= { .min
= 1750000, .max
= 3500000 },
321 .n
= { .min
= 1, .max
= 3 },
322 .m
= { .min
= 104, .max
= 138 },
323 .m1
= { .min
= 17, .max
= 23 },
324 .m2
= { .min
= 5, .max
= 11 },
325 .p
= { .min
= 28, .max
= 112 },
326 .p1
= { .min
= 2, .max
= 8 },
327 .p2
= { .dot_limit
= 0,
328 .p2_slow
= 14, .p2_fast
= 14
332 static const struct intel_limit intel_limits_g4x_dual_channel_lvds
= {
333 .dot
= { .min
= 80000, .max
= 224000 },
334 .vco
= { .min
= 1750000, .max
= 3500000 },
335 .n
= { .min
= 1, .max
= 3 },
336 .m
= { .min
= 104, .max
= 138 },
337 .m1
= { .min
= 17, .max
= 23 },
338 .m2
= { .min
= 5, .max
= 11 },
339 .p
= { .min
= 14, .max
= 42 },
340 .p1
= { .min
= 2, .max
= 6 },
341 .p2
= { .dot_limit
= 0,
342 .p2_slow
= 7, .p2_fast
= 7
346 static const struct intel_limit intel_limits_pineview_sdvo
= {
347 .dot
= { .min
= 20000, .max
= 400000},
348 .vco
= { .min
= 1700000, .max
= 3500000 },
349 /* Pineview's Ncounter is a ring counter */
350 .n
= { .min
= 3, .max
= 6 },
351 .m
= { .min
= 2, .max
= 256 },
352 /* Pineview only has one combined m divider, which we treat as m2. */
353 .m1
= { .min
= 0, .max
= 0 },
354 .m2
= { .min
= 0, .max
= 254 },
355 .p
= { .min
= 5, .max
= 80 },
356 .p1
= { .min
= 1, .max
= 8 },
357 .p2
= { .dot_limit
= 200000,
358 .p2_slow
= 10, .p2_fast
= 5 },
361 static const struct intel_limit intel_limits_pineview_lvds
= {
362 .dot
= { .min
= 20000, .max
= 400000 },
363 .vco
= { .min
= 1700000, .max
= 3500000 },
364 .n
= { .min
= 3, .max
= 6 },
365 .m
= { .min
= 2, .max
= 256 },
366 .m1
= { .min
= 0, .max
= 0 },
367 .m2
= { .min
= 0, .max
= 254 },
368 .p
= { .min
= 7, .max
= 112 },
369 .p1
= { .min
= 1, .max
= 8 },
370 .p2
= { .dot_limit
= 112000,
371 .p2_slow
= 14, .p2_fast
= 14 },
374 /* Ironlake / Sandybridge
376 * We calculate clock using (register_value + 2) for N/M1/M2, so here
377 * the range value for them is (actual_value - 2).
379 static const struct intel_limit intel_limits_ironlake_dac
= {
380 .dot
= { .min
= 25000, .max
= 350000 },
381 .vco
= { .min
= 1760000, .max
= 3510000 },
382 .n
= { .min
= 1, .max
= 5 },
383 .m
= { .min
= 79, .max
= 127 },
384 .m1
= { .min
= 12, .max
= 22 },
385 .m2
= { .min
= 5, .max
= 9 },
386 .p
= { .min
= 5, .max
= 80 },
387 .p1
= { .min
= 1, .max
= 8 },
388 .p2
= { .dot_limit
= 225000,
389 .p2_slow
= 10, .p2_fast
= 5 },
392 static const struct intel_limit intel_limits_ironlake_single_lvds
= {
393 .dot
= { .min
= 25000, .max
= 350000 },
394 .vco
= { .min
= 1760000, .max
= 3510000 },
395 .n
= { .min
= 1, .max
= 3 },
396 .m
= { .min
= 79, .max
= 118 },
397 .m1
= { .min
= 12, .max
= 22 },
398 .m2
= { .min
= 5, .max
= 9 },
399 .p
= { .min
= 28, .max
= 112 },
400 .p1
= { .min
= 2, .max
= 8 },
401 .p2
= { .dot_limit
= 225000,
402 .p2_slow
= 14, .p2_fast
= 14 },
405 static const struct intel_limit intel_limits_ironlake_dual_lvds
= {
406 .dot
= { .min
= 25000, .max
= 350000 },
407 .vco
= { .min
= 1760000, .max
= 3510000 },
408 .n
= { .min
= 1, .max
= 3 },
409 .m
= { .min
= 79, .max
= 127 },
410 .m1
= { .min
= 12, .max
= 22 },
411 .m2
= { .min
= 5, .max
= 9 },
412 .p
= { .min
= 14, .max
= 56 },
413 .p1
= { .min
= 2, .max
= 8 },
414 .p2
= { .dot_limit
= 225000,
415 .p2_slow
= 7, .p2_fast
= 7 },
418 /* LVDS 100mhz refclk limits. */
419 static const struct intel_limit intel_limits_ironlake_single_lvds_100m
= {
420 .dot
= { .min
= 25000, .max
= 350000 },
421 .vco
= { .min
= 1760000, .max
= 3510000 },
422 .n
= { .min
= 1, .max
= 2 },
423 .m
= { .min
= 79, .max
= 126 },
424 .m1
= { .min
= 12, .max
= 22 },
425 .m2
= { .min
= 5, .max
= 9 },
426 .p
= { .min
= 28, .max
= 112 },
427 .p1
= { .min
= 2, .max
= 8 },
428 .p2
= { .dot_limit
= 225000,
429 .p2_slow
= 14, .p2_fast
= 14 },
432 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m
= {
433 .dot
= { .min
= 25000, .max
= 350000 },
434 .vco
= { .min
= 1760000, .max
= 3510000 },
435 .n
= { .min
= 1, .max
= 3 },
436 .m
= { .min
= 79, .max
= 126 },
437 .m1
= { .min
= 12, .max
= 22 },
438 .m2
= { .min
= 5, .max
= 9 },
439 .p
= { .min
= 14, .max
= 42 },
440 .p1
= { .min
= 2, .max
= 6 },
441 .p2
= { .dot_limit
= 225000,
442 .p2_slow
= 7, .p2_fast
= 7 },
445 static const struct intel_limit intel_limits_vlv
= {
447 * These are the data rate limits (measured in fast clocks)
448 * since those are the strictest limits we have. The fast
449 * clock and actual rate limits are more relaxed, so checking
450 * them would make no difference.
452 .dot
= { .min
= 25000 * 5, .max
= 270000 * 5 },
453 .vco
= { .min
= 4000000, .max
= 6000000 },
454 .n
= { .min
= 1, .max
= 7 },
455 .m1
= { .min
= 2, .max
= 3 },
456 .m2
= { .min
= 11, .max
= 156 },
457 .p1
= { .min
= 2, .max
= 3 },
458 .p2
= { .p2_slow
= 2, .p2_fast
= 20 }, /* slow=min, fast=max */
461 static const struct intel_limit intel_limits_chv
= {
463 * These are the data rate limits (measured in fast clocks)
464 * since those are the strictest limits we have. The fast
465 * clock and actual rate limits are more relaxed, so checking
466 * them would make no difference.
468 .dot
= { .min
= 25000 * 5, .max
= 540000 * 5},
469 .vco
= { .min
= 4800000, .max
= 6480000 },
470 .n
= { .min
= 1, .max
= 1 },
471 .m1
= { .min
= 2, .max
= 2 },
472 .m2
= { .min
= 24 << 22, .max
= 175 << 22 },
473 .p1
= { .min
= 2, .max
= 4 },
474 .p2
= { .p2_slow
= 1, .p2_fast
= 14 },
477 static const struct intel_limit intel_limits_bxt
= {
478 /* FIXME: find real dot limits */
479 .dot
= { .min
= 0, .max
= INT_MAX
},
480 .vco
= { .min
= 4800000, .max
= 6700000 },
481 .n
= { .min
= 1, .max
= 1 },
482 .m1
= { .min
= 2, .max
= 2 },
483 /* FIXME: find real m2 limits */
484 .m2
= { .min
= 2 << 22, .max
= 255 << 22 },
485 .p1
= { .min
= 2, .max
= 4 },
486 .p2
= { .p2_slow
= 1, .p2_fast
= 20 },
489 /* WA Display #0827: Gen9:all */
491 skl_wa_827(struct drm_i915_private
*dev_priv
, int pipe
, bool enable
)
494 I915_WRITE(CLKGATE_DIS_PSL(pipe
),
495 I915_READ(CLKGATE_DIS_PSL(pipe
)) |
496 DUPS1_GATING_DIS
| DUPS2_GATING_DIS
);
498 I915_WRITE(CLKGATE_DIS_PSL(pipe
),
499 I915_READ(CLKGATE_DIS_PSL(pipe
)) &
500 ~(DUPS1_GATING_DIS
| DUPS2_GATING_DIS
));
503 /* Wa_2006604312:icl */
505 icl_wa_scalerclkgating(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
509 I915_WRITE(CLKGATE_DIS_PSL(pipe
),
510 I915_READ(CLKGATE_DIS_PSL(pipe
)) | DPFR_GATING_DIS
);
512 I915_WRITE(CLKGATE_DIS_PSL(pipe
),
513 I915_READ(CLKGATE_DIS_PSL(pipe
)) & ~DPFR_GATING_DIS
);
517 needs_modeset(const struct drm_crtc_state
*state
)
519 return drm_atomic_crtc_needs_modeset(state
);
523 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
524 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
525 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
526 * The helpers' return value is the rate of the clock that is fed to the
527 * display engine's pipe which can be the above fast dot clock rate or a
528 * divided-down version of it.
530 /* m1 is reserved as 0 in Pineview, n is a ring counter */
531 static int pnv_calc_dpll_params(int refclk
, struct dpll
*clock
)
533 clock
->m
= clock
->m2
+ 2;
534 clock
->p
= clock
->p1
* clock
->p2
;
535 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
537 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
538 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
543 static u32
i9xx_dpll_compute_m(struct dpll
*dpll
)
545 return 5 * (dpll
->m1
+ 2) + (dpll
->m2
+ 2);
548 static int i9xx_calc_dpll_params(int refclk
, struct dpll
*clock
)
550 clock
->m
= i9xx_dpll_compute_m(clock
);
551 clock
->p
= clock
->p1
* clock
->p2
;
552 if (WARN_ON(clock
->n
+ 2 == 0 || clock
->p
== 0))
554 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
+ 2);
555 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
560 static int vlv_calc_dpll_params(int refclk
, struct dpll
*clock
)
562 clock
->m
= clock
->m1
* clock
->m2
;
563 clock
->p
= clock
->p1
* clock
->p2
;
564 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
566 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
567 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
569 return clock
->dot
/ 5;
572 int chv_calc_dpll_params(int refclk
, struct dpll
*clock
)
574 clock
->m
= clock
->m1
* clock
->m2
;
575 clock
->p
= clock
->p1
* clock
->p2
;
576 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
578 clock
->vco
= DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk
, clock
->m
),
580 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
582 return clock
->dot
/ 5;
585 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
588 * Returns whether the given set of divisors are valid for a given refclk with
589 * the given connectors.
591 static bool intel_PLL_is_valid(struct drm_i915_private
*dev_priv
,
592 const struct intel_limit
*limit
,
593 const struct dpll
*clock
)
595 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
596 INTELPllInvalid("n out of range\n");
597 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
598 INTELPllInvalid("p1 out of range\n");
599 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
600 INTELPllInvalid("m2 out of range\n");
601 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
602 INTELPllInvalid("m1 out of range\n");
604 if (!IS_PINEVIEW(dev_priv
) && !IS_VALLEYVIEW(dev_priv
) &&
605 !IS_CHERRYVIEW(dev_priv
) && !IS_GEN9_LP(dev_priv
))
606 if (clock
->m1
<= clock
->m2
)
607 INTELPllInvalid("m1 <= m2\n");
609 if (!IS_VALLEYVIEW(dev_priv
) && !IS_CHERRYVIEW(dev_priv
) &&
610 !IS_GEN9_LP(dev_priv
)) {
611 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
612 INTELPllInvalid("p out of range\n");
613 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
614 INTELPllInvalid("m out of range\n");
617 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
618 INTELPllInvalid("vco out of range\n");
619 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
620 * connector, etc., rather than just a single range.
622 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
623 INTELPllInvalid("dot out of range\n");
629 i9xx_select_p2_div(const struct intel_limit
*limit
,
630 const struct intel_crtc_state
*crtc_state
,
633 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->base
.crtc
->dev
);
635 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
637 * For LVDS just rely on its current settings for dual-channel.
638 * We haven't figured out how to reliably set up different
639 * single/dual channel state, if we even can.
641 if (intel_is_dual_link_lvds(dev_priv
))
642 return limit
->p2
.p2_fast
;
644 return limit
->p2
.p2_slow
;
646 if (target
< limit
->p2
.dot_limit
)
647 return limit
->p2
.p2_slow
;
649 return limit
->p2
.p2_fast
;
654 * Returns a set of divisors for the desired target clock with the given
655 * refclk, or FALSE. The returned values represent the clock equation:
656 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
658 * Target and reference clocks are specified in kHz.
660 * If match_clock is provided, then best_clock P divider must match the P
661 * divider from @match_clock used for LVDS downclocking.
664 i9xx_find_best_dpll(const struct intel_limit
*limit
,
665 struct intel_crtc_state
*crtc_state
,
666 int target
, int refclk
, struct dpll
*match_clock
,
667 struct dpll
*best_clock
)
669 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
673 memset(best_clock
, 0, sizeof(*best_clock
));
675 clock
.p2
= i9xx_select_p2_div(limit
, crtc_state
, target
);
677 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
679 for (clock
.m2
= limit
->m2
.min
;
680 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
681 if (clock
.m2
>= clock
.m1
)
683 for (clock
.n
= limit
->n
.min
;
684 clock
.n
<= limit
->n
.max
; clock
.n
++) {
685 for (clock
.p1
= limit
->p1
.min
;
686 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
689 i9xx_calc_dpll_params(refclk
, &clock
);
690 if (!intel_PLL_is_valid(to_i915(dev
),
695 clock
.p
!= match_clock
->p
)
698 this_err
= abs(clock
.dot
- target
);
699 if (this_err
< err
) {
708 return (err
!= target
);
712 * Returns a set of divisors for the desired target clock with the given
713 * refclk, or FALSE. The returned values represent the clock equation:
714 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
716 * Target and reference clocks are specified in kHz.
718 * If match_clock is provided, then best_clock P divider must match the P
719 * divider from @match_clock used for LVDS downclocking.
722 pnv_find_best_dpll(const struct intel_limit
*limit
,
723 struct intel_crtc_state
*crtc_state
,
724 int target
, int refclk
, struct dpll
*match_clock
,
725 struct dpll
*best_clock
)
727 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
731 memset(best_clock
, 0, sizeof(*best_clock
));
733 clock
.p2
= i9xx_select_p2_div(limit
, crtc_state
, target
);
735 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
737 for (clock
.m2
= limit
->m2
.min
;
738 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
739 for (clock
.n
= limit
->n
.min
;
740 clock
.n
<= limit
->n
.max
; clock
.n
++) {
741 for (clock
.p1
= limit
->p1
.min
;
742 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
745 pnv_calc_dpll_params(refclk
, &clock
);
746 if (!intel_PLL_is_valid(to_i915(dev
),
751 clock
.p
!= match_clock
->p
)
754 this_err
= abs(clock
.dot
- target
);
755 if (this_err
< err
) {
764 return (err
!= target
);
768 * Returns a set of divisors for the desired target clock with the given
769 * refclk, or FALSE. The returned values represent the clock equation:
770 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
772 * Target and reference clocks are specified in kHz.
774 * If match_clock is provided, then best_clock P divider must match the P
775 * divider from @match_clock used for LVDS downclocking.
778 g4x_find_best_dpll(const struct intel_limit
*limit
,
779 struct intel_crtc_state
*crtc_state
,
780 int target
, int refclk
, struct dpll
*match_clock
,
781 struct dpll
*best_clock
)
783 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
787 /* approximately equals target * 0.00585 */
788 int err_most
= (target
>> 8) + (target
>> 9);
790 memset(best_clock
, 0, sizeof(*best_clock
));
792 clock
.p2
= i9xx_select_p2_div(limit
, crtc_state
, target
);
794 max_n
= limit
->n
.max
;
795 /* based on hardware requirement, prefer smaller n to precision */
796 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
797 /* based on hardware requirement, prefere larger m1,m2 */
798 for (clock
.m1
= limit
->m1
.max
;
799 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
800 for (clock
.m2
= limit
->m2
.max
;
801 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
802 for (clock
.p1
= limit
->p1
.max
;
803 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
806 i9xx_calc_dpll_params(refclk
, &clock
);
807 if (!intel_PLL_is_valid(to_i915(dev
),
812 this_err
= abs(clock
.dot
- target
);
813 if (this_err
< err_most
) {
827 * Check if the calculated PLL configuration is more optimal compared to the
828 * best configuration and error found so far. Return the calculated error.
830 static bool vlv_PLL_is_optimal(struct drm_device
*dev
, int target_freq
,
831 const struct dpll
*calculated_clock
,
832 const struct dpll
*best_clock
,
833 unsigned int best_error_ppm
,
834 unsigned int *error_ppm
)
837 * For CHV ignore the error and consider only the P value.
838 * Prefer a bigger P value based on HW requirements.
840 if (IS_CHERRYVIEW(to_i915(dev
))) {
843 return calculated_clock
->p
> best_clock
->p
;
846 if (WARN_ON_ONCE(!target_freq
))
849 *error_ppm
= div_u64(1000000ULL *
850 abs(target_freq
- calculated_clock
->dot
),
853 * Prefer a better P value over a better (smaller) error if the error
854 * is small. Ensure this preference for future configurations too by
855 * setting the error to 0.
857 if (*error_ppm
< 100 && calculated_clock
->p
> best_clock
->p
) {
863 return *error_ppm
+ 10 < best_error_ppm
;
867 * Returns a set of divisors for the desired target clock with the given
868 * refclk, or FALSE. The returned values represent the clock equation:
869 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
872 vlv_find_best_dpll(const struct intel_limit
*limit
,
873 struct intel_crtc_state
*crtc_state
,
874 int target
, int refclk
, struct dpll
*match_clock
,
875 struct dpll
*best_clock
)
877 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
878 struct drm_device
*dev
= crtc
->base
.dev
;
880 unsigned int bestppm
= 1000000;
881 /* min update 19.2 MHz */
882 int max_n
= min(limit
->n
.max
, refclk
/ 19200);
885 target
*= 5; /* fast clock */
887 memset(best_clock
, 0, sizeof(*best_clock
));
889 /* based on hardware requirement, prefer smaller n to precision */
890 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
891 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
892 for (clock
.p2
= limit
->p2
.p2_fast
; clock
.p2
>= limit
->p2
.p2_slow
;
893 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
894 clock
.p
= clock
.p1
* clock
.p2
;
895 /* based on hardware requirement, prefer bigger m1,m2 values */
896 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
; clock
.m1
++) {
899 clock
.m2
= DIV_ROUND_CLOSEST(target
* clock
.p
* clock
.n
,
902 vlv_calc_dpll_params(refclk
, &clock
);
904 if (!intel_PLL_is_valid(to_i915(dev
),
909 if (!vlv_PLL_is_optimal(dev
, target
,
927 * Returns a set of divisors for the desired target clock with the given
928 * refclk, or FALSE. The returned values represent the clock equation:
929 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
932 chv_find_best_dpll(const struct intel_limit
*limit
,
933 struct intel_crtc_state
*crtc_state
,
934 int target
, int refclk
, struct dpll
*match_clock
,
935 struct dpll
*best_clock
)
937 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
938 struct drm_device
*dev
= crtc
->base
.dev
;
939 unsigned int best_error_ppm
;
944 memset(best_clock
, 0, sizeof(*best_clock
));
945 best_error_ppm
= 1000000;
948 * Based on hardware doc, the n always set to 1, and m1 always
949 * set to 2. If requires to support 200Mhz refclk, we need to
950 * revisit this because n may not 1 anymore.
952 clock
.n
= 1, clock
.m1
= 2;
953 target
*= 5; /* fast clock */
955 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
956 for (clock
.p2
= limit
->p2
.p2_fast
;
957 clock
.p2
>= limit
->p2
.p2_slow
;
958 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
959 unsigned int error_ppm
;
961 clock
.p
= clock
.p1
* clock
.p2
;
963 m2
= DIV_ROUND_CLOSEST_ULL(mul_u32_u32(target
, clock
.p
* clock
.n
) << 22,
966 if (m2
> INT_MAX
/clock
.m1
)
971 chv_calc_dpll_params(refclk
, &clock
);
973 if (!intel_PLL_is_valid(to_i915(dev
), limit
, &clock
))
976 if (!vlv_PLL_is_optimal(dev
, target
, &clock
, best_clock
,
977 best_error_ppm
, &error_ppm
))
981 best_error_ppm
= error_ppm
;
989 bool bxt_find_best_dpll(struct intel_crtc_state
*crtc_state
,
990 struct dpll
*best_clock
)
993 const struct intel_limit
*limit
= &intel_limits_bxt
;
995 return chv_find_best_dpll(limit
, crtc_state
,
996 crtc_state
->port_clock
, refclk
,
1000 bool intel_crtc_active(struct intel_crtc
*crtc
)
1002 /* Be paranoid as we can arrive here with only partial
1003 * state retrieved from the hardware during setup.
1005 * We can ditch the adjusted_mode.crtc_clock check as soon
1006 * as Haswell has gained clock readout/fastboot support.
1008 * We can ditch the crtc->primary->state->fb check as soon as we can
1009 * properly reconstruct framebuffers.
1011 * FIXME: The intel_crtc->active here should be switched to
1012 * crtc->state->active once we have proper CRTC states wired up
1015 return crtc
->active
&& crtc
->base
.primary
->state
->fb
&&
1016 crtc
->config
->base
.adjusted_mode
.crtc_clock
;
1019 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
1022 struct intel_crtc
*crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
1024 return crtc
->config
->cpu_transcoder
;
1027 static bool pipe_scanline_is_moving(struct drm_i915_private
*dev_priv
,
1030 i915_reg_t reg
= PIPEDSL(pipe
);
1034 if (IS_GEN(dev_priv
, 2))
1035 line_mask
= DSL_LINEMASK_GEN2
;
1037 line_mask
= DSL_LINEMASK_GEN3
;
1039 line1
= I915_READ(reg
) & line_mask
;
1041 line2
= I915_READ(reg
) & line_mask
;
1043 return line1
!= line2
;
1046 static void wait_for_pipe_scanline_moving(struct intel_crtc
*crtc
, bool state
)
1048 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1049 enum pipe pipe
= crtc
->pipe
;
1051 /* Wait for the display line to settle/start moving */
1052 if (wait_for(pipe_scanline_is_moving(dev_priv
, pipe
) == state
, 100))
1053 DRM_ERROR("pipe %c scanline %s wait timed out\n",
1054 pipe_name(pipe
), onoff(state
));
1057 static void intel_wait_for_pipe_scanline_stopped(struct intel_crtc
*crtc
)
1059 wait_for_pipe_scanline_moving(crtc
, false);
1062 static void intel_wait_for_pipe_scanline_moving(struct intel_crtc
*crtc
)
1064 wait_for_pipe_scanline_moving(crtc
, true);
1068 intel_wait_for_pipe_off(const struct intel_crtc_state
*old_crtc_state
)
1070 struct intel_crtc
*crtc
= to_intel_crtc(old_crtc_state
->base
.crtc
);
1071 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1073 if (INTEL_GEN(dev_priv
) >= 4) {
1074 enum transcoder cpu_transcoder
= old_crtc_state
->cpu_transcoder
;
1075 i915_reg_t reg
= PIPECONF(cpu_transcoder
);
1077 /* Wait for the Pipe State to go off */
1078 if (intel_wait_for_register(&dev_priv
->uncore
,
1079 reg
, I965_PIPECONF_ACTIVE
, 0,
1081 WARN(1, "pipe_off wait timed out\n");
1083 intel_wait_for_pipe_scanline_stopped(crtc
);
1087 /* Only for pre-ILK configs */
1088 void assert_pll(struct drm_i915_private
*dev_priv
,
1089 enum pipe pipe
, bool state
)
1094 val
= I915_READ(DPLL(pipe
));
1095 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1096 I915_STATE_WARN(cur_state
!= state
,
1097 "PLL state assertion failure (expected %s, current %s)\n",
1098 onoff(state
), onoff(cur_state
));
1101 /* XXX: the dsi pll is shared between MIPI DSI ports */
1102 void assert_dsi_pll(struct drm_i915_private
*dev_priv
, bool state
)
1107 vlv_cck_get(dev_priv
);
1108 val
= vlv_cck_read(dev_priv
, CCK_REG_DSI_PLL_CONTROL
);
1109 vlv_cck_put(dev_priv
);
1111 cur_state
= val
& DSI_PLL_VCO_EN
;
1112 I915_STATE_WARN(cur_state
!= state
,
1113 "DSI PLL state assertion failure (expected %s, current %s)\n",
1114 onoff(state
), onoff(cur_state
));
1117 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
1118 enum pipe pipe
, bool state
)
1121 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1124 if (HAS_DDI(dev_priv
)) {
1125 /* DDI does not have a specific FDI_TX register */
1126 u32 val
= I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder
));
1127 cur_state
= !!(val
& TRANS_DDI_FUNC_ENABLE
);
1129 u32 val
= I915_READ(FDI_TX_CTL(pipe
));
1130 cur_state
= !!(val
& FDI_TX_ENABLE
);
1132 I915_STATE_WARN(cur_state
!= state
,
1133 "FDI TX state assertion failure (expected %s, current %s)\n",
1134 onoff(state
), onoff(cur_state
));
1136 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1137 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1139 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
1140 enum pipe pipe
, bool state
)
1145 val
= I915_READ(FDI_RX_CTL(pipe
));
1146 cur_state
= !!(val
& FDI_RX_ENABLE
);
1147 I915_STATE_WARN(cur_state
!= state
,
1148 "FDI RX state assertion failure (expected %s, current %s)\n",
1149 onoff(state
), onoff(cur_state
));
1151 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1152 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1154 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
1159 /* ILK FDI PLL is always enabled */
1160 if (IS_GEN(dev_priv
, 5))
1163 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1164 if (HAS_DDI(dev_priv
))
1167 val
= I915_READ(FDI_TX_CTL(pipe
));
1168 I915_STATE_WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1171 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
1172 enum pipe pipe
, bool state
)
1177 val
= I915_READ(FDI_RX_CTL(pipe
));
1178 cur_state
= !!(val
& FDI_RX_PLL_ENABLE
);
1179 I915_STATE_WARN(cur_state
!= state
,
1180 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1181 onoff(state
), onoff(cur_state
));
1184 void assert_panel_unlocked(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1188 enum pipe panel_pipe
= INVALID_PIPE
;
1191 if (WARN_ON(HAS_DDI(dev_priv
)))
1194 if (HAS_PCH_SPLIT(dev_priv
)) {
1197 pp_reg
= PP_CONTROL(0);
1198 port_sel
= I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK
;
1201 case PANEL_PORT_SELECT_LVDS
:
1202 intel_lvds_port_enabled(dev_priv
, PCH_LVDS
, &panel_pipe
);
1204 case PANEL_PORT_SELECT_DPA
:
1205 intel_dp_port_enabled(dev_priv
, DP_A
, PORT_A
, &panel_pipe
);
1207 case PANEL_PORT_SELECT_DPC
:
1208 intel_dp_port_enabled(dev_priv
, PCH_DP_C
, PORT_C
, &panel_pipe
);
1210 case PANEL_PORT_SELECT_DPD
:
1211 intel_dp_port_enabled(dev_priv
, PCH_DP_D
, PORT_D
, &panel_pipe
);
1214 MISSING_CASE(port_sel
);
1217 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
1218 /* presumably write lock depends on pipe, not port select */
1219 pp_reg
= PP_CONTROL(pipe
);
1224 pp_reg
= PP_CONTROL(0);
1225 port_sel
= I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK
;
1227 WARN_ON(port_sel
!= PANEL_PORT_SELECT_LVDS
);
1228 intel_lvds_port_enabled(dev_priv
, LVDS
, &panel_pipe
);
1231 val
= I915_READ(pp_reg
);
1232 if (!(val
& PANEL_POWER_ON
) ||
1233 ((val
& PANEL_UNLOCK_MASK
) == PANEL_UNLOCK_REGS
))
1236 I915_STATE_WARN(panel_pipe
== pipe
&& locked
,
1237 "panel assertion failure, pipe %c regs locked\n",
1241 void assert_pipe(struct drm_i915_private
*dev_priv
,
1242 enum pipe pipe
, bool state
)
1245 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1247 enum intel_display_power_domain power_domain
;
1248 intel_wakeref_t wakeref
;
1250 /* we keep both pipes enabled on 830 */
1251 if (IS_I830(dev_priv
))
1254 power_domain
= POWER_DOMAIN_TRANSCODER(cpu_transcoder
);
1255 wakeref
= intel_display_power_get_if_enabled(dev_priv
, power_domain
);
1257 u32 val
= I915_READ(PIPECONF(cpu_transcoder
));
1258 cur_state
= !!(val
& PIPECONF_ENABLE
);
1260 intel_display_power_put(dev_priv
, power_domain
, wakeref
);
1265 I915_STATE_WARN(cur_state
!= state
,
1266 "pipe %c assertion failure (expected %s, current %s)\n",
1267 pipe_name(pipe
), onoff(state
), onoff(cur_state
));
1270 static void assert_plane(struct intel_plane
*plane
, bool state
)
1275 cur_state
= plane
->get_hw_state(plane
, &pipe
);
1277 I915_STATE_WARN(cur_state
!= state
,
1278 "%s assertion failure (expected %s, current %s)\n",
1279 plane
->base
.name
, onoff(state
), onoff(cur_state
));
1282 #define assert_plane_enabled(p) assert_plane(p, true)
1283 #define assert_plane_disabled(p) assert_plane(p, false)
1285 static void assert_planes_disabled(struct intel_crtc
*crtc
)
1287 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1288 struct intel_plane
*plane
;
1290 for_each_intel_plane_on_crtc(&dev_priv
->drm
, crtc
, plane
)
1291 assert_plane_disabled(plane
);
1294 static void assert_vblank_disabled(struct drm_crtc
*crtc
)
1296 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc
) == 0))
1297 drm_crtc_vblank_put(crtc
);
1300 void assert_pch_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1306 val
= I915_READ(PCH_TRANSCONF(pipe
));
1307 enabled
= !!(val
& TRANS_ENABLE
);
1308 I915_STATE_WARN(enabled
,
1309 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1313 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1314 enum pipe pipe
, enum port port
,
1317 enum pipe port_pipe
;
1320 state
= intel_dp_port_enabled(dev_priv
, dp_reg
, port
, &port_pipe
);
1322 I915_STATE_WARN(state
&& port_pipe
== pipe
,
1323 "PCH DP %c enabled on transcoder %c, should be disabled\n",
1324 port_name(port
), pipe_name(pipe
));
1326 I915_STATE_WARN(HAS_PCH_IBX(dev_priv
) && !state
&& port_pipe
== PIPE_B
,
1327 "IBX PCH DP %c still using transcoder B\n",
1331 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1332 enum pipe pipe
, enum port port
,
1333 i915_reg_t hdmi_reg
)
1335 enum pipe port_pipe
;
1338 state
= intel_sdvo_port_enabled(dev_priv
, hdmi_reg
, &port_pipe
);
1340 I915_STATE_WARN(state
&& port_pipe
== pipe
,
1341 "PCH HDMI %c enabled on transcoder %c, should be disabled\n",
1342 port_name(port
), pipe_name(pipe
));
1344 I915_STATE_WARN(HAS_PCH_IBX(dev_priv
) && !state
&& port_pipe
== PIPE_B
,
1345 "IBX PCH HDMI %c still using transcoder B\n",
1349 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1352 enum pipe port_pipe
;
1354 assert_pch_dp_disabled(dev_priv
, pipe
, PORT_B
, PCH_DP_B
);
1355 assert_pch_dp_disabled(dev_priv
, pipe
, PORT_C
, PCH_DP_C
);
1356 assert_pch_dp_disabled(dev_priv
, pipe
, PORT_D
, PCH_DP_D
);
1358 I915_STATE_WARN(intel_crt_port_enabled(dev_priv
, PCH_ADPA
, &port_pipe
) &&
1360 "PCH VGA enabled on transcoder %c, should be disabled\n",
1363 I915_STATE_WARN(intel_lvds_port_enabled(dev_priv
, PCH_LVDS
, &port_pipe
) &&
1365 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1368 /* PCH SDVOB multiplex with HDMIB */
1369 assert_pch_hdmi_disabled(dev_priv
, pipe
, PORT_B
, PCH_HDMIB
);
1370 assert_pch_hdmi_disabled(dev_priv
, pipe
, PORT_C
, PCH_HDMIC
);
1371 assert_pch_hdmi_disabled(dev_priv
, pipe
, PORT_D
, PCH_HDMID
);
1374 static void _vlv_enable_pll(struct intel_crtc
*crtc
,
1375 const struct intel_crtc_state
*pipe_config
)
1377 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1378 enum pipe pipe
= crtc
->pipe
;
1380 I915_WRITE(DPLL(pipe
), pipe_config
->dpll_hw_state
.dpll
);
1381 POSTING_READ(DPLL(pipe
));
1384 if (intel_wait_for_register(&dev_priv
->uncore
,
1389 DRM_ERROR("DPLL %d failed to lock\n", pipe
);
1392 static void vlv_enable_pll(struct intel_crtc
*crtc
,
1393 const struct intel_crtc_state
*pipe_config
)
1395 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1396 enum pipe pipe
= crtc
->pipe
;
1398 assert_pipe_disabled(dev_priv
, pipe
);
1400 /* PLL is protected by panel, make sure we can write it */
1401 assert_panel_unlocked(dev_priv
, pipe
);
1403 if (pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
)
1404 _vlv_enable_pll(crtc
, pipe_config
);
1406 I915_WRITE(DPLL_MD(pipe
), pipe_config
->dpll_hw_state
.dpll_md
);
1407 POSTING_READ(DPLL_MD(pipe
));
1411 static void _chv_enable_pll(struct intel_crtc
*crtc
,
1412 const struct intel_crtc_state
*pipe_config
)
1414 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1415 enum pipe pipe
= crtc
->pipe
;
1416 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1419 vlv_dpio_get(dev_priv
);
1421 /* Enable back the 10bit clock to display controller */
1422 tmp
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1423 tmp
|= DPIO_DCLKP_EN
;
1424 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), tmp
);
1426 vlv_dpio_put(dev_priv
);
1429 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1434 I915_WRITE(DPLL(pipe
), pipe_config
->dpll_hw_state
.dpll
);
1436 /* Check PLL is locked */
1437 if (intel_wait_for_register(&dev_priv
->uncore
,
1438 DPLL(pipe
), DPLL_LOCK_VLV
, DPLL_LOCK_VLV
,
1440 DRM_ERROR("PLL %d failed to lock\n", pipe
);
1443 static void chv_enable_pll(struct intel_crtc
*crtc
,
1444 const struct intel_crtc_state
*pipe_config
)
1446 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1447 enum pipe pipe
= crtc
->pipe
;
1449 assert_pipe_disabled(dev_priv
, pipe
);
1451 /* PLL is protected by panel, make sure we can write it */
1452 assert_panel_unlocked(dev_priv
, pipe
);
1454 if (pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
)
1455 _chv_enable_pll(crtc
, pipe_config
);
1457 if (pipe
!= PIPE_A
) {
1459 * WaPixelRepeatModeFixForC0:chv
1461 * DPLLCMD is AWOL. Use chicken bits to propagate
1462 * the value from DPLLBMD to either pipe B or C.
1464 I915_WRITE(CBR4_VLV
, CBR_DPLLBMD_PIPE(pipe
));
1465 I915_WRITE(DPLL_MD(PIPE_B
), pipe_config
->dpll_hw_state
.dpll_md
);
1466 I915_WRITE(CBR4_VLV
, 0);
1467 dev_priv
->chv_dpll_md
[pipe
] = pipe_config
->dpll_hw_state
.dpll_md
;
1470 * DPLLB VGA mode also seems to cause problems.
1471 * We should always have it disabled.
1473 WARN_ON((I915_READ(DPLL(PIPE_B
)) & DPLL_VGA_MODE_DIS
) == 0);
1475 I915_WRITE(DPLL_MD(pipe
), pipe_config
->dpll_hw_state
.dpll_md
);
1476 POSTING_READ(DPLL_MD(pipe
));
1480 static bool i9xx_has_pps(struct drm_i915_private
*dev_priv
)
1482 if (IS_I830(dev_priv
))
1485 return IS_PINEVIEW(dev_priv
) || IS_MOBILE(dev_priv
);
1488 static void i9xx_enable_pll(struct intel_crtc
*crtc
,
1489 const struct intel_crtc_state
*crtc_state
)
1491 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1492 i915_reg_t reg
= DPLL(crtc
->pipe
);
1493 u32 dpll
= crtc_state
->dpll_hw_state
.dpll
;
1496 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1498 /* PLL is protected by panel, make sure we can write it */
1499 if (i9xx_has_pps(dev_priv
))
1500 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1503 * Apparently we need to have VGA mode enabled prior to changing
1504 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1505 * dividers, even though the register value does change.
1507 I915_WRITE(reg
, dpll
& ~DPLL_VGA_MODE_DIS
);
1508 I915_WRITE(reg
, dpll
);
1510 /* Wait for the clocks to stabilize. */
1514 if (INTEL_GEN(dev_priv
) >= 4) {
1515 I915_WRITE(DPLL_MD(crtc
->pipe
),
1516 crtc_state
->dpll_hw_state
.dpll_md
);
1518 /* The pixel multiplier can only be updated once the
1519 * DPLL is enabled and the clocks are stable.
1521 * So write it again.
1523 I915_WRITE(reg
, dpll
);
1526 /* We do this three times for luck */
1527 for (i
= 0; i
< 3; i
++) {
1528 I915_WRITE(reg
, dpll
);
1530 udelay(150); /* wait for warmup */
1534 static void i9xx_disable_pll(const struct intel_crtc_state
*crtc_state
)
1536 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
1537 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1538 enum pipe pipe
= crtc
->pipe
;
1540 /* Don't disable pipe or pipe PLLs if needed */
1541 if (IS_I830(dev_priv
))
1544 /* Make sure the pipe isn't still relying on us */
1545 assert_pipe_disabled(dev_priv
, pipe
);
1547 I915_WRITE(DPLL(pipe
), DPLL_VGA_MODE_DIS
);
1548 POSTING_READ(DPLL(pipe
));
1551 static void vlv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1555 /* Make sure the pipe isn't still relying on us */
1556 assert_pipe_disabled(dev_priv
, pipe
);
1558 val
= DPLL_INTEGRATED_REF_CLK_VLV
|
1559 DPLL_REF_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
;
1561 val
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
1563 I915_WRITE(DPLL(pipe
), val
);
1564 POSTING_READ(DPLL(pipe
));
1567 static void chv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1569 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1572 /* Make sure the pipe isn't still relying on us */
1573 assert_pipe_disabled(dev_priv
, pipe
);
1575 val
= DPLL_SSC_REF_CLK_CHV
|
1576 DPLL_REF_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
;
1578 val
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
1580 I915_WRITE(DPLL(pipe
), val
);
1581 POSTING_READ(DPLL(pipe
));
1583 vlv_dpio_get(dev_priv
);
1585 /* Disable 10bit clock to display controller */
1586 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1587 val
&= ~DPIO_DCLKP_EN
;
1588 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), val
);
1590 vlv_dpio_put(dev_priv
);
1593 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
,
1594 struct intel_digital_port
*dport
,
1595 unsigned int expected_mask
)
1598 i915_reg_t dpll_reg
;
1600 switch (dport
->base
.port
) {
1602 port_mask
= DPLL_PORTB_READY_MASK
;
1606 port_mask
= DPLL_PORTC_READY_MASK
;
1608 expected_mask
<<= 4;
1611 port_mask
= DPLL_PORTD_READY_MASK
;
1612 dpll_reg
= DPIO_PHY_STATUS
;
1618 if (intel_wait_for_register(&dev_priv
->uncore
,
1619 dpll_reg
, port_mask
, expected_mask
,
1621 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1622 port_name(dport
->base
.port
),
1623 I915_READ(dpll_reg
) & port_mask
, expected_mask
);
1626 static void ironlake_enable_pch_transcoder(const struct intel_crtc_state
*crtc_state
)
1628 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
1629 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1630 enum pipe pipe
= crtc
->pipe
;
1632 u32 val
, pipeconf_val
;
1634 /* Make sure PCH DPLL is enabled */
1635 assert_shared_dpll_enabled(dev_priv
, crtc_state
->shared_dpll
);
1637 /* FDI must be feeding us bits for PCH ports */
1638 assert_fdi_tx_enabled(dev_priv
, pipe
);
1639 assert_fdi_rx_enabled(dev_priv
, pipe
);
1641 if (HAS_PCH_CPT(dev_priv
)) {
1642 /* Workaround: Set the timing override bit before enabling the
1643 * pch transcoder. */
1644 reg
= TRANS_CHICKEN2(pipe
);
1645 val
= I915_READ(reg
);
1646 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1647 I915_WRITE(reg
, val
);
1650 reg
= PCH_TRANSCONF(pipe
);
1651 val
= I915_READ(reg
);
1652 pipeconf_val
= I915_READ(PIPECONF(pipe
));
1654 if (HAS_PCH_IBX(dev_priv
)) {
1656 * Make the BPC in transcoder be consistent with
1657 * that in pipeconf reg. For HDMI we must use 8bpc
1658 * here for both 8bpc and 12bpc.
1660 val
&= ~PIPECONF_BPC_MASK
;
1661 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_HDMI
))
1662 val
|= PIPECONF_8BPC
;
1664 val
|= pipeconf_val
& PIPECONF_BPC_MASK
;
1667 val
&= ~TRANS_INTERLACE_MASK
;
1668 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
) {
1669 if (HAS_PCH_IBX(dev_priv
) &&
1670 intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_SDVO
))
1671 val
|= TRANS_LEGACY_INTERLACED_ILK
;
1673 val
|= TRANS_INTERLACED
;
1675 val
|= TRANS_PROGRESSIVE
;
1678 I915_WRITE(reg
, val
| TRANS_ENABLE
);
1679 if (intel_wait_for_register(&dev_priv
->uncore
,
1680 reg
, TRANS_STATE_ENABLE
, TRANS_STATE_ENABLE
,
1682 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe
));
1685 static void lpt_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1686 enum transcoder cpu_transcoder
)
1688 u32 val
, pipeconf_val
;
1690 /* FDI must be feeding us bits for PCH ports */
1691 assert_fdi_tx_enabled(dev_priv
, (enum pipe
) cpu_transcoder
);
1692 assert_fdi_rx_enabled(dev_priv
, PIPE_A
);
1694 /* Workaround: set timing override bit. */
1695 val
= I915_READ(TRANS_CHICKEN2(PIPE_A
));
1696 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1697 I915_WRITE(TRANS_CHICKEN2(PIPE_A
), val
);
1700 pipeconf_val
= I915_READ(PIPECONF(cpu_transcoder
));
1702 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK_HSW
) ==
1703 PIPECONF_INTERLACED_ILK
)
1704 val
|= TRANS_INTERLACED
;
1706 val
|= TRANS_PROGRESSIVE
;
1708 I915_WRITE(LPT_TRANSCONF
, val
);
1709 if (intel_wait_for_register(&dev_priv
->uncore
,
1714 DRM_ERROR("Failed to enable PCH transcoder\n");
1717 static void ironlake_disable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1723 /* FDI relies on the transcoder */
1724 assert_fdi_tx_disabled(dev_priv
, pipe
);
1725 assert_fdi_rx_disabled(dev_priv
, pipe
);
1727 /* Ports must be off as well */
1728 assert_pch_ports_disabled(dev_priv
, pipe
);
1730 reg
= PCH_TRANSCONF(pipe
);
1731 val
= I915_READ(reg
);
1732 val
&= ~TRANS_ENABLE
;
1733 I915_WRITE(reg
, val
);
1734 /* wait for PCH transcoder off, transcoder state */
1735 if (intel_wait_for_register(&dev_priv
->uncore
,
1736 reg
, TRANS_STATE_ENABLE
, 0,
1738 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe
));
1740 if (HAS_PCH_CPT(dev_priv
)) {
1741 /* Workaround: Clear the timing override chicken bit again. */
1742 reg
= TRANS_CHICKEN2(pipe
);
1743 val
= I915_READ(reg
);
1744 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1745 I915_WRITE(reg
, val
);
1749 void lpt_disable_pch_transcoder(struct drm_i915_private
*dev_priv
)
1753 val
= I915_READ(LPT_TRANSCONF
);
1754 val
&= ~TRANS_ENABLE
;
1755 I915_WRITE(LPT_TRANSCONF
, val
);
1756 /* wait for PCH transcoder off, transcoder state */
1757 if (intel_wait_for_register(&dev_priv
->uncore
,
1758 LPT_TRANSCONF
, TRANS_STATE_ENABLE
, 0,
1760 DRM_ERROR("Failed to disable PCH transcoder\n");
1762 /* Workaround: clear timing override bit. */
1763 val
= I915_READ(TRANS_CHICKEN2(PIPE_A
));
1764 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1765 I915_WRITE(TRANS_CHICKEN2(PIPE_A
), val
);
1768 enum pipe
intel_crtc_pch_transcoder(struct intel_crtc
*crtc
)
1770 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1772 if (HAS_PCH_LPT(dev_priv
))
1778 static u32
intel_crtc_max_vblank_count(const struct intel_crtc_state
*crtc_state
)
1780 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->base
.crtc
->dev
);
1783 * On i965gm the hardware frame counter reads
1784 * zero when the TV encoder is enabled :(
1786 if (IS_I965GM(dev_priv
) &&
1787 (crtc_state
->output_types
& BIT(INTEL_OUTPUT_TVOUT
)))
1790 if (INTEL_GEN(dev_priv
) >= 5 || IS_G4X(dev_priv
))
1791 return 0xffffffff; /* full 32 bit counter */
1792 else if (INTEL_GEN(dev_priv
) >= 3)
1793 return 0xffffff; /* only 24 bits of frame count */
1795 return 0; /* Gen2 doesn't have a hardware frame counter */
1798 static void intel_crtc_vblank_on(const struct intel_crtc_state
*crtc_state
)
1800 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
1802 drm_crtc_set_max_vblank_count(&crtc
->base
,
1803 intel_crtc_max_vblank_count(crtc_state
));
1804 drm_crtc_vblank_on(&crtc
->base
);
1807 static void intel_enable_pipe(const struct intel_crtc_state
*new_crtc_state
)
1809 struct intel_crtc
*crtc
= to_intel_crtc(new_crtc_state
->base
.crtc
);
1810 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1811 enum transcoder cpu_transcoder
= new_crtc_state
->cpu_transcoder
;
1812 enum pipe pipe
= crtc
->pipe
;
1816 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe
));
1818 assert_planes_disabled(crtc
);
1821 * A pipe without a PLL won't actually be able to drive bits from
1822 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1825 if (HAS_GMCH(dev_priv
)) {
1826 if (intel_crtc_has_type(new_crtc_state
, INTEL_OUTPUT_DSI
))
1827 assert_dsi_pll_enabled(dev_priv
);
1829 assert_pll_enabled(dev_priv
, pipe
);
1831 if (new_crtc_state
->has_pch_encoder
) {
1832 /* if driving the PCH, we need FDI enabled */
1833 assert_fdi_rx_pll_enabled(dev_priv
,
1834 intel_crtc_pch_transcoder(crtc
));
1835 assert_fdi_tx_pll_enabled(dev_priv
,
1836 (enum pipe
) cpu_transcoder
);
1838 /* FIXME: assert CPU port conditions for SNB+ */
1841 trace_intel_pipe_enable(dev_priv
, pipe
);
1843 reg
= PIPECONF(cpu_transcoder
);
1844 val
= I915_READ(reg
);
1845 if (val
& PIPECONF_ENABLE
) {
1846 /* we keep both pipes enabled on 830 */
1847 WARN_ON(!IS_I830(dev_priv
));
1851 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
1855 * Until the pipe starts PIPEDSL reads will return a stale value,
1856 * which causes an apparent vblank timestamp jump when PIPEDSL
1857 * resets to its proper value. That also messes up the frame count
1858 * when it's derived from the timestamps. So let's wait for the
1859 * pipe to start properly before we call drm_crtc_vblank_on()
1861 if (intel_crtc_max_vblank_count(new_crtc_state
) == 0)
1862 intel_wait_for_pipe_scanline_moving(crtc
);
1865 static void intel_disable_pipe(const struct intel_crtc_state
*old_crtc_state
)
1867 struct intel_crtc
*crtc
= to_intel_crtc(old_crtc_state
->base
.crtc
);
1868 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1869 enum transcoder cpu_transcoder
= old_crtc_state
->cpu_transcoder
;
1870 enum pipe pipe
= crtc
->pipe
;
1874 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe
));
1877 * Make sure planes won't keep trying to pump pixels to us,
1878 * or we might hang the display.
1880 assert_planes_disabled(crtc
);
1882 trace_intel_pipe_disable(dev_priv
, pipe
);
1884 reg
= PIPECONF(cpu_transcoder
);
1885 val
= I915_READ(reg
);
1886 if ((val
& PIPECONF_ENABLE
) == 0)
1890 * Double wide has implications for planes
1891 * so best keep it disabled when not needed.
1893 if (old_crtc_state
->double_wide
)
1894 val
&= ~PIPECONF_DOUBLE_WIDE
;
1896 /* Don't disable pipe or pipe PLLs if needed */
1897 if (!IS_I830(dev_priv
))
1898 val
&= ~PIPECONF_ENABLE
;
1900 I915_WRITE(reg
, val
);
1901 if ((val
& PIPECONF_ENABLE
) == 0)
1902 intel_wait_for_pipe_off(old_crtc_state
);
1905 static unsigned int intel_tile_size(const struct drm_i915_private
*dev_priv
)
1907 return IS_GEN(dev_priv
, 2) ? 2048 : 4096;
1911 intel_tile_width_bytes(const struct drm_framebuffer
*fb
, int color_plane
)
1913 struct drm_i915_private
*dev_priv
= to_i915(fb
->dev
);
1914 unsigned int cpp
= fb
->format
->cpp
[color_plane
];
1916 switch (fb
->modifier
) {
1917 case DRM_FORMAT_MOD_LINEAR
:
1918 return intel_tile_size(dev_priv
);
1919 case I915_FORMAT_MOD_X_TILED
:
1920 if (IS_GEN(dev_priv
, 2))
1924 case I915_FORMAT_MOD_Y_TILED_CCS
:
1925 if (color_plane
== 1)
1928 case I915_FORMAT_MOD_Y_TILED
:
1929 if (IS_GEN(dev_priv
, 2) || HAS_128_BYTE_Y_TILING(dev_priv
))
1933 case I915_FORMAT_MOD_Yf_TILED_CCS
:
1934 if (color_plane
== 1)
1937 case I915_FORMAT_MOD_Yf_TILED
:
1953 MISSING_CASE(fb
->modifier
);
1959 intel_tile_height(const struct drm_framebuffer
*fb
, int color_plane
)
1961 return intel_tile_size(to_i915(fb
->dev
)) /
1962 intel_tile_width_bytes(fb
, color_plane
);
1965 /* Return the tile dimensions in pixel units */
1966 static void intel_tile_dims(const struct drm_framebuffer
*fb
, int color_plane
,
1967 unsigned int *tile_width
,
1968 unsigned int *tile_height
)
1970 unsigned int tile_width_bytes
= intel_tile_width_bytes(fb
, color_plane
);
1971 unsigned int cpp
= fb
->format
->cpp
[color_plane
];
1973 *tile_width
= tile_width_bytes
/ cpp
;
1974 *tile_height
= intel_tile_size(to_i915(fb
->dev
)) / tile_width_bytes
;
1978 intel_fb_align_height(const struct drm_framebuffer
*fb
,
1979 int color_plane
, unsigned int height
)
1981 unsigned int tile_height
= intel_tile_height(fb
, color_plane
);
1983 return ALIGN(height
, tile_height
);
1986 unsigned int intel_rotation_info_size(const struct intel_rotation_info
*rot_info
)
1988 unsigned int size
= 0;
1991 for (i
= 0 ; i
< ARRAY_SIZE(rot_info
->plane
); i
++)
1992 size
+= rot_info
->plane
[i
].width
* rot_info
->plane
[i
].height
;
1997 unsigned int intel_remapped_info_size(const struct intel_remapped_info
*rem_info
)
1999 unsigned int size
= 0;
2002 for (i
= 0 ; i
< ARRAY_SIZE(rem_info
->plane
); i
++)
2003 size
+= rem_info
->plane
[i
].width
* rem_info
->plane
[i
].height
;
2009 intel_fill_fb_ggtt_view(struct i915_ggtt_view
*view
,
2010 const struct drm_framebuffer
*fb
,
2011 unsigned int rotation
)
2013 view
->type
= I915_GGTT_VIEW_NORMAL
;
2014 if (drm_rotation_90_or_270(rotation
)) {
2015 view
->type
= I915_GGTT_VIEW_ROTATED
;
2016 view
->rotated
= to_intel_framebuffer(fb
)->rot_info
;
2020 static unsigned int intel_cursor_alignment(const struct drm_i915_private
*dev_priv
)
2022 if (IS_I830(dev_priv
))
2024 else if (IS_I85X(dev_priv
))
2026 else if (IS_I845G(dev_priv
) || IS_I865G(dev_priv
))
2032 static unsigned int intel_linear_alignment(const struct drm_i915_private
*dev_priv
)
2034 if (INTEL_GEN(dev_priv
) >= 9)
2036 else if (IS_I965G(dev_priv
) || IS_I965GM(dev_priv
) ||
2037 IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
2039 else if (INTEL_GEN(dev_priv
) >= 4)
2045 static unsigned int intel_surf_alignment(const struct drm_framebuffer
*fb
,
2048 struct drm_i915_private
*dev_priv
= to_i915(fb
->dev
);
2050 /* AUX_DIST needs only 4K alignment */
2051 if (color_plane
== 1)
2054 switch (fb
->modifier
) {
2055 case DRM_FORMAT_MOD_LINEAR
:
2056 return intel_linear_alignment(dev_priv
);
2057 case I915_FORMAT_MOD_X_TILED
:
2058 if (INTEL_GEN(dev_priv
) >= 9)
2061 case I915_FORMAT_MOD_Y_TILED_CCS
:
2062 case I915_FORMAT_MOD_Yf_TILED_CCS
:
2063 case I915_FORMAT_MOD_Y_TILED
:
2064 case I915_FORMAT_MOD_Yf_TILED
:
2065 return 1 * 1024 * 1024;
2067 MISSING_CASE(fb
->modifier
);
2072 static bool intel_plane_uses_fence(const struct intel_plane_state
*plane_state
)
2074 struct intel_plane
*plane
= to_intel_plane(plane_state
->base
.plane
);
2075 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
2077 return INTEL_GEN(dev_priv
) < 4 ||
2079 plane_state
->view
.type
== I915_GGTT_VIEW_NORMAL
);
2083 intel_pin_and_fence_fb_obj(struct drm_framebuffer
*fb
,
2084 const struct i915_ggtt_view
*view
,
2086 unsigned long *out_flags
)
2088 struct drm_device
*dev
= fb
->dev
;
2089 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2090 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2091 intel_wakeref_t wakeref
;
2092 struct i915_vma
*vma
;
2093 unsigned int pinctl
;
2096 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
2098 alignment
= intel_surf_alignment(fb
, 0);
2100 /* Note that the w/a also requires 64 PTE of padding following the
2101 * bo. We currently fill all unused PTE with the shadow page and so
2102 * we should always have valid PTE following the scanout preventing
2105 if (intel_scanout_needs_vtd_wa(dev_priv
) && alignment
< 256 * 1024)
2106 alignment
= 256 * 1024;
2109 * Global gtt pte registers are special registers which actually forward
2110 * writes to a chunk of system memory. Which means that there is no risk
2111 * that the register values disappear as soon as we call
2112 * intel_runtime_pm_put(), so it is correct to wrap only the
2113 * pin/unpin/fence and not more.
2115 wakeref
= intel_runtime_pm_get(dev_priv
);
2117 atomic_inc(&dev_priv
->gpu_error
.pending_fb_pin
);
2121 /* Valleyview is definitely limited to scanning out the first
2122 * 512MiB. Lets presume this behaviour was inherited from the
2123 * g4x display engine and that all earlier gen are similarly
2124 * limited. Testing suggests that it is a little more
2125 * complicated than this. For example, Cherryview appears quite
2126 * happy to scanout from anywhere within its global aperture.
2128 if (HAS_GMCH(dev_priv
))
2129 pinctl
|= PIN_MAPPABLE
;
2131 vma
= i915_gem_object_pin_to_display_plane(obj
,
2132 alignment
, view
, pinctl
);
2136 if (uses_fence
&& i915_vma_is_map_and_fenceable(vma
)) {
2139 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2140 * fence, whereas 965+ only requires a fence if using
2141 * framebuffer compression. For simplicity, we always, when
2142 * possible, install a fence as the cost is not that onerous.
2144 * If we fail to fence the tiled scanout, then either the
2145 * modeset will reject the change (which is highly unlikely as
2146 * the affected systems, all but one, do not have unmappable
2147 * space) or we will not be able to enable full powersaving
2148 * techniques (also likely not to apply due to various limits
2149 * FBC and the like impose on the size of the buffer, which
2150 * presumably we violated anyway with this unmappable buffer).
2151 * Anyway, it is presumably better to stumble onwards with
2152 * something and try to run the system in a "less than optimal"
2153 * mode that matches the user configuration.
2155 ret
= i915_vma_pin_fence(vma
);
2156 if (ret
!= 0 && INTEL_GEN(dev_priv
) < 4) {
2157 i915_gem_object_unpin_from_display_plane(vma
);
2162 if (ret
== 0 && vma
->fence
)
2163 *out_flags
|= PLANE_HAS_FENCE
;
2168 atomic_dec(&dev_priv
->gpu_error
.pending_fb_pin
);
2170 intel_runtime_pm_put(dev_priv
, wakeref
);
2174 void intel_unpin_fb_vma(struct i915_vma
*vma
, unsigned long flags
)
2176 lockdep_assert_held(&vma
->vm
->i915
->drm
.struct_mutex
);
2178 if (flags
& PLANE_HAS_FENCE
)
2179 i915_vma_unpin_fence(vma
);
2180 i915_gem_object_unpin_from_display_plane(vma
);
2184 static int intel_fb_pitch(const struct drm_framebuffer
*fb
, int color_plane
,
2185 unsigned int rotation
)
2187 if (drm_rotation_90_or_270(rotation
))
2188 return to_intel_framebuffer(fb
)->rotated
[color_plane
].pitch
;
2190 return fb
->pitches
[color_plane
];
2194 * Convert the x/y offsets into a linear offset.
2195 * Only valid with 0/180 degree rotation, which is fine since linear
2196 * offset is only used with linear buffers on pre-hsw and tiled buffers
2197 * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2199 u32
intel_fb_xy_to_linear(int x
, int y
,
2200 const struct intel_plane_state
*state
,
2203 const struct drm_framebuffer
*fb
= state
->base
.fb
;
2204 unsigned int cpp
= fb
->format
->cpp
[color_plane
];
2205 unsigned int pitch
= state
->color_plane
[color_plane
].stride
;
2207 return y
* pitch
+ x
* cpp
;
2211 * Add the x/y offsets derived from fb->offsets[] to the user
2212 * specified plane src x/y offsets. The resulting x/y offsets
2213 * specify the start of scanout from the beginning of the gtt mapping.
2215 void intel_add_fb_offsets(int *x
, int *y
,
2216 const struct intel_plane_state
*state
,
2220 *x
+= state
->color_plane
[color_plane
].x
;
2221 *y
+= state
->color_plane
[color_plane
].y
;
2224 static u32
intel_adjust_tile_offset(int *x
, int *y
,
2225 unsigned int tile_width
,
2226 unsigned int tile_height
,
2227 unsigned int tile_size
,
2228 unsigned int pitch_tiles
,
2232 unsigned int pitch_pixels
= pitch_tiles
* tile_width
;
2235 WARN_ON(old_offset
& (tile_size
- 1));
2236 WARN_ON(new_offset
& (tile_size
- 1));
2237 WARN_ON(new_offset
> old_offset
);
2239 tiles
= (old_offset
- new_offset
) / tile_size
;
2241 *y
+= tiles
/ pitch_tiles
* tile_height
;
2242 *x
+= tiles
% pitch_tiles
* tile_width
;
2244 /* minimize x in case it got needlessly big */
2245 *y
+= *x
/ pitch_pixels
* tile_height
;
2251 static bool is_surface_linear(u64 modifier
, int color_plane
)
2253 return modifier
== DRM_FORMAT_MOD_LINEAR
;
2256 static u32
intel_adjust_aligned_offset(int *x
, int *y
,
2257 const struct drm_framebuffer
*fb
,
2259 unsigned int rotation
,
2261 u32 old_offset
, u32 new_offset
)
2263 struct drm_i915_private
*dev_priv
= to_i915(fb
->dev
);
2264 unsigned int cpp
= fb
->format
->cpp
[color_plane
];
2266 WARN_ON(new_offset
> old_offset
);
2268 if (!is_surface_linear(fb
->modifier
, color_plane
)) {
2269 unsigned int tile_size
, tile_width
, tile_height
;
2270 unsigned int pitch_tiles
;
2272 tile_size
= intel_tile_size(dev_priv
);
2273 intel_tile_dims(fb
, color_plane
, &tile_width
, &tile_height
);
2275 if (drm_rotation_90_or_270(rotation
)) {
2276 pitch_tiles
= pitch
/ tile_height
;
2277 swap(tile_width
, tile_height
);
2279 pitch_tiles
= pitch
/ (tile_width
* cpp
);
2282 intel_adjust_tile_offset(x
, y
, tile_width
, tile_height
,
2283 tile_size
, pitch_tiles
,
2284 old_offset
, new_offset
);
2286 old_offset
+= *y
* pitch
+ *x
* cpp
;
2288 *y
= (old_offset
- new_offset
) / pitch
;
2289 *x
= ((old_offset
- new_offset
) - *y
* pitch
) / cpp
;
2296 * Adjust the tile offset by moving the difference into
2299 static u32
intel_plane_adjust_aligned_offset(int *x
, int *y
,
2300 const struct intel_plane_state
*state
,
2302 u32 old_offset
, u32 new_offset
)
2304 return intel_adjust_aligned_offset(x
, y
, state
->base
.fb
, color_plane
,
2305 state
->base
.rotation
,
2306 state
->color_plane
[color_plane
].stride
,
2307 old_offset
, new_offset
);
2311 * Computes the aligned offset to the base tile and adjusts
2312 * x, y. bytes per pixel is assumed to be a power-of-two.
2314 * In the 90/270 rotated case, x and y are assumed
2315 * to be already rotated to match the rotated GTT view, and
2316 * pitch is the tile_height aligned framebuffer height.
2318 * This function is used when computing the derived information
2319 * under intel_framebuffer, so using any of that information
2320 * here is not allowed. Anything under drm_framebuffer can be
2321 * used. This is why the user has to pass in the pitch since it
2322 * is specified in the rotated orientation.
2324 static u32
intel_compute_aligned_offset(struct drm_i915_private
*dev_priv
,
2326 const struct drm_framebuffer
*fb
,
2329 unsigned int rotation
,
2332 unsigned int cpp
= fb
->format
->cpp
[color_plane
];
2333 u32 offset
, offset_aligned
;
2338 if (!is_surface_linear(fb
->modifier
, color_plane
)) {
2339 unsigned int tile_size
, tile_width
, tile_height
;
2340 unsigned int tile_rows
, tiles
, pitch_tiles
;
2342 tile_size
= intel_tile_size(dev_priv
);
2343 intel_tile_dims(fb
, color_plane
, &tile_width
, &tile_height
);
2345 if (drm_rotation_90_or_270(rotation
)) {
2346 pitch_tiles
= pitch
/ tile_height
;
2347 swap(tile_width
, tile_height
);
2349 pitch_tiles
= pitch
/ (tile_width
* cpp
);
2352 tile_rows
= *y
/ tile_height
;
2355 tiles
= *x
/ tile_width
;
2358 offset
= (tile_rows
* pitch_tiles
+ tiles
) * tile_size
;
2359 offset_aligned
= offset
& ~alignment
;
2361 intel_adjust_tile_offset(x
, y
, tile_width
, tile_height
,
2362 tile_size
, pitch_tiles
,
2363 offset
, offset_aligned
);
2365 offset
= *y
* pitch
+ *x
* cpp
;
2366 offset_aligned
= offset
& ~alignment
;
2368 *y
= (offset
& alignment
) / pitch
;
2369 *x
= ((offset
& alignment
) - *y
* pitch
) / cpp
;
2372 return offset_aligned
;
2375 static u32
intel_plane_compute_aligned_offset(int *x
, int *y
,
2376 const struct intel_plane_state
*state
,
2379 struct intel_plane
*intel_plane
= to_intel_plane(state
->base
.plane
);
2380 struct drm_i915_private
*dev_priv
= to_i915(intel_plane
->base
.dev
);
2381 const struct drm_framebuffer
*fb
= state
->base
.fb
;
2382 unsigned int rotation
= state
->base
.rotation
;
2383 int pitch
= state
->color_plane
[color_plane
].stride
;
2386 if (intel_plane
->id
== PLANE_CURSOR
)
2387 alignment
= intel_cursor_alignment(dev_priv
);
2389 alignment
= intel_surf_alignment(fb
, color_plane
);
2391 return intel_compute_aligned_offset(dev_priv
, x
, y
, fb
, color_plane
,
2392 pitch
, rotation
, alignment
);
2395 /* Convert the fb->offset[] into x/y offsets */
2396 static int intel_fb_offset_to_xy(int *x
, int *y
,
2397 const struct drm_framebuffer
*fb
,
2400 struct drm_i915_private
*dev_priv
= to_i915(fb
->dev
);
2401 unsigned int height
;
2403 if (fb
->modifier
!= DRM_FORMAT_MOD_LINEAR
&&
2404 fb
->offsets
[color_plane
] % intel_tile_size(dev_priv
)) {
2405 DRM_DEBUG_KMS("Misaligned offset 0x%08x for color plane %d\n",
2406 fb
->offsets
[color_plane
], color_plane
);
2410 height
= drm_framebuffer_plane_height(fb
->height
, fb
, color_plane
);
2411 height
= ALIGN(height
, intel_tile_height(fb
, color_plane
));
2413 /* Catch potential overflows early */
2414 if (add_overflows_t(u32
, mul_u32_u32(height
, fb
->pitches
[color_plane
]),
2415 fb
->offsets
[color_plane
])) {
2416 DRM_DEBUG_KMS("Bad offset 0x%08x or pitch %d for color plane %d\n",
2417 fb
->offsets
[color_plane
], fb
->pitches
[color_plane
],
2425 intel_adjust_aligned_offset(x
, y
,
2426 fb
, color_plane
, DRM_MODE_ROTATE_0
,
2427 fb
->pitches
[color_plane
],
2428 fb
->offsets
[color_plane
], 0);
2433 static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier
)
2435 switch (fb_modifier
) {
2436 case I915_FORMAT_MOD_X_TILED
:
2437 return I915_TILING_X
;
2438 case I915_FORMAT_MOD_Y_TILED
:
2439 case I915_FORMAT_MOD_Y_TILED_CCS
:
2440 return I915_TILING_Y
;
2442 return I915_TILING_NONE
;
2447 * From the Sky Lake PRM:
2448 * "The Color Control Surface (CCS) contains the compression status of
2449 * the cache-line pairs. The compression state of the cache-line pair
2450 * is specified by 2 bits in the CCS. Each CCS cache-line represents
2451 * an area on the main surface of 16 x16 sets of 128 byte Y-tiled
2452 * cache-line-pairs. CCS is always Y tiled."
2454 * Since cache line pairs refers to horizontally adjacent cache lines,
2455 * each cache line in the CCS corresponds to an area of 32x16 cache
2456 * lines on the main surface. Since each pixel is 4 bytes, this gives
2457 * us a ratio of one byte in the CCS for each 8x16 pixels in the
2460 static const struct drm_format_info ccs_formats
[] = {
2461 { .format
= DRM_FORMAT_XRGB8888
, .depth
= 24, .num_planes
= 2, .cpp
= { 4, 1, }, .hsub
= 8, .vsub
= 16, },
2462 { .format
= DRM_FORMAT_XBGR8888
, .depth
= 24, .num_planes
= 2, .cpp
= { 4, 1, }, .hsub
= 8, .vsub
= 16, },
2463 { .format
= DRM_FORMAT_ARGB8888
, .depth
= 32, .num_planes
= 2, .cpp
= { 4, 1, }, .hsub
= 8, .vsub
= 16, },
2464 { .format
= DRM_FORMAT_ABGR8888
, .depth
= 32, .num_planes
= 2, .cpp
= { 4, 1, }, .hsub
= 8, .vsub
= 16, },
2467 static const struct drm_format_info
*
2468 lookup_format_info(const struct drm_format_info formats
[],
2469 int num_formats
, u32 format
)
2473 for (i
= 0; i
< num_formats
; i
++) {
2474 if (formats
[i
].format
== format
)
2481 static const struct drm_format_info
*
2482 intel_get_format_info(const struct drm_mode_fb_cmd2
*cmd
)
2484 switch (cmd
->modifier
[0]) {
2485 case I915_FORMAT_MOD_Y_TILED_CCS
:
2486 case I915_FORMAT_MOD_Yf_TILED_CCS
:
2487 return lookup_format_info(ccs_formats
,
2488 ARRAY_SIZE(ccs_formats
),
2495 bool is_ccs_modifier(u64 modifier
)
2497 return modifier
== I915_FORMAT_MOD_Y_TILED_CCS
||
2498 modifier
== I915_FORMAT_MOD_Yf_TILED_CCS
;
2501 u32
intel_plane_fb_max_stride(struct drm_i915_private
*dev_priv
,
2502 u32 pixel_format
, u64 modifier
)
2504 struct intel_crtc
*crtc
;
2505 struct intel_plane
*plane
;
2508 * We assume the primary plane for pipe A has
2509 * the highest stride limits of them all.
2511 crtc
= intel_get_crtc_for_pipe(dev_priv
, PIPE_A
);
2512 plane
= to_intel_plane(crtc
->base
.primary
);
2514 return plane
->max_stride(plane
, pixel_format
, modifier
,
2519 u32
intel_fb_max_stride(struct drm_i915_private
*dev_priv
,
2520 u32 pixel_format
, u64 modifier
)
2522 return intel_plane_fb_max_stride(dev_priv
, pixel_format
, modifier
);
2526 intel_fb_stride_alignment(const struct drm_framebuffer
*fb
, int color_plane
)
2528 struct drm_i915_private
*dev_priv
= to_i915(fb
->dev
);
2530 if (fb
->modifier
== DRM_FORMAT_MOD_LINEAR
) {
2531 u32 max_stride
= intel_plane_fb_max_stride(dev_priv
,
2536 * To make remapping with linear generally feasible
2537 * we need the stride to be page aligned.
2539 if (fb
->pitches
[color_plane
] > max_stride
)
2540 return intel_tile_size(dev_priv
);
2544 return intel_tile_width_bytes(fb
, color_plane
);
2548 bool intel_plane_can_remap(const struct intel_plane_state
*plane_state
)
2550 struct intel_plane
*plane
= to_intel_plane(plane_state
->base
.plane
);
2551 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
2552 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
2555 /* We don't want to deal with remapping with cursors */
2556 if (plane
->id
== PLANE_CURSOR
)
2560 * The display engine limits already match/exceed the
2561 * render engine limits, so not much point in remapping.
2562 * Would also need to deal with the fence POT alignment
2563 * and gen2 2KiB GTT tile size.
2565 if (INTEL_GEN(dev_priv
) < 4)
2569 * The new CCS hash mode isn't compatible with remapping as
2570 * the virtual address of the pages affects the compressed data.
2572 if (is_ccs_modifier(fb
->modifier
))
2575 /* Linear needs a page aligned stride for remapping */
2576 if (fb
->modifier
== DRM_FORMAT_MOD_LINEAR
) {
2577 unsigned int alignment
= intel_tile_size(dev_priv
) - 1;
2579 for (i
= 0; i
< fb
->format
->num_planes
; i
++) {
2580 if (fb
->pitches
[i
] & alignment
)
2588 static bool intel_plane_needs_remap(const struct intel_plane_state
*plane_state
)
2590 struct intel_plane
*plane
= to_intel_plane(plane_state
->base
.plane
);
2591 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
2592 unsigned int rotation
= plane_state
->base
.rotation
;
2593 u32 stride
, max_stride
;
2596 * No remapping for invisible planes since we don't have
2597 * an actual source viewport to remap.
2599 if (!plane_state
->base
.visible
)
2602 if (!intel_plane_can_remap(plane_state
))
2606 * FIXME: aux plane limits on gen9+ are
2607 * unclear in Bspec, for now no checking.
2609 stride
= intel_fb_pitch(fb
, 0, rotation
);
2610 max_stride
= plane
->max_stride(plane
, fb
->format
->format
,
2611 fb
->modifier
, rotation
);
2613 return stride
> max_stride
;
2617 intel_fill_fb_info(struct drm_i915_private
*dev_priv
,
2618 struct drm_framebuffer
*fb
)
2620 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
2621 struct intel_rotation_info
*rot_info
= &intel_fb
->rot_info
;
2622 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2623 u32 gtt_offset_rotated
= 0;
2624 unsigned int max_size
= 0;
2625 int i
, num_planes
= fb
->format
->num_planes
;
2626 unsigned int tile_size
= intel_tile_size(dev_priv
);
2628 for (i
= 0; i
< num_planes
; i
++) {
2629 unsigned int width
, height
;
2630 unsigned int cpp
, size
;
2635 cpp
= fb
->format
->cpp
[i
];
2636 width
= drm_framebuffer_plane_width(fb
->width
, fb
, i
);
2637 height
= drm_framebuffer_plane_height(fb
->height
, fb
, i
);
2639 ret
= intel_fb_offset_to_xy(&x
, &y
, fb
, i
);
2641 DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2646 if (is_ccs_modifier(fb
->modifier
) && i
== 1) {
2647 int hsub
= fb
->format
->hsub
;
2648 int vsub
= fb
->format
->vsub
;
2649 int tile_width
, tile_height
;
2653 intel_tile_dims(fb
, i
, &tile_width
, &tile_height
);
2655 tile_height
*= vsub
;
2657 ccs_x
= (x
* hsub
) % tile_width
;
2658 ccs_y
= (y
* vsub
) % tile_height
;
2659 main_x
= intel_fb
->normal
[0].x
% tile_width
;
2660 main_y
= intel_fb
->normal
[0].y
% tile_height
;
2663 * CCS doesn't have its own x/y offset register, so the intra CCS tile
2664 * x/y offsets must match between CCS and the main surface.
2666 if (main_x
!= ccs_x
|| main_y
!= ccs_y
) {
2667 DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
2670 intel_fb
->normal
[0].x
,
2671 intel_fb
->normal
[0].y
,
2678 * The fence (if used) is aligned to the start of the object
2679 * so having the framebuffer wrap around across the edge of the
2680 * fenced region doesn't really work. We have no API to configure
2681 * the fence start offset within the object (nor could we probably
2682 * on gen2/3). So it's just easier if we just require that the
2683 * fb layout agrees with the fence layout. We already check that the
2684 * fb stride matches the fence stride elsewhere.
2686 if (i
== 0 && i915_gem_object_is_tiled(obj
) &&
2687 (x
+ width
) * cpp
> fb
->pitches
[i
]) {
2688 DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2694 * First pixel of the framebuffer from
2695 * the start of the normal gtt mapping.
2697 intel_fb
->normal
[i
].x
= x
;
2698 intel_fb
->normal
[i
].y
= y
;
2700 offset
= intel_compute_aligned_offset(dev_priv
, &x
, &y
, fb
, i
,
2704 offset
/= tile_size
;
2706 if (!is_surface_linear(fb
->modifier
, i
)) {
2707 unsigned int tile_width
, tile_height
;
2708 unsigned int pitch_tiles
;
2711 intel_tile_dims(fb
, i
, &tile_width
, &tile_height
);
2713 rot_info
->plane
[i
].offset
= offset
;
2714 rot_info
->plane
[i
].stride
= DIV_ROUND_UP(fb
->pitches
[i
], tile_width
* cpp
);
2715 rot_info
->plane
[i
].width
= DIV_ROUND_UP(x
+ width
, tile_width
);
2716 rot_info
->plane
[i
].height
= DIV_ROUND_UP(y
+ height
, tile_height
);
2718 intel_fb
->rotated
[i
].pitch
=
2719 rot_info
->plane
[i
].height
* tile_height
;
2721 /* how many tiles does this plane need */
2722 size
= rot_info
->plane
[i
].stride
* rot_info
->plane
[i
].height
;
2724 * If the plane isn't horizontally tile aligned,
2725 * we need one more tile.
2730 /* rotate the x/y offsets to match the GTT view */
2736 rot_info
->plane
[i
].width
* tile_width
,
2737 rot_info
->plane
[i
].height
* tile_height
,
2738 DRM_MODE_ROTATE_270
);
2742 /* rotate the tile dimensions to match the GTT view */
2743 pitch_tiles
= intel_fb
->rotated
[i
].pitch
/ tile_height
;
2744 swap(tile_width
, tile_height
);
2747 * We only keep the x/y offsets, so push all of the
2748 * gtt offset into the x/y offsets.
2750 intel_adjust_tile_offset(&x
, &y
,
2751 tile_width
, tile_height
,
2752 tile_size
, pitch_tiles
,
2753 gtt_offset_rotated
* tile_size
, 0);
2755 gtt_offset_rotated
+= rot_info
->plane
[i
].width
* rot_info
->plane
[i
].height
;
2758 * First pixel of the framebuffer from
2759 * the start of the rotated gtt mapping.
2761 intel_fb
->rotated
[i
].x
= x
;
2762 intel_fb
->rotated
[i
].y
= y
;
2764 size
= DIV_ROUND_UP((y
+ height
) * fb
->pitches
[i
] +
2765 x
* cpp
, tile_size
);
2768 /* how many tiles in total needed in the bo */
2769 max_size
= max(max_size
, offset
+ size
);
2772 if (mul_u32_u32(max_size
, tile_size
) > obj
->base
.size
) {
2773 DRM_DEBUG_KMS("fb too big for bo (need %llu bytes, have %zu bytes)\n",
2774 mul_u32_u32(max_size
, tile_size
), obj
->base
.size
);
2782 intel_plane_remap_gtt(struct intel_plane_state
*plane_state
)
2784 struct drm_i915_private
*dev_priv
=
2785 to_i915(plane_state
->base
.plane
->dev
);
2786 struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
2787 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
2788 struct intel_rotation_info
*info
= &plane_state
->view
.rotated
;
2789 unsigned int rotation
= plane_state
->base
.rotation
;
2790 int i
, num_planes
= fb
->format
->num_planes
;
2791 unsigned int tile_size
= intel_tile_size(dev_priv
);
2792 unsigned int src_x
, src_y
;
2793 unsigned int src_w
, src_h
;
2796 memset(&plane_state
->view
, 0, sizeof(plane_state
->view
));
2797 plane_state
->view
.type
= drm_rotation_90_or_270(rotation
) ?
2798 I915_GGTT_VIEW_ROTATED
: I915_GGTT_VIEW_REMAPPED
;
2800 src_x
= plane_state
->base
.src
.x1
>> 16;
2801 src_y
= plane_state
->base
.src
.y1
>> 16;
2802 src_w
= drm_rect_width(&plane_state
->base
.src
) >> 16;
2803 src_h
= drm_rect_height(&plane_state
->base
.src
) >> 16;
2805 WARN_ON(is_ccs_modifier(fb
->modifier
));
2807 /* Make src coordinates relative to the viewport */
2808 drm_rect_translate(&plane_state
->base
.src
,
2809 -(src_x
<< 16), -(src_y
<< 16));
2811 /* Rotate src coordinates to match rotated GTT view */
2812 if (drm_rotation_90_or_270(rotation
))
2813 drm_rect_rotate(&plane_state
->base
.src
,
2814 src_w
<< 16, src_h
<< 16,
2815 DRM_MODE_ROTATE_270
);
2817 for (i
= 0; i
< num_planes
; i
++) {
2818 unsigned int hsub
= i
? fb
->format
->hsub
: 1;
2819 unsigned int vsub
= i
? fb
->format
->vsub
: 1;
2820 unsigned int cpp
= fb
->format
->cpp
[i
];
2821 unsigned int tile_width
, tile_height
;
2822 unsigned int width
, height
;
2823 unsigned int pitch_tiles
;
2827 intel_tile_dims(fb
, i
, &tile_width
, &tile_height
);
2831 width
= src_w
/ hsub
;
2832 height
= src_h
/ vsub
;
2835 * First pixel of the src viewport from the
2836 * start of the normal gtt mapping.
2838 x
+= intel_fb
->normal
[i
].x
;
2839 y
+= intel_fb
->normal
[i
].y
;
2841 offset
= intel_compute_aligned_offset(dev_priv
, &x
, &y
,
2842 fb
, i
, fb
->pitches
[i
],
2843 DRM_MODE_ROTATE_0
, tile_size
);
2844 offset
/= tile_size
;
2846 info
->plane
[i
].offset
= offset
;
2847 info
->plane
[i
].stride
= DIV_ROUND_UP(fb
->pitches
[i
],
2849 info
->plane
[i
].width
= DIV_ROUND_UP(x
+ width
, tile_width
);
2850 info
->plane
[i
].height
= DIV_ROUND_UP(y
+ height
, tile_height
);
2852 if (drm_rotation_90_or_270(rotation
)) {
2855 /* rotate the x/y offsets to match the GTT view */
2861 info
->plane
[i
].width
* tile_width
,
2862 info
->plane
[i
].height
* tile_height
,
2863 DRM_MODE_ROTATE_270
);
2867 pitch_tiles
= info
->plane
[i
].height
;
2868 plane_state
->color_plane
[i
].stride
= pitch_tiles
* tile_height
;
2870 /* rotate the tile dimensions to match the GTT view */
2871 swap(tile_width
, tile_height
);
2873 pitch_tiles
= info
->plane
[i
].width
;
2874 plane_state
->color_plane
[i
].stride
= pitch_tiles
* tile_width
* cpp
;
2878 * We only keep the x/y offsets, so push all of the
2879 * gtt offset into the x/y offsets.
2881 intel_adjust_tile_offset(&x
, &y
,
2882 tile_width
, tile_height
,
2883 tile_size
, pitch_tiles
,
2884 gtt_offset
* tile_size
, 0);
2886 gtt_offset
+= info
->plane
[i
].width
* info
->plane
[i
].height
;
2888 plane_state
->color_plane
[i
].offset
= 0;
2889 plane_state
->color_plane
[i
].x
= x
;
2890 plane_state
->color_plane
[i
].y
= y
;
2895 intel_plane_compute_gtt(struct intel_plane_state
*plane_state
)
2897 const struct intel_framebuffer
*fb
=
2898 to_intel_framebuffer(plane_state
->base
.fb
);
2899 unsigned int rotation
= plane_state
->base
.rotation
;
2905 num_planes
= fb
->base
.format
->num_planes
;
2907 if (intel_plane_needs_remap(plane_state
)) {
2908 intel_plane_remap_gtt(plane_state
);
2911 * Sometimes even remapping can't overcome
2912 * the stride limitations :( Can happen with
2913 * big plane sizes and suitably misaligned
2916 return intel_plane_check_stride(plane_state
);
2919 intel_fill_fb_ggtt_view(&plane_state
->view
, &fb
->base
, rotation
);
2921 for (i
= 0; i
< num_planes
; i
++) {
2922 plane_state
->color_plane
[i
].stride
= intel_fb_pitch(&fb
->base
, i
, rotation
);
2923 plane_state
->color_plane
[i
].offset
= 0;
2925 if (drm_rotation_90_or_270(rotation
)) {
2926 plane_state
->color_plane
[i
].x
= fb
->rotated
[i
].x
;
2927 plane_state
->color_plane
[i
].y
= fb
->rotated
[i
].y
;
2929 plane_state
->color_plane
[i
].x
= fb
->normal
[i
].x
;
2930 plane_state
->color_plane
[i
].y
= fb
->normal
[i
].y
;
2934 /* Rotate src coordinates to match rotated GTT view */
2935 if (drm_rotation_90_or_270(rotation
))
2936 drm_rect_rotate(&plane_state
->base
.src
,
2937 fb
->base
.width
<< 16, fb
->base
.height
<< 16,
2938 DRM_MODE_ROTATE_270
);
2940 return intel_plane_check_stride(plane_state
);
2943 static int i9xx_format_to_fourcc(int format
)
2946 case DISPPLANE_8BPP
:
2947 return DRM_FORMAT_C8
;
2948 case DISPPLANE_BGRX555
:
2949 return DRM_FORMAT_XRGB1555
;
2950 case DISPPLANE_BGRX565
:
2951 return DRM_FORMAT_RGB565
;
2953 case DISPPLANE_BGRX888
:
2954 return DRM_FORMAT_XRGB8888
;
2955 case DISPPLANE_RGBX888
:
2956 return DRM_FORMAT_XBGR8888
;
2957 case DISPPLANE_BGRX101010
:
2958 return DRM_FORMAT_XRGB2101010
;
2959 case DISPPLANE_RGBX101010
:
2960 return DRM_FORMAT_XBGR2101010
;
2964 int skl_format_to_fourcc(int format
, bool rgb_order
, bool alpha
)
2967 case PLANE_CTL_FORMAT_RGB_565
:
2968 return DRM_FORMAT_RGB565
;
2969 case PLANE_CTL_FORMAT_NV12
:
2970 return DRM_FORMAT_NV12
;
2971 case PLANE_CTL_FORMAT_P010
:
2972 return DRM_FORMAT_P010
;
2973 case PLANE_CTL_FORMAT_P012
:
2974 return DRM_FORMAT_P012
;
2975 case PLANE_CTL_FORMAT_P016
:
2976 return DRM_FORMAT_P016
;
2977 case PLANE_CTL_FORMAT_Y210
:
2978 return DRM_FORMAT_Y210
;
2979 case PLANE_CTL_FORMAT_Y212
:
2980 return DRM_FORMAT_Y212
;
2981 case PLANE_CTL_FORMAT_Y216
:
2982 return DRM_FORMAT_Y216
;
2983 case PLANE_CTL_FORMAT_Y410
:
2984 return DRM_FORMAT_XVYU2101010
;
2985 case PLANE_CTL_FORMAT_Y412
:
2986 return DRM_FORMAT_XVYU12_16161616
;
2987 case PLANE_CTL_FORMAT_Y416
:
2988 return DRM_FORMAT_XVYU16161616
;
2990 case PLANE_CTL_FORMAT_XRGB_8888
:
2993 return DRM_FORMAT_ABGR8888
;
2995 return DRM_FORMAT_XBGR8888
;
2998 return DRM_FORMAT_ARGB8888
;
3000 return DRM_FORMAT_XRGB8888
;
3002 case PLANE_CTL_FORMAT_XRGB_2101010
:
3004 return DRM_FORMAT_XBGR2101010
;
3006 return DRM_FORMAT_XRGB2101010
;
3007 case PLANE_CTL_FORMAT_XRGB_16161616F
:
3010 return DRM_FORMAT_ABGR16161616F
;
3012 return DRM_FORMAT_XBGR16161616F
;
3015 return DRM_FORMAT_ARGB16161616F
;
3017 return DRM_FORMAT_XRGB16161616F
;
3023 intel_alloc_initial_plane_obj(struct intel_crtc
*crtc
,
3024 struct intel_initial_plane_config
*plane_config
)
3026 struct drm_device
*dev
= crtc
->base
.dev
;
3027 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3028 struct drm_i915_gem_object
*obj
= NULL
;
3029 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
3030 struct drm_framebuffer
*fb
= &plane_config
->fb
->base
;
3031 u32 base_aligned
= round_down(plane_config
->base
, PAGE_SIZE
);
3032 u32 size_aligned
= round_up(plane_config
->base
+ plane_config
->size
,
3035 size_aligned
-= base_aligned
;
3037 if (plane_config
->size
== 0)
3040 /* If the FB is too big, just don't use it since fbdev is not very
3041 * important and we should probably use that space with FBC or other
3043 if (size_aligned
* 2 > dev_priv
->stolen_usable_size
)
3046 switch (fb
->modifier
) {
3047 case DRM_FORMAT_MOD_LINEAR
:
3048 case I915_FORMAT_MOD_X_TILED
:
3049 case I915_FORMAT_MOD_Y_TILED
:
3052 DRM_DEBUG_DRIVER("Unsupported modifier for initial FB: 0x%llx\n",
3057 mutex_lock(&dev
->struct_mutex
);
3058 obj
= i915_gem_object_create_stolen_for_preallocated(dev_priv
,
3062 mutex_unlock(&dev
->struct_mutex
);
3066 switch (plane_config
->tiling
) {
3067 case I915_TILING_NONE
:
3071 obj
->tiling_and_stride
= fb
->pitches
[0] | plane_config
->tiling
;
3074 MISSING_CASE(plane_config
->tiling
);
3078 mode_cmd
.pixel_format
= fb
->format
->format
;
3079 mode_cmd
.width
= fb
->width
;
3080 mode_cmd
.height
= fb
->height
;
3081 mode_cmd
.pitches
[0] = fb
->pitches
[0];
3082 mode_cmd
.modifier
[0] = fb
->modifier
;
3083 mode_cmd
.flags
= DRM_MODE_FB_MODIFIERS
;
3085 if (intel_framebuffer_init(to_intel_framebuffer(fb
), obj
, &mode_cmd
)) {
3086 DRM_DEBUG_KMS("intel fb init failed\n");
3091 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj
);
3095 i915_gem_object_put(obj
);
3100 intel_set_plane_visible(struct intel_crtc_state
*crtc_state
,
3101 struct intel_plane_state
*plane_state
,
3104 struct intel_plane
*plane
= to_intel_plane(plane_state
->base
.plane
);
3106 plane_state
->base
.visible
= visible
;
3109 crtc_state
->base
.plane_mask
|= drm_plane_mask(&plane
->base
);
3111 crtc_state
->base
.plane_mask
&= ~drm_plane_mask(&plane
->base
);
3114 static void fixup_active_planes(struct intel_crtc_state
*crtc_state
)
3116 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->base
.crtc
->dev
);
3117 struct drm_plane
*plane
;
3120 * Active_planes aliases if multiple "primary" or cursor planes
3121 * have been used on the same (or wrong) pipe. plane_mask uses
3122 * unique ids, hence we can use that to reconstruct active_planes.
3124 crtc_state
->active_planes
= 0;
3126 drm_for_each_plane_mask(plane
, &dev_priv
->drm
,
3127 crtc_state
->base
.plane_mask
)
3128 crtc_state
->active_planes
|= BIT(to_intel_plane(plane
)->id
);
3131 static void intel_plane_disable_noatomic(struct intel_crtc
*crtc
,
3132 struct intel_plane
*plane
)
3134 struct intel_crtc_state
*crtc_state
=
3135 to_intel_crtc_state(crtc
->base
.state
);
3136 struct intel_plane_state
*plane_state
=
3137 to_intel_plane_state(plane
->base
.state
);
3139 DRM_DEBUG_KMS("Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n",
3140 plane
->base
.base
.id
, plane
->base
.name
,
3141 crtc
->base
.base
.id
, crtc
->base
.name
);
3143 intel_set_plane_visible(crtc_state
, plane_state
, false);
3144 fixup_active_planes(crtc_state
);
3146 if (plane
->id
== PLANE_PRIMARY
)
3147 intel_pre_disable_primary_noatomic(&crtc
->base
);
3149 intel_disable_plane(plane
, crtc_state
);
3153 intel_find_initial_plane_obj(struct intel_crtc
*intel_crtc
,
3154 struct intel_initial_plane_config
*plane_config
)
3156 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3157 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3159 struct drm_i915_gem_object
*obj
;
3160 struct drm_plane
*primary
= intel_crtc
->base
.primary
;
3161 struct drm_plane_state
*plane_state
= primary
->state
;
3162 struct intel_plane
*intel_plane
= to_intel_plane(primary
);
3163 struct intel_plane_state
*intel_state
=
3164 to_intel_plane_state(plane_state
);
3165 struct drm_framebuffer
*fb
;
3167 if (!plane_config
->fb
)
3170 if (intel_alloc_initial_plane_obj(intel_crtc
, plane_config
)) {
3171 fb
= &plane_config
->fb
->base
;
3175 kfree(plane_config
->fb
);
3178 * Failed to alloc the obj, check to see if we should share
3179 * an fb with another CRTC instead
3181 for_each_crtc(dev
, c
) {
3182 struct intel_plane_state
*state
;
3184 if (c
== &intel_crtc
->base
)
3187 if (!to_intel_crtc(c
)->active
)
3190 state
= to_intel_plane_state(c
->primary
->state
);
3194 if (intel_plane_ggtt_offset(state
) == plane_config
->base
) {
3195 fb
= state
->base
.fb
;
3196 drm_framebuffer_get(fb
);
3202 * We've failed to reconstruct the BIOS FB. Current display state
3203 * indicates that the primary plane is visible, but has a NULL FB,
3204 * which will lead to problems later if we don't fix it up. The
3205 * simplest solution is to just disable the primary plane now and
3206 * pretend the BIOS never had it enabled.
3208 intel_plane_disable_noatomic(intel_crtc
, intel_plane
);
3213 intel_state
->base
.rotation
= plane_config
->rotation
;
3214 intel_fill_fb_ggtt_view(&intel_state
->view
, fb
,
3215 intel_state
->base
.rotation
);
3216 intel_state
->color_plane
[0].stride
=
3217 intel_fb_pitch(fb
, 0, intel_state
->base
.rotation
);
3219 mutex_lock(&dev
->struct_mutex
);
3221 intel_pin_and_fence_fb_obj(fb
,
3223 intel_plane_uses_fence(intel_state
),
3224 &intel_state
->flags
);
3225 mutex_unlock(&dev
->struct_mutex
);
3226 if (IS_ERR(intel_state
->vma
)) {
3227 DRM_ERROR("failed to pin boot fb on pipe %d: %li\n",
3228 intel_crtc
->pipe
, PTR_ERR(intel_state
->vma
));
3230 intel_state
->vma
= NULL
;
3231 drm_framebuffer_put(fb
);
3235 obj
= intel_fb_obj(fb
);
3236 intel_fb_obj_flush(obj
, ORIGIN_DIRTYFB
);
3238 plane_state
->src_x
= 0;
3239 plane_state
->src_y
= 0;
3240 plane_state
->src_w
= fb
->width
<< 16;
3241 plane_state
->src_h
= fb
->height
<< 16;
3243 plane_state
->crtc_x
= 0;
3244 plane_state
->crtc_y
= 0;
3245 plane_state
->crtc_w
= fb
->width
;
3246 plane_state
->crtc_h
= fb
->height
;
3248 intel_state
->base
.src
= drm_plane_state_src(plane_state
);
3249 intel_state
->base
.dst
= drm_plane_state_dest(plane_state
);
3251 if (i915_gem_object_is_tiled(obj
))
3252 dev_priv
->preserve_bios_swizzle
= true;
3254 plane_state
->fb
= fb
;
3255 plane_state
->crtc
= &intel_crtc
->base
;
3257 atomic_or(to_intel_plane(primary
)->frontbuffer_bit
,
3258 &obj
->frontbuffer_bits
);
3261 static int skl_max_plane_width(const struct drm_framebuffer
*fb
,
3263 unsigned int rotation
)
3265 int cpp
= fb
->format
->cpp
[color_plane
];
3267 switch (fb
->modifier
) {
3268 case DRM_FORMAT_MOD_LINEAR
:
3269 case I915_FORMAT_MOD_X_TILED
:
3271 case I915_FORMAT_MOD_Y_TILED_CCS
:
3272 case I915_FORMAT_MOD_Yf_TILED_CCS
:
3273 /* FIXME AUX plane? */
3274 case I915_FORMAT_MOD_Y_TILED
:
3275 case I915_FORMAT_MOD_Yf_TILED
:
3281 MISSING_CASE(fb
->modifier
);
3286 static int glk_max_plane_width(const struct drm_framebuffer
*fb
,
3288 unsigned int rotation
)
3290 int cpp
= fb
->format
->cpp
[color_plane
];
3292 switch (fb
->modifier
) {
3293 case DRM_FORMAT_MOD_LINEAR
:
3294 case I915_FORMAT_MOD_X_TILED
:
3299 case I915_FORMAT_MOD_Y_TILED_CCS
:
3300 case I915_FORMAT_MOD_Yf_TILED_CCS
:
3301 /* FIXME AUX plane? */
3302 case I915_FORMAT_MOD_Y_TILED
:
3303 case I915_FORMAT_MOD_Yf_TILED
:
3309 MISSING_CASE(fb
->modifier
);
3314 static int icl_max_plane_width(const struct drm_framebuffer
*fb
,
3316 unsigned int rotation
)
3321 static bool skl_check_main_ccs_coordinates(struct intel_plane_state
*plane_state
,
3322 int main_x
, int main_y
, u32 main_offset
)
3324 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
3325 int hsub
= fb
->format
->hsub
;
3326 int vsub
= fb
->format
->vsub
;
3327 int aux_x
= plane_state
->color_plane
[1].x
;
3328 int aux_y
= plane_state
->color_plane
[1].y
;
3329 u32 aux_offset
= plane_state
->color_plane
[1].offset
;
3330 u32 alignment
= intel_surf_alignment(fb
, 1);
3332 while (aux_offset
>= main_offset
&& aux_y
<= main_y
) {
3335 if (aux_x
== main_x
&& aux_y
== main_y
)
3338 if (aux_offset
== 0)
3343 aux_offset
= intel_plane_adjust_aligned_offset(&x
, &y
, plane_state
, 1,
3344 aux_offset
, aux_offset
- alignment
);
3345 aux_x
= x
* hsub
+ aux_x
% hsub
;
3346 aux_y
= y
* vsub
+ aux_y
% vsub
;
3349 if (aux_x
!= main_x
|| aux_y
!= main_y
)
3352 plane_state
->color_plane
[1].offset
= aux_offset
;
3353 plane_state
->color_plane
[1].x
= aux_x
;
3354 plane_state
->color_plane
[1].y
= aux_y
;
3359 static int skl_check_main_surface(struct intel_plane_state
*plane_state
)
3361 struct drm_i915_private
*dev_priv
= to_i915(plane_state
->base
.plane
->dev
);
3362 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
3363 unsigned int rotation
= plane_state
->base
.rotation
;
3364 int x
= plane_state
->base
.src
.x1
>> 16;
3365 int y
= plane_state
->base
.src
.y1
>> 16;
3366 int w
= drm_rect_width(&plane_state
->base
.src
) >> 16;
3367 int h
= drm_rect_height(&plane_state
->base
.src
) >> 16;
3369 int max_height
= 4096;
3370 u32 alignment
, offset
, aux_offset
= plane_state
->color_plane
[1].offset
;
3372 if (INTEL_GEN(dev_priv
) >= 11)
3373 max_width
= icl_max_plane_width(fb
, 0, rotation
);
3374 else if (INTEL_GEN(dev_priv
) >= 10 || IS_GEMINILAKE(dev_priv
))
3375 max_width
= glk_max_plane_width(fb
, 0, rotation
);
3377 max_width
= skl_max_plane_width(fb
, 0, rotation
);
3379 if (w
> max_width
|| h
> max_height
) {
3380 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
3381 w
, h
, max_width
, max_height
);
3385 intel_add_fb_offsets(&x
, &y
, plane_state
, 0);
3386 offset
= intel_plane_compute_aligned_offset(&x
, &y
, plane_state
, 0);
3387 alignment
= intel_surf_alignment(fb
, 0);
3390 * AUX surface offset is specified as the distance from the
3391 * main surface offset, and it must be non-negative. Make
3392 * sure that is what we will get.
3394 if (offset
> aux_offset
)
3395 offset
= intel_plane_adjust_aligned_offset(&x
, &y
, plane_state
, 0,
3396 offset
, aux_offset
& ~(alignment
- 1));
3399 * When using an X-tiled surface, the plane blows up
3400 * if the x offset + width exceed the stride.
3402 * TODO: linear and Y-tiled seem fine, Yf untested,
3404 if (fb
->modifier
== I915_FORMAT_MOD_X_TILED
) {
3405 int cpp
= fb
->format
->cpp
[0];
3407 while ((x
+ w
) * cpp
> plane_state
->color_plane
[0].stride
) {
3409 DRM_DEBUG_KMS("Unable to find suitable display surface offset due to X-tiling\n");
3413 offset
= intel_plane_adjust_aligned_offset(&x
, &y
, plane_state
, 0,
3414 offset
, offset
- alignment
);
3419 * CCS AUX surface doesn't have its own x/y offsets, we must make sure
3420 * they match with the main surface x/y offsets.
3422 if (is_ccs_modifier(fb
->modifier
)) {
3423 while (!skl_check_main_ccs_coordinates(plane_state
, x
, y
, offset
)) {
3427 offset
= intel_plane_adjust_aligned_offset(&x
, &y
, plane_state
, 0,
3428 offset
, offset
- alignment
);
3431 if (x
!= plane_state
->color_plane
[1].x
|| y
!= plane_state
->color_plane
[1].y
) {
3432 DRM_DEBUG_KMS("Unable to find suitable display surface offset due to CCS\n");
3437 plane_state
->color_plane
[0].offset
= offset
;
3438 plane_state
->color_plane
[0].x
= x
;
3439 plane_state
->color_plane
[0].y
= y
;
3442 * Put the final coordinates back so that the src
3443 * coordinate checks will see the right values.
3445 drm_rect_translate(&plane_state
->base
.src
,
3446 (x
<< 16) - plane_state
->base
.src
.x1
,
3447 (y
<< 16) - plane_state
->base
.src
.y1
);
3452 static int skl_check_nv12_aux_surface(struct intel_plane_state
*plane_state
)
3454 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
3455 unsigned int rotation
= plane_state
->base
.rotation
;
3456 int max_width
= skl_max_plane_width(fb
, 1, rotation
);
3457 int max_height
= 4096;
3458 int x
= plane_state
->base
.src
.x1
>> 17;
3459 int y
= plane_state
->base
.src
.y1
>> 17;
3460 int w
= drm_rect_width(&plane_state
->base
.src
) >> 17;
3461 int h
= drm_rect_height(&plane_state
->base
.src
) >> 17;
3464 intel_add_fb_offsets(&x
, &y
, plane_state
, 1);
3465 offset
= intel_plane_compute_aligned_offset(&x
, &y
, plane_state
, 1);
3467 /* FIXME not quite sure how/if these apply to the chroma plane */
3468 if (w
> max_width
|| h
> max_height
) {
3469 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
3470 w
, h
, max_width
, max_height
);
3474 plane_state
->color_plane
[1].offset
= offset
;
3475 plane_state
->color_plane
[1].x
= x
;
3476 plane_state
->color_plane
[1].y
= y
;
3481 static int skl_check_ccs_aux_surface(struct intel_plane_state
*plane_state
)
3483 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
3484 int src_x
= plane_state
->base
.src
.x1
>> 16;
3485 int src_y
= plane_state
->base
.src
.y1
>> 16;
3486 int hsub
= fb
->format
->hsub
;
3487 int vsub
= fb
->format
->vsub
;
3488 int x
= src_x
/ hsub
;
3489 int y
= src_y
/ vsub
;
3492 intel_add_fb_offsets(&x
, &y
, plane_state
, 1);
3493 offset
= intel_plane_compute_aligned_offset(&x
, &y
, plane_state
, 1);
3495 plane_state
->color_plane
[1].offset
= offset
;
3496 plane_state
->color_plane
[1].x
= x
* hsub
+ src_x
% hsub
;
3497 plane_state
->color_plane
[1].y
= y
* vsub
+ src_y
% vsub
;
3502 int skl_check_plane_surface(struct intel_plane_state
*plane_state
)
3504 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
3507 ret
= intel_plane_compute_gtt(plane_state
);
3511 if (!plane_state
->base
.visible
)
3515 * Handle the AUX surface first since
3516 * the main surface setup depends on it.
3518 if (is_planar_yuv_format(fb
->format
->format
)) {
3519 ret
= skl_check_nv12_aux_surface(plane_state
);
3522 } else if (is_ccs_modifier(fb
->modifier
)) {
3523 ret
= skl_check_ccs_aux_surface(plane_state
);
3527 plane_state
->color_plane
[1].offset
= ~0xfff;
3528 plane_state
->color_plane
[1].x
= 0;
3529 plane_state
->color_plane
[1].y
= 0;
3532 ret
= skl_check_main_surface(plane_state
);
3540 i9xx_plane_max_stride(struct intel_plane
*plane
,
3541 u32 pixel_format
, u64 modifier
,
3542 unsigned int rotation
)
3544 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
3546 if (!HAS_GMCH(dev_priv
)) {
3548 } else if (INTEL_GEN(dev_priv
) >= 4) {
3549 if (modifier
== I915_FORMAT_MOD_X_TILED
)
3553 } else if (INTEL_GEN(dev_priv
) >= 3) {
3554 if (modifier
== I915_FORMAT_MOD_X_TILED
)
3559 if (plane
->i9xx_plane
== PLANE_C
)
3566 static u32
i9xx_plane_ctl_crtc(const struct intel_crtc_state
*crtc_state
)
3568 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
3569 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
3572 if (crtc_state
->gamma_enable
)
3573 dspcntr
|= DISPPLANE_GAMMA_ENABLE
;
3575 if (crtc_state
->csc_enable
)
3576 dspcntr
|= DISPPLANE_PIPE_CSC_ENABLE
;
3578 if (INTEL_GEN(dev_priv
) < 5)
3579 dspcntr
|= DISPPLANE_SEL_PIPE(crtc
->pipe
);
3584 static u32
i9xx_plane_ctl(const struct intel_crtc_state
*crtc_state
,
3585 const struct intel_plane_state
*plane_state
)
3587 struct drm_i915_private
*dev_priv
=
3588 to_i915(plane_state
->base
.plane
->dev
);
3589 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
3590 unsigned int rotation
= plane_state
->base
.rotation
;
3593 dspcntr
= DISPLAY_PLANE_ENABLE
;
3595 if (IS_G4X(dev_priv
) || IS_GEN(dev_priv
, 5) ||
3596 IS_GEN(dev_priv
, 6) || IS_IVYBRIDGE(dev_priv
))
3597 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
3599 switch (fb
->format
->format
) {
3601 dspcntr
|= DISPPLANE_8BPP
;
3603 case DRM_FORMAT_XRGB1555
:
3604 dspcntr
|= DISPPLANE_BGRX555
;
3606 case DRM_FORMAT_RGB565
:
3607 dspcntr
|= DISPPLANE_BGRX565
;
3609 case DRM_FORMAT_XRGB8888
:
3610 dspcntr
|= DISPPLANE_BGRX888
;
3612 case DRM_FORMAT_XBGR8888
:
3613 dspcntr
|= DISPPLANE_RGBX888
;
3615 case DRM_FORMAT_XRGB2101010
:
3616 dspcntr
|= DISPPLANE_BGRX101010
;
3618 case DRM_FORMAT_XBGR2101010
:
3619 dspcntr
|= DISPPLANE_RGBX101010
;
3622 MISSING_CASE(fb
->format
->format
);
3626 if (INTEL_GEN(dev_priv
) >= 4 &&
3627 fb
->modifier
== I915_FORMAT_MOD_X_TILED
)
3628 dspcntr
|= DISPPLANE_TILED
;
3630 if (rotation
& DRM_MODE_ROTATE_180
)
3631 dspcntr
|= DISPPLANE_ROTATE_180
;
3633 if (rotation
& DRM_MODE_REFLECT_X
)
3634 dspcntr
|= DISPPLANE_MIRROR
;
3639 int i9xx_check_plane_surface(struct intel_plane_state
*plane_state
)
3641 struct drm_i915_private
*dev_priv
=
3642 to_i915(plane_state
->base
.plane
->dev
);
3647 ret
= intel_plane_compute_gtt(plane_state
);
3651 if (!plane_state
->base
.visible
)
3654 src_x
= plane_state
->base
.src
.x1
>> 16;
3655 src_y
= plane_state
->base
.src
.y1
>> 16;
3657 intel_add_fb_offsets(&src_x
, &src_y
, plane_state
, 0);
3659 if (INTEL_GEN(dev_priv
) >= 4)
3660 offset
= intel_plane_compute_aligned_offset(&src_x
, &src_y
,
3666 * Put the final coordinates back so that the src
3667 * coordinate checks will see the right values.
3669 drm_rect_translate(&plane_state
->base
.src
,
3670 (src_x
<< 16) - plane_state
->base
.src
.x1
,
3671 (src_y
<< 16) - plane_state
->base
.src
.y1
);
3673 /* HSW/BDW do this automagically in hardware */
3674 if (!IS_HASWELL(dev_priv
) && !IS_BROADWELL(dev_priv
)) {
3675 unsigned int rotation
= plane_state
->base
.rotation
;
3676 int src_w
= drm_rect_width(&plane_state
->base
.src
) >> 16;
3677 int src_h
= drm_rect_height(&plane_state
->base
.src
) >> 16;
3679 if (rotation
& DRM_MODE_ROTATE_180
) {
3682 } else if (rotation
& DRM_MODE_REFLECT_X
) {
3687 plane_state
->color_plane
[0].offset
= offset
;
3688 plane_state
->color_plane
[0].x
= src_x
;
3689 plane_state
->color_plane
[0].y
= src_y
;
3695 i9xx_plane_check(struct intel_crtc_state
*crtc_state
,
3696 struct intel_plane_state
*plane_state
)
3700 ret
= chv_plane_check_rotation(plane_state
);
3704 ret
= drm_atomic_helper_check_plane_state(&plane_state
->base
,
3706 DRM_PLANE_HELPER_NO_SCALING
,
3707 DRM_PLANE_HELPER_NO_SCALING
,
3712 ret
= i9xx_check_plane_surface(plane_state
);
3716 if (!plane_state
->base
.visible
)
3719 ret
= intel_plane_check_src_coordinates(plane_state
);
3723 plane_state
->ctl
= i9xx_plane_ctl(crtc_state
, plane_state
);
3728 static void i9xx_update_plane(struct intel_plane
*plane
,
3729 const struct intel_crtc_state
*crtc_state
,
3730 const struct intel_plane_state
*plane_state
)
3732 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
3733 enum i9xx_plane_id i9xx_plane
= plane
->i9xx_plane
;
3735 int x
= plane_state
->color_plane
[0].x
;
3736 int y
= plane_state
->color_plane
[0].y
;
3737 unsigned long irqflags
;
3741 dspcntr
= plane_state
->ctl
| i9xx_plane_ctl_crtc(crtc_state
);
3743 linear_offset
= intel_fb_xy_to_linear(x
, y
, plane_state
, 0);
3745 if (INTEL_GEN(dev_priv
) >= 4)
3746 dspaddr_offset
= plane_state
->color_plane
[0].offset
;
3748 dspaddr_offset
= linear_offset
;
3750 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
3752 I915_WRITE_FW(DSPSTRIDE(i9xx_plane
), plane_state
->color_plane
[0].stride
);
3754 if (INTEL_GEN(dev_priv
) < 4) {
3755 /* pipesrc and dspsize control the size that is scaled from,
3756 * which should always be the user's requested size.
3758 I915_WRITE_FW(DSPPOS(i9xx_plane
), 0);
3759 I915_WRITE_FW(DSPSIZE(i9xx_plane
),
3760 ((crtc_state
->pipe_src_h
- 1) << 16) |
3761 (crtc_state
->pipe_src_w
- 1));
3762 } else if (IS_CHERRYVIEW(dev_priv
) && i9xx_plane
== PLANE_B
) {
3763 I915_WRITE_FW(PRIMPOS(i9xx_plane
), 0);
3764 I915_WRITE_FW(PRIMSIZE(i9xx_plane
),
3765 ((crtc_state
->pipe_src_h
- 1) << 16) |
3766 (crtc_state
->pipe_src_w
- 1));
3767 I915_WRITE_FW(PRIMCNSTALPHA(i9xx_plane
), 0);
3770 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
3771 I915_WRITE_FW(DSPOFFSET(i9xx_plane
), (y
<< 16) | x
);
3772 } else if (INTEL_GEN(dev_priv
) >= 4) {
3773 I915_WRITE_FW(DSPLINOFF(i9xx_plane
), linear_offset
);
3774 I915_WRITE_FW(DSPTILEOFF(i9xx_plane
), (y
<< 16) | x
);
3778 * The control register self-arms if the plane was previously
3779 * disabled. Try to make the plane enable atomic by writing
3780 * the control register just before the surface register.
3782 I915_WRITE_FW(DSPCNTR(i9xx_plane
), dspcntr
);
3783 if (INTEL_GEN(dev_priv
) >= 4)
3784 I915_WRITE_FW(DSPSURF(i9xx_plane
),
3785 intel_plane_ggtt_offset(plane_state
) +
3788 I915_WRITE_FW(DSPADDR(i9xx_plane
),
3789 intel_plane_ggtt_offset(plane_state
) +
3792 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
3795 static void i9xx_disable_plane(struct intel_plane
*plane
,
3796 const struct intel_crtc_state
*crtc_state
)
3798 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
3799 enum i9xx_plane_id i9xx_plane
= plane
->i9xx_plane
;
3800 unsigned long irqflags
;
3804 * DSPCNTR pipe gamma enable on g4x+ and pipe csc
3805 * enable on ilk+ affect the pipe bottom color as
3806 * well, so we must configure them even if the plane
3809 * On pre-g4x there is no way to gamma correct the
3810 * pipe bottom color but we'll keep on doing this
3811 * anyway so that the crtc state readout works correctly.
3813 dspcntr
= i9xx_plane_ctl_crtc(crtc_state
);
3815 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
3817 I915_WRITE_FW(DSPCNTR(i9xx_plane
), dspcntr
);
3818 if (INTEL_GEN(dev_priv
) >= 4)
3819 I915_WRITE_FW(DSPSURF(i9xx_plane
), 0);
3821 I915_WRITE_FW(DSPADDR(i9xx_plane
), 0);
3823 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
3826 static bool i9xx_plane_get_hw_state(struct intel_plane
*plane
,
3829 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
3830 enum intel_display_power_domain power_domain
;
3831 enum i9xx_plane_id i9xx_plane
= plane
->i9xx_plane
;
3832 intel_wakeref_t wakeref
;
3837 * Not 100% correct for planes that can move between pipes,
3838 * but that's only the case for gen2-4 which don't have any
3839 * display power wells.
3841 power_domain
= POWER_DOMAIN_PIPE(plane
->pipe
);
3842 wakeref
= intel_display_power_get_if_enabled(dev_priv
, power_domain
);
3846 val
= I915_READ(DSPCNTR(i9xx_plane
));
3848 ret
= val
& DISPLAY_PLANE_ENABLE
;
3850 if (INTEL_GEN(dev_priv
) >= 5)
3851 *pipe
= plane
->pipe
;
3853 *pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
3854 DISPPLANE_SEL_PIPE_SHIFT
;
3856 intel_display_power_put(dev_priv
, power_domain
, wakeref
);
3861 static void skl_detach_scaler(struct intel_crtc
*intel_crtc
, int id
)
3863 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3864 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3866 I915_WRITE(SKL_PS_CTRL(intel_crtc
->pipe
, id
), 0);
3867 I915_WRITE(SKL_PS_WIN_POS(intel_crtc
->pipe
, id
), 0);
3868 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc
->pipe
, id
), 0);
3872 * This function detaches (aka. unbinds) unused scalers in hardware
3874 static void skl_detach_scalers(const struct intel_crtc_state
*crtc_state
)
3876 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
3877 const struct intel_crtc_scaler_state
*scaler_state
=
3878 &crtc_state
->scaler_state
;
3881 /* loop through and disable scalers that aren't in use */
3882 for (i
= 0; i
< intel_crtc
->num_scalers
; i
++) {
3883 if (!scaler_state
->scalers
[i
].in_use
)
3884 skl_detach_scaler(intel_crtc
, i
);
3888 static unsigned int skl_plane_stride_mult(const struct drm_framebuffer
*fb
,
3889 int color_plane
, unsigned int rotation
)
3892 * The stride is either expressed as a multiple of 64 bytes chunks for
3893 * linear buffers or in number of tiles for tiled buffers.
3895 if (fb
->modifier
== DRM_FORMAT_MOD_LINEAR
)
3897 else if (drm_rotation_90_or_270(rotation
))
3898 return intel_tile_height(fb
, color_plane
);
3900 return intel_tile_width_bytes(fb
, color_plane
);
3903 u32
skl_plane_stride(const struct intel_plane_state
*plane_state
,
3906 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
3907 unsigned int rotation
= plane_state
->base
.rotation
;
3908 u32 stride
= plane_state
->color_plane
[color_plane
].stride
;
3910 if (color_plane
>= fb
->format
->num_planes
)
3913 return stride
/ skl_plane_stride_mult(fb
, color_plane
, rotation
);
3916 static u32
skl_plane_ctl_format(u32 pixel_format
)
3918 switch (pixel_format
) {
3920 return PLANE_CTL_FORMAT_INDEXED
;
3921 case DRM_FORMAT_RGB565
:
3922 return PLANE_CTL_FORMAT_RGB_565
;
3923 case DRM_FORMAT_XBGR8888
:
3924 case DRM_FORMAT_ABGR8888
:
3925 return PLANE_CTL_FORMAT_XRGB_8888
| PLANE_CTL_ORDER_RGBX
;
3926 case DRM_FORMAT_XRGB8888
:
3927 case DRM_FORMAT_ARGB8888
:
3928 return PLANE_CTL_FORMAT_XRGB_8888
;
3929 case DRM_FORMAT_XRGB2101010
:
3930 return PLANE_CTL_FORMAT_XRGB_2101010
;
3931 case DRM_FORMAT_XBGR2101010
:
3932 return PLANE_CTL_ORDER_RGBX
| PLANE_CTL_FORMAT_XRGB_2101010
;
3933 case DRM_FORMAT_XBGR16161616F
:
3934 case DRM_FORMAT_ABGR16161616F
:
3935 return PLANE_CTL_FORMAT_XRGB_16161616F
| PLANE_CTL_ORDER_RGBX
;
3936 case DRM_FORMAT_XRGB16161616F
:
3937 case DRM_FORMAT_ARGB16161616F
:
3938 return PLANE_CTL_FORMAT_XRGB_16161616F
;
3939 case DRM_FORMAT_YUYV
:
3940 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_YUYV
;
3941 case DRM_FORMAT_YVYU
:
3942 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_YVYU
;
3943 case DRM_FORMAT_UYVY
:
3944 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_UYVY
;
3945 case DRM_FORMAT_VYUY
:
3946 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_VYUY
;
3947 case DRM_FORMAT_NV12
:
3948 return PLANE_CTL_FORMAT_NV12
;
3949 case DRM_FORMAT_P010
:
3950 return PLANE_CTL_FORMAT_P010
;
3951 case DRM_FORMAT_P012
:
3952 return PLANE_CTL_FORMAT_P012
;
3953 case DRM_FORMAT_P016
:
3954 return PLANE_CTL_FORMAT_P016
;
3955 case DRM_FORMAT_Y210
:
3956 return PLANE_CTL_FORMAT_Y210
;
3957 case DRM_FORMAT_Y212
:
3958 return PLANE_CTL_FORMAT_Y212
;
3959 case DRM_FORMAT_Y216
:
3960 return PLANE_CTL_FORMAT_Y216
;
3961 case DRM_FORMAT_XVYU2101010
:
3962 return PLANE_CTL_FORMAT_Y410
;
3963 case DRM_FORMAT_XVYU12_16161616
:
3964 return PLANE_CTL_FORMAT_Y412
;
3965 case DRM_FORMAT_XVYU16161616
:
3966 return PLANE_CTL_FORMAT_Y416
;
3968 MISSING_CASE(pixel_format
);
3974 static u32
skl_plane_ctl_alpha(const struct intel_plane_state
*plane_state
)
3976 if (!plane_state
->base
.fb
->format
->has_alpha
)
3977 return PLANE_CTL_ALPHA_DISABLE
;
3979 switch (plane_state
->base
.pixel_blend_mode
) {
3980 case DRM_MODE_BLEND_PIXEL_NONE
:
3981 return PLANE_CTL_ALPHA_DISABLE
;
3982 case DRM_MODE_BLEND_PREMULTI
:
3983 return PLANE_CTL_ALPHA_SW_PREMULTIPLY
;
3984 case DRM_MODE_BLEND_COVERAGE
:
3985 return PLANE_CTL_ALPHA_HW_PREMULTIPLY
;
3987 MISSING_CASE(plane_state
->base
.pixel_blend_mode
);
3988 return PLANE_CTL_ALPHA_DISABLE
;
3992 static u32
glk_plane_color_ctl_alpha(const struct intel_plane_state
*plane_state
)
3994 if (!plane_state
->base
.fb
->format
->has_alpha
)
3995 return PLANE_COLOR_ALPHA_DISABLE
;
3997 switch (plane_state
->base
.pixel_blend_mode
) {
3998 case DRM_MODE_BLEND_PIXEL_NONE
:
3999 return PLANE_COLOR_ALPHA_DISABLE
;
4000 case DRM_MODE_BLEND_PREMULTI
:
4001 return PLANE_COLOR_ALPHA_SW_PREMULTIPLY
;
4002 case DRM_MODE_BLEND_COVERAGE
:
4003 return PLANE_COLOR_ALPHA_HW_PREMULTIPLY
;
4005 MISSING_CASE(plane_state
->base
.pixel_blend_mode
);
4006 return PLANE_COLOR_ALPHA_DISABLE
;
4010 static u32
skl_plane_ctl_tiling(u64 fb_modifier
)
4012 switch (fb_modifier
) {
4013 case DRM_FORMAT_MOD_LINEAR
:
4015 case I915_FORMAT_MOD_X_TILED
:
4016 return PLANE_CTL_TILED_X
;
4017 case I915_FORMAT_MOD_Y_TILED
:
4018 return PLANE_CTL_TILED_Y
;
4019 case I915_FORMAT_MOD_Y_TILED_CCS
:
4020 return PLANE_CTL_TILED_Y
| PLANE_CTL_RENDER_DECOMPRESSION_ENABLE
;
4021 case I915_FORMAT_MOD_Yf_TILED
:
4022 return PLANE_CTL_TILED_YF
;
4023 case I915_FORMAT_MOD_Yf_TILED_CCS
:
4024 return PLANE_CTL_TILED_YF
| PLANE_CTL_RENDER_DECOMPRESSION_ENABLE
;
4026 MISSING_CASE(fb_modifier
);
4032 static u32
skl_plane_ctl_rotate(unsigned int rotate
)
4035 case DRM_MODE_ROTATE_0
:
4038 * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
4039 * while i915 HW rotation is clockwise, thats why this swapping.
4041 case DRM_MODE_ROTATE_90
:
4042 return PLANE_CTL_ROTATE_270
;
4043 case DRM_MODE_ROTATE_180
:
4044 return PLANE_CTL_ROTATE_180
;
4045 case DRM_MODE_ROTATE_270
:
4046 return PLANE_CTL_ROTATE_90
;
4048 MISSING_CASE(rotate
);
4054 static u32
cnl_plane_ctl_flip(unsigned int reflect
)
4059 case DRM_MODE_REFLECT_X
:
4060 return PLANE_CTL_FLIP_HORIZONTAL
;
4061 case DRM_MODE_REFLECT_Y
:
4063 MISSING_CASE(reflect
);
4069 u32
skl_plane_ctl_crtc(const struct intel_crtc_state
*crtc_state
)
4071 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->base
.crtc
->dev
);
4074 if (INTEL_GEN(dev_priv
) >= 10 || IS_GEMINILAKE(dev_priv
))
4077 if (crtc_state
->gamma_enable
)
4078 plane_ctl
|= PLANE_CTL_PIPE_GAMMA_ENABLE
;
4080 if (crtc_state
->csc_enable
)
4081 plane_ctl
|= PLANE_CTL_PIPE_CSC_ENABLE
;
4086 u32
skl_plane_ctl(const struct intel_crtc_state
*crtc_state
,
4087 const struct intel_plane_state
*plane_state
)
4089 struct drm_i915_private
*dev_priv
=
4090 to_i915(plane_state
->base
.plane
->dev
);
4091 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
4092 unsigned int rotation
= plane_state
->base
.rotation
;
4093 const struct drm_intel_sprite_colorkey
*key
= &plane_state
->ckey
;
4096 plane_ctl
= PLANE_CTL_ENABLE
;
4098 if (INTEL_GEN(dev_priv
) < 10 && !IS_GEMINILAKE(dev_priv
)) {
4099 plane_ctl
|= skl_plane_ctl_alpha(plane_state
);
4100 plane_ctl
|= PLANE_CTL_PLANE_GAMMA_DISABLE
;
4102 if (plane_state
->base
.color_encoding
== DRM_COLOR_YCBCR_BT709
)
4103 plane_ctl
|= PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709
;
4105 if (plane_state
->base
.color_range
== DRM_COLOR_YCBCR_FULL_RANGE
)
4106 plane_ctl
|= PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE
;
4109 plane_ctl
|= skl_plane_ctl_format(fb
->format
->format
);
4110 plane_ctl
|= skl_plane_ctl_tiling(fb
->modifier
);
4111 plane_ctl
|= skl_plane_ctl_rotate(rotation
& DRM_MODE_ROTATE_MASK
);
4113 if (INTEL_GEN(dev_priv
) >= 10)
4114 plane_ctl
|= cnl_plane_ctl_flip(rotation
&
4115 DRM_MODE_REFLECT_MASK
);
4117 if (key
->flags
& I915_SET_COLORKEY_DESTINATION
)
4118 plane_ctl
|= PLANE_CTL_KEY_ENABLE_DESTINATION
;
4119 else if (key
->flags
& I915_SET_COLORKEY_SOURCE
)
4120 plane_ctl
|= PLANE_CTL_KEY_ENABLE_SOURCE
;
4125 u32
glk_plane_color_ctl_crtc(const struct intel_crtc_state
*crtc_state
)
4127 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->base
.crtc
->dev
);
4128 u32 plane_color_ctl
= 0;
4130 if (INTEL_GEN(dev_priv
) >= 11)
4131 return plane_color_ctl
;
4133 if (crtc_state
->gamma_enable
)
4134 plane_color_ctl
|= PLANE_COLOR_PIPE_GAMMA_ENABLE
;
4136 if (crtc_state
->csc_enable
)
4137 plane_color_ctl
|= PLANE_COLOR_PIPE_CSC_ENABLE
;
4139 return plane_color_ctl
;
4142 u32
glk_plane_color_ctl(const struct intel_crtc_state
*crtc_state
,
4143 const struct intel_plane_state
*plane_state
)
4145 struct drm_i915_private
*dev_priv
=
4146 to_i915(plane_state
->base
.plane
->dev
);
4147 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
4148 struct intel_plane
*plane
= to_intel_plane(plane_state
->base
.plane
);
4149 u32 plane_color_ctl
= 0;
4151 plane_color_ctl
|= PLANE_COLOR_PLANE_GAMMA_DISABLE
;
4152 plane_color_ctl
|= glk_plane_color_ctl_alpha(plane_state
);
4154 if (fb
->format
->is_yuv
&& !icl_is_hdr_plane(dev_priv
, plane
->id
)) {
4155 if (plane_state
->base
.color_encoding
== DRM_COLOR_YCBCR_BT709
)
4156 plane_color_ctl
|= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709
;
4158 plane_color_ctl
|= PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709
;
4160 if (plane_state
->base
.color_range
== DRM_COLOR_YCBCR_FULL_RANGE
)
4161 plane_color_ctl
|= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE
;
4162 } else if (fb
->format
->is_yuv
) {
4163 plane_color_ctl
|= PLANE_COLOR_INPUT_CSC_ENABLE
;
4166 return plane_color_ctl
;
4170 __intel_display_resume(struct drm_device
*dev
,
4171 struct drm_atomic_state
*state
,
4172 struct drm_modeset_acquire_ctx
*ctx
)
4174 struct drm_crtc_state
*crtc_state
;
4175 struct drm_crtc
*crtc
;
4178 intel_modeset_setup_hw_state(dev
, ctx
);
4179 i915_redisable_vga(to_i915(dev
));
4185 * We've duplicated the state, pointers to the old state are invalid.
4187 * Don't attempt to use the old state until we commit the duplicated state.
4189 for_each_new_crtc_in_state(state
, crtc
, crtc_state
, i
) {
4191 * Force recalculation even if we restore
4192 * current state. With fast modeset this may not result
4193 * in a modeset when the state is compatible.
4195 crtc_state
->mode_changed
= true;
4198 /* ignore any reset values/BIOS leftovers in the WM registers */
4199 if (!HAS_GMCH(to_i915(dev
)))
4200 to_intel_atomic_state(state
)->skip_intermediate_wm
= true;
4202 ret
= drm_atomic_helper_commit_duplicated_state(state
, ctx
);
4204 WARN_ON(ret
== -EDEADLK
);
4208 static bool gpu_reset_clobbers_display(struct drm_i915_private
*dev_priv
)
4210 return (INTEL_INFO(dev_priv
)->gpu_reset_clobbers_display
&&
4211 intel_has_gpu_reset(dev_priv
));
4214 void intel_prepare_reset(struct drm_i915_private
*dev_priv
)
4216 struct drm_device
*dev
= &dev_priv
->drm
;
4217 struct drm_modeset_acquire_ctx
*ctx
= &dev_priv
->reset_ctx
;
4218 struct drm_atomic_state
*state
;
4221 /* reset doesn't touch the display */
4222 if (!i915_modparams
.force_reset_modeset_test
&&
4223 !gpu_reset_clobbers_display(dev_priv
))
4226 /* We have a modeset vs reset deadlock, defensively unbreak it. */
4227 set_bit(I915_RESET_MODESET
, &dev_priv
->gpu_error
.flags
);
4228 wake_up_all(&dev_priv
->gpu_error
.wait_queue
);
4230 if (atomic_read(&dev_priv
->gpu_error
.pending_fb_pin
)) {
4231 DRM_DEBUG_KMS("Modeset potentially stuck, unbreaking through wedging\n");
4232 i915_gem_set_wedged(dev_priv
);
4236 * Need mode_config.mutex so that we don't
4237 * trample ongoing ->detect() and whatnot.
4239 mutex_lock(&dev
->mode_config
.mutex
);
4240 drm_modeset_acquire_init(ctx
, 0);
4242 ret
= drm_modeset_lock_all_ctx(dev
, ctx
);
4243 if (ret
!= -EDEADLK
)
4246 drm_modeset_backoff(ctx
);
4249 * Disabling the crtcs gracefully seems nicer. Also the
4250 * g33 docs say we should at least disable all the planes.
4252 state
= drm_atomic_helper_duplicate_state(dev
, ctx
);
4253 if (IS_ERR(state
)) {
4254 ret
= PTR_ERR(state
);
4255 DRM_ERROR("Duplicating state failed with %i\n", ret
);
4259 ret
= drm_atomic_helper_disable_all(dev
, ctx
);
4261 DRM_ERROR("Suspending crtc's failed with %i\n", ret
);
4262 drm_atomic_state_put(state
);
4266 dev_priv
->modeset_restore_state
= state
;
4267 state
->acquire_ctx
= ctx
;
4270 void intel_finish_reset(struct drm_i915_private
*dev_priv
)
4272 struct drm_device
*dev
= &dev_priv
->drm
;
4273 struct drm_modeset_acquire_ctx
*ctx
= &dev_priv
->reset_ctx
;
4274 struct drm_atomic_state
*state
;
4277 /* reset doesn't touch the display */
4278 if (!test_bit(I915_RESET_MODESET
, &dev_priv
->gpu_error
.flags
))
4281 state
= fetch_and_zero(&dev_priv
->modeset_restore_state
);
4285 /* reset doesn't touch the display */
4286 if (!gpu_reset_clobbers_display(dev_priv
)) {
4287 /* for testing only restore the display */
4288 ret
= __intel_display_resume(dev
, state
, ctx
);
4290 DRM_ERROR("Restoring old state failed with %i\n", ret
);
4293 * The display has been reset as well,
4294 * so need a full re-initialization.
4296 intel_pps_unlock_regs_wa(dev_priv
);
4297 intel_modeset_init_hw(dev
);
4298 intel_init_clock_gating(dev_priv
);
4300 spin_lock_irq(&dev_priv
->irq_lock
);
4301 if (dev_priv
->display
.hpd_irq_setup
)
4302 dev_priv
->display
.hpd_irq_setup(dev_priv
);
4303 spin_unlock_irq(&dev_priv
->irq_lock
);
4305 ret
= __intel_display_resume(dev
, state
, ctx
);
4307 DRM_ERROR("Restoring old state failed with %i\n", ret
);
4309 intel_hpd_init(dev_priv
);
4312 drm_atomic_state_put(state
);
4314 drm_modeset_drop_locks(ctx
);
4315 drm_modeset_acquire_fini(ctx
);
4316 mutex_unlock(&dev
->mode_config
.mutex
);
4318 clear_bit(I915_RESET_MODESET
, &dev_priv
->gpu_error
.flags
);
4321 static void icl_set_pipe_chicken(struct intel_crtc
*crtc
)
4323 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
4324 enum pipe pipe
= crtc
->pipe
;
4327 tmp
= I915_READ(PIPE_CHICKEN(pipe
));
4330 * Display WA #1153: icl
4331 * enable hardware to bypass the alpha math
4332 * and rounding for per-pixel values 00 and 0xff
4334 tmp
|= PER_PIXEL_ALPHA_BYPASS_EN
;
4336 * Display WA # 1605353570: icl
4337 * Set the pixel rounding bit to 1 for allowing
4338 * passthrough of Frame buffer pixels unmodified
4341 tmp
|= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU
;
4342 I915_WRITE(PIPE_CHICKEN(pipe
), tmp
);
4345 static void intel_update_pipe_config(const struct intel_crtc_state
*old_crtc_state
,
4346 const struct intel_crtc_state
*new_crtc_state
)
4348 struct intel_crtc
*crtc
= to_intel_crtc(new_crtc_state
->base
.crtc
);
4349 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
4351 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
4352 crtc
->base
.mode
= new_crtc_state
->base
.mode
;
4355 * Update pipe size and adjust fitter if needed: the reason for this is
4356 * that in compute_mode_changes we check the native mode (not the pfit
4357 * mode) to see if we can flip rather than do a full mode set. In the
4358 * fastboot case, we'll flip, but if we don't update the pipesrc and
4359 * pfit state, we'll end up with a big fb scanned out into the wrong
4363 I915_WRITE(PIPESRC(crtc
->pipe
),
4364 ((new_crtc_state
->pipe_src_w
- 1) << 16) |
4365 (new_crtc_state
->pipe_src_h
- 1));
4367 /* on skylake this is done by detaching scalers */
4368 if (INTEL_GEN(dev_priv
) >= 9) {
4369 skl_detach_scalers(new_crtc_state
);
4371 if (new_crtc_state
->pch_pfit
.enabled
)
4372 skylake_pfit_enable(new_crtc_state
);
4373 } else if (HAS_PCH_SPLIT(dev_priv
)) {
4374 if (new_crtc_state
->pch_pfit
.enabled
)
4375 ironlake_pfit_enable(new_crtc_state
);
4376 else if (old_crtc_state
->pch_pfit
.enabled
)
4377 ironlake_pfit_disable(old_crtc_state
);
4380 if (INTEL_GEN(dev_priv
) >= 11)
4381 icl_set_pipe_chicken(crtc
);
4384 static void intel_fdi_normal_train(struct intel_crtc
*crtc
)
4386 struct drm_device
*dev
= crtc
->base
.dev
;
4387 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4388 int pipe
= crtc
->pipe
;
4392 /* enable normal train */
4393 reg
= FDI_TX_CTL(pipe
);
4394 temp
= I915_READ(reg
);
4395 if (IS_IVYBRIDGE(dev_priv
)) {
4396 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
4397 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
4399 temp
&= ~FDI_LINK_TRAIN_NONE
;
4400 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
4402 I915_WRITE(reg
, temp
);
4404 reg
= FDI_RX_CTL(pipe
);
4405 temp
= I915_READ(reg
);
4406 if (HAS_PCH_CPT(dev_priv
)) {
4407 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
4408 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
4410 temp
&= ~FDI_LINK_TRAIN_NONE
;
4411 temp
|= FDI_LINK_TRAIN_NONE
;
4413 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
4415 /* wait one idle pattern time */
4419 /* IVB wants error correction enabled */
4420 if (IS_IVYBRIDGE(dev_priv
))
4421 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
4422 FDI_FE_ERRC_ENABLE
);
4425 /* The FDI link training functions for ILK/Ibexpeak. */
4426 static void ironlake_fdi_link_train(struct intel_crtc
*crtc
,
4427 const struct intel_crtc_state
*crtc_state
)
4429 struct drm_device
*dev
= crtc
->base
.dev
;
4430 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4431 int pipe
= crtc
->pipe
;
4435 /* FDI needs bits from pipe first */
4436 assert_pipe_enabled(dev_priv
, pipe
);
4438 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4440 reg
= FDI_RX_IMR(pipe
);
4441 temp
= I915_READ(reg
);
4442 temp
&= ~FDI_RX_SYMBOL_LOCK
;
4443 temp
&= ~FDI_RX_BIT_LOCK
;
4444 I915_WRITE(reg
, temp
);
4448 /* enable CPU FDI TX and PCH FDI RX */
4449 reg
= FDI_TX_CTL(pipe
);
4450 temp
= I915_READ(reg
);
4451 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
4452 temp
|= FDI_DP_PORT_WIDTH(crtc_state
->fdi_lanes
);
4453 temp
&= ~FDI_LINK_TRAIN_NONE
;
4454 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
4455 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
4457 reg
= FDI_RX_CTL(pipe
);
4458 temp
= I915_READ(reg
);
4459 temp
&= ~FDI_LINK_TRAIN_NONE
;
4460 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
4461 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
4466 /* Ironlake workaround, enable clock pointer after FDI enable*/
4467 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
4468 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
4469 FDI_RX_PHASE_SYNC_POINTER_EN
);
4471 reg
= FDI_RX_IIR(pipe
);
4472 for (tries
= 0; tries
< 5; tries
++) {
4473 temp
= I915_READ(reg
);
4474 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
4476 if ((temp
& FDI_RX_BIT_LOCK
)) {
4477 DRM_DEBUG_KMS("FDI train 1 done.\n");
4478 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
4483 DRM_ERROR("FDI train 1 fail!\n");
4486 reg
= FDI_TX_CTL(pipe
);
4487 temp
= I915_READ(reg
);
4488 temp
&= ~FDI_LINK_TRAIN_NONE
;
4489 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
4490 I915_WRITE(reg
, temp
);
4492 reg
= FDI_RX_CTL(pipe
);
4493 temp
= I915_READ(reg
);
4494 temp
&= ~FDI_LINK_TRAIN_NONE
;
4495 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
4496 I915_WRITE(reg
, temp
);
4501 reg
= FDI_RX_IIR(pipe
);
4502 for (tries
= 0; tries
< 5; tries
++) {
4503 temp
= I915_READ(reg
);
4504 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
4506 if (temp
& FDI_RX_SYMBOL_LOCK
) {
4507 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
4508 DRM_DEBUG_KMS("FDI train 2 done.\n");
4513 DRM_ERROR("FDI train 2 fail!\n");
4515 DRM_DEBUG_KMS("FDI train done\n");
4519 static const int snb_b_fdi_train_param
[] = {
4520 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
4521 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
4522 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
4523 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
4526 /* The FDI link training functions for SNB/Cougarpoint. */
4527 static void gen6_fdi_link_train(struct intel_crtc
*crtc
,
4528 const struct intel_crtc_state
*crtc_state
)
4530 struct drm_device
*dev
= crtc
->base
.dev
;
4531 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4532 int pipe
= crtc
->pipe
;
4536 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4538 reg
= FDI_RX_IMR(pipe
);
4539 temp
= I915_READ(reg
);
4540 temp
&= ~FDI_RX_SYMBOL_LOCK
;
4541 temp
&= ~FDI_RX_BIT_LOCK
;
4542 I915_WRITE(reg
, temp
);
4547 /* enable CPU FDI TX and PCH FDI RX */
4548 reg
= FDI_TX_CTL(pipe
);
4549 temp
= I915_READ(reg
);
4550 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
4551 temp
|= FDI_DP_PORT_WIDTH(crtc_state
->fdi_lanes
);
4552 temp
&= ~FDI_LINK_TRAIN_NONE
;
4553 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
4554 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
4556 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
4557 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
4559 I915_WRITE(FDI_RX_MISC(pipe
),
4560 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
4562 reg
= FDI_RX_CTL(pipe
);
4563 temp
= I915_READ(reg
);
4564 if (HAS_PCH_CPT(dev_priv
)) {
4565 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
4566 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
4568 temp
&= ~FDI_LINK_TRAIN_NONE
;
4569 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
4571 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
4576 for (i
= 0; i
< 4; i
++) {
4577 reg
= FDI_TX_CTL(pipe
);
4578 temp
= I915_READ(reg
);
4579 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
4580 temp
|= snb_b_fdi_train_param
[i
];
4581 I915_WRITE(reg
, temp
);
4586 for (retry
= 0; retry
< 5; retry
++) {
4587 reg
= FDI_RX_IIR(pipe
);
4588 temp
= I915_READ(reg
);
4589 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
4590 if (temp
& FDI_RX_BIT_LOCK
) {
4591 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
4592 DRM_DEBUG_KMS("FDI train 1 done.\n");
4601 DRM_ERROR("FDI train 1 fail!\n");
4604 reg
= FDI_TX_CTL(pipe
);
4605 temp
= I915_READ(reg
);
4606 temp
&= ~FDI_LINK_TRAIN_NONE
;
4607 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
4608 if (IS_GEN(dev_priv
, 6)) {
4609 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
4611 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
4613 I915_WRITE(reg
, temp
);
4615 reg
= FDI_RX_CTL(pipe
);
4616 temp
= I915_READ(reg
);
4617 if (HAS_PCH_CPT(dev_priv
)) {
4618 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
4619 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
4621 temp
&= ~FDI_LINK_TRAIN_NONE
;
4622 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
4624 I915_WRITE(reg
, temp
);
4629 for (i
= 0; i
< 4; i
++) {
4630 reg
= FDI_TX_CTL(pipe
);
4631 temp
= I915_READ(reg
);
4632 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
4633 temp
|= snb_b_fdi_train_param
[i
];
4634 I915_WRITE(reg
, temp
);
4639 for (retry
= 0; retry
< 5; retry
++) {
4640 reg
= FDI_RX_IIR(pipe
);
4641 temp
= I915_READ(reg
);
4642 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
4643 if (temp
& FDI_RX_SYMBOL_LOCK
) {
4644 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
4645 DRM_DEBUG_KMS("FDI train 2 done.\n");
4654 DRM_ERROR("FDI train 2 fail!\n");
4656 DRM_DEBUG_KMS("FDI train done.\n");
4659 /* Manual link training for Ivy Bridge A0 parts */
4660 static void ivb_manual_fdi_link_train(struct intel_crtc
*crtc
,
4661 const struct intel_crtc_state
*crtc_state
)
4663 struct drm_device
*dev
= crtc
->base
.dev
;
4664 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4665 int pipe
= crtc
->pipe
;
4669 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4671 reg
= FDI_RX_IMR(pipe
);
4672 temp
= I915_READ(reg
);
4673 temp
&= ~FDI_RX_SYMBOL_LOCK
;
4674 temp
&= ~FDI_RX_BIT_LOCK
;
4675 I915_WRITE(reg
, temp
);
4680 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
4681 I915_READ(FDI_RX_IIR(pipe
)));
4683 /* Try each vswing and preemphasis setting twice before moving on */
4684 for (j
= 0; j
< ARRAY_SIZE(snb_b_fdi_train_param
) * 2; j
++) {
4685 /* disable first in case we need to retry */
4686 reg
= FDI_TX_CTL(pipe
);
4687 temp
= I915_READ(reg
);
4688 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
4689 temp
&= ~FDI_TX_ENABLE
;
4690 I915_WRITE(reg
, temp
);
4692 reg
= FDI_RX_CTL(pipe
);
4693 temp
= I915_READ(reg
);
4694 temp
&= ~FDI_LINK_TRAIN_AUTO
;
4695 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
4696 temp
&= ~FDI_RX_ENABLE
;
4697 I915_WRITE(reg
, temp
);
4699 /* enable CPU FDI TX and PCH FDI RX */
4700 reg
= FDI_TX_CTL(pipe
);
4701 temp
= I915_READ(reg
);
4702 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
4703 temp
|= FDI_DP_PORT_WIDTH(crtc_state
->fdi_lanes
);
4704 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
4705 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
4706 temp
|= snb_b_fdi_train_param
[j
/2];
4707 temp
|= FDI_COMPOSITE_SYNC
;
4708 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
4710 I915_WRITE(FDI_RX_MISC(pipe
),
4711 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
4713 reg
= FDI_RX_CTL(pipe
);
4714 temp
= I915_READ(reg
);
4715 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
4716 temp
|= FDI_COMPOSITE_SYNC
;
4717 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
4720 udelay(1); /* should be 0.5us */
4722 for (i
= 0; i
< 4; i
++) {
4723 reg
= FDI_RX_IIR(pipe
);
4724 temp
= I915_READ(reg
);
4725 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
4727 if (temp
& FDI_RX_BIT_LOCK
||
4728 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
4729 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
4730 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4734 udelay(1); /* should be 0.5us */
4737 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j
/ 2);
4742 reg
= FDI_TX_CTL(pipe
);
4743 temp
= I915_READ(reg
);
4744 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
4745 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
4746 I915_WRITE(reg
, temp
);
4748 reg
= FDI_RX_CTL(pipe
);
4749 temp
= I915_READ(reg
);
4750 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
4751 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
4752 I915_WRITE(reg
, temp
);
4755 udelay(2); /* should be 1.5us */
4757 for (i
= 0; i
< 4; i
++) {
4758 reg
= FDI_RX_IIR(pipe
);
4759 temp
= I915_READ(reg
);
4760 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
4762 if (temp
& FDI_RX_SYMBOL_LOCK
||
4763 (I915_READ(reg
) & FDI_RX_SYMBOL_LOCK
)) {
4764 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
4765 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4769 udelay(2); /* should be 1.5us */
4772 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j
/ 2);
4776 DRM_DEBUG_KMS("FDI train done.\n");
4779 static void ironlake_fdi_pll_enable(const struct intel_crtc_state
*crtc_state
)
4781 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
4782 struct drm_i915_private
*dev_priv
= to_i915(intel_crtc
->base
.dev
);
4783 int pipe
= intel_crtc
->pipe
;
4787 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4788 reg
= FDI_RX_CTL(pipe
);
4789 temp
= I915_READ(reg
);
4790 temp
&= ~(FDI_DP_PORT_WIDTH_MASK
| (0x7 << 16));
4791 temp
|= FDI_DP_PORT_WIDTH(crtc_state
->fdi_lanes
);
4792 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
4793 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
4798 /* Switch from Rawclk to PCDclk */
4799 temp
= I915_READ(reg
);
4800 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
4805 /* Enable CPU FDI TX PLL, always on for Ironlake */
4806 reg
= FDI_TX_CTL(pipe
);
4807 temp
= I915_READ(reg
);
4808 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
4809 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
4816 static void ironlake_fdi_pll_disable(struct intel_crtc
*intel_crtc
)
4818 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4819 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4820 int pipe
= intel_crtc
->pipe
;
4824 /* Switch from PCDclk to Rawclk */
4825 reg
= FDI_RX_CTL(pipe
);
4826 temp
= I915_READ(reg
);
4827 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
4829 /* Disable CPU FDI TX PLL */
4830 reg
= FDI_TX_CTL(pipe
);
4831 temp
= I915_READ(reg
);
4832 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
4837 reg
= FDI_RX_CTL(pipe
);
4838 temp
= I915_READ(reg
);
4839 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
4841 /* Wait for the clocks to turn off. */
4846 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
4848 struct drm_device
*dev
= crtc
->dev
;
4849 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4850 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4851 int pipe
= intel_crtc
->pipe
;
4855 /* disable CPU FDI tx and PCH FDI rx */
4856 reg
= FDI_TX_CTL(pipe
);
4857 temp
= I915_READ(reg
);
4858 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
4861 reg
= FDI_RX_CTL(pipe
);
4862 temp
= I915_READ(reg
);
4863 temp
&= ~(0x7 << 16);
4864 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
4865 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
4870 /* Ironlake workaround, disable clock pointer after downing FDI */
4871 if (HAS_PCH_IBX(dev_priv
))
4872 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
4874 /* still set train pattern 1 */
4875 reg
= FDI_TX_CTL(pipe
);
4876 temp
= I915_READ(reg
);
4877 temp
&= ~FDI_LINK_TRAIN_NONE
;
4878 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
4879 I915_WRITE(reg
, temp
);
4881 reg
= FDI_RX_CTL(pipe
);
4882 temp
= I915_READ(reg
);
4883 if (HAS_PCH_CPT(dev_priv
)) {
4884 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
4885 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
4887 temp
&= ~FDI_LINK_TRAIN_NONE
;
4888 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
4890 /* BPC in FDI rx is consistent with that in PIPECONF */
4891 temp
&= ~(0x07 << 16);
4892 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
4893 I915_WRITE(reg
, temp
);
4899 bool intel_has_pending_fb_unpin(struct drm_i915_private
*dev_priv
)
4901 struct drm_crtc
*crtc
;
4904 drm_for_each_crtc(crtc
, &dev_priv
->drm
) {
4905 struct drm_crtc_commit
*commit
;
4906 spin_lock(&crtc
->commit_lock
);
4907 commit
= list_first_entry_or_null(&crtc
->commit_list
,
4908 struct drm_crtc_commit
, commit_entry
);
4909 cleanup_done
= commit
?
4910 try_wait_for_completion(&commit
->cleanup_done
) : true;
4911 spin_unlock(&crtc
->commit_lock
);
4916 drm_crtc_wait_one_vblank(crtc
);
4924 void lpt_disable_iclkip(struct drm_i915_private
*dev_priv
)
4928 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_GATE
);
4930 mutex_lock(&dev_priv
->sb_lock
);
4932 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
4933 temp
|= SBI_SSCCTL_DISABLE
;
4934 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
4936 mutex_unlock(&dev_priv
->sb_lock
);
4939 /* Program iCLKIP clock to the desired frequency */
4940 static void lpt_program_iclkip(const struct intel_crtc_state
*crtc_state
)
4942 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
4943 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
4944 int clock
= crtc_state
->base
.adjusted_mode
.crtc_clock
;
4945 u32 divsel
, phaseinc
, auxdiv
, phasedir
= 0;
4948 lpt_disable_iclkip(dev_priv
);
4950 /* The iCLK virtual clock root frequency is in MHz,
4951 * but the adjusted_mode->crtc_clock in in KHz. To get the
4952 * divisors, it is necessary to divide one by another, so we
4953 * convert the virtual clock precision to KHz here for higher
4956 for (auxdiv
= 0; auxdiv
< 2; auxdiv
++) {
4957 u32 iclk_virtual_root_freq
= 172800 * 1000;
4958 u32 iclk_pi_range
= 64;
4959 u32 desired_divisor
;
4961 desired_divisor
= DIV_ROUND_CLOSEST(iclk_virtual_root_freq
,
4963 divsel
= (desired_divisor
/ iclk_pi_range
) - 2;
4964 phaseinc
= desired_divisor
% iclk_pi_range
;
4967 * Near 20MHz is a corner case which is
4968 * out of range for the 7-bit divisor
4974 /* This should not happen with any sane values */
4975 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel
) &
4976 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
);
4977 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir
) &
4978 ~SBI_SSCDIVINTPHASE_INCVAL_MASK
);
4980 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4987 mutex_lock(&dev_priv
->sb_lock
);
4989 /* Program SSCDIVINTPHASE6 */
4990 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
4991 temp
&= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
;
4992 temp
|= SBI_SSCDIVINTPHASE_DIVSEL(divsel
);
4993 temp
&= ~SBI_SSCDIVINTPHASE_INCVAL_MASK
;
4994 temp
|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc
);
4995 temp
|= SBI_SSCDIVINTPHASE_DIR(phasedir
);
4996 temp
|= SBI_SSCDIVINTPHASE_PROPAGATE
;
4997 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE6
, temp
, SBI_ICLK
);
4999 /* Program SSCAUXDIV */
5000 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
5001 temp
&= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
5002 temp
|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv
);
5003 intel_sbi_write(dev_priv
, SBI_SSCAUXDIV6
, temp
, SBI_ICLK
);
5005 /* Enable modulator and associated divider */
5006 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
5007 temp
&= ~SBI_SSCCTL_DISABLE
;
5008 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
5010 mutex_unlock(&dev_priv
->sb_lock
);
5012 /* Wait for initialization time */
5015 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_UNGATE
);
5018 int lpt_get_iclkip(struct drm_i915_private
*dev_priv
)
5020 u32 divsel
, phaseinc
, auxdiv
;
5021 u32 iclk_virtual_root_freq
= 172800 * 1000;
5022 u32 iclk_pi_range
= 64;
5023 u32 desired_divisor
;
5026 if ((I915_READ(PIXCLK_GATE
) & PIXCLK_GATE_UNGATE
) == 0)
5029 mutex_lock(&dev_priv
->sb_lock
);
5031 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
5032 if (temp
& SBI_SSCCTL_DISABLE
) {
5033 mutex_unlock(&dev_priv
->sb_lock
);
5037 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
5038 divsel
= (temp
& SBI_SSCDIVINTPHASE_DIVSEL_MASK
) >>
5039 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT
;
5040 phaseinc
= (temp
& SBI_SSCDIVINTPHASE_INCVAL_MASK
) >>
5041 SBI_SSCDIVINTPHASE_INCVAL_SHIFT
;
5043 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
5044 auxdiv
= (temp
& SBI_SSCAUXDIV_FINALDIV2SEL_MASK
) >>
5045 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT
;
5047 mutex_unlock(&dev_priv
->sb_lock
);
5049 desired_divisor
= (divsel
+ 2) * iclk_pi_range
+ phaseinc
;
5051 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq
,
5052 desired_divisor
<< auxdiv
);
5055 static void ironlake_pch_transcoder_set_timings(const struct intel_crtc_state
*crtc_state
,
5056 enum pipe pch_transcoder
)
5058 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
5059 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
5060 enum transcoder cpu_transcoder
= crtc_state
->cpu_transcoder
;
5062 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder
),
5063 I915_READ(HTOTAL(cpu_transcoder
)));
5064 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder
),
5065 I915_READ(HBLANK(cpu_transcoder
)));
5066 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder
),
5067 I915_READ(HSYNC(cpu_transcoder
)));
5069 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder
),
5070 I915_READ(VTOTAL(cpu_transcoder
)));
5071 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder
),
5072 I915_READ(VBLANK(cpu_transcoder
)));
5073 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder
),
5074 I915_READ(VSYNC(cpu_transcoder
)));
5075 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder
),
5076 I915_READ(VSYNCSHIFT(cpu_transcoder
)));
5079 static void cpt_set_fdi_bc_bifurcation(struct drm_i915_private
*dev_priv
, bool enable
)
5083 temp
= I915_READ(SOUTH_CHICKEN1
);
5084 if (!!(temp
& FDI_BC_BIFURCATION_SELECT
) == enable
)
5087 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
5088 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
5090 temp
&= ~FDI_BC_BIFURCATION_SELECT
;
5092 temp
|= FDI_BC_BIFURCATION_SELECT
;
5094 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable
? "en" : "dis");
5095 I915_WRITE(SOUTH_CHICKEN1
, temp
);
5096 POSTING_READ(SOUTH_CHICKEN1
);
5099 static void ivybridge_update_fdi_bc_bifurcation(const struct intel_crtc_state
*crtc_state
)
5101 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
5102 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
5104 switch (crtc
->pipe
) {
5108 if (crtc_state
->fdi_lanes
> 2)
5109 cpt_set_fdi_bc_bifurcation(dev_priv
, false);
5111 cpt_set_fdi_bc_bifurcation(dev_priv
, true);
5115 cpt_set_fdi_bc_bifurcation(dev_priv
, true);
5124 * Finds the encoder associated with the given CRTC. This can only be
5125 * used when we know that the CRTC isn't feeding multiple encoders!
5127 static struct intel_encoder
*
5128 intel_get_crtc_new_encoder(const struct intel_atomic_state
*state
,
5129 const struct intel_crtc_state
*crtc_state
)
5131 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
5132 const struct drm_connector_state
*connector_state
;
5133 const struct drm_connector
*connector
;
5134 struct intel_encoder
*encoder
= NULL
;
5135 int num_encoders
= 0;
5138 for_each_new_connector_in_state(&state
->base
, connector
, connector_state
, i
) {
5139 if (connector_state
->crtc
!= &crtc
->base
)
5142 encoder
= to_intel_encoder(connector_state
->best_encoder
);
5146 WARN(num_encoders
!= 1, "%d encoders for pipe %c\n",
5147 num_encoders
, pipe_name(crtc
->pipe
));
5153 * Enable PCH resources required for PCH ports:
5155 * - FDI training & RX/TX
5156 * - update transcoder timings
5157 * - DP transcoding bits
5160 static void ironlake_pch_enable(const struct intel_atomic_state
*state
,
5161 const struct intel_crtc_state
*crtc_state
)
5163 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
5164 struct drm_device
*dev
= crtc
->base
.dev
;
5165 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5166 int pipe
= crtc
->pipe
;
5169 assert_pch_transcoder_disabled(dev_priv
, pipe
);
5171 if (IS_IVYBRIDGE(dev_priv
))
5172 ivybridge_update_fdi_bc_bifurcation(crtc_state
);
5174 /* Write the TU size bits before fdi link training, so that error
5175 * detection works. */
5176 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
5177 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
5179 /* For PCH output, training FDI link */
5180 dev_priv
->display
.fdi_link_train(crtc
, crtc_state
);
5182 /* We need to program the right clock selection before writing the pixel
5183 * mutliplier into the DPLL. */
5184 if (HAS_PCH_CPT(dev_priv
)) {
5187 temp
= I915_READ(PCH_DPLL_SEL
);
5188 temp
|= TRANS_DPLL_ENABLE(pipe
);
5189 sel
= TRANS_DPLLB_SEL(pipe
);
5190 if (crtc_state
->shared_dpll
==
5191 intel_get_shared_dpll_by_id(dev_priv
, DPLL_ID_PCH_PLL_B
))
5195 I915_WRITE(PCH_DPLL_SEL
, temp
);
5198 /* XXX: pch pll's can be enabled any time before we enable the PCH
5199 * transcoder, and we actually should do this to not upset any PCH
5200 * transcoder that already use the clock when we share it.
5202 * Note that enable_shared_dpll tries to do the right thing, but
5203 * get_shared_dpll unconditionally resets the pll - we need that to have
5204 * the right LVDS enable sequence. */
5205 intel_enable_shared_dpll(crtc_state
);
5207 /* set transcoder timing, panel must allow it */
5208 assert_panel_unlocked(dev_priv
, pipe
);
5209 ironlake_pch_transcoder_set_timings(crtc_state
, pipe
);
5211 intel_fdi_normal_train(crtc
);
5213 /* For PCH DP, enable TRANS_DP_CTL */
5214 if (HAS_PCH_CPT(dev_priv
) &&
5215 intel_crtc_has_dp_encoder(crtc_state
)) {
5216 const struct drm_display_mode
*adjusted_mode
=
5217 &crtc_state
->base
.adjusted_mode
;
5218 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) >> 5;
5219 i915_reg_t reg
= TRANS_DP_CTL(pipe
);
5222 temp
= I915_READ(reg
);
5223 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
5224 TRANS_DP_SYNC_MASK
|
5226 temp
|= TRANS_DP_OUTPUT_ENABLE
;
5227 temp
|= bpc
<< 9; /* same format but at 11:9 */
5229 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
5230 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
5231 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
5232 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
5234 port
= intel_get_crtc_new_encoder(state
, crtc_state
)->port
;
5235 WARN_ON(port
< PORT_B
|| port
> PORT_D
);
5236 temp
|= TRANS_DP_PORT_SEL(port
);
5238 I915_WRITE(reg
, temp
);
5241 ironlake_enable_pch_transcoder(crtc_state
);
5244 static void lpt_pch_enable(const struct intel_atomic_state
*state
,
5245 const struct intel_crtc_state
*crtc_state
)
5247 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
5248 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
5249 enum transcoder cpu_transcoder
= crtc_state
->cpu_transcoder
;
5251 assert_pch_transcoder_disabled(dev_priv
, PIPE_A
);
5253 lpt_program_iclkip(crtc_state
);
5255 /* Set transcoder timing. */
5256 ironlake_pch_transcoder_set_timings(crtc_state
, PIPE_A
);
5258 lpt_enable_pch_transcoder(dev_priv
, cpu_transcoder
);
5261 static void cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
5263 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5264 i915_reg_t dslreg
= PIPEDSL(pipe
);
5267 temp
= I915_READ(dslreg
);
5269 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
5270 if (wait_for(I915_READ(dslreg
) != temp
, 5))
5271 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe
));
5276 * The hardware phase 0.0 refers to the center of the pixel.
5277 * We want to start from the top/left edge which is phase
5278 * -0.5. That matches how the hardware calculates the scaling
5279 * factors (from top-left of the first pixel to bottom-right
5280 * of the last pixel, as opposed to the pixel centers).
5282 * For 4:2:0 subsampled chroma planes we obviously have to
5283 * adjust that so that the chroma sample position lands in
5286 * Note that for packed YCbCr 4:2:2 formats there is no way to
5287 * control chroma siting. The hardware simply replicates the
5288 * chroma samples for both of the luma samples, and thus we don't
5289 * actually get the expected MPEG2 chroma siting convention :(
5290 * The same behaviour is observed on pre-SKL platforms as well.
5292 * Theory behind the formula (note that we ignore sub-pixel
5293 * source coordinates):
5294 * s = source sample position
5295 * d = destination sample position
5300 * | | 1.5 (initial phase)
5308 * | -0.375 (initial phase)
5315 u16
skl_scaler_calc_phase(int sub
, int scale
, bool chroma_cosited
)
5317 int phase
= -0x8000;
5321 phase
+= (sub
- 1) * 0x8000 / sub
;
5323 phase
+= scale
/ (2 * sub
);
5326 * Hardware initial phase limited to [-0.5:1.5].
5327 * Since the max hardware scale factor is 3.0, we
5328 * should never actually excdeed 1.0 here.
5330 WARN_ON(phase
< -0x8000 || phase
> 0x18000);
5333 phase
= 0x10000 + phase
;
5335 trip
= PS_PHASE_TRIP
;
5337 return ((phase
>> 2) & PS_PHASE_MASK
) | trip
;
5340 #define SKL_MIN_SRC_W 8
5341 #define SKL_MAX_SRC_W 4096
5342 #define SKL_MIN_SRC_H 8
5343 #define SKL_MAX_SRC_H 4096
5344 #define SKL_MIN_DST_W 8
5345 #define SKL_MAX_DST_W 4096
5346 #define SKL_MIN_DST_H 8
5347 #define SKL_MAX_DST_H 4096
5348 #define ICL_MAX_SRC_W 5120
5349 #define ICL_MAX_SRC_H 4096
5350 #define ICL_MAX_DST_W 5120
5351 #define ICL_MAX_DST_H 4096
5352 #define SKL_MIN_YUV_420_SRC_W 16
5353 #define SKL_MIN_YUV_420_SRC_H 16
5356 skl_update_scaler(struct intel_crtc_state
*crtc_state
, bool force_detach
,
5357 unsigned int scaler_user
, int *scaler_id
,
5358 int src_w
, int src_h
, int dst_w
, int dst_h
,
5359 const struct drm_format_info
*format
, bool need_scaler
)
5361 struct intel_crtc_scaler_state
*scaler_state
=
5362 &crtc_state
->scaler_state
;
5363 struct intel_crtc
*intel_crtc
=
5364 to_intel_crtc(crtc_state
->base
.crtc
);
5365 struct drm_i915_private
*dev_priv
= to_i915(intel_crtc
->base
.dev
);
5366 const struct drm_display_mode
*adjusted_mode
=
5367 &crtc_state
->base
.adjusted_mode
;
5370 * Src coordinates are already rotated by 270 degrees for
5371 * the 90/270 degree plane rotation cases (to match the
5372 * GTT mapping), hence no need to account for rotation here.
5374 if (src_w
!= dst_w
|| src_h
!= dst_h
)
5378 * Scaling/fitting not supported in IF-ID mode in GEN9+
5379 * TODO: Interlace fetch mode doesn't support YUV420 planar formats.
5380 * Once NV12 is enabled, handle it here while allocating scaler
5383 if (INTEL_GEN(dev_priv
) >= 9 && crtc_state
->base
.enable
&&
5384 need_scaler
&& adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
5385 DRM_DEBUG_KMS("Pipe/Plane scaling not supported with IF-ID mode\n");
5390 * if plane is being disabled or scaler is no more required or force detach
5391 * - free scaler binded to this plane/crtc
5392 * - in order to do this, update crtc->scaler_usage
5394 * Here scaler state in crtc_state is set free so that
5395 * scaler can be assigned to other user. Actual register
5396 * update to free the scaler is done in plane/panel-fit programming.
5397 * For this purpose crtc/plane_state->scaler_id isn't reset here.
5399 if (force_detach
|| !need_scaler
) {
5400 if (*scaler_id
>= 0) {
5401 scaler_state
->scaler_users
&= ~(1 << scaler_user
);
5402 scaler_state
->scalers
[*scaler_id
].in_use
= 0;
5404 DRM_DEBUG_KMS("scaler_user index %u.%u: "
5405 "Staged freeing scaler id %d scaler_users = 0x%x\n",
5406 intel_crtc
->pipe
, scaler_user
, *scaler_id
,
5407 scaler_state
->scaler_users
);
5413 if (format
&& is_planar_yuv_format(format
->format
) &&
5414 (src_h
< SKL_MIN_YUV_420_SRC_H
|| src_w
< SKL_MIN_YUV_420_SRC_W
)) {
5415 DRM_DEBUG_KMS("Planar YUV: src dimensions not met\n");
5420 if (src_w
< SKL_MIN_SRC_W
|| src_h
< SKL_MIN_SRC_H
||
5421 dst_w
< SKL_MIN_DST_W
|| dst_h
< SKL_MIN_DST_H
||
5422 (INTEL_GEN(dev_priv
) >= 11 &&
5423 (src_w
> ICL_MAX_SRC_W
|| src_h
> ICL_MAX_SRC_H
||
5424 dst_w
> ICL_MAX_DST_W
|| dst_h
> ICL_MAX_DST_H
)) ||
5425 (INTEL_GEN(dev_priv
) < 11 &&
5426 (src_w
> SKL_MAX_SRC_W
|| src_h
> SKL_MAX_SRC_H
||
5427 dst_w
> SKL_MAX_DST_W
|| dst_h
> SKL_MAX_DST_H
))) {
5428 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
5429 "size is out of scaler range\n",
5430 intel_crtc
->pipe
, scaler_user
, src_w
, src_h
, dst_w
, dst_h
);
5434 /* mark this plane as a scaler user in crtc_state */
5435 scaler_state
->scaler_users
|= (1 << scaler_user
);
5436 DRM_DEBUG_KMS("scaler_user index %u.%u: "
5437 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
5438 intel_crtc
->pipe
, scaler_user
, src_w
, src_h
, dst_w
, dst_h
,
5439 scaler_state
->scaler_users
);
5445 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
5447 * @state: crtc's scaler state
5450 * 0 - scaler_usage updated successfully
5451 * error - requested scaling cannot be supported or other error condition
5453 int skl_update_scaler_crtc(struct intel_crtc_state
*state
)
5455 const struct drm_display_mode
*adjusted_mode
= &state
->base
.adjusted_mode
;
5456 bool need_scaler
= false;
5458 if (state
->output_format
== INTEL_OUTPUT_FORMAT_YCBCR420
)
5461 return skl_update_scaler(state
, !state
->base
.active
, SKL_CRTC_INDEX
,
5462 &state
->scaler_state
.scaler_id
,
5463 state
->pipe_src_w
, state
->pipe_src_h
,
5464 adjusted_mode
->crtc_hdisplay
,
5465 adjusted_mode
->crtc_vdisplay
, NULL
, need_scaler
);
5469 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
5470 * @crtc_state: crtc's scaler state
5471 * @plane_state: atomic plane state to update
5474 * 0 - scaler_usage updated successfully
5475 * error - requested scaling cannot be supported or other error condition
5477 static int skl_update_scaler_plane(struct intel_crtc_state
*crtc_state
,
5478 struct intel_plane_state
*plane_state
)
5480 struct intel_plane
*intel_plane
=
5481 to_intel_plane(plane_state
->base
.plane
);
5482 struct drm_i915_private
*dev_priv
= to_i915(intel_plane
->base
.dev
);
5483 struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
5485 bool force_detach
= !fb
|| !plane_state
->base
.visible
;
5486 bool need_scaler
= false;
5488 /* Pre-gen11 and SDR planes always need a scaler for planar formats. */
5489 if (!icl_is_hdr_plane(dev_priv
, intel_plane
->id
) &&
5490 fb
&& is_planar_yuv_format(fb
->format
->format
))
5493 ret
= skl_update_scaler(crtc_state
, force_detach
,
5494 drm_plane_index(&intel_plane
->base
),
5495 &plane_state
->scaler_id
,
5496 drm_rect_width(&plane_state
->base
.src
) >> 16,
5497 drm_rect_height(&plane_state
->base
.src
) >> 16,
5498 drm_rect_width(&plane_state
->base
.dst
),
5499 drm_rect_height(&plane_state
->base
.dst
),
5500 fb
? fb
->format
: NULL
, need_scaler
);
5502 if (ret
|| plane_state
->scaler_id
< 0)
5505 /* check colorkey */
5506 if (plane_state
->ckey
.flags
) {
5507 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
5508 intel_plane
->base
.base
.id
,
5509 intel_plane
->base
.name
);
5513 /* Check src format */
5514 switch (fb
->format
->format
) {
5515 case DRM_FORMAT_RGB565
:
5516 case DRM_FORMAT_XBGR8888
:
5517 case DRM_FORMAT_XRGB8888
:
5518 case DRM_FORMAT_ABGR8888
:
5519 case DRM_FORMAT_ARGB8888
:
5520 case DRM_FORMAT_XRGB2101010
:
5521 case DRM_FORMAT_XBGR2101010
:
5522 case DRM_FORMAT_XBGR16161616F
:
5523 case DRM_FORMAT_ABGR16161616F
:
5524 case DRM_FORMAT_XRGB16161616F
:
5525 case DRM_FORMAT_ARGB16161616F
:
5526 case DRM_FORMAT_YUYV
:
5527 case DRM_FORMAT_YVYU
:
5528 case DRM_FORMAT_UYVY
:
5529 case DRM_FORMAT_VYUY
:
5530 case DRM_FORMAT_NV12
:
5531 case DRM_FORMAT_P010
:
5532 case DRM_FORMAT_P012
:
5533 case DRM_FORMAT_P016
:
5534 case DRM_FORMAT_Y210
:
5535 case DRM_FORMAT_Y212
:
5536 case DRM_FORMAT_Y216
:
5537 case DRM_FORMAT_XVYU2101010
:
5538 case DRM_FORMAT_XVYU12_16161616
:
5539 case DRM_FORMAT_XVYU16161616
:
5542 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
5543 intel_plane
->base
.base
.id
, intel_plane
->base
.name
,
5544 fb
->base
.id
, fb
->format
->format
);
5551 static void skylake_scaler_disable(struct intel_crtc
*crtc
)
5555 for (i
= 0; i
< crtc
->num_scalers
; i
++)
5556 skl_detach_scaler(crtc
, i
);
5559 static void skylake_pfit_enable(const struct intel_crtc_state
*crtc_state
)
5561 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
5562 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
5563 enum pipe pipe
= crtc
->pipe
;
5564 const struct intel_crtc_scaler_state
*scaler_state
=
5565 &crtc_state
->scaler_state
;
5567 if (crtc_state
->pch_pfit
.enabled
) {
5568 u16 uv_rgb_hphase
, uv_rgb_vphase
;
5569 int pfit_w
, pfit_h
, hscale
, vscale
;
5572 if (WARN_ON(crtc_state
->scaler_state
.scaler_id
< 0))
5575 pfit_w
= (crtc_state
->pch_pfit
.size
>> 16) & 0xFFFF;
5576 pfit_h
= crtc_state
->pch_pfit
.size
& 0xFFFF;
5578 hscale
= (crtc_state
->pipe_src_w
<< 16) / pfit_w
;
5579 vscale
= (crtc_state
->pipe_src_h
<< 16) / pfit_h
;
5581 uv_rgb_hphase
= skl_scaler_calc_phase(1, hscale
, false);
5582 uv_rgb_vphase
= skl_scaler_calc_phase(1, vscale
, false);
5584 id
= scaler_state
->scaler_id
;
5585 I915_WRITE(SKL_PS_CTRL(pipe
, id
), PS_SCALER_EN
|
5586 PS_FILTER_MEDIUM
| scaler_state
->scalers
[id
].mode
);
5587 I915_WRITE_FW(SKL_PS_VPHASE(pipe
, id
),
5588 PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase
));
5589 I915_WRITE_FW(SKL_PS_HPHASE(pipe
, id
),
5590 PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase
));
5591 I915_WRITE(SKL_PS_WIN_POS(pipe
, id
), crtc_state
->pch_pfit
.pos
);
5592 I915_WRITE(SKL_PS_WIN_SZ(pipe
, id
), crtc_state
->pch_pfit
.size
);
5596 static void ironlake_pfit_enable(const struct intel_crtc_state
*crtc_state
)
5598 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
5599 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
5600 int pipe
= crtc
->pipe
;
5602 if (crtc_state
->pch_pfit
.enabled
) {
5603 /* Force use of hard-coded filter coefficients
5604 * as some pre-programmed values are broken,
5607 if (IS_IVYBRIDGE(dev_priv
) || IS_HASWELL(dev_priv
))
5608 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
|
5609 PF_PIPE_SEL_IVB(pipe
));
5611 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
5612 I915_WRITE(PF_WIN_POS(pipe
), crtc_state
->pch_pfit
.pos
);
5613 I915_WRITE(PF_WIN_SZ(pipe
), crtc_state
->pch_pfit
.size
);
5617 void hsw_enable_ips(const struct intel_crtc_state
*crtc_state
)
5619 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
5620 struct drm_device
*dev
= crtc
->base
.dev
;
5621 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5623 if (!crtc_state
->ips_enabled
)
5627 * We can only enable IPS after we enable a plane and wait for a vblank
5628 * This function is called from post_plane_update, which is run after
5631 WARN_ON(!(crtc_state
->active_planes
& ~BIT(PLANE_CURSOR
)));
5633 if (IS_BROADWELL(dev_priv
)) {
5634 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
,
5635 IPS_ENABLE
| IPS_PCODE_CONTROL
));
5636 /* Quoting Art Runyan: "its not safe to expect any particular
5637 * value in IPS_CTL bit 31 after enabling IPS through the
5638 * mailbox." Moreover, the mailbox may return a bogus state,
5639 * so we need to just enable it and continue on.
5642 I915_WRITE(IPS_CTL
, IPS_ENABLE
);
5643 /* The bit only becomes 1 in the next vblank, so this wait here
5644 * is essentially intel_wait_for_vblank. If we don't have this
5645 * and don't wait for vblanks until the end of crtc_enable, then
5646 * the HW state readout code will complain that the expected
5647 * IPS_CTL value is not the one we read. */
5648 if (intel_wait_for_register(&dev_priv
->uncore
,
5649 IPS_CTL
, IPS_ENABLE
, IPS_ENABLE
,
5651 DRM_ERROR("Timed out waiting for IPS enable\n");
5655 void hsw_disable_ips(const struct intel_crtc_state
*crtc_state
)
5657 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
5658 struct drm_device
*dev
= crtc
->base
.dev
;
5659 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5661 if (!crtc_state
->ips_enabled
)
5664 if (IS_BROADWELL(dev_priv
)) {
5665 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0));
5667 * Wait for PCODE to finish disabling IPS. The BSpec specified
5668 * 42ms timeout value leads to occasional timeouts so use 100ms
5671 if (intel_wait_for_register(&dev_priv
->uncore
,
5672 IPS_CTL
, IPS_ENABLE
, 0,
5674 DRM_ERROR("Timed out waiting for IPS disable\n");
5676 I915_WRITE(IPS_CTL
, 0);
5677 POSTING_READ(IPS_CTL
);
5680 /* We need to wait for a vblank before we can disable the plane. */
5681 intel_wait_for_vblank(dev_priv
, crtc
->pipe
);
5684 static void intel_crtc_dpms_overlay_disable(struct intel_crtc
*intel_crtc
)
5686 if (intel_crtc
->overlay
) {
5687 struct drm_device
*dev
= intel_crtc
->base
.dev
;
5689 mutex_lock(&dev
->struct_mutex
);
5690 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
5691 mutex_unlock(&dev
->struct_mutex
);
5694 /* Let userspace switch the overlay on again. In most cases userspace
5695 * has to recompute where to put it anyway.
5700 * intel_post_enable_primary - Perform operations after enabling primary plane
5701 * @crtc: the CRTC whose primary plane was just enabled
5702 * @new_crtc_state: the enabling state
5704 * Performs potentially sleeping operations that must be done after the primary
5705 * plane is enabled, such as updating FBC and IPS. Note that this may be
5706 * called due to an explicit primary plane update, or due to an implicit
5707 * re-enable that is caused when a sprite plane is updated to no longer
5708 * completely hide the primary plane.
5711 intel_post_enable_primary(struct drm_crtc
*crtc
,
5712 const struct intel_crtc_state
*new_crtc_state
)
5714 struct drm_device
*dev
= crtc
->dev
;
5715 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5716 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5717 int pipe
= intel_crtc
->pipe
;
5720 * Gen2 reports pipe underruns whenever all planes are disabled.
5721 * So don't enable underrun reporting before at least some planes
5723 * FIXME: Need to fix the logic to work when we turn off all planes
5724 * but leave the pipe running.
5726 if (IS_GEN(dev_priv
, 2))
5727 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
5729 /* Underruns don't always raise interrupts, so check manually. */
5730 intel_check_cpu_fifo_underruns(dev_priv
);
5731 intel_check_pch_fifo_underruns(dev_priv
);
5734 /* FIXME get rid of this and use pre_plane_update */
5736 intel_pre_disable_primary_noatomic(struct drm_crtc
*crtc
)
5738 struct drm_device
*dev
= crtc
->dev
;
5739 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5740 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5741 int pipe
= intel_crtc
->pipe
;
5744 * Gen2 reports pipe underruns whenever all planes are disabled.
5745 * So disable underrun reporting before all the planes get disabled.
5747 if (IS_GEN(dev_priv
, 2))
5748 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
5750 hsw_disable_ips(to_intel_crtc_state(crtc
->state
));
5753 * Vblank time updates from the shadow to live plane control register
5754 * are blocked if the memory self-refresh mode is active at that
5755 * moment. So to make sure the plane gets truly disabled, disable
5756 * first the self-refresh mode. The self-refresh enable bit in turn
5757 * will be checked/applied by the HW only at the next frame start
5758 * event which is after the vblank start event, so we need to have a
5759 * wait-for-vblank between disabling the plane and the pipe.
5761 if (HAS_GMCH(dev_priv
) &&
5762 intel_set_memory_cxsr(dev_priv
, false))
5763 intel_wait_for_vblank(dev_priv
, pipe
);
5766 static bool hsw_pre_update_disable_ips(const struct intel_crtc_state
*old_crtc_state
,
5767 const struct intel_crtc_state
*new_crtc_state
)
5769 struct intel_crtc
*crtc
= to_intel_crtc(new_crtc_state
->base
.crtc
);
5770 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
5772 if (!old_crtc_state
->ips_enabled
)
5775 if (needs_modeset(&new_crtc_state
->base
))
5779 * Workaround : Do not read or write the pipe palette/gamma data while
5780 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
5782 * Disable IPS before we program the LUT.
5784 if (IS_HASWELL(dev_priv
) &&
5785 (new_crtc_state
->base
.color_mgmt_changed
||
5786 new_crtc_state
->update_pipe
) &&
5787 new_crtc_state
->gamma_mode
== GAMMA_MODE_MODE_SPLIT
)
5790 return !new_crtc_state
->ips_enabled
;
5793 static bool hsw_post_update_enable_ips(const struct intel_crtc_state
*old_crtc_state
,
5794 const struct intel_crtc_state
*new_crtc_state
)
5796 struct intel_crtc
*crtc
= to_intel_crtc(new_crtc_state
->base
.crtc
);
5797 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
5799 if (!new_crtc_state
->ips_enabled
)
5802 if (needs_modeset(&new_crtc_state
->base
))
5806 * Workaround : Do not read or write the pipe palette/gamma data while
5807 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
5809 * Re-enable IPS after the LUT has been programmed.
5811 if (IS_HASWELL(dev_priv
) &&
5812 (new_crtc_state
->base
.color_mgmt_changed
||
5813 new_crtc_state
->update_pipe
) &&
5814 new_crtc_state
->gamma_mode
== GAMMA_MODE_MODE_SPLIT
)
5818 * We can't read out IPS on broadwell, assume the worst and
5819 * forcibly enable IPS on the first fastset.
5821 if (new_crtc_state
->update_pipe
&&
5822 old_crtc_state
->base
.adjusted_mode
.private_flags
& I915_MODE_FLAG_INHERITED
)
5825 return !old_crtc_state
->ips_enabled
;
5828 static bool needs_nv12_wa(struct drm_i915_private
*dev_priv
,
5829 const struct intel_crtc_state
*crtc_state
)
5831 if (!crtc_state
->nv12_planes
)
5834 /* WA Display #0827: Gen9:all */
5835 if (IS_GEN(dev_priv
, 9) && !IS_GEMINILAKE(dev_priv
))
5841 static bool needs_scalerclk_wa(struct drm_i915_private
*dev_priv
,
5842 const struct intel_crtc_state
*crtc_state
)
5844 /* Wa_2006604312:icl */
5845 if (crtc_state
->scaler_state
.scaler_users
> 0 && IS_ICELAKE(dev_priv
))
5851 static void intel_post_plane_update(struct intel_crtc_state
*old_crtc_state
)
5853 struct intel_crtc
*crtc
= to_intel_crtc(old_crtc_state
->base
.crtc
);
5854 struct drm_device
*dev
= crtc
->base
.dev
;
5855 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5856 struct drm_atomic_state
*old_state
= old_crtc_state
->base
.state
;
5857 struct intel_crtc_state
*pipe_config
=
5858 intel_atomic_get_new_crtc_state(to_intel_atomic_state(old_state
),
5860 struct drm_plane
*primary
= crtc
->base
.primary
;
5861 struct drm_plane_state
*old_primary_state
=
5862 drm_atomic_get_old_plane_state(old_state
, primary
);
5864 intel_frontbuffer_flip(to_i915(crtc
->base
.dev
), pipe_config
->fb_bits
);
5866 if (pipe_config
->update_wm_post
&& pipe_config
->base
.active
)
5867 intel_update_watermarks(crtc
);
5869 if (hsw_post_update_enable_ips(old_crtc_state
, pipe_config
))
5870 hsw_enable_ips(pipe_config
);
5872 if (old_primary_state
) {
5873 struct drm_plane_state
*new_primary_state
=
5874 drm_atomic_get_new_plane_state(old_state
, primary
);
5876 intel_fbc_post_update(crtc
);
5878 if (new_primary_state
->visible
&&
5879 (needs_modeset(&pipe_config
->base
) ||
5880 !old_primary_state
->visible
))
5881 intel_post_enable_primary(&crtc
->base
, pipe_config
);
5884 if (needs_nv12_wa(dev_priv
, old_crtc_state
) &&
5885 !needs_nv12_wa(dev_priv
, pipe_config
))
5886 skl_wa_827(dev_priv
, crtc
->pipe
, false);
5888 if (needs_scalerclk_wa(dev_priv
, old_crtc_state
) &&
5889 !needs_scalerclk_wa(dev_priv
, pipe_config
))
5890 icl_wa_scalerclkgating(dev_priv
, crtc
->pipe
, false);
5893 static void intel_pre_plane_update(struct intel_crtc_state
*old_crtc_state
,
5894 struct intel_crtc_state
*pipe_config
)
5896 struct intel_crtc
*crtc
= to_intel_crtc(old_crtc_state
->base
.crtc
);
5897 struct drm_device
*dev
= crtc
->base
.dev
;
5898 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5899 struct drm_atomic_state
*old_state
= old_crtc_state
->base
.state
;
5900 struct drm_plane
*primary
= crtc
->base
.primary
;
5901 struct drm_plane_state
*old_primary_state
=
5902 drm_atomic_get_old_plane_state(old_state
, primary
);
5903 bool modeset
= needs_modeset(&pipe_config
->base
);
5904 struct intel_atomic_state
*old_intel_state
=
5905 to_intel_atomic_state(old_state
);
5907 if (hsw_pre_update_disable_ips(old_crtc_state
, pipe_config
))
5908 hsw_disable_ips(old_crtc_state
);
5910 if (old_primary_state
) {
5911 struct intel_plane_state
*new_primary_state
=
5912 intel_atomic_get_new_plane_state(old_intel_state
,
5913 to_intel_plane(primary
));
5915 intel_fbc_pre_update(crtc
, pipe_config
, new_primary_state
);
5917 * Gen2 reports pipe underruns whenever all planes are disabled.
5918 * So disable underrun reporting before all the planes get disabled.
5920 if (IS_GEN(dev_priv
, 2) && old_primary_state
->visible
&&
5921 (modeset
|| !new_primary_state
->base
.visible
))
5922 intel_set_cpu_fifo_underrun_reporting(dev_priv
, crtc
->pipe
, false);
5925 /* Display WA 827 */
5926 if (!needs_nv12_wa(dev_priv
, old_crtc_state
) &&
5927 needs_nv12_wa(dev_priv
, pipe_config
))
5928 skl_wa_827(dev_priv
, crtc
->pipe
, true);
5930 /* Wa_2006604312:icl */
5931 if (!needs_scalerclk_wa(dev_priv
, old_crtc_state
) &&
5932 needs_scalerclk_wa(dev_priv
, pipe_config
))
5933 icl_wa_scalerclkgating(dev_priv
, crtc
->pipe
, true);
5936 * Vblank time updates from the shadow to live plane control register
5937 * are blocked if the memory self-refresh mode is active at that
5938 * moment. So to make sure the plane gets truly disabled, disable
5939 * first the self-refresh mode. The self-refresh enable bit in turn
5940 * will be checked/applied by the HW only at the next frame start
5941 * event which is after the vblank start event, so we need to have a
5942 * wait-for-vblank between disabling the plane and the pipe.
5944 if (HAS_GMCH(dev_priv
) && old_crtc_state
->base
.active
&&
5945 pipe_config
->disable_cxsr
&& intel_set_memory_cxsr(dev_priv
, false))
5946 intel_wait_for_vblank(dev_priv
, crtc
->pipe
);
5949 * IVB workaround: must disable low power watermarks for at least
5950 * one frame before enabling scaling. LP watermarks can be re-enabled
5951 * when scaling is disabled.
5953 * WaCxSRDisabledForSpriteScaling:ivb
5955 if (pipe_config
->disable_lp_wm
&& ilk_disable_lp_wm(dev
) &&
5956 old_crtc_state
->base
.active
)
5957 intel_wait_for_vblank(dev_priv
, crtc
->pipe
);
5960 * If we're doing a modeset, we're done. No need to do any pre-vblank
5961 * watermark programming here.
5963 if (needs_modeset(&pipe_config
->base
))
5967 * For platforms that support atomic watermarks, program the
5968 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
5969 * will be the intermediate values that are safe for both pre- and
5970 * post- vblank; when vblank happens, the 'active' values will be set
5971 * to the final 'target' values and we'll do this again to get the
5972 * optimal watermarks. For gen9+ platforms, the values we program here
5973 * will be the final target values which will get automatically latched
5974 * at vblank time; no further programming will be necessary.
5976 * If a platform hasn't been transitioned to atomic watermarks yet,
5977 * we'll continue to update watermarks the old way, if flags tell
5980 if (dev_priv
->display
.initial_watermarks
!= NULL
)
5981 dev_priv
->display
.initial_watermarks(old_intel_state
,
5983 else if (pipe_config
->update_wm_pre
)
5984 intel_update_watermarks(crtc
);
5987 static void intel_crtc_disable_planes(struct intel_atomic_state
*state
,
5988 struct intel_crtc
*crtc
)
5990 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
5991 const struct intel_crtc_state
*new_crtc_state
=
5992 intel_atomic_get_new_crtc_state(state
, crtc
);
5993 unsigned int update_mask
= new_crtc_state
->update_planes
;
5994 const struct intel_plane_state
*old_plane_state
;
5995 struct intel_plane
*plane
;
5996 unsigned fb_bits
= 0;
5999 intel_crtc_dpms_overlay_disable(crtc
);
6001 for_each_old_intel_plane_in_state(state
, plane
, old_plane_state
, i
) {
6002 if (crtc
->pipe
!= plane
->pipe
||
6003 !(update_mask
& BIT(plane
->id
)))
6006 intel_disable_plane(plane
, new_crtc_state
);
6008 if (old_plane_state
->base
.visible
)
6009 fb_bits
|= plane
->frontbuffer_bit
;
6012 intel_frontbuffer_flip(dev_priv
, fb_bits
);
6015 static void intel_encoders_pre_pll_enable(struct drm_crtc
*crtc
,
6016 struct intel_crtc_state
*crtc_state
,
6017 struct drm_atomic_state
*old_state
)
6019 struct drm_connector_state
*conn_state
;
6020 struct drm_connector
*conn
;
6023 for_each_new_connector_in_state(old_state
, conn
, conn_state
, i
) {
6024 struct intel_encoder
*encoder
=
6025 to_intel_encoder(conn_state
->best_encoder
);
6027 if (conn_state
->crtc
!= crtc
)
6030 if (encoder
->pre_pll_enable
)
6031 encoder
->pre_pll_enable(encoder
, crtc_state
, conn_state
);
6035 static void intel_encoders_pre_enable(struct drm_crtc
*crtc
,
6036 struct intel_crtc_state
*crtc_state
,
6037 struct drm_atomic_state
*old_state
)
6039 struct drm_connector_state
*conn_state
;
6040 struct drm_connector
*conn
;
6043 for_each_new_connector_in_state(old_state
, conn
, conn_state
, i
) {
6044 struct intel_encoder
*encoder
=
6045 to_intel_encoder(conn_state
->best_encoder
);
6047 if (conn_state
->crtc
!= crtc
)
6050 if (encoder
->pre_enable
)
6051 encoder
->pre_enable(encoder
, crtc_state
, conn_state
);
6055 static void intel_encoders_enable(struct drm_crtc
*crtc
,
6056 struct intel_crtc_state
*crtc_state
,
6057 struct drm_atomic_state
*old_state
)
6059 struct drm_connector_state
*conn_state
;
6060 struct drm_connector
*conn
;
6063 for_each_new_connector_in_state(old_state
, conn
, conn_state
, i
) {
6064 struct intel_encoder
*encoder
=
6065 to_intel_encoder(conn_state
->best_encoder
);
6067 if (conn_state
->crtc
!= crtc
)
6070 if (encoder
->enable
)
6071 encoder
->enable(encoder
, crtc_state
, conn_state
);
6072 intel_opregion_notify_encoder(encoder
, true);
6076 static void intel_encoders_disable(struct drm_crtc
*crtc
,
6077 struct intel_crtc_state
*old_crtc_state
,
6078 struct drm_atomic_state
*old_state
)
6080 struct drm_connector_state
*old_conn_state
;
6081 struct drm_connector
*conn
;
6084 for_each_old_connector_in_state(old_state
, conn
, old_conn_state
, i
) {
6085 struct intel_encoder
*encoder
=
6086 to_intel_encoder(old_conn_state
->best_encoder
);
6088 if (old_conn_state
->crtc
!= crtc
)
6091 intel_opregion_notify_encoder(encoder
, false);
6092 if (encoder
->disable
)
6093 encoder
->disable(encoder
, old_crtc_state
, old_conn_state
);
6097 static void intel_encoders_post_disable(struct drm_crtc
*crtc
,
6098 struct intel_crtc_state
*old_crtc_state
,
6099 struct drm_atomic_state
*old_state
)
6101 struct drm_connector_state
*old_conn_state
;
6102 struct drm_connector
*conn
;
6105 for_each_old_connector_in_state(old_state
, conn
, old_conn_state
, i
) {
6106 struct intel_encoder
*encoder
=
6107 to_intel_encoder(old_conn_state
->best_encoder
);
6109 if (old_conn_state
->crtc
!= crtc
)
6112 if (encoder
->post_disable
)
6113 encoder
->post_disable(encoder
, old_crtc_state
, old_conn_state
);
6117 static void intel_encoders_post_pll_disable(struct drm_crtc
*crtc
,
6118 struct intel_crtc_state
*old_crtc_state
,
6119 struct drm_atomic_state
*old_state
)
6121 struct drm_connector_state
*old_conn_state
;
6122 struct drm_connector
*conn
;
6125 for_each_old_connector_in_state(old_state
, conn
, old_conn_state
, i
) {
6126 struct intel_encoder
*encoder
=
6127 to_intel_encoder(old_conn_state
->best_encoder
);
6129 if (old_conn_state
->crtc
!= crtc
)
6132 if (encoder
->post_pll_disable
)
6133 encoder
->post_pll_disable(encoder
, old_crtc_state
, old_conn_state
);
6137 static void intel_encoders_update_pipe(struct drm_crtc
*crtc
,
6138 struct intel_crtc_state
*crtc_state
,
6139 struct drm_atomic_state
*old_state
)
6141 struct drm_connector_state
*conn_state
;
6142 struct drm_connector
*conn
;
6145 for_each_new_connector_in_state(old_state
, conn
, conn_state
, i
) {
6146 struct intel_encoder
*encoder
=
6147 to_intel_encoder(conn_state
->best_encoder
);
6149 if (conn_state
->crtc
!= crtc
)
6152 if (encoder
->update_pipe
)
6153 encoder
->update_pipe(encoder
, crtc_state
, conn_state
);
6157 static void intel_disable_primary_plane(const struct intel_crtc_state
*crtc_state
)
6159 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
6160 struct intel_plane
*plane
= to_intel_plane(crtc
->base
.primary
);
6162 plane
->disable_plane(plane
, crtc_state
);
6165 static void ironlake_crtc_enable(struct intel_crtc_state
*pipe_config
,
6166 struct drm_atomic_state
*old_state
)
6168 struct drm_crtc
*crtc
= pipe_config
->base
.crtc
;
6169 struct drm_device
*dev
= crtc
->dev
;
6170 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6171 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6172 int pipe
= intel_crtc
->pipe
;
6173 struct intel_atomic_state
*old_intel_state
=
6174 to_intel_atomic_state(old_state
);
6176 if (WARN_ON(intel_crtc
->active
))
6180 * Sometimes spurious CPU pipe underruns happen during FDI
6181 * training, at least with VGA+HDMI cloning. Suppress them.
6183 * On ILK we get an occasional spurious CPU pipe underruns
6184 * between eDP port A enable and vdd enable. Also PCH port
6185 * enable seems to result in the occasional CPU pipe underrun.
6187 * Spurious PCH underruns also occur during PCH enabling.
6189 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
6190 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, false);
6192 if (pipe_config
->has_pch_encoder
)
6193 intel_prepare_shared_dpll(pipe_config
);
6195 if (intel_crtc_has_dp_encoder(pipe_config
))
6196 intel_dp_set_m_n(pipe_config
, M1_N1
);
6198 intel_set_pipe_timings(pipe_config
);
6199 intel_set_pipe_src_size(pipe_config
);
6201 if (pipe_config
->has_pch_encoder
) {
6202 intel_cpu_transcoder_set_m_n(pipe_config
,
6203 &pipe_config
->fdi_m_n
, NULL
);
6206 ironlake_set_pipeconf(pipe_config
);
6208 intel_crtc
->active
= true;
6210 intel_encoders_pre_enable(crtc
, pipe_config
, old_state
);
6212 if (pipe_config
->has_pch_encoder
) {
6213 /* Note: FDI PLL enabling _must_ be done before we enable the
6214 * cpu pipes, hence this is separate from all the other fdi/pch
6216 ironlake_fdi_pll_enable(pipe_config
);
6218 assert_fdi_tx_disabled(dev_priv
, pipe
);
6219 assert_fdi_rx_disabled(dev_priv
, pipe
);
6222 ironlake_pfit_enable(pipe_config
);
6225 * On ILK+ LUT must be loaded before the pipe is running but with
6228 intel_color_load_luts(pipe_config
);
6229 intel_color_commit(pipe_config
);
6230 /* update DSPCNTR to configure gamma for pipe bottom color */
6231 intel_disable_primary_plane(pipe_config
);
6233 if (dev_priv
->display
.initial_watermarks
!= NULL
)
6234 dev_priv
->display
.initial_watermarks(old_intel_state
, pipe_config
);
6235 intel_enable_pipe(pipe_config
);
6237 if (pipe_config
->has_pch_encoder
)
6238 ironlake_pch_enable(old_intel_state
, pipe_config
);
6240 assert_vblank_disabled(crtc
);
6241 intel_crtc_vblank_on(pipe_config
);
6243 intel_encoders_enable(crtc
, pipe_config
, old_state
);
6245 if (HAS_PCH_CPT(dev_priv
))
6246 cpt_verify_modeset(dev
, intel_crtc
->pipe
);
6249 * Must wait for vblank to avoid spurious PCH FIFO underruns.
6250 * And a second vblank wait is needed at least on ILK with
6251 * some interlaced HDMI modes. Let's do the double wait always
6252 * in case there are more corner cases we don't know about.
6254 if (pipe_config
->has_pch_encoder
) {
6255 intel_wait_for_vblank(dev_priv
, pipe
);
6256 intel_wait_for_vblank(dev_priv
, pipe
);
6258 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
6259 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, true);
6262 /* IPS only exists on ULT machines and is tied to pipe A. */
6263 static bool hsw_crtc_supports_ips(struct intel_crtc
*crtc
)
6265 return HAS_IPS(to_i915(crtc
->base
.dev
)) && crtc
->pipe
== PIPE_A
;
6268 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private
*dev_priv
,
6269 enum pipe pipe
, bool apply
)
6271 u32 val
= I915_READ(CLKGATE_DIS_PSL(pipe
));
6272 u32 mask
= DPF_GATING_DIS
| DPF_RAM_GATING_DIS
| DPFR_GATING_DIS
;
6279 I915_WRITE(CLKGATE_DIS_PSL(pipe
), val
);
6282 static void icl_pipe_mbus_enable(struct intel_crtc
*crtc
)
6284 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
6285 enum pipe pipe
= crtc
->pipe
;
6288 val
= MBUS_DBOX_A_CREDIT(2);
6289 val
|= MBUS_DBOX_BW_CREDIT(1);
6290 val
|= MBUS_DBOX_B_CREDIT(8);
6292 I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe
), val
);
6295 static void haswell_crtc_enable(struct intel_crtc_state
*pipe_config
,
6296 struct drm_atomic_state
*old_state
)
6298 struct drm_crtc
*crtc
= pipe_config
->base
.crtc
;
6299 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
6300 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6301 int pipe
= intel_crtc
->pipe
, hsw_workaround_pipe
;
6302 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
6303 struct intel_atomic_state
*old_intel_state
=
6304 to_intel_atomic_state(old_state
);
6305 bool psl_clkgate_wa
;
6307 if (WARN_ON(intel_crtc
->active
))
6310 intel_encoders_pre_pll_enable(crtc
, pipe_config
, old_state
);
6312 if (pipe_config
->shared_dpll
)
6313 intel_enable_shared_dpll(pipe_config
);
6315 intel_encoders_pre_enable(crtc
, pipe_config
, old_state
);
6317 if (intel_crtc_has_dp_encoder(pipe_config
))
6318 intel_dp_set_m_n(pipe_config
, M1_N1
);
6320 if (!transcoder_is_dsi(cpu_transcoder
))
6321 intel_set_pipe_timings(pipe_config
);
6323 intel_set_pipe_src_size(pipe_config
);
6325 if (cpu_transcoder
!= TRANSCODER_EDP
&&
6326 !transcoder_is_dsi(cpu_transcoder
)) {
6327 I915_WRITE(PIPE_MULT(cpu_transcoder
),
6328 pipe_config
->pixel_multiplier
- 1);
6331 if (pipe_config
->has_pch_encoder
) {
6332 intel_cpu_transcoder_set_m_n(pipe_config
,
6333 &pipe_config
->fdi_m_n
, NULL
);
6336 if (!transcoder_is_dsi(cpu_transcoder
))
6337 haswell_set_pipeconf(pipe_config
);
6339 if (INTEL_GEN(dev_priv
) >= 9 || IS_BROADWELL(dev_priv
))
6340 bdw_set_pipemisc(pipe_config
);
6342 intel_crtc
->active
= true;
6344 /* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
6345 psl_clkgate_wa
= (IS_GEMINILAKE(dev_priv
) || IS_CANNONLAKE(dev_priv
)) &&
6346 pipe_config
->pch_pfit
.enabled
;
6348 glk_pipe_scaler_clock_gating_wa(dev_priv
, pipe
, true);
6350 if (INTEL_GEN(dev_priv
) >= 9)
6351 skylake_pfit_enable(pipe_config
);
6353 ironlake_pfit_enable(pipe_config
);
6356 * On ILK+ LUT must be loaded before the pipe is running but with
6359 intel_color_load_luts(pipe_config
);
6360 intel_color_commit(pipe_config
);
6361 /* update DSPCNTR to configure gamma/csc for pipe bottom color */
6362 if (INTEL_GEN(dev_priv
) < 9)
6363 intel_disable_primary_plane(pipe_config
);
6365 if (INTEL_GEN(dev_priv
) >= 11)
6366 icl_set_pipe_chicken(intel_crtc
);
6368 intel_ddi_set_pipe_settings(pipe_config
);
6369 if (!transcoder_is_dsi(cpu_transcoder
))
6370 intel_ddi_enable_transcoder_func(pipe_config
);
6372 if (dev_priv
->display
.initial_watermarks
!= NULL
)
6373 dev_priv
->display
.initial_watermarks(old_intel_state
, pipe_config
);
6375 if (INTEL_GEN(dev_priv
) >= 11)
6376 icl_pipe_mbus_enable(intel_crtc
);
6378 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
6379 if (!transcoder_is_dsi(cpu_transcoder
))
6380 intel_enable_pipe(pipe_config
);
6382 if (pipe_config
->has_pch_encoder
)
6383 lpt_pch_enable(old_intel_state
, pipe_config
);
6385 if (intel_crtc_has_type(pipe_config
, INTEL_OUTPUT_DP_MST
))
6386 intel_ddi_set_vc_payload_alloc(pipe_config
, true);
6388 assert_vblank_disabled(crtc
);
6389 intel_crtc_vblank_on(pipe_config
);
6391 intel_encoders_enable(crtc
, pipe_config
, old_state
);
6393 if (psl_clkgate_wa
) {
6394 intel_wait_for_vblank(dev_priv
, pipe
);
6395 glk_pipe_scaler_clock_gating_wa(dev_priv
, pipe
, false);
6398 /* If we change the relative order between pipe/planes enabling, we need
6399 * to change the workaround. */
6400 hsw_workaround_pipe
= pipe_config
->hsw_workaround_pipe
;
6401 if (IS_HASWELL(dev_priv
) && hsw_workaround_pipe
!= INVALID_PIPE
) {
6402 intel_wait_for_vblank(dev_priv
, hsw_workaround_pipe
);
6403 intel_wait_for_vblank(dev_priv
, hsw_workaround_pipe
);
6407 static void ironlake_pfit_disable(const struct intel_crtc_state
*old_crtc_state
)
6409 struct intel_crtc
*crtc
= to_intel_crtc(old_crtc_state
->base
.crtc
);
6410 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
6411 enum pipe pipe
= crtc
->pipe
;
6413 /* To avoid upsetting the power well on haswell only disable the pfit if
6414 * it's in use. The hw state code will make sure we get this right. */
6415 if (old_crtc_state
->pch_pfit
.enabled
) {
6416 I915_WRITE(PF_CTL(pipe
), 0);
6417 I915_WRITE(PF_WIN_POS(pipe
), 0);
6418 I915_WRITE(PF_WIN_SZ(pipe
), 0);
6422 static void ironlake_crtc_disable(struct intel_crtc_state
*old_crtc_state
,
6423 struct drm_atomic_state
*old_state
)
6425 struct drm_crtc
*crtc
= old_crtc_state
->base
.crtc
;
6426 struct drm_device
*dev
= crtc
->dev
;
6427 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6428 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6429 int pipe
= intel_crtc
->pipe
;
6432 * Sometimes spurious CPU pipe underruns happen when the
6433 * pipe is already disabled, but FDI RX/TX is still enabled.
6434 * Happens at least with VGA+HDMI cloning. Suppress them.
6436 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
6437 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, false);
6439 intel_encoders_disable(crtc
, old_crtc_state
, old_state
);
6441 drm_crtc_vblank_off(crtc
);
6442 assert_vblank_disabled(crtc
);
6444 intel_disable_pipe(old_crtc_state
);
6446 ironlake_pfit_disable(old_crtc_state
);
6448 if (old_crtc_state
->has_pch_encoder
)
6449 ironlake_fdi_disable(crtc
);
6451 intel_encoders_post_disable(crtc
, old_crtc_state
, old_state
);
6453 if (old_crtc_state
->has_pch_encoder
) {
6454 ironlake_disable_pch_transcoder(dev_priv
, pipe
);
6456 if (HAS_PCH_CPT(dev_priv
)) {
6460 /* disable TRANS_DP_CTL */
6461 reg
= TRANS_DP_CTL(pipe
);
6462 temp
= I915_READ(reg
);
6463 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
|
6464 TRANS_DP_PORT_SEL_MASK
);
6465 temp
|= TRANS_DP_PORT_SEL_NONE
;
6466 I915_WRITE(reg
, temp
);
6468 /* disable DPLL_SEL */
6469 temp
= I915_READ(PCH_DPLL_SEL
);
6470 temp
&= ~(TRANS_DPLL_ENABLE(pipe
) | TRANS_DPLLB_SEL(pipe
));
6471 I915_WRITE(PCH_DPLL_SEL
, temp
);
6474 ironlake_fdi_pll_disable(intel_crtc
);
6477 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
6478 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, true);
6481 static void haswell_crtc_disable(struct intel_crtc_state
*old_crtc_state
,
6482 struct drm_atomic_state
*old_state
)
6484 struct drm_crtc
*crtc
= old_crtc_state
->base
.crtc
;
6485 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
6486 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6487 enum transcoder cpu_transcoder
= old_crtc_state
->cpu_transcoder
;
6489 intel_encoders_disable(crtc
, old_crtc_state
, old_state
);
6491 drm_crtc_vblank_off(crtc
);
6492 assert_vblank_disabled(crtc
);
6494 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
6495 if (!transcoder_is_dsi(cpu_transcoder
))
6496 intel_disable_pipe(old_crtc_state
);
6498 if (intel_crtc_has_type(old_crtc_state
, INTEL_OUTPUT_DP_MST
))
6499 intel_ddi_set_vc_payload_alloc(old_crtc_state
, false);
6501 if (!transcoder_is_dsi(cpu_transcoder
))
6502 intel_ddi_disable_transcoder_func(old_crtc_state
);
6504 intel_dsc_disable(old_crtc_state
);
6506 if (INTEL_GEN(dev_priv
) >= 9)
6507 skylake_scaler_disable(intel_crtc
);
6509 ironlake_pfit_disable(old_crtc_state
);
6511 intel_encoders_post_disable(crtc
, old_crtc_state
, old_state
);
6513 intel_encoders_post_pll_disable(crtc
, old_crtc_state
, old_state
);
6516 static void i9xx_pfit_enable(const struct intel_crtc_state
*crtc_state
)
6518 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
6519 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
6521 if (!crtc_state
->gmch_pfit
.control
)
6525 * The panel fitter should only be adjusted whilst the pipe is disabled,
6526 * according to register description and PRM.
6528 WARN_ON(I915_READ(PFIT_CONTROL
) & PFIT_ENABLE
);
6529 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
6531 I915_WRITE(PFIT_PGM_RATIOS
, crtc_state
->gmch_pfit
.pgm_ratios
);
6532 I915_WRITE(PFIT_CONTROL
, crtc_state
->gmch_pfit
.control
);
6534 /* Border color in case we don't scale up to the full screen. Black by
6535 * default, change to something else for debugging. */
6536 I915_WRITE(BCLRPAT(crtc
->pipe
), 0);
6539 bool intel_port_is_combophy(struct drm_i915_private
*dev_priv
, enum port port
)
6541 if (port
== PORT_NONE
)
6544 if (IS_ELKHARTLAKE(dev_priv
))
6545 return port
<= PORT_C
;
6547 if (INTEL_GEN(dev_priv
) >= 11)
6548 return port
<= PORT_B
;
6553 bool intel_port_is_tc(struct drm_i915_private
*dev_priv
, enum port port
)
6555 if (INTEL_GEN(dev_priv
) >= 11 && !IS_ELKHARTLAKE(dev_priv
))
6556 return port
>= PORT_C
&& port
<= PORT_F
;
6561 enum tc_port
intel_port_to_tc(struct drm_i915_private
*dev_priv
, enum port port
)
6563 if (!intel_port_is_tc(dev_priv
, port
))
6564 return PORT_TC_NONE
;
6566 return port
- PORT_C
;
6569 enum intel_display_power_domain
intel_port_to_power_domain(enum port port
)
6573 return POWER_DOMAIN_PORT_DDI_A_LANES
;
6575 return POWER_DOMAIN_PORT_DDI_B_LANES
;
6577 return POWER_DOMAIN_PORT_DDI_C_LANES
;
6579 return POWER_DOMAIN_PORT_DDI_D_LANES
;
6581 return POWER_DOMAIN_PORT_DDI_E_LANES
;
6583 return POWER_DOMAIN_PORT_DDI_F_LANES
;
6586 return POWER_DOMAIN_PORT_OTHER
;
6590 enum intel_display_power_domain
6591 intel_aux_power_domain(struct intel_digital_port
*dig_port
)
6593 switch (dig_port
->aux_ch
) {
6595 return POWER_DOMAIN_AUX_A
;
6597 return POWER_DOMAIN_AUX_B
;
6599 return POWER_DOMAIN_AUX_C
;
6601 return POWER_DOMAIN_AUX_D
;
6603 return POWER_DOMAIN_AUX_E
;
6605 return POWER_DOMAIN_AUX_F
;
6607 MISSING_CASE(dig_port
->aux_ch
);
6608 return POWER_DOMAIN_AUX_A
;
6612 static u64
get_crtc_power_domains(struct drm_crtc
*crtc
,
6613 struct intel_crtc_state
*crtc_state
)
6615 struct drm_device
*dev
= crtc
->dev
;
6616 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6617 struct drm_encoder
*encoder
;
6618 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6619 enum pipe pipe
= intel_crtc
->pipe
;
6621 enum transcoder transcoder
= crtc_state
->cpu_transcoder
;
6623 if (!crtc_state
->base
.active
)
6626 mask
= BIT_ULL(POWER_DOMAIN_PIPE(pipe
));
6627 mask
|= BIT_ULL(POWER_DOMAIN_TRANSCODER(transcoder
));
6628 if (crtc_state
->pch_pfit
.enabled
||
6629 crtc_state
->pch_pfit
.force_thru
)
6630 mask
|= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe
));
6632 drm_for_each_encoder_mask(encoder
, dev
, crtc_state
->base
.encoder_mask
) {
6633 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
6635 mask
|= BIT_ULL(intel_encoder
->power_domain
);
6638 if (HAS_DDI(dev_priv
) && crtc_state
->has_audio
)
6639 mask
|= BIT_ULL(POWER_DOMAIN_AUDIO
);
6641 if (crtc_state
->shared_dpll
)
6642 mask
|= BIT_ULL(POWER_DOMAIN_DISPLAY_CORE
);
6648 modeset_get_crtc_power_domains(struct drm_crtc
*crtc
,
6649 struct intel_crtc_state
*crtc_state
)
6651 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
6652 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6653 enum intel_display_power_domain domain
;
6654 u64 domains
, new_domains
, old_domains
;
6656 old_domains
= intel_crtc
->enabled_power_domains
;
6657 intel_crtc
->enabled_power_domains
= new_domains
=
6658 get_crtc_power_domains(crtc
, crtc_state
);
6660 domains
= new_domains
& ~old_domains
;
6662 for_each_power_domain(domain
, domains
)
6663 intel_display_power_get(dev_priv
, domain
);
6665 return old_domains
& ~new_domains
;
6668 static void modeset_put_power_domains(struct drm_i915_private
*dev_priv
,
6671 enum intel_display_power_domain domain
;
6673 for_each_power_domain(domain
, domains
)
6674 intel_display_power_put_unchecked(dev_priv
, domain
);
6677 static void valleyview_crtc_enable(struct intel_crtc_state
*pipe_config
,
6678 struct drm_atomic_state
*old_state
)
6680 struct intel_atomic_state
*old_intel_state
=
6681 to_intel_atomic_state(old_state
);
6682 struct drm_crtc
*crtc
= pipe_config
->base
.crtc
;
6683 struct drm_device
*dev
= crtc
->dev
;
6684 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6685 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6686 int pipe
= intel_crtc
->pipe
;
6688 if (WARN_ON(intel_crtc
->active
))
6691 if (intel_crtc_has_dp_encoder(pipe_config
))
6692 intel_dp_set_m_n(pipe_config
, M1_N1
);
6694 intel_set_pipe_timings(pipe_config
);
6695 intel_set_pipe_src_size(pipe_config
);
6697 if (IS_CHERRYVIEW(dev_priv
) && pipe
== PIPE_B
) {
6698 I915_WRITE(CHV_BLEND(pipe
), CHV_BLEND_LEGACY
);
6699 I915_WRITE(CHV_CANVAS(pipe
), 0);
6702 i9xx_set_pipeconf(pipe_config
);
6704 intel_crtc
->active
= true;
6706 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
6708 intel_encoders_pre_pll_enable(crtc
, pipe_config
, old_state
);
6710 if (IS_CHERRYVIEW(dev_priv
)) {
6711 chv_prepare_pll(intel_crtc
, pipe_config
);
6712 chv_enable_pll(intel_crtc
, pipe_config
);
6714 vlv_prepare_pll(intel_crtc
, pipe_config
);
6715 vlv_enable_pll(intel_crtc
, pipe_config
);
6718 intel_encoders_pre_enable(crtc
, pipe_config
, old_state
);
6720 i9xx_pfit_enable(pipe_config
);
6722 intel_color_load_luts(pipe_config
);
6723 intel_color_commit(pipe_config
);
6724 /* update DSPCNTR to configure gamma for pipe bottom color */
6725 intel_disable_primary_plane(pipe_config
);
6727 dev_priv
->display
.initial_watermarks(old_intel_state
,
6729 intel_enable_pipe(pipe_config
);
6731 assert_vblank_disabled(crtc
);
6732 intel_crtc_vblank_on(pipe_config
);
6734 intel_encoders_enable(crtc
, pipe_config
, old_state
);
6737 static void i9xx_set_pll_dividers(const struct intel_crtc_state
*crtc_state
)
6739 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
6740 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
6742 I915_WRITE(FP0(crtc
->pipe
), crtc_state
->dpll_hw_state
.fp0
);
6743 I915_WRITE(FP1(crtc
->pipe
), crtc_state
->dpll_hw_state
.fp1
);
6746 static void i9xx_crtc_enable(struct intel_crtc_state
*pipe_config
,
6747 struct drm_atomic_state
*old_state
)
6749 struct intel_atomic_state
*old_intel_state
=
6750 to_intel_atomic_state(old_state
);
6751 struct drm_crtc
*crtc
= pipe_config
->base
.crtc
;
6752 struct drm_device
*dev
= crtc
->dev
;
6753 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6754 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6755 enum pipe pipe
= intel_crtc
->pipe
;
6757 if (WARN_ON(intel_crtc
->active
))
6760 i9xx_set_pll_dividers(pipe_config
);
6762 if (intel_crtc_has_dp_encoder(pipe_config
))
6763 intel_dp_set_m_n(pipe_config
, M1_N1
);
6765 intel_set_pipe_timings(pipe_config
);
6766 intel_set_pipe_src_size(pipe_config
);
6768 i9xx_set_pipeconf(pipe_config
);
6770 intel_crtc
->active
= true;
6772 if (!IS_GEN(dev_priv
, 2))
6773 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
6775 intel_encoders_pre_enable(crtc
, pipe_config
, old_state
);
6777 i9xx_enable_pll(intel_crtc
, pipe_config
);
6779 i9xx_pfit_enable(pipe_config
);
6781 intel_color_load_luts(pipe_config
);
6782 intel_color_commit(pipe_config
);
6783 /* update DSPCNTR to configure gamma for pipe bottom color */
6784 intel_disable_primary_plane(pipe_config
);
6786 if (dev_priv
->display
.initial_watermarks
!= NULL
)
6787 dev_priv
->display
.initial_watermarks(old_intel_state
,
6790 intel_update_watermarks(intel_crtc
);
6791 intel_enable_pipe(pipe_config
);
6793 assert_vblank_disabled(crtc
);
6794 intel_crtc_vblank_on(pipe_config
);
6796 intel_encoders_enable(crtc
, pipe_config
, old_state
);
6799 static void i9xx_pfit_disable(const struct intel_crtc_state
*old_crtc_state
)
6801 struct intel_crtc
*crtc
= to_intel_crtc(old_crtc_state
->base
.crtc
);
6802 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
6804 if (!old_crtc_state
->gmch_pfit
.control
)
6807 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
6809 DRM_DEBUG_KMS("disabling pfit, current: 0x%08x\n",
6810 I915_READ(PFIT_CONTROL
));
6811 I915_WRITE(PFIT_CONTROL
, 0);
6814 static void i9xx_crtc_disable(struct intel_crtc_state
*old_crtc_state
,
6815 struct drm_atomic_state
*old_state
)
6817 struct drm_crtc
*crtc
= old_crtc_state
->base
.crtc
;
6818 struct drm_device
*dev
= crtc
->dev
;
6819 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6820 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6821 int pipe
= intel_crtc
->pipe
;
6824 * On gen2 planes are double buffered but the pipe isn't, so we must
6825 * wait for planes to fully turn off before disabling the pipe.
6827 if (IS_GEN(dev_priv
, 2))
6828 intel_wait_for_vblank(dev_priv
, pipe
);
6830 intel_encoders_disable(crtc
, old_crtc_state
, old_state
);
6832 drm_crtc_vblank_off(crtc
);
6833 assert_vblank_disabled(crtc
);
6835 intel_disable_pipe(old_crtc_state
);
6837 i9xx_pfit_disable(old_crtc_state
);
6839 intel_encoders_post_disable(crtc
, old_crtc_state
, old_state
);
6841 if (!intel_crtc_has_type(old_crtc_state
, INTEL_OUTPUT_DSI
)) {
6842 if (IS_CHERRYVIEW(dev_priv
))
6843 chv_disable_pll(dev_priv
, pipe
);
6844 else if (IS_VALLEYVIEW(dev_priv
))
6845 vlv_disable_pll(dev_priv
, pipe
);
6847 i9xx_disable_pll(old_crtc_state
);
6850 intel_encoders_post_pll_disable(crtc
, old_crtc_state
, old_state
);
6852 if (!IS_GEN(dev_priv
, 2))
6853 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
6855 if (!dev_priv
->display
.initial_watermarks
)
6856 intel_update_watermarks(intel_crtc
);
6858 /* clock the pipe down to 640x480@60 to potentially save power */
6859 if (IS_I830(dev_priv
))
6860 i830_enable_pipe(dev_priv
, pipe
);
6863 static void intel_crtc_disable_noatomic(struct drm_crtc
*crtc
,
6864 struct drm_modeset_acquire_ctx
*ctx
)
6866 struct intel_encoder
*encoder
;
6867 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6868 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
6869 enum intel_display_power_domain domain
;
6870 struct intel_plane
*plane
;
6872 struct drm_atomic_state
*state
;
6873 struct intel_crtc_state
*crtc_state
;
6876 if (!intel_crtc
->active
)
6879 for_each_intel_plane_on_crtc(&dev_priv
->drm
, intel_crtc
, plane
) {
6880 const struct intel_plane_state
*plane_state
=
6881 to_intel_plane_state(plane
->base
.state
);
6883 if (plane_state
->base
.visible
)
6884 intel_plane_disable_noatomic(intel_crtc
, plane
);
6887 state
= drm_atomic_state_alloc(crtc
->dev
);
6889 DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory",
6890 crtc
->base
.id
, crtc
->name
);
6894 state
->acquire_ctx
= ctx
;
6896 /* Everything's already locked, -EDEADLK can't happen. */
6897 crtc_state
= intel_atomic_get_crtc_state(state
, intel_crtc
);
6898 ret
= drm_atomic_add_affected_connectors(state
, crtc
);
6900 WARN_ON(IS_ERR(crtc_state
) || ret
);
6902 dev_priv
->display
.crtc_disable(crtc_state
, state
);
6904 drm_atomic_state_put(state
);
6906 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
6907 crtc
->base
.id
, crtc
->name
);
6909 WARN_ON(drm_atomic_set_mode_for_crtc(crtc
->state
, NULL
) < 0);
6910 crtc
->state
->active
= false;
6911 intel_crtc
->active
= false;
6912 crtc
->enabled
= false;
6913 crtc
->state
->connector_mask
= 0;
6914 crtc
->state
->encoder_mask
= 0;
6916 for_each_encoder_on_crtc(crtc
->dev
, crtc
, encoder
)
6917 encoder
->base
.crtc
= NULL
;
6919 intel_fbc_disable(intel_crtc
);
6920 intel_update_watermarks(intel_crtc
);
6921 intel_disable_shared_dpll(to_intel_crtc_state(crtc
->state
));
6923 domains
= intel_crtc
->enabled_power_domains
;
6924 for_each_power_domain(domain
, domains
)
6925 intel_display_power_put_unchecked(dev_priv
, domain
);
6926 intel_crtc
->enabled_power_domains
= 0;
6928 dev_priv
->active_crtcs
&= ~(1 << intel_crtc
->pipe
);
6929 dev_priv
->min_cdclk
[intel_crtc
->pipe
] = 0;
6930 dev_priv
->min_voltage_level
[intel_crtc
->pipe
] = 0;
6934 * turn all crtc's off, but do not adjust state
6935 * This has to be paired with a call to intel_modeset_setup_hw_state.
6937 int intel_display_suspend(struct drm_device
*dev
)
6939 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6940 struct drm_atomic_state
*state
;
6943 state
= drm_atomic_helper_suspend(dev
);
6944 ret
= PTR_ERR_OR_ZERO(state
);
6946 DRM_ERROR("Suspending crtc's failed with %i\n", ret
);
6948 dev_priv
->modeset_restore_state
= state
;
6952 void intel_encoder_destroy(struct drm_encoder
*encoder
)
6954 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
6956 drm_encoder_cleanup(encoder
);
6957 kfree(intel_encoder
);
6960 /* Cross check the actual hw state with our own modeset state tracking (and it's
6961 * internal consistency). */
6962 static void intel_connector_verify_state(struct drm_crtc_state
*crtc_state
,
6963 struct drm_connector_state
*conn_state
)
6965 struct intel_connector
*connector
= to_intel_connector(conn_state
->connector
);
6967 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6968 connector
->base
.base
.id
,
6969 connector
->base
.name
);
6971 if (connector
->get_hw_state(connector
)) {
6972 struct intel_encoder
*encoder
= connector
->encoder
;
6974 I915_STATE_WARN(!crtc_state
,
6975 "connector enabled without attached crtc\n");
6980 I915_STATE_WARN(!crtc_state
->active
,
6981 "connector is active, but attached crtc isn't\n");
6983 if (!encoder
|| encoder
->type
== INTEL_OUTPUT_DP_MST
)
6986 I915_STATE_WARN(conn_state
->best_encoder
!= &encoder
->base
,
6987 "atomic encoder doesn't match attached encoder\n");
6989 I915_STATE_WARN(conn_state
->crtc
!= encoder
->base
.crtc
,
6990 "attached encoder crtc differs from connector crtc\n");
6992 I915_STATE_WARN(crtc_state
&& crtc_state
->active
,
6993 "attached crtc is active, but connector isn't\n");
6994 I915_STATE_WARN(!crtc_state
&& conn_state
->best_encoder
,
6995 "best encoder set without crtc!\n");
6999 static int pipe_required_fdi_lanes(struct intel_crtc_state
*crtc_state
)
7001 if (crtc_state
->base
.enable
&& crtc_state
->has_pch_encoder
)
7002 return crtc_state
->fdi_lanes
;
7007 static int ironlake_check_fdi_lanes(struct drm_device
*dev
, enum pipe pipe
,
7008 struct intel_crtc_state
*pipe_config
)
7010 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7011 struct drm_atomic_state
*state
= pipe_config
->base
.state
;
7012 struct intel_crtc
*other_crtc
;
7013 struct intel_crtc_state
*other_crtc_state
;
7015 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
7016 pipe_name(pipe
), pipe_config
->fdi_lanes
);
7017 if (pipe_config
->fdi_lanes
> 4) {
7018 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
7019 pipe_name(pipe
), pipe_config
->fdi_lanes
);
7023 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
7024 if (pipe_config
->fdi_lanes
> 2) {
7025 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
7026 pipe_config
->fdi_lanes
);
7033 if (INTEL_INFO(dev_priv
)->num_pipes
== 2)
7036 /* Ivybridge 3 pipe is really complicated */
7041 if (pipe_config
->fdi_lanes
<= 2)
7044 other_crtc
= intel_get_crtc_for_pipe(dev_priv
, PIPE_C
);
7046 intel_atomic_get_crtc_state(state
, other_crtc
);
7047 if (IS_ERR(other_crtc_state
))
7048 return PTR_ERR(other_crtc_state
);
7050 if (pipe_required_fdi_lanes(other_crtc_state
) > 0) {
7051 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
7052 pipe_name(pipe
), pipe_config
->fdi_lanes
);
7057 if (pipe_config
->fdi_lanes
> 2) {
7058 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
7059 pipe_name(pipe
), pipe_config
->fdi_lanes
);
7063 other_crtc
= intel_get_crtc_for_pipe(dev_priv
, PIPE_B
);
7065 intel_atomic_get_crtc_state(state
, other_crtc
);
7066 if (IS_ERR(other_crtc_state
))
7067 return PTR_ERR(other_crtc_state
);
7069 if (pipe_required_fdi_lanes(other_crtc_state
) > 2) {
7070 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
7080 static int ironlake_fdi_compute_config(struct intel_crtc
*intel_crtc
,
7081 struct intel_crtc_state
*pipe_config
)
7083 struct drm_device
*dev
= intel_crtc
->base
.dev
;
7084 const struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
7085 int lane
, link_bw
, fdi_dotclock
, ret
;
7086 bool needs_recompute
= false;
7089 /* FDI is a binary signal running at ~2.7GHz, encoding
7090 * each output octet as 10 bits. The actual frequency
7091 * is stored as a divider into a 100MHz clock, and the
7092 * mode pixel clock is stored in units of 1KHz.
7093 * Hence the bw of each lane in terms of the mode signal
7096 link_bw
= intel_fdi_link_freq(to_i915(dev
), pipe_config
);
7098 fdi_dotclock
= adjusted_mode
->crtc_clock
;
7100 lane
= ironlake_get_lanes_required(fdi_dotclock
, link_bw
,
7101 pipe_config
->pipe_bpp
);
7103 pipe_config
->fdi_lanes
= lane
;
7105 intel_link_compute_m_n(pipe_config
->pipe_bpp
, lane
, fdi_dotclock
,
7106 link_bw
, &pipe_config
->fdi_m_n
, false);
7108 ret
= ironlake_check_fdi_lanes(dev
, intel_crtc
->pipe
, pipe_config
);
7109 if (ret
== -EDEADLK
)
7112 if (ret
== -EINVAL
&& pipe_config
->pipe_bpp
> 6*3) {
7113 pipe_config
->pipe_bpp
-= 2*3;
7114 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
7115 pipe_config
->pipe_bpp
);
7116 needs_recompute
= true;
7117 pipe_config
->bw_constrained
= true;
7122 if (needs_recompute
)
7128 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state
*crtc_state
)
7130 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
7131 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
7133 /* IPS only exists on ULT machines and is tied to pipe A. */
7134 if (!hsw_crtc_supports_ips(crtc
))
7137 if (!i915_modparams
.enable_ips
)
7140 if (crtc_state
->pipe_bpp
> 24)
7144 * We compare against max which means we must take
7145 * the increased cdclk requirement into account when
7146 * calculating the new cdclk.
7148 * Should measure whether using a lower cdclk w/o IPS
7150 if (IS_BROADWELL(dev_priv
) &&
7151 crtc_state
->pixel_rate
> dev_priv
->max_cdclk_freq
* 95 / 100)
7157 static bool hsw_compute_ips_config(struct intel_crtc_state
*crtc_state
)
7159 struct drm_i915_private
*dev_priv
=
7160 to_i915(crtc_state
->base
.crtc
->dev
);
7161 struct intel_atomic_state
*intel_state
=
7162 to_intel_atomic_state(crtc_state
->base
.state
);
7164 if (!hsw_crtc_state_ips_capable(crtc_state
))
7168 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
7169 * enabled and disabled dynamically based on package C states,
7170 * user space can't make reliable use of the CRCs, so let's just
7171 * completely disable it.
7173 if (crtc_state
->crc_enabled
)
7176 /* IPS should be fine as long as at least one plane is enabled. */
7177 if (!(crtc_state
->active_planes
& ~BIT(PLANE_CURSOR
)))
7180 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
7181 if (IS_BROADWELL(dev_priv
) &&
7182 crtc_state
->pixel_rate
> intel_state
->cdclk
.logical
.cdclk
* 95 / 100)
7188 static bool intel_crtc_supports_double_wide(const struct intel_crtc
*crtc
)
7190 const struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
7192 /* GDG double wide on either pipe, otherwise pipe A only */
7193 return INTEL_GEN(dev_priv
) < 4 &&
7194 (crtc
->pipe
== PIPE_A
|| IS_I915G(dev_priv
));
7197 static u32
ilk_pipe_pixel_rate(const struct intel_crtc_state
*pipe_config
)
7201 pixel_rate
= pipe_config
->base
.adjusted_mode
.crtc_clock
;
7204 * We only use IF-ID interlacing. If we ever use
7205 * PF-ID we'll need to adjust the pixel_rate here.
7208 if (pipe_config
->pch_pfit
.enabled
) {
7209 u64 pipe_w
, pipe_h
, pfit_w
, pfit_h
;
7210 u32 pfit_size
= pipe_config
->pch_pfit
.size
;
7212 pipe_w
= pipe_config
->pipe_src_w
;
7213 pipe_h
= pipe_config
->pipe_src_h
;
7215 pfit_w
= (pfit_size
>> 16) & 0xFFFF;
7216 pfit_h
= pfit_size
& 0xFFFF;
7217 if (pipe_w
< pfit_w
)
7219 if (pipe_h
< pfit_h
)
7222 if (WARN_ON(!pfit_w
|| !pfit_h
))
7225 pixel_rate
= div_u64(mul_u32_u32(pixel_rate
, pipe_w
* pipe_h
),
7232 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state
*crtc_state
)
7234 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->base
.crtc
->dev
);
7236 if (HAS_GMCH(dev_priv
))
7237 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
7238 crtc_state
->pixel_rate
=
7239 crtc_state
->base
.adjusted_mode
.crtc_clock
;
7241 crtc_state
->pixel_rate
=
7242 ilk_pipe_pixel_rate(crtc_state
);
7245 static int intel_crtc_compute_config(struct intel_crtc
*crtc
,
7246 struct intel_crtc_state
*pipe_config
)
7248 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
7249 const struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
7250 int clock_limit
= dev_priv
->max_dotclk_freq
;
7252 if (INTEL_GEN(dev_priv
) < 4) {
7253 clock_limit
= dev_priv
->max_cdclk_freq
* 9 / 10;
7256 * Enable double wide mode when the dot clock
7257 * is > 90% of the (display) core speed.
7259 if (intel_crtc_supports_double_wide(crtc
) &&
7260 adjusted_mode
->crtc_clock
> clock_limit
) {
7261 clock_limit
= dev_priv
->max_dotclk_freq
;
7262 pipe_config
->double_wide
= true;
7266 if (adjusted_mode
->crtc_clock
> clock_limit
) {
7267 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
7268 adjusted_mode
->crtc_clock
, clock_limit
,
7269 yesno(pipe_config
->double_wide
));
7273 if ((pipe_config
->output_format
== INTEL_OUTPUT_FORMAT_YCBCR420
||
7274 pipe_config
->output_format
== INTEL_OUTPUT_FORMAT_YCBCR444
) &&
7275 pipe_config
->base
.ctm
) {
7277 * There is only one pipe CSC unit per pipe, and we need that
7278 * for output conversion from RGB->YCBCR. So if CTM is already
7279 * applied we can't support YCBCR420 output.
7281 DRM_DEBUG_KMS("YCBCR420 and CTM together are not possible\n");
7286 * Pipe horizontal size must be even in:
7288 * - LVDS dual channel mode
7289 * - Double wide pipe
7291 if (pipe_config
->pipe_src_w
& 1) {
7292 if (pipe_config
->double_wide
) {
7293 DRM_DEBUG_KMS("Odd pipe source width not supported with double wide pipe\n");
7297 if (intel_crtc_has_type(pipe_config
, INTEL_OUTPUT_LVDS
) &&
7298 intel_is_dual_link_lvds(dev_priv
)) {
7299 DRM_DEBUG_KMS("Odd pipe source width not supported with dual link LVDS\n");
7304 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
7305 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
7307 if ((INTEL_GEN(dev_priv
) > 4 || IS_G4X(dev_priv
)) &&
7308 adjusted_mode
->crtc_hsync_start
== adjusted_mode
->crtc_hdisplay
)
7311 intel_crtc_compute_pixel_rate(pipe_config
);
7313 if (pipe_config
->has_pch_encoder
)
7314 return ironlake_fdi_compute_config(crtc
, pipe_config
);
7320 intel_reduce_m_n_ratio(u32
*num
, u32
*den
)
7322 while (*num
> DATA_LINK_M_N_MASK
||
7323 *den
> DATA_LINK_M_N_MASK
) {
7329 static void compute_m_n(unsigned int m
, unsigned int n
,
7330 u32
*ret_m
, u32
*ret_n
,
7334 * Several DP dongles in particular seem to be fussy about
7335 * too large link M/N values. Give N value as 0x8000 that
7336 * should be acceptable by specific devices. 0x8000 is the
7337 * specified fixed N value for asynchronous clock mode,
7338 * which the devices expect also in synchronous clock mode.
7343 *ret_n
= min_t(unsigned int, roundup_pow_of_two(n
), DATA_LINK_N_MAX
);
7345 *ret_m
= div_u64(mul_u32_u32(m
, *ret_n
), n
);
7346 intel_reduce_m_n_ratio(ret_m
, ret_n
);
7350 intel_link_compute_m_n(u16 bits_per_pixel
, int nlanes
,
7351 int pixel_clock
, int link_clock
,
7352 struct intel_link_m_n
*m_n
,
7357 compute_m_n(bits_per_pixel
* pixel_clock
,
7358 link_clock
* nlanes
* 8,
7359 &m_n
->gmch_m
, &m_n
->gmch_n
,
7362 compute_m_n(pixel_clock
, link_clock
,
7363 &m_n
->link_m
, &m_n
->link_n
,
7367 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
7369 if (i915_modparams
.panel_use_ssc
>= 0)
7370 return i915_modparams
.panel_use_ssc
!= 0;
7371 return dev_priv
->vbt
.lvds_use_ssc
7372 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
7375 static u32
pnv_dpll_compute_fp(struct dpll
*dpll
)
7377 return (1 << dpll
->n
) << 16 | dpll
->m2
;
7380 static u32
i9xx_dpll_compute_fp(struct dpll
*dpll
)
7382 return dpll
->n
<< 16 | dpll
->m1
<< 8 | dpll
->m2
;
7385 static void i9xx_update_pll_dividers(struct intel_crtc
*crtc
,
7386 struct intel_crtc_state
*crtc_state
,
7387 struct dpll
*reduced_clock
)
7389 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
7392 if (IS_PINEVIEW(dev_priv
)) {
7393 fp
= pnv_dpll_compute_fp(&crtc_state
->dpll
);
7395 fp2
= pnv_dpll_compute_fp(reduced_clock
);
7397 fp
= i9xx_dpll_compute_fp(&crtc_state
->dpll
);
7399 fp2
= i9xx_dpll_compute_fp(reduced_clock
);
7402 crtc_state
->dpll_hw_state
.fp0
= fp
;
7404 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
7406 crtc_state
->dpll_hw_state
.fp1
= fp2
;
7408 crtc_state
->dpll_hw_state
.fp1
= fp
;
7412 static void vlv_pllb_recal_opamp(struct drm_i915_private
*dev_priv
, enum pipe
7418 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7419 * and set it to a reasonable value instead.
7421 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
7422 reg_val
&= 0xffffff00;
7423 reg_val
|= 0x00000030;
7424 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
7426 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
7427 reg_val
&= 0x00ffffff;
7428 reg_val
|= 0x8c000000;
7429 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
7431 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
7432 reg_val
&= 0xffffff00;
7433 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
7435 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
7436 reg_val
&= 0x00ffffff;
7437 reg_val
|= 0xb0000000;
7438 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
7441 static void intel_pch_transcoder_set_m_n(const struct intel_crtc_state
*crtc_state
,
7442 const struct intel_link_m_n
*m_n
)
7444 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
7445 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
7446 enum pipe pipe
= crtc
->pipe
;
7448 I915_WRITE(PCH_TRANS_DATA_M1(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
7449 I915_WRITE(PCH_TRANS_DATA_N1(pipe
), m_n
->gmch_n
);
7450 I915_WRITE(PCH_TRANS_LINK_M1(pipe
), m_n
->link_m
);
7451 I915_WRITE(PCH_TRANS_LINK_N1(pipe
), m_n
->link_n
);
7454 static bool transcoder_has_m2_n2(struct drm_i915_private
*dev_priv
,
7455 enum transcoder transcoder
)
7457 if (IS_HASWELL(dev_priv
))
7458 return transcoder
== TRANSCODER_EDP
;
7461 * Strictly speaking some registers are available before
7462 * gen7, but we only support DRRS on gen7+
7464 return IS_GEN(dev_priv
, 7) || IS_CHERRYVIEW(dev_priv
);
7467 static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state
*crtc_state
,
7468 const struct intel_link_m_n
*m_n
,
7469 const struct intel_link_m_n
*m2_n2
)
7471 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
7472 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
7473 enum pipe pipe
= crtc
->pipe
;
7474 enum transcoder transcoder
= crtc_state
->cpu_transcoder
;
7476 if (INTEL_GEN(dev_priv
) >= 5) {
7477 I915_WRITE(PIPE_DATA_M1(transcoder
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
7478 I915_WRITE(PIPE_DATA_N1(transcoder
), m_n
->gmch_n
);
7479 I915_WRITE(PIPE_LINK_M1(transcoder
), m_n
->link_m
);
7480 I915_WRITE(PIPE_LINK_N1(transcoder
), m_n
->link_n
);
7482 * M2_N2 registers are set only if DRRS is supported
7483 * (to make sure the registers are not unnecessarily accessed).
7485 if (m2_n2
&& crtc_state
->has_drrs
&&
7486 transcoder_has_m2_n2(dev_priv
, transcoder
)) {
7487 I915_WRITE(PIPE_DATA_M2(transcoder
),
7488 TU_SIZE(m2_n2
->tu
) | m2_n2
->gmch_m
);
7489 I915_WRITE(PIPE_DATA_N2(transcoder
), m2_n2
->gmch_n
);
7490 I915_WRITE(PIPE_LINK_M2(transcoder
), m2_n2
->link_m
);
7491 I915_WRITE(PIPE_LINK_N2(transcoder
), m2_n2
->link_n
);
7494 I915_WRITE(PIPE_DATA_M_G4X(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
7495 I915_WRITE(PIPE_DATA_N_G4X(pipe
), m_n
->gmch_n
);
7496 I915_WRITE(PIPE_LINK_M_G4X(pipe
), m_n
->link_m
);
7497 I915_WRITE(PIPE_LINK_N_G4X(pipe
), m_n
->link_n
);
7501 void intel_dp_set_m_n(const struct intel_crtc_state
*crtc_state
, enum link_m_n_set m_n
)
7503 const struct intel_link_m_n
*dp_m_n
, *dp_m2_n2
= NULL
;
7506 dp_m_n
= &crtc_state
->dp_m_n
;
7507 dp_m2_n2
= &crtc_state
->dp_m2_n2
;
7508 } else if (m_n
== M2_N2
) {
7511 * M2_N2 registers are not supported. Hence m2_n2 divider value
7512 * needs to be programmed into M1_N1.
7514 dp_m_n
= &crtc_state
->dp_m2_n2
;
7516 DRM_ERROR("Unsupported divider value\n");
7520 if (crtc_state
->has_pch_encoder
)
7521 intel_pch_transcoder_set_m_n(crtc_state
, &crtc_state
->dp_m_n
);
7523 intel_cpu_transcoder_set_m_n(crtc_state
, dp_m_n
, dp_m2_n2
);
7526 static void vlv_compute_dpll(struct intel_crtc
*crtc
,
7527 struct intel_crtc_state
*pipe_config
)
7529 pipe_config
->dpll_hw_state
.dpll
= DPLL_INTEGRATED_REF_CLK_VLV
|
7530 DPLL_REF_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
;
7531 if (crtc
->pipe
!= PIPE_A
)
7532 pipe_config
->dpll_hw_state
.dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
7534 /* DPLL not used with DSI, but still need the rest set up */
7535 if (!intel_crtc_has_type(pipe_config
, INTEL_OUTPUT_DSI
))
7536 pipe_config
->dpll_hw_state
.dpll
|= DPLL_VCO_ENABLE
|
7537 DPLL_EXT_BUFFER_ENABLE_VLV
;
7539 pipe_config
->dpll_hw_state
.dpll_md
=
7540 (pipe_config
->pixel_multiplier
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
7543 static void chv_compute_dpll(struct intel_crtc
*crtc
,
7544 struct intel_crtc_state
*pipe_config
)
7546 pipe_config
->dpll_hw_state
.dpll
= DPLL_SSC_REF_CLK_CHV
|
7547 DPLL_REF_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
;
7548 if (crtc
->pipe
!= PIPE_A
)
7549 pipe_config
->dpll_hw_state
.dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
7551 /* DPLL not used with DSI, but still need the rest set up */
7552 if (!intel_crtc_has_type(pipe_config
, INTEL_OUTPUT_DSI
))
7553 pipe_config
->dpll_hw_state
.dpll
|= DPLL_VCO_ENABLE
;
7555 pipe_config
->dpll_hw_state
.dpll_md
=
7556 (pipe_config
->pixel_multiplier
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
7559 static void vlv_prepare_pll(struct intel_crtc
*crtc
,
7560 const struct intel_crtc_state
*pipe_config
)
7562 struct drm_device
*dev
= crtc
->base
.dev
;
7563 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7564 enum pipe pipe
= crtc
->pipe
;
7566 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
7567 u32 coreclk
, reg_val
;
7570 I915_WRITE(DPLL(pipe
),
7571 pipe_config
->dpll_hw_state
.dpll
&
7572 ~(DPLL_VCO_ENABLE
| DPLL_EXT_BUFFER_ENABLE_VLV
));
7574 /* No need to actually set up the DPLL with DSI */
7575 if ((pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
) == 0)
7578 vlv_dpio_get(dev_priv
);
7580 bestn
= pipe_config
->dpll
.n
;
7581 bestm1
= pipe_config
->dpll
.m1
;
7582 bestm2
= pipe_config
->dpll
.m2
;
7583 bestp1
= pipe_config
->dpll
.p1
;
7584 bestp2
= pipe_config
->dpll
.p2
;
7586 /* See eDP HDMI DPIO driver vbios notes doc */
7588 /* PLL B needs special handling */
7590 vlv_pllb_recal_opamp(dev_priv
, pipe
);
7592 /* Set up Tx target for periodic Rcomp update */
7593 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9_BCAST
, 0x0100000f);
7595 /* Disable target IRef on PLL */
7596 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW8(pipe
));
7597 reg_val
&= 0x00ffffff;
7598 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW8(pipe
), reg_val
);
7600 /* Disable fast lock */
7601 vlv_dpio_write(dev_priv
, pipe
, VLV_CMN_DW0
, 0x610);
7603 /* Set idtafcrecal before PLL is enabled */
7604 mdiv
= ((bestm1
<< DPIO_M1DIV_SHIFT
) | (bestm2
& DPIO_M2DIV_MASK
));
7605 mdiv
|= ((bestp1
<< DPIO_P1_SHIFT
) | (bestp2
<< DPIO_P2_SHIFT
));
7606 mdiv
|= ((bestn
<< DPIO_N_SHIFT
));
7607 mdiv
|= (1 << DPIO_K_SHIFT
);
7610 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7611 * but we don't support that).
7612 * Note: don't use the DAC post divider as it seems unstable.
7614 mdiv
|= (DPIO_POST_DIV_HDMIDP
<< DPIO_POST_DIV_SHIFT
);
7615 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
7617 mdiv
|= DPIO_ENABLE_CALIBRATION
;
7618 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
7620 /* Set HBR and RBR LPF coefficients */
7621 if (pipe_config
->port_clock
== 162000 ||
7622 intel_crtc_has_type(pipe_config
, INTEL_OUTPUT_ANALOG
) ||
7623 intel_crtc_has_type(pipe_config
, INTEL_OUTPUT_HDMI
))
7624 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
7627 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
7630 if (intel_crtc_has_dp_encoder(pipe_config
)) {
7631 /* Use SSC source */
7633 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
7636 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
7638 } else { /* HDMI or VGA */
7639 /* Use bend source */
7641 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
7644 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
7648 coreclk
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW7(pipe
));
7649 coreclk
= (coreclk
& 0x0000ff00) | 0x01c00000;
7650 if (intel_crtc_has_dp_encoder(pipe_config
))
7651 coreclk
|= 0x01000000;
7652 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW7(pipe
), coreclk
);
7654 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW11(pipe
), 0x87871000);
7656 vlv_dpio_put(dev_priv
);
7659 static void chv_prepare_pll(struct intel_crtc
*crtc
,
7660 const struct intel_crtc_state
*pipe_config
)
7662 struct drm_device
*dev
= crtc
->base
.dev
;
7663 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7664 enum pipe pipe
= crtc
->pipe
;
7665 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
7666 u32 loopfilter
, tribuf_calcntr
;
7667 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
, bestm2_frac
;
7671 /* Enable Refclk and SSC */
7672 I915_WRITE(DPLL(pipe
),
7673 pipe_config
->dpll_hw_state
.dpll
& ~DPLL_VCO_ENABLE
);
7675 /* No need to actually set up the DPLL with DSI */
7676 if ((pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
) == 0)
7679 bestn
= pipe_config
->dpll
.n
;
7680 bestm2_frac
= pipe_config
->dpll
.m2
& 0x3fffff;
7681 bestm1
= pipe_config
->dpll
.m1
;
7682 bestm2
= pipe_config
->dpll
.m2
>> 22;
7683 bestp1
= pipe_config
->dpll
.p1
;
7684 bestp2
= pipe_config
->dpll
.p2
;
7685 vco
= pipe_config
->dpll
.vco
;
7689 vlv_dpio_get(dev_priv
);
7691 /* p1 and p2 divider */
7692 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW13(port
),
7693 5 << DPIO_CHV_S1_DIV_SHIFT
|
7694 bestp1
<< DPIO_CHV_P1_DIV_SHIFT
|
7695 bestp2
<< DPIO_CHV_P2_DIV_SHIFT
|
7696 1 << DPIO_CHV_K_DIV_SHIFT
);
7698 /* Feedback post-divider - m2 */
7699 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW0(port
), bestm2
);
7701 /* Feedback refclk divider - n and m1 */
7702 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW1(port
),
7703 DPIO_CHV_M1_DIV_BY_2
|
7704 1 << DPIO_CHV_N_DIV_SHIFT
);
7706 /* M2 fraction division */
7707 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW2(port
), bestm2_frac
);
7709 /* M2 fraction division enable */
7710 dpio_val
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW3(port
));
7711 dpio_val
&= ~(DPIO_CHV_FEEDFWD_GAIN_MASK
| DPIO_CHV_FRAC_DIV_EN
);
7712 dpio_val
|= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT
);
7714 dpio_val
|= DPIO_CHV_FRAC_DIV_EN
;
7715 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW3(port
), dpio_val
);
7717 /* Program digital lock detect threshold */
7718 dpio_val
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW9(port
));
7719 dpio_val
&= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK
|
7720 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE
);
7721 dpio_val
|= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT
);
7723 dpio_val
|= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE
;
7724 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW9(port
), dpio_val
);
7727 if (vco
== 5400000) {
7728 loopfilter
|= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT
);
7729 loopfilter
|= (0x8 << DPIO_CHV_INT_COEFF_SHIFT
);
7730 loopfilter
|= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7731 tribuf_calcntr
= 0x9;
7732 } else if (vco
<= 6200000) {
7733 loopfilter
|= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT
);
7734 loopfilter
|= (0xB << DPIO_CHV_INT_COEFF_SHIFT
);
7735 loopfilter
|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7736 tribuf_calcntr
= 0x9;
7737 } else if (vco
<= 6480000) {
7738 loopfilter
|= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT
);
7739 loopfilter
|= (0x9 << DPIO_CHV_INT_COEFF_SHIFT
);
7740 loopfilter
|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7741 tribuf_calcntr
= 0x8;
7743 /* Not supported. Apply the same limits as in the max case */
7744 loopfilter
|= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT
);
7745 loopfilter
|= (0x9 << DPIO_CHV_INT_COEFF_SHIFT
);
7746 loopfilter
|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7749 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW6(port
), loopfilter
);
7751 dpio_val
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW8(port
));
7752 dpio_val
&= ~DPIO_CHV_TDC_TARGET_CNT_MASK
;
7753 dpio_val
|= (tribuf_calcntr
<< DPIO_CHV_TDC_TARGET_CNT_SHIFT
);
7754 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW8(port
), dpio_val
);
7757 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
),
7758 vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
)) |
7761 vlv_dpio_put(dev_priv
);
7765 * vlv_force_pll_on - forcibly enable just the PLL
7766 * @dev_priv: i915 private structure
7767 * @pipe: pipe PLL to enable
7768 * @dpll: PLL configuration
7770 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7771 * in cases where we need the PLL enabled even when @pipe is not going to
7774 int vlv_force_pll_on(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
7775 const struct dpll
*dpll
)
7777 struct intel_crtc
*crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
7778 struct intel_crtc_state
*pipe_config
;
7780 pipe_config
= kzalloc(sizeof(*pipe_config
), GFP_KERNEL
);
7784 pipe_config
->base
.crtc
= &crtc
->base
;
7785 pipe_config
->pixel_multiplier
= 1;
7786 pipe_config
->dpll
= *dpll
;
7788 if (IS_CHERRYVIEW(dev_priv
)) {
7789 chv_compute_dpll(crtc
, pipe_config
);
7790 chv_prepare_pll(crtc
, pipe_config
);
7791 chv_enable_pll(crtc
, pipe_config
);
7793 vlv_compute_dpll(crtc
, pipe_config
);
7794 vlv_prepare_pll(crtc
, pipe_config
);
7795 vlv_enable_pll(crtc
, pipe_config
);
7804 * vlv_force_pll_off - forcibly disable just the PLL
7805 * @dev_priv: i915 private structure
7806 * @pipe: pipe PLL to disable
7808 * Disable the PLL for @pipe. To be used in cases where we need
7809 * the PLL enabled even when @pipe is not going to be enabled.
7811 void vlv_force_pll_off(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
7813 if (IS_CHERRYVIEW(dev_priv
))
7814 chv_disable_pll(dev_priv
, pipe
);
7816 vlv_disable_pll(dev_priv
, pipe
);
7819 static void i9xx_compute_dpll(struct intel_crtc
*crtc
,
7820 struct intel_crtc_state
*crtc_state
,
7821 struct dpll
*reduced_clock
)
7823 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
7825 struct dpll
*clock
= &crtc_state
->dpll
;
7827 i9xx_update_pll_dividers(crtc
, crtc_state
, reduced_clock
);
7829 dpll
= DPLL_VGA_MODE_DIS
;
7831 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
))
7832 dpll
|= DPLLB_MODE_LVDS
;
7834 dpll
|= DPLLB_MODE_DAC_SERIAL
;
7836 if (IS_I945G(dev_priv
) || IS_I945GM(dev_priv
) ||
7837 IS_G33(dev_priv
) || IS_PINEVIEW(dev_priv
)) {
7838 dpll
|= (crtc_state
->pixel_multiplier
- 1)
7839 << SDVO_MULTIPLIER_SHIFT_HIRES
;
7842 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_SDVO
) ||
7843 intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_HDMI
))
7844 dpll
|= DPLL_SDVO_HIGH_SPEED
;
7846 if (intel_crtc_has_dp_encoder(crtc_state
))
7847 dpll
|= DPLL_SDVO_HIGH_SPEED
;
7849 /* compute bitmask from p1 value */
7850 if (IS_PINEVIEW(dev_priv
))
7851 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
7853 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7854 if (IS_G4X(dev_priv
) && reduced_clock
)
7855 dpll
|= (1 << (reduced_clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
7857 switch (clock
->p2
) {
7859 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
7862 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
7865 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
7868 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
7871 if (INTEL_GEN(dev_priv
) >= 4)
7872 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
7874 if (crtc_state
->sdvo_tv_clock
)
7875 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
7876 else if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
7877 intel_panel_use_ssc(dev_priv
))
7878 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
7880 dpll
|= PLL_REF_INPUT_DREFCLK
;
7882 dpll
|= DPLL_VCO_ENABLE
;
7883 crtc_state
->dpll_hw_state
.dpll
= dpll
;
7885 if (INTEL_GEN(dev_priv
) >= 4) {
7886 u32 dpll_md
= (crtc_state
->pixel_multiplier
- 1)
7887 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
7888 crtc_state
->dpll_hw_state
.dpll_md
= dpll_md
;
7892 static void i8xx_compute_dpll(struct intel_crtc
*crtc
,
7893 struct intel_crtc_state
*crtc_state
,
7894 struct dpll
*reduced_clock
)
7896 struct drm_device
*dev
= crtc
->base
.dev
;
7897 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7899 struct dpll
*clock
= &crtc_state
->dpll
;
7901 i9xx_update_pll_dividers(crtc
, crtc_state
, reduced_clock
);
7903 dpll
= DPLL_VGA_MODE_DIS
;
7905 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
7906 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7909 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
7911 dpll
|= (clock
->p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7913 dpll
|= PLL_P2_DIVIDE_BY_4
;
7918 * "[Almador Errata}: For the correct operation of the muxed DVO pins
7919 * (GDEVSELB/I2Cdata, GIRDBY/I2CClk) and (GFRAMEB/DVI_Data,
7920 * GTRDYB/DVI_Clk): Bit 31 (DPLL VCO Enable) and Bit 30 (2X Clock
7921 * Enable) must be set to “1” in both the DPLL A Control Register
7922 * (06014h-06017h) and DPLL B Control Register (06018h-0601Bh)."
7924 * For simplicity We simply keep both bits always enabled in
7925 * both DPLLS. The spec says we should disable the DVO 2X clock
7926 * when not needed, but this seems to work fine in practice.
7928 if (IS_I830(dev_priv
) ||
7929 intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_DVO
))
7930 dpll
|= DPLL_DVO_2X_MODE
;
7932 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
7933 intel_panel_use_ssc(dev_priv
))
7934 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
7936 dpll
|= PLL_REF_INPUT_DREFCLK
;
7938 dpll
|= DPLL_VCO_ENABLE
;
7939 crtc_state
->dpll_hw_state
.dpll
= dpll
;
7942 static void intel_set_pipe_timings(const struct intel_crtc_state
*crtc_state
)
7944 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
7945 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
7946 enum pipe pipe
= crtc
->pipe
;
7947 enum transcoder cpu_transcoder
= crtc_state
->cpu_transcoder
;
7948 const struct drm_display_mode
*adjusted_mode
= &crtc_state
->base
.adjusted_mode
;
7949 u32 crtc_vtotal
, crtc_vblank_end
;
7952 /* We need to be careful not to changed the adjusted mode, for otherwise
7953 * the hw state checker will get angry at the mismatch. */
7954 crtc_vtotal
= adjusted_mode
->crtc_vtotal
;
7955 crtc_vblank_end
= adjusted_mode
->crtc_vblank_end
;
7957 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
7958 /* the chip adds 2 halflines automatically */
7960 crtc_vblank_end
-= 1;
7962 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_SDVO
))
7963 vsyncshift
= (adjusted_mode
->crtc_htotal
- 1) / 2;
7965 vsyncshift
= adjusted_mode
->crtc_hsync_start
-
7966 adjusted_mode
->crtc_htotal
/ 2;
7968 vsyncshift
+= adjusted_mode
->crtc_htotal
;
7971 if (INTEL_GEN(dev_priv
) > 3)
7972 I915_WRITE(VSYNCSHIFT(cpu_transcoder
), vsyncshift
);
7974 I915_WRITE(HTOTAL(cpu_transcoder
),
7975 (adjusted_mode
->crtc_hdisplay
- 1) |
7976 ((adjusted_mode
->crtc_htotal
- 1) << 16));
7977 I915_WRITE(HBLANK(cpu_transcoder
),
7978 (adjusted_mode
->crtc_hblank_start
- 1) |
7979 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
7980 I915_WRITE(HSYNC(cpu_transcoder
),
7981 (adjusted_mode
->crtc_hsync_start
- 1) |
7982 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
7984 I915_WRITE(VTOTAL(cpu_transcoder
),
7985 (adjusted_mode
->crtc_vdisplay
- 1) |
7986 ((crtc_vtotal
- 1) << 16));
7987 I915_WRITE(VBLANK(cpu_transcoder
),
7988 (adjusted_mode
->crtc_vblank_start
- 1) |
7989 ((crtc_vblank_end
- 1) << 16));
7990 I915_WRITE(VSYNC(cpu_transcoder
),
7991 (adjusted_mode
->crtc_vsync_start
- 1) |
7992 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
7994 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7995 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7996 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7998 if (IS_HASWELL(dev_priv
) && cpu_transcoder
== TRANSCODER_EDP
&&
7999 (pipe
== PIPE_B
|| pipe
== PIPE_C
))
8000 I915_WRITE(VTOTAL(pipe
), I915_READ(VTOTAL(cpu_transcoder
)));
8004 static void intel_set_pipe_src_size(const struct intel_crtc_state
*crtc_state
)
8006 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
8007 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
8008 enum pipe pipe
= crtc
->pipe
;
8010 /* pipesrc controls the size that is scaled from, which should
8011 * always be the user's requested size.
8013 I915_WRITE(PIPESRC(pipe
),
8014 ((crtc_state
->pipe_src_w
- 1) << 16) |
8015 (crtc_state
->pipe_src_h
- 1));
8018 static void intel_get_pipe_timings(struct intel_crtc
*crtc
,
8019 struct intel_crtc_state
*pipe_config
)
8021 struct drm_device
*dev
= crtc
->base
.dev
;
8022 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8023 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
8026 tmp
= I915_READ(HTOTAL(cpu_transcoder
));
8027 pipe_config
->base
.adjusted_mode
.crtc_hdisplay
= (tmp
& 0xffff) + 1;
8028 pipe_config
->base
.adjusted_mode
.crtc_htotal
= ((tmp
>> 16) & 0xffff) + 1;
8030 if (!transcoder_is_dsi(cpu_transcoder
)) {
8031 tmp
= I915_READ(HBLANK(cpu_transcoder
));
8032 pipe_config
->base
.adjusted_mode
.crtc_hblank_start
=
8034 pipe_config
->base
.adjusted_mode
.crtc_hblank_end
=
8035 ((tmp
>> 16) & 0xffff) + 1;
8037 tmp
= I915_READ(HSYNC(cpu_transcoder
));
8038 pipe_config
->base
.adjusted_mode
.crtc_hsync_start
= (tmp
& 0xffff) + 1;
8039 pipe_config
->base
.adjusted_mode
.crtc_hsync_end
= ((tmp
>> 16) & 0xffff) + 1;
8041 tmp
= I915_READ(VTOTAL(cpu_transcoder
));
8042 pipe_config
->base
.adjusted_mode
.crtc_vdisplay
= (tmp
& 0xffff) + 1;
8043 pipe_config
->base
.adjusted_mode
.crtc_vtotal
= ((tmp
>> 16) & 0xffff) + 1;
8045 if (!transcoder_is_dsi(cpu_transcoder
)) {
8046 tmp
= I915_READ(VBLANK(cpu_transcoder
));
8047 pipe_config
->base
.adjusted_mode
.crtc_vblank_start
=
8049 pipe_config
->base
.adjusted_mode
.crtc_vblank_end
=
8050 ((tmp
>> 16) & 0xffff) + 1;
8052 tmp
= I915_READ(VSYNC(cpu_transcoder
));
8053 pipe_config
->base
.adjusted_mode
.crtc_vsync_start
= (tmp
& 0xffff) + 1;
8054 pipe_config
->base
.adjusted_mode
.crtc_vsync_end
= ((tmp
>> 16) & 0xffff) + 1;
8056 if (I915_READ(PIPECONF(cpu_transcoder
)) & PIPECONF_INTERLACE_MASK
) {
8057 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_INTERLACE
;
8058 pipe_config
->base
.adjusted_mode
.crtc_vtotal
+= 1;
8059 pipe_config
->base
.adjusted_mode
.crtc_vblank_end
+= 1;
8063 static void intel_get_pipe_src_size(struct intel_crtc
*crtc
,
8064 struct intel_crtc_state
*pipe_config
)
8066 struct drm_device
*dev
= crtc
->base
.dev
;
8067 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8070 tmp
= I915_READ(PIPESRC(crtc
->pipe
));
8071 pipe_config
->pipe_src_h
= (tmp
& 0xffff) + 1;
8072 pipe_config
->pipe_src_w
= ((tmp
>> 16) & 0xffff) + 1;
8074 pipe_config
->base
.mode
.vdisplay
= pipe_config
->pipe_src_h
;
8075 pipe_config
->base
.mode
.hdisplay
= pipe_config
->pipe_src_w
;
8078 void intel_mode_from_pipe_config(struct drm_display_mode
*mode
,
8079 struct intel_crtc_state
*pipe_config
)
8081 mode
->hdisplay
= pipe_config
->base
.adjusted_mode
.crtc_hdisplay
;
8082 mode
->htotal
= pipe_config
->base
.adjusted_mode
.crtc_htotal
;
8083 mode
->hsync_start
= pipe_config
->base
.adjusted_mode
.crtc_hsync_start
;
8084 mode
->hsync_end
= pipe_config
->base
.adjusted_mode
.crtc_hsync_end
;
8086 mode
->vdisplay
= pipe_config
->base
.adjusted_mode
.crtc_vdisplay
;
8087 mode
->vtotal
= pipe_config
->base
.adjusted_mode
.crtc_vtotal
;
8088 mode
->vsync_start
= pipe_config
->base
.adjusted_mode
.crtc_vsync_start
;
8089 mode
->vsync_end
= pipe_config
->base
.adjusted_mode
.crtc_vsync_end
;
8091 mode
->flags
= pipe_config
->base
.adjusted_mode
.flags
;
8092 mode
->type
= DRM_MODE_TYPE_DRIVER
;
8094 mode
->clock
= pipe_config
->base
.adjusted_mode
.crtc_clock
;
8096 mode
->hsync
= drm_mode_hsync(mode
);
8097 mode
->vrefresh
= drm_mode_vrefresh(mode
);
8098 drm_mode_set_name(mode
);
8101 static void i9xx_set_pipeconf(const struct intel_crtc_state
*crtc_state
)
8103 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
8104 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
8109 /* we keep both pipes enabled on 830 */
8110 if (IS_I830(dev_priv
))
8111 pipeconf
|= I915_READ(PIPECONF(crtc
->pipe
)) & PIPECONF_ENABLE
;
8113 if (crtc_state
->double_wide
)
8114 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
8116 /* only g4x and later have fancy bpc/dither controls */
8117 if (IS_G4X(dev_priv
) || IS_VALLEYVIEW(dev_priv
) ||
8118 IS_CHERRYVIEW(dev_priv
)) {
8119 /* Bspec claims that we can't use dithering for 30bpp pipes. */
8120 if (crtc_state
->dither
&& crtc_state
->pipe_bpp
!= 30)
8121 pipeconf
|= PIPECONF_DITHER_EN
|
8122 PIPECONF_DITHER_TYPE_SP
;
8124 switch (crtc_state
->pipe_bpp
) {
8126 pipeconf
|= PIPECONF_6BPC
;
8129 pipeconf
|= PIPECONF_8BPC
;
8132 pipeconf
|= PIPECONF_10BPC
;
8135 /* Case prevented by intel_choose_pipe_bpp_dither. */
8140 if (crtc_state
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
) {
8141 if (INTEL_GEN(dev_priv
) < 4 ||
8142 intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_SDVO
))
8143 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
8145 pipeconf
|= PIPECONF_INTERLACE_W_SYNC_SHIFT
;
8147 pipeconf
|= PIPECONF_PROGRESSIVE
;
8150 if ((IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) &&
8151 crtc_state
->limited_color_range
)
8152 pipeconf
|= PIPECONF_COLOR_RANGE_SELECT
;
8154 pipeconf
|= PIPECONF_GAMMA_MODE(crtc_state
->gamma_mode
);
8156 I915_WRITE(PIPECONF(crtc
->pipe
), pipeconf
);
8157 POSTING_READ(PIPECONF(crtc
->pipe
));
8160 static int i8xx_crtc_compute_clock(struct intel_crtc
*crtc
,
8161 struct intel_crtc_state
*crtc_state
)
8163 struct drm_device
*dev
= crtc
->base
.dev
;
8164 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8165 const struct intel_limit
*limit
;
8168 memset(&crtc_state
->dpll_hw_state
, 0,
8169 sizeof(crtc_state
->dpll_hw_state
));
8171 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
8172 if (intel_panel_use_ssc(dev_priv
)) {
8173 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
8174 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
8177 limit
= &intel_limits_i8xx_lvds
;
8178 } else if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_DVO
)) {
8179 limit
= &intel_limits_i8xx_dvo
;
8181 limit
= &intel_limits_i8xx_dac
;
8184 if (!crtc_state
->clock_set
&&
8185 !i9xx_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
8186 refclk
, NULL
, &crtc_state
->dpll
)) {
8187 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8191 i8xx_compute_dpll(crtc
, crtc_state
, NULL
);
8196 static int g4x_crtc_compute_clock(struct intel_crtc
*crtc
,
8197 struct intel_crtc_state
*crtc_state
)
8199 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
8200 const struct intel_limit
*limit
;
8203 memset(&crtc_state
->dpll_hw_state
, 0,
8204 sizeof(crtc_state
->dpll_hw_state
));
8206 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
8207 if (intel_panel_use_ssc(dev_priv
)) {
8208 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
8209 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
8212 if (intel_is_dual_link_lvds(dev_priv
))
8213 limit
= &intel_limits_g4x_dual_channel_lvds
;
8215 limit
= &intel_limits_g4x_single_channel_lvds
;
8216 } else if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_HDMI
) ||
8217 intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_ANALOG
)) {
8218 limit
= &intel_limits_g4x_hdmi
;
8219 } else if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_SDVO
)) {
8220 limit
= &intel_limits_g4x_sdvo
;
8222 /* The option is for other outputs */
8223 limit
= &intel_limits_i9xx_sdvo
;
8226 if (!crtc_state
->clock_set
&&
8227 !g4x_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
8228 refclk
, NULL
, &crtc_state
->dpll
)) {
8229 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8233 i9xx_compute_dpll(crtc
, crtc_state
, NULL
);
8238 static int pnv_crtc_compute_clock(struct intel_crtc
*crtc
,
8239 struct intel_crtc_state
*crtc_state
)
8241 struct drm_device
*dev
= crtc
->base
.dev
;
8242 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8243 const struct intel_limit
*limit
;
8246 memset(&crtc_state
->dpll_hw_state
, 0,
8247 sizeof(crtc_state
->dpll_hw_state
));
8249 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
8250 if (intel_panel_use_ssc(dev_priv
)) {
8251 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
8252 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
8255 limit
= &intel_limits_pineview_lvds
;
8257 limit
= &intel_limits_pineview_sdvo
;
8260 if (!crtc_state
->clock_set
&&
8261 !pnv_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
8262 refclk
, NULL
, &crtc_state
->dpll
)) {
8263 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8267 i9xx_compute_dpll(crtc
, crtc_state
, NULL
);
8272 static int i9xx_crtc_compute_clock(struct intel_crtc
*crtc
,
8273 struct intel_crtc_state
*crtc_state
)
8275 struct drm_device
*dev
= crtc
->base
.dev
;
8276 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8277 const struct intel_limit
*limit
;
8280 memset(&crtc_state
->dpll_hw_state
, 0,
8281 sizeof(crtc_state
->dpll_hw_state
));
8283 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
8284 if (intel_panel_use_ssc(dev_priv
)) {
8285 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
8286 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
8289 limit
= &intel_limits_i9xx_lvds
;
8291 limit
= &intel_limits_i9xx_sdvo
;
8294 if (!crtc_state
->clock_set
&&
8295 !i9xx_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
8296 refclk
, NULL
, &crtc_state
->dpll
)) {
8297 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8301 i9xx_compute_dpll(crtc
, crtc_state
, NULL
);
8306 static int chv_crtc_compute_clock(struct intel_crtc
*crtc
,
8307 struct intel_crtc_state
*crtc_state
)
8309 int refclk
= 100000;
8310 const struct intel_limit
*limit
= &intel_limits_chv
;
8312 memset(&crtc_state
->dpll_hw_state
, 0,
8313 sizeof(crtc_state
->dpll_hw_state
));
8315 if (!crtc_state
->clock_set
&&
8316 !chv_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
8317 refclk
, NULL
, &crtc_state
->dpll
)) {
8318 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8322 chv_compute_dpll(crtc
, crtc_state
);
8327 static int vlv_crtc_compute_clock(struct intel_crtc
*crtc
,
8328 struct intel_crtc_state
*crtc_state
)
8330 int refclk
= 100000;
8331 const struct intel_limit
*limit
= &intel_limits_vlv
;
8333 memset(&crtc_state
->dpll_hw_state
, 0,
8334 sizeof(crtc_state
->dpll_hw_state
));
8336 if (!crtc_state
->clock_set
&&
8337 !vlv_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
8338 refclk
, NULL
, &crtc_state
->dpll
)) {
8339 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8343 vlv_compute_dpll(crtc
, crtc_state
);
8348 static bool i9xx_has_pfit(struct drm_i915_private
*dev_priv
)
8350 if (IS_I830(dev_priv
))
8353 return INTEL_GEN(dev_priv
) >= 4 ||
8354 IS_PINEVIEW(dev_priv
) || IS_MOBILE(dev_priv
);
8357 static void i9xx_get_pfit_config(struct intel_crtc
*crtc
,
8358 struct intel_crtc_state
*pipe_config
)
8360 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
8363 if (!i9xx_has_pfit(dev_priv
))
8366 tmp
= I915_READ(PFIT_CONTROL
);
8367 if (!(tmp
& PFIT_ENABLE
))
8370 /* Check whether the pfit is attached to our pipe. */
8371 if (INTEL_GEN(dev_priv
) < 4) {
8372 if (crtc
->pipe
!= PIPE_B
)
8375 if ((tmp
& PFIT_PIPE_MASK
) != (crtc
->pipe
<< PFIT_PIPE_SHIFT
))
8379 pipe_config
->gmch_pfit
.control
= tmp
;
8380 pipe_config
->gmch_pfit
.pgm_ratios
= I915_READ(PFIT_PGM_RATIOS
);
8383 static void vlv_crtc_clock_get(struct intel_crtc
*crtc
,
8384 struct intel_crtc_state
*pipe_config
)
8386 struct drm_device
*dev
= crtc
->base
.dev
;
8387 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8388 int pipe
= pipe_config
->cpu_transcoder
;
8391 int refclk
= 100000;
8393 /* In case of DSI, DPLL will not be used */
8394 if ((pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
) == 0)
8397 vlv_dpio_get(dev_priv
);
8398 mdiv
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW3(pipe
));
8399 vlv_dpio_put(dev_priv
);
8401 clock
.m1
= (mdiv
>> DPIO_M1DIV_SHIFT
) & 7;
8402 clock
.m2
= mdiv
& DPIO_M2DIV_MASK
;
8403 clock
.n
= (mdiv
>> DPIO_N_SHIFT
) & 0xf;
8404 clock
.p1
= (mdiv
>> DPIO_P1_SHIFT
) & 7;
8405 clock
.p2
= (mdiv
>> DPIO_P2_SHIFT
) & 0x1f;
8407 pipe_config
->port_clock
= vlv_calc_dpll_params(refclk
, &clock
);
8411 i9xx_get_initial_plane_config(struct intel_crtc
*crtc
,
8412 struct intel_initial_plane_config
*plane_config
)
8414 struct drm_device
*dev
= crtc
->base
.dev
;
8415 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8416 struct intel_plane
*plane
= to_intel_plane(crtc
->base
.primary
);
8417 enum i9xx_plane_id i9xx_plane
= plane
->i9xx_plane
;
8419 u32 val
, base
, offset
;
8420 int fourcc
, pixel_format
;
8421 unsigned int aligned_height
;
8422 struct drm_framebuffer
*fb
;
8423 struct intel_framebuffer
*intel_fb
;
8425 if (!plane
->get_hw_state(plane
, &pipe
))
8428 WARN_ON(pipe
!= crtc
->pipe
);
8430 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
8432 DRM_DEBUG_KMS("failed to alloc fb\n");
8436 fb
= &intel_fb
->base
;
8440 val
= I915_READ(DSPCNTR(i9xx_plane
));
8442 if (INTEL_GEN(dev_priv
) >= 4) {
8443 if (val
& DISPPLANE_TILED
) {
8444 plane_config
->tiling
= I915_TILING_X
;
8445 fb
->modifier
= I915_FORMAT_MOD_X_TILED
;
8448 if (val
& DISPPLANE_ROTATE_180
)
8449 plane_config
->rotation
= DRM_MODE_ROTATE_180
;
8452 if (IS_CHERRYVIEW(dev_priv
) && pipe
== PIPE_B
&&
8453 val
& DISPPLANE_MIRROR
)
8454 plane_config
->rotation
|= DRM_MODE_REFLECT_X
;
8456 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
8457 fourcc
= i9xx_format_to_fourcc(pixel_format
);
8458 fb
->format
= drm_format_info(fourcc
);
8460 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
8461 offset
= I915_READ(DSPOFFSET(i9xx_plane
));
8462 base
= I915_READ(DSPSURF(i9xx_plane
)) & 0xfffff000;
8463 } else if (INTEL_GEN(dev_priv
) >= 4) {
8464 if (plane_config
->tiling
)
8465 offset
= I915_READ(DSPTILEOFF(i9xx_plane
));
8467 offset
= I915_READ(DSPLINOFF(i9xx_plane
));
8468 base
= I915_READ(DSPSURF(i9xx_plane
)) & 0xfffff000;
8470 base
= I915_READ(DSPADDR(i9xx_plane
));
8472 plane_config
->base
= base
;
8474 val
= I915_READ(PIPESRC(pipe
));
8475 fb
->width
= ((val
>> 16) & 0xfff) + 1;
8476 fb
->height
= ((val
>> 0) & 0xfff) + 1;
8478 val
= I915_READ(DSPSTRIDE(i9xx_plane
));
8479 fb
->pitches
[0] = val
& 0xffffffc0;
8481 aligned_height
= intel_fb_align_height(fb
, 0, fb
->height
);
8483 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
8485 DRM_DEBUG_KMS("%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8486 crtc
->base
.name
, plane
->base
.name
, fb
->width
, fb
->height
,
8487 fb
->format
->cpp
[0] * 8, base
, fb
->pitches
[0],
8488 plane_config
->size
);
8490 plane_config
->fb
= intel_fb
;
8493 static void chv_crtc_clock_get(struct intel_crtc
*crtc
,
8494 struct intel_crtc_state
*pipe_config
)
8496 struct drm_device
*dev
= crtc
->base
.dev
;
8497 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8498 int pipe
= pipe_config
->cpu_transcoder
;
8499 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
8501 u32 cmn_dw13
, pll_dw0
, pll_dw1
, pll_dw2
, pll_dw3
;
8502 int refclk
= 100000;
8504 /* In case of DSI, DPLL will not be used */
8505 if ((pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
) == 0)
8508 vlv_dpio_get(dev_priv
);
8509 cmn_dw13
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW13(port
));
8510 pll_dw0
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW0(port
));
8511 pll_dw1
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW1(port
));
8512 pll_dw2
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW2(port
));
8513 pll_dw3
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW3(port
));
8514 vlv_dpio_put(dev_priv
);
8516 clock
.m1
= (pll_dw1
& 0x7) == DPIO_CHV_M1_DIV_BY_2
? 2 : 0;
8517 clock
.m2
= (pll_dw0
& 0xff) << 22;
8518 if (pll_dw3
& DPIO_CHV_FRAC_DIV_EN
)
8519 clock
.m2
|= pll_dw2
& 0x3fffff;
8520 clock
.n
= (pll_dw1
>> DPIO_CHV_N_DIV_SHIFT
) & 0xf;
8521 clock
.p1
= (cmn_dw13
>> DPIO_CHV_P1_DIV_SHIFT
) & 0x7;
8522 clock
.p2
= (cmn_dw13
>> DPIO_CHV_P2_DIV_SHIFT
) & 0x1f;
8524 pipe_config
->port_clock
= chv_calc_dpll_params(refclk
, &clock
);
8527 static void intel_get_crtc_ycbcr_config(struct intel_crtc
*crtc
,
8528 struct intel_crtc_state
*pipe_config
)
8530 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
8531 enum intel_output_format output
= INTEL_OUTPUT_FORMAT_RGB
;
8533 pipe_config
->lspcon_downsampling
= false;
8535 if (IS_BROADWELL(dev_priv
) || INTEL_GEN(dev_priv
) >= 9) {
8536 u32 tmp
= I915_READ(PIPEMISC(crtc
->pipe
));
8538 if (tmp
& PIPEMISC_OUTPUT_COLORSPACE_YUV
) {
8539 bool ycbcr420_enabled
= tmp
& PIPEMISC_YUV420_ENABLE
;
8540 bool blend
= tmp
& PIPEMISC_YUV420_MODE_FULL_BLEND
;
8542 if (ycbcr420_enabled
) {
8543 /* We support 4:2:0 in full blend mode only */
8545 output
= INTEL_OUTPUT_FORMAT_INVALID
;
8546 else if (!(IS_GEMINILAKE(dev_priv
) ||
8547 INTEL_GEN(dev_priv
) >= 10))
8548 output
= INTEL_OUTPUT_FORMAT_INVALID
;
8550 output
= INTEL_OUTPUT_FORMAT_YCBCR420
;
8553 * Currently there is no interface defined to
8554 * check user preference between RGB/YCBCR444
8555 * or YCBCR420. So the only possible case for
8556 * YCBCR444 usage is driving YCBCR420 output
8557 * with LSPCON, when pipe is configured for
8558 * YCBCR444 output and LSPCON takes care of
8561 pipe_config
->lspcon_downsampling
= true;
8562 output
= INTEL_OUTPUT_FORMAT_YCBCR444
;
8567 pipe_config
->output_format
= output
;
8570 static void i9xx_get_pipe_color_config(struct intel_crtc_state
*crtc_state
)
8572 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
8573 struct intel_plane
*plane
= to_intel_plane(crtc
->base
.primary
);
8574 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
8575 enum i9xx_plane_id i9xx_plane
= plane
->i9xx_plane
;
8578 tmp
= I915_READ(DSPCNTR(i9xx_plane
));
8580 if (tmp
& DISPPLANE_GAMMA_ENABLE
)
8581 crtc_state
->gamma_enable
= true;
8583 if (!HAS_GMCH(dev_priv
) &&
8584 tmp
& DISPPLANE_PIPE_CSC_ENABLE
)
8585 crtc_state
->csc_enable
= true;
8588 static bool i9xx_get_pipe_config(struct intel_crtc
*crtc
,
8589 struct intel_crtc_state
*pipe_config
)
8591 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
8592 enum intel_display_power_domain power_domain
;
8593 intel_wakeref_t wakeref
;
8597 power_domain
= POWER_DOMAIN_PIPE(crtc
->pipe
);
8598 wakeref
= intel_display_power_get_if_enabled(dev_priv
, power_domain
);
8602 pipe_config
->output_format
= INTEL_OUTPUT_FORMAT_RGB
;
8603 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
8604 pipe_config
->shared_dpll
= NULL
;
8608 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
8609 if (!(tmp
& PIPECONF_ENABLE
))
8612 if (IS_G4X(dev_priv
) || IS_VALLEYVIEW(dev_priv
) ||
8613 IS_CHERRYVIEW(dev_priv
)) {
8614 switch (tmp
& PIPECONF_BPC_MASK
) {
8616 pipe_config
->pipe_bpp
= 18;
8619 pipe_config
->pipe_bpp
= 24;
8621 case PIPECONF_10BPC
:
8622 pipe_config
->pipe_bpp
= 30;
8629 if ((IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) &&
8630 (tmp
& PIPECONF_COLOR_RANGE_SELECT
))
8631 pipe_config
->limited_color_range
= true;
8633 pipe_config
->gamma_mode
= (tmp
& PIPECONF_GAMMA_MODE_MASK_I9XX
) >>
8634 PIPECONF_GAMMA_MODE_SHIFT
;
8636 if (IS_CHERRYVIEW(dev_priv
))
8637 pipe_config
->cgm_mode
= I915_READ(CGM_PIPE_MODE(crtc
->pipe
));
8639 i9xx_get_pipe_color_config(pipe_config
);
8641 if (INTEL_GEN(dev_priv
) < 4)
8642 pipe_config
->double_wide
= tmp
& PIPECONF_DOUBLE_WIDE
;
8644 intel_get_pipe_timings(crtc
, pipe_config
);
8645 intel_get_pipe_src_size(crtc
, pipe_config
);
8647 i9xx_get_pfit_config(crtc
, pipe_config
);
8649 if (INTEL_GEN(dev_priv
) >= 4) {
8650 /* No way to read it out on pipes B and C */
8651 if (IS_CHERRYVIEW(dev_priv
) && crtc
->pipe
!= PIPE_A
)
8652 tmp
= dev_priv
->chv_dpll_md
[crtc
->pipe
];
8654 tmp
= I915_READ(DPLL_MD(crtc
->pipe
));
8655 pipe_config
->pixel_multiplier
=
8656 ((tmp
& DPLL_MD_UDI_MULTIPLIER_MASK
)
8657 >> DPLL_MD_UDI_MULTIPLIER_SHIFT
) + 1;
8658 pipe_config
->dpll_hw_state
.dpll_md
= tmp
;
8659 } else if (IS_I945G(dev_priv
) || IS_I945GM(dev_priv
) ||
8660 IS_G33(dev_priv
) || IS_PINEVIEW(dev_priv
)) {
8661 tmp
= I915_READ(DPLL(crtc
->pipe
));
8662 pipe_config
->pixel_multiplier
=
8663 ((tmp
& SDVO_MULTIPLIER_MASK
)
8664 >> SDVO_MULTIPLIER_SHIFT_HIRES
) + 1;
8666 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8667 * port and will be fixed up in the encoder->get_config
8669 pipe_config
->pixel_multiplier
= 1;
8671 pipe_config
->dpll_hw_state
.dpll
= I915_READ(DPLL(crtc
->pipe
));
8672 if (!IS_VALLEYVIEW(dev_priv
) && !IS_CHERRYVIEW(dev_priv
)) {
8673 pipe_config
->dpll_hw_state
.fp0
= I915_READ(FP0(crtc
->pipe
));
8674 pipe_config
->dpll_hw_state
.fp1
= I915_READ(FP1(crtc
->pipe
));
8676 /* Mask out read-only status bits. */
8677 pipe_config
->dpll_hw_state
.dpll
&= ~(DPLL_LOCK_VLV
|
8678 DPLL_PORTC_READY_MASK
|
8679 DPLL_PORTB_READY_MASK
);
8682 if (IS_CHERRYVIEW(dev_priv
))
8683 chv_crtc_clock_get(crtc
, pipe_config
);
8684 else if (IS_VALLEYVIEW(dev_priv
))
8685 vlv_crtc_clock_get(crtc
, pipe_config
);
8687 i9xx_crtc_clock_get(crtc
, pipe_config
);
8690 * Normally the dotclock is filled in by the encoder .get_config()
8691 * but in case the pipe is enabled w/o any ports we need a sane
8694 pipe_config
->base
.adjusted_mode
.crtc_clock
=
8695 pipe_config
->port_clock
/ pipe_config
->pixel_multiplier
;
8700 intel_display_power_put(dev_priv
, power_domain
, wakeref
);
8705 static void ironlake_init_pch_refclk(struct drm_i915_private
*dev_priv
)
8707 struct intel_encoder
*encoder
;
8710 bool has_lvds
= false;
8711 bool has_cpu_edp
= false;
8712 bool has_panel
= false;
8713 bool has_ck505
= false;
8714 bool can_ssc
= false;
8715 bool using_ssc_source
= false;
8717 /* We need to take the global config into account */
8718 for_each_intel_encoder(&dev_priv
->drm
, encoder
) {
8719 switch (encoder
->type
) {
8720 case INTEL_OUTPUT_LVDS
:
8724 case INTEL_OUTPUT_EDP
:
8726 if (encoder
->port
== PORT_A
)
8734 if (HAS_PCH_IBX(dev_priv
)) {
8735 has_ck505
= dev_priv
->vbt
.display_clock_mode
;
8736 can_ssc
= has_ck505
;
8742 /* Check if any DPLLs are using the SSC source */
8743 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
8744 u32 temp
= I915_READ(PCH_DPLL(i
));
8746 if (!(temp
& DPLL_VCO_ENABLE
))
8749 if ((temp
& PLL_REF_INPUT_MASK
) ==
8750 PLLB_REF_INPUT_SPREADSPECTRUMIN
) {
8751 using_ssc_source
= true;
8756 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
8757 has_panel
, has_lvds
, has_ck505
, using_ssc_source
);
8759 /* Ironlake: try to setup display ref clock before DPLL
8760 * enabling. This is only under driver's control after
8761 * PCH B stepping, previous chipset stepping should be
8762 * ignoring this setting.
8764 val
= I915_READ(PCH_DREF_CONTROL
);
8766 /* As we must carefully and slowly disable/enable each source in turn,
8767 * compute the final state we want first and check if we need to
8768 * make any changes at all.
8771 final
&= ~DREF_NONSPREAD_SOURCE_MASK
;
8773 final
|= DREF_NONSPREAD_CK505_ENABLE
;
8775 final
|= DREF_NONSPREAD_SOURCE_ENABLE
;
8777 final
&= ~DREF_SSC_SOURCE_MASK
;
8778 final
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
8779 final
&= ~DREF_SSC1_ENABLE
;
8782 final
|= DREF_SSC_SOURCE_ENABLE
;
8784 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
8785 final
|= DREF_SSC1_ENABLE
;
8788 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
8789 final
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
8791 final
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
8793 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
8794 } else if (using_ssc_source
) {
8795 final
|= DREF_SSC_SOURCE_ENABLE
;
8796 final
|= DREF_SSC1_ENABLE
;
8802 /* Always enable nonspread source */
8803 val
&= ~DREF_NONSPREAD_SOURCE_MASK
;
8806 val
|= DREF_NONSPREAD_CK505_ENABLE
;
8808 val
|= DREF_NONSPREAD_SOURCE_ENABLE
;
8811 val
&= ~DREF_SSC_SOURCE_MASK
;
8812 val
|= DREF_SSC_SOURCE_ENABLE
;
8814 /* SSC must be turned on before enabling the CPU output */
8815 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
8816 DRM_DEBUG_KMS("Using SSC on panel\n");
8817 val
|= DREF_SSC1_ENABLE
;
8819 val
&= ~DREF_SSC1_ENABLE
;
8821 /* Get SSC going before enabling the outputs */
8822 I915_WRITE(PCH_DREF_CONTROL
, val
);
8823 POSTING_READ(PCH_DREF_CONTROL
);
8826 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
8828 /* Enable CPU source on CPU attached eDP */
8830 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
8831 DRM_DEBUG_KMS("Using SSC on eDP\n");
8832 val
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
8834 val
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
8836 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
8838 I915_WRITE(PCH_DREF_CONTROL
, val
);
8839 POSTING_READ(PCH_DREF_CONTROL
);
8842 DRM_DEBUG_KMS("Disabling CPU source output\n");
8844 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
8846 /* Turn off CPU output */
8847 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
8849 I915_WRITE(PCH_DREF_CONTROL
, val
);
8850 POSTING_READ(PCH_DREF_CONTROL
);
8853 if (!using_ssc_source
) {
8854 DRM_DEBUG_KMS("Disabling SSC source\n");
8856 /* Turn off the SSC source */
8857 val
&= ~DREF_SSC_SOURCE_MASK
;
8858 val
|= DREF_SSC_SOURCE_DISABLE
;
8861 val
&= ~DREF_SSC1_ENABLE
;
8863 I915_WRITE(PCH_DREF_CONTROL
, val
);
8864 POSTING_READ(PCH_DREF_CONTROL
);
8869 BUG_ON(val
!= final
);
8872 static void lpt_reset_fdi_mphy(struct drm_i915_private
*dev_priv
)
8876 tmp
= I915_READ(SOUTH_CHICKEN2
);
8877 tmp
|= FDI_MPHY_IOSFSB_RESET_CTL
;
8878 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
8880 if (wait_for_us(I915_READ(SOUTH_CHICKEN2
) &
8881 FDI_MPHY_IOSFSB_RESET_STATUS
, 100))
8882 DRM_ERROR("FDI mPHY reset assert timeout\n");
8884 tmp
= I915_READ(SOUTH_CHICKEN2
);
8885 tmp
&= ~FDI_MPHY_IOSFSB_RESET_CTL
;
8886 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
8888 if (wait_for_us((I915_READ(SOUTH_CHICKEN2
) &
8889 FDI_MPHY_IOSFSB_RESET_STATUS
) == 0, 100))
8890 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8893 /* WaMPhyProgramming:hsw */
8894 static void lpt_program_fdi_mphy(struct drm_i915_private
*dev_priv
)
8898 tmp
= intel_sbi_read(dev_priv
, 0x8008, SBI_MPHY
);
8899 tmp
&= ~(0xFF << 24);
8900 tmp
|= (0x12 << 24);
8901 intel_sbi_write(dev_priv
, 0x8008, tmp
, SBI_MPHY
);
8903 tmp
= intel_sbi_read(dev_priv
, 0x2008, SBI_MPHY
);
8905 intel_sbi_write(dev_priv
, 0x2008, tmp
, SBI_MPHY
);
8907 tmp
= intel_sbi_read(dev_priv
, 0x2108, SBI_MPHY
);
8909 intel_sbi_write(dev_priv
, 0x2108, tmp
, SBI_MPHY
);
8911 tmp
= intel_sbi_read(dev_priv
, 0x206C, SBI_MPHY
);
8912 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
8913 intel_sbi_write(dev_priv
, 0x206C, tmp
, SBI_MPHY
);
8915 tmp
= intel_sbi_read(dev_priv
, 0x216C, SBI_MPHY
);
8916 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
8917 intel_sbi_write(dev_priv
, 0x216C, tmp
, SBI_MPHY
);
8919 tmp
= intel_sbi_read(dev_priv
, 0x2080, SBI_MPHY
);
8922 intel_sbi_write(dev_priv
, 0x2080, tmp
, SBI_MPHY
);
8924 tmp
= intel_sbi_read(dev_priv
, 0x2180, SBI_MPHY
);
8927 intel_sbi_write(dev_priv
, 0x2180, tmp
, SBI_MPHY
);
8929 tmp
= intel_sbi_read(dev_priv
, 0x208C, SBI_MPHY
);
8932 intel_sbi_write(dev_priv
, 0x208C, tmp
, SBI_MPHY
);
8934 tmp
= intel_sbi_read(dev_priv
, 0x218C, SBI_MPHY
);
8937 intel_sbi_write(dev_priv
, 0x218C, tmp
, SBI_MPHY
);
8939 tmp
= intel_sbi_read(dev_priv
, 0x2098, SBI_MPHY
);
8940 tmp
&= ~(0xFF << 16);
8941 tmp
|= (0x1C << 16);
8942 intel_sbi_write(dev_priv
, 0x2098, tmp
, SBI_MPHY
);
8944 tmp
= intel_sbi_read(dev_priv
, 0x2198, SBI_MPHY
);
8945 tmp
&= ~(0xFF << 16);
8946 tmp
|= (0x1C << 16);
8947 intel_sbi_write(dev_priv
, 0x2198, tmp
, SBI_MPHY
);
8949 tmp
= intel_sbi_read(dev_priv
, 0x20C4, SBI_MPHY
);
8951 intel_sbi_write(dev_priv
, 0x20C4, tmp
, SBI_MPHY
);
8953 tmp
= intel_sbi_read(dev_priv
, 0x21C4, SBI_MPHY
);
8955 intel_sbi_write(dev_priv
, 0x21C4, tmp
, SBI_MPHY
);
8957 tmp
= intel_sbi_read(dev_priv
, 0x20EC, SBI_MPHY
);
8958 tmp
&= ~(0xF << 28);
8960 intel_sbi_write(dev_priv
, 0x20EC, tmp
, SBI_MPHY
);
8962 tmp
= intel_sbi_read(dev_priv
, 0x21EC, SBI_MPHY
);
8963 tmp
&= ~(0xF << 28);
8965 intel_sbi_write(dev_priv
, 0x21EC, tmp
, SBI_MPHY
);
8968 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8969 * Programming" based on the parameters passed:
8970 * - Sequence to enable CLKOUT_DP
8971 * - Sequence to enable CLKOUT_DP without spread
8972 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8974 static void lpt_enable_clkout_dp(struct drm_i915_private
*dev_priv
,
8975 bool with_spread
, bool with_fdi
)
8979 if (WARN(with_fdi
&& !with_spread
, "FDI requires downspread\n"))
8981 if (WARN(HAS_PCH_LPT_LP(dev_priv
) &&
8982 with_fdi
, "LP PCH doesn't have FDI\n"))
8985 mutex_lock(&dev_priv
->sb_lock
);
8987 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
8988 tmp
&= ~SBI_SSCCTL_DISABLE
;
8989 tmp
|= SBI_SSCCTL_PATHALT
;
8990 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
8995 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
8996 tmp
&= ~SBI_SSCCTL_PATHALT
;
8997 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
9000 lpt_reset_fdi_mphy(dev_priv
);
9001 lpt_program_fdi_mphy(dev_priv
);
9005 reg
= HAS_PCH_LPT_LP(dev_priv
) ? SBI_GEN0
: SBI_DBUFF0
;
9006 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
9007 tmp
|= SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
9008 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
9010 mutex_unlock(&dev_priv
->sb_lock
);
9013 /* Sequence to disable CLKOUT_DP */
9014 void lpt_disable_clkout_dp(struct drm_i915_private
*dev_priv
)
9018 mutex_lock(&dev_priv
->sb_lock
);
9020 reg
= HAS_PCH_LPT_LP(dev_priv
) ? SBI_GEN0
: SBI_DBUFF0
;
9021 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
9022 tmp
&= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
9023 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
9025 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
9026 if (!(tmp
& SBI_SSCCTL_DISABLE
)) {
9027 if (!(tmp
& SBI_SSCCTL_PATHALT
)) {
9028 tmp
|= SBI_SSCCTL_PATHALT
;
9029 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
9032 tmp
|= SBI_SSCCTL_DISABLE
;
9033 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
9036 mutex_unlock(&dev_priv
->sb_lock
);
9039 #define BEND_IDX(steps) ((50 + (steps)) / 5)
9041 static const u16 sscdivintphase
[] = {
9042 [BEND_IDX( 50)] = 0x3B23,
9043 [BEND_IDX( 45)] = 0x3B23,
9044 [BEND_IDX( 40)] = 0x3C23,
9045 [BEND_IDX( 35)] = 0x3C23,
9046 [BEND_IDX( 30)] = 0x3D23,
9047 [BEND_IDX( 25)] = 0x3D23,
9048 [BEND_IDX( 20)] = 0x3E23,
9049 [BEND_IDX( 15)] = 0x3E23,
9050 [BEND_IDX( 10)] = 0x3F23,
9051 [BEND_IDX( 5)] = 0x3F23,
9052 [BEND_IDX( 0)] = 0x0025,
9053 [BEND_IDX( -5)] = 0x0025,
9054 [BEND_IDX(-10)] = 0x0125,
9055 [BEND_IDX(-15)] = 0x0125,
9056 [BEND_IDX(-20)] = 0x0225,
9057 [BEND_IDX(-25)] = 0x0225,
9058 [BEND_IDX(-30)] = 0x0325,
9059 [BEND_IDX(-35)] = 0x0325,
9060 [BEND_IDX(-40)] = 0x0425,
9061 [BEND_IDX(-45)] = 0x0425,
9062 [BEND_IDX(-50)] = 0x0525,
9067 * steps -50 to 50 inclusive, in steps of 5
9068 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
9069 * change in clock period = -(steps / 10) * 5.787 ps
9071 static void lpt_bend_clkout_dp(struct drm_i915_private
*dev_priv
, int steps
)
9074 int idx
= BEND_IDX(steps
);
9076 if (WARN_ON(steps
% 5 != 0))
9079 if (WARN_ON(idx
>= ARRAY_SIZE(sscdivintphase
)))
9082 mutex_lock(&dev_priv
->sb_lock
);
9084 if (steps
% 10 != 0)
9088 intel_sbi_write(dev_priv
, SBI_SSCDITHPHASE
, tmp
, SBI_ICLK
);
9090 tmp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE
, SBI_ICLK
);
9092 tmp
|= sscdivintphase
[idx
];
9093 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE
, tmp
, SBI_ICLK
);
9095 mutex_unlock(&dev_priv
->sb_lock
);
9100 static void lpt_init_pch_refclk(struct drm_i915_private
*dev_priv
)
9102 struct intel_encoder
*encoder
;
9103 bool has_vga
= false;
9105 for_each_intel_encoder(&dev_priv
->drm
, encoder
) {
9106 switch (encoder
->type
) {
9107 case INTEL_OUTPUT_ANALOG
:
9116 lpt_bend_clkout_dp(dev_priv
, 0);
9117 lpt_enable_clkout_dp(dev_priv
, true, true);
9119 lpt_disable_clkout_dp(dev_priv
);
9124 * Initialize reference clocks when the driver loads
9126 void intel_init_pch_refclk(struct drm_i915_private
*dev_priv
)
9128 if (HAS_PCH_IBX(dev_priv
) || HAS_PCH_CPT(dev_priv
))
9129 ironlake_init_pch_refclk(dev_priv
);
9130 else if (HAS_PCH_LPT(dev_priv
))
9131 lpt_init_pch_refclk(dev_priv
);
9134 static void ironlake_set_pipeconf(const struct intel_crtc_state
*crtc_state
)
9136 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
9137 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
9138 enum pipe pipe
= crtc
->pipe
;
9143 switch (crtc_state
->pipe_bpp
) {
9145 val
|= PIPECONF_6BPC
;
9148 val
|= PIPECONF_8BPC
;
9151 val
|= PIPECONF_10BPC
;
9154 val
|= PIPECONF_12BPC
;
9157 /* Case prevented by intel_choose_pipe_bpp_dither. */
9161 if (crtc_state
->dither
)
9162 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
9164 if (crtc_state
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
9165 val
|= PIPECONF_INTERLACED_ILK
;
9167 val
|= PIPECONF_PROGRESSIVE
;
9169 if (crtc_state
->limited_color_range
)
9170 val
|= PIPECONF_COLOR_RANGE_SELECT
;
9172 val
|= PIPECONF_GAMMA_MODE(crtc_state
->gamma_mode
);
9174 I915_WRITE(PIPECONF(pipe
), val
);
9175 POSTING_READ(PIPECONF(pipe
));
9178 static void haswell_set_pipeconf(const struct intel_crtc_state
*crtc_state
)
9180 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
9181 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
9182 enum transcoder cpu_transcoder
= crtc_state
->cpu_transcoder
;
9185 if (IS_HASWELL(dev_priv
) && crtc_state
->dither
)
9186 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
9188 if (crtc_state
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
9189 val
|= PIPECONF_INTERLACED_ILK
;
9191 val
|= PIPECONF_PROGRESSIVE
;
9193 I915_WRITE(PIPECONF(cpu_transcoder
), val
);
9194 POSTING_READ(PIPECONF(cpu_transcoder
));
9197 static void bdw_set_pipemisc(const struct intel_crtc_state
*crtc_state
)
9199 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
9200 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
9203 switch (crtc_state
->pipe_bpp
) {
9205 val
|= PIPEMISC_DITHER_6_BPC
;
9208 val
|= PIPEMISC_DITHER_8_BPC
;
9211 val
|= PIPEMISC_DITHER_10_BPC
;
9214 val
|= PIPEMISC_DITHER_12_BPC
;
9217 MISSING_CASE(crtc_state
->pipe_bpp
);
9221 if (crtc_state
->dither
)
9222 val
|= PIPEMISC_DITHER_ENABLE
| PIPEMISC_DITHER_TYPE_SP
;
9224 if (crtc_state
->output_format
== INTEL_OUTPUT_FORMAT_YCBCR420
||
9225 crtc_state
->output_format
== INTEL_OUTPUT_FORMAT_YCBCR444
)
9226 val
|= PIPEMISC_OUTPUT_COLORSPACE_YUV
;
9228 if (crtc_state
->output_format
== INTEL_OUTPUT_FORMAT_YCBCR420
)
9229 val
|= PIPEMISC_YUV420_ENABLE
|
9230 PIPEMISC_YUV420_MODE_FULL_BLEND
;
9232 if (INTEL_GEN(dev_priv
) >= 11 &&
9233 (crtc_state
->active_planes
& ~(icl_hdr_plane_mask() |
9234 BIT(PLANE_CURSOR
))) == 0)
9235 val
|= PIPEMISC_HDR_MODE_PRECISION
;
9237 I915_WRITE(PIPEMISC(crtc
->pipe
), val
);
9240 int bdw_get_pipemisc_bpp(struct intel_crtc
*crtc
)
9242 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
9245 tmp
= I915_READ(PIPEMISC(crtc
->pipe
));
9247 switch (tmp
& PIPEMISC_DITHER_BPC_MASK
) {
9248 case PIPEMISC_DITHER_6_BPC
:
9250 case PIPEMISC_DITHER_8_BPC
:
9252 case PIPEMISC_DITHER_10_BPC
:
9254 case PIPEMISC_DITHER_12_BPC
:
9262 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
)
9265 * Account for spread spectrum to avoid
9266 * oversubscribing the link. Max center spread
9267 * is 2.5%; use 5% for safety's sake.
9269 u32 bps
= target_clock
* bpp
* 21 / 20;
9270 return DIV_ROUND_UP(bps
, link_bw
* 8);
9273 static bool ironlake_needs_fb_cb_tune(struct dpll
*dpll
, int factor
)
9275 return i9xx_dpll_compute_m(dpll
) < factor
* dpll
->n
;
9278 static void ironlake_compute_dpll(struct intel_crtc
*crtc
,
9279 struct intel_crtc_state
*crtc_state
,
9280 struct dpll
*reduced_clock
)
9282 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
9286 /* Enable autotuning of the PLL clock (if permissible) */
9288 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
9289 if ((intel_panel_use_ssc(dev_priv
) &&
9290 dev_priv
->vbt
.lvds_ssc_freq
== 100000) ||
9291 (HAS_PCH_IBX(dev_priv
) &&
9292 intel_is_dual_link_lvds(dev_priv
)))
9294 } else if (crtc_state
->sdvo_tv_clock
) {
9298 fp
= i9xx_dpll_compute_fp(&crtc_state
->dpll
);
9300 if (ironlake_needs_fb_cb_tune(&crtc_state
->dpll
, factor
))
9303 if (reduced_clock
) {
9304 fp2
= i9xx_dpll_compute_fp(reduced_clock
);
9306 if (reduced_clock
->m
< factor
* reduced_clock
->n
)
9314 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
))
9315 dpll
|= DPLLB_MODE_LVDS
;
9317 dpll
|= DPLLB_MODE_DAC_SERIAL
;
9319 dpll
|= (crtc_state
->pixel_multiplier
- 1)
9320 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
9322 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_SDVO
) ||
9323 intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_HDMI
))
9324 dpll
|= DPLL_SDVO_HIGH_SPEED
;
9326 if (intel_crtc_has_dp_encoder(crtc_state
))
9327 dpll
|= DPLL_SDVO_HIGH_SPEED
;
9330 * The high speed IO clock is only really required for
9331 * SDVO/HDMI/DP, but we also enable it for CRT to make it
9332 * possible to share the DPLL between CRT and HDMI. Enabling
9333 * the clock needlessly does no real harm, except use up a
9334 * bit of power potentially.
9336 * We'll limit this to IVB with 3 pipes, since it has only two
9337 * DPLLs and so DPLL sharing is the only way to get three pipes
9338 * driving PCH ports at the same time. On SNB we could do this,
9339 * and potentially avoid enabling the second DPLL, but it's not
9340 * clear if it''s a win or loss power wise. No point in doing
9341 * this on ILK at all since it has a fixed DPLL<->pipe mapping.
9343 if (INTEL_INFO(dev_priv
)->num_pipes
== 3 &&
9344 intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_ANALOG
))
9345 dpll
|= DPLL_SDVO_HIGH_SPEED
;
9347 /* compute bitmask from p1 value */
9348 dpll
|= (1 << (crtc_state
->dpll
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
9350 dpll
|= (1 << (crtc_state
->dpll
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
9352 switch (crtc_state
->dpll
.p2
) {
9354 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
9357 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
9360 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
9363 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
9367 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
9368 intel_panel_use_ssc(dev_priv
))
9369 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
9371 dpll
|= PLL_REF_INPUT_DREFCLK
;
9373 dpll
|= DPLL_VCO_ENABLE
;
9375 crtc_state
->dpll_hw_state
.dpll
= dpll
;
9376 crtc_state
->dpll_hw_state
.fp0
= fp
;
9377 crtc_state
->dpll_hw_state
.fp1
= fp2
;
9380 static int ironlake_crtc_compute_clock(struct intel_crtc
*crtc
,
9381 struct intel_crtc_state
*crtc_state
)
9383 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
9384 const struct intel_limit
*limit
;
9385 int refclk
= 120000;
9387 memset(&crtc_state
->dpll_hw_state
, 0,
9388 sizeof(crtc_state
->dpll_hw_state
));
9390 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
9391 if (!crtc_state
->has_pch_encoder
)
9394 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
9395 if (intel_panel_use_ssc(dev_priv
)) {
9396 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
9397 dev_priv
->vbt
.lvds_ssc_freq
);
9398 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
9401 if (intel_is_dual_link_lvds(dev_priv
)) {
9402 if (refclk
== 100000)
9403 limit
= &intel_limits_ironlake_dual_lvds_100m
;
9405 limit
= &intel_limits_ironlake_dual_lvds
;
9407 if (refclk
== 100000)
9408 limit
= &intel_limits_ironlake_single_lvds_100m
;
9410 limit
= &intel_limits_ironlake_single_lvds
;
9413 limit
= &intel_limits_ironlake_dac
;
9416 if (!crtc_state
->clock_set
&&
9417 !g4x_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
9418 refclk
, NULL
, &crtc_state
->dpll
)) {
9419 DRM_ERROR("Couldn't find PLL settings for mode!\n");
9423 ironlake_compute_dpll(crtc
, crtc_state
, NULL
);
9425 if (!intel_get_shared_dpll(crtc_state
, NULL
)) {
9426 DRM_DEBUG_KMS("failed to find PLL for pipe %c\n",
9427 pipe_name(crtc
->pipe
));
9434 static void intel_pch_transcoder_get_m_n(struct intel_crtc
*crtc
,
9435 struct intel_link_m_n
*m_n
)
9437 struct drm_device
*dev
= crtc
->base
.dev
;
9438 struct drm_i915_private
*dev_priv
= to_i915(dev
);
9439 enum pipe pipe
= crtc
->pipe
;
9441 m_n
->link_m
= I915_READ(PCH_TRANS_LINK_M1(pipe
));
9442 m_n
->link_n
= I915_READ(PCH_TRANS_LINK_N1(pipe
));
9443 m_n
->gmch_m
= I915_READ(PCH_TRANS_DATA_M1(pipe
))
9445 m_n
->gmch_n
= I915_READ(PCH_TRANS_DATA_N1(pipe
));
9446 m_n
->tu
= ((I915_READ(PCH_TRANS_DATA_M1(pipe
))
9447 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
9450 static void intel_cpu_transcoder_get_m_n(struct intel_crtc
*crtc
,
9451 enum transcoder transcoder
,
9452 struct intel_link_m_n
*m_n
,
9453 struct intel_link_m_n
*m2_n2
)
9455 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
9456 enum pipe pipe
= crtc
->pipe
;
9458 if (INTEL_GEN(dev_priv
) >= 5) {
9459 m_n
->link_m
= I915_READ(PIPE_LINK_M1(transcoder
));
9460 m_n
->link_n
= I915_READ(PIPE_LINK_N1(transcoder
));
9461 m_n
->gmch_m
= I915_READ(PIPE_DATA_M1(transcoder
))
9463 m_n
->gmch_n
= I915_READ(PIPE_DATA_N1(transcoder
));
9464 m_n
->tu
= ((I915_READ(PIPE_DATA_M1(transcoder
))
9465 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
9467 if (m2_n2
&& transcoder_has_m2_n2(dev_priv
, transcoder
)) {
9468 m2_n2
->link_m
= I915_READ(PIPE_LINK_M2(transcoder
));
9469 m2_n2
->link_n
= I915_READ(PIPE_LINK_N2(transcoder
));
9470 m2_n2
->gmch_m
= I915_READ(PIPE_DATA_M2(transcoder
))
9472 m2_n2
->gmch_n
= I915_READ(PIPE_DATA_N2(transcoder
));
9473 m2_n2
->tu
= ((I915_READ(PIPE_DATA_M2(transcoder
))
9474 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
9477 m_n
->link_m
= I915_READ(PIPE_LINK_M_G4X(pipe
));
9478 m_n
->link_n
= I915_READ(PIPE_LINK_N_G4X(pipe
));
9479 m_n
->gmch_m
= I915_READ(PIPE_DATA_M_G4X(pipe
))
9481 m_n
->gmch_n
= I915_READ(PIPE_DATA_N_G4X(pipe
));
9482 m_n
->tu
= ((I915_READ(PIPE_DATA_M_G4X(pipe
))
9483 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
9487 void intel_dp_get_m_n(struct intel_crtc
*crtc
,
9488 struct intel_crtc_state
*pipe_config
)
9490 if (pipe_config
->has_pch_encoder
)
9491 intel_pch_transcoder_get_m_n(crtc
, &pipe_config
->dp_m_n
);
9493 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
9494 &pipe_config
->dp_m_n
,
9495 &pipe_config
->dp_m2_n2
);
9498 static void ironlake_get_fdi_m_n_config(struct intel_crtc
*crtc
,
9499 struct intel_crtc_state
*pipe_config
)
9501 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
9502 &pipe_config
->fdi_m_n
, NULL
);
9505 static void skylake_get_pfit_config(struct intel_crtc
*crtc
,
9506 struct intel_crtc_state
*pipe_config
)
9508 struct drm_device
*dev
= crtc
->base
.dev
;
9509 struct drm_i915_private
*dev_priv
= to_i915(dev
);
9510 struct intel_crtc_scaler_state
*scaler_state
= &pipe_config
->scaler_state
;
9515 /* find scaler attached to this pipe */
9516 for (i
= 0; i
< crtc
->num_scalers
; i
++) {
9517 ps_ctrl
= I915_READ(SKL_PS_CTRL(crtc
->pipe
, i
));
9518 if (ps_ctrl
& PS_SCALER_EN
&& !(ps_ctrl
& PS_PLANE_SEL_MASK
)) {
9520 pipe_config
->pch_pfit
.enabled
= true;
9521 pipe_config
->pch_pfit
.pos
= I915_READ(SKL_PS_WIN_POS(crtc
->pipe
, i
));
9522 pipe_config
->pch_pfit
.size
= I915_READ(SKL_PS_WIN_SZ(crtc
->pipe
, i
));
9523 scaler_state
->scalers
[i
].in_use
= true;
9528 scaler_state
->scaler_id
= id
;
9530 scaler_state
->scaler_users
|= (1 << SKL_CRTC_INDEX
);
9532 scaler_state
->scaler_users
&= ~(1 << SKL_CRTC_INDEX
);
9537 skylake_get_initial_plane_config(struct intel_crtc
*crtc
,
9538 struct intel_initial_plane_config
*plane_config
)
9540 struct drm_device
*dev
= crtc
->base
.dev
;
9541 struct drm_i915_private
*dev_priv
= to_i915(dev
);
9542 struct intel_plane
*plane
= to_intel_plane(crtc
->base
.primary
);
9543 enum plane_id plane_id
= plane
->id
;
9545 u32 val
, base
, offset
, stride_mult
, tiling
, alpha
;
9546 int fourcc
, pixel_format
;
9547 unsigned int aligned_height
;
9548 struct drm_framebuffer
*fb
;
9549 struct intel_framebuffer
*intel_fb
;
9551 if (!plane
->get_hw_state(plane
, &pipe
))
9554 WARN_ON(pipe
!= crtc
->pipe
);
9556 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
9558 DRM_DEBUG_KMS("failed to alloc fb\n");
9562 fb
= &intel_fb
->base
;
9566 val
= I915_READ(PLANE_CTL(pipe
, plane_id
));
9568 if (INTEL_GEN(dev_priv
) >= 11)
9569 pixel_format
= val
& ICL_PLANE_CTL_FORMAT_MASK
;
9571 pixel_format
= val
& PLANE_CTL_FORMAT_MASK
;
9573 if (INTEL_GEN(dev_priv
) >= 10 || IS_GEMINILAKE(dev_priv
)) {
9574 alpha
= I915_READ(PLANE_COLOR_CTL(pipe
, plane_id
));
9575 alpha
&= PLANE_COLOR_ALPHA_MASK
;
9577 alpha
= val
& PLANE_CTL_ALPHA_MASK
;
9580 fourcc
= skl_format_to_fourcc(pixel_format
,
9581 val
& PLANE_CTL_ORDER_RGBX
, alpha
);
9582 fb
->format
= drm_format_info(fourcc
);
9584 tiling
= val
& PLANE_CTL_TILED_MASK
;
9586 case PLANE_CTL_TILED_LINEAR
:
9587 fb
->modifier
= DRM_FORMAT_MOD_LINEAR
;
9589 case PLANE_CTL_TILED_X
:
9590 plane_config
->tiling
= I915_TILING_X
;
9591 fb
->modifier
= I915_FORMAT_MOD_X_TILED
;
9593 case PLANE_CTL_TILED_Y
:
9594 plane_config
->tiling
= I915_TILING_Y
;
9595 if (val
& PLANE_CTL_RENDER_DECOMPRESSION_ENABLE
)
9596 fb
->modifier
= I915_FORMAT_MOD_Y_TILED_CCS
;
9598 fb
->modifier
= I915_FORMAT_MOD_Y_TILED
;
9600 case PLANE_CTL_TILED_YF
:
9601 if (val
& PLANE_CTL_RENDER_DECOMPRESSION_ENABLE
)
9602 fb
->modifier
= I915_FORMAT_MOD_Yf_TILED_CCS
;
9604 fb
->modifier
= I915_FORMAT_MOD_Yf_TILED
;
9607 MISSING_CASE(tiling
);
9612 * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
9613 * while i915 HW rotation is clockwise, thats why this swapping.
9615 switch (val
& PLANE_CTL_ROTATE_MASK
) {
9616 case PLANE_CTL_ROTATE_0
:
9617 plane_config
->rotation
= DRM_MODE_ROTATE_0
;
9619 case PLANE_CTL_ROTATE_90
:
9620 plane_config
->rotation
= DRM_MODE_ROTATE_270
;
9622 case PLANE_CTL_ROTATE_180
:
9623 plane_config
->rotation
= DRM_MODE_ROTATE_180
;
9625 case PLANE_CTL_ROTATE_270
:
9626 plane_config
->rotation
= DRM_MODE_ROTATE_90
;
9630 if (INTEL_GEN(dev_priv
) >= 10 &&
9631 val
& PLANE_CTL_FLIP_HORIZONTAL
)
9632 plane_config
->rotation
|= DRM_MODE_REFLECT_X
;
9634 base
= I915_READ(PLANE_SURF(pipe
, plane_id
)) & 0xfffff000;
9635 plane_config
->base
= base
;
9637 offset
= I915_READ(PLANE_OFFSET(pipe
, plane_id
));
9639 val
= I915_READ(PLANE_SIZE(pipe
, plane_id
));
9640 fb
->height
= ((val
>> 16) & 0xfff) + 1;
9641 fb
->width
= ((val
>> 0) & 0x1fff) + 1;
9643 val
= I915_READ(PLANE_STRIDE(pipe
, plane_id
));
9644 stride_mult
= skl_plane_stride_mult(fb
, 0, DRM_MODE_ROTATE_0
);
9645 fb
->pitches
[0] = (val
& 0x3ff) * stride_mult
;
9647 aligned_height
= intel_fb_align_height(fb
, 0, fb
->height
);
9649 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
9651 DRM_DEBUG_KMS("%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9652 crtc
->base
.name
, plane
->base
.name
, fb
->width
, fb
->height
,
9653 fb
->format
->cpp
[0] * 8, base
, fb
->pitches
[0],
9654 plane_config
->size
);
9656 plane_config
->fb
= intel_fb
;
9663 static void ironlake_get_pfit_config(struct intel_crtc
*crtc
,
9664 struct intel_crtc_state
*pipe_config
)
9666 struct drm_device
*dev
= crtc
->base
.dev
;
9667 struct drm_i915_private
*dev_priv
= to_i915(dev
);
9670 tmp
= I915_READ(PF_CTL(crtc
->pipe
));
9672 if (tmp
& PF_ENABLE
) {
9673 pipe_config
->pch_pfit
.enabled
= true;
9674 pipe_config
->pch_pfit
.pos
= I915_READ(PF_WIN_POS(crtc
->pipe
));
9675 pipe_config
->pch_pfit
.size
= I915_READ(PF_WIN_SZ(crtc
->pipe
));
9677 /* We currently do not free assignements of panel fitters on
9678 * ivb/hsw (since we don't use the higher upscaling modes which
9679 * differentiates them) so just WARN about this case for now. */
9680 if (IS_GEN(dev_priv
, 7)) {
9681 WARN_ON((tmp
& PF_PIPE_SEL_MASK_IVB
) !=
9682 PF_PIPE_SEL_IVB(crtc
->pipe
));
9687 static bool ironlake_get_pipe_config(struct intel_crtc
*crtc
,
9688 struct intel_crtc_state
*pipe_config
)
9690 struct drm_device
*dev
= crtc
->base
.dev
;
9691 struct drm_i915_private
*dev_priv
= to_i915(dev
);
9692 enum intel_display_power_domain power_domain
;
9693 intel_wakeref_t wakeref
;
9697 power_domain
= POWER_DOMAIN_PIPE(crtc
->pipe
);
9698 wakeref
= intel_display_power_get_if_enabled(dev_priv
, power_domain
);
9702 pipe_config
->output_format
= INTEL_OUTPUT_FORMAT_RGB
;
9703 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
9704 pipe_config
->shared_dpll
= NULL
;
9707 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
9708 if (!(tmp
& PIPECONF_ENABLE
))
9711 switch (tmp
& PIPECONF_BPC_MASK
) {
9713 pipe_config
->pipe_bpp
= 18;
9716 pipe_config
->pipe_bpp
= 24;
9718 case PIPECONF_10BPC
:
9719 pipe_config
->pipe_bpp
= 30;
9721 case PIPECONF_12BPC
:
9722 pipe_config
->pipe_bpp
= 36;
9728 if (tmp
& PIPECONF_COLOR_RANGE_SELECT
)
9729 pipe_config
->limited_color_range
= true;
9731 pipe_config
->gamma_mode
= (tmp
& PIPECONF_GAMMA_MODE_MASK_ILK
) >>
9732 PIPECONF_GAMMA_MODE_SHIFT
;
9734 pipe_config
->csc_mode
= I915_READ(PIPE_CSC_MODE(crtc
->pipe
));
9736 i9xx_get_pipe_color_config(pipe_config
);
9738 if (I915_READ(PCH_TRANSCONF(crtc
->pipe
)) & TRANS_ENABLE
) {
9739 struct intel_shared_dpll
*pll
;
9740 enum intel_dpll_id pll_id
;
9742 pipe_config
->has_pch_encoder
= true;
9744 tmp
= I915_READ(FDI_RX_CTL(crtc
->pipe
));
9745 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
9746 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
9748 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
9750 if (HAS_PCH_IBX(dev_priv
)) {
9752 * The pipe->pch transcoder and pch transcoder->pll
9755 pll_id
= (enum intel_dpll_id
) crtc
->pipe
;
9757 tmp
= I915_READ(PCH_DPLL_SEL
);
9758 if (tmp
& TRANS_DPLLB_SEL(crtc
->pipe
))
9759 pll_id
= DPLL_ID_PCH_PLL_B
;
9761 pll_id
= DPLL_ID_PCH_PLL_A
;
9764 pipe_config
->shared_dpll
=
9765 intel_get_shared_dpll_by_id(dev_priv
, pll_id
);
9766 pll
= pipe_config
->shared_dpll
;
9768 WARN_ON(!pll
->info
->funcs
->get_hw_state(dev_priv
, pll
,
9769 &pipe_config
->dpll_hw_state
));
9771 tmp
= pipe_config
->dpll_hw_state
.dpll
;
9772 pipe_config
->pixel_multiplier
=
9773 ((tmp
& PLL_REF_SDVO_HDMI_MULTIPLIER_MASK
)
9774 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
) + 1;
9776 ironlake_pch_clock_get(crtc
, pipe_config
);
9778 pipe_config
->pixel_multiplier
= 1;
9781 intel_get_pipe_timings(crtc
, pipe_config
);
9782 intel_get_pipe_src_size(crtc
, pipe_config
);
9784 ironlake_get_pfit_config(crtc
, pipe_config
);
9789 intel_display_power_put(dev_priv
, power_domain
, wakeref
);
9793 static int haswell_crtc_compute_clock(struct intel_crtc
*crtc
,
9794 struct intel_crtc_state
*crtc_state
)
9796 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
9797 struct intel_atomic_state
*state
=
9798 to_intel_atomic_state(crtc_state
->base
.state
);
9800 if (!intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_DSI
) ||
9801 INTEL_GEN(dev_priv
) >= 11) {
9802 struct intel_encoder
*encoder
=
9803 intel_get_crtc_new_encoder(state
, crtc_state
);
9805 if (!intel_get_shared_dpll(crtc_state
, encoder
)) {
9806 DRM_DEBUG_KMS("failed to find PLL for pipe %c\n",
9807 pipe_name(crtc
->pipe
));
9815 static void cannonlake_get_ddi_pll(struct drm_i915_private
*dev_priv
,
9817 struct intel_crtc_state
*pipe_config
)
9819 enum intel_dpll_id id
;
9822 temp
= I915_READ(DPCLKA_CFGCR0
) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port
);
9823 id
= temp
>> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port
);
9825 if (WARN_ON(id
< SKL_DPLL0
|| id
> SKL_DPLL2
))
9828 pipe_config
->shared_dpll
= intel_get_shared_dpll_by_id(dev_priv
, id
);
9831 static void icelake_get_ddi_pll(struct drm_i915_private
*dev_priv
,
9833 struct intel_crtc_state
*pipe_config
)
9835 enum intel_dpll_id id
;
9838 /* TODO: TBT pll not implemented. */
9839 if (intel_port_is_combophy(dev_priv
, port
)) {
9840 temp
= I915_READ(DPCLKA_CFGCR0_ICL
) &
9841 DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port
);
9842 id
= temp
>> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port
);
9843 } else if (intel_port_is_tc(dev_priv
, port
)) {
9844 id
= icl_tc_port_to_pll_id(intel_port_to_tc(dev_priv
, port
));
9846 WARN(1, "Invalid port %x\n", port
);
9850 pipe_config
->shared_dpll
= intel_get_shared_dpll_by_id(dev_priv
, id
);
9853 static void bxt_get_ddi_pll(struct drm_i915_private
*dev_priv
,
9855 struct intel_crtc_state
*pipe_config
)
9857 enum intel_dpll_id id
;
9861 id
= DPLL_ID_SKL_DPLL0
;
9864 id
= DPLL_ID_SKL_DPLL1
;
9867 id
= DPLL_ID_SKL_DPLL2
;
9870 DRM_ERROR("Incorrect port type\n");
9874 pipe_config
->shared_dpll
= intel_get_shared_dpll_by_id(dev_priv
, id
);
9877 static void skylake_get_ddi_pll(struct drm_i915_private
*dev_priv
,
9879 struct intel_crtc_state
*pipe_config
)
9881 enum intel_dpll_id id
;
9884 temp
= I915_READ(DPLL_CTRL2
) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port
);
9885 id
= temp
>> (port
* 3 + 1);
9887 if (WARN_ON(id
< SKL_DPLL0
|| id
> SKL_DPLL3
))
9890 pipe_config
->shared_dpll
= intel_get_shared_dpll_by_id(dev_priv
, id
);
9893 static void haswell_get_ddi_pll(struct drm_i915_private
*dev_priv
,
9895 struct intel_crtc_state
*pipe_config
)
9897 enum intel_dpll_id id
;
9898 u32 ddi_pll_sel
= I915_READ(PORT_CLK_SEL(port
));
9900 switch (ddi_pll_sel
) {
9901 case PORT_CLK_SEL_WRPLL1
:
9902 id
= DPLL_ID_WRPLL1
;
9904 case PORT_CLK_SEL_WRPLL2
:
9905 id
= DPLL_ID_WRPLL2
;
9907 case PORT_CLK_SEL_SPLL
:
9910 case PORT_CLK_SEL_LCPLL_810
:
9911 id
= DPLL_ID_LCPLL_810
;
9913 case PORT_CLK_SEL_LCPLL_1350
:
9914 id
= DPLL_ID_LCPLL_1350
;
9916 case PORT_CLK_SEL_LCPLL_2700
:
9917 id
= DPLL_ID_LCPLL_2700
;
9920 MISSING_CASE(ddi_pll_sel
);
9922 case PORT_CLK_SEL_NONE
:
9926 pipe_config
->shared_dpll
= intel_get_shared_dpll_by_id(dev_priv
, id
);
9929 static bool hsw_get_transcoder_state(struct intel_crtc
*crtc
,
9930 struct intel_crtc_state
*pipe_config
,
9931 u64
*power_domain_mask
,
9932 intel_wakeref_t
*wakerefs
)
9934 struct drm_device
*dev
= crtc
->base
.dev
;
9935 struct drm_i915_private
*dev_priv
= to_i915(dev
);
9936 enum intel_display_power_domain power_domain
;
9937 unsigned long panel_transcoder_mask
= 0;
9938 unsigned long enabled_panel_transcoders
= 0;
9939 enum transcoder panel_transcoder
;
9943 if (INTEL_GEN(dev_priv
) >= 11)
9944 panel_transcoder_mask
|=
9945 BIT(TRANSCODER_DSI_0
) | BIT(TRANSCODER_DSI_1
);
9947 if (HAS_TRANSCODER_EDP(dev_priv
))
9948 panel_transcoder_mask
|= BIT(TRANSCODER_EDP
);
9951 * The pipe->transcoder mapping is fixed with the exception of the eDP
9952 * and DSI transcoders handled below.
9954 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
9957 * XXX: Do intel_display_power_get_if_enabled before reading this (for
9958 * consistency and less surprising code; it's in always on power).
9960 for_each_set_bit(panel_transcoder
,
9961 &panel_transcoder_mask
,
9962 ARRAY_SIZE(INTEL_INFO(dev_priv
)->trans_offsets
)) {
9963 bool force_thru
= false;
9964 enum pipe trans_pipe
;
9966 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(panel_transcoder
));
9967 if (!(tmp
& TRANS_DDI_FUNC_ENABLE
))
9971 * Log all enabled ones, only use the first one.
9973 * FIXME: This won't work for two separate DSI displays.
9975 enabled_panel_transcoders
|= BIT(panel_transcoder
);
9976 if (enabled_panel_transcoders
!= BIT(panel_transcoder
))
9979 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
9981 WARN(1, "unknown pipe linked to transcoder %s\n",
9982 transcoder_name(panel_transcoder
));
9984 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
9987 case TRANS_DDI_EDP_INPUT_A_ON
:
9988 trans_pipe
= PIPE_A
;
9990 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
9991 trans_pipe
= PIPE_B
;
9993 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
9994 trans_pipe
= PIPE_C
;
9998 if (trans_pipe
== crtc
->pipe
) {
9999 pipe_config
->cpu_transcoder
= panel_transcoder
;
10000 pipe_config
->pch_pfit
.force_thru
= force_thru
;
10005 * Valid combos: none, eDP, DSI0, DSI1, DSI0+DSI1
10007 WARN_ON((enabled_panel_transcoders
& BIT(TRANSCODER_EDP
)) &&
10008 enabled_panel_transcoders
!= BIT(TRANSCODER_EDP
));
10010 power_domain
= POWER_DOMAIN_TRANSCODER(pipe_config
->cpu_transcoder
);
10011 WARN_ON(*power_domain_mask
& BIT_ULL(power_domain
));
10013 wf
= intel_display_power_get_if_enabled(dev_priv
, power_domain
);
10017 wakerefs
[power_domain
] = wf
;
10018 *power_domain_mask
|= BIT_ULL(power_domain
);
10020 tmp
= I915_READ(PIPECONF(pipe_config
->cpu_transcoder
));
10022 return tmp
& PIPECONF_ENABLE
;
10025 static bool bxt_get_dsi_transcoder_state(struct intel_crtc
*crtc
,
10026 struct intel_crtc_state
*pipe_config
,
10027 u64
*power_domain_mask
,
10028 intel_wakeref_t
*wakerefs
)
10030 struct drm_device
*dev
= crtc
->base
.dev
;
10031 struct drm_i915_private
*dev_priv
= to_i915(dev
);
10032 enum intel_display_power_domain power_domain
;
10033 enum transcoder cpu_transcoder
;
10034 intel_wakeref_t wf
;
10038 for_each_port_masked(port
, BIT(PORT_A
) | BIT(PORT_C
)) {
10039 if (port
== PORT_A
)
10040 cpu_transcoder
= TRANSCODER_DSI_A
;
10042 cpu_transcoder
= TRANSCODER_DSI_C
;
10044 power_domain
= POWER_DOMAIN_TRANSCODER(cpu_transcoder
);
10045 WARN_ON(*power_domain_mask
& BIT_ULL(power_domain
));
10047 wf
= intel_display_power_get_if_enabled(dev_priv
, power_domain
);
10051 wakerefs
[power_domain
] = wf
;
10052 *power_domain_mask
|= BIT_ULL(power_domain
);
10055 * The PLL needs to be enabled with a valid divider
10056 * configuration, otherwise accessing DSI registers will hang
10057 * the machine. See BSpec North Display Engine
10058 * registers/MIPI[BXT]. We can break out here early, since we
10059 * need the same DSI PLL to be enabled for both DSI ports.
10061 if (!bxt_dsi_pll_is_enabled(dev_priv
))
10064 /* XXX: this works for video mode only */
10065 tmp
= I915_READ(BXT_MIPI_PORT_CTRL(port
));
10066 if (!(tmp
& DPI_ENABLE
))
10069 tmp
= I915_READ(MIPI_CTRL(port
));
10070 if ((tmp
& BXT_PIPE_SELECT_MASK
) != BXT_PIPE_SELECT(crtc
->pipe
))
10073 pipe_config
->cpu_transcoder
= cpu_transcoder
;
10077 return transcoder_is_dsi(pipe_config
->cpu_transcoder
);
10080 static void haswell_get_ddi_port_state(struct intel_crtc
*crtc
,
10081 struct intel_crtc_state
*pipe_config
)
10083 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
10084 struct intel_shared_dpll
*pll
;
10088 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(pipe_config
->cpu_transcoder
));
10090 port
= (tmp
& TRANS_DDI_PORT_MASK
) >> TRANS_DDI_PORT_SHIFT
;
10092 if (INTEL_GEN(dev_priv
) >= 11)
10093 icelake_get_ddi_pll(dev_priv
, port
, pipe_config
);
10094 else if (IS_CANNONLAKE(dev_priv
))
10095 cannonlake_get_ddi_pll(dev_priv
, port
, pipe_config
);
10096 else if (IS_GEN9_BC(dev_priv
))
10097 skylake_get_ddi_pll(dev_priv
, port
, pipe_config
);
10098 else if (IS_GEN9_LP(dev_priv
))
10099 bxt_get_ddi_pll(dev_priv
, port
, pipe_config
);
10101 haswell_get_ddi_pll(dev_priv
, port
, pipe_config
);
10103 pll
= pipe_config
->shared_dpll
;
10105 WARN_ON(!pll
->info
->funcs
->get_hw_state(dev_priv
, pll
,
10106 &pipe_config
->dpll_hw_state
));
10110 * Haswell has only FDI/PCH transcoder A. It is which is connected to
10111 * DDI E. So just check whether this pipe is wired to DDI E and whether
10112 * the PCH transcoder is on.
10114 if (INTEL_GEN(dev_priv
) < 9 &&
10115 (port
== PORT_E
) && I915_READ(LPT_TRANSCONF
) & TRANS_ENABLE
) {
10116 pipe_config
->has_pch_encoder
= true;
10118 tmp
= I915_READ(FDI_RX_CTL(PIPE_A
));
10119 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
10120 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
10122 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
10126 static bool haswell_get_pipe_config(struct intel_crtc
*crtc
,
10127 struct intel_crtc_state
*pipe_config
)
10129 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
10130 intel_wakeref_t wakerefs
[POWER_DOMAIN_NUM
], wf
;
10131 enum intel_display_power_domain power_domain
;
10132 u64 power_domain_mask
;
10135 intel_crtc_init_scalers(crtc
, pipe_config
);
10137 power_domain
= POWER_DOMAIN_PIPE(crtc
->pipe
);
10138 wf
= intel_display_power_get_if_enabled(dev_priv
, power_domain
);
10142 wakerefs
[power_domain
] = wf
;
10143 power_domain_mask
= BIT_ULL(power_domain
);
10145 pipe_config
->shared_dpll
= NULL
;
10147 active
= hsw_get_transcoder_state(crtc
, pipe_config
,
10148 &power_domain_mask
, wakerefs
);
10150 if (IS_GEN9_LP(dev_priv
) &&
10151 bxt_get_dsi_transcoder_state(crtc
, pipe_config
,
10152 &power_domain_mask
, wakerefs
)) {
10160 if (!transcoder_is_dsi(pipe_config
->cpu_transcoder
) ||
10161 INTEL_GEN(dev_priv
) >= 11) {
10162 haswell_get_ddi_port_state(crtc
, pipe_config
);
10163 intel_get_pipe_timings(crtc
, pipe_config
);
10166 intel_get_pipe_src_size(crtc
, pipe_config
);
10167 intel_get_crtc_ycbcr_config(crtc
, pipe_config
);
10169 pipe_config
->gamma_mode
= I915_READ(GAMMA_MODE(crtc
->pipe
));
10171 pipe_config
->csc_mode
= I915_READ(PIPE_CSC_MODE(crtc
->pipe
));
10173 if (INTEL_GEN(dev_priv
) >= 9) {
10174 u32 tmp
= I915_READ(SKL_BOTTOM_COLOR(crtc
->pipe
));
10176 if (tmp
& SKL_BOTTOM_COLOR_GAMMA_ENABLE
)
10177 pipe_config
->gamma_enable
= true;
10179 if (tmp
& SKL_BOTTOM_COLOR_CSC_ENABLE
)
10180 pipe_config
->csc_enable
= true;
10182 i9xx_get_pipe_color_config(pipe_config
);
10185 power_domain
= POWER_DOMAIN_PIPE_PANEL_FITTER(crtc
->pipe
);
10186 WARN_ON(power_domain_mask
& BIT_ULL(power_domain
));
10188 wf
= intel_display_power_get_if_enabled(dev_priv
, power_domain
);
10190 wakerefs
[power_domain
] = wf
;
10191 power_domain_mask
|= BIT_ULL(power_domain
);
10193 if (INTEL_GEN(dev_priv
) >= 9)
10194 skylake_get_pfit_config(crtc
, pipe_config
);
10196 ironlake_get_pfit_config(crtc
, pipe_config
);
10199 if (hsw_crtc_supports_ips(crtc
)) {
10200 if (IS_HASWELL(dev_priv
))
10201 pipe_config
->ips_enabled
= I915_READ(IPS_CTL
) & IPS_ENABLE
;
10204 * We cannot readout IPS state on broadwell, set to
10205 * true so we can set it to a defined state on first
10208 pipe_config
->ips_enabled
= true;
10212 if (pipe_config
->cpu_transcoder
!= TRANSCODER_EDP
&&
10213 !transcoder_is_dsi(pipe_config
->cpu_transcoder
)) {
10214 pipe_config
->pixel_multiplier
=
10215 I915_READ(PIPE_MULT(pipe_config
->cpu_transcoder
)) + 1;
10217 pipe_config
->pixel_multiplier
= 1;
10221 for_each_power_domain(power_domain
, power_domain_mask
)
10222 intel_display_power_put(dev_priv
,
10223 power_domain
, wakerefs
[power_domain
]);
10228 static u32
intel_cursor_base(const struct intel_plane_state
*plane_state
)
10230 struct drm_i915_private
*dev_priv
=
10231 to_i915(plane_state
->base
.plane
->dev
);
10232 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
10233 const struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
10236 if (INTEL_INFO(dev_priv
)->display
.cursor_needs_physical
)
10237 base
= obj
->phys_handle
->busaddr
;
10239 base
= intel_plane_ggtt_offset(plane_state
);
10241 base
+= plane_state
->color_plane
[0].offset
;
10243 /* ILK+ do this automagically */
10244 if (HAS_GMCH(dev_priv
) &&
10245 plane_state
->base
.rotation
& DRM_MODE_ROTATE_180
)
10246 base
+= (plane_state
->base
.crtc_h
*
10247 plane_state
->base
.crtc_w
- 1) * fb
->format
->cpp
[0];
10252 static u32
intel_cursor_position(const struct intel_plane_state
*plane_state
)
10254 int x
= plane_state
->base
.crtc_x
;
10255 int y
= plane_state
->base
.crtc_y
;
10259 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
10262 pos
|= x
<< CURSOR_X_SHIFT
;
10265 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
10268 pos
|= y
<< CURSOR_Y_SHIFT
;
10273 static bool intel_cursor_size_ok(const struct intel_plane_state
*plane_state
)
10275 const struct drm_mode_config
*config
=
10276 &plane_state
->base
.plane
->dev
->mode_config
;
10277 int width
= plane_state
->base
.crtc_w
;
10278 int height
= plane_state
->base
.crtc_h
;
10280 return width
> 0 && width
<= config
->cursor_width
&&
10281 height
> 0 && height
<= config
->cursor_height
;
10284 static int intel_cursor_check_surface(struct intel_plane_state
*plane_state
)
10290 ret
= intel_plane_compute_gtt(plane_state
);
10294 if (!plane_state
->base
.visible
)
10297 src_x
= plane_state
->base
.src_x
>> 16;
10298 src_y
= plane_state
->base
.src_y
>> 16;
10300 intel_add_fb_offsets(&src_x
, &src_y
, plane_state
, 0);
10301 offset
= intel_plane_compute_aligned_offset(&src_x
, &src_y
,
10304 if (src_x
!= 0 || src_y
!= 0) {
10305 DRM_DEBUG_KMS("Arbitrary cursor panning not supported\n");
10309 plane_state
->color_plane
[0].offset
= offset
;
10314 static int intel_check_cursor(struct intel_crtc_state
*crtc_state
,
10315 struct intel_plane_state
*plane_state
)
10317 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
10320 if (fb
&& fb
->modifier
!= DRM_FORMAT_MOD_LINEAR
) {
10321 DRM_DEBUG_KMS("cursor cannot be tiled\n");
10325 ret
= drm_atomic_helper_check_plane_state(&plane_state
->base
,
10327 DRM_PLANE_HELPER_NO_SCALING
,
10328 DRM_PLANE_HELPER_NO_SCALING
,
10333 ret
= intel_cursor_check_surface(plane_state
);
10337 if (!plane_state
->base
.visible
)
10340 ret
= intel_plane_check_src_coordinates(plane_state
);
10347 static unsigned int
10348 i845_cursor_max_stride(struct intel_plane
*plane
,
10349 u32 pixel_format
, u64 modifier
,
10350 unsigned int rotation
)
10355 static u32
i845_cursor_ctl_crtc(const struct intel_crtc_state
*crtc_state
)
10359 if (crtc_state
->gamma_enable
)
10360 cntl
|= CURSOR_GAMMA_ENABLE
;
10365 static u32
i845_cursor_ctl(const struct intel_crtc_state
*crtc_state
,
10366 const struct intel_plane_state
*plane_state
)
10368 return CURSOR_ENABLE
|
10369 CURSOR_FORMAT_ARGB
|
10370 CURSOR_STRIDE(plane_state
->color_plane
[0].stride
);
10373 static bool i845_cursor_size_ok(const struct intel_plane_state
*plane_state
)
10375 int width
= plane_state
->base
.crtc_w
;
10378 * 845g/865g are only limited by the width of their cursors,
10379 * the height is arbitrary up to the precision of the register.
10381 return intel_cursor_size_ok(plane_state
) && IS_ALIGNED(width
, 64);
10384 static int i845_check_cursor(struct intel_crtc_state
*crtc_state
,
10385 struct intel_plane_state
*plane_state
)
10387 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
10390 ret
= intel_check_cursor(crtc_state
, plane_state
);
10394 /* if we want to turn off the cursor ignore width and height */
10398 /* Check for which cursor types we support */
10399 if (!i845_cursor_size_ok(plane_state
)) {
10400 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
10401 plane_state
->base
.crtc_w
,
10402 plane_state
->base
.crtc_h
);
10406 WARN_ON(plane_state
->base
.visible
&&
10407 plane_state
->color_plane
[0].stride
!= fb
->pitches
[0]);
10409 switch (fb
->pitches
[0]) {
10416 DRM_DEBUG_KMS("Invalid cursor stride (%u)\n",
10421 plane_state
->ctl
= i845_cursor_ctl(crtc_state
, plane_state
);
10426 static void i845_update_cursor(struct intel_plane
*plane
,
10427 const struct intel_crtc_state
*crtc_state
,
10428 const struct intel_plane_state
*plane_state
)
10430 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
10431 u32 cntl
= 0, base
= 0, pos
= 0, size
= 0;
10432 unsigned long irqflags
;
10434 if (plane_state
&& plane_state
->base
.visible
) {
10435 unsigned int width
= plane_state
->base
.crtc_w
;
10436 unsigned int height
= plane_state
->base
.crtc_h
;
10438 cntl
= plane_state
->ctl
|
10439 i845_cursor_ctl_crtc(crtc_state
);
10441 size
= (height
<< 12) | width
;
10443 base
= intel_cursor_base(plane_state
);
10444 pos
= intel_cursor_position(plane_state
);
10447 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
10449 /* On these chipsets we can only modify the base/size/stride
10450 * whilst the cursor is disabled.
10452 if (plane
->cursor
.base
!= base
||
10453 plane
->cursor
.size
!= size
||
10454 plane
->cursor
.cntl
!= cntl
) {
10455 I915_WRITE_FW(CURCNTR(PIPE_A
), 0);
10456 I915_WRITE_FW(CURBASE(PIPE_A
), base
);
10457 I915_WRITE_FW(CURSIZE
, size
);
10458 I915_WRITE_FW(CURPOS(PIPE_A
), pos
);
10459 I915_WRITE_FW(CURCNTR(PIPE_A
), cntl
);
10461 plane
->cursor
.base
= base
;
10462 plane
->cursor
.size
= size
;
10463 plane
->cursor
.cntl
= cntl
;
10465 I915_WRITE_FW(CURPOS(PIPE_A
), pos
);
10468 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
10471 static void i845_disable_cursor(struct intel_plane
*plane
,
10472 const struct intel_crtc_state
*crtc_state
)
10474 i845_update_cursor(plane
, crtc_state
, NULL
);
10477 static bool i845_cursor_get_hw_state(struct intel_plane
*plane
,
10480 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
10481 enum intel_display_power_domain power_domain
;
10482 intel_wakeref_t wakeref
;
10485 power_domain
= POWER_DOMAIN_PIPE(PIPE_A
);
10486 wakeref
= intel_display_power_get_if_enabled(dev_priv
, power_domain
);
10490 ret
= I915_READ(CURCNTR(PIPE_A
)) & CURSOR_ENABLE
;
10494 intel_display_power_put(dev_priv
, power_domain
, wakeref
);
10499 static unsigned int
10500 i9xx_cursor_max_stride(struct intel_plane
*plane
,
10501 u32 pixel_format
, u64 modifier
,
10502 unsigned int rotation
)
10504 return plane
->base
.dev
->mode_config
.cursor_width
* 4;
10507 static u32
i9xx_cursor_ctl_crtc(const struct intel_crtc_state
*crtc_state
)
10509 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
10510 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
10513 if (INTEL_GEN(dev_priv
) >= 11)
10516 if (crtc_state
->gamma_enable
)
10517 cntl
= MCURSOR_GAMMA_ENABLE
;
10519 if (crtc_state
->csc_enable
)
10520 cntl
|= MCURSOR_PIPE_CSC_ENABLE
;
10522 if (INTEL_GEN(dev_priv
) < 5 && !IS_G4X(dev_priv
))
10523 cntl
|= MCURSOR_PIPE_SELECT(crtc
->pipe
);
10528 static u32
i9xx_cursor_ctl(const struct intel_crtc_state
*crtc_state
,
10529 const struct intel_plane_state
*plane_state
)
10531 struct drm_i915_private
*dev_priv
=
10532 to_i915(plane_state
->base
.plane
->dev
);
10535 if (IS_GEN(dev_priv
, 6) || IS_IVYBRIDGE(dev_priv
))
10536 cntl
|= MCURSOR_TRICKLE_FEED_DISABLE
;
10538 switch (plane_state
->base
.crtc_w
) {
10540 cntl
|= MCURSOR_MODE_64_ARGB_AX
;
10543 cntl
|= MCURSOR_MODE_128_ARGB_AX
;
10546 cntl
|= MCURSOR_MODE_256_ARGB_AX
;
10549 MISSING_CASE(plane_state
->base
.crtc_w
);
10553 if (plane_state
->base
.rotation
& DRM_MODE_ROTATE_180
)
10554 cntl
|= MCURSOR_ROTATE_180
;
10559 static bool i9xx_cursor_size_ok(const struct intel_plane_state
*plane_state
)
10561 struct drm_i915_private
*dev_priv
=
10562 to_i915(plane_state
->base
.plane
->dev
);
10563 int width
= plane_state
->base
.crtc_w
;
10564 int height
= plane_state
->base
.crtc_h
;
10566 if (!intel_cursor_size_ok(plane_state
))
10569 /* Cursor width is limited to a few power-of-two sizes */
10580 * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor
10581 * height from 8 lines up to the cursor width, when the
10582 * cursor is not rotated. Everything else requires square
10585 if (HAS_CUR_FBC(dev_priv
) &&
10586 plane_state
->base
.rotation
& DRM_MODE_ROTATE_0
) {
10587 if (height
< 8 || height
> width
)
10590 if (height
!= width
)
10597 static int i9xx_check_cursor(struct intel_crtc_state
*crtc_state
,
10598 struct intel_plane_state
*plane_state
)
10600 struct intel_plane
*plane
= to_intel_plane(plane_state
->base
.plane
);
10601 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
10602 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
10603 enum pipe pipe
= plane
->pipe
;
10606 ret
= intel_check_cursor(crtc_state
, plane_state
);
10610 /* if we want to turn off the cursor ignore width and height */
10614 /* Check for which cursor types we support */
10615 if (!i9xx_cursor_size_ok(plane_state
)) {
10616 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
10617 plane_state
->base
.crtc_w
,
10618 plane_state
->base
.crtc_h
);
10622 WARN_ON(plane_state
->base
.visible
&&
10623 plane_state
->color_plane
[0].stride
!= fb
->pitches
[0]);
10625 if (fb
->pitches
[0] != plane_state
->base
.crtc_w
* fb
->format
->cpp
[0]) {
10626 DRM_DEBUG_KMS("Invalid cursor stride (%u) (cursor width %d)\n",
10627 fb
->pitches
[0], plane_state
->base
.crtc_w
);
10632 * There's something wrong with the cursor on CHV pipe C.
10633 * If it straddles the left edge of the screen then
10634 * moving it away from the edge or disabling it often
10635 * results in a pipe underrun, and often that can lead to
10636 * dead pipe (constant underrun reported, and it scans
10637 * out just a solid color). To recover from that, the
10638 * display power well must be turned off and on again.
10639 * Refuse the put the cursor into that compromised position.
10641 if (IS_CHERRYVIEW(dev_priv
) && pipe
== PIPE_C
&&
10642 plane_state
->base
.visible
&& plane_state
->base
.crtc_x
< 0) {
10643 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
10647 plane_state
->ctl
= i9xx_cursor_ctl(crtc_state
, plane_state
);
10652 static void i9xx_update_cursor(struct intel_plane
*plane
,
10653 const struct intel_crtc_state
*crtc_state
,
10654 const struct intel_plane_state
*plane_state
)
10656 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
10657 enum pipe pipe
= plane
->pipe
;
10658 u32 cntl
= 0, base
= 0, pos
= 0, fbc_ctl
= 0;
10659 unsigned long irqflags
;
10661 if (plane_state
&& plane_state
->base
.visible
) {
10662 cntl
= plane_state
->ctl
|
10663 i9xx_cursor_ctl_crtc(crtc_state
);
10665 if (plane_state
->base
.crtc_h
!= plane_state
->base
.crtc_w
)
10666 fbc_ctl
= CUR_FBC_CTL_EN
| (plane_state
->base
.crtc_h
- 1);
10668 base
= intel_cursor_base(plane_state
);
10669 pos
= intel_cursor_position(plane_state
);
10672 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
10675 * On some platforms writing CURCNTR first will also
10676 * cause CURPOS to be armed by the CURBASE write.
10677 * Without the CURCNTR write the CURPOS write would
10678 * arm itself. Thus we always update CURCNTR before
10681 * On other platforms CURPOS always requires the
10682 * CURBASE write to arm the update. Additonally
10683 * a write to any of the cursor register will cancel
10684 * an already armed cursor update. Thus leaving out
10685 * the CURBASE write after CURPOS could lead to a
10686 * cursor that doesn't appear to move, or even change
10687 * shape. Thus we always write CURBASE.
10689 * The other registers are armed by by the CURBASE write
10690 * except when the plane is getting enabled at which time
10691 * the CURCNTR write arms the update.
10694 if (INTEL_GEN(dev_priv
) >= 9)
10695 skl_write_cursor_wm(plane
, crtc_state
);
10697 if (plane
->cursor
.base
!= base
||
10698 plane
->cursor
.size
!= fbc_ctl
||
10699 plane
->cursor
.cntl
!= cntl
) {
10700 if (HAS_CUR_FBC(dev_priv
))
10701 I915_WRITE_FW(CUR_FBC_CTL(pipe
), fbc_ctl
);
10702 I915_WRITE_FW(CURCNTR(pipe
), cntl
);
10703 I915_WRITE_FW(CURPOS(pipe
), pos
);
10704 I915_WRITE_FW(CURBASE(pipe
), base
);
10706 plane
->cursor
.base
= base
;
10707 plane
->cursor
.size
= fbc_ctl
;
10708 plane
->cursor
.cntl
= cntl
;
10710 I915_WRITE_FW(CURPOS(pipe
), pos
);
10711 I915_WRITE_FW(CURBASE(pipe
), base
);
10714 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
10717 static void i9xx_disable_cursor(struct intel_plane
*plane
,
10718 const struct intel_crtc_state
*crtc_state
)
10720 i9xx_update_cursor(plane
, crtc_state
, NULL
);
10723 static bool i9xx_cursor_get_hw_state(struct intel_plane
*plane
,
10726 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
10727 enum intel_display_power_domain power_domain
;
10728 intel_wakeref_t wakeref
;
10733 * Not 100% correct for planes that can move between pipes,
10734 * but that's only the case for gen2-3 which don't have any
10735 * display power wells.
10737 power_domain
= POWER_DOMAIN_PIPE(plane
->pipe
);
10738 wakeref
= intel_display_power_get_if_enabled(dev_priv
, power_domain
);
10742 val
= I915_READ(CURCNTR(plane
->pipe
));
10744 ret
= val
& MCURSOR_MODE
;
10746 if (INTEL_GEN(dev_priv
) >= 5 || IS_G4X(dev_priv
))
10747 *pipe
= plane
->pipe
;
10749 *pipe
= (val
& MCURSOR_PIPE_SELECT_MASK
) >>
10750 MCURSOR_PIPE_SELECT_SHIFT
;
10752 intel_display_power_put(dev_priv
, power_domain
, wakeref
);
10757 /* VESA 640x480x72Hz mode to set on the pipe */
10758 static const struct drm_display_mode load_detect_mode
= {
10759 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
10760 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
10763 struct drm_framebuffer
*
10764 intel_framebuffer_create(struct drm_i915_gem_object
*obj
,
10765 struct drm_mode_fb_cmd2
*mode_cmd
)
10767 struct intel_framebuffer
*intel_fb
;
10770 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
10772 return ERR_PTR(-ENOMEM
);
10774 ret
= intel_framebuffer_init(intel_fb
, obj
, mode_cmd
);
10778 return &intel_fb
->base
;
10782 return ERR_PTR(ret
);
10785 static int intel_modeset_disable_planes(struct drm_atomic_state
*state
,
10786 struct drm_crtc
*crtc
)
10788 struct drm_plane
*plane
;
10789 struct drm_plane_state
*plane_state
;
10792 ret
= drm_atomic_add_affected_planes(state
, crtc
);
10796 for_each_new_plane_in_state(state
, plane
, plane_state
, i
) {
10797 if (plane_state
->crtc
!= crtc
)
10800 ret
= drm_atomic_set_crtc_for_plane(plane_state
, NULL
);
10804 drm_atomic_set_fb_for_plane(plane_state
, NULL
);
10810 int intel_get_load_detect_pipe(struct drm_connector
*connector
,
10811 const struct drm_display_mode
*mode
,
10812 struct intel_load_detect_pipe
*old
,
10813 struct drm_modeset_acquire_ctx
*ctx
)
10815 struct intel_crtc
*intel_crtc
;
10816 struct intel_encoder
*intel_encoder
=
10817 intel_attached_encoder(connector
);
10818 struct drm_crtc
*possible_crtc
;
10819 struct drm_encoder
*encoder
= &intel_encoder
->base
;
10820 struct drm_crtc
*crtc
= NULL
;
10821 struct drm_device
*dev
= encoder
->dev
;
10822 struct drm_i915_private
*dev_priv
= to_i915(dev
);
10823 struct drm_mode_config
*config
= &dev
->mode_config
;
10824 struct drm_atomic_state
*state
= NULL
, *restore_state
= NULL
;
10825 struct drm_connector_state
*connector_state
;
10826 struct intel_crtc_state
*crtc_state
;
10829 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10830 connector
->base
.id
, connector
->name
,
10831 encoder
->base
.id
, encoder
->name
);
10833 old
->restore_state
= NULL
;
10835 WARN_ON(!drm_modeset_is_locked(&config
->connection_mutex
));
10838 * Algorithm gets a little messy:
10840 * - if the connector already has an assigned crtc, use it (but make
10841 * sure it's on first)
10843 * - try to find the first unused crtc that can drive this connector,
10844 * and use that if we find one
10847 /* See if we already have a CRTC for this connector */
10848 if (connector
->state
->crtc
) {
10849 crtc
= connector
->state
->crtc
;
10851 ret
= drm_modeset_lock(&crtc
->mutex
, ctx
);
10855 /* Make sure the crtc and connector are running */
10859 /* Find an unused one (if possible) */
10860 for_each_crtc(dev
, possible_crtc
) {
10862 if (!(encoder
->possible_crtcs
& (1 << i
)))
10865 ret
= drm_modeset_lock(&possible_crtc
->mutex
, ctx
);
10869 if (possible_crtc
->state
->enable
) {
10870 drm_modeset_unlock(&possible_crtc
->mutex
);
10874 crtc
= possible_crtc
;
10879 * If we didn't find an unused CRTC, don't use any.
10882 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10888 intel_crtc
= to_intel_crtc(crtc
);
10890 state
= drm_atomic_state_alloc(dev
);
10891 restore_state
= drm_atomic_state_alloc(dev
);
10892 if (!state
|| !restore_state
) {
10897 state
->acquire_ctx
= ctx
;
10898 restore_state
->acquire_ctx
= ctx
;
10900 connector_state
= drm_atomic_get_connector_state(state
, connector
);
10901 if (IS_ERR(connector_state
)) {
10902 ret
= PTR_ERR(connector_state
);
10906 ret
= drm_atomic_set_crtc_for_connector(connector_state
, crtc
);
10910 crtc_state
= intel_atomic_get_crtc_state(state
, intel_crtc
);
10911 if (IS_ERR(crtc_state
)) {
10912 ret
= PTR_ERR(crtc_state
);
10916 crtc_state
->base
.active
= crtc_state
->base
.enable
= true;
10919 mode
= &load_detect_mode
;
10921 ret
= drm_atomic_set_mode_for_crtc(&crtc_state
->base
, mode
);
10925 ret
= intel_modeset_disable_planes(state
, crtc
);
10929 ret
= PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state
, connector
));
10931 ret
= PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state
, crtc
));
10933 ret
= drm_atomic_add_affected_planes(restore_state
, crtc
);
10935 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret
);
10939 ret
= drm_atomic_commit(state
);
10941 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10945 old
->restore_state
= restore_state
;
10946 drm_atomic_state_put(state
);
10948 /* let the connector get through one full cycle before testing */
10949 intel_wait_for_vblank(dev_priv
, intel_crtc
->pipe
);
10954 drm_atomic_state_put(state
);
10957 if (restore_state
) {
10958 drm_atomic_state_put(restore_state
);
10959 restore_state
= NULL
;
10962 if (ret
== -EDEADLK
)
10968 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
10969 struct intel_load_detect_pipe
*old
,
10970 struct drm_modeset_acquire_ctx
*ctx
)
10972 struct intel_encoder
*intel_encoder
=
10973 intel_attached_encoder(connector
);
10974 struct drm_encoder
*encoder
= &intel_encoder
->base
;
10975 struct drm_atomic_state
*state
= old
->restore_state
;
10978 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10979 connector
->base
.id
, connector
->name
,
10980 encoder
->base
.id
, encoder
->name
);
10985 ret
= drm_atomic_helper_commit_duplicated_state(state
, ctx
);
10987 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret
);
10988 drm_atomic_state_put(state
);
10991 static int i9xx_pll_refclk(struct drm_device
*dev
,
10992 const struct intel_crtc_state
*pipe_config
)
10994 struct drm_i915_private
*dev_priv
= to_i915(dev
);
10995 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
10997 if ((dpll
& PLL_REF_INPUT_MASK
) == PLLB_REF_INPUT_SPREADSPECTRUMIN
)
10998 return dev_priv
->vbt
.lvds_ssc_freq
;
10999 else if (HAS_PCH_SPLIT(dev_priv
))
11001 else if (!IS_GEN(dev_priv
, 2))
11007 /* Returns the clock of the currently programmed mode of the given pipe. */
11008 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
11009 struct intel_crtc_state
*pipe_config
)
11011 struct drm_device
*dev
= crtc
->base
.dev
;
11012 struct drm_i915_private
*dev_priv
= to_i915(dev
);
11013 int pipe
= pipe_config
->cpu_transcoder
;
11014 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
11018 int refclk
= i9xx_pll_refclk(dev
, pipe_config
);
11020 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
11021 fp
= pipe_config
->dpll_hw_state
.fp0
;
11023 fp
= pipe_config
->dpll_hw_state
.fp1
;
11025 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
11026 if (IS_PINEVIEW(dev_priv
)) {
11027 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
11028 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
11030 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
11031 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
11034 if (!IS_GEN(dev_priv
, 2)) {
11035 if (IS_PINEVIEW(dev_priv
))
11036 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
11037 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
11039 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
11040 DPLL_FPA01_P1_POST_DIV_SHIFT
);
11042 switch (dpll
& DPLL_MODE_MASK
) {
11043 case DPLLB_MODE_DAC_SERIAL
:
11044 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
11047 case DPLLB_MODE_LVDS
:
11048 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
11052 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
11053 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
11057 if (IS_PINEVIEW(dev_priv
))
11058 port_clock
= pnv_calc_dpll_params(refclk
, &clock
);
11060 port_clock
= i9xx_calc_dpll_params(refclk
, &clock
);
11062 u32 lvds
= IS_I830(dev_priv
) ? 0 : I915_READ(LVDS
);
11063 bool is_lvds
= (pipe
== 1) && (lvds
& LVDS_PORT_EN
);
11066 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
11067 DPLL_FPA01_P1_POST_DIV_SHIFT
);
11069 if (lvds
& LVDS_CLKB_POWER_UP
)
11074 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
11077 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
11078 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
11080 if (dpll
& PLL_P2_DIVIDE_BY_4
)
11086 port_clock
= i9xx_calc_dpll_params(refclk
, &clock
);
11090 * This value includes pixel_multiplier. We will use
11091 * port_clock to compute adjusted_mode.crtc_clock in the
11092 * encoder's get_config() function.
11094 pipe_config
->port_clock
= port_clock
;
11097 int intel_dotclock_calculate(int link_freq
,
11098 const struct intel_link_m_n
*m_n
)
11101 * The calculation for the data clock is:
11102 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
11103 * But we want to avoid losing precison if possible, so:
11104 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
11106 * and the link clock is simpler:
11107 * link_clock = (m * link_clock) / n
11113 return div_u64(mul_u32_u32(m_n
->link_m
, link_freq
), m_n
->link_n
);
11116 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
11117 struct intel_crtc_state
*pipe_config
)
11119 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
11121 /* read out port_clock from the DPLL */
11122 i9xx_crtc_clock_get(crtc
, pipe_config
);
11125 * In case there is an active pipe without active ports,
11126 * we may need some idea for the dotclock anyway.
11127 * Calculate one based on the FDI configuration.
11129 pipe_config
->base
.adjusted_mode
.crtc_clock
=
11130 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv
, pipe_config
),
11131 &pipe_config
->fdi_m_n
);
11134 /* Returns the currently programmed mode of the given encoder. */
11135 struct drm_display_mode
*
11136 intel_encoder_current_mode(struct intel_encoder
*encoder
)
11138 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
11139 struct intel_crtc_state
*crtc_state
;
11140 struct drm_display_mode
*mode
;
11141 struct intel_crtc
*crtc
;
11144 if (!encoder
->get_hw_state(encoder
, &pipe
))
11147 crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
11149 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
11153 crtc_state
= kzalloc(sizeof(*crtc_state
), GFP_KERNEL
);
11159 crtc_state
->base
.crtc
= &crtc
->base
;
11161 if (!dev_priv
->display
.get_pipe_config(crtc
, crtc_state
)) {
11167 encoder
->get_config(encoder
, crtc_state
);
11169 intel_mode_from_pipe_config(mode
, crtc_state
);
11176 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
11178 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11180 drm_crtc_cleanup(crtc
);
11185 * intel_wm_need_update - Check whether watermarks need updating
11186 * @cur: current plane state
11187 * @new: new plane state
11189 * Check current plane state versus the new one to determine whether
11190 * watermarks need to be recalculated.
11192 * Returns true or false.
11194 static bool intel_wm_need_update(struct intel_plane_state
*cur
,
11195 struct intel_plane_state
*new)
11197 /* Update watermarks on tiling or size changes. */
11198 if (new->base
.visible
!= cur
->base
.visible
)
11201 if (!cur
->base
.fb
|| !new->base
.fb
)
11204 if (cur
->base
.fb
->modifier
!= new->base
.fb
->modifier
||
11205 cur
->base
.rotation
!= new->base
.rotation
||
11206 drm_rect_width(&new->base
.src
) != drm_rect_width(&cur
->base
.src
) ||
11207 drm_rect_height(&new->base
.src
) != drm_rect_height(&cur
->base
.src
) ||
11208 drm_rect_width(&new->base
.dst
) != drm_rect_width(&cur
->base
.dst
) ||
11209 drm_rect_height(&new->base
.dst
) != drm_rect_height(&cur
->base
.dst
))
11215 static bool needs_scaling(const struct intel_plane_state
*state
)
11217 int src_w
= drm_rect_width(&state
->base
.src
) >> 16;
11218 int src_h
= drm_rect_height(&state
->base
.src
) >> 16;
11219 int dst_w
= drm_rect_width(&state
->base
.dst
);
11220 int dst_h
= drm_rect_height(&state
->base
.dst
);
11222 return (src_w
!= dst_w
|| src_h
!= dst_h
);
11225 int intel_plane_atomic_calc_changes(const struct intel_crtc_state
*old_crtc_state
,
11226 struct drm_crtc_state
*crtc_state
,
11227 const struct intel_plane_state
*old_plane_state
,
11228 struct drm_plane_state
*plane_state
)
11230 struct intel_crtc_state
*pipe_config
= to_intel_crtc_state(crtc_state
);
11231 struct drm_crtc
*crtc
= crtc_state
->crtc
;
11232 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11233 struct intel_plane
*plane
= to_intel_plane(plane_state
->plane
);
11234 struct drm_device
*dev
= crtc
->dev
;
11235 struct drm_i915_private
*dev_priv
= to_i915(dev
);
11236 bool mode_changed
= needs_modeset(crtc_state
);
11237 bool was_crtc_enabled
= old_crtc_state
->base
.active
;
11238 bool is_crtc_enabled
= crtc_state
->active
;
11239 bool turn_off
, turn_on
, visible
, was_visible
;
11240 struct drm_framebuffer
*fb
= plane_state
->fb
;
11243 if (INTEL_GEN(dev_priv
) >= 9 && plane
->id
!= PLANE_CURSOR
) {
11244 ret
= skl_update_scaler_plane(
11245 to_intel_crtc_state(crtc_state
),
11246 to_intel_plane_state(plane_state
));
11251 was_visible
= old_plane_state
->base
.visible
;
11252 visible
= plane_state
->visible
;
11254 if (!was_crtc_enabled
&& WARN_ON(was_visible
))
11255 was_visible
= false;
11258 * Visibility is calculated as if the crtc was on, but
11259 * after scaler setup everything depends on it being off
11260 * when the crtc isn't active.
11262 * FIXME this is wrong for watermarks. Watermarks should also
11263 * be computed as if the pipe would be active. Perhaps move
11264 * per-plane wm computation to the .check_plane() hook, and
11265 * only combine the results from all planes in the current place?
11267 if (!is_crtc_enabled
) {
11268 plane_state
->visible
= visible
= false;
11269 to_intel_crtc_state(crtc_state
)->active_planes
&= ~BIT(plane
->id
);
11272 if (!was_visible
&& !visible
)
11275 if (fb
!= old_plane_state
->base
.fb
)
11276 pipe_config
->fb_changed
= true;
11278 turn_off
= was_visible
&& (!visible
|| mode_changed
);
11279 turn_on
= visible
&& (!was_visible
|| mode_changed
);
11281 DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
11282 intel_crtc
->base
.base
.id
, intel_crtc
->base
.name
,
11283 plane
->base
.base
.id
, plane
->base
.name
,
11284 fb
? fb
->base
.id
: -1);
11286 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
11287 plane
->base
.base
.id
, plane
->base
.name
,
11288 was_visible
, visible
,
11289 turn_off
, turn_on
, mode_changed
);
11292 if (INTEL_GEN(dev_priv
) < 5 && !IS_G4X(dev_priv
))
11293 pipe_config
->update_wm_pre
= true;
11295 /* must disable cxsr around plane enable/disable */
11296 if (plane
->id
!= PLANE_CURSOR
)
11297 pipe_config
->disable_cxsr
= true;
11298 } else if (turn_off
) {
11299 if (INTEL_GEN(dev_priv
) < 5 && !IS_G4X(dev_priv
))
11300 pipe_config
->update_wm_post
= true;
11302 /* must disable cxsr around plane enable/disable */
11303 if (plane
->id
!= PLANE_CURSOR
)
11304 pipe_config
->disable_cxsr
= true;
11305 } else if (intel_wm_need_update(to_intel_plane_state(plane
->base
.state
),
11306 to_intel_plane_state(plane_state
))) {
11307 if (INTEL_GEN(dev_priv
) < 5 && !IS_G4X(dev_priv
)) {
11308 /* FIXME bollocks */
11309 pipe_config
->update_wm_pre
= true;
11310 pipe_config
->update_wm_post
= true;
11314 if (visible
|| was_visible
)
11315 pipe_config
->fb_bits
|= plane
->frontbuffer_bit
;
11318 * ILK/SNB DVSACNTR/Sprite Enable
11319 * IVB SPR_CTL/Sprite Enable
11320 * "When in Self Refresh Big FIFO mode, a write to enable the
11321 * plane will be internally buffered and delayed while Big FIFO
11322 * mode is exiting."
11324 * Which means that enabling the sprite can take an extra frame
11325 * when we start in big FIFO mode (LP1+). Thus we need to drop
11326 * down to LP0 and wait for vblank in order to make sure the
11327 * sprite gets enabled on the next vblank after the register write.
11328 * Doing otherwise would risk enabling the sprite one frame after
11329 * we've already signalled flip completion. We can resume LP1+
11330 * once the sprite has been enabled.
11333 * WaCxSRDisabledForSpriteScaling:ivb
11334 * IVB SPR_SCALE/Scaling Enable
11335 * "Low Power watermarks must be disabled for at least one
11336 * frame before enabling sprite scaling, and kept disabled
11337 * until sprite scaling is disabled."
11339 * ILK/SNB DVSASCALE/Scaling Enable
11340 * "When in Self Refresh Big FIFO mode, scaling enable will be
11341 * masked off while Big FIFO mode is exiting."
11343 * Despite the w/a only being listed for IVB we assume that
11344 * the ILK/SNB note has similar ramifications, hence we apply
11345 * the w/a on all three platforms.
11347 * With experimental results seems this is needed also for primary
11348 * plane, not only sprite plane.
11350 if (plane
->id
!= PLANE_CURSOR
&&
11351 (IS_GEN_RANGE(dev_priv
, 5, 6) ||
11352 IS_IVYBRIDGE(dev_priv
)) &&
11353 (turn_on
|| (!needs_scaling(old_plane_state
) &&
11354 needs_scaling(to_intel_plane_state(plane_state
)))))
11355 pipe_config
->disable_lp_wm
= true;
11360 static bool encoders_cloneable(const struct intel_encoder
*a
,
11361 const struct intel_encoder
*b
)
11363 /* masks could be asymmetric, so check both ways */
11364 return a
== b
|| (a
->cloneable
& (1 << b
->type
) &&
11365 b
->cloneable
& (1 << a
->type
));
11368 static bool check_single_encoder_cloning(struct drm_atomic_state
*state
,
11369 struct intel_crtc
*crtc
,
11370 struct intel_encoder
*encoder
)
11372 struct intel_encoder
*source_encoder
;
11373 struct drm_connector
*connector
;
11374 struct drm_connector_state
*connector_state
;
11377 for_each_new_connector_in_state(state
, connector
, connector_state
, i
) {
11378 if (connector_state
->crtc
!= &crtc
->base
)
11382 to_intel_encoder(connector_state
->best_encoder
);
11383 if (!encoders_cloneable(encoder
, source_encoder
))
11390 static int icl_add_linked_planes(struct intel_atomic_state
*state
)
11392 struct intel_plane
*plane
, *linked
;
11393 struct intel_plane_state
*plane_state
, *linked_plane_state
;
11396 for_each_new_intel_plane_in_state(state
, plane
, plane_state
, i
) {
11397 linked
= plane_state
->linked_plane
;
11402 linked_plane_state
= intel_atomic_get_plane_state(state
, linked
);
11403 if (IS_ERR(linked_plane_state
))
11404 return PTR_ERR(linked_plane_state
);
11406 WARN_ON(linked_plane_state
->linked_plane
!= plane
);
11407 WARN_ON(linked_plane_state
->slave
== plane_state
->slave
);
11413 static int icl_check_nv12_planes(struct intel_crtc_state
*crtc_state
)
11415 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
11416 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
11417 struct intel_atomic_state
*state
= to_intel_atomic_state(crtc_state
->base
.state
);
11418 struct intel_plane
*plane
, *linked
;
11419 struct intel_plane_state
*plane_state
;
11422 if (INTEL_GEN(dev_priv
) < 11)
11426 * Destroy all old plane links and make the slave plane invisible
11427 * in the crtc_state->active_planes mask.
11429 for_each_new_intel_plane_in_state(state
, plane
, plane_state
, i
) {
11430 if (plane
->pipe
!= crtc
->pipe
|| !plane_state
->linked_plane
)
11433 plane_state
->linked_plane
= NULL
;
11434 if (plane_state
->slave
&& !plane_state
->base
.visible
) {
11435 crtc_state
->active_planes
&= ~BIT(plane
->id
);
11436 crtc_state
->update_planes
|= BIT(plane
->id
);
11439 plane_state
->slave
= false;
11442 if (!crtc_state
->nv12_planes
)
11445 for_each_new_intel_plane_in_state(state
, plane
, plane_state
, i
) {
11446 struct intel_plane_state
*linked_state
= NULL
;
11448 if (plane
->pipe
!= crtc
->pipe
||
11449 !(crtc_state
->nv12_planes
& BIT(plane
->id
)))
11452 for_each_intel_plane_on_crtc(&dev_priv
->drm
, crtc
, linked
) {
11453 if (!icl_is_nv12_y_plane(linked
->id
))
11456 if (crtc_state
->active_planes
& BIT(linked
->id
))
11459 linked_state
= intel_atomic_get_plane_state(state
, linked
);
11460 if (IS_ERR(linked_state
))
11461 return PTR_ERR(linked_state
);
11466 if (!linked_state
) {
11467 DRM_DEBUG_KMS("Need %d free Y planes for planar YUV\n",
11468 hweight8(crtc_state
->nv12_planes
));
11473 plane_state
->linked_plane
= linked
;
11475 linked_state
->slave
= true;
11476 linked_state
->linked_plane
= plane
;
11477 crtc_state
->active_planes
|= BIT(linked
->id
);
11478 crtc_state
->update_planes
|= BIT(linked
->id
);
11479 DRM_DEBUG_KMS("Using %s as Y plane for %s\n", linked
->base
.name
, plane
->base
.name
);
11485 static int intel_crtc_atomic_check(struct drm_crtc
*crtc
,
11486 struct drm_crtc_state
*crtc_state
)
11488 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
11489 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11490 struct intel_crtc_state
*pipe_config
=
11491 to_intel_crtc_state(crtc_state
);
11493 bool mode_changed
= needs_modeset(crtc_state
);
11495 if (INTEL_GEN(dev_priv
) < 5 && !IS_G4X(dev_priv
) &&
11496 mode_changed
&& !crtc_state
->active
)
11497 pipe_config
->update_wm_post
= true;
11499 if (mode_changed
&& crtc_state
->enable
&&
11500 dev_priv
->display
.crtc_compute_clock
&&
11501 !WARN_ON(pipe_config
->shared_dpll
)) {
11502 ret
= dev_priv
->display
.crtc_compute_clock(intel_crtc
,
11508 if (mode_changed
|| pipe_config
->update_pipe
||
11509 crtc_state
->color_mgmt_changed
) {
11510 ret
= intel_color_check(pipe_config
);
11516 if (dev_priv
->display
.compute_pipe_wm
) {
11517 ret
= dev_priv
->display
.compute_pipe_wm(pipe_config
);
11519 DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
11524 if (dev_priv
->display
.compute_intermediate_wm
) {
11525 if (WARN_ON(!dev_priv
->display
.compute_pipe_wm
))
11529 * Calculate 'intermediate' watermarks that satisfy both the
11530 * old state and the new state. We can program these
11533 ret
= dev_priv
->display
.compute_intermediate_wm(pipe_config
);
11535 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
11540 if (INTEL_GEN(dev_priv
) >= 9) {
11541 if (mode_changed
|| pipe_config
->update_pipe
)
11542 ret
= skl_update_scaler_crtc(pipe_config
);
11545 ret
= icl_check_nv12_planes(pipe_config
);
11547 ret
= skl_check_pipe_max_pixel_rate(intel_crtc
,
11550 ret
= intel_atomic_setup_scalers(dev_priv
, intel_crtc
,
11554 if (HAS_IPS(dev_priv
))
11555 pipe_config
->ips_enabled
= hsw_compute_ips_config(pipe_config
);
11560 static const struct drm_crtc_helper_funcs intel_helper_funcs
= {
11561 .atomic_check
= intel_crtc_atomic_check
,
11564 static void intel_modeset_update_connector_atomic_state(struct drm_device
*dev
)
11566 struct intel_connector
*connector
;
11567 struct drm_connector_list_iter conn_iter
;
11569 drm_connector_list_iter_begin(dev
, &conn_iter
);
11570 for_each_intel_connector_iter(connector
, &conn_iter
) {
11571 if (connector
->base
.state
->crtc
)
11572 drm_connector_put(&connector
->base
);
11574 if (connector
->base
.encoder
) {
11575 connector
->base
.state
->best_encoder
=
11576 connector
->base
.encoder
;
11577 connector
->base
.state
->crtc
=
11578 connector
->base
.encoder
->crtc
;
11580 drm_connector_get(&connector
->base
);
11582 connector
->base
.state
->best_encoder
= NULL
;
11583 connector
->base
.state
->crtc
= NULL
;
11586 drm_connector_list_iter_end(&conn_iter
);
11590 compute_sink_pipe_bpp(const struct drm_connector_state
*conn_state
,
11591 struct intel_crtc_state
*pipe_config
)
11593 struct drm_connector
*connector
= conn_state
->connector
;
11594 const struct drm_display_info
*info
= &connector
->display_info
;
11597 switch (conn_state
->max_bpc
) {
11614 if (bpp
< pipe_config
->pipe_bpp
) {
11615 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Limiting display bpp to %d instead of "
11616 "EDID bpp %d, requested bpp %d, max platform bpp %d\n",
11617 connector
->base
.id
, connector
->name
,
11618 bpp
, 3 * info
->bpc
, 3 * conn_state
->max_requested_bpc
,
11619 pipe_config
->pipe_bpp
);
11621 pipe_config
->pipe_bpp
= bpp
;
11628 compute_baseline_pipe_bpp(struct intel_crtc
*crtc
,
11629 struct intel_crtc_state
*pipe_config
)
11631 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
11632 struct drm_atomic_state
*state
= pipe_config
->base
.state
;
11633 struct drm_connector
*connector
;
11634 struct drm_connector_state
*connector_state
;
11637 if ((IS_G4X(dev_priv
) || IS_VALLEYVIEW(dev_priv
) ||
11638 IS_CHERRYVIEW(dev_priv
)))
11640 else if (INTEL_GEN(dev_priv
) >= 5)
11645 pipe_config
->pipe_bpp
= bpp
;
11647 /* Clamp display bpp to connector max bpp */
11648 for_each_new_connector_in_state(state
, connector
, connector_state
, i
) {
11651 if (connector_state
->crtc
!= &crtc
->base
)
11654 ret
= compute_sink_pipe_bpp(connector_state
, pipe_config
);
11662 static void intel_dump_crtc_timings(const struct drm_display_mode
*mode
)
11664 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11665 "type: 0x%x flags: 0x%x\n",
11667 mode
->crtc_hdisplay
, mode
->crtc_hsync_start
,
11668 mode
->crtc_hsync_end
, mode
->crtc_htotal
,
11669 mode
->crtc_vdisplay
, mode
->crtc_vsync_start
,
11670 mode
->crtc_vsync_end
, mode
->crtc_vtotal
, mode
->type
, mode
->flags
);
11674 intel_dump_m_n_config(struct intel_crtc_state
*pipe_config
, char *id
,
11675 unsigned int lane_count
, struct intel_link_m_n
*m_n
)
11677 DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11679 m_n
->gmch_m
, m_n
->gmch_n
,
11680 m_n
->link_m
, m_n
->link_n
, m_n
->tu
);
11684 intel_dump_infoframe(struct drm_i915_private
*dev_priv
,
11685 const union hdmi_infoframe
*frame
)
11687 if ((drm_debug
& DRM_UT_KMS
) == 0)
11690 hdmi_infoframe_log(KERN_DEBUG
, dev_priv
->drm
.dev
, frame
);
11693 #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
11695 static const char * const output_type_str
[] = {
11696 OUTPUT_TYPE(UNUSED
),
11697 OUTPUT_TYPE(ANALOG
),
11701 OUTPUT_TYPE(TVOUT
),
11707 OUTPUT_TYPE(DP_MST
),
11712 static void snprintf_output_types(char *buf
, size_t len
,
11713 unsigned int output_types
)
11720 for (i
= 0; i
< ARRAY_SIZE(output_type_str
); i
++) {
11723 if ((output_types
& BIT(i
)) == 0)
11726 r
= snprintf(str
, len
, "%s%s",
11727 str
!= buf
? "," : "", output_type_str
[i
]);
11733 output_types
&= ~BIT(i
);
11736 WARN_ON_ONCE(output_types
!= 0);
11739 static const char * const output_format_str
[] = {
11740 [INTEL_OUTPUT_FORMAT_INVALID
] = "Invalid",
11741 [INTEL_OUTPUT_FORMAT_RGB
] = "RGB",
11742 [INTEL_OUTPUT_FORMAT_YCBCR420
] = "YCBCR4:2:0",
11743 [INTEL_OUTPUT_FORMAT_YCBCR444
] = "YCBCR4:4:4",
11746 static const char *output_formats(enum intel_output_format format
)
11748 if (format
>= ARRAY_SIZE(output_format_str
))
11749 format
= INTEL_OUTPUT_FORMAT_INVALID
;
11750 return output_format_str
[format
];
11753 static void intel_dump_pipe_config(struct intel_crtc
*crtc
,
11754 struct intel_crtc_state
*pipe_config
,
11755 const char *context
)
11757 struct drm_device
*dev
= crtc
->base
.dev
;
11758 struct drm_i915_private
*dev_priv
= to_i915(dev
);
11759 struct drm_plane
*plane
;
11760 struct intel_plane
*intel_plane
;
11761 struct intel_plane_state
*state
;
11762 struct drm_framebuffer
*fb
;
11765 DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n",
11766 crtc
->base
.base
.id
, crtc
->base
.name
, context
);
11768 snprintf_output_types(buf
, sizeof(buf
), pipe_config
->output_types
);
11769 DRM_DEBUG_KMS("output_types: %s (0x%x)\n",
11770 buf
, pipe_config
->output_types
);
11772 DRM_DEBUG_KMS("output format: %s\n",
11773 output_formats(pipe_config
->output_format
));
11775 DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
11776 transcoder_name(pipe_config
->cpu_transcoder
),
11777 pipe_config
->pipe_bpp
, pipe_config
->dither
);
11779 if (pipe_config
->has_pch_encoder
)
11780 intel_dump_m_n_config(pipe_config
, "fdi",
11781 pipe_config
->fdi_lanes
,
11782 &pipe_config
->fdi_m_n
);
11784 if (intel_crtc_has_dp_encoder(pipe_config
)) {
11785 intel_dump_m_n_config(pipe_config
, "dp m_n",
11786 pipe_config
->lane_count
, &pipe_config
->dp_m_n
);
11787 if (pipe_config
->has_drrs
)
11788 intel_dump_m_n_config(pipe_config
, "dp m2_n2",
11789 pipe_config
->lane_count
,
11790 &pipe_config
->dp_m2_n2
);
11793 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11794 pipe_config
->has_audio
, pipe_config
->has_infoframe
);
11796 DRM_DEBUG_KMS("infoframes enabled: 0x%x\n",
11797 pipe_config
->infoframes
.enable
);
11799 if (pipe_config
->infoframes
.enable
&
11800 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL
))
11801 DRM_DEBUG_KMS("GCP: 0x%x\n", pipe_config
->infoframes
.gcp
);
11802 if (pipe_config
->infoframes
.enable
&
11803 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI
))
11804 intel_dump_infoframe(dev_priv
, &pipe_config
->infoframes
.avi
);
11805 if (pipe_config
->infoframes
.enable
&
11806 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD
))
11807 intel_dump_infoframe(dev_priv
, &pipe_config
->infoframes
.spd
);
11808 if (pipe_config
->infoframes
.enable
&
11809 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR
))
11810 intel_dump_infoframe(dev_priv
, &pipe_config
->infoframes
.hdmi
);
11812 DRM_DEBUG_KMS("requested mode:\n");
11813 drm_mode_debug_printmodeline(&pipe_config
->base
.mode
);
11814 DRM_DEBUG_KMS("adjusted mode:\n");
11815 drm_mode_debug_printmodeline(&pipe_config
->base
.adjusted_mode
);
11816 intel_dump_crtc_timings(&pipe_config
->base
.adjusted_mode
);
11817 DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
11818 pipe_config
->port_clock
,
11819 pipe_config
->pipe_src_w
, pipe_config
->pipe_src_h
,
11820 pipe_config
->pixel_rate
);
11822 if (INTEL_GEN(dev_priv
) >= 9)
11823 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11825 pipe_config
->scaler_state
.scaler_users
,
11826 pipe_config
->scaler_state
.scaler_id
);
11828 if (HAS_GMCH(dev_priv
))
11829 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11830 pipe_config
->gmch_pfit
.control
,
11831 pipe_config
->gmch_pfit
.pgm_ratios
,
11832 pipe_config
->gmch_pfit
.lvds_border_bits
);
11834 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s, force thru: %s\n",
11835 pipe_config
->pch_pfit
.pos
,
11836 pipe_config
->pch_pfit
.size
,
11837 enableddisabled(pipe_config
->pch_pfit
.enabled
),
11838 yesno(pipe_config
->pch_pfit
.force_thru
));
11840 DRM_DEBUG_KMS("ips: %i, double wide: %i\n",
11841 pipe_config
->ips_enabled
, pipe_config
->double_wide
);
11843 intel_dpll_dump_hw_state(dev_priv
, &pipe_config
->dpll_hw_state
);
11845 DRM_DEBUG_KMS("planes on this crtc\n");
11846 list_for_each_entry(plane
, &dev
->mode_config
.plane_list
, head
) {
11847 struct drm_format_name_buf format_name
;
11848 intel_plane
= to_intel_plane(plane
);
11849 if (intel_plane
->pipe
!= crtc
->pipe
)
11852 state
= to_intel_plane_state(plane
->state
);
11853 fb
= state
->base
.fb
;
11855 DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
11856 plane
->base
.id
, plane
->name
, state
->scaler_id
);
11860 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n",
11861 plane
->base
.id
, plane
->name
,
11862 fb
->base
.id
, fb
->width
, fb
->height
,
11863 drm_get_format_name(fb
->format
->format
, &format_name
));
11864 if (INTEL_GEN(dev_priv
) >= 9)
11865 DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
11867 state
->base
.src
.x1
>> 16,
11868 state
->base
.src
.y1
>> 16,
11869 drm_rect_width(&state
->base
.src
) >> 16,
11870 drm_rect_height(&state
->base
.src
) >> 16,
11871 state
->base
.dst
.x1
, state
->base
.dst
.y1
,
11872 drm_rect_width(&state
->base
.dst
),
11873 drm_rect_height(&state
->base
.dst
));
11877 static bool check_digital_port_conflicts(struct drm_atomic_state
*state
)
11879 struct drm_device
*dev
= state
->dev
;
11880 struct drm_connector
*connector
;
11881 struct drm_connector_list_iter conn_iter
;
11882 unsigned int used_ports
= 0;
11883 unsigned int used_mst_ports
= 0;
11887 * Walk the connector list instead of the encoder
11888 * list to detect the problem on ddi platforms
11889 * where there's just one encoder per digital port.
11891 drm_connector_list_iter_begin(dev
, &conn_iter
);
11892 drm_for_each_connector_iter(connector
, &conn_iter
) {
11893 struct drm_connector_state
*connector_state
;
11894 struct intel_encoder
*encoder
;
11896 connector_state
= drm_atomic_get_new_connector_state(state
, connector
);
11897 if (!connector_state
)
11898 connector_state
= connector
->state
;
11900 if (!connector_state
->best_encoder
)
11903 encoder
= to_intel_encoder(connector_state
->best_encoder
);
11905 WARN_ON(!connector_state
->crtc
);
11907 switch (encoder
->type
) {
11908 unsigned int port_mask
;
11909 case INTEL_OUTPUT_DDI
:
11910 if (WARN_ON(!HAS_DDI(to_i915(dev
))))
11912 /* else: fall through */
11913 case INTEL_OUTPUT_DP
:
11914 case INTEL_OUTPUT_HDMI
:
11915 case INTEL_OUTPUT_EDP
:
11916 port_mask
= 1 << encoder
->port
;
11918 /* the same port mustn't appear more than once */
11919 if (used_ports
& port_mask
)
11922 used_ports
|= port_mask
;
11924 case INTEL_OUTPUT_DP_MST
:
11926 1 << encoder
->port
;
11932 drm_connector_list_iter_end(&conn_iter
);
11934 /* can't mix MST and SST/HDMI on the same port */
11935 if (used_ports
& used_mst_ports
)
11942 clear_intel_crtc_state(struct intel_crtc_state
*crtc_state
)
11944 struct drm_i915_private
*dev_priv
=
11945 to_i915(crtc_state
->base
.crtc
->dev
);
11946 struct intel_crtc_state
*saved_state
;
11948 saved_state
= kzalloc(sizeof(*saved_state
), GFP_KERNEL
);
11952 /* FIXME: before the switch to atomic started, a new pipe_config was
11953 * kzalloc'd. Code that depends on any field being zero should be
11954 * fixed, so that the crtc_state can be safely duplicated. For now,
11955 * only fields that are know to not cause problems are preserved. */
11957 saved_state
->scaler_state
= crtc_state
->scaler_state
;
11958 saved_state
->shared_dpll
= crtc_state
->shared_dpll
;
11959 saved_state
->dpll_hw_state
= crtc_state
->dpll_hw_state
;
11960 saved_state
->crc_enabled
= crtc_state
->crc_enabled
;
11961 if (IS_G4X(dev_priv
) ||
11962 IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
11963 saved_state
->wm
= crtc_state
->wm
;
11965 /* Keep base drm_crtc_state intact, only clear our extended struct */
11966 BUILD_BUG_ON(offsetof(struct intel_crtc_state
, base
));
11967 memcpy(&crtc_state
->base
+ 1, &saved_state
->base
+ 1,
11968 sizeof(*crtc_state
) - sizeof(crtc_state
->base
));
11970 kfree(saved_state
);
11975 intel_modeset_pipe_config(struct drm_crtc
*crtc
,
11976 struct intel_crtc_state
*pipe_config
)
11978 struct drm_atomic_state
*state
= pipe_config
->base
.state
;
11979 struct intel_encoder
*encoder
;
11980 struct drm_connector
*connector
;
11981 struct drm_connector_state
*connector_state
;
11986 ret
= clear_intel_crtc_state(pipe_config
);
11990 pipe_config
->cpu_transcoder
=
11991 (enum transcoder
) to_intel_crtc(crtc
)->pipe
;
11994 * Sanitize sync polarity flags based on requested ones. If neither
11995 * positive or negative polarity is requested, treat this as meaning
11996 * negative polarity.
11998 if (!(pipe_config
->base
.adjusted_mode
.flags
&
11999 (DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NHSYNC
)))
12000 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_NHSYNC
;
12002 if (!(pipe_config
->base
.adjusted_mode
.flags
&
12003 (DRM_MODE_FLAG_PVSYNC
| DRM_MODE_FLAG_NVSYNC
)))
12004 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_NVSYNC
;
12006 ret
= compute_baseline_pipe_bpp(to_intel_crtc(crtc
),
12011 base_bpp
= pipe_config
->pipe_bpp
;
12014 * Determine the real pipe dimensions. Note that stereo modes can
12015 * increase the actual pipe size due to the frame doubling and
12016 * insertion of additional space for blanks between the frame. This
12017 * is stored in the crtc timings. We use the requested mode to do this
12018 * computation to clearly distinguish it from the adjusted mode, which
12019 * can be changed by the connectors in the below retry loop.
12021 drm_mode_get_hv_timing(&pipe_config
->base
.mode
,
12022 &pipe_config
->pipe_src_w
,
12023 &pipe_config
->pipe_src_h
);
12025 for_each_new_connector_in_state(state
, connector
, connector_state
, i
) {
12026 if (connector_state
->crtc
!= crtc
)
12029 encoder
= to_intel_encoder(connector_state
->best_encoder
);
12031 if (!check_single_encoder_cloning(state
, to_intel_crtc(crtc
), encoder
)) {
12032 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
12037 * Determine output_types before calling the .compute_config()
12038 * hooks so that the hooks can use this information safely.
12040 if (encoder
->compute_output_type
)
12041 pipe_config
->output_types
|=
12042 BIT(encoder
->compute_output_type(encoder
, pipe_config
,
12045 pipe_config
->output_types
|= BIT(encoder
->type
);
12049 /* Ensure the port clock defaults are reset when retrying. */
12050 pipe_config
->port_clock
= 0;
12051 pipe_config
->pixel_multiplier
= 1;
12053 /* Fill in default crtc timings, allow encoders to overwrite them. */
12054 drm_mode_set_crtcinfo(&pipe_config
->base
.adjusted_mode
,
12055 CRTC_STEREO_DOUBLE
);
12057 /* Pass our mode to the connectors and the CRTC to give them a chance to
12058 * adjust it according to limitations or connector properties, and also
12059 * a chance to reject the mode entirely.
12061 for_each_new_connector_in_state(state
, connector
, connector_state
, i
) {
12062 if (connector_state
->crtc
!= crtc
)
12065 encoder
= to_intel_encoder(connector_state
->best_encoder
);
12066 ret
= encoder
->compute_config(encoder
, pipe_config
,
12069 if (ret
!= -EDEADLK
)
12070 DRM_DEBUG_KMS("Encoder config failure: %d\n",
12076 /* Set default port clock if not overwritten by the encoder. Needs to be
12077 * done afterwards in case the encoder adjusts the mode. */
12078 if (!pipe_config
->port_clock
)
12079 pipe_config
->port_clock
= pipe_config
->base
.adjusted_mode
.crtc_clock
12080 * pipe_config
->pixel_multiplier
;
12082 ret
= intel_crtc_compute_config(to_intel_crtc(crtc
), pipe_config
);
12083 if (ret
== -EDEADLK
)
12086 DRM_DEBUG_KMS("CRTC fixup failed\n");
12090 if (ret
== RETRY
) {
12091 if (WARN(!retry
, "loop in pipe configuration computation\n"))
12094 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12096 goto encoder_retry
;
12099 /* Dithering seems to not pass-through bits correctly when it should, so
12100 * only enable it on 6bpc panels and when its not a compliance
12101 * test requesting 6bpc video pattern.
12103 pipe_config
->dither
= (pipe_config
->pipe_bpp
== 6*3) &&
12104 !pipe_config
->dither_force_disable
;
12105 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12106 base_bpp
, pipe_config
->pipe_bpp
, pipe_config
->dither
);
12111 static bool intel_fuzzy_clock_check(int clock1
, int clock2
)
12115 if (clock1
== clock2
)
12118 if (!clock1
|| !clock2
)
12121 diff
= abs(clock1
- clock2
);
12123 if (((((diff
+ clock1
+ clock2
) * 100)) / (clock1
+ clock2
)) < 105)
12130 intel_compare_m_n(unsigned int m
, unsigned int n
,
12131 unsigned int m2
, unsigned int n2
,
12134 if (m
== m2
&& n
== n2
)
12137 if (exact
|| !m
|| !n
|| !m2
|| !n2
)
12140 BUILD_BUG_ON(DATA_LINK_M_N_MASK
> INT_MAX
);
12147 } else if (n
< n2
) {
12157 return intel_fuzzy_clock_check(m
, m2
);
12161 intel_compare_link_m_n(const struct intel_link_m_n
*m_n
,
12162 struct intel_link_m_n
*m2_n2
,
12165 if (m_n
->tu
== m2_n2
->tu
&&
12166 intel_compare_m_n(m_n
->gmch_m
, m_n
->gmch_n
,
12167 m2_n2
->gmch_m
, m2_n2
->gmch_n
, !adjust
) &&
12168 intel_compare_m_n(m_n
->link_m
, m_n
->link_n
,
12169 m2_n2
->link_m
, m2_n2
->link_n
, !adjust
)) {
12180 intel_compare_infoframe(const union hdmi_infoframe
*a
,
12181 const union hdmi_infoframe
*b
)
12183 return memcmp(a
, b
, sizeof(*a
)) == 0;
12187 pipe_config_infoframe_err(struct drm_i915_private
*dev_priv
,
12188 bool adjust
, const char *name
,
12189 const union hdmi_infoframe
*a
,
12190 const union hdmi_infoframe
*b
)
12193 if ((drm_debug
& DRM_UT_KMS
) == 0)
12196 drm_dbg(DRM_UT_KMS
, "mismatch in %s infoframe", name
);
12197 drm_dbg(DRM_UT_KMS
, "expected:");
12198 hdmi_infoframe_log(KERN_DEBUG
, dev_priv
->drm
.dev
, a
);
12199 drm_dbg(DRM_UT_KMS
, "found");
12200 hdmi_infoframe_log(KERN_DEBUG
, dev_priv
->drm
.dev
, b
);
12202 drm_err("mismatch in %s infoframe", name
);
12203 drm_err("expected:");
12204 hdmi_infoframe_log(KERN_ERR
, dev_priv
->drm
.dev
, a
);
12206 hdmi_infoframe_log(KERN_ERR
, dev_priv
->drm
.dev
, b
);
12210 static void __printf(3, 4)
12211 pipe_config_err(bool adjust
, const char *name
, const char *format
, ...)
12213 struct va_format vaf
;
12216 va_start(args
, format
);
12221 drm_dbg(DRM_UT_KMS
, "mismatch in %s %pV", name
, &vaf
);
12223 drm_err("mismatch in %s %pV", name
, &vaf
);
12228 static bool fastboot_enabled(struct drm_i915_private
*dev_priv
)
12230 if (i915_modparams
.fastboot
!= -1)
12231 return i915_modparams
.fastboot
;
12233 /* Enable fastboot by default on Skylake and newer */
12234 if (INTEL_GEN(dev_priv
) >= 9)
12237 /* Enable fastboot by default on VLV and CHV */
12238 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
12241 /* Disabled by default on all others */
12246 intel_pipe_config_compare(struct drm_i915_private
*dev_priv
,
12247 struct intel_crtc_state
*current_config
,
12248 struct intel_crtc_state
*pipe_config
,
12252 bool fixup_inherited
= adjust
&&
12253 (current_config
->base
.mode
.private_flags
& I915_MODE_FLAG_INHERITED
) &&
12254 !(pipe_config
->base
.mode
.private_flags
& I915_MODE_FLAG_INHERITED
);
12256 if (fixup_inherited
&& !fastboot_enabled(dev_priv
)) {
12257 DRM_DEBUG_KMS("initial modeset and fastboot not set\n");
12261 #define PIPE_CONF_CHECK_X(name) do { \
12262 if (current_config->name != pipe_config->name) { \
12263 pipe_config_err(adjust, __stringify(name), \
12264 "(expected 0x%08x, found 0x%08x)\n", \
12265 current_config->name, \
12266 pipe_config->name); \
12271 #define PIPE_CONF_CHECK_I(name) do { \
12272 if (current_config->name != pipe_config->name) { \
12273 pipe_config_err(adjust, __stringify(name), \
12274 "(expected %i, found %i)\n", \
12275 current_config->name, \
12276 pipe_config->name); \
12281 #define PIPE_CONF_CHECK_BOOL(name) do { \
12282 if (current_config->name != pipe_config->name) { \
12283 pipe_config_err(adjust, __stringify(name), \
12284 "(expected %s, found %s)\n", \
12285 yesno(current_config->name), \
12286 yesno(pipe_config->name)); \
12292 * Checks state where we only read out the enabling, but not the entire
12293 * state itself (like full infoframes or ELD for audio). These states
12294 * require a full modeset on bootup to fix up.
12296 #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \
12297 if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \
12298 PIPE_CONF_CHECK_BOOL(name); \
12300 pipe_config_err(adjust, __stringify(name), \
12301 "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)\n", \
12302 yesno(current_config->name), \
12303 yesno(pipe_config->name)); \
12308 #define PIPE_CONF_CHECK_P(name) do { \
12309 if (current_config->name != pipe_config->name) { \
12310 pipe_config_err(adjust, __stringify(name), \
12311 "(expected %p, found %p)\n", \
12312 current_config->name, \
12313 pipe_config->name); \
12318 #define PIPE_CONF_CHECK_M_N(name) do { \
12319 if (!intel_compare_link_m_n(¤t_config->name, \
12320 &pipe_config->name,\
12322 pipe_config_err(adjust, __stringify(name), \
12323 "(expected tu %i gmch %i/%i link %i/%i, " \
12324 "found tu %i, gmch %i/%i link %i/%i)\n", \
12325 current_config->name.tu, \
12326 current_config->name.gmch_m, \
12327 current_config->name.gmch_n, \
12328 current_config->name.link_m, \
12329 current_config->name.link_n, \
12330 pipe_config->name.tu, \
12331 pipe_config->name.gmch_m, \
12332 pipe_config->name.gmch_n, \
12333 pipe_config->name.link_m, \
12334 pipe_config->name.link_n); \
12339 /* This is required for BDW+ where there is only one set of registers for
12340 * switching between high and low RR.
12341 * This macro can be used whenever a comparison has to be made between one
12342 * hw state and multiple sw state variables.
12344 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) do { \
12345 if (!intel_compare_link_m_n(¤t_config->name, \
12346 &pipe_config->name, adjust) && \
12347 !intel_compare_link_m_n(¤t_config->alt_name, \
12348 &pipe_config->name, adjust)) { \
12349 pipe_config_err(adjust, __stringify(name), \
12350 "(expected tu %i gmch %i/%i link %i/%i, " \
12351 "or tu %i gmch %i/%i link %i/%i, " \
12352 "found tu %i, gmch %i/%i link %i/%i)\n", \
12353 current_config->name.tu, \
12354 current_config->name.gmch_m, \
12355 current_config->name.gmch_n, \
12356 current_config->name.link_m, \
12357 current_config->name.link_n, \
12358 current_config->alt_name.tu, \
12359 current_config->alt_name.gmch_m, \
12360 current_config->alt_name.gmch_n, \
12361 current_config->alt_name.link_m, \
12362 current_config->alt_name.link_n, \
12363 pipe_config->name.tu, \
12364 pipe_config->name.gmch_m, \
12365 pipe_config->name.gmch_n, \
12366 pipe_config->name.link_m, \
12367 pipe_config->name.link_n); \
12372 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \
12373 if ((current_config->name ^ pipe_config->name) & (mask)) { \
12374 pipe_config_err(adjust, __stringify(name), \
12375 "(%x) (expected %i, found %i)\n", \
12377 current_config->name & (mask), \
12378 pipe_config->name & (mask)); \
12383 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) do { \
12384 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12385 pipe_config_err(adjust, __stringify(name), \
12386 "(expected %i, found %i)\n", \
12387 current_config->name, \
12388 pipe_config->name); \
12393 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \
12394 if (!intel_compare_infoframe(¤t_config->infoframes.name, \
12395 &pipe_config->infoframes.name)) { \
12396 pipe_config_infoframe_err(dev_priv, adjust, __stringify(name), \
12397 ¤t_config->infoframes.name, \
12398 &pipe_config->infoframes.name); \
12403 #define PIPE_CONF_QUIRK(quirk) \
12404 ((current_config->quirks | pipe_config->quirks) & (quirk))
12406 PIPE_CONF_CHECK_I(cpu_transcoder
);
12408 PIPE_CONF_CHECK_BOOL(has_pch_encoder
);
12409 PIPE_CONF_CHECK_I(fdi_lanes
);
12410 PIPE_CONF_CHECK_M_N(fdi_m_n
);
12412 PIPE_CONF_CHECK_I(lane_count
);
12413 PIPE_CONF_CHECK_X(lane_lat_optim_mask
);
12415 if (INTEL_GEN(dev_priv
) < 8) {
12416 PIPE_CONF_CHECK_M_N(dp_m_n
);
12418 if (current_config
->has_drrs
)
12419 PIPE_CONF_CHECK_M_N(dp_m2_n2
);
12421 PIPE_CONF_CHECK_M_N_ALT(dp_m_n
, dp_m2_n2
);
12423 PIPE_CONF_CHECK_X(output_types
);
12425 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hdisplay
);
12426 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_htotal
);
12427 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hblank_start
);
12428 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hblank_end
);
12429 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hsync_start
);
12430 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hsync_end
);
12432 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vdisplay
);
12433 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vtotal
);
12434 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vblank_start
);
12435 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vblank_end
);
12436 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vsync_start
);
12437 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vsync_end
);
12439 PIPE_CONF_CHECK_I(pixel_multiplier
);
12440 PIPE_CONF_CHECK_I(output_format
);
12441 PIPE_CONF_CHECK_BOOL(has_hdmi_sink
);
12442 if ((INTEL_GEN(dev_priv
) < 8 && !IS_HASWELL(dev_priv
)) ||
12443 IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
12444 PIPE_CONF_CHECK_BOOL(limited_color_range
);
12446 PIPE_CONF_CHECK_BOOL(hdmi_scrambling
);
12447 PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio
);
12448 PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_infoframe
);
12450 PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio
);
12452 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
12453 DRM_MODE_FLAG_INTERLACE
);
12455 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS
)) {
12456 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
12457 DRM_MODE_FLAG_PHSYNC
);
12458 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
12459 DRM_MODE_FLAG_NHSYNC
);
12460 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
12461 DRM_MODE_FLAG_PVSYNC
);
12462 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
12463 DRM_MODE_FLAG_NVSYNC
);
12466 PIPE_CONF_CHECK_X(gmch_pfit
.control
);
12467 /* pfit ratios are autocomputed by the hw on gen4+ */
12468 if (INTEL_GEN(dev_priv
) < 4)
12469 PIPE_CONF_CHECK_X(gmch_pfit
.pgm_ratios
);
12470 PIPE_CONF_CHECK_X(gmch_pfit
.lvds_border_bits
);
12473 * Changing the EDP transcoder input mux
12474 * (A_ONOFF vs. A_ON) requires a full modeset.
12476 PIPE_CONF_CHECK_BOOL(pch_pfit
.force_thru
);
12479 PIPE_CONF_CHECK_I(pipe_src_w
);
12480 PIPE_CONF_CHECK_I(pipe_src_h
);
12482 PIPE_CONF_CHECK_BOOL(pch_pfit
.enabled
);
12483 if (current_config
->pch_pfit
.enabled
) {
12484 PIPE_CONF_CHECK_X(pch_pfit
.pos
);
12485 PIPE_CONF_CHECK_X(pch_pfit
.size
);
12488 PIPE_CONF_CHECK_I(scaler_state
.scaler_id
);
12489 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate
);
12491 PIPE_CONF_CHECK_X(gamma_mode
);
12492 if (IS_CHERRYVIEW(dev_priv
))
12493 PIPE_CONF_CHECK_X(cgm_mode
);
12495 PIPE_CONF_CHECK_X(csc_mode
);
12496 PIPE_CONF_CHECK_BOOL(gamma_enable
);
12497 PIPE_CONF_CHECK_BOOL(csc_enable
);
12500 PIPE_CONF_CHECK_BOOL(double_wide
);
12502 PIPE_CONF_CHECK_P(shared_dpll
);
12503 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll
);
12504 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll_md
);
12505 PIPE_CONF_CHECK_X(dpll_hw_state
.fp0
);
12506 PIPE_CONF_CHECK_X(dpll_hw_state
.fp1
);
12507 PIPE_CONF_CHECK_X(dpll_hw_state
.wrpll
);
12508 PIPE_CONF_CHECK_X(dpll_hw_state
.spll
);
12509 PIPE_CONF_CHECK_X(dpll_hw_state
.ctrl1
);
12510 PIPE_CONF_CHECK_X(dpll_hw_state
.cfgcr1
);
12511 PIPE_CONF_CHECK_X(dpll_hw_state
.cfgcr2
);
12512 PIPE_CONF_CHECK_X(dpll_hw_state
.cfgcr0
);
12513 PIPE_CONF_CHECK_X(dpll_hw_state
.ebb0
);
12514 PIPE_CONF_CHECK_X(dpll_hw_state
.ebb4
);
12515 PIPE_CONF_CHECK_X(dpll_hw_state
.pll0
);
12516 PIPE_CONF_CHECK_X(dpll_hw_state
.pll1
);
12517 PIPE_CONF_CHECK_X(dpll_hw_state
.pll2
);
12518 PIPE_CONF_CHECK_X(dpll_hw_state
.pll3
);
12519 PIPE_CONF_CHECK_X(dpll_hw_state
.pll6
);
12520 PIPE_CONF_CHECK_X(dpll_hw_state
.pll8
);
12521 PIPE_CONF_CHECK_X(dpll_hw_state
.pll9
);
12522 PIPE_CONF_CHECK_X(dpll_hw_state
.pll10
);
12523 PIPE_CONF_CHECK_X(dpll_hw_state
.pcsdw12
);
12524 PIPE_CONF_CHECK_X(dpll_hw_state
.mg_refclkin_ctl
);
12525 PIPE_CONF_CHECK_X(dpll_hw_state
.mg_clktop2_coreclkctl1
);
12526 PIPE_CONF_CHECK_X(dpll_hw_state
.mg_clktop2_hsclkctl
);
12527 PIPE_CONF_CHECK_X(dpll_hw_state
.mg_pll_div0
);
12528 PIPE_CONF_CHECK_X(dpll_hw_state
.mg_pll_div1
);
12529 PIPE_CONF_CHECK_X(dpll_hw_state
.mg_pll_lf
);
12530 PIPE_CONF_CHECK_X(dpll_hw_state
.mg_pll_frac_lock
);
12531 PIPE_CONF_CHECK_X(dpll_hw_state
.mg_pll_ssc
);
12532 PIPE_CONF_CHECK_X(dpll_hw_state
.mg_pll_bias
);
12533 PIPE_CONF_CHECK_X(dpll_hw_state
.mg_pll_tdc_coldst_bias
);
12535 PIPE_CONF_CHECK_X(dsi_pll
.ctrl
);
12536 PIPE_CONF_CHECK_X(dsi_pll
.div
);
12538 if (IS_G4X(dev_priv
) || INTEL_GEN(dev_priv
) >= 5)
12539 PIPE_CONF_CHECK_I(pipe_bpp
);
12541 PIPE_CONF_CHECK_CLOCK_FUZZY(base
.adjusted_mode
.crtc_clock
);
12542 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock
);
12544 PIPE_CONF_CHECK_I(min_voltage_level
);
12546 PIPE_CONF_CHECK_X(infoframes
.enable
);
12547 PIPE_CONF_CHECK_X(infoframes
.gcp
);
12548 PIPE_CONF_CHECK_INFOFRAME(avi
);
12549 PIPE_CONF_CHECK_INFOFRAME(spd
);
12550 PIPE_CONF_CHECK_INFOFRAME(hdmi
);
12552 #undef PIPE_CONF_CHECK_X
12553 #undef PIPE_CONF_CHECK_I
12554 #undef PIPE_CONF_CHECK_BOOL
12555 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE
12556 #undef PIPE_CONF_CHECK_P
12557 #undef PIPE_CONF_CHECK_FLAGS
12558 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12559 #undef PIPE_CONF_QUIRK
12564 static void intel_pipe_config_sanity_check(struct drm_i915_private
*dev_priv
,
12565 const struct intel_crtc_state
*pipe_config
)
12567 if (pipe_config
->has_pch_encoder
) {
12568 int fdi_dotclock
= intel_dotclock_calculate(intel_fdi_link_freq(dev_priv
, pipe_config
),
12569 &pipe_config
->fdi_m_n
);
12570 int dotclock
= pipe_config
->base
.adjusted_mode
.crtc_clock
;
12573 * FDI already provided one idea for the dotclock.
12574 * Yell if the encoder disagrees.
12576 WARN(!intel_fuzzy_clock_check(fdi_dotclock
, dotclock
),
12577 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12578 fdi_dotclock
, dotclock
);
12582 static void verify_wm_state(struct drm_crtc
*crtc
,
12583 struct drm_crtc_state
*new_state
)
12585 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
12586 struct skl_hw_state
{
12587 struct skl_ddb_entry ddb_y
[I915_MAX_PLANES
];
12588 struct skl_ddb_entry ddb_uv
[I915_MAX_PLANES
];
12589 struct skl_ddb_allocation ddb
;
12590 struct skl_pipe_wm wm
;
12592 struct skl_ddb_allocation
*sw_ddb
;
12593 struct skl_pipe_wm
*sw_wm
;
12594 struct skl_ddb_entry
*hw_ddb_entry
, *sw_ddb_entry
;
12595 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
12596 const enum pipe pipe
= intel_crtc
->pipe
;
12597 int plane
, level
, max_level
= ilk_wm_max_level(dev_priv
);
12599 if (INTEL_GEN(dev_priv
) < 9 || !new_state
->active
)
12602 hw
= kzalloc(sizeof(*hw
), GFP_KERNEL
);
12606 skl_pipe_wm_get_hw_state(intel_crtc
, &hw
->wm
);
12607 sw_wm
= &to_intel_crtc_state(new_state
)->wm
.skl
.optimal
;
12609 skl_pipe_ddb_get_hw_state(intel_crtc
, hw
->ddb_y
, hw
->ddb_uv
);
12611 skl_ddb_get_hw_state(dev_priv
, &hw
->ddb
);
12612 sw_ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
12614 if (INTEL_GEN(dev_priv
) >= 11 &&
12615 hw
->ddb
.enabled_slices
!= sw_ddb
->enabled_slices
)
12616 DRM_ERROR("mismatch in DBUF Slices (expected %u, got %u)\n",
12617 sw_ddb
->enabled_slices
,
12618 hw
->ddb
.enabled_slices
);
12621 for_each_universal_plane(dev_priv
, pipe
, plane
) {
12622 struct skl_plane_wm
*hw_plane_wm
, *sw_plane_wm
;
12624 hw_plane_wm
= &hw
->wm
.planes
[plane
];
12625 sw_plane_wm
= &sw_wm
->planes
[plane
];
12628 for (level
= 0; level
<= max_level
; level
++) {
12629 if (skl_wm_level_equals(&hw_plane_wm
->wm
[level
],
12630 &sw_plane_wm
->wm
[level
]))
12633 DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
12634 pipe_name(pipe
), plane
+ 1, level
,
12635 sw_plane_wm
->wm
[level
].plane_en
,
12636 sw_plane_wm
->wm
[level
].plane_res_b
,
12637 sw_plane_wm
->wm
[level
].plane_res_l
,
12638 hw_plane_wm
->wm
[level
].plane_en
,
12639 hw_plane_wm
->wm
[level
].plane_res_b
,
12640 hw_plane_wm
->wm
[level
].plane_res_l
);
12643 if (!skl_wm_level_equals(&hw_plane_wm
->trans_wm
,
12644 &sw_plane_wm
->trans_wm
)) {
12645 DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
12646 pipe_name(pipe
), plane
+ 1,
12647 sw_plane_wm
->trans_wm
.plane_en
,
12648 sw_plane_wm
->trans_wm
.plane_res_b
,
12649 sw_plane_wm
->trans_wm
.plane_res_l
,
12650 hw_plane_wm
->trans_wm
.plane_en
,
12651 hw_plane_wm
->trans_wm
.plane_res_b
,
12652 hw_plane_wm
->trans_wm
.plane_res_l
);
12656 hw_ddb_entry
= &hw
->ddb_y
[plane
];
12657 sw_ddb_entry
= &to_intel_crtc_state(new_state
)->wm
.skl
.plane_ddb_y
[plane
];
12659 if (!skl_ddb_entry_equal(hw_ddb_entry
, sw_ddb_entry
)) {
12660 DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
12661 pipe_name(pipe
), plane
+ 1,
12662 sw_ddb_entry
->start
, sw_ddb_entry
->end
,
12663 hw_ddb_entry
->start
, hw_ddb_entry
->end
);
12669 * If the cursor plane isn't active, we may not have updated it's ddb
12670 * allocation. In that case since the ddb allocation will be updated
12671 * once the plane becomes visible, we can skip this check
12674 struct skl_plane_wm
*hw_plane_wm
, *sw_plane_wm
;
12676 hw_plane_wm
= &hw
->wm
.planes
[PLANE_CURSOR
];
12677 sw_plane_wm
= &sw_wm
->planes
[PLANE_CURSOR
];
12680 for (level
= 0; level
<= max_level
; level
++) {
12681 if (skl_wm_level_equals(&hw_plane_wm
->wm
[level
],
12682 &sw_plane_wm
->wm
[level
]))
12685 DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
12686 pipe_name(pipe
), level
,
12687 sw_plane_wm
->wm
[level
].plane_en
,
12688 sw_plane_wm
->wm
[level
].plane_res_b
,
12689 sw_plane_wm
->wm
[level
].plane_res_l
,
12690 hw_plane_wm
->wm
[level
].plane_en
,
12691 hw_plane_wm
->wm
[level
].plane_res_b
,
12692 hw_plane_wm
->wm
[level
].plane_res_l
);
12695 if (!skl_wm_level_equals(&hw_plane_wm
->trans_wm
,
12696 &sw_plane_wm
->trans_wm
)) {
12697 DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
12699 sw_plane_wm
->trans_wm
.plane_en
,
12700 sw_plane_wm
->trans_wm
.plane_res_b
,
12701 sw_plane_wm
->trans_wm
.plane_res_l
,
12702 hw_plane_wm
->trans_wm
.plane_en
,
12703 hw_plane_wm
->trans_wm
.plane_res_b
,
12704 hw_plane_wm
->trans_wm
.plane_res_l
);
12708 hw_ddb_entry
= &hw
->ddb_y
[PLANE_CURSOR
];
12709 sw_ddb_entry
= &to_intel_crtc_state(new_state
)->wm
.skl
.plane_ddb_y
[PLANE_CURSOR
];
12711 if (!skl_ddb_entry_equal(hw_ddb_entry
, sw_ddb_entry
)) {
12712 DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
12714 sw_ddb_entry
->start
, sw_ddb_entry
->end
,
12715 hw_ddb_entry
->start
, hw_ddb_entry
->end
);
12723 verify_connector_state(struct drm_device
*dev
,
12724 struct drm_atomic_state
*state
,
12725 struct drm_crtc
*crtc
)
12727 struct drm_connector
*connector
;
12728 struct drm_connector_state
*new_conn_state
;
12731 for_each_new_connector_in_state(state
, connector
, new_conn_state
, i
) {
12732 struct drm_encoder
*encoder
= connector
->encoder
;
12733 struct drm_crtc_state
*crtc_state
= NULL
;
12735 if (new_conn_state
->crtc
!= crtc
)
12739 crtc_state
= drm_atomic_get_new_crtc_state(state
, new_conn_state
->crtc
);
12741 intel_connector_verify_state(crtc_state
, new_conn_state
);
12743 I915_STATE_WARN(new_conn_state
->best_encoder
!= encoder
,
12744 "connector's atomic encoder doesn't match legacy encoder\n");
12749 verify_encoder_state(struct drm_device
*dev
, struct drm_atomic_state
*state
)
12751 struct intel_encoder
*encoder
;
12752 struct drm_connector
*connector
;
12753 struct drm_connector_state
*old_conn_state
, *new_conn_state
;
12756 for_each_intel_encoder(dev
, encoder
) {
12757 bool enabled
= false, found
= false;
12760 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12761 encoder
->base
.base
.id
,
12762 encoder
->base
.name
);
12764 for_each_oldnew_connector_in_state(state
, connector
, old_conn_state
,
12765 new_conn_state
, i
) {
12766 if (old_conn_state
->best_encoder
== &encoder
->base
)
12769 if (new_conn_state
->best_encoder
!= &encoder
->base
)
12771 found
= enabled
= true;
12773 I915_STATE_WARN(new_conn_state
->crtc
!=
12774 encoder
->base
.crtc
,
12775 "connector's crtc doesn't match encoder crtc\n");
12781 I915_STATE_WARN(!!encoder
->base
.crtc
!= enabled
,
12782 "encoder's enabled state mismatch "
12783 "(expected %i, found %i)\n",
12784 !!encoder
->base
.crtc
, enabled
);
12786 if (!encoder
->base
.crtc
) {
12789 active
= encoder
->get_hw_state(encoder
, &pipe
);
12790 I915_STATE_WARN(active
,
12791 "encoder detached but still enabled on pipe %c.\n",
12798 verify_crtc_state(struct drm_crtc
*crtc
,
12799 struct drm_crtc_state
*old_crtc_state
,
12800 struct drm_crtc_state
*new_crtc_state
)
12802 struct drm_device
*dev
= crtc
->dev
;
12803 struct drm_i915_private
*dev_priv
= to_i915(dev
);
12804 struct intel_encoder
*encoder
;
12805 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
12806 struct intel_crtc_state
*pipe_config
, *sw_config
;
12807 struct drm_atomic_state
*old_state
;
12810 old_state
= old_crtc_state
->state
;
12811 __drm_atomic_helper_crtc_destroy_state(old_crtc_state
);
12812 pipe_config
= to_intel_crtc_state(old_crtc_state
);
12813 memset(pipe_config
, 0, sizeof(*pipe_config
));
12814 pipe_config
->base
.crtc
= crtc
;
12815 pipe_config
->base
.state
= old_state
;
12817 DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc
->base
.id
, crtc
->name
);
12819 active
= dev_priv
->display
.get_pipe_config(intel_crtc
, pipe_config
);
12821 /* we keep both pipes enabled on 830 */
12822 if (IS_I830(dev_priv
))
12823 active
= new_crtc_state
->active
;
12825 I915_STATE_WARN(new_crtc_state
->active
!= active
,
12826 "crtc active state doesn't match with hw state "
12827 "(expected %i, found %i)\n", new_crtc_state
->active
, active
);
12829 I915_STATE_WARN(intel_crtc
->active
!= new_crtc_state
->active
,
12830 "transitional active state does not match atomic hw state "
12831 "(expected %i, found %i)\n", new_crtc_state
->active
, intel_crtc
->active
);
12833 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
12836 active
= encoder
->get_hw_state(encoder
, &pipe
);
12837 I915_STATE_WARN(active
!= new_crtc_state
->active
,
12838 "[ENCODER:%i] active %i with crtc active %i\n",
12839 encoder
->base
.base
.id
, active
, new_crtc_state
->active
);
12841 I915_STATE_WARN(active
&& intel_crtc
->pipe
!= pipe
,
12842 "Encoder connected to wrong pipe %c\n",
12846 encoder
->get_config(encoder
, pipe_config
);
12849 intel_crtc_compute_pixel_rate(pipe_config
);
12851 if (!new_crtc_state
->active
)
12854 intel_pipe_config_sanity_check(dev_priv
, pipe_config
);
12856 sw_config
= to_intel_crtc_state(new_crtc_state
);
12857 if (!intel_pipe_config_compare(dev_priv
, sw_config
,
12858 pipe_config
, false)) {
12859 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12860 intel_dump_pipe_config(intel_crtc
, pipe_config
,
12862 intel_dump_pipe_config(intel_crtc
, sw_config
,
12868 intel_verify_planes(struct intel_atomic_state
*state
)
12870 struct intel_plane
*plane
;
12871 const struct intel_plane_state
*plane_state
;
12874 for_each_new_intel_plane_in_state(state
, plane
,
12876 assert_plane(plane
, plane_state
->slave
||
12877 plane_state
->base
.visible
);
12881 verify_single_dpll_state(struct drm_i915_private
*dev_priv
,
12882 struct intel_shared_dpll
*pll
,
12883 struct drm_crtc
*crtc
,
12884 struct drm_crtc_state
*new_state
)
12886 struct intel_dpll_hw_state dpll_hw_state
;
12887 unsigned int crtc_mask
;
12890 memset(&dpll_hw_state
, 0, sizeof(dpll_hw_state
));
12892 DRM_DEBUG_KMS("%s\n", pll
->info
->name
);
12894 active
= pll
->info
->funcs
->get_hw_state(dev_priv
, pll
, &dpll_hw_state
);
12896 if (!(pll
->info
->flags
& INTEL_DPLL_ALWAYS_ON
)) {
12897 I915_STATE_WARN(!pll
->on
&& pll
->active_mask
,
12898 "pll in active use but not on in sw tracking\n");
12899 I915_STATE_WARN(pll
->on
&& !pll
->active_mask
,
12900 "pll is on but not used by any active crtc\n");
12901 I915_STATE_WARN(pll
->on
!= active
,
12902 "pll on state mismatch (expected %i, found %i)\n",
12907 I915_STATE_WARN(pll
->active_mask
& ~pll
->state
.crtc_mask
,
12908 "more active pll users than references: %x vs %x\n",
12909 pll
->active_mask
, pll
->state
.crtc_mask
);
12914 crtc_mask
= drm_crtc_mask(crtc
);
12916 if (new_state
->active
)
12917 I915_STATE_WARN(!(pll
->active_mask
& crtc_mask
),
12918 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
12919 pipe_name(drm_crtc_index(crtc
)), pll
->active_mask
);
12921 I915_STATE_WARN(pll
->active_mask
& crtc_mask
,
12922 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
12923 pipe_name(drm_crtc_index(crtc
)), pll
->active_mask
);
12925 I915_STATE_WARN(!(pll
->state
.crtc_mask
& crtc_mask
),
12926 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
12927 crtc_mask
, pll
->state
.crtc_mask
);
12929 I915_STATE_WARN(pll
->on
&& memcmp(&pll
->state
.hw_state
,
12931 sizeof(dpll_hw_state
)),
12932 "pll hw state mismatch\n");
12936 verify_shared_dpll_state(struct drm_device
*dev
, struct drm_crtc
*crtc
,
12937 struct drm_crtc_state
*old_crtc_state
,
12938 struct drm_crtc_state
*new_crtc_state
)
12940 struct drm_i915_private
*dev_priv
= to_i915(dev
);
12941 struct intel_crtc_state
*old_state
= to_intel_crtc_state(old_crtc_state
);
12942 struct intel_crtc_state
*new_state
= to_intel_crtc_state(new_crtc_state
);
12944 if (new_state
->shared_dpll
)
12945 verify_single_dpll_state(dev_priv
, new_state
->shared_dpll
, crtc
, new_crtc_state
);
12947 if (old_state
->shared_dpll
&&
12948 old_state
->shared_dpll
!= new_state
->shared_dpll
) {
12949 unsigned int crtc_mask
= drm_crtc_mask(crtc
);
12950 struct intel_shared_dpll
*pll
= old_state
->shared_dpll
;
12952 I915_STATE_WARN(pll
->active_mask
& crtc_mask
,
12953 "pll active mismatch (didn't expect pipe %c in active mask)\n",
12954 pipe_name(drm_crtc_index(crtc
)));
12955 I915_STATE_WARN(pll
->state
.crtc_mask
& crtc_mask
,
12956 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
12957 pipe_name(drm_crtc_index(crtc
)));
12962 intel_modeset_verify_crtc(struct drm_crtc
*crtc
,
12963 struct drm_atomic_state
*state
,
12964 struct drm_crtc_state
*old_state
,
12965 struct drm_crtc_state
*new_state
)
12967 if (!needs_modeset(new_state
) &&
12968 !to_intel_crtc_state(new_state
)->update_pipe
)
12971 verify_wm_state(crtc
, new_state
);
12972 verify_connector_state(crtc
->dev
, state
, crtc
);
12973 verify_crtc_state(crtc
, old_state
, new_state
);
12974 verify_shared_dpll_state(crtc
->dev
, crtc
, old_state
, new_state
);
12978 verify_disabled_dpll_state(struct drm_device
*dev
)
12980 struct drm_i915_private
*dev_priv
= to_i915(dev
);
12983 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++)
12984 verify_single_dpll_state(dev_priv
, &dev_priv
->shared_dplls
[i
], NULL
, NULL
);
12988 intel_modeset_verify_disabled(struct drm_device
*dev
,
12989 struct drm_atomic_state
*state
)
12991 verify_encoder_state(dev
, state
);
12992 verify_connector_state(dev
, state
, NULL
);
12993 verify_disabled_dpll_state(dev
);
12996 static void update_scanline_offset(const struct intel_crtc_state
*crtc_state
)
12998 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
12999 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
13002 * The scanline counter increments at the leading edge of hsync.
13004 * On most platforms it starts counting from vtotal-1 on the
13005 * first active line. That means the scanline counter value is
13006 * always one less than what we would expect. Ie. just after
13007 * start of vblank, which also occurs at start of hsync (on the
13008 * last active line), the scanline counter will read vblank_start-1.
13010 * On gen2 the scanline counter starts counting from 1 instead
13011 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13012 * to keep the value positive), instead of adding one.
13014 * On HSW+ the behaviour of the scanline counter depends on the output
13015 * type. For DP ports it behaves like most other platforms, but on HDMI
13016 * there's an extra 1 line difference. So we need to add two instead of
13017 * one to the value.
13019 * On VLV/CHV DSI the scanline counter would appear to increment
13020 * approx. 1/3 of a scanline before start of vblank. Unfortunately
13021 * that means we can't tell whether we're in vblank or not while
13022 * we're on that particular line. We must still set scanline_offset
13023 * to 1 so that the vblank timestamps come out correct when we query
13024 * the scanline counter from within the vblank interrupt handler.
13025 * However if queried just before the start of vblank we'll get an
13026 * answer that's slightly in the future.
13028 if (IS_GEN(dev_priv
, 2)) {
13029 const struct drm_display_mode
*adjusted_mode
= &crtc_state
->base
.adjusted_mode
;
13032 vtotal
= adjusted_mode
->crtc_vtotal
;
13033 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
13036 crtc
->scanline_offset
= vtotal
- 1;
13037 } else if (HAS_DDI(dev_priv
) &&
13038 intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_HDMI
)) {
13039 crtc
->scanline_offset
= 2;
13041 crtc
->scanline_offset
= 1;
13044 static void intel_modeset_clear_plls(struct drm_atomic_state
*state
)
13046 struct drm_device
*dev
= state
->dev
;
13047 struct drm_i915_private
*dev_priv
= to_i915(dev
);
13048 struct drm_crtc
*crtc
;
13049 struct drm_crtc_state
*old_crtc_state
, *new_crtc_state
;
13052 if (!dev_priv
->display
.crtc_compute_clock
)
13055 for_each_oldnew_crtc_in_state(state
, crtc
, old_crtc_state
, new_crtc_state
, i
) {
13056 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
13057 struct intel_shared_dpll
*old_dpll
=
13058 to_intel_crtc_state(old_crtc_state
)->shared_dpll
;
13060 if (!needs_modeset(new_crtc_state
))
13063 to_intel_crtc_state(new_crtc_state
)->shared_dpll
= NULL
;
13068 intel_release_shared_dpll(old_dpll
, intel_crtc
, state
);
13073 * This implements the workaround described in the "notes" section of the mode
13074 * set sequence documentation. When going from no pipes or single pipe to
13075 * multiple pipes, and planes are enabled after the pipe, we need to wait at
13076 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13078 static int haswell_mode_set_planes_workaround(struct drm_atomic_state
*state
)
13080 struct drm_crtc_state
*crtc_state
;
13081 struct intel_crtc
*intel_crtc
;
13082 struct drm_crtc
*crtc
;
13083 struct intel_crtc_state
*first_crtc_state
= NULL
;
13084 struct intel_crtc_state
*other_crtc_state
= NULL
;
13085 enum pipe first_pipe
= INVALID_PIPE
, enabled_pipe
= INVALID_PIPE
;
13088 /* look at all crtc's that are going to be enabled in during modeset */
13089 for_each_new_crtc_in_state(state
, crtc
, crtc_state
, i
) {
13090 intel_crtc
= to_intel_crtc(crtc
);
13092 if (!crtc_state
->active
|| !needs_modeset(crtc_state
))
13095 if (first_crtc_state
) {
13096 other_crtc_state
= to_intel_crtc_state(crtc_state
);
13099 first_crtc_state
= to_intel_crtc_state(crtc_state
);
13100 first_pipe
= intel_crtc
->pipe
;
13104 /* No workaround needed? */
13105 if (!first_crtc_state
)
13108 /* w/a possibly needed, check how many crtc's are already enabled. */
13109 for_each_intel_crtc(state
->dev
, intel_crtc
) {
13110 struct intel_crtc_state
*pipe_config
;
13112 pipe_config
= intel_atomic_get_crtc_state(state
, intel_crtc
);
13113 if (IS_ERR(pipe_config
))
13114 return PTR_ERR(pipe_config
);
13116 pipe_config
->hsw_workaround_pipe
= INVALID_PIPE
;
13118 if (!pipe_config
->base
.active
||
13119 needs_modeset(&pipe_config
->base
))
13122 /* 2 or more enabled crtcs means no need for w/a */
13123 if (enabled_pipe
!= INVALID_PIPE
)
13126 enabled_pipe
= intel_crtc
->pipe
;
13129 if (enabled_pipe
!= INVALID_PIPE
)
13130 first_crtc_state
->hsw_workaround_pipe
= enabled_pipe
;
13131 else if (other_crtc_state
)
13132 other_crtc_state
->hsw_workaround_pipe
= first_pipe
;
13137 static int intel_lock_all_pipes(struct drm_atomic_state
*state
)
13139 struct drm_crtc
*crtc
;
13141 /* Add all pipes to the state */
13142 for_each_crtc(state
->dev
, crtc
) {
13143 struct drm_crtc_state
*crtc_state
;
13145 crtc_state
= drm_atomic_get_crtc_state(state
, crtc
);
13146 if (IS_ERR(crtc_state
))
13147 return PTR_ERR(crtc_state
);
13153 static int intel_modeset_all_pipes(struct drm_atomic_state
*state
)
13155 struct drm_crtc
*crtc
;
13158 * Add all pipes to the state, and force
13159 * a modeset on all the active ones.
13161 for_each_crtc(state
->dev
, crtc
) {
13162 struct drm_crtc_state
*crtc_state
;
13165 crtc_state
= drm_atomic_get_crtc_state(state
, crtc
);
13166 if (IS_ERR(crtc_state
))
13167 return PTR_ERR(crtc_state
);
13169 if (!crtc_state
->active
|| needs_modeset(crtc_state
))
13172 crtc_state
->mode_changed
= true;
13174 ret
= drm_atomic_add_affected_connectors(state
, crtc
);
13178 ret
= drm_atomic_add_affected_planes(state
, crtc
);
13186 static int intel_modeset_checks(struct drm_atomic_state
*state
)
13188 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
13189 struct drm_i915_private
*dev_priv
= to_i915(state
->dev
);
13190 struct drm_crtc
*crtc
;
13191 struct drm_crtc_state
*old_crtc_state
, *new_crtc_state
;
13194 if (!check_digital_port_conflicts(state
)) {
13195 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13199 /* keep the current setting */
13200 if (!intel_state
->cdclk
.force_min_cdclk_changed
)
13201 intel_state
->cdclk
.force_min_cdclk
=
13202 dev_priv
->cdclk
.force_min_cdclk
;
13204 intel_state
->modeset
= true;
13205 intel_state
->active_crtcs
= dev_priv
->active_crtcs
;
13206 intel_state
->cdclk
.logical
= dev_priv
->cdclk
.logical
;
13207 intel_state
->cdclk
.actual
= dev_priv
->cdclk
.actual
;
13208 intel_state
->cdclk
.pipe
= INVALID_PIPE
;
13210 for_each_oldnew_crtc_in_state(state
, crtc
, old_crtc_state
, new_crtc_state
, i
) {
13211 if (new_crtc_state
->active
)
13212 intel_state
->active_crtcs
|= 1 << i
;
13214 intel_state
->active_crtcs
&= ~(1 << i
);
13216 if (old_crtc_state
->active
!= new_crtc_state
->active
)
13217 intel_state
->active_pipe_changes
|= drm_crtc_mask(crtc
);
13221 * See if the config requires any additional preparation, e.g.
13222 * to adjust global state with pipes off. We need to do this
13223 * here so we can get the modeset_pipe updated config for the new
13224 * mode set on this crtc. For other crtcs we need to use the
13225 * adjusted_mode bits in the crtc directly.
13227 if (dev_priv
->display
.modeset_calc_cdclk
) {
13230 ret
= dev_priv
->display
.modeset_calc_cdclk(state
);
13235 * Writes to dev_priv->cdclk.logical must protected by
13236 * holding all the crtc locks, even if we don't end up
13237 * touching the hardware
13239 if (intel_cdclk_changed(&dev_priv
->cdclk
.logical
,
13240 &intel_state
->cdclk
.logical
)) {
13241 ret
= intel_lock_all_pipes(state
);
13246 if (is_power_of_2(intel_state
->active_crtcs
)) {
13247 struct drm_crtc
*crtc
;
13248 struct drm_crtc_state
*crtc_state
;
13250 pipe
= ilog2(intel_state
->active_crtcs
);
13251 crtc
= &intel_get_crtc_for_pipe(dev_priv
, pipe
)->base
;
13252 crtc_state
= drm_atomic_get_new_crtc_state(state
, crtc
);
13253 if (crtc_state
&& needs_modeset(crtc_state
))
13254 pipe
= INVALID_PIPE
;
13256 pipe
= INVALID_PIPE
;
13259 /* All pipes must be switched off while we change the cdclk. */
13260 if (pipe
!= INVALID_PIPE
&&
13261 intel_cdclk_needs_cd2x_update(dev_priv
,
13262 &dev_priv
->cdclk
.actual
,
13263 &intel_state
->cdclk
.actual
)) {
13264 ret
= intel_lock_all_pipes(state
);
13268 intel_state
->cdclk
.pipe
= pipe
;
13269 } else if (intel_cdclk_needs_modeset(&dev_priv
->cdclk
.actual
,
13270 &intel_state
->cdclk
.actual
)) {
13271 ret
= intel_modeset_all_pipes(state
);
13275 intel_state
->cdclk
.pipe
= INVALID_PIPE
;
13278 DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n",
13279 intel_state
->cdclk
.logical
.cdclk
,
13280 intel_state
->cdclk
.actual
.cdclk
);
13281 DRM_DEBUG_KMS("New voltage level calculated to be logical %u, actual %u\n",
13282 intel_state
->cdclk
.logical
.voltage_level
,
13283 intel_state
->cdclk
.actual
.voltage_level
);
13286 intel_modeset_clear_plls(state
);
13288 if (IS_HASWELL(dev_priv
))
13289 return haswell_mode_set_planes_workaround(state
);
13295 * Handle calculation of various watermark data at the end of the atomic check
13296 * phase. The code here should be run after the per-crtc and per-plane 'check'
13297 * handlers to ensure that all derived state has been updated.
13299 static int calc_watermark_data(struct intel_atomic_state
*state
)
13301 struct drm_device
*dev
= state
->base
.dev
;
13302 struct drm_i915_private
*dev_priv
= to_i915(dev
);
13304 /* Is there platform-specific watermark information to calculate? */
13305 if (dev_priv
->display
.compute_global_watermarks
)
13306 return dev_priv
->display
.compute_global_watermarks(state
);
13312 * intel_atomic_check - validate state object
13314 * @state: state to validate
13316 static int intel_atomic_check(struct drm_device
*dev
,
13317 struct drm_atomic_state
*state
)
13319 struct drm_i915_private
*dev_priv
= to_i915(dev
);
13320 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
13321 struct drm_crtc
*crtc
;
13322 struct drm_crtc_state
*old_crtc_state
, *crtc_state
;
13324 bool any_ms
= intel_state
->cdclk
.force_min_cdclk_changed
;
13326 /* Catch I915_MODE_FLAG_INHERITED */
13327 for_each_oldnew_crtc_in_state(state
, crtc
, old_crtc_state
,
13329 if (crtc_state
->mode
.private_flags
!=
13330 old_crtc_state
->mode
.private_flags
)
13331 crtc_state
->mode_changed
= true;
13334 ret
= drm_atomic_helper_check_modeset(dev
, state
);
13338 for_each_oldnew_crtc_in_state(state
, crtc
, old_crtc_state
, crtc_state
, i
) {
13339 struct intel_crtc_state
*pipe_config
=
13340 to_intel_crtc_state(crtc_state
);
13342 if (!needs_modeset(crtc_state
))
13345 if (!crtc_state
->enable
) {
13350 ret
= intel_modeset_pipe_config(crtc
, pipe_config
);
13351 if (ret
== -EDEADLK
)
13354 intel_dump_pipe_config(to_intel_crtc(crtc
),
13355 pipe_config
, "[failed]");
13359 if (intel_pipe_config_compare(dev_priv
,
13360 to_intel_crtc_state(old_crtc_state
),
13361 pipe_config
, true)) {
13362 crtc_state
->mode_changed
= false;
13363 pipe_config
->update_pipe
= true;
13366 if (needs_modeset(crtc_state
))
13369 intel_dump_pipe_config(to_intel_crtc(crtc
), pipe_config
,
13370 needs_modeset(crtc_state
) ?
13371 "[modeset]" : "[fastset]");
13374 ret
= drm_dp_mst_atomic_check(state
);
13379 ret
= intel_modeset_checks(state
);
13384 intel_state
->cdclk
.logical
= dev_priv
->cdclk
.logical
;
13387 ret
= icl_add_linked_planes(intel_state
);
13391 ret
= drm_atomic_helper_check_planes(dev
, state
);
13395 intel_fbc_choose_crtc(dev_priv
, intel_state
);
13396 return calc_watermark_data(intel_state
);
13399 static int intel_atomic_prepare_commit(struct drm_device
*dev
,
13400 struct drm_atomic_state
*state
)
13402 return drm_atomic_helper_prepare_planes(dev
, state
);
13405 u32
intel_crtc_get_vblank_counter(struct intel_crtc
*crtc
)
13407 struct drm_device
*dev
= crtc
->base
.dev
;
13408 struct drm_vblank_crtc
*vblank
= &dev
->vblank
[drm_crtc_index(&crtc
->base
)];
13410 if (!vblank
->max_vblank_count
)
13411 return (u32
)drm_crtc_accurate_vblank_count(&crtc
->base
);
13413 return dev
->driver
->get_vblank_counter(dev
, crtc
->pipe
);
13416 static void intel_update_crtc(struct drm_crtc
*crtc
,
13417 struct drm_atomic_state
*state
,
13418 struct drm_crtc_state
*old_crtc_state
,
13419 struct drm_crtc_state
*new_crtc_state
)
13421 struct drm_device
*dev
= crtc
->dev
;
13422 struct drm_i915_private
*dev_priv
= to_i915(dev
);
13423 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
13424 struct intel_crtc_state
*pipe_config
= to_intel_crtc_state(new_crtc_state
);
13425 bool modeset
= needs_modeset(new_crtc_state
);
13426 struct intel_plane_state
*new_plane_state
=
13427 intel_atomic_get_new_plane_state(to_intel_atomic_state(state
),
13428 to_intel_plane(crtc
->primary
));
13431 update_scanline_offset(pipe_config
);
13432 dev_priv
->display
.crtc_enable(pipe_config
, state
);
13434 /* vblanks work again, re-enable pipe CRC. */
13435 intel_crtc_enable_pipe_crc(intel_crtc
);
13437 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state
),
13440 if (pipe_config
->update_pipe
)
13441 intel_encoders_update_pipe(crtc
, pipe_config
, state
);
13444 if (pipe_config
->update_pipe
&& !pipe_config
->enable_fbc
)
13445 intel_fbc_disable(intel_crtc
);
13446 else if (new_plane_state
)
13447 intel_fbc_enable(intel_crtc
, pipe_config
, new_plane_state
);
13449 intel_begin_crtc_commit(to_intel_atomic_state(state
), intel_crtc
);
13451 if (INTEL_GEN(dev_priv
) >= 9)
13452 skl_update_planes_on_crtc(to_intel_atomic_state(state
), intel_crtc
);
13454 i9xx_update_planes_on_crtc(to_intel_atomic_state(state
), intel_crtc
);
13456 intel_finish_crtc_commit(to_intel_atomic_state(state
), intel_crtc
);
13459 static void intel_update_crtcs(struct drm_atomic_state
*state
)
13461 struct drm_crtc
*crtc
;
13462 struct drm_crtc_state
*old_crtc_state
, *new_crtc_state
;
13465 for_each_oldnew_crtc_in_state(state
, crtc
, old_crtc_state
, new_crtc_state
, i
) {
13466 if (!new_crtc_state
->active
)
13469 intel_update_crtc(crtc
, state
, old_crtc_state
,
13474 static void skl_update_crtcs(struct drm_atomic_state
*state
)
13476 struct drm_i915_private
*dev_priv
= to_i915(state
->dev
);
13477 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
13478 struct drm_crtc
*crtc
;
13479 struct intel_crtc
*intel_crtc
;
13480 struct drm_crtc_state
*old_crtc_state
, *new_crtc_state
;
13481 struct intel_crtc_state
*cstate
;
13482 unsigned int updated
= 0;
13486 u8 hw_enabled_slices
= dev_priv
->wm
.skl_hw
.ddb
.enabled_slices
;
13487 u8 required_slices
= intel_state
->wm_results
.ddb
.enabled_slices
;
13488 struct skl_ddb_entry entries
[I915_MAX_PIPES
] = {};
13490 for_each_oldnew_crtc_in_state(state
, crtc
, old_crtc_state
, new_crtc_state
, i
)
13491 /* ignore allocations for crtc's that have been turned off. */
13492 if (new_crtc_state
->active
)
13493 entries
[i
] = to_intel_crtc_state(old_crtc_state
)->wm
.skl
.ddb
;
13495 /* If 2nd DBuf slice required, enable it here */
13496 if (INTEL_GEN(dev_priv
) >= 11 && required_slices
> hw_enabled_slices
)
13497 icl_dbuf_slices_update(dev_priv
, required_slices
);
13500 * Whenever the number of active pipes changes, we need to make sure we
13501 * update the pipes in the right order so that their ddb allocations
13502 * never overlap with eachother inbetween CRTC updates. Otherwise we'll
13503 * cause pipe underruns and other bad stuff.
13508 for_each_oldnew_crtc_in_state(state
, crtc
, old_crtc_state
, new_crtc_state
, i
) {
13509 bool vbl_wait
= false;
13510 unsigned int cmask
= drm_crtc_mask(crtc
);
13512 intel_crtc
= to_intel_crtc(crtc
);
13513 cstate
= to_intel_crtc_state(new_crtc_state
);
13514 pipe
= intel_crtc
->pipe
;
13516 if (updated
& cmask
|| !cstate
->base
.active
)
13519 if (skl_ddb_allocation_overlaps(&cstate
->wm
.skl
.ddb
,
13521 INTEL_INFO(dev_priv
)->num_pipes
, i
))
13525 entries
[i
] = cstate
->wm
.skl
.ddb
;
13528 * If this is an already active pipe, it's DDB changed,
13529 * and this isn't the last pipe that needs updating
13530 * then we need to wait for a vblank to pass for the
13531 * new ddb allocation to take effect.
13533 if (!skl_ddb_entry_equal(&cstate
->wm
.skl
.ddb
,
13534 &to_intel_crtc_state(old_crtc_state
)->wm
.skl
.ddb
) &&
13535 !new_crtc_state
->active_changed
&&
13536 intel_state
->wm_results
.dirty_pipes
!= updated
)
13539 intel_update_crtc(crtc
, state
, old_crtc_state
,
13543 intel_wait_for_vblank(dev_priv
, pipe
);
13547 } while (progress
);
13549 /* If 2nd DBuf slice is no more required disable it */
13550 if (INTEL_GEN(dev_priv
) >= 11 && required_slices
< hw_enabled_slices
)
13551 icl_dbuf_slices_update(dev_priv
, required_slices
);
13554 static void intel_atomic_helper_free_state(struct drm_i915_private
*dev_priv
)
13556 struct intel_atomic_state
*state
, *next
;
13557 struct llist_node
*freed
;
13559 freed
= llist_del_all(&dev_priv
->atomic_helper
.free_list
);
13560 llist_for_each_entry_safe(state
, next
, freed
, freed
)
13561 drm_atomic_state_put(&state
->base
);
13564 static void intel_atomic_helper_free_state_worker(struct work_struct
*work
)
13566 struct drm_i915_private
*dev_priv
=
13567 container_of(work
, typeof(*dev_priv
), atomic_helper
.free_work
);
13569 intel_atomic_helper_free_state(dev_priv
);
13572 static void intel_atomic_commit_fence_wait(struct intel_atomic_state
*intel_state
)
13574 struct wait_queue_entry wait_fence
, wait_reset
;
13575 struct drm_i915_private
*dev_priv
= to_i915(intel_state
->base
.dev
);
13577 init_wait_entry(&wait_fence
, 0);
13578 init_wait_entry(&wait_reset
, 0);
13580 prepare_to_wait(&intel_state
->commit_ready
.wait
,
13581 &wait_fence
, TASK_UNINTERRUPTIBLE
);
13582 prepare_to_wait(&dev_priv
->gpu_error
.wait_queue
,
13583 &wait_reset
, TASK_UNINTERRUPTIBLE
);
13586 if (i915_sw_fence_done(&intel_state
->commit_ready
)
13587 || test_bit(I915_RESET_MODESET
, &dev_priv
->gpu_error
.flags
))
13592 finish_wait(&intel_state
->commit_ready
.wait
, &wait_fence
);
13593 finish_wait(&dev_priv
->gpu_error
.wait_queue
, &wait_reset
);
13596 static void intel_atomic_cleanup_work(struct work_struct
*work
)
13598 struct drm_atomic_state
*state
=
13599 container_of(work
, struct drm_atomic_state
, commit_work
);
13600 struct drm_i915_private
*i915
= to_i915(state
->dev
);
13602 drm_atomic_helper_cleanup_planes(&i915
->drm
, state
);
13603 drm_atomic_helper_commit_cleanup_done(state
);
13604 drm_atomic_state_put(state
);
13606 intel_atomic_helper_free_state(i915
);
13609 static void intel_atomic_commit_tail(struct drm_atomic_state
*state
)
13611 struct drm_device
*dev
= state
->dev
;
13612 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
13613 struct drm_i915_private
*dev_priv
= to_i915(dev
);
13614 struct drm_crtc_state
*old_crtc_state
, *new_crtc_state
;
13615 struct intel_crtc_state
*new_intel_crtc_state
, *old_intel_crtc_state
;
13616 struct drm_crtc
*crtc
;
13617 struct intel_crtc
*intel_crtc
;
13618 u64 put_domains
[I915_MAX_PIPES
] = {};
13619 intel_wakeref_t wakeref
= 0;
13622 intel_atomic_commit_fence_wait(intel_state
);
13624 drm_atomic_helper_wait_for_dependencies(state
);
13626 if (intel_state
->modeset
)
13627 wakeref
= intel_display_power_get(dev_priv
, POWER_DOMAIN_MODESET
);
13629 for_each_oldnew_crtc_in_state(state
, crtc
, old_crtc_state
, new_crtc_state
, i
) {
13630 old_intel_crtc_state
= to_intel_crtc_state(old_crtc_state
);
13631 new_intel_crtc_state
= to_intel_crtc_state(new_crtc_state
);
13632 intel_crtc
= to_intel_crtc(crtc
);
13634 if (needs_modeset(new_crtc_state
) ||
13635 to_intel_crtc_state(new_crtc_state
)->update_pipe
) {
13637 put_domains
[intel_crtc
->pipe
] =
13638 modeset_get_crtc_power_domains(crtc
,
13639 new_intel_crtc_state
);
13642 if (!needs_modeset(new_crtc_state
))
13645 intel_pre_plane_update(old_intel_crtc_state
, new_intel_crtc_state
);
13647 if (old_crtc_state
->active
) {
13648 intel_crtc_disable_planes(intel_state
, intel_crtc
);
13651 * We need to disable pipe CRC before disabling the pipe,
13652 * or we race against vblank off.
13654 intel_crtc_disable_pipe_crc(intel_crtc
);
13656 dev_priv
->display
.crtc_disable(old_intel_crtc_state
, state
);
13657 intel_crtc
->active
= false;
13658 intel_fbc_disable(intel_crtc
);
13659 intel_disable_shared_dpll(old_intel_crtc_state
);
13662 * Underruns don't always raise
13663 * interrupts, so check manually.
13665 intel_check_cpu_fifo_underruns(dev_priv
);
13666 intel_check_pch_fifo_underruns(dev_priv
);
13668 /* FIXME unify this for all platforms */
13669 if (!new_crtc_state
->active
&&
13670 !HAS_GMCH(dev_priv
) &&
13671 dev_priv
->display
.initial_watermarks
)
13672 dev_priv
->display
.initial_watermarks(intel_state
,
13673 new_intel_crtc_state
);
13677 /* FIXME: Eventually get rid of our intel_crtc->config pointer */
13678 for_each_new_crtc_in_state(state
, crtc
, new_crtc_state
, i
)
13679 to_intel_crtc(crtc
)->config
= to_intel_crtc_state(new_crtc_state
);
13681 if (intel_state
->modeset
) {
13682 drm_atomic_helper_update_legacy_modeset_state(state
->dev
, state
);
13684 intel_set_cdclk_pre_plane_update(dev_priv
,
13685 &intel_state
->cdclk
.actual
,
13686 &dev_priv
->cdclk
.actual
,
13687 intel_state
->cdclk
.pipe
);
13690 * SKL workaround: bspec recommends we disable the SAGV when we
13691 * have more then one pipe enabled
13693 if (!intel_can_enable_sagv(state
))
13694 intel_disable_sagv(dev_priv
);
13696 intel_modeset_verify_disabled(dev
, state
);
13699 /* Complete the events for pipes that have now been disabled */
13700 for_each_new_crtc_in_state(state
, crtc
, new_crtc_state
, i
) {
13701 bool modeset
= needs_modeset(new_crtc_state
);
13703 /* Complete events for now disable pipes here. */
13704 if (modeset
&& !new_crtc_state
->active
&& new_crtc_state
->event
) {
13705 spin_lock_irq(&dev
->event_lock
);
13706 drm_crtc_send_vblank_event(crtc
, new_crtc_state
->event
);
13707 spin_unlock_irq(&dev
->event_lock
);
13709 new_crtc_state
->event
= NULL
;
13713 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13714 dev_priv
->display
.update_crtcs(state
);
13716 if (intel_state
->modeset
)
13717 intel_set_cdclk_post_plane_update(dev_priv
,
13718 &intel_state
->cdclk
.actual
,
13719 &dev_priv
->cdclk
.actual
,
13720 intel_state
->cdclk
.pipe
);
13722 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
13723 * already, but still need the state for the delayed optimization. To
13725 * - wrap the optimization/post_plane_update stuff into a per-crtc work.
13726 * - schedule that vblank worker _before_ calling hw_done
13727 * - at the start of commit_tail, cancel it _synchrously
13728 * - switch over to the vblank wait helper in the core after that since
13729 * we don't need out special handling any more.
13731 drm_atomic_helper_wait_for_flip_done(dev
, state
);
13733 for_each_new_crtc_in_state(state
, crtc
, new_crtc_state
, i
) {
13734 new_intel_crtc_state
= to_intel_crtc_state(new_crtc_state
);
13736 if (new_crtc_state
->active
&&
13737 !needs_modeset(new_crtc_state
) &&
13738 (new_intel_crtc_state
->base
.color_mgmt_changed
||
13739 new_intel_crtc_state
->update_pipe
))
13740 intel_color_load_luts(new_intel_crtc_state
);
13744 * Now that the vblank has passed, we can go ahead and program the
13745 * optimal watermarks on platforms that need two-step watermark
13748 * TODO: Move this (and other cleanup) to an async worker eventually.
13750 for_each_new_crtc_in_state(state
, crtc
, new_crtc_state
, i
) {
13751 new_intel_crtc_state
= to_intel_crtc_state(new_crtc_state
);
13753 if (dev_priv
->display
.optimize_watermarks
)
13754 dev_priv
->display
.optimize_watermarks(intel_state
,
13755 new_intel_crtc_state
);
13758 for_each_oldnew_crtc_in_state(state
, crtc
, old_crtc_state
, new_crtc_state
, i
) {
13759 intel_post_plane_update(to_intel_crtc_state(old_crtc_state
));
13761 if (put_domains
[i
])
13762 modeset_put_power_domains(dev_priv
, put_domains
[i
]);
13764 intel_modeset_verify_crtc(crtc
, state
, old_crtc_state
, new_crtc_state
);
13767 if (intel_state
->modeset
)
13768 intel_verify_planes(intel_state
);
13770 if (intel_state
->modeset
&& intel_can_enable_sagv(state
))
13771 intel_enable_sagv(dev_priv
);
13773 drm_atomic_helper_commit_hw_done(state
);
13775 if (intel_state
->modeset
) {
13776 /* As one of the primary mmio accessors, KMS has a high
13777 * likelihood of triggering bugs in unclaimed access. After we
13778 * finish modesetting, see if an error has been flagged, and if
13779 * so enable debugging for the next modeset - and hope we catch
13782 intel_uncore_arm_unclaimed_mmio_detection(&dev_priv
->uncore
);
13783 intel_display_power_put(dev_priv
, POWER_DOMAIN_MODESET
, wakeref
);
13787 * Defer the cleanup of the old state to a separate worker to not
13788 * impede the current task (userspace for blocking modesets) that
13789 * are executed inline. For out-of-line asynchronous modesets/flips,
13790 * deferring to a new worker seems overkill, but we would place a
13791 * schedule point (cond_resched()) here anyway to keep latencies
13794 INIT_WORK(&state
->commit_work
, intel_atomic_cleanup_work
);
13795 queue_work(system_highpri_wq
, &state
->commit_work
);
13798 static void intel_atomic_commit_work(struct work_struct
*work
)
13800 struct drm_atomic_state
*state
=
13801 container_of(work
, struct drm_atomic_state
, commit_work
);
13803 intel_atomic_commit_tail(state
);
13806 static int __i915_sw_fence_call
13807 intel_atomic_commit_ready(struct i915_sw_fence
*fence
,
13808 enum i915_sw_fence_notify notify
)
13810 struct intel_atomic_state
*state
=
13811 container_of(fence
, struct intel_atomic_state
, commit_ready
);
13814 case FENCE_COMPLETE
:
13815 /* we do blocking waits in the worker, nothing to do here */
13819 struct intel_atomic_helper
*helper
=
13820 &to_i915(state
->base
.dev
)->atomic_helper
;
13822 if (llist_add(&state
->freed
, &helper
->free_list
))
13823 schedule_work(&helper
->free_work
);
13828 return NOTIFY_DONE
;
13831 static void intel_atomic_track_fbs(struct drm_atomic_state
*state
)
13833 struct drm_plane_state
*old_plane_state
, *new_plane_state
;
13834 struct drm_plane
*plane
;
13837 for_each_oldnew_plane_in_state(state
, plane
, old_plane_state
, new_plane_state
, i
)
13838 i915_gem_track_fb(intel_fb_obj(old_plane_state
->fb
),
13839 intel_fb_obj(new_plane_state
->fb
),
13840 to_intel_plane(plane
)->frontbuffer_bit
);
13844 * intel_atomic_commit - commit validated state object
13846 * @state: the top-level driver state object
13847 * @nonblock: nonblocking commit
13849 * This function commits a top-level state object that has been validated
13850 * with drm_atomic_helper_check().
13853 * Zero for success or -errno.
13855 static int intel_atomic_commit(struct drm_device
*dev
,
13856 struct drm_atomic_state
*state
,
13859 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
13860 struct drm_i915_private
*dev_priv
= to_i915(dev
);
13863 drm_atomic_state_get(state
);
13864 i915_sw_fence_init(&intel_state
->commit_ready
,
13865 intel_atomic_commit_ready
);
13868 * The intel_legacy_cursor_update() fast path takes care
13869 * of avoiding the vblank waits for simple cursor
13870 * movement and flips. For cursor on/off and size changes,
13871 * we want to perform the vblank waits so that watermark
13872 * updates happen during the correct frames. Gen9+ have
13873 * double buffered watermarks and so shouldn't need this.
13875 * Unset state->legacy_cursor_update before the call to
13876 * drm_atomic_helper_setup_commit() because otherwise
13877 * drm_atomic_helper_wait_for_flip_done() is a noop and
13878 * we get FIFO underruns because we didn't wait
13881 * FIXME doing watermarks and fb cleanup from a vblank worker
13882 * (assuming we had any) would solve these problems.
13884 if (INTEL_GEN(dev_priv
) < 9 && state
->legacy_cursor_update
) {
13885 struct intel_crtc_state
*new_crtc_state
;
13886 struct intel_crtc
*crtc
;
13889 for_each_new_intel_crtc_in_state(intel_state
, crtc
, new_crtc_state
, i
)
13890 if (new_crtc_state
->wm
.need_postvbl_update
||
13891 new_crtc_state
->update_wm_post
)
13892 state
->legacy_cursor_update
= false;
13895 ret
= intel_atomic_prepare_commit(dev
, state
);
13897 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret
);
13898 i915_sw_fence_commit(&intel_state
->commit_ready
);
13902 ret
= drm_atomic_helper_setup_commit(state
, nonblock
);
13904 ret
= drm_atomic_helper_swap_state(state
, true);
13907 i915_sw_fence_commit(&intel_state
->commit_ready
);
13909 drm_atomic_helper_cleanup_planes(dev
, state
);
13912 dev_priv
->wm
.distrust_bios_wm
= false;
13913 intel_shared_dpll_swap_state(state
);
13914 intel_atomic_track_fbs(state
);
13916 if (intel_state
->modeset
) {
13917 memcpy(dev_priv
->min_cdclk
, intel_state
->min_cdclk
,
13918 sizeof(intel_state
->min_cdclk
));
13919 memcpy(dev_priv
->min_voltage_level
,
13920 intel_state
->min_voltage_level
,
13921 sizeof(intel_state
->min_voltage_level
));
13922 dev_priv
->active_crtcs
= intel_state
->active_crtcs
;
13923 dev_priv
->cdclk
.force_min_cdclk
=
13924 intel_state
->cdclk
.force_min_cdclk
;
13926 intel_cdclk_swap_state(intel_state
);
13929 drm_atomic_state_get(state
);
13930 INIT_WORK(&state
->commit_work
, intel_atomic_commit_work
);
13932 i915_sw_fence_commit(&intel_state
->commit_ready
);
13933 if (nonblock
&& intel_state
->modeset
) {
13934 queue_work(dev_priv
->modeset_wq
, &state
->commit_work
);
13935 } else if (nonblock
) {
13936 queue_work(system_unbound_wq
, &state
->commit_work
);
13938 if (intel_state
->modeset
)
13939 flush_workqueue(dev_priv
->modeset_wq
);
13940 intel_atomic_commit_tail(state
);
13946 static const struct drm_crtc_funcs intel_crtc_funcs
= {
13947 .gamma_set
= drm_atomic_helper_legacy_gamma_set
,
13948 .set_config
= drm_atomic_helper_set_config
,
13949 .destroy
= intel_crtc_destroy
,
13950 .page_flip
= drm_atomic_helper_page_flip
,
13951 .atomic_duplicate_state
= intel_crtc_duplicate_state
,
13952 .atomic_destroy_state
= intel_crtc_destroy_state
,
13953 .set_crc_source
= intel_crtc_set_crc_source
,
13954 .verify_crc_source
= intel_crtc_verify_crc_source
,
13955 .get_crc_sources
= intel_crtc_get_crc_sources
,
13958 struct wait_rps_boost
{
13959 struct wait_queue_entry wait
;
13961 struct drm_crtc
*crtc
;
13962 struct i915_request
*request
;
13965 static int do_rps_boost(struct wait_queue_entry
*_wait
,
13966 unsigned mode
, int sync
, void *key
)
13968 struct wait_rps_boost
*wait
= container_of(_wait
, typeof(*wait
), wait
);
13969 struct i915_request
*rq
= wait
->request
;
13972 * If we missed the vblank, but the request is already running it
13973 * is reasonable to assume that it will complete before the next
13974 * vblank without our intervention, so leave RPS alone.
13976 if (!i915_request_started(rq
))
13977 gen6_rps_boost(rq
);
13978 i915_request_put(rq
);
13980 drm_crtc_vblank_put(wait
->crtc
);
13982 list_del(&wait
->wait
.entry
);
13987 static void add_rps_boost_after_vblank(struct drm_crtc
*crtc
,
13988 struct dma_fence
*fence
)
13990 struct wait_rps_boost
*wait
;
13992 if (!dma_fence_is_i915(fence
))
13995 if (INTEL_GEN(to_i915(crtc
->dev
)) < 6)
13998 if (drm_crtc_vblank_get(crtc
))
14001 wait
= kmalloc(sizeof(*wait
), GFP_KERNEL
);
14003 drm_crtc_vblank_put(crtc
);
14007 wait
->request
= to_request(dma_fence_get(fence
));
14010 wait
->wait
.func
= do_rps_boost
;
14011 wait
->wait
.flags
= 0;
14013 add_wait_queue(drm_crtc_vblank_waitqueue(crtc
), &wait
->wait
);
14016 static int intel_plane_pin_fb(struct intel_plane_state
*plane_state
)
14018 struct intel_plane
*plane
= to_intel_plane(plane_state
->base
.plane
);
14019 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
14020 struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
14021 struct i915_vma
*vma
;
14023 if (plane
->id
== PLANE_CURSOR
&&
14024 INTEL_INFO(dev_priv
)->display
.cursor_needs_physical
) {
14025 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
14026 const int align
= intel_cursor_alignment(dev_priv
);
14029 err
= i915_gem_object_attach_phys(obj
, align
);
14034 vma
= intel_pin_and_fence_fb_obj(fb
,
14035 &plane_state
->view
,
14036 intel_plane_uses_fence(plane_state
),
14037 &plane_state
->flags
);
14039 return PTR_ERR(vma
);
14041 plane_state
->vma
= vma
;
14046 static void intel_plane_unpin_fb(struct intel_plane_state
*old_plane_state
)
14048 struct i915_vma
*vma
;
14050 vma
= fetch_and_zero(&old_plane_state
->vma
);
14052 intel_unpin_fb_vma(vma
, old_plane_state
->flags
);
14055 static void fb_obj_bump_render_priority(struct drm_i915_gem_object
*obj
)
14057 struct i915_sched_attr attr
= {
14058 .priority
= I915_PRIORITY_DISPLAY
,
14061 i915_gem_object_wait_priority(obj
, 0, &attr
);
14065 * intel_prepare_plane_fb - Prepare fb for usage on plane
14066 * @plane: drm plane to prepare for
14067 * @new_state: the plane state being prepared
14069 * Prepares a framebuffer for usage on a display plane. Generally this
14070 * involves pinning the underlying object and updating the frontbuffer tracking
14071 * bits. Some older platforms need special physical address handling for
14074 * Must be called with struct_mutex held.
14076 * Returns 0 on success, negative error code on failure.
14079 intel_prepare_plane_fb(struct drm_plane
*plane
,
14080 struct drm_plane_state
*new_state
)
14082 struct intel_atomic_state
*intel_state
=
14083 to_intel_atomic_state(new_state
->state
);
14084 struct drm_i915_private
*dev_priv
= to_i915(plane
->dev
);
14085 struct drm_framebuffer
*fb
= new_state
->fb
;
14086 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
14087 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(plane
->state
->fb
);
14091 struct drm_crtc_state
*crtc_state
=
14092 drm_atomic_get_new_crtc_state(new_state
->state
,
14093 plane
->state
->crtc
);
14095 /* Big Hammer, we also need to ensure that any pending
14096 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
14097 * current scanout is retired before unpinning the old
14098 * framebuffer. Note that we rely on userspace rendering
14099 * into the buffer attached to the pipe they are waiting
14100 * on. If not, userspace generates a GPU hang with IPEHR
14101 * point to the MI_WAIT_FOR_EVENT.
14103 * This should only fail upon a hung GPU, in which case we
14104 * can safely continue.
14106 if (needs_modeset(crtc_state
)) {
14107 ret
= i915_sw_fence_await_reservation(&intel_state
->commit_ready
,
14108 old_obj
->resv
, NULL
,
14116 if (new_state
->fence
) { /* explicit fencing */
14117 ret
= i915_sw_fence_await_dma_fence(&intel_state
->commit_ready
,
14119 I915_FENCE_TIMEOUT
,
14128 ret
= i915_gem_object_pin_pages(obj
);
14132 ret
= mutex_lock_interruptible(&dev_priv
->drm
.struct_mutex
);
14134 i915_gem_object_unpin_pages(obj
);
14138 ret
= intel_plane_pin_fb(to_intel_plane_state(new_state
));
14140 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
14141 i915_gem_object_unpin_pages(obj
);
14145 fb_obj_bump_render_priority(obj
);
14146 intel_fb_obj_flush(obj
, ORIGIN_DIRTYFB
);
14148 if (!new_state
->fence
) { /* implicit fencing */
14149 struct dma_fence
*fence
;
14151 ret
= i915_sw_fence_await_reservation(&intel_state
->commit_ready
,
14153 false, I915_FENCE_TIMEOUT
,
14158 fence
= reservation_object_get_excl_rcu(obj
->resv
);
14160 add_rps_boost_after_vblank(new_state
->crtc
, fence
);
14161 dma_fence_put(fence
);
14164 add_rps_boost_after_vblank(new_state
->crtc
, new_state
->fence
);
14168 * We declare pageflips to be interactive and so merit a small bias
14169 * towards upclocking to deliver the frame on time. By only changing
14170 * the RPS thresholds to sample more regularly and aim for higher
14171 * clocks we can hopefully deliver low power workloads (like kodi)
14172 * that are not quite steady state without resorting to forcing
14173 * maximum clocks following a vblank miss (see do_rps_boost()).
14175 if (!intel_state
->rps_interactive
) {
14176 intel_rps_mark_interactive(dev_priv
, true);
14177 intel_state
->rps_interactive
= true;
14184 * intel_cleanup_plane_fb - Cleans up an fb after plane use
14185 * @plane: drm plane to clean up for
14186 * @old_state: the state from the previous modeset
14188 * Cleans up a framebuffer that has just been removed from a plane.
14190 * Must be called with struct_mutex held.
14193 intel_cleanup_plane_fb(struct drm_plane
*plane
,
14194 struct drm_plane_state
*old_state
)
14196 struct intel_atomic_state
*intel_state
=
14197 to_intel_atomic_state(old_state
->state
);
14198 struct drm_i915_private
*dev_priv
= to_i915(plane
->dev
);
14200 if (intel_state
->rps_interactive
) {
14201 intel_rps_mark_interactive(dev_priv
, false);
14202 intel_state
->rps_interactive
= false;
14205 /* Should only be called after a successful intel_prepare_plane_fb()! */
14206 mutex_lock(&dev_priv
->drm
.struct_mutex
);
14207 intel_plane_unpin_fb(to_intel_plane_state(old_state
));
14208 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
14212 skl_max_scale(const struct intel_crtc_state
*crtc_state
,
14215 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
14216 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
14217 int max_scale
, mult
;
14218 int crtc_clock
, max_dotclk
, tmpclk1
, tmpclk2
;
14220 if (!crtc_state
->base
.enable
)
14221 return DRM_PLANE_HELPER_NO_SCALING
;
14223 crtc_clock
= crtc_state
->base
.adjusted_mode
.crtc_clock
;
14224 max_dotclk
= to_intel_atomic_state(crtc_state
->base
.state
)->cdclk
.logical
.cdclk
;
14226 if (IS_GEMINILAKE(dev_priv
) || INTEL_GEN(dev_priv
) >= 10)
14229 if (WARN_ON_ONCE(!crtc_clock
|| max_dotclk
< crtc_clock
))
14230 return DRM_PLANE_HELPER_NO_SCALING
;
14233 * skl max scale is lower of:
14234 * close to 3 but not 3, -1 is for that purpose
14238 mult
= is_planar_yuv_format(pixel_format
) ? 2 : 3;
14239 tmpclk1
= (1 << 16) * mult
- 1;
14240 tmpclk2
= (1 << 8) * ((max_dotclk
<< 8) / crtc_clock
);
14241 max_scale
= min(tmpclk1
, tmpclk2
);
14246 static void intel_begin_crtc_commit(struct intel_atomic_state
*state
,
14247 struct intel_crtc
*crtc
)
14249 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
14250 struct intel_crtc_state
*old_crtc_state
=
14251 intel_atomic_get_old_crtc_state(state
, crtc
);
14252 struct intel_crtc_state
*new_crtc_state
=
14253 intel_atomic_get_new_crtc_state(state
, crtc
);
14254 bool modeset
= needs_modeset(&new_crtc_state
->base
);
14256 /* Perform vblank evasion around commit operation */
14257 intel_pipe_update_start(new_crtc_state
);
14262 if (new_crtc_state
->base
.color_mgmt_changed
||
14263 new_crtc_state
->update_pipe
)
14264 intel_color_commit(new_crtc_state
);
14266 if (new_crtc_state
->update_pipe
)
14267 intel_update_pipe_config(old_crtc_state
, new_crtc_state
);
14268 else if (INTEL_GEN(dev_priv
) >= 9)
14269 skl_detach_scalers(new_crtc_state
);
14271 if (INTEL_GEN(dev_priv
) >= 9 || IS_BROADWELL(dev_priv
))
14272 bdw_set_pipemisc(new_crtc_state
);
14275 if (dev_priv
->display
.atomic_update_watermarks
)
14276 dev_priv
->display
.atomic_update_watermarks(state
,
14280 void intel_crtc_arm_fifo_underrun(struct intel_crtc
*crtc
,
14281 struct intel_crtc_state
*crtc_state
)
14283 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
14285 if (!IS_GEN(dev_priv
, 2))
14286 intel_set_cpu_fifo_underrun_reporting(dev_priv
, crtc
->pipe
, true);
14288 if (crtc_state
->has_pch_encoder
) {
14289 enum pipe pch_transcoder
=
14290 intel_crtc_pch_transcoder(crtc
);
14292 intel_set_pch_fifo_underrun_reporting(dev_priv
, pch_transcoder
, true);
14296 static void intel_finish_crtc_commit(struct intel_atomic_state
*state
,
14297 struct intel_crtc
*crtc
)
14299 struct intel_crtc_state
*old_crtc_state
=
14300 intel_atomic_get_old_crtc_state(state
, crtc
);
14301 struct intel_crtc_state
*new_crtc_state
=
14302 intel_atomic_get_new_crtc_state(state
, crtc
);
14304 intel_pipe_update_end(new_crtc_state
);
14306 if (new_crtc_state
->update_pipe
&&
14307 !needs_modeset(&new_crtc_state
->base
) &&
14308 old_crtc_state
->base
.mode
.private_flags
& I915_MODE_FLAG_INHERITED
)
14309 intel_crtc_arm_fifo_underrun(crtc
, new_crtc_state
);
14313 * intel_plane_destroy - destroy a plane
14314 * @plane: plane to destroy
14316 * Common destruction function for all types of planes (primary, cursor,
14319 void intel_plane_destroy(struct drm_plane
*plane
)
14321 drm_plane_cleanup(plane
);
14322 kfree(to_intel_plane(plane
));
14325 static bool i8xx_plane_format_mod_supported(struct drm_plane
*_plane
,
14326 u32 format
, u64 modifier
)
14328 switch (modifier
) {
14329 case DRM_FORMAT_MOD_LINEAR
:
14330 case I915_FORMAT_MOD_X_TILED
:
14337 case DRM_FORMAT_C8
:
14338 case DRM_FORMAT_RGB565
:
14339 case DRM_FORMAT_XRGB1555
:
14340 case DRM_FORMAT_XRGB8888
:
14341 return modifier
== DRM_FORMAT_MOD_LINEAR
||
14342 modifier
== I915_FORMAT_MOD_X_TILED
;
14348 static bool i965_plane_format_mod_supported(struct drm_plane
*_plane
,
14349 u32 format
, u64 modifier
)
14351 switch (modifier
) {
14352 case DRM_FORMAT_MOD_LINEAR
:
14353 case I915_FORMAT_MOD_X_TILED
:
14360 case DRM_FORMAT_C8
:
14361 case DRM_FORMAT_RGB565
:
14362 case DRM_FORMAT_XRGB8888
:
14363 case DRM_FORMAT_XBGR8888
:
14364 case DRM_FORMAT_XRGB2101010
:
14365 case DRM_FORMAT_XBGR2101010
:
14366 return modifier
== DRM_FORMAT_MOD_LINEAR
||
14367 modifier
== I915_FORMAT_MOD_X_TILED
;
14373 static bool intel_cursor_format_mod_supported(struct drm_plane
*_plane
,
14374 u32 format
, u64 modifier
)
14376 return modifier
== DRM_FORMAT_MOD_LINEAR
&&
14377 format
== DRM_FORMAT_ARGB8888
;
14380 static const struct drm_plane_funcs i965_plane_funcs
= {
14381 .update_plane
= drm_atomic_helper_update_plane
,
14382 .disable_plane
= drm_atomic_helper_disable_plane
,
14383 .destroy
= intel_plane_destroy
,
14384 .atomic_get_property
= intel_plane_atomic_get_property
,
14385 .atomic_set_property
= intel_plane_atomic_set_property
,
14386 .atomic_duplicate_state
= intel_plane_duplicate_state
,
14387 .atomic_destroy_state
= intel_plane_destroy_state
,
14388 .format_mod_supported
= i965_plane_format_mod_supported
,
14391 static const struct drm_plane_funcs i8xx_plane_funcs
= {
14392 .update_plane
= drm_atomic_helper_update_plane
,
14393 .disable_plane
= drm_atomic_helper_disable_plane
,
14394 .destroy
= intel_plane_destroy
,
14395 .atomic_get_property
= intel_plane_atomic_get_property
,
14396 .atomic_set_property
= intel_plane_atomic_set_property
,
14397 .atomic_duplicate_state
= intel_plane_duplicate_state
,
14398 .atomic_destroy_state
= intel_plane_destroy_state
,
14399 .format_mod_supported
= i8xx_plane_format_mod_supported
,
14403 intel_legacy_cursor_update(struct drm_plane
*plane
,
14404 struct drm_crtc
*crtc
,
14405 struct drm_framebuffer
*fb
,
14406 int crtc_x
, int crtc_y
,
14407 unsigned int crtc_w
, unsigned int crtc_h
,
14408 u32 src_x
, u32 src_y
,
14409 u32 src_w
, u32 src_h
,
14410 struct drm_modeset_acquire_ctx
*ctx
)
14412 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
14414 struct drm_plane_state
*old_plane_state
, *new_plane_state
;
14415 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
14416 struct drm_framebuffer
*old_fb
;
14417 struct intel_crtc_state
*crtc_state
=
14418 to_intel_crtc_state(crtc
->state
);
14419 struct intel_crtc_state
*new_crtc_state
;
14422 * When crtc is inactive or there is a modeset pending,
14423 * wait for it to complete in the slowpath
14425 if (!crtc_state
->base
.active
|| needs_modeset(&crtc_state
->base
) ||
14426 crtc_state
->update_pipe
)
14429 old_plane_state
= plane
->state
;
14431 * Don't do an async update if there is an outstanding commit modifying
14432 * the plane. This prevents our async update's changes from getting
14433 * overridden by a previous synchronous update's state.
14435 if (old_plane_state
->commit
&&
14436 !try_wait_for_completion(&old_plane_state
->commit
->hw_done
))
14440 * If any parameters change that may affect watermarks,
14441 * take the slowpath. Only changing fb or position should be
14444 if (old_plane_state
->crtc
!= crtc
||
14445 old_plane_state
->src_w
!= src_w
||
14446 old_plane_state
->src_h
!= src_h
||
14447 old_plane_state
->crtc_w
!= crtc_w
||
14448 old_plane_state
->crtc_h
!= crtc_h
||
14449 !old_plane_state
->fb
!= !fb
)
14452 new_plane_state
= intel_plane_duplicate_state(plane
);
14453 if (!new_plane_state
)
14456 new_crtc_state
= to_intel_crtc_state(intel_crtc_duplicate_state(crtc
));
14457 if (!new_crtc_state
) {
14462 drm_atomic_set_fb_for_plane(new_plane_state
, fb
);
14464 new_plane_state
->src_x
= src_x
;
14465 new_plane_state
->src_y
= src_y
;
14466 new_plane_state
->src_w
= src_w
;
14467 new_plane_state
->src_h
= src_h
;
14468 new_plane_state
->crtc_x
= crtc_x
;
14469 new_plane_state
->crtc_y
= crtc_y
;
14470 new_plane_state
->crtc_w
= crtc_w
;
14471 new_plane_state
->crtc_h
= crtc_h
;
14473 ret
= intel_plane_atomic_check_with_state(crtc_state
, new_crtc_state
,
14474 to_intel_plane_state(old_plane_state
),
14475 to_intel_plane_state(new_plane_state
));
14479 ret
= mutex_lock_interruptible(&dev_priv
->drm
.struct_mutex
);
14483 ret
= intel_plane_pin_fb(to_intel_plane_state(new_plane_state
));
14487 intel_fb_obj_flush(intel_fb_obj(fb
), ORIGIN_FLIP
);
14489 old_fb
= old_plane_state
->fb
;
14490 i915_gem_track_fb(intel_fb_obj(old_fb
), intel_fb_obj(fb
),
14491 intel_plane
->frontbuffer_bit
);
14493 /* Swap plane state */
14494 plane
->state
= new_plane_state
;
14497 * We cannot swap crtc_state as it may be in use by an atomic commit or
14498 * page flip that's running simultaneously. If we swap crtc_state and
14499 * destroy the old state, we will cause a use-after-free there.
14501 * Only update active_planes, which is needed for our internal
14502 * bookkeeping. Either value will do the right thing when updating
14503 * planes atomically. If the cursor was part of the atomic update then
14504 * we would have taken the slowpath.
14506 crtc_state
->active_planes
= new_crtc_state
->active_planes
;
14508 if (plane
->state
->visible
)
14509 intel_update_plane(intel_plane
, crtc_state
,
14510 to_intel_plane_state(plane
->state
));
14512 intel_disable_plane(intel_plane
, crtc_state
);
14514 intel_plane_unpin_fb(to_intel_plane_state(old_plane_state
));
14517 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
14519 if (new_crtc_state
)
14520 intel_crtc_destroy_state(crtc
, &new_crtc_state
->base
);
14522 intel_plane_destroy_state(plane
, new_plane_state
);
14524 intel_plane_destroy_state(plane
, old_plane_state
);
14528 return drm_atomic_helper_update_plane(plane
, crtc
, fb
,
14529 crtc_x
, crtc_y
, crtc_w
, crtc_h
,
14530 src_x
, src_y
, src_w
, src_h
, ctx
);
14533 static const struct drm_plane_funcs intel_cursor_plane_funcs
= {
14534 .update_plane
= intel_legacy_cursor_update
,
14535 .disable_plane
= drm_atomic_helper_disable_plane
,
14536 .destroy
= intel_plane_destroy
,
14537 .atomic_get_property
= intel_plane_atomic_get_property
,
14538 .atomic_set_property
= intel_plane_atomic_set_property
,
14539 .atomic_duplicate_state
= intel_plane_duplicate_state
,
14540 .atomic_destroy_state
= intel_plane_destroy_state
,
14541 .format_mod_supported
= intel_cursor_format_mod_supported
,
14544 static bool i9xx_plane_has_fbc(struct drm_i915_private
*dev_priv
,
14545 enum i9xx_plane_id i9xx_plane
)
14547 if (!HAS_FBC(dev_priv
))
14550 if (IS_BROADWELL(dev_priv
) || IS_HASWELL(dev_priv
))
14551 return i9xx_plane
== PLANE_A
; /* tied to pipe A */
14552 else if (IS_IVYBRIDGE(dev_priv
))
14553 return i9xx_plane
== PLANE_A
|| i9xx_plane
== PLANE_B
||
14554 i9xx_plane
== PLANE_C
;
14555 else if (INTEL_GEN(dev_priv
) >= 4)
14556 return i9xx_plane
== PLANE_A
|| i9xx_plane
== PLANE_B
;
14558 return i9xx_plane
== PLANE_A
;
14561 static struct intel_plane
*
14562 intel_primary_plane_create(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
14564 struct intel_plane
*plane
;
14565 const struct drm_plane_funcs
*plane_funcs
;
14566 unsigned int supported_rotations
;
14567 unsigned int possible_crtcs
;
14568 const u64
*modifiers
;
14569 const u32
*formats
;
14573 if (INTEL_GEN(dev_priv
) >= 9)
14574 return skl_universal_plane_create(dev_priv
, pipe
,
14577 plane
= intel_plane_alloc();
14581 plane
->pipe
= pipe
;
14583 * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
14584 * port is hooked to pipe B. Hence we want plane A feeding pipe B.
14586 if (HAS_FBC(dev_priv
) && INTEL_GEN(dev_priv
) < 4)
14587 plane
->i9xx_plane
= (enum i9xx_plane_id
) !pipe
;
14589 plane
->i9xx_plane
= (enum i9xx_plane_id
) pipe
;
14590 plane
->id
= PLANE_PRIMARY
;
14591 plane
->frontbuffer_bit
= INTEL_FRONTBUFFER(pipe
, plane
->id
);
14593 plane
->has_fbc
= i9xx_plane_has_fbc(dev_priv
, plane
->i9xx_plane
);
14594 if (plane
->has_fbc
) {
14595 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
14597 fbc
->possible_framebuffer_bits
|= plane
->frontbuffer_bit
;
14600 if (INTEL_GEN(dev_priv
) >= 4) {
14601 formats
= i965_primary_formats
;
14602 num_formats
= ARRAY_SIZE(i965_primary_formats
);
14603 modifiers
= i9xx_format_modifiers
;
14605 plane
->max_stride
= i9xx_plane_max_stride
;
14606 plane
->update_plane
= i9xx_update_plane
;
14607 plane
->disable_plane
= i9xx_disable_plane
;
14608 plane
->get_hw_state
= i9xx_plane_get_hw_state
;
14609 plane
->check_plane
= i9xx_plane_check
;
14611 plane_funcs
= &i965_plane_funcs
;
14613 formats
= i8xx_primary_formats
;
14614 num_formats
= ARRAY_SIZE(i8xx_primary_formats
);
14615 modifiers
= i9xx_format_modifiers
;
14617 plane
->max_stride
= i9xx_plane_max_stride
;
14618 plane
->update_plane
= i9xx_update_plane
;
14619 plane
->disable_plane
= i9xx_disable_plane
;
14620 plane
->get_hw_state
= i9xx_plane_get_hw_state
;
14621 plane
->check_plane
= i9xx_plane_check
;
14623 plane_funcs
= &i8xx_plane_funcs
;
14626 possible_crtcs
= BIT(pipe
);
14628 if (INTEL_GEN(dev_priv
) >= 5 || IS_G4X(dev_priv
))
14629 ret
= drm_universal_plane_init(&dev_priv
->drm
, &plane
->base
,
14630 possible_crtcs
, plane_funcs
,
14631 formats
, num_formats
, modifiers
,
14632 DRM_PLANE_TYPE_PRIMARY
,
14633 "primary %c", pipe_name(pipe
));
14635 ret
= drm_universal_plane_init(&dev_priv
->drm
, &plane
->base
,
14636 possible_crtcs
, plane_funcs
,
14637 formats
, num_formats
, modifiers
,
14638 DRM_PLANE_TYPE_PRIMARY
,
14640 plane_name(plane
->i9xx_plane
));
14644 if (IS_CHERRYVIEW(dev_priv
) && pipe
== PIPE_B
) {
14645 supported_rotations
=
14646 DRM_MODE_ROTATE_0
| DRM_MODE_ROTATE_180
|
14647 DRM_MODE_REFLECT_X
;
14648 } else if (INTEL_GEN(dev_priv
) >= 4) {
14649 supported_rotations
=
14650 DRM_MODE_ROTATE_0
| DRM_MODE_ROTATE_180
;
14652 supported_rotations
= DRM_MODE_ROTATE_0
;
14655 if (INTEL_GEN(dev_priv
) >= 4)
14656 drm_plane_create_rotation_property(&plane
->base
,
14658 supported_rotations
);
14660 drm_plane_helper_add(&plane
->base
, &intel_plane_helper_funcs
);
14665 intel_plane_free(plane
);
14667 return ERR_PTR(ret
);
14670 static struct intel_plane
*
14671 intel_cursor_plane_create(struct drm_i915_private
*dev_priv
,
14674 unsigned int possible_crtcs
;
14675 struct intel_plane
*cursor
;
14678 cursor
= intel_plane_alloc();
14679 if (IS_ERR(cursor
))
14682 cursor
->pipe
= pipe
;
14683 cursor
->i9xx_plane
= (enum i9xx_plane_id
) pipe
;
14684 cursor
->id
= PLANE_CURSOR
;
14685 cursor
->frontbuffer_bit
= INTEL_FRONTBUFFER(pipe
, cursor
->id
);
14687 if (IS_I845G(dev_priv
) || IS_I865G(dev_priv
)) {
14688 cursor
->max_stride
= i845_cursor_max_stride
;
14689 cursor
->update_plane
= i845_update_cursor
;
14690 cursor
->disable_plane
= i845_disable_cursor
;
14691 cursor
->get_hw_state
= i845_cursor_get_hw_state
;
14692 cursor
->check_plane
= i845_check_cursor
;
14694 cursor
->max_stride
= i9xx_cursor_max_stride
;
14695 cursor
->update_plane
= i9xx_update_cursor
;
14696 cursor
->disable_plane
= i9xx_disable_cursor
;
14697 cursor
->get_hw_state
= i9xx_cursor_get_hw_state
;
14698 cursor
->check_plane
= i9xx_check_cursor
;
14701 cursor
->cursor
.base
= ~0;
14702 cursor
->cursor
.cntl
= ~0;
14704 if (IS_I845G(dev_priv
) || IS_I865G(dev_priv
) || HAS_CUR_FBC(dev_priv
))
14705 cursor
->cursor
.size
= ~0;
14707 possible_crtcs
= BIT(pipe
);
14709 ret
= drm_universal_plane_init(&dev_priv
->drm
, &cursor
->base
,
14710 possible_crtcs
, &intel_cursor_plane_funcs
,
14711 intel_cursor_formats
,
14712 ARRAY_SIZE(intel_cursor_formats
),
14713 cursor_format_modifiers
,
14714 DRM_PLANE_TYPE_CURSOR
,
14715 "cursor %c", pipe_name(pipe
));
14719 if (INTEL_GEN(dev_priv
) >= 4)
14720 drm_plane_create_rotation_property(&cursor
->base
,
14722 DRM_MODE_ROTATE_0
|
14723 DRM_MODE_ROTATE_180
);
14725 drm_plane_helper_add(&cursor
->base
, &intel_plane_helper_funcs
);
14730 intel_plane_free(cursor
);
14732 return ERR_PTR(ret
);
14735 static void intel_crtc_init_scalers(struct intel_crtc
*crtc
,
14736 struct intel_crtc_state
*crtc_state
)
14738 struct intel_crtc_scaler_state
*scaler_state
=
14739 &crtc_state
->scaler_state
;
14740 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
14743 crtc
->num_scalers
= RUNTIME_INFO(dev_priv
)->num_scalers
[crtc
->pipe
];
14744 if (!crtc
->num_scalers
)
14747 for (i
= 0; i
< crtc
->num_scalers
; i
++) {
14748 struct intel_scaler
*scaler
= &scaler_state
->scalers
[i
];
14750 scaler
->in_use
= 0;
14754 scaler_state
->scaler_id
= -1;
14757 static int intel_crtc_init(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
14759 struct intel_crtc
*intel_crtc
;
14760 struct intel_crtc_state
*crtc_state
= NULL
;
14761 struct intel_plane
*primary
= NULL
;
14762 struct intel_plane
*cursor
= NULL
;
14765 intel_crtc
= kzalloc(sizeof(*intel_crtc
), GFP_KERNEL
);
14769 crtc_state
= kzalloc(sizeof(*crtc_state
), GFP_KERNEL
);
14774 intel_crtc
->config
= crtc_state
;
14775 intel_crtc
->base
.state
= &crtc_state
->base
;
14776 crtc_state
->base
.crtc
= &intel_crtc
->base
;
14778 primary
= intel_primary_plane_create(dev_priv
, pipe
);
14779 if (IS_ERR(primary
)) {
14780 ret
= PTR_ERR(primary
);
14783 intel_crtc
->plane_ids_mask
|= BIT(primary
->id
);
14785 for_each_sprite(dev_priv
, pipe
, sprite
) {
14786 struct intel_plane
*plane
;
14788 plane
= intel_sprite_plane_create(dev_priv
, pipe
, sprite
);
14789 if (IS_ERR(plane
)) {
14790 ret
= PTR_ERR(plane
);
14793 intel_crtc
->plane_ids_mask
|= BIT(plane
->id
);
14796 cursor
= intel_cursor_plane_create(dev_priv
, pipe
);
14797 if (IS_ERR(cursor
)) {
14798 ret
= PTR_ERR(cursor
);
14801 intel_crtc
->plane_ids_mask
|= BIT(cursor
->id
);
14803 ret
= drm_crtc_init_with_planes(&dev_priv
->drm
, &intel_crtc
->base
,
14804 &primary
->base
, &cursor
->base
,
14806 "pipe %c", pipe_name(pipe
));
14810 intel_crtc
->pipe
= pipe
;
14812 /* initialize shared scalers */
14813 intel_crtc_init_scalers(intel_crtc
, crtc_state
);
14815 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->pipe_to_crtc_mapping
) ||
14816 dev_priv
->pipe_to_crtc_mapping
[pipe
] != NULL
);
14817 dev_priv
->pipe_to_crtc_mapping
[pipe
] = intel_crtc
;
14819 if (INTEL_GEN(dev_priv
) < 9) {
14820 enum i9xx_plane_id i9xx_plane
= primary
->i9xx_plane
;
14822 BUG_ON(i9xx_plane
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
14823 dev_priv
->plane_to_crtc_mapping
[i9xx_plane
] != NULL
);
14824 dev_priv
->plane_to_crtc_mapping
[i9xx_plane
] = intel_crtc
;
14827 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
14829 intel_color_init(intel_crtc
);
14831 WARN_ON(drm_crtc_index(&intel_crtc
->base
) != intel_crtc
->pipe
);
14837 * drm_mode_config_cleanup() will free up any
14838 * crtcs/planes already initialized.
14846 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device
*dev
, void *data
,
14847 struct drm_file
*file
)
14849 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
14850 struct drm_crtc
*drmmode_crtc
;
14851 struct intel_crtc
*crtc
;
14853 drmmode_crtc
= drm_crtc_find(dev
, file
, pipe_from_crtc_id
->crtc_id
);
14857 crtc
= to_intel_crtc(drmmode_crtc
);
14858 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
14863 static int intel_encoder_clones(struct intel_encoder
*encoder
)
14865 struct drm_device
*dev
= encoder
->base
.dev
;
14866 struct intel_encoder
*source_encoder
;
14867 int index_mask
= 0;
14870 for_each_intel_encoder(dev
, source_encoder
) {
14871 if (encoders_cloneable(encoder
, source_encoder
))
14872 index_mask
|= (1 << entry
);
14880 static bool ilk_has_edp_a(struct drm_i915_private
*dev_priv
)
14882 if (!IS_MOBILE(dev_priv
))
14885 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
14888 if (IS_GEN(dev_priv
, 5) && (I915_READ(FUSE_STRAP
) & ILK_eDP_A_DISABLE
))
14894 static bool intel_ddi_crt_present(struct drm_i915_private
*dev_priv
)
14896 if (INTEL_GEN(dev_priv
) >= 9)
14899 if (IS_HSW_ULT(dev_priv
) || IS_BDW_ULT(dev_priv
))
14902 if (HAS_PCH_LPT_H(dev_priv
) &&
14903 I915_READ(SFUSE_STRAP
) & SFUSE_STRAP_CRT_DISABLED
)
14906 /* DDI E can't be used if DDI A requires 4 lanes */
14907 if (I915_READ(DDI_BUF_CTL(PORT_A
)) & DDI_A_4_LANES
)
14910 if (!dev_priv
->vbt
.int_crt_support
)
14916 void intel_pps_unlock_regs_wa(struct drm_i915_private
*dev_priv
)
14921 if (HAS_DDI(dev_priv
))
14924 * This w/a is needed at least on CPT/PPT, but to be sure apply it
14925 * everywhere where registers can be write protected.
14927 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
14932 for (pps_idx
= 0; pps_idx
< pps_num
; pps_idx
++) {
14933 u32 val
= I915_READ(PP_CONTROL(pps_idx
));
14935 val
= (val
& ~PANEL_UNLOCK_MASK
) | PANEL_UNLOCK_REGS
;
14936 I915_WRITE(PP_CONTROL(pps_idx
), val
);
14940 static void intel_pps_init(struct drm_i915_private
*dev_priv
)
14942 if (HAS_PCH_SPLIT(dev_priv
) || IS_GEN9_LP(dev_priv
))
14943 dev_priv
->pps_mmio_base
= PCH_PPS_BASE
;
14944 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
14945 dev_priv
->pps_mmio_base
= VLV_PPS_BASE
;
14947 dev_priv
->pps_mmio_base
= PPS_BASE
;
14949 intel_pps_unlock_regs_wa(dev_priv
);
14952 static void intel_setup_outputs(struct drm_i915_private
*dev_priv
)
14954 struct intel_encoder
*encoder
;
14955 bool dpd_is_edp
= false;
14957 intel_pps_init(dev_priv
);
14959 if (!HAS_DISPLAY(dev_priv
))
14962 if (IS_ELKHARTLAKE(dev_priv
)) {
14963 intel_ddi_init(dev_priv
, PORT_A
);
14964 intel_ddi_init(dev_priv
, PORT_B
);
14965 intel_ddi_init(dev_priv
, PORT_C
);
14966 icl_dsi_init(dev_priv
);
14967 } else if (INTEL_GEN(dev_priv
) >= 11) {
14968 intel_ddi_init(dev_priv
, PORT_A
);
14969 intel_ddi_init(dev_priv
, PORT_B
);
14970 intel_ddi_init(dev_priv
, PORT_C
);
14971 intel_ddi_init(dev_priv
, PORT_D
);
14972 intel_ddi_init(dev_priv
, PORT_E
);
14974 * On some ICL SKUs port F is not present. No strap bits for
14975 * this, so rely on VBT.
14976 * Work around broken VBTs on SKUs known to have no port F.
14978 if (IS_ICL_WITH_PORT_F(dev_priv
) &&
14979 intel_bios_is_port_present(dev_priv
, PORT_F
))
14980 intel_ddi_init(dev_priv
, PORT_F
);
14982 icl_dsi_init(dev_priv
);
14983 } else if (IS_GEN9_LP(dev_priv
)) {
14985 * FIXME: Broxton doesn't support port detection via the
14986 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14987 * detect the ports.
14989 intel_ddi_init(dev_priv
, PORT_A
);
14990 intel_ddi_init(dev_priv
, PORT_B
);
14991 intel_ddi_init(dev_priv
, PORT_C
);
14993 vlv_dsi_init(dev_priv
);
14994 } else if (HAS_DDI(dev_priv
)) {
14997 if (intel_ddi_crt_present(dev_priv
))
14998 intel_crt_init(dev_priv
);
15001 * Haswell uses DDI functions to detect digital outputs.
15002 * On SKL pre-D0 the strap isn't connected, so we assume
15005 found
= I915_READ(DDI_BUF_CTL(PORT_A
)) & DDI_INIT_DISPLAY_DETECTED
;
15006 /* WaIgnoreDDIAStrap: skl */
15007 if (found
|| IS_GEN9_BC(dev_priv
))
15008 intel_ddi_init(dev_priv
, PORT_A
);
15010 /* DDI B, C, D, and F detection is indicated by the SFUSE_STRAP
15012 found
= I915_READ(SFUSE_STRAP
);
15014 if (found
& SFUSE_STRAP_DDIB_DETECTED
)
15015 intel_ddi_init(dev_priv
, PORT_B
);
15016 if (found
& SFUSE_STRAP_DDIC_DETECTED
)
15017 intel_ddi_init(dev_priv
, PORT_C
);
15018 if (found
& SFUSE_STRAP_DDID_DETECTED
)
15019 intel_ddi_init(dev_priv
, PORT_D
);
15020 if (found
& SFUSE_STRAP_DDIF_DETECTED
)
15021 intel_ddi_init(dev_priv
, PORT_F
);
15023 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
15025 if (IS_GEN9_BC(dev_priv
) &&
15026 intel_bios_is_port_present(dev_priv
, PORT_E
))
15027 intel_ddi_init(dev_priv
, PORT_E
);
15029 } else if (HAS_PCH_SPLIT(dev_priv
)) {
15033 * intel_edp_init_connector() depends on this completing first,
15034 * to prevent the registration of both eDP and LVDS and the
15035 * incorrect sharing of the PPS.
15037 intel_lvds_init(dev_priv
);
15038 intel_crt_init(dev_priv
);
15040 dpd_is_edp
= intel_dp_is_port_edp(dev_priv
, PORT_D
);
15042 if (ilk_has_edp_a(dev_priv
))
15043 intel_dp_init(dev_priv
, DP_A
, PORT_A
);
15045 if (I915_READ(PCH_HDMIB
) & SDVO_DETECTED
) {
15046 /* PCH SDVOB multiplex with HDMIB */
15047 found
= intel_sdvo_init(dev_priv
, PCH_SDVOB
, PORT_B
);
15049 intel_hdmi_init(dev_priv
, PCH_HDMIB
, PORT_B
);
15050 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
15051 intel_dp_init(dev_priv
, PCH_DP_B
, PORT_B
);
15054 if (I915_READ(PCH_HDMIC
) & SDVO_DETECTED
)
15055 intel_hdmi_init(dev_priv
, PCH_HDMIC
, PORT_C
);
15057 if (!dpd_is_edp
&& I915_READ(PCH_HDMID
) & SDVO_DETECTED
)
15058 intel_hdmi_init(dev_priv
, PCH_HDMID
, PORT_D
);
15060 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
15061 intel_dp_init(dev_priv
, PCH_DP_C
, PORT_C
);
15063 if (I915_READ(PCH_DP_D
) & DP_DETECTED
)
15064 intel_dp_init(dev_priv
, PCH_DP_D
, PORT_D
);
15065 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
15066 bool has_edp
, has_port
;
15068 if (IS_VALLEYVIEW(dev_priv
) && dev_priv
->vbt
.int_crt_support
)
15069 intel_crt_init(dev_priv
);
15072 * The DP_DETECTED bit is the latched state of the DDC
15073 * SDA pin at boot. However since eDP doesn't require DDC
15074 * (no way to plug in a DP->HDMI dongle) the DDC pins for
15075 * eDP ports may have been muxed to an alternate function.
15076 * Thus we can't rely on the DP_DETECTED bit alone to detect
15077 * eDP ports. Consult the VBT as well as DP_DETECTED to
15078 * detect eDP ports.
15080 * Sadly the straps seem to be missing sometimes even for HDMI
15081 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
15082 * and VBT for the presence of the port. Additionally we can't
15083 * trust the port type the VBT declares as we've seen at least
15084 * HDMI ports that the VBT claim are DP or eDP.
15086 has_edp
= intel_dp_is_port_edp(dev_priv
, PORT_B
);
15087 has_port
= intel_bios_is_port_present(dev_priv
, PORT_B
);
15088 if (I915_READ(VLV_DP_B
) & DP_DETECTED
|| has_port
)
15089 has_edp
&= intel_dp_init(dev_priv
, VLV_DP_B
, PORT_B
);
15090 if ((I915_READ(VLV_HDMIB
) & SDVO_DETECTED
|| has_port
) && !has_edp
)
15091 intel_hdmi_init(dev_priv
, VLV_HDMIB
, PORT_B
);
15093 has_edp
= intel_dp_is_port_edp(dev_priv
, PORT_C
);
15094 has_port
= intel_bios_is_port_present(dev_priv
, PORT_C
);
15095 if (I915_READ(VLV_DP_C
) & DP_DETECTED
|| has_port
)
15096 has_edp
&= intel_dp_init(dev_priv
, VLV_DP_C
, PORT_C
);
15097 if ((I915_READ(VLV_HDMIC
) & SDVO_DETECTED
|| has_port
) && !has_edp
)
15098 intel_hdmi_init(dev_priv
, VLV_HDMIC
, PORT_C
);
15100 if (IS_CHERRYVIEW(dev_priv
)) {
15102 * eDP not supported on port D,
15103 * so no need to worry about it
15105 has_port
= intel_bios_is_port_present(dev_priv
, PORT_D
);
15106 if (I915_READ(CHV_DP_D
) & DP_DETECTED
|| has_port
)
15107 intel_dp_init(dev_priv
, CHV_DP_D
, PORT_D
);
15108 if (I915_READ(CHV_HDMID
) & SDVO_DETECTED
|| has_port
)
15109 intel_hdmi_init(dev_priv
, CHV_HDMID
, PORT_D
);
15112 vlv_dsi_init(dev_priv
);
15113 } else if (IS_PINEVIEW(dev_priv
)) {
15114 intel_lvds_init(dev_priv
);
15115 intel_crt_init(dev_priv
);
15116 } else if (IS_GEN_RANGE(dev_priv
, 3, 4)) {
15117 bool found
= false;
15119 if (IS_MOBILE(dev_priv
))
15120 intel_lvds_init(dev_priv
);
15122 intel_crt_init(dev_priv
);
15124 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
15125 DRM_DEBUG_KMS("probing SDVOB\n");
15126 found
= intel_sdvo_init(dev_priv
, GEN3_SDVOB
, PORT_B
);
15127 if (!found
&& IS_G4X(dev_priv
)) {
15128 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
15129 intel_hdmi_init(dev_priv
, GEN4_HDMIB
, PORT_B
);
15132 if (!found
&& IS_G4X(dev_priv
))
15133 intel_dp_init(dev_priv
, DP_B
, PORT_B
);
15136 /* Before G4X SDVOC doesn't have its own detect register */
15138 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
15139 DRM_DEBUG_KMS("probing SDVOC\n");
15140 found
= intel_sdvo_init(dev_priv
, GEN3_SDVOC
, PORT_C
);
15143 if (!found
&& (I915_READ(GEN3_SDVOC
) & SDVO_DETECTED
)) {
15145 if (IS_G4X(dev_priv
)) {
15146 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
15147 intel_hdmi_init(dev_priv
, GEN4_HDMIC
, PORT_C
);
15149 if (IS_G4X(dev_priv
))
15150 intel_dp_init(dev_priv
, DP_C
, PORT_C
);
15153 if (IS_G4X(dev_priv
) && (I915_READ(DP_D
) & DP_DETECTED
))
15154 intel_dp_init(dev_priv
, DP_D
, PORT_D
);
15156 if (SUPPORTS_TV(dev_priv
))
15157 intel_tv_init(dev_priv
);
15158 } else if (IS_GEN(dev_priv
, 2)) {
15159 if (IS_I85X(dev_priv
))
15160 intel_lvds_init(dev_priv
);
15162 intel_crt_init(dev_priv
);
15163 intel_dvo_init(dev_priv
);
15166 intel_psr_init(dev_priv
);
15168 for_each_intel_encoder(&dev_priv
->drm
, encoder
) {
15169 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
15170 encoder
->base
.possible_clones
=
15171 intel_encoder_clones(encoder
);
15174 intel_init_pch_refclk(dev_priv
);
15176 drm_helper_move_panel_connectors_to_head(&dev_priv
->drm
);
15179 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
15181 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
15182 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
15184 drm_framebuffer_cleanup(fb
);
15186 i915_gem_object_lock(obj
);
15187 WARN_ON(!obj
->framebuffer_references
--);
15188 i915_gem_object_unlock(obj
);
15190 i915_gem_object_put(obj
);
15195 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
15196 struct drm_file
*file
,
15197 unsigned int *handle
)
15199 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
15201 if (obj
->userptr
.mm
) {
15202 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
15206 return drm_gem_handle_create(file
, &obj
->base
, handle
);
15209 static int intel_user_framebuffer_dirty(struct drm_framebuffer
*fb
,
15210 struct drm_file
*file
,
15211 unsigned flags
, unsigned color
,
15212 struct drm_clip_rect
*clips
,
15213 unsigned num_clips
)
15215 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
15217 i915_gem_object_flush_if_display(obj
);
15218 intel_fb_obj_flush(obj
, ORIGIN_DIRTYFB
);
15223 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
15224 .destroy
= intel_user_framebuffer_destroy
,
15225 .create_handle
= intel_user_framebuffer_create_handle
,
15226 .dirty
= intel_user_framebuffer_dirty
,
15229 static int intel_framebuffer_init(struct intel_framebuffer
*intel_fb
,
15230 struct drm_i915_gem_object
*obj
,
15231 struct drm_mode_fb_cmd2
*mode_cmd
)
15233 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
15234 struct drm_framebuffer
*fb
= &intel_fb
->base
;
15236 unsigned int tiling
, stride
;
15240 i915_gem_object_lock(obj
);
15241 obj
->framebuffer_references
++;
15242 tiling
= i915_gem_object_get_tiling(obj
);
15243 stride
= i915_gem_object_get_stride(obj
);
15244 i915_gem_object_unlock(obj
);
15246 if (mode_cmd
->flags
& DRM_MODE_FB_MODIFIERS
) {
15248 * If there's a fence, enforce that
15249 * the fb modifier and tiling mode match.
15251 if (tiling
!= I915_TILING_NONE
&&
15252 tiling
!= intel_fb_modifier_to_tiling(mode_cmd
->modifier
[0])) {
15253 DRM_DEBUG_KMS("tiling_mode doesn't match fb modifier\n");
15257 if (tiling
== I915_TILING_X
) {
15258 mode_cmd
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
15259 } else if (tiling
== I915_TILING_Y
) {
15260 DRM_DEBUG_KMS("No Y tiling for legacy addfb\n");
15265 if (!drm_any_plane_has_format(&dev_priv
->drm
,
15266 mode_cmd
->pixel_format
,
15267 mode_cmd
->modifier
[0])) {
15268 struct drm_format_name_buf format_name
;
15270 DRM_DEBUG_KMS("unsupported pixel format %s / modifier 0x%llx\n",
15271 drm_get_format_name(mode_cmd
->pixel_format
,
15273 mode_cmd
->modifier
[0]);
15278 * gen2/3 display engine uses the fence if present,
15279 * so the tiling mode must match the fb modifier exactly.
15281 if (INTEL_GEN(dev_priv
) < 4 &&
15282 tiling
!= intel_fb_modifier_to_tiling(mode_cmd
->modifier
[0])) {
15283 DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n");
15287 max_stride
= intel_fb_max_stride(dev_priv
, mode_cmd
->pixel_format
,
15288 mode_cmd
->modifier
[0]);
15289 if (mode_cmd
->pitches
[0] > max_stride
) {
15290 DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n",
15291 mode_cmd
->modifier
[0] != DRM_FORMAT_MOD_LINEAR
?
15292 "tiled" : "linear",
15293 mode_cmd
->pitches
[0], max_stride
);
15298 * If there's a fence, enforce that
15299 * the fb pitch and fence stride match.
15301 if (tiling
!= I915_TILING_NONE
&& mode_cmd
->pitches
[0] != stride
) {
15302 DRM_DEBUG_KMS("pitch (%d) must match tiling stride (%d)\n",
15303 mode_cmd
->pitches
[0], stride
);
15307 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
15308 if (mode_cmd
->offsets
[0] != 0)
15311 drm_helper_mode_fill_fb_struct(&dev_priv
->drm
, fb
, mode_cmd
);
15313 for (i
= 0; i
< fb
->format
->num_planes
; i
++) {
15314 u32 stride_alignment
;
15316 if (mode_cmd
->handles
[i
] != mode_cmd
->handles
[0]) {
15317 DRM_DEBUG_KMS("bad plane %d handle\n", i
);
15321 stride_alignment
= intel_fb_stride_alignment(fb
, i
);
15324 * Display WA #0531: skl,bxt,kbl,glk
15326 * Render decompression and plane width > 3840
15327 * combined with horizontal panning requires the
15328 * plane stride to be a multiple of 4. We'll just
15329 * require the entire fb to accommodate that to avoid
15330 * potential runtime errors at plane configuration time.
15332 if (IS_GEN(dev_priv
, 9) && i
== 0 && fb
->width
> 3840 &&
15333 is_ccs_modifier(fb
->modifier
))
15334 stride_alignment
*= 4;
15336 if (fb
->pitches
[i
] & (stride_alignment
- 1)) {
15337 DRM_DEBUG_KMS("plane %d pitch (%d) must be at least %u byte aligned\n",
15338 i
, fb
->pitches
[i
], stride_alignment
);
15342 fb
->obj
[i
] = &obj
->base
;
15345 ret
= intel_fill_fb_info(dev_priv
, fb
);
15349 ret
= drm_framebuffer_init(&dev_priv
->drm
, fb
, &intel_fb_funcs
);
15351 DRM_ERROR("framebuffer init failed %d\n", ret
);
15358 i915_gem_object_lock(obj
);
15359 obj
->framebuffer_references
--;
15360 i915_gem_object_unlock(obj
);
15364 static struct drm_framebuffer
*
15365 intel_user_framebuffer_create(struct drm_device
*dev
,
15366 struct drm_file
*filp
,
15367 const struct drm_mode_fb_cmd2
*user_mode_cmd
)
15369 struct drm_framebuffer
*fb
;
15370 struct drm_i915_gem_object
*obj
;
15371 struct drm_mode_fb_cmd2 mode_cmd
= *user_mode_cmd
;
15373 obj
= i915_gem_object_lookup(filp
, mode_cmd
.handles
[0]);
15375 return ERR_PTR(-ENOENT
);
15377 fb
= intel_framebuffer_create(obj
, &mode_cmd
);
15379 i915_gem_object_put(obj
);
15384 static void intel_atomic_state_free(struct drm_atomic_state
*state
)
15386 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
15388 drm_atomic_state_default_release(state
);
15390 i915_sw_fence_fini(&intel_state
->commit_ready
);
15395 static enum drm_mode_status
15396 intel_mode_valid(struct drm_device
*dev
,
15397 const struct drm_display_mode
*mode
)
15399 struct drm_i915_private
*dev_priv
= to_i915(dev
);
15400 int hdisplay_max
, htotal_max
;
15401 int vdisplay_max
, vtotal_max
;
15404 * Can't reject DBLSCAN here because Xorg ddxen can add piles
15405 * of DBLSCAN modes to the output's mode list when they detect
15406 * the scaling mode property on the connector. And they don't
15407 * ask the kernel to validate those modes in any way until
15408 * modeset time at which point the client gets a protocol error.
15409 * So in order to not upset those clients we silently ignore the
15410 * DBLSCAN flag on such connectors. For other connectors we will
15411 * reject modes with the DBLSCAN flag in encoder->compute_config().
15412 * And we always reject DBLSCAN modes in connector->mode_valid()
15413 * as we never want such modes on the connector's mode list.
15416 if (mode
->vscan
> 1)
15417 return MODE_NO_VSCAN
;
15419 if (mode
->flags
& DRM_MODE_FLAG_HSKEW
)
15420 return MODE_H_ILLEGAL
;
15422 if (mode
->flags
& (DRM_MODE_FLAG_CSYNC
|
15423 DRM_MODE_FLAG_NCSYNC
|
15424 DRM_MODE_FLAG_PCSYNC
))
15427 if (mode
->flags
& (DRM_MODE_FLAG_BCAST
|
15428 DRM_MODE_FLAG_PIXMUX
|
15429 DRM_MODE_FLAG_CLKDIV2
))
15432 if (INTEL_GEN(dev_priv
) >= 9 ||
15433 IS_BROADWELL(dev_priv
) || IS_HASWELL(dev_priv
)) {
15434 hdisplay_max
= 8192; /* FDI max 4096 handled elsewhere */
15435 vdisplay_max
= 4096;
15438 } else if (INTEL_GEN(dev_priv
) >= 3) {
15439 hdisplay_max
= 4096;
15440 vdisplay_max
= 4096;
15444 hdisplay_max
= 2048;
15445 vdisplay_max
= 2048;
15450 if (mode
->hdisplay
> hdisplay_max
||
15451 mode
->hsync_start
> htotal_max
||
15452 mode
->hsync_end
> htotal_max
||
15453 mode
->htotal
> htotal_max
)
15454 return MODE_H_ILLEGAL
;
15456 if (mode
->vdisplay
> vdisplay_max
||
15457 mode
->vsync_start
> vtotal_max
||
15458 mode
->vsync_end
> vtotal_max
||
15459 mode
->vtotal
> vtotal_max
)
15460 return MODE_V_ILLEGAL
;
15465 static const struct drm_mode_config_funcs intel_mode_funcs
= {
15466 .fb_create
= intel_user_framebuffer_create
,
15467 .get_format_info
= intel_get_format_info
,
15468 .output_poll_changed
= intel_fbdev_output_poll_changed
,
15469 .mode_valid
= intel_mode_valid
,
15470 .atomic_check
= intel_atomic_check
,
15471 .atomic_commit
= intel_atomic_commit
,
15472 .atomic_state_alloc
= intel_atomic_state_alloc
,
15473 .atomic_state_clear
= intel_atomic_state_clear
,
15474 .atomic_state_free
= intel_atomic_state_free
,
15478 * intel_init_display_hooks - initialize the display modesetting hooks
15479 * @dev_priv: device private
15481 void intel_init_display_hooks(struct drm_i915_private
*dev_priv
)
15483 intel_init_cdclk_hooks(dev_priv
);
15485 if (INTEL_GEN(dev_priv
) >= 9) {
15486 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
15487 dev_priv
->display
.get_initial_plane_config
=
15488 skylake_get_initial_plane_config
;
15489 dev_priv
->display
.crtc_compute_clock
=
15490 haswell_crtc_compute_clock
;
15491 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
15492 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
15493 } else if (HAS_DDI(dev_priv
)) {
15494 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
15495 dev_priv
->display
.get_initial_plane_config
=
15496 i9xx_get_initial_plane_config
;
15497 dev_priv
->display
.crtc_compute_clock
=
15498 haswell_crtc_compute_clock
;
15499 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
15500 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
15501 } else if (HAS_PCH_SPLIT(dev_priv
)) {
15502 dev_priv
->display
.get_pipe_config
= ironlake_get_pipe_config
;
15503 dev_priv
->display
.get_initial_plane_config
=
15504 i9xx_get_initial_plane_config
;
15505 dev_priv
->display
.crtc_compute_clock
=
15506 ironlake_crtc_compute_clock
;
15507 dev_priv
->display
.crtc_enable
= ironlake_crtc_enable
;
15508 dev_priv
->display
.crtc_disable
= ironlake_crtc_disable
;
15509 } else if (IS_CHERRYVIEW(dev_priv
)) {
15510 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
15511 dev_priv
->display
.get_initial_plane_config
=
15512 i9xx_get_initial_plane_config
;
15513 dev_priv
->display
.crtc_compute_clock
= chv_crtc_compute_clock
;
15514 dev_priv
->display
.crtc_enable
= valleyview_crtc_enable
;
15515 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
15516 } else if (IS_VALLEYVIEW(dev_priv
)) {
15517 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
15518 dev_priv
->display
.get_initial_plane_config
=
15519 i9xx_get_initial_plane_config
;
15520 dev_priv
->display
.crtc_compute_clock
= vlv_crtc_compute_clock
;
15521 dev_priv
->display
.crtc_enable
= valleyview_crtc_enable
;
15522 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
15523 } else if (IS_G4X(dev_priv
)) {
15524 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
15525 dev_priv
->display
.get_initial_plane_config
=
15526 i9xx_get_initial_plane_config
;
15527 dev_priv
->display
.crtc_compute_clock
= g4x_crtc_compute_clock
;
15528 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
15529 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
15530 } else if (IS_PINEVIEW(dev_priv
)) {
15531 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
15532 dev_priv
->display
.get_initial_plane_config
=
15533 i9xx_get_initial_plane_config
;
15534 dev_priv
->display
.crtc_compute_clock
= pnv_crtc_compute_clock
;
15535 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
15536 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
15537 } else if (!IS_GEN(dev_priv
, 2)) {
15538 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
15539 dev_priv
->display
.get_initial_plane_config
=
15540 i9xx_get_initial_plane_config
;
15541 dev_priv
->display
.crtc_compute_clock
= i9xx_crtc_compute_clock
;
15542 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
15543 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
15545 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
15546 dev_priv
->display
.get_initial_plane_config
=
15547 i9xx_get_initial_plane_config
;
15548 dev_priv
->display
.crtc_compute_clock
= i8xx_crtc_compute_clock
;
15549 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
15550 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
15553 if (IS_GEN(dev_priv
, 5)) {
15554 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
15555 } else if (IS_GEN(dev_priv
, 6)) {
15556 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
15557 } else if (IS_IVYBRIDGE(dev_priv
)) {
15558 /* FIXME: detect B0+ stepping and use auto training */
15559 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
15560 } else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
15561 dev_priv
->display
.fdi_link_train
= hsw_fdi_link_train
;
15564 if (INTEL_GEN(dev_priv
) >= 9)
15565 dev_priv
->display
.update_crtcs
= skl_update_crtcs
;
15567 dev_priv
->display
.update_crtcs
= intel_update_crtcs
;
15570 static i915_reg_t
i915_vgacntrl_reg(struct drm_i915_private
*dev_priv
)
15572 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
15573 return VLV_VGACNTRL
;
15574 else if (INTEL_GEN(dev_priv
) >= 5)
15575 return CPU_VGACNTRL
;
15580 /* Disable the VGA plane that we never use */
15581 static void i915_disable_vga(struct drm_i915_private
*dev_priv
)
15583 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
15585 i915_reg_t vga_reg
= i915_vgacntrl_reg(dev_priv
);
15587 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15588 vga_get_uninterruptible(pdev
, VGA_RSRC_LEGACY_IO
);
15589 outb(SR01
, VGA_SR_INDEX
);
15590 sr1
= inb(VGA_SR_DATA
);
15591 outb(sr1
| 1<<5, VGA_SR_DATA
);
15592 vga_put(pdev
, VGA_RSRC_LEGACY_IO
);
15595 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
15596 POSTING_READ(vga_reg
);
15599 void intel_modeset_init_hw(struct drm_device
*dev
)
15601 struct drm_i915_private
*dev_priv
= to_i915(dev
);
15603 intel_update_cdclk(dev_priv
);
15604 intel_dump_cdclk_state(&dev_priv
->cdclk
.hw
, "Current CDCLK");
15605 dev_priv
->cdclk
.logical
= dev_priv
->cdclk
.actual
= dev_priv
->cdclk
.hw
;
15609 * Calculate what we think the watermarks should be for the state we've read
15610 * out of the hardware and then immediately program those watermarks so that
15611 * we ensure the hardware settings match our internal state.
15613 * We can calculate what we think WM's should be by creating a duplicate of the
15614 * current state (which was constructed during hardware readout) and running it
15615 * through the atomic check code to calculate new watermark values in the
15618 static void sanitize_watermarks(struct drm_device
*dev
)
15620 struct drm_i915_private
*dev_priv
= to_i915(dev
);
15621 struct drm_atomic_state
*state
;
15622 struct intel_atomic_state
*intel_state
;
15623 struct drm_crtc
*crtc
;
15624 struct drm_crtc_state
*cstate
;
15625 struct drm_modeset_acquire_ctx ctx
;
15629 /* Only supported on platforms that use atomic watermark design */
15630 if (!dev_priv
->display
.optimize_watermarks
)
15634 * We need to hold connection_mutex before calling duplicate_state so
15635 * that the connector loop is protected.
15637 drm_modeset_acquire_init(&ctx
, 0);
15639 ret
= drm_modeset_lock_all_ctx(dev
, &ctx
);
15640 if (ret
== -EDEADLK
) {
15641 drm_modeset_backoff(&ctx
);
15643 } else if (WARN_ON(ret
)) {
15647 state
= drm_atomic_helper_duplicate_state(dev
, &ctx
);
15648 if (WARN_ON(IS_ERR(state
)))
15651 intel_state
= to_intel_atomic_state(state
);
15654 * Hardware readout is the only time we don't want to calculate
15655 * intermediate watermarks (since we don't trust the current
15658 if (!HAS_GMCH(dev_priv
))
15659 intel_state
->skip_intermediate_wm
= true;
15661 ret
= intel_atomic_check(dev
, state
);
15664 * If we fail here, it means that the hardware appears to be
15665 * programmed in a way that shouldn't be possible, given our
15666 * understanding of watermark requirements. This might mean a
15667 * mistake in the hardware readout code or a mistake in the
15668 * watermark calculations for a given platform. Raise a WARN
15669 * so that this is noticeable.
15671 * If this actually happens, we'll have to just leave the
15672 * BIOS-programmed watermarks untouched and hope for the best.
15674 WARN(true, "Could not determine valid watermarks for inherited state\n");
15678 /* Write calculated watermark values back */
15679 for_each_new_crtc_in_state(state
, crtc
, cstate
, i
) {
15680 struct intel_crtc_state
*cs
= to_intel_crtc_state(cstate
);
15682 cs
->wm
.need_postvbl_update
= true;
15683 dev_priv
->display
.optimize_watermarks(intel_state
, cs
);
15685 to_intel_crtc_state(crtc
->state
)->wm
= cs
->wm
;
15689 drm_atomic_state_put(state
);
15691 drm_modeset_drop_locks(&ctx
);
15692 drm_modeset_acquire_fini(&ctx
);
15695 static void intel_update_fdi_pll_freq(struct drm_i915_private
*dev_priv
)
15697 if (IS_GEN(dev_priv
, 5)) {
15699 I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
;
15701 dev_priv
->fdi_pll_freq
= (fdi_pll_clk
+ 2) * 10000;
15702 } else if (IS_GEN(dev_priv
, 6) || IS_IVYBRIDGE(dev_priv
)) {
15703 dev_priv
->fdi_pll_freq
= 270000;
15708 DRM_DEBUG_DRIVER("FDI PLL freq=%d\n", dev_priv
->fdi_pll_freq
);
15711 static int intel_initial_commit(struct drm_device
*dev
)
15713 struct drm_atomic_state
*state
= NULL
;
15714 struct drm_modeset_acquire_ctx ctx
;
15715 struct drm_crtc
*crtc
;
15716 struct drm_crtc_state
*crtc_state
;
15719 state
= drm_atomic_state_alloc(dev
);
15723 drm_modeset_acquire_init(&ctx
, 0);
15726 state
->acquire_ctx
= &ctx
;
15728 drm_for_each_crtc(crtc
, dev
) {
15729 crtc_state
= drm_atomic_get_crtc_state(state
, crtc
);
15730 if (IS_ERR(crtc_state
)) {
15731 ret
= PTR_ERR(crtc_state
);
15735 if (crtc_state
->active
) {
15736 ret
= drm_atomic_add_affected_planes(state
, crtc
);
15741 * FIXME hack to force a LUT update to avoid the
15742 * plane update forcing the pipe gamma on without
15743 * having a proper LUT loaded. Remove once we
15744 * have readout for pipe gamma enable.
15746 crtc_state
->color_mgmt_changed
= true;
15750 ret
= drm_atomic_commit(state
);
15753 if (ret
== -EDEADLK
) {
15754 drm_atomic_state_clear(state
);
15755 drm_modeset_backoff(&ctx
);
15759 drm_atomic_state_put(state
);
15761 drm_modeset_drop_locks(&ctx
);
15762 drm_modeset_acquire_fini(&ctx
);
15767 int intel_modeset_init(struct drm_device
*dev
)
15769 struct drm_i915_private
*dev_priv
= to_i915(dev
);
15770 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
15772 struct intel_crtc
*crtc
;
15775 dev_priv
->modeset_wq
= alloc_ordered_workqueue("i915_modeset", 0);
15777 drm_mode_config_init(dev
);
15779 dev
->mode_config
.min_width
= 0;
15780 dev
->mode_config
.min_height
= 0;
15782 dev
->mode_config
.preferred_depth
= 24;
15783 dev
->mode_config
.prefer_shadow
= 1;
15785 dev
->mode_config
.allow_fb_modifiers
= true;
15787 dev
->mode_config
.funcs
= &intel_mode_funcs
;
15789 init_llist_head(&dev_priv
->atomic_helper
.free_list
);
15790 INIT_WORK(&dev_priv
->atomic_helper
.free_work
,
15791 intel_atomic_helper_free_state_worker
);
15793 intel_init_quirks(dev_priv
);
15795 intel_fbc_init(dev_priv
);
15797 intel_init_pm(dev_priv
);
15800 * There may be no VBT; and if the BIOS enabled SSC we can
15801 * just keep using it to avoid unnecessary flicker. Whereas if the
15802 * BIOS isn't using it, don't assume it will work even if the VBT
15803 * indicates as much.
15805 if (HAS_PCH_IBX(dev_priv
) || HAS_PCH_CPT(dev_priv
)) {
15806 bool bios_lvds_use_ssc
= !!(I915_READ(PCH_DREF_CONTROL
) &
15809 if (dev_priv
->vbt
.lvds_use_ssc
!= bios_lvds_use_ssc
) {
15810 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15811 bios_lvds_use_ssc
? "en" : "dis",
15812 dev_priv
->vbt
.lvds_use_ssc
? "en" : "dis");
15813 dev_priv
->vbt
.lvds_use_ssc
= bios_lvds_use_ssc
;
15817 /* maximum framebuffer dimensions */
15818 if (IS_GEN(dev_priv
, 2)) {
15819 dev
->mode_config
.max_width
= 2048;
15820 dev
->mode_config
.max_height
= 2048;
15821 } else if (IS_GEN(dev_priv
, 3)) {
15822 dev
->mode_config
.max_width
= 4096;
15823 dev
->mode_config
.max_height
= 4096;
15825 dev
->mode_config
.max_width
= 8192;
15826 dev
->mode_config
.max_height
= 8192;
15829 if (IS_I845G(dev_priv
) || IS_I865G(dev_priv
)) {
15830 dev
->mode_config
.cursor_width
= IS_I845G(dev_priv
) ? 64 : 512;
15831 dev
->mode_config
.cursor_height
= 1023;
15832 } else if (IS_GEN(dev_priv
, 2)) {
15833 dev
->mode_config
.cursor_width
= 64;
15834 dev
->mode_config
.cursor_height
= 64;
15836 dev
->mode_config
.cursor_width
= 256;
15837 dev
->mode_config
.cursor_height
= 256;
15840 dev
->mode_config
.fb_base
= ggtt
->gmadr
.start
;
15842 DRM_DEBUG_KMS("%d display pipe%s available.\n",
15843 INTEL_INFO(dev_priv
)->num_pipes
,
15844 INTEL_INFO(dev_priv
)->num_pipes
> 1 ? "s" : "");
15846 for_each_pipe(dev_priv
, pipe
) {
15847 ret
= intel_crtc_init(dev_priv
, pipe
);
15849 drm_mode_config_cleanup(dev
);
15854 intel_shared_dpll_init(dev
);
15855 intel_update_fdi_pll_freq(dev_priv
);
15857 intel_update_czclk(dev_priv
);
15858 intel_modeset_init_hw(dev
);
15860 intel_hdcp_component_init(dev_priv
);
15862 if (dev_priv
->max_cdclk_freq
== 0)
15863 intel_update_max_cdclk(dev_priv
);
15865 /* Just disable it once at startup */
15866 i915_disable_vga(dev_priv
);
15867 intel_setup_outputs(dev_priv
);
15869 drm_modeset_lock_all(dev
);
15870 intel_modeset_setup_hw_state(dev
, dev
->mode_config
.acquire_ctx
);
15871 drm_modeset_unlock_all(dev
);
15873 for_each_intel_crtc(dev
, crtc
) {
15874 struct intel_initial_plane_config plane_config
= {};
15880 * Note that reserving the BIOS fb up front prevents us
15881 * from stuffing other stolen allocations like the ring
15882 * on top. This prevents some ugliness at boot time, and
15883 * can even allow for smooth boot transitions if the BIOS
15884 * fb is large enough for the active pipe configuration.
15886 dev_priv
->display
.get_initial_plane_config(crtc
,
15890 * If the fb is shared between multiple heads, we'll
15891 * just get the first one.
15893 intel_find_initial_plane_obj(crtc
, &plane_config
);
15897 * Make sure hardware watermarks really match the state we read out.
15898 * Note that we need to do this after reconstructing the BIOS fb's
15899 * since the watermark calculation done here will use pstate->fb.
15901 if (!HAS_GMCH(dev_priv
))
15902 sanitize_watermarks(dev
);
15905 * Force all active planes to recompute their states. So that on
15906 * mode_setcrtc after probe, all the intel_plane_state variables
15907 * are already calculated and there is no assert_plane warnings
15910 ret
= intel_initial_commit(dev
);
15912 DRM_DEBUG_KMS("Initial commit in probe failed.\n");
15917 void i830_enable_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
15919 struct intel_crtc
*crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
15920 /* 640x480@60Hz, ~25175 kHz */
15921 struct dpll clock
= {
15931 WARN_ON(i9xx_calc_dpll_params(48000, &clock
) != 25154);
15933 DRM_DEBUG_KMS("enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
15934 pipe_name(pipe
), clock
.vco
, clock
.dot
);
15936 fp
= i9xx_dpll_compute_fp(&clock
);
15937 dpll
= DPLL_DVO_2X_MODE
|
15938 DPLL_VGA_MODE_DIS
|
15939 ((clock
.p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
) |
15940 PLL_P2_DIVIDE_BY_4
|
15941 PLL_REF_INPUT_DREFCLK
|
15944 I915_WRITE(FP0(pipe
), fp
);
15945 I915_WRITE(FP1(pipe
), fp
);
15947 I915_WRITE(HTOTAL(pipe
), (640 - 1) | ((800 - 1) << 16));
15948 I915_WRITE(HBLANK(pipe
), (640 - 1) | ((800 - 1) << 16));
15949 I915_WRITE(HSYNC(pipe
), (656 - 1) | ((752 - 1) << 16));
15950 I915_WRITE(VTOTAL(pipe
), (480 - 1) | ((525 - 1) << 16));
15951 I915_WRITE(VBLANK(pipe
), (480 - 1) | ((525 - 1) << 16));
15952 I915_WRITE(VSYNC(pipe
), (490 - 1) | ((492 - 1) << 16));
15953 I915_WRITE(PIPESRC(pipe
), ((640 - 1) << 16) | (480 - 1));
15956 * Apparently we need to have VGA mode enabled prior to changing
15957 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
15958 * dividers, even though the register value does change.
15960 I915_WRITE(DPLL(pipe
), dpll
& ~DPLL_VGA_MODE_DIS
);
15961 I915_WRITE(DPLL(pipe
), dpll
);
15963 /* Wait for the clocks to stabilize. */
15964 POSTING_READ(DPLL(pipe
));
15967 /* The pixel multiplier can only be updated once the
15968 * DPLL is enabled and the clocks are stable.
15970 * So write it again.
15972 I915_WRITE(DPLL(pipe
), dpll
);
15974 /* We do this three times for luck */
15975 for (i
= 0; i
< 3 ; i
++) {
15976 I915_WRITE(DPLL(pipe
), dpll
);
15977 POSTING_READ(DPLL(pipe
));
15978 udelay(150); /* wait for warmup */
15981 I915_WRITE(PIPECONF(pipe
), PIPECONF_ENABLE
| PIPECONF_PROGRESSIVE
);
15982 POSTING_READ(PIPECONF(pipe
));
15984 intel_wait_for_pipe_scanline_moving(crtc
);
15987 void i830_disable_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
15989 struct intel_crtc
*crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
15991 DRM_DEBUG_KMS("disabling pipe %c due to force quirk\n",
15994 WARN_ON(I915_READ(DSPCNTR(PLANE_A
)) & DISPLAY_PLANE_ENABLE
);
15995 WARN_ON(I915_READ(DSPCNTR(PLANE_B
)) & DISPLAY_PLANE_ENABLE
);
15996 WARN_ON(I915_READ(DSPCNTR(PLANE_C
)) & DISPLAY_PLANE_ENABLE
);
15997 WARN_ON(I915_READ(CURCNTR(PIPE_A
)) & MCURSOR_MODE
);
15998 WARN_ON(I915_READ(CURCNTR(PIPE_B
)) & MCURSOR_MODE
);
16000 I915_WRITE(PIPECONF(pipe
), 0);
16001 POSTING_READ(PIPECONF(pipe
));
16003 intel_wait_for_pipe_scanline_stopped(crtc
);
16005 I915_WRITE(DPLL(pipe
), DPLL_VGA_MODE_DIS
);
16006 POSTING_READ(DPLL(pipe
));
16010 intel_sanitize_plane_mapping(struct drm_i915_private
*dev_priv
)
16012 struct intel_crtc
*crtc
;
16014 if (INTEL_GEN(dev_priv
) >= 4)
16017 for_each_intel_crtc(&dev_priv
->drm
, crtc
) {
16018 struct intel_plane
*plane
=
16019 to_intel_plane(crtc
->base
.primary
);
16020 struct intel_crtc
*plane_crtc
;
16023 if (!plane
->get_hw_state(plane
, &pipe
))
16026 if (pipe
== crtc
->pipe
)
16029 DRM_DEBUG_KMS("[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n",
16030 plane
->base
.base
.id
, plane
->base
.name
);
16032 plane_crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
16033 intel_plane_disable_noatomic(plane_crtc
, plane
);
16037 static bool intel_crtc_has_encoders(struct intel_crtc
*crtc
)
16039 struct drm_device
*dev
= crtc
->base
.dev
;
16040 struct intel_encoder
*encoder
;
16042 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
)
16048 static struct intel_connector
*intel_encoder_find_connector(struct intel_encoder
*encoder
)
16050 struct drm_device
*dev
= encoder
->base
.dev
;
16051 struct intel_connector
*connector
;
16053 for_each_connector_on_encoder(dev
, &encoder
->base
, connector
)
16059 static bool has_pch_trancoder(struct drm_i915_private
*dev_priv
,
16060 enum pipe pch_transcoder
)
16062 return HAS_PCH_IBX(dev_priv
) || HAS_PCH_CPT(dev_priv
) ||
16063 (HAS_PCH_LPT_H(dev_priv
) && pch_transcoder
== PIPE_A
);
16066 static void intel_sanitize_crtc(struct intel_crtc
*crtc
,
16067 struct drm_modeset_acquire_ctx
*ctx
)
16069 struct drm_device
*dev
= crtc
->base
.dev
;
16070 struct drm_i915_private
*dev_priv
= to_i915(dev
);
16071 struct intel_crtc_state
*crtc_state
= to_intel_crtc_state(crtc
->base
.state
);
16072 enum transcoder cpu_transcoder
= crtc_state
->cpu_transcoder
;
16074 /* Clear any frame start delays used for debugging left by the BIOS */
16075 if (crtc
->active
&& !transcoder_is_dsi(cpu_transcoder
)) {
16076 i915_reg_t reg
= PIPECONF(cpu_transcoder
);
16079 I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
16082 if (crtc_state
->base
.active
) {
16083 struct intel_plane
*plane
;
16085 /* Disable everything but the primary plane */
16086 for_each_intel_plane_on_crtc(dev
, crtc
, plane
) {
16087 const struct intel_plane_state
*plane_state
=
16088 to_intel_plane_state(plane
->base
.state
);
16090 if (plane_state
->base
.visible
&&
16091 plane
->base
.type
!= DRM_PLANE_TYPE_PRIMARY
)
16092 intel_plane_disable_noatomic(crtc
, plane
);
16096 * Disable any background color set by the BIOS, but enable the
16097 * gamma and CSC to match how we program our planes.
16099 if (INTEL_GEN(dev_priv
) >= 9)
16100 I915_WRITE(SKL_BOTTOM_COLOR(crtc
->pipe
),
16101 SKL_BOTTOM_COLOR_GAMMA_ENABLE
|
16102 SKL_BOTTOM_COLOR_CSC_ENABLE
);
16105 /* Adjust the state of the output pipe according to whether we
16106 * have active connectors/encoders. */
16107 if (crtc_state
->base
.active
&& !intel_crtc_has_encoders(crtc
))
16108 intel_crtc_disable_noatomic(&crtc
->base
, ctx
);
16110 if (crtc_state
->base
.active
|| HAS_GMCH(dev_priv
)) {
16112 * We start out with underrun reporting disabled to avoid races.
16113 * For correct bookkeeping mark this on active crtcs.
16115 * Also on gmch platforms we dont have any hardware bits to
16116 * disable the underrun reporting. Which means we need to start
16117 * out with underrun reporting disabled also on inactive pipes,
16118 * since otherwise we'll complain about the garbage we read when
16119 * e.g. coming up after runtime pm.
16121 * No protection against concurrent access is required - at
16122 * worst a fifo underrun happens which also sets this to false.
16124 crtc
->cpu_fifo_underrun_disabled
= true;
16126 * We track the PCH trancoder underrun reporting state
16127 * within the crtc. With crtc for pipe A housing the underrun
16128 * reporting state for PCH transcoder A, crtc for pipe B housing
16129 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
16130 * and marking underrun reporting as disabled for the non-existing
16131 * PCH transcoders B and C would prevent enabling the south
16132 * error interrupt (see cpt_can_enable_serr_int()).
16134 if (has_pch_trancoder(dev_priv
, crtc
->pipe
))
16135 crtc
->pch_fifo_underrun_disabled
= true;
16139 static bool has_bogus_dpll_config(const struct intel_crtc_state
*crtc_state
)
16141 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->base
.crtc
->dev
);
16144 * Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram
16145 * the hardware when a high res displays plugged in. DPLL P
16146 * divider is zero, and the pipe timings are bonkers. We'll
16147 * try to disable everything in that case.
16149 * FIXME would be nice to be able to sanitize this state
16150 * without several WARNs, but for now let's take the easy
16153 return IS_GEN(dev_priv
, 6) &&
16154 crtc_state
->base
.active
&&
16155 crtc_state
->shared_dpll
&&
16156 crtc_state
->port_clock
== 0;
16159 static void intel_sanitize_encoder(struct intel_encoder
*encoder
)
16161 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
16162 struct intel_connector
*connector
;
16163 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
16164 struct intel_crtc_state
*crtc_state
= crtc
?
16165 to_intel_crtc_state(crtc
->base
.state
) : NULL
;
16167 /* We need to check both for a crtc link (meaning that the
16168 * encoder is active and trying to read from a pipe) and the
16169 * pipe itself being active. */
16170 bool has_active_crtc
= crtc_state
&&
16171 crtc_state
->base
.active
;
16173 if (crtc_state
&& has_bogus_dpll_config(crtc_state
)) {
16174 DRM_DEBUG_KMS("BIOS has misprogrammed the hardware. Disabling pipe %c\n",
16175 pipe_name(crtc
->pipe
));
16176 has_active_crtc
= false;
16179 connector
= intel_encoder_find_connector(encoder
);
16180 if (connector
&& !has_active_crtc
) {
16181 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
16182 encoder
->base
.base
.id
,
16183 encoder
->base
.name
);
16185 /* Connector is active, but has no active pipe. This is
16186 * fallout from our resume register restoring. Disable
16187 * the encoder manually again. */
16189 struct drm_encoder
*best_encoder
;
16191 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
16192 encoder
->base
.base
.id
,
16193 encoder
->base
.name
);
16195 /* avoid oopsing in case the hooks consult best_encoder */
16196 best_encoder
= connector
->base
.state
->best_encoder
;
16197 connector
->base
.state
->best_encoder
= &encoder
->base
;
16199 if (encoder
->disable
)
16200 encoder
->disable(encoder
, crtc_state
,
16201 connector
->base
.state
);
16202 if (encoder
->post_disable
)
16203 encoder
->post_disable(encoder
, crtc_state
,
16204 connector
->base
.state
);
16206 connector
->base
.state
->best_encoder
= best_encoder
;
16208 encoder
->base
.crtc
= NULL
;
16210 /* Inconsistent output/port/pipe state happens presumably due to
16211 * a bug in one of the get_hw_state functions. Or someplace else
16212 * in our code, like the register restore mess on resume. Clamp
16213 * things to off as a safer default. */
16215 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
16216 connector
->base
.encoder
= NULL
;
16219 /* notify opregion of the sanitized encoder state */
16220 intel_opregion_notify_encoder(encoder
, connector
&& has_active_crtc
);
16222 if (INTEL_GEN(dev_priv
) >= 11)
16223 icl_sanitize_encoder_pll_mapping(encoder
);
16226 void i915_redisable_vga_power_on(struct drm_i915_private
*dev_priv
)
16228 i915_reg_t vga_reg
= i915_vgacntrl_reg(dev_priv
);
16230 if (!(I915_READ(vga_reg
) & VGA_DISP_DISABLE
)) {
16231 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
16232 i915_disable_vga(dev_priv
);
16236 void i915_redisable_vga(struct drm_i915_private
*dev_priv
)
16238 intel_wakeref_t wakeref
;
16241 * This function can be called both from intel_modeset_setup_hw_state or
16242 * at a very early point in our resume sequence, where the power well
16243 * structures are not yet restored. Since this function is at a very
16244 * paranoid "someone might have enabled VGA while we were not looking"
16245 * level, just check if the power well is enabled instead of trying to
16246 * follow the "don't touch the power well if we don't need it" policy
16247 * the rest of the driver uses.
16249 wakeref
= intel_display_power_get_if_enabled(dev_priv
,
16254 i915_redisable_vga_power_on(dev_priv
);
16256 intel_display_power_put(dev_priv
, POWER_DOMAIN_VGA
, wakeref
);
16259 /* FIXME read out full plane state for all planes */
16260 static void readout_plane_state(struct drm_i915_private
*dev_priv
)
16262 struct intel_plane
*plane
;
16263 struct intel_crtc
*crtc
;
16265 for_each_intel_plane(&dev_priv
->drm
, plane
) {
16266 struct intel_plane_state
*plane_state
=
16267 to_intel_plane_state(plane
->base
.state
);
16268 struct intel_crtc_state
*crtc_state
;
16269 enum pipe pipe
= PIPE_A
;
16272 visible
= plane
->get_hw_state(plane
, &pipe
);
16274 crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
16275 crtc_state
= to_intel_crtc_state(crtc
->base
.state
);
16277 intel_set_plane_visible(crtc_state
, plane_state
, visible
);
16279 DRM_DEBUG_KMS("[PLANE:%d:%s] hw state readout: %s, pipe %c\n",
16280 plane
->base
.base
.id
, plane
->base
.name
,
16281 enableddisabled(visible
), pipe_name(pipe
));
16284 for_each_intel_crtc(&dev_priv
->drm
, crtc
) {
16285 struct intel_crtc_state
*crtc_state
=
16286 to_intel_crtc_state(crtc
->base
.state
);
16288 fixup_active_planes(crtc_state
);
16292 static void intel_modeset_readout_hw_state(struct drm_device
*dev
)
16294 struct drm_i915_private
*dev_priv
= to_i915(dev
);
16296 struct intel_crtc
*crtc
;
16297 struct intel_encoder
*encoder
;
16298 struct intel_connector
*connector
;
16299 struct drm_connector_list_iter conn_iter
;
16302 dev_priv
->active_crtcs
= 0;
16304 for_each_intel_crtc(dev
, crtc
) {
16305 struct intel_crtc_state
*crtc_state
=
16306 to_intel_crtc_state(crtc
->base
.state
);
16308 __drm_atomic_helper_crtc_destroy_state(&crtc_state
->base
);
16309 memset(crtc_state
, 0, sizeof(*crtc_state
));
16310 crtc_state
->base
.crtc
= &crtc
->base
;
16312 crtc_state
->base
.active
= crtc_state
->base
.enable
=
16313 dev_priv
->display
.get_pipe_config(crtc
, crtc_state
);
16315 crtc
->base
.enabled
= crtc_state
->base
.enable
;
16316 crtc
->active
= crtc_state
->base
.active
;
16318 if (crtc_state
->base
.active
)
16319 dev_priv
->active_crtcs
|= 1 << crtc
->pipe
;
16321 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
16322 crtc
->base
.base
.id
, crtc
->base
.name
,
16323 enableddisabled(crtc_state
->base
.active
));
16326 readout_plane_state(dev_priv
);
16328 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
16329 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
16331 pll
->on
= pll
->info
->funcs
->get_hw_state(dev_priv
, pll
,
16332 &pll
->state
.hw_state
);
16333 pll
->state
.crtc_mask
= 0;
16334 for_each_intel_crtc(dev
, crtc
) {
16335 struct intel_crtc_state
*crtc_state
=
16336 to_intel_crtc_state(crtc
->base
.state
);
16338 if (crtc_state
->base
.active
&&
16339 crtc_state
->shared_dpll
== pll
)
16340 pll
->state
.crtc_mask
|= 1 << crtc
->pipe
;
16342 pll
->active_mask
= pll
->state
.crtc_mask
;
16344 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
16345 pll
->info
->name
, pll
->state
.crtc_mask
, pll
->on
);
16348 for_each_intel_encoder(dev
, encoder
) {
16351 if (encoder
->get_hw_state(encoder
, &pipe
)) {
16352 struct intel_crtc_state
*crtc_state
;
16354 crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
16355 crtc_state
= to_intel_crtc_state(crtc
->base
.state
);
16357 encoder
->base
.crtc
= &crtc
->base
;
16358 encoder
->get_config(encoder
, crtc_state
);
16360 encoder
->base
.crtc
= NULL
;
16363 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
16364 encoder
->base
.base
.id
, encoder
->base
.name
,
16365 enableddisabled(encoder
->base
.crtc
),
16369 drm_connector_list_iter_begin(dev
, &conn_iter
);
16370 for_each_intel_connector_iter(connector
, &conn_iter
) {
16371 if (connector
->get_hw_state(connector
)) {
16372 connector
->base
.dpms
= DRM_MODE_DPMS_ON
;
16374 encoder
= connector
->encoder
;
16375 connector
->base
.encoder
= &encoder
->base
;
16377 if (encoder
->base
.crtc
&&
16378 encoder
->base
.crtc
->state
->active
) {
16380 * This has to be done during hardware readout
16381 * because anything calling .crtc_disable may
16382 * rely on the connector_mask being accurate.
16384 encoder
->base
.crtc
->state
->connector_mask
|=
16385 drm_connector_mask(&connector
->base
);
16386 encoder
->base
.crtc
->state
->encoder_mask
|=
16387 drm_encoder_mask(&encoder
->base
);
16391 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
16392 connector
->base
.encoder
= NULL
;
16394 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
16395 connector
->base
.base
.id
, connector
->base
.name
,
16396 enableddisabled(connector
->base
.encoder
));
16398 drm_connector_list_iter_end(&conn_iter
);
16400 for_each_intel_crtc(dev
, crtc
) {
16401 struct intel_crtc_state
*crtc_state
=
16402 to_intel_crtc_state(crtc
->base
.state
);
16405 memset(&crtc
->base
.mode
, 0, sizeof(crtc
->base
.mode
));
16406 if (crtc_state
->base
.active
) {
16407 intel_mode_from_pipe_config(&crtc
->base
.mode
, crtc_state
);
16408 crtc
->base
.mode
.hdisplay
= crtc_state
->pipe_src_w
;
16409 crtc
->base
.mode
.vdisplay
= crtc_state
->pipe_src_h
;
16410 intel_mode_from_pipe_config(&crtc_state
->base
.adjusted_mode
, crtc_state
);
16411 WARN_ON(drm_atomic_set_mode_for_crtc(crtc
->base
.state
, &crtc
->base
.mode
));
16414 * The initial mode needs to be set in order to keep
16415 * the atomic core happy. It wants a valid mode if the
16416 * crtc's enabled, so we do the above call.
16418 * But we don't set all the derived state fully, hence
16419 * set a flag to indicate that a full recalculation is
16420 * needed on the next commit.
16422 crtc_state
->base
.mode
.private_flags
= I915_MODE_FLAG_INHERITED
;
16424 intel_crtc_compute_pixel_rate(crtc_state
);
16426 if (dev_priv
->display
.modeset_calc_cdclk
) {
16427 min_cdclk
= intel_crtc_compute_min_cdclk(crtc_state
);
16428 if (WARN_ON(min_cdclk
< 0))
16432 drm_calc_timestamping_constants(&crtc
->base
,
16433 &crtc_state
->base
.adjusted_mode
);
16434 update_scanline_offset(crtc_state
);
16437 dev_priv
->min_cdclk
[crtc
->pipe
] = min_cdclk
;
16438 dev_priv
->min_voltage_level
[crtc
->pipe
] =
16439 crtc_state
->min_voltage_level
;
16441 intel_pipe_config_sanity_check(dev_priv
, crtc_state
);
16446 get_encoder_power_domains(struct drm_i915_private
*dev_priv
)
16448 struct intel_encoder
*encoder
;
16450 for_each_intel_encoder(&dev_priv
->drm
, encoder
) {
16451 struct intel_crtc_state
*crtc_state
;
16453 if (!encoder
->get_power_domains
)
16457 * MST-primary and inactive encoders don't have a crtc state
16458 * and neither of these require any power domain references.
16460 if (!encoder
->base
.crtc
)
16463 crtc_state
= to_intel_crtc_state(encoder
->base
.crtc
->state
);
16464 encoder
->get_power_domains(encoder
, crtc_state
);
16468 static void intel_early_display_was(struct drm_i915_private
*dev_priv
)
16470 /* Display WA #1185 WaDisableDARBFClkGating:cnl,glk */
16471 if (IS_CANNONLAKE(dev_priv
) || IS_GEMINILAKE(dev_priv
))
16472 I915_WRITE(GEN9_CLKGATE_DIS_0
, I915_READ(GEN9_CLKGATE_DIS_0
) |
16475 if (IS_HASWELL(dev_priv
)) {
16477 * WaRsPkgCStateDisplayPMReq:hsw
16478 * System hang if this isn't done before disabling all planes!
16480 I915_WRITE(CHICKEN_PAR1_1
,
16481 I915_READ(CHICKEN_PAR1_1
) | FORCE_ARB_IDLE_PLANES
);
16485 static void ibx_sanitize_pch_hdmi_port(struct drm_i915_private
*dev_priv
,
16486 enum port port
, i915_reg_t hdmi_reg
)
16488 u32 val
= I915_READ(hdmi_reg
);
16490 if (val
& SDVO_ENABLE
||
16491 (val
& SDVO_PIPE_SEL_MASK
) == SDVO_PIPE_SEL(PIPE_A
))
16494 DRM_DEBUG_KMS("Sanitizing transcoder select for HDMI %c\n",
16497 val
&= ~SDVO_PIPE_SEL_MASK
;
16498 val
|= SDVO_PIPE_SEL(PIPE_A
);
16500 I915_WRITE(hdmi_reg
, val
);
16503 static void ibx_sanitize_pch_dp_port(struct drm_i915_private
*dev_priv
,
16504 enum port port
, i915_reg_t dp_reg
)
16506 u32 val
= I915_READ(dp_reg
);
16508 if (val
& DP_PORT_EN
||
16509 (val
& DP_PIPE_SEL_MASK
) == DP_PIPE_SEL(PIPE_A
))
16512 DRM_DEBUG_KMS("Sanitizing transcoder select for DP %c\n",
16515 val
&= ~DP_PIPE_SEL_MASK
;
16516 val
|= DP_PIPE_SEL(PIPE_A
);
16518 I915_WRITE(dp_reg
, val
);
16521 static void ibx_sanitize_pch_ports(struct drm_i915_private
*dev_priv
)
16524 * The BIOS may select transcoder B on some of the PCH
16525 * ports even it doesn't enable the port. This would trip
16526 * assert_pch_dp_disabled() and assert_pch_hdmi_disabled().
16527 * Sanitize the transcoder select bits to prevent that. We
16528 * assume that the BIOS never actually enabled the port,
16529 * because if it did we'd actually have to toggle the port
16530 * on and back off to make the transcoder A select stick
16531 * (see. intel_dp_link_down(), intel_disable_hdmi(),
16532 * intel_disable_sdvo()).
16534 ibx_sanitize_pch_dp_port(dev_priv
, PORT_B
, PCH_DP_B
);
16535 ibx_sanitize_pch_dp_port(dev_priv
, PORT_C
, PCH_DP_C
);
16536 ibx_sanitize_pch_dp_port(dev_priv
, PORT_D
, PCH_DP_D
);
16538 /* PCH SDVOB multiplex with HDMIB */
16539 ibx_sanitize_pch_hdmi_port(dev_priv
, PORT_B
, PCH_HDMIB
);
16540 ibx_sanitize_pch_hdmi_port(dev_priv
, PORT_C
, PCH_HDMIC
);
16541 ibx_sanitize_pch_hdmi_port(dev_priv
, PORT_D
, PCH_HDMID
);
16544 /* Scan out the current hw modeset state,
16545 * and sanitizes it to the current state
16548 intel_modeset_setup_hw_state(struct drm_device
*dev
,
16549 struct drm_modeset_acquire_ctx
*ctx
)
16551 struct drm_i915_private
*dev_priv
= to_i915(dev
);
16552 struct intel_crtc_state
*crtc_state
;
16553 struct intel_encoder
*encoder
;
16554 struct intel_crtc
*crtc
;
16555 intel_wakeref_t wakeref
;
16558 wakeref
= intel_display_power_get(dev_priv
, POWER_DOMAIN_INIT
);
16560 intel_early_display_was(dev_priv
);
16561 intel_modeset_readout_hw_state(dev
);
16563 /* HW state is read out, now we need to sanitize this mess. */
16564 get_encoder_power_domains(dev_priv
);
16566 if (HAS_PCH_IBX(dev_priv
))
16567 ibx_sanitize_pch_ports(dev_priv
);
16570 * intel_sanitize_plane_mapping() may need to do vblank
16571 * waits, so we need vblank interrupts restored beforehand.
16573 for_each_intel_crtc(&dev_priv
->drm
, crtc
) {
16574 crtc_state
= to_intel_crtc_state(crtc
->base
.state
);
16576 drm_crtc_vblank_reset(&crtc
->base
);
16578 if (crtc_state
->base
.active
)
16579 intel_crtc_vblank_on(crtc_state
);
16582 intel_sanitize_plane_mapping(dev_priv
);
16584 for_each_intel_encoder(dev
, encoder
)
16585 intel_sanitize_encoder(encoder
);
16587 for_each_intel_crtc(&dev_priv
->drm
, crtc
) {
16588 crtc_state
= to_intel_crtc_state(crtc
->base
.state
);
16589 intel_sanitize_crtc(crtc
, ctx
);
16590 intel_dump_pipe_config(crtc
, crtc_state
,
16591 "[setup_hw_state]");
16594 intel_modeset_update_connector_atomic_state(dev
);
16596 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
16597 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
16599 if (!pll
->on
|| pll
->active_mask
)
16602 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n",
16605 pll
->info
->funcs
->disable(dev_priv
, pll
);
16609 if (IS_G4X(dev_priv
)) {
16610 g4x_wm_get_hw_state(dev_priv
);
16611 g4x_wm_sanitize(dev_priv
);
16612 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
16613 vlv_wm_get_hw_state(dev_priv
);
16614 vlv_wm_sanitize(dev_priv
);
16615 } else if (INTEL_GEN(dev_priv
) >= 9) {
16616 skl_wm_get_hw_state(dev_priv
);
16617 } else if (HAS_PCH_SPLIT(dev_priv
)) {
16618 ilk_wm_get_hw_state(dev_priv
);
16621 for_each_intel_crtc(dev
, crtc
) {
16624 crtc_state
= to_intel_crtc_state(crtc
->base
.state
);
16625 put_domains
= modeset_get_crtc_power_domains(&crtc
->base
, crtc_state
);
16626 if (WARN_ON(put_domains
))
16627 modeset_put_power_domains(dev_priv
, put_domains
);
16630 intel_display_power_put(dev_priv
, POWER_DOMAIN_INIT
, wakeref
);
16632 intel_fbc_init_pipe_state(dev_priv
);
16635 void intel_display_resume(struct drm_device
*dev
)
16637 struct drm_i915_private
*dev_priv
= to_i915(dev
);
16638 struct drm_atomic_state
*state
= dev_priv
->modeset_restore_state
;
16639 struct drm_modeset_acquire_ctx ctx
;
16642 dev_priv
->modeset_restore_state
= NULL
;
16644 state
->acquire_ctx
= &ctx
;
16646 drm_modeset_acquire_init(&ctx
, 0);
16649 ret
= drm_modeset_lock_all_ctx(dev
, &ctx
);
16650 if (ret
!= -EDEADLK
)
16653 drm_modeset_backoff(&ctx
);
16657 ret
= __intel_display_resume(dev
, state
, &ctx
);
16659 intel_enable_ipc(dev_priv
);
16660 drm_modeset_drop_locks(&ctx
);
16661 drm_modeset_acquire_fini(&ctx
);
16664 DRM_ERROR("Restoring old state failed with %i\n", ret
);
16666 drm_atomic_state_put(state
);
16669 static void intel_hpd_poll_fini(struct drm_device
*dev
)
16671 struct intel_connector
*connector
;
16672 struct drm_connector_list_iter conn_iter
;
16674 /* Kill all the work that may have been queued by hpd. */
16675 drm_connector_list_iter_begin(dev
, &conn_iter
);
16676 for_each_intel_connector_iter(connector
, &conn_iter
) {
16677 if (connector
->modeset_retry_work
.func
)
16678 cancel_work_sync(&connector
->modeset_retry_work
);
16679 if (connector
->hdcp
.shim
) {
16680 cancel_delayed_work_sync(&connector
->hdcp
.check_work
);
16681 cancel_work_sync(&connector
->hdcp
.prop_work
);
16684 drm_connector_list_iter_end(&conn_iter
);
16687 void intel_modeset_cleanup(struct drm_device
*dev
)
16689 struct drm_i915_private
*dev_priv
= to_i915(dev
);
16691 flush_workqueue(dev_priv
->modeset_wq
);
16693 flush_work(&dev_priv
->atomic_helper
.free_work
);
16694 WARN_ON(!llist_empty(&dev_priv
->atomic_helper
.free_list
));
16697 * Interrupts and polling as the first thing to avoid creating havoc.
16698 * Too much stuff here (turning of connectors, ...) would
16699 * experience fancy races otherwise.
16701 intel_irq_uninstall(dev_priv
);
16704 * Due to the hpd irq storm handling the hotplug work can re-arm the
16705 * poll handlers. Hence disable polling after hpd handling is shut down.
16707 intel_hpd_poll_fini(dev
);
16709 /* poll work can call into fbdev, hence clean that up afterwards */
16710 intel_fbdev_fini(dev_priv
);
16712 intel_unregister_dsm_handler();
16714 intel_fbc_global_disable(dev_priv
);
16716 /* flush any delayed tasks or pending work */
16717 flush_scheduled_work();
16719 intel_hdcp_component_fini(dev_priv
);
16721 drm_mode_config_cleanup(dev
);
16723 intel_overlay_cleanup(dev_priv
);
16725 intel_gmbus_teardown(dev_priv
);
16727 destroy_workqueue(dev_priv
->modeset_wq
);
16729 intel_fbc_cleanup_cfb(dev_priv
);
16733 * set vga decode state - true == enable VGA decode
16735 int intel_modeset_vga_set_state(struct drm_i915_private
*dev_priv
, bool state
)
16737 unsigned reg
= INTEL_GEN(dev_priv
) >= 6 ? SNB_GMCH_CTRL
: INTEL_GMCH_CTRL
;
16740 if (pci_read_config_word(dev_priv
->bridge_dev
, reg
, &gmch_ctrl
)) {
16741 DRM_ERROR("failed to read control word\n");
16745 if (!!(gmch_ctrl
& INTEL_GMCH_VGA_DISABLE
) == !state
)
16749 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
16751 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
16753 if (pci_write_config_word(dev_priv
->bridge_dev
, reg
, gmch_ctrl
)) {
16754 DRM_ERROR("failed to write control word\n");
16761 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
16763 struct intel_display_error_state
{
16765 u32 power_well_driver
;
16767 struct intel_cursor_error_state
{
16772 } cursor
[I915_MAX_PIPES
];
16774 struct intel_pipe_error_state
{
16775 bool power_domain_on
;
16778 } pipe
[I915_MAX_PIPES
];
16780 struct intel_plane_error_state
{
16788 } plane
[I915_MAX_PIPES
];
16790 struct intel_transcoder_error_state
{
16792 bool power_domain_on
;
16793 enum transcoder cpu_transcoder
;
16806 struct intel_display_error_state
*
16807 intel_display_capture_error_state(struct drm_i915_private
*dev_priv
)
16809 struct intel_display_error_state
*error
;
16810 int transcoders
[] = {
16818 BUILD_BUG_ON(ARRAY_SIZE(transcoders
) != ARRAY_SIZE(error
->transcoder
));
16820 if (!HAS_DISPLAY(dev_priv
))
16823 error
= kzalloc(sizeof(*error
), GFP_ATOMIC
);
16827 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
16828 error
->power_well_driver
= I915_READ(HSW_PWR_WELL_CTL2
);
16830 for_each_pipe(dev_priv
, i
) {
16831 error
->pipe
[i
].power_domain_on
=
16832 __intel_display_power_is_enabled(dev_priv
,
16833 POWER_DOMAIN_PIPE(i
));
16834 if (!error
->pipe
[i
].power_domain_on
)
16837 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
16838 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
16839 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
16841 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
16842 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
16843 if (INTEL_GEN(dev_priv
) <= 3) {
16844 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
16845 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
16847 if (INTEL_GEN(dev_priv
) <= 7 && !IS_HASWELL(dev_priv
))
16848 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
16849 if (INTEL_GEN(dev_priv
) >= 4) {
16850 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
16851 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
16854 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
16856 if (HAS_GMCH(dev_priv
))
16857 error
->pipe
[i
].stat
= I915_READ(PIPESTAT(i
));
16860 for (i
= 0; i
< ARRAY_SIZE(error
->transcoder
); i
++) {
16861 enum transcoder cpu_transcoder
= transcoders
[i
];
16863 if (!INTEL_INFO(dev_priv
)->trans_offsets
[cpu_transcoder
])
16866 error
->transcoder
[i
].available
= true;
16867 error
->transcoder
[i
].power_domain_on
=
16868 __intel_display_power_is_enabled(dev_priv
,
16869 POWER_DOMAIN_TRANSCODER(cpu_transcoder
));
16870 if (!error
->transcoder
[i
].power_domain_on
)
16873 error
->transcoder
[i
].cpu_transcoder
= cpu_transcoder
;
16875 error
->transcoder
[i
].conf
= I915_READ(PIPECONF(cpu_transcoder
));
16876 error
->transcoder
[i
].htotal
= I915_READ(HTOTAL(cpu_transcoder
));
16877 error
->transcoder
[i
].hblank
= I915_READ(HBLANK(cpu_transcoder
));
16878 error
->transcoder
[i
].hsync
= I915_READ(HSYNC(cpu_transcoder
));
16879 error
->transcoder
[i
].vtotal
= I915_READ(VTOTAL(cpu_transcoder
));
16880 error
->transcoder
[i
].vblank
= I915_READ(VBLANK(cpu_transcoder
));
16881 error
->transcoder
[i
].vsync
= I915_READ(VSYNC(cpu_transcoder
));
16887 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
16890 intel_display_print_error_state(struct drm_i915_error_state_buf
*m
,
16891 struct intel_display_error_state
*error
)
16893 struct drm_i915_private
*dev_priv
= m
->i915
;
16899 err_printf(m
, "Num Pipes: %d\n", INTEL_INFO(dev_priv
)->num_pipes
);
16900 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
16901 err_printf(m
, "PWR_WELL_CTL2: %08x\n",
16902 error
->power_well_driver
);
16903 for_each_pipe(dev_priv
, i
) {
16904 err_printf(m
, "Pipe [%d]:\n", i
);
16905 err_printf(m
, " Power: %s\n",
16906 onoff(error
->pipe
[i
].power_domain_on
));
16907 err_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
16908 err_printf(m
, " STAT: %08x\n", error
->pipe
[i
].stat
);
16910 err_printf(m
, "Plane [%d]:\n", i
);
16911 err_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
16912 err_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
16913 if (INTEL_GEN(dev_priv
) <= 3) {
16914 err_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
16915 err_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
16917 if (INTEL_GEN(dev_priv
) <= 7 && !IS_HASWELL(dev_priv
))
16918 err_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
16919 if (INTEL_GEN(dev_priv
) >= 4) {
16920 err_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
16921 err_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
16924 err_printf(m
, "Cursor [%d]:\n", i
);
16925 err_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
16926 err_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
16927 err_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);
16930 for (i
= 0; i
< ARRAY_SIZE(error
->transcoder
); i
++) {
16931 if (!error
->transcoder
[i
].available
)
16934 err_printf(m
, "CPU transcoder: %s\n",
16935 transcoder_name(error
->transcoder
[i
].cpu_transcoder
));
16936 err_printf(m
, " Power: %s\n",
16937 onoff(error
->transcoder
[i
].power_domain_on
));
16938 err_printf(m
, " CONF: %08x\n", error
->transcoder
[i
].conf
);
16939 err_printf(m
, " HTOTAL: %08x\n", error
->transcoder
[i
].htotal
);
16940 err_printf(m
, " HBLANK: %08x\n", error
->transcoder
[i
].hblank
);
16941 err_printf(m
, " HSYNC: %08x\n", error
->transcoder
[i
].hsync
);
16942 err_printf(m
, " VTOTAL: %08x\n", error
->transcoder
[i
].vtotal
);
16943 err_printf(m
, " VBLANK: %08x\n", error
->transcoder
[i
].vblank
);
16944 err_printf(m
, " VSYNC: %08x\n", error
->transcoder
[i
].vsync
);