2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/i2c.h>
28 #include <linux/input.h>
29 #include <linux/intel-iommu.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/reservation.h>
33 #include <linux/slab.h>
34 #include <linux/vgaarb.h>
36 #include <drm/drm_atomic.h>
37 #include <drm/drm_atomic_helper.h>
38 #include <drm/drm_atomic_uapi.h>
39 #include <drm/drm_dp_helper.h>
40 #include <drm/drm_edid.h>
41 #include <drm/drm_fourcc.h>
42 #include <drm/drm_plane_helper.h>
43 #include <drm/drm_probe_helper.h>
44 #include <drm/drm_rect.h>
45 #include <drm/i915_drm.h>
48 #include "i915_gem_clflush.h"
49 #include "i915_trace.h"
50 #include "intel_atomic.h"
51 #include "intel_atomic_plane.h"
52 #include "intel_color.h"
53 #include "intel_cdclk.h"
54 #include "intel_crt.h"
55 #include "intel_ddi.h"
57 #include "intel_drv.h"
58 #include "intel_dsi.h"
59 #include "intel_dvo.h"
60 #include "intel_fbc.h"
61 #include "intel_fbdev.h"
62 #include "intel_fifo_underrun.h"
63 #include "intel_frontbuffer.h"
64 #include "intel_hdcp.h"
65 #include "intel_hdmi.h"
66 #include "intel_hotplug.h"
67 #include "intel_lvds.h"
68 #include "intel_overlay.h"
69 #include "intel_pipe_crc.h"
71 #include "intel_psr.h"
72 #include "intel_quirks.h"
73 #include "intel_sdvo.h"
74 #include "intel_sideband.h"
75 #include "intel_sprite.h"
77 #include "intel_vdsc.h"
79 /* Primary plane formats for gen <= 3 */
80 static const u32 i8xx_primary_formats
[] = {
87 /* Primary plane formats for gen >= 4 */
88 static const u32 i965_primary_formats
[] = {
93 DRM_FORMAT_XRGB2101010
,
94 DRM_FORMAT_XBGR2101010
,
97 static const u64 i9xx_format_modifiers
[] = {
98 I915_FORMAT_MOD_X_TILED
,
99 DRM_FORMAT_MOD_LINEAR
,
100 DRM_FORMAT_MOD_INVALID
104 static const u32 intel_cursor_formats
[] = {
108 static const u64 cursor_format_modifiers
[] = {
109 DRM_FORMAT_MOD_LINEAR
,
110 DRM_FORMAT_MOD_INVALID
113 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
114 struct intel_crtc_state
*pipe_config
);
115 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
116 struct intel_crtc_state
*pipe_config
);
118 static int intel_framebuffer_init(struct intel_framebuffer
*ifb
,
119 struct drm_i915_gem_object
*obj
,
120 struct drm_mode_fb_cmd2
*mode_cmd
);
121 static void intel_set_pipe_timings(const struct intel_crtc_state
*crtc_state
);
122 static void intel_set_pipe_src_size(const struct intel_crtc_state
*crtc_state
);
123 static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state
*crtc_state
,
124 const struct intel_link_m_n
*m_n
,
125 const struct intel_link_m_n
*m2_n2
);
126 static void i9xx_set_pipeconf(const struct intel_crtc_state
*crtc_state
);
127 static void ironlake_set_pipeconf(const struct intel_crtc_state
*crtc_state
);
128 static void haswell_set_pipeconf(const struct intel_crtc_state
*crtc_state
);
129 static void haswell_set_pipemisc(const struct intel_crtc_state
*crtc_state
);
130 static void vlv_prepare_pll(struct intel_crtc
*crtc
,
131 const struct intel_crtc_state
*pipe_config
);
132 static void chv_prepare_pll(struct intel_crtc
*crtc
,
133 const struct intel_crtc_state
*pipe_config
);
134 static void intel_begin_crtc_commit(struct intel_atomic_state
*, struct intel_crtc
*);
135 static void intel_finish_crtc_commit(struct intel_atomic_state
*, struct intel_crtc
*);
136 static void intel_crtc_init_scalers(struct intel_crtc
*crtc
,
137 struct intel_crtc_state
*crtc_state
);
138 static void skylake_pfit_enable(const struct intel_crtc_state
*crtc_state
);
139 static void ironlake_pfit_disable(const struct intel_crtc_state
*old_crtc_state
);
140 static void ironlake_pfit_enable(const struct intel_crtc_state
*crtc_state
);
141 static void intel_modeset_setup_hw_state(struct drm_device
*dev
,
142 struct drm_modeset_acquire_ctx
*ctx
);
143 static void intel_pre_disable_primary_noatomic(struct drm_crtc
*crtc
);
148 } dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
152 int p2_slow
, p2_fast
;
156 /* returns HPLL frequency in kHz */
157 int vlv_get_hpll_vco(struct drm_i915_private
*dev_priv
)
159 int hpll_freq
, vco_freq
[] = { 800, 1600, 2000, 2400 };
161 /* Obtain SKU information */
162 hpll_freq
= vlv_cck_read(dev_priv
, CCK_FUSE_REG
) &
163 CCK_FUSE_HPLL_FREQ_MASK
;
165 return vco_freq
[hpll_freq
] * 1000;
168 int vlv_get_cck_clock(struct drm_i915_private
*dev_priv
,
169 const char *name
, u32 reg
, int ref_freq
)
174 val
= vlv_cck_read(dev_priv
, reg
);
175 divider
= val
& CCK_FREQUENCY_VALUES
;
177 WARN((val
& CCK_FREQUENCY_STATUS
) !=
178 (divider
<< CCK_FREQUENCY_STATUS_SHIFT
),
179 "%s change in progress\n", name
);
181 return DIV_ROUND_CLOSEST(ref_freq
<< 1, divider
+ 1);
184 int vlv_get_cck_clock_hpll(struct drm_i915_private
*dev_priv
,
185 const char *name
, u32 reg
)
189 vlv_cck_get(dev_priv
);
191 if (dev_priv
->hpll_freq
== 0)
192 dev_priv
->hpll_freq
= vlv_get_hpll_vco(dev_priv
);
194 hpll
= vlv_get_cck_clock(dev_priv
, name
, reg
, dev_priv
->hpll_freq
);
196 vlv_cck_put(dev_priv
);
201 static void intel_update_czclk(struct drm_i915_private
*dev_priv
)
203 if (!(IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)))
206 dev_priv
->czclk_freq
= vlv_get_cck_clock_hpll(dev_priv
, "czclk",
207 CCK_CZ_CLOCK_CONTROL
);
209 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv
->czclk_freq
);
212 static inline u32
/* units of 100MHz */
213 intel_fdi_link_freq(struct drm_i915_private
*dev_priv
,
214 const struct intel_crtc_state
*pipe_config
)
216 if (HAS_DDI(dev_priv
))
217 return pipe_config
->port_clock
; /* SPLL */
219 return dev_priv
->fdi_pll_freq
;
222 static const struct intel_limit intel_limits_i8xx_dac
= {
223 .dot
= { .min
= 25000, .max
= 350000 },
224 .vco
= { .min
= 908000, .max
= 1512000 },
225 .n
= { .min
= 2, .max
= 16 },
226 .m
= { .min
= 96, .max
= 140 },
227 .m1
= { .min
= 18, .max
= 26 },
228 .m2
= { .min
= 6, .max
= 16 },
229 .p
= { .min
= 4, .max
= 128 },
230 .p1
= { .min
= 2, .max
= 33 },
231 .p2
= { .dot_limit
= 165000,
232 .p2_slow
= 4, .p2_fast
= 2 },
235 static const struct intel_limit intel_limits_i8xx_dvo
= {
236 .dot
= { .min
= 25000, .max
= 350000 },
237 .vco
= { .min
= 908000, .max
= 1512000 },
238 .n
= { .min
= 2, .max
= 16 },
239 .m
= { .min
= 96, .max
= 140 },
240 .m1
= { .min
= 18, .max
= 26 },
241 .m2
= { .min
= 6, .max
= 16 },
242 .p
= { .min
= 4, .max
= 128 },
243 .p1
= { .min
= 2, .max
= 33 },
244 .p2
= { .dot_limit
= 165000,
245 .p2_slow
= 4, .p2_fast
= 4 },
248 static const struct intel_limit intel_limits_i8xx_lvds
= {
249 .dot
= { .min
= 25000, .max
= 350000 },
250 .vco
= { .min
= 908000, .max
= 1512000 },
251 .n
= { .min
= 2, .max
= 16 },
252 .m
= { .min
= 96, .max
= 140 },
253 .m1
= { .min
= 18, .max
= 26 },
254 .m2
= { .min
= 6, .max
= 16 },
255 .p
= { .min
= 4, .max
= 128 },
256 .p1
= { .min
= 1, .max
= 6 },
257 .p2
= { .dot_limit
= 165000,
258 .p2_slow
= 14, .p2_fast
= 7 },
261 static const struct intel_limit intel_limits_i9xx_sdvo
= {
262 .dot
= { .min
= 20000, .max
= 400000 },
263 .vco
= { .min
= 1400000, .max
= 2800000 },
264 .n
= { .min
= 1, .max
= 6 },
265 .m
= { .min
= 70, .max
= 120 },
266 .m1
= { .min
= 8, .max
= 18 },
267 .m2
= { .min
= 3, .max
= 7 },
268 .p
= { .min
= 5, .max
= 80 },
269 .p1
= { .min
= 1, .max
= 8 },
270 .p2
= { .dot_limit
= 200000,
271 .p2_slow
= 10, .p2_fast
= 5 },
274 static const struct intel_limit intel_limits_i9xx_lvds
= {
275 .dot
= { .min
= 20000, .max
= 400000 },
276 .vco
= { .min
= 1400000, .max
= 2800000 },
277 .n
= { .min
= 1, .max
= 6 },
278 .m
= { .min
= 70, .max
= 120 },
279 .m1
= { .min
= 8, .max
= 18 },
280 .m2
= { .min
= 3, .max
= 7 },
281 .p
= { .min
= 7, .max
= 98 },
282 .p1
= { .min
= 1, .max
= 8 },
283 .p2
= { .dot_limit
= 112000,
284 .p2_slow
= 14, .p2_fast
= 7 },
288 static const struct intel_limit intel_limits_g4x_sdvo
= {
289 .dot
= { .min
= 25000, .max
= 270000 },
290 .vco
= { .min
= 1750000, .max
= 3500000},
291 .n
= { .min
= 1, .max
= 4 },
292 .m
= { .min
= 104, .max
= 138 },
293 .m1
= { .min
= 17, .max
= 23 },
294 .m2
= { .min
= 5, .max
= 11 },
295 .p
= { .min
= 10, .max
= 30 },
296 .p1
= { .min
= 1, .max
= 3},
297 .p2
= { .dot_limit
= 270000,
303 static const struct intel_limit intel_limits_g4x_hdmi
= {
304 .dot
= { .min
= 22000, .max
= 400000 },
305 .vco
= { .min
= 1750000, .max
= 3500000},
306 .n
= { .min
= 1, .max
= 4 },
307 .m
= { .min
= 104, .max
= 138 },
308 .m1
= { .min
= 16, .max
= 23 },
309 .m2
= { .min
= 5, .max
= 11 },
310 .p
= { .min
= 5, .max
= 80 },
311 .p1
= { .min
= 1, .max
= 8},
312 .p2
= { .dot_limit
= 165000,
313 .p2_slow
= 10, .p2_fast
= 5 },
316 static const struct intel_limit intel_limits_g4x_single_channel_lvds
= {
317 .dot
= { .min
= 20000, .max
= 115000 },
318 .vco
= { .min
= 1750000, .max
= 3500000 },
319 .n
= { .min
= 1, .max
= 3 },
320 .m
= { .min
= 104, .max
= 138 },
321 .m1
= { .min
= 17, .max
= 23 },
322 .m2
= { .min
= 5, .max
= 11 },
323 .p
= { .min
= 28, .max
= 112 },
324 .p1
= { .min
= 2, .max
= 8 },
325 .p2
= { .dot_limit
= 0,
326 .p2_slow
= 14, .p2_fast
= 14
330 static const struct intel_limit intel_limits_g4x_dual_channel_lvds
= {
331 .dot
= { .min
= 80000, .max
= 224000 },
332 .vco
= { .min
= 1750000, .max
= 3500000 },
333 .n
= { .min
= 1, .max
= 3 },
334 .m
= { .min
= 104, .max
= 138 },
335 .m1
= { .min
= 17, .max
= 23 },
336 .m2
= { .min
= 5, .max
= 11 },
337 .p
= { .min
= 14, .max
= 42 },
338 .p1
= { .min
= 2, .max
= 6 },
339 .p2
= { .dot_limit
= 0,
340 .p2_slow
= 7, .p2_fast
= 7
344 static const struct intel_limit intel_limits_pineview_sdvo
= {
345 .dot
= { .min
= 20000, .max
= 400000},
346 .vco
= { .min
= 1700000, .max
= 3500000 },
347 /* Pineview's Ncounter is a ring counter */
348 .n
= { .min
= 3, .max
= 6 },
349 .m
= { .min
= 2, .max
= 256 },
350 /* Pineview only has one combined m divider, which we treat as m2. */
351 .m1
= { .min
= 0, .max
= 0 },
352 .m2
= { .min
= 0, .max
= 254 },
353 .p
= { .min
= 5, .max
= 80 },
354 .p1
= { .min
= 1, .max
= 8 },
355 .p2
= { .dot_limit
= 200000,
356 .p2_slow
= 10, .p2_fast
= 5 },
359 static const struct intel_limit intel_limits_pineview_lvds
= {
360 .dot
= { .min
= 20000, .max
= 400000 },
361 .vco
= { .min
= 1700000, .max
= 3500000 },
362 .n
= { .min
= 3, .max
= 6 },
363 .m
= { .min
= 2, .max
= 256 },
364 .m1
= { .min
= 0, .max
= 0 },
365 .m2
= { .min
= 0, .max
= 254 },
366 .p
= { .min
= 7, .max
= 112 },
367 .p1
= { .min
= 1, .max
= 8 },
368 .p2
= { .dot_limit
= 112000,
369 .p2_slow
= 14, .p2_fast
= 14 },
372 /* Ironlake / Sandybridge
374 * We calculate clock using (register_value + 2) for N/M1/M2, so here
375 * the range value for them is (actual_value - 2).
377 static const struct intel_limit intel_limits_ironlake_dac
= {
378 .dot
= { .min
= 25000, .max
= 350000 },
379 .vco
= { .min
= 1760000, .max
= 3510000 },
380 .n
= { .min
= 1, .max
= 5 },
381 .m
= { .min
= 79, .max
= 127 },
382 .m1
= { .min
= 12, .max
= 22 },
383 .m2
= { .min
= 5, .max
= 9 },
384 .p
= { .min
= 5, .max
= 80 },
385 .p1
= { .min
= 1, .max
= 8 },
386 .p2
= { .dot_limit
= 225000,
387 .p2_slow
= 10, .p2_fast
= 5 },
390 static const struct intel_limit intel_limits_ironlake_single_lvds
= {
391 .dot
= { .min
= 25000, .max
= 350000 },
392 .vco
= { .min
= 1760000, .max
= 3510000 },
393 .n
= { .min
= 1, .max
= 3 },
394 .m
= { .min
= 79, .max
= 118 },
395 .m1
= { .min
= 12, .max
= 22 },
396 .m2
= { .min
= 5, .max
= 9 },
397 .p
= { .min
= 28, .max
= 112 },
398 .p1
= { .min
= 2, .max
= 8 },
399 .p2
= { .dot_limit
= 225000,
400 .p2_slow
= 14, .p2_fast
= 14 },
403 static const struct intel_limit intel_limits_ironlake_dual_lvds
= {
404 .dot
= { .min
= 25000, .max
= 350000 },
405 .vco
= { .min
= 1760000, .max
= 3510000 },
406 .n
= { .min
= 1, .max
= 3 },
407 .m
= { .min
= 79, .max
= 127 },
408 .m1
= { .min
= 12, .max
= 22 },
409 .m2
= { .min
= 5, .max
= 9 },
410 .p
= { .min
= 14, .max
= 56 },
411 .p1
= { .min
= 2, .max
= 8 },
412 .p2
= { .dot_limit
= 225000,
413 .p2_slow
= 7, .p2_fast
= 7 },
416 /* LVDS 100mhz refclk limits. */
417 static const struct intel_limit intel_limits_ironlake_single_lvds_100m
= {
418 .dot
= { .min
= 25000, .max
= 350000 },
419 .vco
= { .min
= 1760000, .max
= 3510000 },
420 .n
= { .min
= 1, .max
= 2 },
421 .m
= { .min
= 79, .max
= 126 },
422 .m1
= { .min
= 12, .max
= 22 },
423 .m2
= { .min
= 5, .max
= 9 },
424 .p
= { .min
= 28, .max
= 112 },
425 .p1
= { .min
= 2, .max
= 8 },
426 .p2
= { .dot_limit
= 225000,
427 .p2_slow
= 14, .p2_fast
= 14 },
430 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m
= {
431 .dot
= { .min
= 25000, .max
= 350000 },
432 .vco
= { .min
= 1760000, .max
= 3510000 },
433 .n
= { .min
= 1, .max
= 3 },
434 .m
= { .min
= 79, .max
= 126 },
435 .m1
= { .min
= 12, .max
= 22 },
436 .m2
= { .min
= 5, .max
= 9 },
437 .p
= { .min
= 14, .max
= 42 },
438 .p1
= { .min
= 2, .max
= 6 },
439 .p2
= { .dot_limit
= 225000,
440 .p2_slow
= 7, .p2_fast
= 7 },
443 static const struct intel_limit intel_limits_vlv
= {
445 * These are the data rate limits (measured in fast clocks)
446 * since those are the strictest limits we have. The fast
447 * clock and actual rate limits are more relaxed, so checking
448 * them would make no difference.
450 .dot
= { .min
= 25000 * 5, .max
= 270000 * 5 },
451 .vco
= { .min
= 4000000, .max
= 6000000 },
452 .n
= { .min
= 1, .max
= 7 },
453 .m1
= { .min
= 2, .max
= 3 },
454 .m2
= { .min
= 11, .max
= 156 },
455 .p1
= { .min
= 2, .max
= 3 },
456 .p2
= { .p2_slow
= 2, .p2_fast
= 20 }, /* slow=min, fast=max */
459 static const struct intel_limit intel_limits_chv
= {
461 * These are the data rate limits (measured in fast clocks)
462 * since those are the strictest limits we have. The fast
463 * clock and actual rate limits are more relaxed, so checking
464 * them would make no difference.
466 .dot
= { .min
= 25000 * 5, .max
= 540000 * 5},
467 .vco
= { .min
= 4800000, .max
= 6480000 },
468 .n
= { .min
= 1, .max
= 1 },
469 .m1
= { .min
= 2, .max
= 2 },
470 .m2
= { .min
= 24 << 22, .max
= 175 << 22 },
471 .p1
= { .min
= 2, .max
= 4 },
472 .p2
= { .p2_slow
= 1, .p2_fast
= 14 },
475 static const struct intel_limit intel_limits_bxt
= {
476 /* FIXME: find real dot limits */
477 .dot
= { .min
= 0, .max
= INT_MAX
},
478 .vco
= { .min
= 4800000, .max
= 6700000 },
479 .n
= { .min
= 1, .max
= 1 },
480 .m1
= { .min
= 2, .max
= 2 },
481 /* FIXME: find real m2 limits */
482 .m2
= { .min
= 2 << 22, .max
= 255 << 22 },
483 .p1
= { .min
= 2, .max
= 4 },
484 .p2
= { .p2_slow
= 1, .p2_fast
= 20 },
487 /* WA Display #0827: Gen9:all */
489 skl_wa_827(struct drm_i915_private
*dev_priv
, int pipe
, bool enable
)
492 I915_WRITE(CLKGATE_DIS_PSL(pipe
),
493 I915_READ(CLKGATE_DIS_PSL(pipe
)) |
494 DUPS1_GATING_DIS
| DUPS2_GATING_DIS
);
496 I915_WRITE(CLKGATE_DIS_PSL(pipe
),
497 I915_READ(CLKGATE_DIS_PSL(pipe
)) &
498 ~(DUPS1_GATING_DIS
| DUPS2_GATING_DIS
));
501 /* Wa_2006604312:icl */
503 icl_wa_scalerclkgating(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
507 I915_WRITE(CLKGATE_DIS_PSL(pipe
),
508 I915_READ(CLKGATE_DIS_PSL(pipe
)) | DPFR_GATING_DIS
);
510 I915_WRITE(CLKGATE_DIS_PSL(pipe
),
511 I915_READ(CLKGATE_DIS_PSL(pipe
)) & ~DPFR_GATING_DIS
);
515 needs_modeset(const struct drm_crtc_state
*state
)
517 return drm_atomic_crtc_needs_modeset(state
);
521 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
522 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
523 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
524 * The helpers' return value is the rate of the clock that is fed to the
525 * display engine's pipe which can be the above fast dot clock rate or a
526 * divided-down version of it.
528 /* m1 is reserved as 0 in Pineview, n is a ring counter */
529 static int pnv_calc_dpll_params(int refclk
, struct dpll
*clock
)
531 clock
->m
= clock
->m2
+ 2;
532 clock
->p
= clock
->p1
* clock
->p2
;
533 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
535 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
536 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
541 static u32
i9xx_dpll_compute_m(struct dpll
*dpll
)
543 return 5 * (dpll
->m1
+ 2) + (dpll
->m2
+ 2);
546 static int i9xx_calc_dpll_params(int refclk
, struct dpll
*clock
)
548 clock
->m
= i9xx_dpll_compute_m(clock
);
549 clock
->p
= clock
->p1
* clock
->p2
;
550 if (WARN_ON(clock
->n
+ 2 == 0 || clock
->p
== 0))
552 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
+ 2);
553 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
558 static int vlv_calc_dpll_params(int refclk
, struct dpll
*clock
)
560 clock
->m
= clock
->m1
* clock
->m2
;
561 clock
->p
= clock
->p1
* clock
->p2
;
562 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
564 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
565 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
567 return clock
->dot
/ 5;
570 int chv_calc_dpll_params(int refclk
, struct dpll
*clock
)
572 clock
->m
= clock
->m1
* clock
->m2
;
573 clock
->p
= clock
->p1
* clock
->p2
;
574 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
576 clock
->vco
= DIV_ROUND_CLOSEST_ULL((u64
)refclk
* clock
->m
,
578 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
580 return clock
->dot
/ 5;
583 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
586 * Returns whether the given set of divisors are valid for a given refclk with
587 * the given connectors.
589 static bool intel_PLL_is_valid(struct drm_i915_private
*dev_priv
,
590 const struct intel_limit
*limit
,
591 const struct dpll
*clock
)
593 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
594 INTELPllInvalid("n out of range\n");
595 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
596 INTELPllInvalid("p1 out of range\n");
597 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
598 INTELPllInvalid("m2 out of range\n");
599 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
600 INTELPllInvalid("m1 out of range\n");
602 if (!IS_PINEVIEW(dev_priv
) && !IS_VALLEYVIEW(dev_priv
) &&
603 !IS_CHERRYVIEW(dev_priv
) && !IS_GEN9_LP(dev_priv
))
604 if (clock
->m1
<= clock
->m2
)
605 INTELPllInvalid("m1 <= m2\n");
607 if (!IS_VALLEYVIEW(dev_priv
) && !IS_CHERRYVIEW(dev_priv
) &&
608 !IS_GEN9_LP(dev_priv
)) {
609 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
610 INTELPllInvalid("p out of range\n");
611 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
612 INTELPllInvalid("m out of range\n");
615 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
616 INTELPllInvalid("vco out of range\n");
617 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
618 * connector, etc., rather than just a single range.
620 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
621 INTELPllInvalid("dot out of range\n");
627 i9xx_select_p2_div(const struct intel_limit
*limit
,
628 const struct intel_crtc_state
*crtc_state
,
631 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->base
.crtc
->dev
);
633 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
635 * For LVDS just rely on its current settings for dual-channel.
636 * We haven't figured out how to reliably set up different
637 * single/dual channel state, if we even can.
639 if (intel_is_dual_link_lvds(dev_priv
))
640 return limit
->p2
.p2_fast
;
642 return limit
->p2
.p2_slow
;
644 if (target
< limit
->p2
.dot_limit
)
645 return limit
->p2
.p2_slow
;
647 return limit
->p2
.p2_fast
;
652 * Returns a set of divisors for the desired target clock with the given
653 * refclk, or FALSE. The returned values represent the clock equation:
654 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
656 * Target and reference clocks are specified in kHz.
658 * If match_clock is provided, then best_clock P divider must match the P
659 * divider from @match_clock used for LVDS downclocking.
662 i9xx_find_best_dpll(const struct intel_limit
*limit
,
663 struct intel_crtc_state
*crtc_state
,
664 int target
, int refclk
, struct dpll
*match_clock
,
665 struct dpll
*best_clock
)
667 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
671 memset(best_clock
, 0, sizeof(*best_clock
));
673 clock
.p2
= i9xx_select_p2_div(limit
, crtc_state
, target
);
675 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
677 for (clock
.m2
= limit
->m2
.min
;
678 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
679 if (clock
.m2
>= clock
.m1
)
681 for (clock
.n
= limit
->n
.min
;
682 clock
.n
<= limit
->n
.max
; clock
.n
++) {
683 for (clock
.p1
= limit
->p1
.min
;
684 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
687 i9xx_calc_dpll_params(refclk
, &clock
);
688 if (!intel_PLL_is_valid(to_i915(dev
),
693 clock
.p
!= match_clock
->p
)
696 this_err
= abs(clock
.dot
- target
);
697 if (this_err
< err
) {
706 return (err
!= target
);
710 * Returns a set of divisors for the desired target clock with the given
711 * refclk, or FALSE. The returned values represent the clock equation:
712 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
714 * Target and reference clocks are specified in kHz.
716 * If match_clock is provided, then best_clock P divider must match the P
717 * divider from @match_clock used for LVDS downclocking.
720 pnv_find_best_dpll(const struct intel_limit
*limit
,
721 struct intel_crtc_state
*crtc_state
,
722 int target
, int refclk
, struct dpll
*match_clock
,
723 struct dpll
*best_clock
)
725 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
729 memset(best_clock
, 0, sizeof(*best_clock
));
731 clock
.p2
= i9xx_select_p2_div(limit
, crtc_state
, target
);
733 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
735 for (clock
.m2
= limit
->m2
.min
;
736 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
737 for (clock
.n
= limit
->n
.min
;
738 clock
.n
<= limit
->n
.max
; clock
.n
++) {
739 for (clock
.p1
= limit
->p1
.min
;
740 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
743 pnv_calc_dpll_params(refclk
, &clock
);
744 if (!intel_PLL_is_valid(to_i915(dev
),
749 clock
.p
!= match_clock
->p
)
752 this_err
= abs(clock
.dot
- target
);
753 if (this_err
< err
) {
762 return (err
!= target
);
766 * Returns a set of divisors for the desired target clock with the given
767 * refclk, or FALSE. The returned values represent the clock equation:
768 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
770 * Target and reference clocks are specified in kHz.
772 * If match_clock is provided, then best_clock P divider must match the P
773 * divider from @match_clock used for LVDS downclocking.
776 g4x_find_best_dpll(const struct intel_limit
*limit
,
777 struct intel_crtc_state
*crtc_state
,
778 int target
, int refclk
, struct dpll
*match_clock
,
779 struct dpll
*best_clock
)
781 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
785 /* approximately equals target * 0.00585 */
786 int err_most
= (target
>> 8) + (target
>> 9);
788 memset(best_clock
, 0, sizeof(*best_clock
));
790 clock
.p2
= i9xx_select_p2_div(limit
, crtc_state
, target
);
792 max_n
= limit
->n
.max
;
793 /* based on hardware requirement, prefer smaller n to precision */
794 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
795 /* based on hardware requirement, prefere larger m1,m2 */
796 for (clock
.m1
= limit
->m1
.max
;
797 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
798 for (clock
.m2
= limit
->m2
.max
;
799 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
800 for (clock
.p1
= limit
->p1
.max
;
801 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
804 i9xx_calc_dpll_params(refclk
, &clock
);
805 if (!intel_PLL_is_valid(to_i915(dev
),
810 this_err
= abs(clock
.dot
- target
);
811 if (this_err
< err_most
) {
825 * Check if the calculated PLL configuration is more optimal compared to the
826 * best configuration and error found so far. Return the calculated error.
828 static bool vlv_PLL_is_optimal(struct drm_device
*dev
, int target_freq
,
829 const struct dpll
*calculated_clock
,
830 const struct dpll
*best_clock
,
831 unsigned int best_error_ppm
,
832 unsigned int *error_ppm
)
835 * For CHV ignore the error and consider only the P value.
836 * Prefer a bigger P value based on HW requirements.
838 if (IS_CHERRYVIEW(to_i915(dev
))) {
841 return calculated_clock
->p
> best_clock
->p
;
844 if (WARN_ON_ONCE(!target_freq
))
847 *error_ppm
= div_u64(1000000ULL *
848 abs(target_freq
- calculated_clock
->dot
),
851 * Prefer a better P value over a better (smaller) error if the error
852 * is small. Ensure this preference for future configurations too by
853 * setting the error to 0.
855 if (*error_ppm
< 100 && calculated_clock
->p
> best_clock
->p
) {
861 return *error_ppm
+ 10 < best_error_ppm
;
865 * Returns a set of divisors for the desired target clock with the given
866 * refclk, or FALSE. The returned values represent the clock equation:
867 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
870 vlv_find_best_dpll(const struct intel_limit
*limit
,
871 struct intel_crtc_state
*crtc_state
,
872 int target
, int refclk
, struct dpll
*match_clock
,
873 struct dpll
*best_clock
)
875 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
876 struct drm_device
*dev
= crtc
->base
.dev
;
878 unsigned int bestppm
= 1000000;
879 /* min update 19.2 MHz */
880 int max_n
= min(limit
->n
.max
, refclk
/ 19200);
883 target
*= 5; /* fast clock */
885 memset(best_clock
, 0, sizeof(*best_clock
));
887 /* based on hardware requirement, prefer smaller n to precision */
888 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
889 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
890 for (clock
.p2
= limit
->p2
.p2_fast
; clock
.p2
>= limit
->p2
.p2_slow
;
891 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
892 clock
.p
= clock
.p1
* clock
.p2
;
893 /* based on hardware requirement, prefer bigger m1,m2 values */
894 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
; clock
.m1
++) {
897 clock
.m2
= DIV_ROUND_CLOSEST(target
* clock
.p
* clock
.n
,
900 vlv_calc_dpll_params(refclk
, &clock
);
902 if (!intel_PLL_is_valid(to_i915(dev
),
907 if (!vlv_PLL_is_optimal(dev
, target
,
925 * Returns a set of divisors for the desired target clock with the given
926 * refclk, or FALSE. The returned values represent the clock equation:
927 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
930 chv_find_best_dpll(const struct intel_limit
*limit
,
931 struct intel_crtc_state
*crtc_state
,
932 int target
, int refclk
, struct dpll
*match_clock
,
933 struct dpll
*best_clock
)
935 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
936 struct drm_device
*dev
= crtc
->base
.dev
;
937 unsigned int best_error_ppm
;
942 memset(best_clock
, 0, sizeof(*best_clock
));
943 best_error_ppm
= 1000000;
946 * Based on hardware doc, the n always set to 1, and m1 always
947 * set to 2. If requires to support 200Mhz refclk, we need to
948 * revisit this because n may not 1 anymore.
950 clock
.n
= 1, clock
.m1
= 2;
951 target
*= 5; /* fast clock */
953 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
954 for (clock
.p2
= limit
->p2
.p2_fast
;
955 clock
.p2
>= limit
->p2
.p2_slow
;
956 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
957 unsigned int error_ppm
;
959 clock
.p
= clock
.p1
* clock
.p2
;
961 m2
= DIV_ROUND_CLOSEST_ULL(((u64
)target
* clock
.p
*
962 clock
.n
) << 22, refclk
* clock
.m1
);
964 if (m2
> INT_MAX
/clock
.m1
)
969 chv_calc_dpll_params(refclk
, &clock
);
971 if (!intel_PLL_is_valid(to_i915(dev
), limit
, &clock
))
974 if (!vlv_PLL_is_optimal(dev
, target
, &clock
, best_clock
,
975 best_error_ppm
, &error_ppm
))
979 best_error_ppm
= error_ppm
;
987 bool bxt_find_best_dpll(struct intel_crtc_state
*crtc_state
,
988 struct dpll
*best_clock
)
991 const struct intel_limit
*limit
= &intel_limits_bxt
;
993 return chv_find_best_dpll(limit
, crtc_state
,
994 crtc_state
->port_clock
, refclk
,
998 bool intel_crtc_active(struct intel_crtc
*crtc
)
1000 /* Be paranoid as we can arrive here with only partial
1001 * state retrieved from the hardware during setup.
1003 * We can ditch the adjusted_mode.crtc_clock check as soon
1004 * as Haswell has gained clock readout/fastboot support.
1006 * We can ditch the crtc->primary->state->fb check as soon as we can
1007 * properly reconstruct framebuffers.
1009 * FIXME: The intel_crtc->active here should be switched to
1010 * crtc->state->active once we have proper CRTC states wired up
1013 return crtc
->active
&& crtc
->base
.primary
->state
->fb
&&
1014 crtc
->config
->base
.adjusted_mode
.crtc_clock
;
1017 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
1020 struct intel_crtc
*crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
1022 return crtc
->config
->cpu_transcoder
;
1025 static bool pipe_scanline_is_moving(struct drm_i915_private
*dev_priv
,
1028 i915_reg_t reg
= PIPEDSL(pipe
);
1032 if (IS_GEN(dev_priv
, 2))
1033 line_mask
= DSL_LINEMASK_GEN2
;
1035 line_mask
= DSL_LINEMASK_GEN3
;
1037 line1
= I915_READ(reg
) & line_mask
;
1039 line2
= I915_READ(reg
) & line_mask
;
1041 return line1
!= line2
;
1044 static void wait_for_pipe_scanline_moving(struct intel_crtc
*crtc
, bool state
)
1046 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1047 enum pipe pipe
= crtc
->pipe
;
1049 /* Wait for the display line to settle/start moving */
1050 if (wait_for(pipe_scanline_is_moving(dev_priv
, pipe
) == state
, 100))
1051 DRM_ERROR("pipe %c scanline %s wait timed out\n",
1052 pipe_name(pipe
), onoff(state
));
1055 static void intel_wait_for_pipe_scanline_stopped(struct intel_crtc
*crtc
)
1057 wait_for_pipe_scanline_moving(crtc
, false);
1060 static void intel_wait_for_pipe_scanline_moving(struct intel_crtc
*crtc
)
1062 wait_for_pipe_scanline_moving(crtc
, true);
1066 intel_wait_for_pipe_off(const struct intel_crtc_state
*old_crtc_state
)
1068 struct intel_crtc
*crtc
= to_intel_crtc(old_crtc_state
->base
.crtc
);
1069 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1071 if (INTEL_GEN(dev_priv
) >= 4) {
1072 enum transcoder cpu_transcoder
= old_crtc_state
->cpu_transcoder
;
1073 i915_reg_t reg
= PIPECONF(cpu_transcoder
);
1075 /* Wait for the Pipe State to go off */
1076 if (intel_wait_for_register(&dev_priv
->uncore
,
1077 reg
, I965_PIPECONF_ACTIVE
, 0,
1079 WARN(1, "pipe_off wait timed out\n");
1081 intel_wait_for_pipe_scanline_stopped(crtc
);
1085 /* Only for pre-ILK configs */
1086 void assert_pll(struct drm_i915_private
*dev_priv
,
1087 enum pipe pipe
, bool state
)
1092 val
= I915_READ(DPLL(pipe
));
1093 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1094 I915_STATE_WARN(cur_state
!= state
,
1095 "PLL state assertion failure (expected %s, current %s)\n",
1096 onoff(state
), onoff(cur_state
));
1099 /* XXX: the dsi pll is shared between MIPI DSI ports */
1100 void assert_dsi_pll(struct drm_i915_private
*dev_priv
, bool state
)
1105 vlv_cck_get(dev_priv
);
1106 val
= vlv_cck_read(dev_priv
, CCK_REG_DSI_PLL_CONTROL
);
1107 vlv_cck_put(dev_priv
);
1109 cur_state
= val
& DSI_PLL_VCO_EN
;
1110 I915_STATE_WARN(cur_state
!= state
,
1111 "DSI PLL state assertion failure (expected %s, current %s)\n",
1112 onoff(state
), onoff(cur_state
));
1115 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
1116 enum pipe pipe
, bool state
)
1119 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1122 if (HAS_DDI(dev_priv
)) {
1123 /* DDI does not have a specific FDI_TX register */
1124 u32 val
= I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder
));
1125 cur_state
= !!(val
& TRANS_DDI_FUNC_ENABLE
);
1127 u32 val
= I915_READ(FDI_TX_CTL(pipe
));
1128 cur_state
= !!(val
& FDI_TX_ENABLE
);
1130 I915_STATE_WARN(cur_state
!= state
,
1131 "FDI TX state assertion failure (expected %s, current %s)\n",
1132 onoff(state
), onoff(cur_state
));
1134 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1135 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1137 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
1138 enum pipe pipe
, bool state
)
1143 val
= I915_READ(FDI_RX_CTL(pipe
));
1144 cur_state
= !!(val
& FDI_RX_ENABLE
);
1145 I915_STATE_WARN(cur_state
!= state
,
1146 "FDI RX state assertion failure (expected %s, current %s)\n",
1147 onoff(state
), onoff(cur_state
));
1149 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1150 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1152 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
1157 /* ILK FDI PLL is always enabled */
1158 if (IS_GEN(dev_priv
, 5))
1161 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1162 if (HAS_DDI(dev_priv
))
1165 val
= I915_READ(FDI_TX_CTL(pipe
));
1166 I915_STATE_WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1169 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
1170 enum pipe pipe
, bool state
)
1175 val
= I915_READ(FDI_RX_CTL(pipe
));
1176 cur_state
= !!(val
& FDI_RX_PLL_ENABLE
);
1177 I915_STATE_WARN(cur_state
!= state
,
1178 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1179 onoff(state
), onoff(cur_state
));
1182 void assert_panel_unlocked(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1186 enum pipe panel_pipe
= INVALID_PIPE
;
1189 if (WARN_ON(HAS_DDI(dev_priv
)))
1192 if (HAS_PCH_SPLIT(dev_priv
)) {
1195 pp_reg
= PP_CONTROL(0);
1196 port_sel
= I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK
;
1199 case PANEL_PORT_SELECT_LVDS
:
1200 intel_lvds_port_enabled(dev_priv
, PCH_LVDS
, &panel_pipe
);
1202 case PANEL_PORT_SELECT_DPA
:
1203 intel_dp_port_enabled(dev_priv
, DP_A
, PORT_A
, &panel_pipe
);
1205 case PANEL_PORT_SELECT_DPC
:
1206 intel_dp_port_enabled(dev_priv
, PCH_DP_C
, PORT_C
, &panel_pipe
);
1208 case PANEL_PORT_SELECT_DPD
:
1209 intel_dp_port_enabled(dev_priv
, PCH_DP_D
, PORT_D
, &panel_pipe
);
1212 MISSING_CASE(port_sel
);
1215 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
1216 /* presumably write lock depends on pipe, not port select */
1217 pp_reg
= PP_CONTROL(pipe
);
1222 pp_reg
= PP_CONTROL(0);
1223 port_sel
= I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK
;
1225 WARN_ON(port_sel
!= PANEL_PORT_SELECT_LVDS
);
1226 intel_lvds_port_enabled(dev_priv
, LVDS
, &panel_pipe
);
1229 val
= I915_READ(pp_reg
);
1230 if (!(val
& PANEL_POWER_ON
) ||
1231 ((val
& PANEL_UNLOCK_MASK
) == PANEL_UNLOCK_REGS
))
1234 I915_STATE_WARN(panel_pipe
== pipe
&& locked
,
1235 "panel assertion failure, pipe %c regs locked\n",
1239 void assert_pipe(struct drm_i915_private
*dev_priv
,
1240 enum pipe pipe
, bool state
)
1243 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1245 enum intel_display_power_domain power_domain
;
1246 intel_wakeref_t wakeref
;
1248 /* we keep both pipes enabled on 830 */
1249 if (IS_I830(dev_priv
))
1252 power_domain
= POWER_DOMAIN_TRANSCODER(cpu_transcoder
);
1253 wakeref
= intel_display_power_get_if_enabled(dev_priv
, power_domain
);
1255 u32 val
= I915_READ(PIPECONF(cpu_transcoder
));
1256 cur_state
= !!(val
& PIPECONF_ENABLE
);
1258 intel_display_power_put(dev_priv
, power_domain
, wakeref
);
1263 I915_STATE_WARN(cur_state
!= state
,
1264 "pipe %c assertion failure (expected %s, current %s)\n",
1265 pipe_name(pipe
), onoff(state
), onoff(cur_state
));
1268 static void assert_plane(struct intel_plane
*plane
, bool state
)
1273 cur_state
= plane
->get_hw_state(plane
, &pipe
);
1275 I915_STATE_WARN(cur_state
!= state
,
1276 "%s assertion failure (expected %s, current %s)\n",
1277 plane
->base
.name
, onoff(state
), onoff(cur_state
));
1280 #define assert_plane_enabled(p) assert_plane(p, true)
1281 #define assert_plane_disabled(p) assert_plane(p, false)
1283 static void assert_planes_disabled(struct intel_crtc
*crtc
)
1285 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1286 struct intel_plane
*plane
;
1288 for_each_intel_plane_on_crtc(&dev_priv
->drm
, crtc
, plane
)
1289 assert_plane_disabled(plane
);
1292 static void assert_vblank_disabled(struct drm_crtc
*crtc
)
1294 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc
) == 0))
1295 drm_crtc_vblank_put(crtc
);
1298 void assert_pch_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1304 val
= I915_READ(PCH_TRANSCONF(pipe
));
1305 enabled
= !!(val
& TRANS_ENABLE
);
1306 I915_STATE_WARN(enabled
,
1307 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1311 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1312 enum pipe pipe
, enum port port
,
1315 enum pipe port_pipe
;
1318 state
= intel_dp_port_enabled(dev_priv
, dp_reg
, port
, &port_pipe
);
1320 I915_STATE_WARN(state
&& port_pipe
== pipe
,
1321 "PCH DP %c enabled on transcoder %c, should be disabled\n",
1322 port_name(port
), pipe_name(pipe
));
1324 I915_STATE_WARN(HAS_PCH_IBX(dev_priv
) && !state
&& port_pipe
== PIPE_B
,
1325 "IBX PCH DP %c still using transcoder B\n",
1329 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1330 enum pipe pipe
, enum port port
,
1331 i915_reg_t hdmi_reg
)
1333 enum pipe port_pipe
;
1336 state
= intel_sdvo_port_enabled(dev_priv
, hdmi_reg
, &port_pipe
);
1338 I915_STATE_WARN(state
&& port_pipe
== pipe
,
1339 "PCH HDMI %c enabled on transcoder %c, should be disabled\n",
1340 port_name(port
), pipe_name(pipe
));
1342 I915_STATE_WARN(HAS_PCH_IBX(dev_priv
) && !state
&& port_pipe
== PIPE_B
,
1343 "IBX PCH HDMI %c still using transcoder B\n",
1347 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1350 enum pipe port_pipe
;
1352 assert_pch_dp_disabled(dev_priv
, pipe
, PORT_B
, PCH_DP_B
);
1353 assert_pch_dp_disabled(dev_priv
, pipe
, PORT_C
, PCH_DP_C
);
1354 assert_pch_dp_disabled(dev_priv
, pipe
, PORT_D
, PCH_DP_D
);
1356 I915_STATE_WARN(intel_crt_port_enabled(dev_priv
, PCH_ADPA
, &port_pipe
) &&
1358 "PCH VGA enabled on transcoder %c, should be disabled\n",
1361 I915_STATE_WARN(intel_lvds_port_enabled(dev_priv
, PCH_LVDS
, &port_pipe
) &&
1363 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1366 /* PCH SDVOB multiplex with HDMIB */
1367 assert_pch_hdmi_disabled(dev_priv
, pipe
, PORT_B
, PCH_HDMIB
);
1368 assert_pch_hdmi_disabled(dev_priv
, pipe
, PORT_C
, PCH_HDMIC
);
1369 assert_pch_hdmi_disabled(dev_priv
, pipe
, PORT_D
, PCH_HDMID
);
1372 static void _vlv_enable_pll(struct intel_crtc
*crtc
,
1373 const struct intel_crtc_state
*pipe_config
)
1375 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1376 enum pipe pipe
= crtc
->pipe
;
1378 I915_WRITE(DPLL(pipe
), pipe_config
->dpll_hw_state
.dpll
);
1379 POSTING_READ(DPLL(pipe
));
1382 if (intel_wait_for_register(&dev_priv
->uncore
,
1387 DRM_ERROR("DPLL %d failed to lock\n", pipe
);
1390 static void vlv_enable_pll(struct intel_crtc
*crtc
,
1391 const struct intel_crtc_state
*pipe_config
)
1393 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1394 enum pipe pipe
= crtc
->pipe
;
1396 assert_pipe_disabled(dev_priv
, pipe
);
1398 /* PLL is protected by panel, make sure we can write it */
1399 assert_panel_unlocked(dev_priv
, pipe
);
1401 if (pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
)
1402 _vlv_enable_pll(crtc
, pipe_config
);
1404 I915_WRITE(DPLL_MD(pipe
), pipe_config
->dpll_hw_state
.dpll_md
);
1405 POSTING_READ(DPLL_MD(pipe
));
1409 static void _chv_enable_pll(struct intel_crtc
*crtc
,
1410 const struct intel_crtc_state
*pipe_config
)
1412 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1413 enum pipe pipe
= crtc
->pipe
;
1414 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1417 vlv_dpio_get(dev_priv
);
1419 /* Enable back the 10bit clock to display controller */
1420 tmp
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1421 tmp
|= DPIO_DCLKP_EN
;
1422 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), tmp
);
1424 vlv_dpio_put(dev_priv
);
1427 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1432 I915_WRITE(DPLL(pipe
), pipe_config
->dpll_hw_state
.dpll
);
1434 /* Check PLL is locked */
1435 if (intel_wait_for_register(&dev_priv
->uncore
,
1436 DPLL(pipe
), DPLL_LOCK_VLV
, DPLL_LOCK_VLV
,
1438 DRM_ERROR("PLL %d failed to lock\n", pipe
);
1441 static void chv_enable_pll(struct intel_crtc
*crtc
,
1442 const struct intel_crtc_state
*pipe_config
)
1444 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1445 enum pipe pipe
= crtc
->pipe
;
1447 assert_pipe_disabled(dev_priv
, pipe
);
1449 /* PLL is protected by panel, make sure we can write it */
1450 assert_panel_unlocked(dev_priv
, pipe
);
1452 if (pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
)
1453 _chv_enable_pll(crtc
, pipe_config
);
1455 if (pipe
!= PIPE_A
) {
1457 * WaPixelRepeatModeFixForC0:chv
1459 * DPLLCMD is AWOL. Use chicken bits to propagate
1460 * the value from DPLLBMD to either pipe B or C.
1462 I915_WRITE(CBR4_VLV
, CBR_DPLLBMD_PIPE(pipe
));
1463 I915_WRITE(DPLL_MD(PIPE_B
), pipe_config
->dpll_hw_state
.dpll_md
);
1464 I915_WRITE(CBR4_VLV
, 0);
1465 dev_priv
->chv_dpll_md
[pipe
] = pipe_config
->dpll_hw_state
.dpll_md
;
1468 * DPLLB VGA mode also seems to cause problems.
1469 * We should always have it disabled.
1471 WARN_ON((I915_READ(DPLL(PIPE_B
)) & DPLL_VGA_MODE_DIS
) == 0);
1473 I915_WRITE(DPLL_MD(pipe
), pipe_config
->dpll_hw_state
.dpll_md
);
1474 POSTING_READ(DPLL_MD(pipe
));
1478 static bool i9xx_has_pps(struct drm_i915_private
*dev_priv
)
1480 if (IS_I830(dev_priv
))
1483 return IS_PINEVIEW(dev_priv
) || IS_MOBILE(dev_priv
);
1486 static void i9xx_enable_pll(struct intel_crtc
*crtc
,
1487 const struct intel_crtc_state
*crtc_state
)
1489 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1490 i915_reg_t reg
= DPLL(crtc
->pipe
);
1491 u32 dpll
= crtc_state
->dpll_hw_state
.dpll
;
1494 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1496 /* PLL is protected by panel, make sure we can write it */
1497 if (i9xx_has_pps(dev_priv
))
1498 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1501 * Apparently we need to have VGA mode enabled prior to changing
1502 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1503 * dividers, even though the register value does change.
1505 I915_WRITE(reg
, dpll
& ~DPLL_VGA_MODE_DIS
);
1506 I915_WRITE(reg
, dpll
);
1508 /* Wait for the clocks to stabilize. */
1512 if (INTEL_GEN(dev_priv
) >= 4) {
1513 I915_WRITE(DPLL_MD(crtc
->pipe
),
1514 crtc_state
->dpll_hw_state
.dpll_md
);
1516 /* The pixel multiplier can only be updated once the
1517 * DPLL is enabled and the clocks are stable.
1519 * So write it again.
1521 I915_WRITE(reg
, dpll
);
1524 /* We do this three times for luck */
1525 for (i
= 0; i
< 3; i
++) {
1526 I915_WRITE(reg
, dpll
);
1528 udelay(150); /* wait for warmup */
1532 static void i9xx_disable_pll(const struct intel_crtc_state
*crtc_state
)
1534 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
1535 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1536 enum pipe pipe
= crtc
->pipe
;
1538 /* Don't disable pipe or pipe PLLs if needed */
1539 if (IS_I830(dev_priv
))
1542 /* Make sure the pipe isn't still relying on us */
1543 assert_pipe_disabled(dev_priv
, pipe
);
1545 I915_WRITE(DPLL(pipe
), DPLL_VGA_MODE_DIS
);
1546 POSTING_READ(DPLL(pipe
));
1549 static void vlv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1553 /* Make sure the pipe isn't still relying on us */
1554 assert_pipe_disabled(dev_priv
, pipe
);
1556 val
= DPLL_INTEGRATED_REF_CLK_VLV
|
1557 DPLL_REF_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
;
1559 val
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
1561 I915_WRITE(DPLL(pipe
), val
);
1562 POSTING_READ(DPLL(pipe
));
1565 static void chv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1567 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1570 /* Make sure the pipe isn't still relying on us */
1571 assert_pipe_disabled(dev_priv
, pipe
);
1573 val
= DPLL_SSC_REF_CLK_CHV
|
1574 DPLL_REF_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
;
1576 val
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
1578 I915_WRITE(DPLL(pipe
), val
);
1579 POSTING_READ(DPLL(pipe
));
1581 vlv_dpio_get(dev_priv
);
1583 /* Disable 10bit clock to display controller */
1584 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1585 val
&= ~DPIO_DCLKP_EN
;
1586 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), val
);
1588 vlv_dpio_put(dev_priv
);
1591 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
,
1592 struct intel_digital_port
*dport
,
1593 unsigned int expected_mask
)
1596 i915_reg_t dpll_reg
;
1598 switch (dport
->base
.port
) {
1600 port_mask
= DPLL_PORTB_READY_MASK
;
1604 port_mask
= DPLL_PORTC_READY_MASK
;
1606 expected_mask
<<= 4;
1609 port_mask
= DPLL_PORTD_READY_MASK
;
1610 dpll_reg
= DPIO_PHY_STATUS
;
1616 if (intel_wait_for_register(&dev_priv
->uncore
,
1617 dpll_reg
, port_mask
, expected_mask
,
1619 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1620 port_name(dport
->base
.port
),
1621 I915_READ(dpll_reg
) & port_mask
, expected_mask
);
1624 static void ironlake_enable_pch_transcoder(const struct intel_crtc_state
*crtc_state
)
1626 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
1627 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1628 enum pipe pipe
= crtc
->pipe
;
1630 u32 val
, pipeconf_val
;
1632 /* Make sure PCH DPLL is enabled */
1633 assert_shared_dpll_enabled(dev_priv
, crtc_state
->shared_dpll
);
1635 /* FDI must be feeding us bits for PCH ports */
1636 assert_fdi_tx_enabled(dev_priv
, pipe
);
1637 assert_fdi_rx_enabled(dev_priv
, pipe
);
1639 if (HAS_PCH_CPT(dev_priv
)) {
1640 /* Workaround: Set the timing override bit before enabling the
1641 * pch transcoder. */
1642 reg
= TRANS_CHICKEN2(pipe
);
1643 val
= I915_READ(reg
);
1644 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1645 I915_WRITE(reg
, val
);
1648 reg
= PCH_TRANSCONF(pipe
);
1649 val
= I915_READ(reg
);
1650 pipeconf_val
= I915_READ(PIPECONF(pipe
));
1652 if (HAS_PCH_IBX(dev_priv
)) {
1654 * Make the BPC in transcoder be consistent with
1655 * that in pipeconf reg. For HDMI we must use 8bpc
1656 * here for both 8bpc and 12bpc.
1658 val
&= ~PIPECONF_BPC_MASK
;
1659 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_HDMI
))
1660 val
|= PIPECONF_8BPC
;
1662 val
|= pipeconf_val
& PIPECONF_BPC_MASK
;
1665 val
&= ~TRANS_INTERLACE_MASK
;
1666 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
) {
1667 if (HAS_PCH_IBX(dev_priv
) &&
1668 intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_SDVO
))
1669 val
|= TRANS_LEGACY_INTERLACED_ILK
;
1671 val
|= TRANS_INTERLACED
;
1673 val
|= TRANS_PROGRESSIVE
;
1676 I915_WRITE(reg
, val
| TRANS_ENABLE
);
1677 if (intel_wait_for_register(&dev_priv
->uncore
,
1678 reg
, TRANS_STATE_ENABLE
, TRANS_STATE_ENABLE
,
1680 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe
));
1683 static void lpt_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1684 enum transcoder cpu_transcoder
)
1686 u32 val
, pipeconf_val
;
1688 /* FDI must be feeding us bits for PCH ports */
1689 assert_fdi_tx_enabled(dev_priv
, (enum pipe
) cpu_transcoder
);
1690 assert_fdi_rx_enabled(dev_priv
, PIPE_A
);
1692 /* Workaround: set timing override bit. */
1693 val
= I915_READ(TRANS_CHICKEN2(PIPE_A
));
1694 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1695 I915_WRITE(TRANS_CHICKEN2(PIPE_A
), val
);
1698 pipeconf_val
= I915_READ(PIPECONF(cpu_transcoder
));
1700 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK_HSW
) ==
1701 PIPECONF_INTERLACED_ILK
)
1702 val
|= TRANS_INTERLACED
;
1704 val
|= TRANS_PROGRESSIVE
;
1706 I915_WRITE(LPT_TRANSCONF
, val
);
1707 if (intel_wait_for_register(&dev_priv
->uncore
,
1712 DRM_ERROR("Failed to enable PCH transcoder\n");
1715 static void ironlake_disable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1721 /* FDI relies on the transcoder */
1722 assert_fdi_tx_disabled(dev_priv
, pipe
);
1723 assert_fdi_rx_disabled(dev_priv
, pipe
);
1725 /* Ports must be off as well */
1726 assert_pch_ports_disabled(dev_priv
, pipe
);
1728 reg
= PCH_TRANSCONF(pipe
);
1729 val
= I915_READ(reg
);
1730 val
&= ~TRANS_ENABLE
;
1731 I915_WRITE(reg
, val
);
1732 /* wait for PCH transcoder off, transcoder state */
1733 if (intel_wait_for_register(&dev_priv
->uncore
,
1734 reg
, TRANS_STATE_ENABLE
, 0,
1736 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe
));
1738 if (HAS_PCH_CPT(dev_priv
)) {
1739 /* Workaround: Clear the timing override chicken bit again. */
1740 reg
= TRANS_CHICKEN2(pipe
);
1741 val
= I915_READ(reg
);
1742 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1743 I915_WRITE(reg
, val
);
1747 void lpt_disable_pch_transcoder(struct drm_i915_private
*dev_priv
)
1751 val
= I915_READ(LPT_TRANSCONF
);
1752 val
&= ~TRANS_ENABLE
;
1753 I915_WRITE(LPT_TRANSCONF
, val
);
1754 /* wait for PCH transcoder off, transcoder state */
1755 if (intel_wait_for_register(&dev_priv
->uncore
,
1756 LPT_TRANSCONF
, TRANS_STATE_ENABLE
, 0,
1758 DRM_ERROR("Failed to disable PCH transcoder\n");
1760 /* Workaround: clear timing override bit. */
1761 val
= I915_READ(TRANS_CHICKEN2(PIPE_A
));
1762 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1763 I915_WRITE(TRANS_CHICKEN2(PIPE_A
), val
);
1766 enum pipe
intel_crtc_pch_transcoder(struct intel_crtc
*crtc
)
1768 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1770 if (HAS_PCH_LPT(dev_priv
))
1776 static u32
intel_crtc_max_vblank_count(const struct intel_crtc_state
*crtc_state
)
1778 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->base
.crtc
->dev
);
1781 * On i965gm the hardware frame counter reads
1782 * zero when the TV encoder is enabled :(
1784 if (IS_I965GM(dev_priv
) &&
1785 (crtc_state
->output_types
& BIT(INTEL_OUTPUT_TVOUT
)))
1788 if (INTEL_GEN(dev_priv
) >= 5 || IS_G4X(dev_priv
))
1789 return 0xffffffff; /* full 32 bit counter */
1790 else if (INTEL_GEN(dev_priv
) >= 3)
1791 return 0xffffff; /* only 24 bits of frame count */
1793 return 0; /* Gen2 doesn't have a hardware frame counter */
1796 static void intel_crtc_vblank_on(const struct intel_crtc_state
*crtc_state
)
1798 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
1800 drm_crtc_set_max_vblank_count(&crtc
->base
,
1801 intel_crtc_max_vblank_count(crtc_state
));
1802 drm_crtc_vblank_on(&crtc
->base
);
1805 static void intel_enable_pipe(const struct intel_crtc_state
*new_crtc_state
)
1807 struct intel_crtc
*crtc
= to_intel_crtc(new_crtc_state
->base
.crtc
);
1808 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1809 enum transcoder cpu_transcoder
= new_crtc_state
->cpu_transcoder
;
1810 enum pipe pipe
= crtc
->pipe
;
1814 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe
));
1816 assert_planes_disabled(crtc
);
1819 * A pipe without a PLL won't actually be able to drive bits from
1820 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1823 if (HAS_GMCH(dev_priv
)) {
1824 if (intel_crtc_has_type(new_crtc_state
, INTEL_OUTPUT_DSI
))
1825 assert_dsi_pll_enabled(dev_priv
);
1827 assert_pll_enabled(dev_priv
, pipe
);
1829 if (new_crtc_state
->has_pch_encoder
) {
1830 /* if driving the PCH, we need FDI enabled */
1831 assert_fdi_rx_pll_enabled(dev_priv
,
1832 intel_crtc_pch_transcoder(crtc
));
1833 assert_fdi_tx_pll_enabled(dev_priv
,
1834 (enum pipe
) cpu_transcoder
);
1836 /* FIXME: assert CPU port conditions for SNB+ */
1839 trace_intel_pipe_enable(dev_priv
, pipe
);
1841 reg
= PIPECONF(cpu_transcoder
);
1842 val
= I915_READ(reg
);
1843 if (val
& PIPECONF_ENABLE
) {
1844 /* we keep both pipes enabled on 830 */
1845 WARN_ON(!IS_I830(dev_priv
));
1849 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
1853 * Until the pipe starts PIPEDSL reads will return a stale value,
1854 * which causes an apparent vblank timestamp jump when PIPEDSL
1855 * resets to its proper value. That also messes up the frame count
1856 * when it's derived from the timestamps. So let's wait for the
1857 * pipe to start properly before we call drm_crtc_vblank_on()
1859 if (intel_crtc_max_vblank_count(new_crtc_state
) == 0)
1860 intel_wait_for_pipe_scanline_moving(crtc
);
1863 static void intel_disable_pipe(const struct intel_crtc_state
*old_crtc_state
)
1865 struct intel_crtc
*crtc
= to_intel_crtc(old_crtc_state
->base
.crtc
);
1866 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1867 enum transcoder cpu_transcoder
= old_crtc_state
->cpu_transcoder
;
1868 enum pipe pipe
= crtc
->pipe
;
1872 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe
));
1875 * Make sure planes won't keep trying to pump pixels to us,
1876 * or we might hang the display.
1878 assert_planes_disabled(crtc
);
1880 trace_intel_pipe_disable(dev_priv
, pipe
);
1882 reg
= PIPECONF(cpu_transcoder
);
1883 val
= I915_READ(reg
);
1884 if ((val
& PIPECONF_ENABLE
) == 0)
1888 * Double wide has implications for planes
1889 * so best keep it disabled when not needed.
1891 if (old_crtc_state
->double_wide
)
1892 val
&= ~PIPECONF_DOUBLE_WIDE
;
1894 /* Don't disable pipe or pipe PLLs if needed */
1895 if (!IS_I830(dev_priv
))
1896 val
&= ~PIPECONF_ENABLE
;
1898 I915_WRITE(reg
, val
);
1899 if ((val
& PIPECONF_ENABLE
) == 0)
1900 intel_wait_for_pipe_off(old_crtc_state
);
1903 static unsigned int intel_tile_size(const struct drm_i915_private
*dev_priv
)
1905 return IS_GEN(dev_priv
, 2) ? 2048 : 4096;
1909 intel_tile_width_bytes(const struct drm_framebuffer
*fb
, int color_plane
)
1911 struct drm_i915_private
*dev_priv
= to_i915(fb
->dev
);
1912 unsigned int cpp
= fb
->format
->cpp
[color_plane
];
1914 switch (fb
->modifier
) {
1915 case DRM_FORMAT_MOD_LINEAR
:
1917 case I915_FORMAT_MOD_X_TILED
:
1918 if (IS_GEN(dev_priv
, 2))
1922 case I915_FORMAT_MOD_Y_TILED_CCS
:
1923 if (color_plane
== 1)
1926 case I915_FORMAT_MOD_Y_TILED
:
1927 if (IS_GEN(dev_priv
, 2) || HAS_128_BYTE_Y_TILING(dev_priv
))
1931 case I915_FORMAT_MOD_Yf_TILED_CCS
:
1932 if (color_plane
== 1)
1935 case I915_FORMAT_MOD_Yf_TILED
:
1951 MISSING_CASE(fb
->modifier
);
1957 intel_tile_height(const struct drm_framebuffer
*fb
, int color_plane
)
1959 if (fb
->modifier
== DRM_FORMAT_MOD_LINEAR
)
1962 return intel_tile_size(to_i915(fb
->dev
)) /
1963 intel_tile_width_bytes(fb
, color_plane
);
1966 /* Return the tile dimensions in pixel units */
1967 static void intel_tile_dims(const struct drm_framebuffer
*fb
, int color_plane
,
1968 unsigned int *tile_width
,
1969 unsigned int *tile_height
)
1971 unsigned int tile_width_bytes
= intel_tile_width_bytes(fb
, color_plane
);
1972 unsigned int cpp
= fb
->format
->cpp
[color_plane
];
1974 *tile_width
= tile_width_bytes
/ cpp
;
1975 *tile_height
= intel_tile_size(to_i915(fb
->dev
)) / tile_width_bytes
;
1979 intel_fb_align_height(const struct drm_framebuffer
*fb
,
1980 int color_plane
, unsigned int height
)
1982 unsigned int tile_height
= intel_tile_height(fb
, color_plane
);
1984 return ALIGN(height
, tile_height
);
1987 unsigned int intel_rotation_info_size(const struct intel_rotation_info
*rot_info
)
1989 unsigned int size
= 0;
1992 for (i
= 0 ; i
< ARRAY_SIZE(rot_info
->plane
); i
++)
1993 size
+= rot_info
->plane
[i
].width
* rot_info
->plane
[i
].height
;
1999 intel_fill_fb_ggtt_view(struct i915_ggtt_view
*view
,
2000 const struct drm_framebuffer
*fb
,
2001 unsigned int rotation
)
2003 view
->type
= I915_GGTT_VIEW_NORMAL
;
2004 if (drm_rotation_90_or_270(rotation
)) {
2005 view
->type
= I915_GGTT_VIEW_ROTATED
;
2006 view
->rotated
= to_intel_framebuffer(fb
)->rot_info
;
2010 static unsigned int intel_cursor_alignment(const struct drm_i915_private
*dev_priv
)
2012 if (IS_I830(dev_priv
))
2014 else if (IS_I85X(dev_priv
))
2016 else if (IS_I845G(dev_priv
) || IS_I865G(dev_priv
))
2022 static unsigned int intel_linear_alignment(const struct drm_i915_private
*dev_priv
)
2024 if (INTEL_GEN(dev_priv
) >= 9)
2026 else if (IS_I965G(dev_priv
) || IS_I965GM(dev_priv
) ||
2027 IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
2029 else if (INTEL_GEN(dev_priv
) >= 4)
2035 static unsigned int intel_surf_alignment(const struct drm_framebuffer
*fb
,
2038 struct drm_i915_private
*dev_priv
= to_i915(fb
->dev
);
2040 /* AUX_DIST needs only 4K alignment */
2041 if (color_plane
== 1)
2044 switch (fb
->modifier
) {
2045 case DRM_FORMAT_MOD_LINEAR
:
2046 return intel_linear_alignment(dev_priv
);
2047 case I915_FORMAT_MOD_X_TILED
:
2048 if (INTEL_GEN(dev_priv
) >= 9)
2051 case I915_FORMAT_MOD_Y_TILED_CCS
:
2052 case I915_FORMAT_MOD_Yf_TILED_CCS
:
2053 case I915_FORMAT_MOD_Y_TILED
:
2054 case I915_FORMAT_MOD_Yf_TILED
:
2055 return 1 * 1024 * 1024;
2057 MISSING_CASE(fb
->modifier
);
2062 static bool intel_plane_uses_fence(const struct intel_plane_state
*plane_state
)
2064 struct intel_plane
*plane
= to_intel_plane(plane_state
->base
.plane
);
2065 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
2067 return INTEL_GEN(dev_priv
) < 4 || plane
->has_fbc
;
2071 intel_pin_and_fence_fb_obj(struct drm_framebuffer
*fb
,
2072 const struct i915_ggtt_view
*view
,
2074 unsigned long *out_flags
)
2076 struct drm_device
*dev
= fb
->dev
;
2077 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2078 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2079 intel_wakeref_t wakeref
;
2080 struct i915_vma
*vma
;
2081 unsigned int pinctl
;
2084 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
2086 alignment
= intel_surf_alignment(fb
, 0);
2088 /* Note that the w/a also requires 64 PTE of padding following the
2089 * bo. We currently fill all unused PTE with the shadow page and so
2090 * we should always have valid PTE following the scanout preventing
2093 if (intel_scanout_needs_vtd_wa(dev_priv
) && alignment
< 256 * 1024)
2094 alignment
= 256 * 1024;
2097 * Global gtt pte registers are special registers which actually forward
2098 * writes to a chunk of system memory. Which means that there is no risk
2099 * that the register values disappear as soon as we call
2100 * intel_runtime_pm_put(), so it is correct to wrap only the
2101 * pin/unpin/fence and not more.
2103 wakeref
= intel_runtime_pm_get(dev_priv
);
2105 atomic_inc(&dev_priv
->gpu_error
.pending_fb_pin
);
2109 /* Valleyview is definitely limited to scanning out the first
2110 * 512MiB. Lets presume this behaviour was inherited from the
2111 * g4x display engine and that all earlier gen are similarly
2112 * limited. Testing suggests that it is a little more
2113 * complicated than this. For example, Cherryview appears quite
2114 * happy to scanout from anywhere within its global aperture.
2116 if (HAS_GMCH(dev_priv
))
2117 pinctl
|= PIN_MAPPABLE
;
2119 vma
= i915_gem_object_pin_to_display_plane(obj
,
2120 alignment
, view
, pinctl
);
2124 if (uses_fence
&& i915_vma_is_map_and_fenceable(vma
)) {
2127 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2128 * fence, whereas 965+ only requires a fence if using
2129 * framebuffer compression. For simplicity, we always, when
2130 * possible, install a fence as the cost is not that onerous.
2132 * If we fail to fence the tiled scanout, then either the
2133 * modeset will reject the change (which is highly unlikely as
2134 * the affected systems, all but one, do not have unmappable
2135 * space) or we will not be able to enable full powersaving
2136 * techniques (also likely not to apply due to various limits
2137 * FBC and the like impose on the size of the buffer, which
2138 * presumably we violated anyway with this unmappable buffer).
2139 * Anyway, it is presumably better to stumble onwards with
2140 * something and try to run the system in a "less than optimal"
2141 * mode that matches the user configuration.
2143 ret
= i915_vma_pin_fence(vma
);
2144 if (ret
!= 0 && INTEL_GEN(dev_priv
) < 4) {
2145 i915_gem_object_unpin_from_display_plane(vma
);
2150 if (ret
== 0 && vma
->fence
)
2151 *out_flags
|= PLANE_HAS_FENCE
;
2156 atomic_dec(&dev_priv
->gpu_error
.pending_fb_pin
);
2158 intel_runtime_pm_put(dev_priv
, wakeref
);
2162 void intel_unpin_fb_vma(struct i915_vma
*vma
, unsigned long flags
)
2164 lockdep_assert_held(&vma
->vm
->i915
->drm
.struct_mutex
);
2166 if (flags
& PLANE_HAS_FENCE
)
2167 i915_vma_unpin_fence(vma
);
2168 i915_gem_object_unpin_from_display_plane(vma
);
2172 static int intel_fb_pitch(const struct drm_framebuffer
*fb
, int color_plane
,
2173 unsigned int rotation
)
2175 if (drm_rotation_90_or_270(rotation
))
2176 return to_intel_framebuffer(fb
)->rotated
[color_plane
].pitch
;
2178 return fb
->pitches
[color_plane
];
2182 * Convert the x/y offsets into a linear offset.
2183 * Only valid with 0/180 degree rotation, which is fine since linear
2184 * offset is only used with linear buffers on pre-hsw and tiled buffers
2185 * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2187 u32
intel_fb_xy_to_linear(int x
, int y
,
2188 const struct intel_plane_state
*state
,
2191 const struct drm_framebuffer
*fb
= state
->base
.fb
;
2192 unsigned int cpp
= fb
->format
->cpp
[color_plane
];
2193 unsigned int pitch
= state
->color_plane
[color_plane
].stride
;
2195 return y
* pitch
+ x
* cpp
;
2199 * Add the x/y offsets derived from fb->offsets[] to the user
2200 * specified plane src x/y offsets. The resulting x/y offsets
2201 * specify the start of scanout from the beginning of the gtt mapping.
2203 void intel_add_fb_offsets(int *x
, int *y
,
2204 const struct intel_plane_state
*state
,
2208 const struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(state
->base
.fb
);
2209 unsigned int rotation
= state
->base
.rotation
;
2211 if (drm_rotation_90_or_270(rotation
)) {
2212 *x
+= intel_fb
->rotated
[color_plane
].x
;
2213 *y
+= intel_fb
->rotated
[color_plane
].y
;
2215 *x
+= intel_fb
->normal
[color_plane
].x
;
2216 *y
+= intel_fb
->normal
[color_plane
].y
;
2220 static u32
intel_adjust_tile_offset(int *x
, int *y
,
2221 unsigned int tile_width
,
2222 unsigned int tile_height
,
2223 unsigned int tile_size
,
2224 unsigned int pitch_tiles
,
2228 unsigned int pitch_pixels
= pitch_tiles
* tile_width
;
2231 WARN_ON(old_offset
& (tile_size
- 1));
2232 WARN_ON(new_offset
& (tile_size
- 1));
2233 WARN_ON(new_offset
> old_offset
);
2235 tiles
= (old_offset
- new_offset
) / tile_size
;
2237 *y
+= tiles
/ pitch_tiles
* tile_height
;
2238 *x
+= tiles
% pitch_tiles
* tile_width
;
2240 /* minimize x in case it got needlessly big */
2241 *y
+= *x
/ pitch_pixels
* tile_height
;
2247 static bool is_surface_linear(u64 modifier
, int color_plane
)
2249 return modifier
== DRM_FORMAT_MOD_LINEAR
;
2252 static u32
intel_adjust_aligned_offset(int *x
, int *y
,
2253 const struct drm_framebuffer
*fb
,
2255 unsigned int rotation
,
2257 u32 old_offset
, u32 new_offset
)
2259 struct drm_i915_private
*dev_priv
= to_i915(fb
->dev
);
2260 unsigned int cpp
= fb
->format
->cpp
[color_plane
];
2262 WARN_ON(new_offset
> old_offset
);
2264 if (!is_surface_linear(fb
->modifier
, color_plane
)) {
2265 unsigned int tile_size
, tile_width
, tile_height
;
2266 unsigned int pitch_tiles
;
2268 tile_size
= intel_tile_size(dev_priv
);
2269 intel_tile_dims(fb
, color_plane
, &tile_width
, &tile_height
);
2271 if (drm_rotation_90_or_270(rotation
)) {
2272 pitch_tiles
= pitch
/ tile_height
;
2273 swap(tile_width
, tile_height
);
2275 pitch_tiles
= pitch
/ (tile_width
* cpp
);
2278 intel_adjust_tile_offset(x
, y
, tile_width
, tile_height
,
2279 tile_size
, pitch_tiles
,
2280 old_offset
, new_offset
);
2282 old_offset
+= *y
* pitch
+ *x
* cpp
;
2284 *y
= (old_offset
- new_offset
) / pitch
;
2285 *x
= ((old_offset
- new_offset
) - *y
* pitch
) / cpp
;
2292 * Adjust the tile offset by moving the difference into
2295 static u32
intel_plane_adjust_aligned_offset(int *x
, int *y
,
2296 const struct intel_plane_state
*state
,
2298 u32 old_offset
, u32 new_offset
)
2300 return intel_adjust_aligned_offset(x
, y
, state
->base
.fb
, color_plane
,
2301 state
->base
.rotation
,
2302 state
->color_plane
[color_plane
].stride
,
2303 old_offset
, new_offset
);
2307 * Computes the aligned offset to the base tile and adjusts
2308 * x, y. bytes per pixel is assumed to be a power-of-two.
2310 * In the 90/270 rotated case, x and y are assumed
2311 * to be already rotated to match the rotated GTT view, and
2312 * pitch is the tile_height aligned framebuffer height.
2314 * This function is used when computing the derived information
2315 * under intel_framebuffer, so using any of that information
2316 * here is not allowed. Anything under drm_framebuffer can be
2317 * used. This is why the user has to pass in the pitch since it
2318 * is specified in the rotated orientation.
2320 static u32
intel_compute_aligned_offset(struct drm_i915_private
*dev_priv
,
2322 const struct drm_framebuffer
*fb
,
2325 unsigned int rotation
,
2328 unsigned int cpp
= fb
->format
->cpp
[color_plane
];
2329 u32 offset
, offset_aligned
;
2334 if (!is_surface_linear(fb
->modifier
, color_plane
)) {
2335 unsigned int tile_size
, tile_width
, tile_height
;
2336 unsigned int tile_rows
, tiles
, pitch_tiles
;
2338 tile_size
= intel_tile_size(dev_priv
);
2339 intel_tile_dims(fb
, color_plane
, &tile_width
, &tile_height
);
2341 if (drm_rotation_90_or_270(rotation
)) {
2342 pitch_tiles
= pitch
/ tile_height
;
2343 swap(tile_width
, tile_height
);
2345 pitch_tiles
= pitch
/ (tile_width
* cpp
);
2348 tile_rows
= *y
/ tile_height
;
2351 tiles
= *x
/ tile_width
;
2354 offset
= (tile_rows
* pitch_tiles
+ tiles
) * tile_size
;
2355 offset_aligned
= offset
& ~alignment
;
2357 intel_adjust_tile_offset(x
, y
, tile_width
, tile_height
,
2358 tile_size
, pitch_tiles
,
2359 offset
, offset_aligned
);
2361 offset
= *y
* pitch
+ *x
* cpp
;
2362 offset_aligned
= offset
& ~alignment
;
2364 *y
= (offset
& alignment
) / pitch
;
2365 *x
= ((offset
& alignment
) - *y
* pitch
) / cpp
;
2368 return offset_aligned
;
2371 static u32
intel_plane_compute_aligned_offset(int *x
, int *y
,
2372 const struct intel_plane_state
*state
,
2375 struct intel_plane
*intel_plane
= to_intel_plane(state
->base
.plane
);
2376 struct drm_i915_private
*dev_priv
= to_i915(intel_plane
->base
.dev
);
2377 const struct drm_framebuffer
*fb
= state
->base
.fb
;
2378 unsigned int rotation
= state
->base
.rotation
;
2379 int pitch
= state
->color_plane
[color_plane
].stride
;
2382 if (intel_plane
->id
== PLANE_CURSOR
)
2383 alignment
= intel_cursor_alignment(dev_priv
);
2385 alignment
= intel_surf_alignment(fb
, color_plane
);
2387 return intel_compute_aligned_offset(dev_priv
, x
, y
, fb
, color_plane
,
2388 pitch
, rotation
, alignment
);
2391 /* Convert the fb->offset[] into x/y offsets */
2392 static int intel_fb_offset_to_xy(int *x
, int *y
,
2393 const struct drm_framebuffer
*fb
,
2396 struct drm_i915_private
*dev_priv
= to_i915(fb
->dev
);
2397 unsigned int height
;
2399 if (fb
->modifier
!= DRM_FORMAT_MOD_LINEAR
&&
2400 fb
->offsets
[color_plane
] % intel_tile_size(dev_priv
)) {
2401 DRM_DEBUG_KMS("Misaligned offset 0x%08x for color plane %d\n",
2402 fb
->offsets
[color_plane
], color_plane
);
2406 height
= drm_framebuffer_plane_height(fb
->height
, fb
, color_plane
);
2407 height
= ALIGN(height
, intel_tile_height(fb
, color_plane
));
2409 /* Catch potential overflows early */
2410 if (add_overflows_t(u32
, mul_u32_u32(height
, fb
->pitches
[color_plane
]),
2411 fb
->offsets
[color_plane
])) {
2412 DRM_DEBUG_KMS("Bad offset 0x%08x or pitch %d for color plane %d\n",
2413 fb
->offsets
[color_plane
], fb
->pitches
[color_plane
],
2421 intel_adjust_aligned_offset(x
, y
,
2422 fb
, color_plane
, DRM_MODE_ROTATE_0
,
2423 fb
->pitches
[color_plane
],
2424 fb
->offsets
[color_plane
], 0);
2429 static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier
)
2431 switch (fb_modifier
) {
2432 case I915_FORMAT_MOD_X_TILED
:
2433 return I915_TILING_X
;
2434 case I915_FORMAT_MOD_Y_TILED
:
2435 case I915_FORMAT_MOD_Y_TILED_CCS
:
2436 return I915_TILING_Y
;
2438 return I915_TILING_NONE
;
2443 * From the Sky Lake PRM:
2444 * "The Color Control Surface (CCS) contains the compression status of
2445 * the cache-line pairs. The compression state of the cache-line pair
2446 * is specified by 2 bits in the CCS. Each CCS cache-line represents
2447 * an area on the main surface of 16 x16 sets of 128 byte Y-tiled
2448 * cache-line-pairs. CCS is always Y tiled."
2450 * Since cache line pairs refers to horizontally adjacent cache lines,
2451 * each cache line in the CCS corresponds to an area of 32x16 cache
2452 * lines on the main surface. Since each pixel is 4 bytes, this gives
2453 * us a ratio of one byte in the CCS for each 8x16 pixels in the
2456 static const struct drm_format_info ccs_formats
[] = {
2457 { .format
= DRM_FORMAT_XRGB8888
, .depth
= 24, .num_planes
= 2, .cpp
= { 4, 1, }, .hsub
= 8, .vsub
= 16, },
2458 { .format
= DRM_FORMAT_XBGR8888
, .depth
= 24, .num_planes
= 2, .cpp
= { 4, 1, }, .hsub
= 8, .vsub
= 16, },
2459 { .format
= DRM_FORMAT_ARGB8888
, .depth
= 32, .num_planes
= 2, .cpp
= { 4, 1, }, .hsub
= 8, .vsub
= 16, },
2460 { .format
= DRM_FORMAT_ABGR8888
, .depth
= 32, .num_planes
= 2, .cpp
= { 4, 1, }, .hsub
= 8, .vsub
= 16, },
2463 static const struct drm_format_info
*
2464 lookup_format_info(const struct drm_format_info formats
[],
2465 int num_formats
, u32 format
)
2469 for (i
= 0; i
< num_formats
; i
++) {
2470 if (formats
[i
].format
== format
)
2477 static const struct drm_format_info
*
2478 intel_get_format_info(const struct drm_mode_fb_cmd2
*cmd
)
2480 switch (cmd
->modifier
[0]) {
2481 case I915_FORMAT_MOD_Y_TILED_CCS
:
2482 case I915_FORMAT_MOD_Yf_TILED_CCS
:
2483 return lookup_format_info(ccs_formats
,
2484 ARRAY_SIZE(ccs_formats
),
2491 bool is_ccs_modifier(u64 modifier
)
2493 return modifier
== I915_FORMAT_MOD_Y_TILED_CCS
||
2494 modifier
== I915_FORMAT_MOD_Yf_TILED_CCS
;
2498 intel_fill_fb_info(struct drm_i915_private
*dev_priv
,
2499 struct drm_framebuffer
*fb
)
2501 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
2502 struct intel_rotation_info
*rot_info
= &intel_fb
->rot_info
;
2503 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2504 u32 gtt_offset_rotated
= 0;
2505 unsigned int max_size
= 0;
2506 int i
, num_planes
= fb
->format
->num_planes
;
2507 unsigned int tile_size
= intel_tile_size(dev_priv
);
2509 for (i
= 0; i
< num_planes
; i
++) {
2510 unsigned int width
, height
;
2511 unsigned int cpp
, size
;
2516 cpp
= fb
->format
->cpp
[i
];
2517 width
= drm_framebuffer_plane_width(fb
->width
, fb
, i
);
2518 height
= drm_framebuffer_plane_height(fb
->height
, fb
, i
);
2520 ret
= intel_fb_offset_to_xy(&x
, &y
, fb
, i
);
2522 DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2527 if (is_ccs_modifier(fb
->modifier
) && i
== 1) {
2528 int hsub
= fb
->format
->hsub
;
2529 int vsub
= fb
->format
->vsub
;
2530 int tile_width
, tile_height
;
2534 intel_tile_dims(fb
, i
, &tile_width
, &tile_height
);
2536 tile_height
*= vsub
;
2538 ccs_x
= (x
* hsub
) % tile_width
;
2539 ccs_y
= (y
* vsub
) % tile_height
;
2540 main_x
= intel_fb
->normal
[0].x
% tile_width
;
2541 main_y
= intel_fb
->normal
[0].y
% tile_height
;
2544 * CCS doesn't have its own x/y offset register, so the intra CCS tile
2545 * x/y offsets must match between CCS and the main surface.
2547 if (main_x
!= ccs_x
|| main_y
!= ccs_y
) {
2548 DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
2551 intel_fb
->normal
[0].x
,
2552 intel_fb
->normal
[0].y
,
2559 * The fence (if used) is aligned to the start of the object
2560 * so having the framebuffer wrap around across the edge of the
2561 * fenced region doesn't really work. We have no API to configure
2562 * the fence start offset within the object (nor could we probably
2563 * on gen2/3). So it's just easier if we just require that the
2564 * fb layout agrees with the fence layout. We already check that the
2565 * fb stride matches the fence stride elsewhere.
2567 if (i
== 0 && i915_gem_object_is_tiled(obj
) &&
2568 (x
+ width
) * cpp
> fb
->pitches
[i
]) {
2569 DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2575 * First pixel of the framebuffer from
2576 * the start of the normal gtt mapping.
2578 intel_fb
->normal
[i
].x
= x
;
2579 intel_fb
->normal
[i
].y
= y
;
2581 offset
= intel_compute_aligned_offset(dev_priv
, &x
, &y
, fb
, i
,
2585 offset
/= tile_size
;
2587 if (!is_surface_linear(fb
->modifier
, i
)) {
2588 unsigned int tile_width
, tile_height
;
2589 unsigned int pitch_tiles
;
2592 intel_tile_dims(fb
, i
, &tile_width
, &tile_height
);
2594 rot_info
->plane
[i
].offset
= offset
;
2595 rot_info
->plane
[i
].stride
= DIV_ROUND_UP(fb
->pitches
[i
], tile_width
* cpp
);
2596 rot_info
->plane
[i
].width
= DIV_ROUND_UP(x
+ width
, tile_width
);
2597 rot_info
->plane
[i
].height
= DIV_ROUND_UP(y
+ height
, tile_height
);
2599 intel_fb
->rotated
[i
].pitch
=
2600 rot_info
->plane
[i
].height
* tile_height
;
2602 /* how many tiles does this plane need */
2603 size
= rot_info
->plane
[i
].stride
* rot_info
->plane
[i
].height
;
2605 * If the plane isn't horizontally tile aligned,
2606 * we need one more tile.
2611 /* rotate the x/y offsets to match the GTT view */
2617 rot_info
->plane
[i
].width
* tile_width
,
2618 rot_info
->plane
[i
].height
* tile_height
,
2619 DRM_MODE_ROTATE_270
);
2623 /* rotate the tile dimensions to match the GTT view */
2624 pitch_tiles
= intel_fb
->rotated
[i
].pitch
/ tile_height
;
2625 swap(tile_width
, tile_height
);
2628 * We only keep the x/y offsets, so push all of the
2629 * gtt offset into the x/y offsets.
2631 intel_adjust_tile_offset(&x
, &y
,
2632 tile_width
, tile_height
,
2633 tile_size
, pitch_tiles
,
2634 gtt_offset_rotated
* tile_size
, 0);
2636 gtt_offset_rotated
+= rot_info
->plane
[i
].width
* rot_info
->plane
[i
].height
;
2639 * First pixel of the framebuffer from
2640 * the start of the rotated gtt mapping.
2642 intel_fb
->rotated
[i
].x
= x
;
2643 intel_fb
->rotated
[i
].y
= y
;
2645 size
= DIV_ROUND_UP((y
+ height
) * fb
->pitches
[i
] +
2646 x
* cpp
, tile_size
);
2649 /* how many tiles in total needed in the bo */
2650 max_size
= max(max_size
, offset
+ size
);
2653 if (mul_u32_u32(max_size
, tile_size
) > obj
->base
.size
) {
2654 DRM_DEBUG_KMS("fb too big for bo (need %llu bytes, have %zu bytes)\n",
2655 mul_u32_u32(max_size
, tile_size
), obj
->base
.size
);
2662 static int i9xx_format_to_fourcc(int format
)
2665 case DISPPLANE_8BPP
:
2666 return DRM_FORMAT_C8
;
2667 case DISPPLANE_BGRX555
:
2668 return DRM_FORMAT_XRGB1555
;
2669 case DISPPLANE_BGRX565
:
2670 return DRM_FORMAT_RGB565
;
2672 case DISPPLANE_BGRX888
:
2673 return DRM_FORMAT_XRGB8888
;
2674 case DISPPLANE_RGBX888
:
2675 return DRM_FORMAT_XBGR8888
;
2676 case DISPPLANE_BGRX101010
:
2677 return DRM_FORMAT_XRGB2101010
;
2678 case DISPPLANE_RGBX101010
:
2679 return DRM_FORMAT_XBGR2101010
;
2683 int skl_format_to_fourcc(int format
, bool rgb_order
, bool alpha
)
2686 case PLANE_CTL_FORMAT_RGB_565
:
2687 return DRM_FORMAT_RGB565
;
2688 case PLANE_CTL_FORMAT_NV12
:
2689 return DRM_FORMAT_NV12
;
2690 case PLANE_CTL_FORMAT_P010
:
2691 return DRM_FORMAT_P010
;
2692 case PLANE_CTL_FORMAT_P012
:
2693 return DRM_FORMAT_P012
;
2694 case PLANE_CTL_FORMAT_P016
:
2695 return DRM_FORMAT_P016
;
2696 case PLANE_CTL_FORMAT_Y210
:
2697 return DRM_FORMAT_Y210
;
2698 case PLANE_CTL_FORMAT_Y212
:
2699 return DRM_FORMAT_Y212
;
2700 case PLANE_CTL_FORMAT_Y216
:
2701 return DRM_FORMAT_Y216
;
2702 case PLANE_CTL_FORMAT_Y410
:
2703 return DRM_FORMAT_XVYU2101010
;
2704 case PLANE_CTL_FORMAT_Y412
:
2705 return DRM_FORMAT_XVYU12_16161616
;
2706 case PLANE_CTL_FORMAT_Y416
:
2707 return DRM_FORMAT_XVYU16161616
;
2709 case PLANE_CTL_FORMAT_XRGB_8888
:
2712 return DRM_FORMAT_ABGR8888
;
2714 return DRM_FORMAT_XBGR8888
;
2717 return DRM_FORMAT_ARGB8888
;
2719 return DRM_FORMAT_XRGB8888
;
2721 case PLANE_CTL_FORMAT_XRGB_2101010
:
2723 return DRM_FORMAT_XBGR2101010
;
2725 return DRM_FORMAT_XRGB2101010
;
2726 case PLANE_CTL_FORMAT_XRGB_16161616F
:
2729 return DRM_FORMAT_ABGR16161616F
;
2731 return DRM_FORMAT_XBGR16161616F
;
2734 return DRM_FORMAT_ARGB16161616F
;
2736 return DRM_FORMAT_XRGB16161616F
;
2742 intel_alloc_initial_plane_obj(struct intel_crtc
*crtc
,
2743 struct intel_initial_plane_config
*plane_config
)
2745 struct drm_device
*dev
= crtc
->base
.dev
;
2746 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2747 struct drm_i915_gem_object
*obj
= NULL
;
2748 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
2749 struct drm_framebuffer
*fb
= &plane_config
->fb
->base
;
2750 u32 base_aligned
= round_down(plane_config
->base
, PAGE_SIZE
);
2751 u32 size_aligned
= round_up(plane_config
->base
+ plane_config
->size
,
2754 size_aligned
-= base_aligned
;
2756 if (plane_config
->size
== 0)
2759 /* If the FB is too big, just don't use it since fbdev is not very
2760 * important and we should probably use that space with FBC or other
2762 if (size_aligned
* 2 > dev_priv
->stolen_usable_size
)
2765 switch (fb
->modifier
) {
2766 case DRM_FORMAT_MOD_LINEAR
:
2767 case I915_FORMAT_MOD_X_TILED
:
2768 case I915_FORMAT_MOD_Y_TILED
:
2771 DRM_DEBUG_DRIVER("Unsupported modifier for initial FB: 0x%llx\n",
2776 mutex_lock(&dev
->struct_mutex
);
2777 obj
= i915_gem_object_create_stolen_for_preallocated(dev_priv
,
2781 mutex_unlock(&dev
->struct_mutex
);
2785 switch (plane_config
->tiling
) {
2786 case I915_TILING_NONE
:
2790 obj
->tiling_and_stride
= fb
->pitches
[0] | plane_config
->tiling
;
2793 MISSING_CASE(plane_config
->tiling
);
2797 mode_cmd
.pixel_format
= fb
->format
->format
;
2798 mode_cmd
.width
= fb
->width
;
2799 mode_cmd
.height
= fb
->height
;
2800 mode_cmd
.pitches
[0] = fb
->pitches
[0];
2801 mode_cmd
.modifier
[0] = fb
->modifier
;
2802 mode_cmd
.flags
= DRM_MODE_FB_MODIFIERS
;
2804 if (intel_framebuffer_init(to_intel_framebuffer(fb
), obj
, &mode_cmd
)) {
2805 DRM_DEBUG_KMS("intel fb init failed\n");
2810 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj
);
2814 i915_gem_object_put(obj
);
2819 intel_set_plane_visible(struct intel_crtc_state
*crtc_state
,
2820 struct intel_plane_state
*plane_state
,
2823 struct intel_plane
*plane
= to_intel_plane(plane_state
->base
.plane
);
2825 plane_state
->base
.visible
= visible
;
2828 crtc_state
->base
.plane_mask
|= drm_plane_mask(&plane
->base
);
2830 crtc_state
->base
.plane_mask
&= ~drm_plane_mask(&plane
->base
);
2833 static void fixup_active_planes(struct intel_crtc_state
*crtc_state
)
2835 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->base
.crtc
->dev
);
2836 struct drm_plane
*plane
;
2839 * Active_planes aliases if multiple "primary" or cursor planes
2840 * have been used on the same (or wrong) pipe. plane_mask uses
2841 * unique ids, hence we can use that to reconstruct active_planes.
2843 crtc_state
->active_planes
= 0;
2845 drm_for_each_plane_mask(plane
, &dev_priv
->drm
,
2846 crtc_state
->base
.plane_mask
)
2847 crtc_state
->active_planes
|= BIT(to_intel_plane(plane
)->id
);
2850 static void intel_plane_disable_noatomic(struct intel_crtc
*crtc
,
2851 struct intel_plane
*plane
)
2853 struct intel_crtc_state
*crtc_state
=
2854 to_intel_crtc_state(crtc
->base
.state
);
2855 struct intel_plane_state
*plane_state
=
2856 to_intel_plane_state(plane
->base
.state
);
2858 DRM_DEBUG_KMS("Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n",
2859 plane
->base
.base
.id
, plane
->base
.name
,
2860 crtc
->base
.base
.id
, crtc
->base
.name
);
2862 intel_set_plane_visible(crtc_state
, plane_state
, false);
2863 fixup_active_planes(crtc_state
);
2865 if (plane
->id
== PLANE_PRIMARY
)
2866 intel_pre_disable_primary_noatomic(&crtc
->base
);
2868 intel_disable_plane(plane
, crtc_state
);
2872 intel_find_initial_plane_obj(struct intel_crtc
*intel_crtc
,
2873 struct intel_initial_plane_config
*plane_config
)
2875 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2876 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2878 struct drm_i915_gem_object
*obj
;
2879 struct drm_plane
*primary
= intel_crtc
->base
.primary
;
2880 struct drm_plane_state
*plane_state
= primary
->state
;
2881 struct intel_plane
*intel_plane
= to_intel_plane(primary
);
2882 struct intel_plane_state
*intel_state
=
2883 to_intel_plane_state(plane_state
);
2884 struct drm_framebuffer
*fb
;
2886 if (!plane_config
->fb
)
2889 if (intel_alloc_initial_plane_obj(intel_crtc
, plane_config
)) {
2890 fb
= &plane_config
->fb
->base
;
2894 kfree(plane_config
->fb
);
2897 * Failed to alloc the obj, check to see if we should share
2898 * an fb with another CRTC instead
2900 for_each_crtc(dev
, c
) {
2901 struct intel_plane_state
*state
;
2903 if (c
== &intel_crtc
->base
)
2906 if (!to_intel_crtc(c
)->active
)
2909 state
= to_intel_plane_state(c
->primary
->state
);
2913 if (intel_plane_ggtt_offset(state
) == plane_config
->base
) {
2914 fb
= state
->base
.fb
;
2915 drm_framebuffer_get(fb
);
2921 * We've failed to reconstruct the BIOS FB. Current display state
2922 * indicates that the primary plane is visible, but has a NULL FB,
2923 * which will lead to problems later if we don't fix it up. The
2924 * simplest solution is to just disable the primary plane now and
2925 * pretend the BIOS never had it enabled.
2927 intel_plane_disable_noatomic(intel_crtc
, intel_plane
);
2932 intel_state
->base
.rotation
= plane_config
->rotation
;
2933 intel_fill_fb_ggtt_view(&intel_state
->view
, fb
,
2934 intel_state
->base
.rotation
);
2935 intel_state
->color_plane
[0].stride
=
2936 intel_fb_pitch(fb
, 0, intel_state
->base
.rotation
);
2938 mutex_lock(&dev
->struct_mutex
);
2940 intel_pin_and_fence_fb_obj(fb
,
2942 intel_plane_uses_fence(intel_state
),
2943 &intel_state
->flags
);
2944 mutex_unlock(&dev
->struct_mutex
);
2945 if (IS_ERR(intel_state
->vma
)) {
2946 DRM_ERROR("failed to pin boot fb on pipe %d: %li\n",
2947 intel_crtc
->pipe
, PTR_ERR(intel_state
->vma
));
2949 intel_state
->vma
= NULL
;
2950 drm_framebuffer_put(fb
);
2954 obj
= intel_fb_obj(fb
);
2955 intel_fb_obj_flush(obj
, ORIGIN_DIRTYFB
);
2957 plane_state
->src_x
= 0;
2958 plane_state
->src_y
= 0;
2959 plane_state
->src_w
= fb
->width
<< 16;
2960 plane_state
->src_h
= fb
->height
<< 16;
2962 plane_state
->crtc_x
= 0;
2963 plane_state
->crtc_y
= 0;
2964 plane_state
->crtc_w
= fb
->width
;
2965 plane_state
->crtc_h
= fb
->height
;
2967 intel_state
->base
.src
= drm_plane_state_src(plane_state
);
2968 intel_state
->base
.dst
= drm_plane_state_dest(plane_state
);
2970 if (i915_gem_object_is_tiled(obj
))
2971 dev_priv
->preserve_bios_swizzle
= true;
2973 plane_state
->fb
= fb
;
2974 plane_state
->crtc
= &intel_crtc
->base
;
2976 atomic_or(to_intel_plane(primary
)->frontbuffer_bit
,
2977 &obj
->frontbuffer_bits
);
2980 static int skl_max_plane_width(const struct drm_framebuffer
*fb
,
2982 unsigned int rotation
)
2984 int cpp
= fb
->format
->cpp
[color_plane
];
2986 switch (fb
->modifier
) {
2987 case DRM_FORMAT_MOD_LINEAR
:
2988 case I915_FORMAT_MOD_X_TILED
:
2990 case I915_FORMAT_MOD_Y_TILED_CCS
:
2991 case I915_FORMAT_MOD_Yf_TILED_CCS
:
2992 /* FIXME AUX plane? */
2993 case I915_FORMAT_MOD_Y_TILED
:
2994 case I915_FORMAT_MOD_Yf_TILED
:
3000 MISSING_CASE(fb
->modifier
);
3005 static int glk_max_plane_width(const struct drm_framebuffer
*fb
,
3007 unsigned int rotation
)
3009 int cpp
= fb
->format
->cpp
[color_plane
];
3011 switch (fb
->modifier
) {
3012 case DRM_FORMAT_MOD_LINEAR
:
3013 case I915_FORMAT_MOD_X_TILED
:
3018 case I915_FORMAT_MOD_Y_TILED_CCS
:
3019 case I915_FORMAT_MOD_Yf_TILED_CCS
:
3020 /* FIXME AUX plane? */
3021 case I915_FORMAT_MOD_Y_TILED
:
3022 case I915_FORMAT_MOD_Yf_TILED
:
3028 MISSING_CASE(fb
->modifier
);
3033 static int icl_max_plane_width(const struct drm_framebuffer
*fb
,
3035 unsigned int rotation
)
3040 static bool skl_check_main_ccs_coordinates(struct intel_plane_state
*plane_state
,
3041 int main_x
, int main_y
, u32 main_offset
)
3043 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
3044 int hsub
= fb
->format
->hsub
;
3045 int vsub
= fb
->format
->vsub
;
3046 int aux_x
= plane_state
->color_plane
[1].x
;
3047 int aux_y
= plane_state
->color_plane
[1].y
;
3048 u32 aux_offset
= plane_state
->color_plane
[1].offset
;
3049 u32 alignment
= intel_surf_alignment(fb
, 1);
3051 while (aux_offset
>= main_offset
&& aux_y
<= main_y
) {
3054 if (aux_x
== main_x
&& aux_y
== main_y
)
3057 if (aux_offset
== 0)
3062 aux_offset
= intel_plane_adjust_aligned_offset(&x
, &y
, plane_state
, 1,
3063 aux_offset
, aux_offset
- alignment
);
3064 aux_x
= x
* hsub
+ aux_x
% hsub
;
3065 aux_y
= y
* vsub
+ aux_y
% vsub
;
3068 if (aux_x
!= main_x
|| aux_y
!= main_y
)
3071 plane_state
->color_plane
[1].offset
= aux_offset
;
3072 plane_state
->color_plane
[1].x
= aux_x
;
3073 plane_state
->color_plane
[1].y
= aux_y
;
3078 static int skl_check_main_surface(struct intel_plane_state
*plane_state
)
3080 struct drm_i915_private
*dev_priv
= to_i915(plane_state
->base
.plane
->dev
);
3081 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
3082 unsigned int rotation
= plane_state
->base
.rotation
;
3083 int x
= plane_state
->base
.src
.x1
>> 16;
3084 int y
= plane_state
->base
.src
.y1
>> 16;
3085 int w
= drm_rect_width(&plane_state
->base
.src
) >> 16;
3086 int h
= drm_rect_height(&plane_state
->base
.src
) >> 16;
3088 int max_height
= 4096;
3089 u32 alignment
, offset
, aux_offset
= plane_state
->color_plane
[1].offset
;
3091 if (INTEL_GEN(dev_priv
) >= 11)
3092 max_width
= icl_max_plane_width(fb
, 0, rotation
);
3093 else if (INTEL_GEN(dev_priv
) >= 10 || IS_GEMINILAKE(dev_priv
))
3094 max_width
= glk_max_plane_width(fb
, 0, rotation
);
3096 max_width
= skl_max_plane_width(fb
, 0, rotation
);
3098 if (w
> max_width
|| h
> max_height
) {
3099 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
3100 w
, h
, max_width
, max_height
);
3104 intel_add_fb_offsets(&x
, &y
, plane_state
, 0);
3105 offset
= intel_plane_compute_aligned_offset(&x
, &y
, plane_state
, 0);
3106 alignment
= intel_surf_alignment(fb
, 0);
3109 * AUX surface offset is specified as the distance from the
3110 * main surface offset, and it must be non-negative. Make
3111 * sure that is what we will get.
3113 if (offset
> aux_offset
)
3114 offset
= intel_plane_adjust_aligned_offset(&x
, &y
, plane_state
, 0,
3115 offset
, aux_offset
& ~(alignment
- 1));
3118 * When using an X-tiled surface, the plane blows up
3119 * if the x offset + width exceed the stride.
3121 * TODO: linear and Y-tiled seem fine, Yf untested,
3123 if (fb
->modifier
== I915_FORMAT_MOD_X_TILED
) {
3124 int cpp
= fb
->format
->cpp
[0];
3126 while ((x
+ w
) * cpp
> plane_state
->color_plane
[0].stride
) {
3128 DRM_DEBUG_KMS("Unable to find suitable display surface offset due to X-tiling\n");
3132 offset
= intel_plane_adjust_aligned_offset(&x
, &y
, plane_state
, 0,
3133 offset
, offset
- alignment
);
3138 * CCS AUX surface doesn't have its own x/y offsets, we must make sure
3139 * they match with the main surface x/y offsets.
3141 if (is_ccs_modifier(fb
->modifier
)) {
3142 while (!skl_check_main_ccs_coordinates(plane_state
, x
, y
, offset
)) {
3146 offset
= intel_plane_adjust_aligned_offset(&x
, &y
, plane_state
, 0,
3147 offset
, offset
- alignment
);
3150 if (x
!= plane_state
->color_plane
[1].x
|| y
!= plane_state
->color_plane
[1].y
) {
3151 DRM_DEBUG_KMS("Unable to find suitable display surface offset due to CCS\n");
3156 plane_state
->color_plane
[0].offset
= offset
;
3157 plane_state
->color_plane
[0].x
= x
;
3158 plane_state
->color_plane
[0].y
= y
;
3163 static int skl_check_nv12_aux_surface(struct intel_plane_state
*plane_state
)
3165 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
3166 unsigned int rotation
= plane_state
->base
.rotation
;
3167 int max_width
= skl_max_plane_width(fb
, 1, rotation
);
3168 int max_height
= 4096;
3169 int x
= plane_state
->base
.src
.x1
>> 17;
3170 int y
= plane_state
->base
.src
.y1
>> 17;
3171 int w
= drm_rect_width(&plane_state
->base
.src
) >> 17;
3172 int h
= drm_rect_height(&plane_state
->base
.src
) >> 17;
3175 intel_add_fb_offsets(&x
, &y
, plane_state
, 1);
3176 offset
= intel_plane_compute_aligned_offset(&x
, &y
, plane_state
, 1);
3178 /* FIXME not quite sure how/if these apply to the chroma plane */
3179 if (w
> max_width
|| h
> max_height
) {
3180 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
3181 w
, h
, max_width
, max_height
);
3185 plane_state
->color_plane
[1].offset
= offset
;
3186 plane_state
->color_plane
[1].x
= x
;
3187 plane_state
->color_plane
[1].y
= y
;
3192 static int skl_check_ccs_aux_surface(struct intel_plane_state
*plane_state
)
3194 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
3195 int src_x
= plane_state
->base
.src
.x1
>> 16;
3196 int src_y
= plane_state
->base
.src
.y1
>> 16;
3197 int hsub
= fb
->format
->hsub
;
3198 int vsub
= fb
->format
->vsub
;
3199 int x
= src_x
/ hsub
;
3200 int y
= src_y
/ vsub
;
3203 intel_add_fb_offsets(&x
, &y
, plane_state
, 1);
3204 offset
= intel_plane_compute_aligned_offset(&x
, &y
, plane_state
, 1);
3206 plane_state
->color_plane
[1].offset
= offset
;
3207 plane_state
->color_plane
[1].x
= x
* hsub
+ src_x
% hsub
;
3208 plane_state
->color_plane
[1].y
= y
* vsub
+ src_y
% vsub
;
3213 int skl_check_plane_surface(struct intel_plane_state
*plane_state
)
3215 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
3216 unsigned int rotation
= plane_state
->base
.rotation
;
3219 intel_fill_fb_ggtt_view(&plane_state
->view
, fb
, rotation
);
3220 plane_state
->color_plane
[0].stride
= intel_fb_pitch(fb
, 0, rotation
);
3221 plane_state
->color_plane
[1].stride
= intel_fb_pitch(fb
, 1, rotation
);
3223 ret
= intel_plane_check_stride(plane_state
);
3227 if (!plane_state
->base
.visible
)
3230 /* Rotate src coordinates to match rotated GTT view */
3231 if (drm_rotation_90_or_270(rotation
))
3232 drm_rect_rotate(&plane_state
->base
.src
,
3233 fb
->width
<< 16, fb
->height
<< 16,
3234 DRM_MODE_ROTATE_270
);
3237 * Handle the AUX surface first since
3238 * the main surface setup depends on it.
3240 if (is_planar_yuv_format(fb
->format
->format
)) {
3241 ret
= skl_check_nv12_aux_surface(plane_state
);
3244 } else if (is_ccs_modifier(fb
->modifier
)) {
3245 ret
= skl_check_ccs_aux_surface(plane_state
);
3249 plane_state
->color_plane
[1].offset
= ~0xfff;
3250 plane_state
->color_plane
[1].x
= 0;
3251 plane_state
->color_plane
[1].y
= 0;
3254 ret
= skl_check_main_surface(plane_state
);
3262 i9xx_plane_max_stride(struct intel_plane
*plane
,
3263 u32 pixel_format
, u64 modifier
,
3264 unsigned int rotation
)
3266 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
3268 if (!HAS_GMCH(dev_priv
)) {
3270 } else if (INTEL_GEN(dev_priv
) >= 4) {
3271 if (modifier
== I915_FORMAT_MOD_X_TILED
)
3275 } else if (INTEL_GEN(dev_priv
) >= 3) {
3276 if (modifier
== I915_FORMAT_MOD_X_TILED
)
3281 if (plane
->i9xx_plane
== PLANE_C
)
3288 static u32
i9xx_plane_ctl_crtc(const struct intel_crtc_state
*crtc_state
)
3290 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
3291 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
3294 if (crtc_state
->gamma_enable
)
3295 dspcntr
|= DISPPLANE_GAMMA_ENABLE
;
3297 if (crtc_state
->csc_enable
)
3298 dspcntr
|= DISPPLANE_PIPE_CSC_ENABLE
;
3300 if (INTEL_GEN(dev_priv
) < 5)
3301 dspcntr
|= DISPPLANE_SEL_PIPE(crtc
->pipe
);
3306 static u32
i9xx_plane_ctl(const struct intel_crtc_state
*crtc_state
,
3307 const struct intel_plane_state
*plane_state
)
3309 struct drm_i915_private
*dev_priv
=
3310 to_i915(plane_state
->base
.plane
->dev
);
3311 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
3312 unsigned int rotation
= plane_state
->base
.rotation
;
3315 dspcntr
= DISPLAY_PLANE_ENABLE
;
3317 if (IS_G4X(dev_priv
) || IS_GEN(dev_priv
, 5) ||
3318 IS_GEN(dev_priv
, 6) || IS_IVYBRIDGE(dev_priv
))
3319 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
3321 switch (fb
->format
->format
) {
3323 dspcntr
|= DISPPLANE_8BPP
;
3325 case DRM_FORMAT_XRGB1555
:
3326 dspcntr
|= DISPPLANE_BGRX555
;
3328 case DRM_FORMAT_RGB565
:
3329 dspcntr
|= DISPPLANE_BGRX565
;
3331 case DRM_FORMAT_XRGB8888
:
3332 dspcntr
|= DISPPLANE_BGRX888
;
3334 case DRM_FORMAT_XBGR8888
:
3335 dspcntr
|= DISPPLANE_RGBX888
;
3337 case DRM_FORMAT_XRGB2101010
:
3338 dspcntr
|= DISPPLANE_BGRX101010
;
3340 case DRM_FORMAT_XBGR2101010
:
3341 dspcntr
|= DISPPLANE_RGBX101010
;
3344 MISSING_CASE(fb
->format
->format
);
3348 if (INTEL_GEN(dev_priv
) >= 4 &&
3349 fb
->modifier
== I915_FORMAT_MOD_X_TILED
)
3350 dspcntr
|= DISPPLANE_TILED
;
3352 if (rotation
& DRM_MODE_ROTATE_180
)
3353 dspcntr
|= DISPPLANE_ROTATE_180
;
3355 if (rotation
& DRM_MODE_REFLECT_X
)
3356 dspcntr
|= DISPPLANE_MIRROR
;
3361 int i9xx_check_plane_surface(struct intel_plane_state
*plane_state
)
3363 struct drm_i915_private
*dev_priv
=
3364 to_i915(plane_state
->base
.plane
->dev
);
3365 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
3366 unsigned int rotation
= plane_state
->base
.rotation
;
3367 int src_x
= plane_state
->base
.src
.x1
>> 16;
3368 int src_y
= plane_state
->base
.src
.y1
>> 16;
3372 intel_fill_fb_ggtt_view(&plane_state
->view
, fb
, rotation
);
3373 plane_state
->color_plane
[0].stride
= intel_fb_pitch(fb
, 0, rotation
);
3375 ret
= intel_plane_check_stride(plane_state
);
3379 intel_add_fb_offsets(&src_x
, &src_y
, plane_state
, 0);
3381 if (INTEL_GEN(dev_priv
) >= 4)
3382 offset
= intel_plane_compute_aligned_offset(&src_x
, &src_y
,
3387 /* HSW/BDW do this automagically in hardware */
3388 if (!IS_HASWELL(dev_priv
) && !IS_BROADWELL(dev_priv
)) {
3389 int src_w
= drm_rect_width(&plane_state
->base
.src
) >> 16;
3390 int src_h
= drm_rect_height(&plane_state
->base
.src
) >> 16;
3392 if (rotation
& DRM_MODE_ROTATE_180
) {
3395 } else if (rotation
& DRM_MODE_REFLECT_X
) {
3400 plane_state
->color_plane
[0].offset
= offset
;
3401 plane_state
->color_plane
[0].x
= src_x
;
3402 plane_state
->color_plane
[0].y
= src_y
;
3408 i9xx_plane_check(struct intel_crtc_state
*crtc_state
,
3409 struct intel_plane_state
*plane_state
)
3413 ret
= chv_plane_check_rotation(plane_state
);
3417 ret
= drm_atomic_helper_check_plane_state(&plane_state
->base
,
3419 DRM_PLANE_HELPER_NO_SCALING
,
3420 DRM_PLANE_HELPER_NO_SCALING
,
3425 if (!plane_state
->base
.visible
)
3428 ret
= intel_plane_check_src_coordinates(plane_state
);
3432 ret
= i9xx_check_plane_surface(plane_state
);
3436 plane_state
->ctl
= i9xx_plane_ctl(crtc_state
, plane_state
);
3441 static void i9xx_update_plane(struct intel_plane
*plane
,
3442 const struct intel_crtc_state
*crtc_state
,
3443 const struct intel_plane_state
*plane_state
)
3445 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
3446 enum i9xx_plane_id i9xx_plane
= plane
->i9xx_plane
;
3448 int x
= plane_state
->color_plane
[0].x
;
3449 int y
= plane_state
->color_plane
[0].y
;
3450 unsigned long irqflags
;
3454 dspcntr
= plane_state
->ctl
| i9xx_plane_ctl_crtc(crtc_state
);
3456 linear_offset
= intel_fb_xy_to_linear(x
, y
, plane_state
, 0);
3458 if (INTEL_GEN(dev_priv
) >= 4)
3459 dspaddr_offset
= plane_state
->color_plane
[0].offset
;
3461 dspaddr_offset
= linear_offset
;
3463 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
3465 I915_WRITE_FW(DSPSTRIDE(i9xx_plane
), plane_state
->color_plane
[0].stride
);
3467 if (INTEL_GEN(dev_priv
) < 4) {
3468 /* pipesrc and dspsize control the size that is scaled from,
3469 * which should always be the user's requested size.
3471 I915_WRITE_FW(DSPPOS(i9xx_plane
), 0);
3472 I915_WRITE_FW(DSPSIZE(i9xx_plane
),
3473 ((crtc_state
->pipe_src_h
- 1) << 16) |
3474 (crtc_state
->pipe_src_w
- 1));
3475 } else if (IS_CHERRYVIEW(dev_priv
) && i9xx_plane
== PLANE_B
) {
3476 I915_WRITE_FW(PRIMPOS(i9xx_plane
), 0);
3477 I915_WRITE_FW(PRIMSIZE(i9xx_plane
),
3478 ((crtc_state
->pipe_src_h
- 1) << 16) |
3479 (crtc_state
->pipe_src_w
- 1));
3480 I915_WRITE_FW(PRIMCNSTALPHA(i9xx_plane
), 0);
3483 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
3484 I915_WRITE_FW(DSPOFFSET(i9xx_plane
), (y
<< 16) | x
);
3485 } else if (INTEL_GEN(dev_priv
) >= 4) {
3486 I915_WRITE_FW(DSPLINOFF(i9xx_plane
), linear_offset
);
3487 I915_WRITE_FW(DSPTILEOFF(i9xx_plane
), (y
<< 16) | x
);
3491 * The control register self-arms if the plane was previously
3492 * disabled. Try to make the plane enable atomic by writing
3493 * the control register just before the surface register.
3495 I915_WRITE_FW(DSPCNTR(i9xx_plane
), dspcntr
);
3496 if (INTEL_GEN(dev_priv
) >= 4)
3497 I915_WRITE_FW(DSPSURF(i9xx_plane
),
3498 intel_plane_ggtt_offset(plane_state
) +
3501 I915_WRITE_FW(DSPADDR(i9xx_plane
),
3502 intel_plane_ggtt_offset(plane_state
) +
3505 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
3508 static void i9xx_disable_plane(struct intel_plane
*plane
,
3509 const struct intel_crtc_state
*crtc_state
)
3511 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
3512 enum i9xx_plane_id i9xx_plane
= plane
->i9xx_plane
;
3513 unsigned long irqflags
;
3517 * DSPCNTR pipe gamma enable on g4x+ and pipe csc
3518 * enable on ilk+ affect the pipe bottom color as
3519 * well, so we must configure them even if the plane
3522 * On pre-g4x there is no way to gamma correct the
3523 * pipe bottom color but we'll keep on doing this
3524 * anyway so that the crtc state readout works correctly.
3526 dspcntr
= i9xx_plane_ctl_crtc(crtc_state
);
3528 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
3530 I915_WRITE_FW(DSPCNTR(i9xx_plane
), dspcntr
);
3531 if (INTEL_GEN(dev_priv
) >= 4)
3532 I915_WRITE_FW(DSPSURF(i9xx_plane
), 0);
3534 I915_WRITE_FW(DSPADDR(i9xx_plane
), 0);
3536 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
3539 static bool i9xx_plane_get_hw_state(struct intel_plane
*plane
,
3542 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
3543 enum intel_display_power_domain power_domain
;
3544 enum i9xx_plane_id i9xx_plane
= plane
->i9xx_plane
;
3545 intel_wakeref_t wakeref
;
3550 * Not 100% correct for planes that can move between pipes,
3551 * but that's only the case for gen2-4 which don't have any
3552 * display power wells.
3554 power_domain
= POWER_DOMAIN_PIPE(plane
->pipe
);
3555 wakeref
= intel_display_power_get_if_enabled(dev_priv
, power_domain
);
3559 val
= I915_READ(DSPCNTR(i9xx_plane
));
3561 ret
= val
& DISPLAY_PLANE_ENABLE
;
3563 if (INTEL_GEN(dev_priv
) >= 5)
3564 *pipe
= plane
->pipe
;
3566 *pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
3567 DISPPLANE_SEL_PIPE_SHIFT
;
3569 intel_display_power_put(dev_priv
, power_domain
, wakeref
);
3575 intel_fb_stride_alignment(const struct drm_framebuffer
*fb
, int color_plane
)
3577 if (fb
->modifier
== DRM_FORMAT_MOD_LINEAR
)
3580 return intel_tile_width_bytes(fb
, color_plane
);
3583 static void skl_detach_scaler(struct intel_crtc
*intel_crtc
, int id
)
3585 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3586 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3588 I915_WRITE(SKL_PS_CTRL(intel_crtc
->pipe
, id
), 0);
3589 I915_WRITE(SKL_PS_WIN_POS(intel_crtc
->pipe
, id
), 0);
3590 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc
->pipe
, id
), 0);
3594 * This function detaches (aka. unbinds) unused scalers in hardware
3596 static void skl_detach_scalers(const struct intel_crtc_state
*crtc_state
)
3598 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
3599 const struct intel_crtc_scaler_state
*scaler_state
=
3600 &crtc_state
->scaler_state
;
3603 /* loop through and disable scalers that aren't in use */
3604 for (i
= 0; i
< intel_crtc
->num_scalers
; i
++) {
3605 if (!scaler_state
->scalers
[i
].in_use
)
3606 skl_detach_scaler(intel_crtc
, i
);
3610 static unsigned int skl_plane_stride_mult(const struct drm_framebuffer
*fb
,
3611 int color_plane
, unsigned int rotation
)
3614 * The stride is either expressed as a multiple of 64 bytes chunks for
3615 * linear buffers or in number of tiles for tiled buffers.
3617 if (fb
->modifier
== DRM_FORMAT_MOD_LINEAR
)
3619 else if (drm_rotation_90_or_270(rotation
))
3620 return intel_tile_height(fb
, color_plane
);
3622 return intel_tile_width_bytes(fb
, color_plane
);
3625 u32
skl_plane_stride(const struct intel_plane_state
*plane_state
,
3628 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
3629 unsigned int rotation
= plane_state
->base
.rotation
;
3630 u32 stride
= plane_state
->color_plane
[color_plane
].stride
;
3632 if (color_plane
>= fb
->format
->num_planes
)
3635 return stride
/ skl_plane_stride_mult(fb
, color_plane
, rotation
);
3638 static u32
skl_plane_ctl_format(u32 pixel_format
)
3640 switch (pixel_format
) {
3642 return PLANE_CTL_FORMAT_INDEXED
;
3643 case DRM_FORMAT_RGB565
:
3644 return PLANE_CTL_FORMAT_RGB_565
;
3645 case DRM_FORMAT_XBGR8888
:
3646 case DRM_FORMAT_ABGR8888
:
3647 return PLANE_CTL_FORMAT_XRGB_8888
| PLANE_CTL_ORDER_RGBX
;
3648 case DRM_FORMAT_XRGB8888
:
3649 case DRM_FORMAT_ARGB8888
:
3650 return PLANE_CTL_FORMAT_XRGB_8888
;
3651 case DRM_FORMAT_XRGB2101010
:
3652 return PLANE_CTL_FORMAT_XRGB_2101010
;
3653 case DRM_FORMAT_XBGR2101010
:
3654 return PLANE_CTL_ORDER_RGBX
| PLANE_CTL_FORMAT_XRGB_2101010
;
3655 case DRM_FORMAT_XBGR16161616F
:
3656 case DRM_FORMAT_ABGR16161616F
:
3657 return PLANE_CTL_FORMAT_XRGB_16161616F
| PLANE_CTL_ORDER_RGBX
;
3658 case DRM_FORMAT_XRGB16161616F
:
3659 case DRM_FORMAT_ARGB16161616F
:
3660 return PLANE_CTL_FORMAT_XRGB_16161616F
;
3661 case DRM_FORMAT_YUYV
:
3662 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_YUYV
;
3663 case DRM_FORMAT_YVYU
:
3664 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_YVYU
;
3665 case DRM_FORMAT_UYVY
:
3666 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_UYVY
;
3667 case DRM_FORMAT_VYUY
:
3668 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_VYUY
;
3669 case DRM_FORMAT_NV12
:
3670 return PLANE_CTL_FORMAT_NV12
;
3671 case DRM_FORMAT_P010
:
3672 return PLANE_CTL_FORMAT_P010
;
3673 case DRM_FORMAT_P012
:
3674 return PLANE_CTL_FORMAT_P012
;
3675 case DRM_FORMAT_P016
:
3676 return PLANE_CTL_FORMAT_P016
;
3677 case DRM_FORMAT_Y210
:
3678 return PLANE_CTL_FORMAT_Y210
;
3679 case DRM_FORMAT_Y212
:
3680 return PLANE_CTL_FORMAT_Y212
;
3681 case DRM_FORMAT_Y216
:
3682 return PLANE_CTL_FORMAT_Y216
;
3683 case DRM_FORMAT_XVYU2101010
:
3684 return PLANE_CTL_FORMAT_Y410
;
3685 case DRM_FORMAT_XVYU12_16161616
:
3686 return PLANE_CTL_FORMAT_Y412
;
3687 case DRM_FORMAT_XVYU16161616
:
3688 return PLANE_CTL_FORMAT_Y416
;
3690 MISSING_CASE(pixel_format
);
3696 static u32
skl_plane_ctl_alpha(const struct intel_plane_state
*plane_state
)
3698 if (!plane_state
->base
.fb
->format
->has_alpha
)
3699 return PLANE_CTL_ALPHA_DISABLE
;
3701 switch (plane_state
->base
.pixel_blend_mode
) {
3702 case DRM_MODE_BLEND_PIXEL_NONE
:
3703 return PLANE_CTL_ALPHA_DISABLE
;
3704 case DRM_MODE_BLEND_PREMULTI
:
3705 return PLANE_CTL_ALPHA_SW_PREMULTIPLY
;
3706 case DRM_MODE_BLEND_COVERAGE
:
3707 return PLANE_CTL_ALPHA_HW_PREMULTIPLY
;
3709 MISSING_CASE(plane_state
->base
.pixel_blend_mode
);
3710 return PLANE_CTL_ALPHA_DISABLE
;
3714 static u32
glk_plane_color_ctl_alpha(const struct intel_plane_state
*plane_state
)
3716 if (!plane_state
->base
.fb
->format
->has_alpha
)
3717 return PLANE_COLOR_ALPHA_DISABLE
;
3719 switch (plane_state
->base
.pixel_blend_mode
) {
3720 case DRM_MODE_BLEND_PIXEL_NONE
:
3721 return PLANE_COLOR_ALPHA_DISABLE
;
3722 case DRM_MODE_BLEND_PREMULTI
:
3723 return PLANE_COLOR_ALPHA_SW_PREMULTIPLY
;
3724 case DRM_MODE_BLEND_COVERAGE
:
3725 return PLANE_COLOR_ALPHA_HW_PREMULTIPLY
;
3727 MISSING_CASE(plane_state
->base
.pixel_blend_mode
);
3728 return PLANE_COLOR_ALPHA_DISABLE
;
3732 static u32
skl_plane_ctl_tiling(u64 fb_modifier
)
3734 switch (fb_modifier
) {
3735 case DRM_FORMAT_MOD_LINEAR
:
3737 case I915_FORMAT_MOD_X_TILED
:
3738 return PLANE_CTL_TILED_X
;
3739 case I915_FORMAT_MOD_Y_TILED
:
3740 return PLANE_CTL_TILED_Y
;
3741 case I915_FORMAT_MOD_Y_TILED_CCS
:
3742 return PLANE_CTL_TILED_Y
| PLANE_CTL_RENDER_DECOMPRESSION_ENABLE
;
3743 case I915_FORMAT_MOD_Yf_TILED
:
3744 return PLANE_CTL_TILED_YF
;
3745 case I915_FORMAT_MOD_Yf_TILED_CCS
:
3746 return PLANE_CTL_TILED_YF
| PLANE_CTL_RENDER_DECOMPRESSION_ENABLE
;
3748 MISSING_CASE(fb_modifier
);
3754 static u32
skl_plane_ctl_rotate(unsigned int rotate
)
3757 case DRM_MODE_ROTATE_0
:
3760 * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
3761 * while i915 HW rotation is clockwise, thats why this swapping.
3763 case DRM_MODE_ROTATE_90
:
3764 return PLANE_CTL_ROTATE_270
;
3765 case DRM_MODE_ROTATE_180
:
3766 return PLANE_CTL_ROTATE_180
;
3767 case DRM_MODE_ROTATE_270
:
3768 return PLANE_CTL_ROTATE_90
;
3770 MISSING_CASE(rotate
);
3776 static u32
cnl_plane_ctl_flip(unsigned int reflect
)
3781 case DRM_MODE_REFLECT_X
:
3782 return PLANE_CTL_FLIP_HORIZONTAL
;
3783 case DRM_MODE_REFLECT_Y
:
3785 MISSING_CASE(reflect
);
3791 u32
skl_plane_ctl_crtc(const struct intel_crtc_state
*crtc_state
)
3793 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->base
.crtc
->dev
);
3796 if (INTEL_GEN(dev_priv
) >= 10 || IS_GEMINILAKE(dev_priv
))
3799 if (crtc_state
->gamma_enable
)
3800 plane_ctl
|= PLANE_CTL_PIPE_GAMMA_ENABLE
;
3802 if (crtc_state
->csc_enable
)
3803 plane_ctl
|= PLANE_CTL_PIPE_CSC_ENABLE
;
3808 u32
skl_plane_ctl(const struct intel_crtc_state
*crtc_state
,
3809 const struct intel_plane_state
*plane_state
)
3811 struct drm_i915_private
*dev_priv
=
3812 to_i915(plane_state
->base
.plane
->dev
);
3813 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
3814 unsigned int rotation
= plane_state
->base
.rotation
;
3815 const struct drm_intel_sprite_colorkey
*key
= &plane_state
->ckey
;
3818 plane_ctl
= PLANE_CTL_ENABLE
;
3820 if (INTEL_GEN(dev_priv
) < 10 && !IS_GEMINILAKE(dev_priv
)) {
3821 plane_ctl
|= skl_plane_ctl_alpha(plane_state
);
3822 plane_ctl
|= PLANE_CTL_PLANE_GAMMA_DISABLE
;
3824 if (plane_state
->base
.color_encoding
== DRM_COLOR_YCBCR_BT709
)
3825 plane_ctl
|= PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709
;
3827 if (plane_state
->base
.color_range
== DRM_COLOR_YCBCR_FULL_RANGE
)
3828 plane_ctl
|= PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE
;
3831 plane_ctl
|= skl_plane_ctl_format(fb
->format
->format
);
3832 plane_ctl
|= skl_plane_ctl_tiling(fb
->modifier
);
3833 plane_ctl
|= skl_plane_ctl_rotate(rotation
& DRM_MODE_ROTATE_MASK
);
3835 if (INTEL_GEN(dev_priv
) >= 10)
3836 plane_ctl
|= cnl_plane_ctl_flip(rotation
&
3837 DRM_MODE_REFLECT_MASK
);
3839 if (key
->flags
& I915_SET_COLORKEY_DESTINATION
)
3840 plane_ctl
|= PLANE_CTL_KEY_ENABLE_DESTINATION
;
3841 else if (key
->flags
& I915_SET_COLORKEY_SOURCE
)
3842 plane_ctl
|= PLANE_CTL_KEY_ENABLE_SOURCE
;
3847 u32
glk_plane_color_ctl_crtc(const struct intel_crtc_state
*crtc_state
)
3849 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->base
.crtc
->dev
);
3850 u32 plane_color_ctl
= 0;
3852 if (INTEL_GEN(dev_priv
) >= 11)
3853 return plane_color_ctl
;
3855 if (crtc_state
->gamma_enable
)
3856 plane_color_ctl
|= PLANE_COLOR_PIPE_GAMMA_ENABLE
;
3858 if (crtc_state
->csc_enable
)
3859 plane_color_ctl
|= PLANE_COLOR_PIPE_CSC_ENABLE
;
3861 return plane_color_ctl
;
3864 u32
glk_plane_color_ctl(const struct intel_crtc_state
*crtc_state
,
3865 const struct intel_plane_state
*plane_state
)
3867 struct drm_i915_private
*dev_priv
=
3868 to_i915(plane_state
->base
.plane
->dev
);
3869 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
3870 struct intel_plane
*plane
= to_intel_plane(plane_state
->base
.plane
);
3871 u32 plane_color_ctl
= 0;
3873 plane_color_ctl
|= PLANE_COLOR_PLANE_GAMMA_DISABLE
;
3874 plane_color_ctl
|= glk_plane_color_ctl_alpha(plane_state
);
3876 if (fb
->format
->is_yuv
&& !icl_is_hdr_plane(dev_priv
, plane
->id
)) {
3877 if (plane_state
->base
.color_encoding
== DRM_COLOR_YCBCR_BT709
)
3878 plane_color_ctl
|= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709
;
3880 plane_color_ctl
|= PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709
;
3882 if (plane_state
->base
.color_range
== DRM_COLOR_YCBCR_FULL_RANGE
)
3883 plane_color_ctl
|= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE
;
3884 } else if (fb
->format
->is_yuv
) {
3885 plane_color_ctl
|= PLANE_COLOR_INPUT_CSC_ENABLE
;
3888 return plane_color_ctl
;
3892 __intel_display_resume(struct drm_device
*dev
,
3893 struct drm_atomic_state
*state
,
3894 struct drm_modeset_acquire_ctx
*ctx
)
3896 struct drm_crtc_state
*crtc_state
;
3897 struct drm_crtc
*crtc
;
3900 intel_modeset_setup_hw_state(dev
, ctx
);
3901 i915_redisable_vga(to_i915(dev
));
3907 * We've duplicated the state, pointers to the old state are invalid.
3909 * Don't attempt to use the old state until we commit the duplicated state.
3911 for_each_new_crtc_in_state(state
, crtc
, crtc_state
, i
) {
3913 * Force recalculation even if we restore
3914 * current state. With fast modeset this may not result
3915 * in a modeset when the state is compatible.
3917 crtc_state
->mode_changed
= true;
3920 /* ignore any reset values/BIOS leftovers in the WM registers */
3921 if (!HAS_GMCH(to_i915(dev
)))
3922 to_intel_atomic_state(state
)->skip_intermediate_wm
= true;
3924 ret
= drm_atomic_helper_commit_duplicated_state(state
, ctx
);
3926 WARN_ON(ret
== -EDEADLK
);
3930 static bool gpu_reset_clobbers_display(struct drm_i915_private
*dev_priv
)
3932 return (INTEL_INFO(dev_priv
)->gpu_reset_clobbers_display
&&
3933 intel_has_gpu_reset(dev_priv
));
3936 void intel_prepare_reset(struct drm_i915_private
*dev_priv
)
3938 struct drm_device
*dev
= &dev_priv
->drm
;
3939 struct drm_modeset_acquire_ctx
*ctx
= &dev_priv
->reset_ctx
;
3940 struct drm_atomic_state
*state
;
3943 /* reset doesn't touch the display */
3944 if (!i915_modparams
.force_reset_modeset_test
&&
3945 !gpu_reset_clobbers_display(dev_priv
))
3948 /* We have a modeset vs reset deadlock, defensively unbreak it. */
3949 set_bit(I915_RESET_MODESET
, &dev_priv
->gpu_error
.flags
);
3950 wake_up_all(&dev_priv
->gpu_error
.wait_queue
);
3952 if (atomic_read(&dev_priv
->gpu_error
.pending_fb_pin
)) {
3953 DRM_DEBUG_KMS("Modeset potentially stuck, unbreaking through wedging\n");
3954 i915_gem_set_wedged(dev_priv
);
3958 * Need mode_config.mutex so that we don't
3959 * trample ongoing ->detect() and whatnot.
3961 mutex_lock(&dev
->mode_config
.mutex
);
3962 drm_modeset_acquire_init(ctx
, 0);
3964 ret
= drm_modeset_lock_all_ctx(dev
, ctx
);
3965 if (ret
!= -EDEADLK
)
3968 drm_modeset_backoff(ctx
);
3971 * Disabling the crtcs gracefully seems nicer. Also the
3972 * g33 docs say we should at least disable all the planes.
3974 state
= drm_atomic_helper_duplicate_state(dev
, ctx
);
3975 if (IS_ERR(state
)) {
3976 ret
= PTR_ERR(state
);
3977 DRM_ERROR("Duplicating state failed with %i\n", ret
);
3981 ret
= drm_atomic_helper_disable_all(dev
, ctx
);
3983 DRM_ERROR("Suspending crtc's failed with %i\n", ret
);
3984 drm_atomic_state_put(state
);
3988 dev_priv
->modeset_restore_state
= state
;
3989 state
->acquire_ctx
= ctx
;
3992 void intel_finish_reset(struct drm_i915_private
*dev_priv
)
3994 struct drm_device
*dev
= &dev_priv
->drm
;
3995 struct drm_modeset_acquire_ctx
*ctx
= &dev_priv
->reset_ctx
;
3996 struct drm_atomic_state
*state
;
3999 /* reset doesn't touch the display */
4000 if (!test_bit(I915_RESET_MODESET
, &dev_priv
->gpu_error
.flags
))
4003 state
= fetch_and_zero(&dev_priv
->modeset_restore_state
);
4007 /* reset doesn't touch the display */
4008 if (!gpu_reset_clobbers_display(dev_priv
)) {
4009 /* for testing only restore the display */
4010 ret
= __intel_display_resume(dev
, state
, ctx
);
4012 DRM_ERROR("Restoring old state failed with %i\n", ret
);
4015 * The display has been reset as well,
4016 * so need a full re-initialization.
4018 intel_pps_unlock_regs_wa(dev_priv
);
4019 intel_modeset_init_hw(dev
);
4020 intel_init_clock_gating(dev_priv
);
4022 spin_lock_irq(&dev_priv
->irq_lock
);
4023 if (dev_priv
->display
.hpd_irq_setup
)
4024 dev_priv
->display
.hpd_irq_setup(dev_priv
);
4025 spin_unlock_irq(&dev_priv
->irq_lock
);
4027 ret
= __intel_display_resume(dev
, state
, ctx
);
4029 DRM_ERROR("Restoring old state failed with %i\n", ret
);
4031 intel_hpd_init(dev_priv
);
4034 drm_atomic_state_put(state
);
4036 drm_modeset_drop_locks(ctx
);
4037 drm_modeset_acquire_fini(ctx
);
4038 mutex_unlock(&dev
->mode_config
.mutex
);
4040 clear_bit(I915_RESET_MODESET
, &dev_priv
->gpu_error
.flags
);
4043 static void icl_set_pipe_chicken(struct intel_crtc
*crtc
)
4045 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
4046 enum pipe pipe
= crtc
->pipe
;
4049 tmp
= I915_READ(PIPE_CHICKEN(pipe
));
4052 * Display WA #1153: icl
4053 * enable hardware to bypass the alpha math
4054 * and rounding for per-pixel values 00 and 0xff
4056 tmp
|= PER_PIXEL_ALPHA_BYPASS_EN
;
4058 * Display WA # 1605353570: icl
4059 * Set the pixel rounding bit to 1 for allowing
4060 * passthrough of Frame buffer pixels unmodified
4063 tmp
|= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU
;
4064 I915_WRITE(PIPE_CHICKEN(pipe
), tmp
);
4067 static void intel_update_pipe_config(const struct intel_crtc_state
*old_crtc_state
,
4068 const struct intel_crtc_state
*new_crtc_state
)
4070 struct intel_crtc
*crtc
= to_intel_crtc(new_crtc_state
->base
.crtc
);
4071 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
4073 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
4074 crtc
->base
.mode
= new_crtc_state
->base
.mode
;
4077 * Update pipe size and adjust fitter if needed: the reason for this is
4078 * that in compute_mode_changes we check the native mode (not the pfit
4079 * mode) to see if we can flip rather than do a full mode set. In the
4080 * fastboot case, we'll flip, but if we don't update the pipesrc and
4081 * pfit state, we'll end up with a big fb scanned out into the wrong
4085 I915_WRITE(PIPESRC(crtc
->pipe
),
4086 ((new_crtc_state
->pipe_src_w
- 1) << 16) |
4087 (new_crtc_state
->pipe_src_h
- 1));
4089 /* on skylake this is done by detaching scalers */
4090 if (INTEL_GEN(dev_priv
) >= 9) {
4091 skl_detach_scalers(new_crtc_state
);
4093 if (new_crtc_state
->pch_pfit
.enabled
)
4094 skylake_pfit_enable(new_crtc_state
);
4095 } else if (HAS_PCH_SPLIT(dev_priv
)) {
4096 if (new_crtc_state
->pch_pfit
.enabled
)
4097 ironlake_pfit_enable(new_crtc_state
);
4098 else if (old_crtc_state
->pch_pfit
.enabled
)
4099 ironlake_pfit_disable(old_crtc_state
);
4102 if (INTEL_GEN(dev_priv
) >= 11)
4103 icl_set_pipe_chicken(crtc
);
4106 static void intel_fdi_normal_train(struct intel_crtc
*crtc
)
4108 struct drm_device
*dev
= crtc
->base
.dev
;
4109 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4110 int pipe
= crtc
->pipe
;
4114 /* enable normal train */
4115 reg
= FDI_TX_CTL(pipe
);
4116 temp
= I915_READ(reg
);
4117 if (IS_IVYBRIDGE(dev_priv
)) {
4118 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
4119 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
4121 temp
&= ~FDI_LINK_TRAIN_NONE
;
4122 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
4124 I915_WRITE(reg
, temp
);
4126 reg
= FDI_RX_CTL(pipe
);
4127 temp
= I915_READ(reg
);
4128 if (HAS_PCH_CPT(dev_priv
)) {
4129 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
4130 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
4132 temp
&= ~FDI_LINK_TRAIN_NONE
;
4133 temp
|= FDI_LINK_TRAIN_NONE
;
4135 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
4137 /* wait one idle pattern time */
4141 /* IVB wants error correction enabled */
4142 if (IS_IVYBRIDGE(dev_priv
))
4143 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
4144 FDI_FE_ERRC_ENABLE
);
4147 /* The FDI link training functions for ILK/Ibexpeak. */
4148 static void ironlake_fdi_link_train(struct intel_crtc
*crtc
,
4149 const struct intel_crtc_state
*crtc_state
)
4151 struct drm_device
*dev
= crtc
->base
.dev
;
4152 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4153 int pipe
= crtc
->pipe
;
4157 /* FDI needs bits from pipe first */
4158 assert_pipe_enabled(dev_priv
, pipe
);
4160 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4162 reg
= FDI_RX_IMR(pipe
);
4163 temp
= I915_READ(reg
);
4164 temp
&= ~FDI_RX_SYMBOL_LOCK
;
4165 temp
&= ~FDI_RX_BIT_LOCK
;
4166 I915_WRITE(reg
, temp
);
4170 /* enable CPU FDI TX and PCH FDI RX */
4171 reg
= FDI_TX_CTL(pipe
);
4172 temp
= I915_READ(reg
);
4173 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
4174 temp
|= FDI_DP_PORT_WIDTH(crtc_state
->fdi_lanes
);
4175 temp
&= ~FDI_LINK_TRAIN_NONE
;
4176 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
4177 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
4179 reg
= FDI_RX_CTL(pipe
);
4180 temp
= I915_READ(reg
);
4181 temp
&= ~FDI_LINK_TRAIN_NONE
;
4182 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
4183 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
4188 /* Ironlake workaround, enable clock pointer after FDI enable*/
4189 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
4190 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
4191 FDI_RX_PHASE_SYNC_POINTER_EN
);
4193 reg
= FDI_RX_IIR(pipe
);
4194 for (tries
= 0; tries
< 5; tries
++) {
4195 temp
= I915_READ(reg
);
4196 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
4198 if ((temp
& FDI_RX_BIT_LOCK
)) {
4199 DRM_DEBUG_KMS("FDI train 1 done.\n");
4200 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
4205 DRM_ERROR("FDI train 1 fail!\n");
4208 reg
= FDI_TX_CTL(pipe
);
4209 temp
= I915_READ(reg
);
4210 temp
&= ~FDI_LINK_TRAIN_NONE
;
4211 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
4212 I915_WRITE(reg
, temp
);
4214 reg
= FDI_RX_CTL(pipe
);
4215 temp
= I915_READ(reg
);
4216 temp
&= ~FDI_LINK_TRAIN_NONE
;
4217 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
4218 I915_WRITE(reg
, temp
);
4223 reg
= FDI_RX_IIR(pipe
);
4224 for (tries
= 0; tries
< 5; tries
++) {
4225 temp
= I915_READ(reg
);
4226 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
4228 if (temp
& FDI_RX_SYMBOL_LOCK
) {
4229 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
4230 DRM_DEBUG_KMS("FDI train 2 done.\n");
4235 DRM_ERROR("FDI train 2 fail!\n");
4237 DRM_DEBUG_KMS("FDI train done\n");
4241 static const int snb_b_fdi_train_param
[] = {
4242 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
4243 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
4244 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
4245 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
4248 /* The FDI link training functions for SNB/Cougarpoint. */
4249 static void gen6_fdi_link_train(struct intel_crtc
*crtc
,
4250 const struct intel_crtc_state
*crtc_state
)
4252 struct drm_device
*dev
= crtc
->base
.dev
;
4253 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4254 int pipe
= crtc
->pipe
;
4258 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4260 reg
= FDI_RX_IMR(pipe
);
4261 temp
= I915_READ(reg
);
4262 temp
&= ~FDI_RX_SYMBOL_LOCK
;
4263 temp
&= ~FDI_RX_BIT_LOCK
;
4264 I915_WRITE(reg
, temp
);
4269 /* enable CPU FDI TX and PCH FDI RX */
4270 reg
= FDI_TX_CTL(pipe
);
4271 temp
= I915_READ(reg
);
4272 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
4273 temp
|= FDI_DP_PORT_WIDTH(crtc_state
->fdi_lanes
);
4274 temp
&= ~FDI_LINK_TRAIN_NONE
;
4275 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
4276 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
4278 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
4279 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
4281 I915_WRITE(FDI_RX_MISC(pipe
),
4282 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
4284 reg
= FDI_RX_CTL(pipe
);
4285 temp
= I915_READ(reg
);
4286 if (HAS_PCH_CPT(dev_priv
)) {
4287 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
4288 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
4290 temp
&= ~FDI_LINK_TRAIN_NONE
;
4291 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
4293 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
4298 for (i
= 0; i
< 4; i
++) {
4299 reg
= FDI_TX_CTL(pipe
);
4300 temp
= I915_READ(reg
);
4301 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
4302 temp
|= snb_b_fdi_train_param
[i
];
4303 I915_WRITE(reg
, temp
);
4308 for (retry
= 0; retry
< 5; retry
++) {
4309 reg
= FDI_RX_IIR(pipe
);
4310 temp
= I915_READ(reg
);
4311 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
4312 if (temp
& FDI_RX_BIT_LOCK
) {
4313 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
4314 DRM_DEBUG_KMS("FDI train 1 done.\n");
4323 DRM_ERROR("FDI train 1 fail!\n");
4326 reg
= FDI_TX_CTL(pipe
);
4327 temp
= I915_READ(reg
);
4328 temp
&= ~FDI_LINK_TRAIN_NONE
;
4329 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
4330 if (IS_GEN(dev_priv
, 6)) {
4331 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
4333 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
4335 I915_WRITE(reg
, temp
);
4337 reg
= FDI_RX_CTL(pipe
);
4338 temp
= I915_READ(reg
);
4339 if (HAS_PCH_CPT(dev_priv
)) {
4340 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
4341 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
4343 temp
&= ~FDI_LINK_TRAIN_NONE
;
4344 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
4346 I915_WRITE(reg
, temp
);
4351 for (i
= 0; i
< 4; i
++) {
4352 reg
= FDI_TX_CTL(pipe
);
4353 temp
= I915_READ(reg
);
4354 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
4355 temp
|= snb_b_fdi_train_param
[i
];
4356 I915_WRITE(reg
, temp
);
4361 for (retry
= 0; retry
< 5; retry
++) {
4362 reg
= FDI_RX_IIR(pipe
);
4363 temp
= I915_READ(reg
);
4364 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
4365 if (temp
& FDI_RX_SYMBOL_LOCK
) {
4366 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
4367 DRM_DEBUG_KMS("FDI train 2 done.\n");
4376 DRM_ERROR("FDI train 2 fail!\n");
4378 DRM_DEBUG_KMS("FDI train done.\n");
4381 /* Manual link training for Ivy Bridge A0 parts */
4382 static void ivb_manual_fdi_link_train(struct intel_crtc
*crtc
,
4383 const struct intel_crtc_state
*crtc_state
)
4385 struct drm_device
*dev
= crtc
->base
.dev
;
4386 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4387 int pipe
= crtc
->pipe
;
4391 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4393 reg
= FDI_RX_IMR(pipe
);
4394 temp
= I915_READ(reg
);
4395 temp
&= ~FDI_RX_SYMBOL_LOCK
;
4396 temp
&= ~FDI_RX_BIT_LOCK
;
4397 I915_WRITE(reg
, temp
);
4402 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
4403 I915_READ(FDI_RX_IIR(pipe
)));
4405 /* Try each vswing and preemphasis setting twice before moving on */
4406 for (j
= 0; j
< ARRAY_SIZE(snb_b_fdi_train_param
) * 2; j
++) {
4407 /* disable first in case we need to retry */
4408 reg
= FDI_TX_CTL(pipe
);
4409 temp
= I915_READ(reg
);
4410 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
4411 temp
&= ~FDI_TX_ENABLE
;
4412 I915_WRITE(reg
, temp
);
4414 reg
= FDI_RX_CTL(pipe
);
4415 temp
= I915_READ(reg
);
4416 temp
&= ~FDI_LINK_TRAIN_AUTO
;
4417 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
4418 temp
&= ~FDI_RX_ENABLE
;
4419 I915_WRITE(reg
, temp
);
4421 /* enable CPU FDI TX and PCH FDI RX */
4422 reg
= FDI_TX_CTL(pipe
);
4423 temp
= I915_READ(reg
);
4424 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
4425 temp
|= FDI_DP_PORT_WIDTH(crtc_state
->fdi_lanes
);
4426 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
4427 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
4428 temp
|= snb_b_fdi_train_param
[j
/2];
4429 temp
|= FDI_COMPOSITE_SYNC
;
4430 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
4432 I915_WRITE(FDI_RX_MISC(pipe
),
4433 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
4435 reg
= FDI_RX_CTL(pipe
);
4436 temp
= I915_READ(reg
);
4437 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
4438 temp
|= FDI_COMPOSITE_SYNC
;
4439 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
4442 udelay(1); /* should be 0.5us */
4444 for (i
= 0; i
< 4; i
++) {
4445 reg
= FDI_RX_IIR(pipe
);
4446 temp
= I915_READ(reg
);
4447 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
4449 if (temp
& FDI_RX_BIT_LOCK
||
4450 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
4451 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
4452 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4456 udelay(1); /* should be 0.5us */
4459 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j
/ 2);
4464 reg
= FDI_TX_CTL(pipe
);
4465 temp
= I915_READ(reg
);
4466 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
4467 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
4468 I915_WRITE(reg
, temp
);
4470 reg
= FDI_RX_CTL(pipe
);
4471 temp
= I915_READ(reg
);
4472 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
4473 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
4474 I915_WRITE(reg
, temp
);
4477 udelay(2); /* should be 1.5us */
4479 for (i
= 0; i
< 4; i
++) {
4480 reg
= FDI_RX_IIR(pipe
);
4481 temp
= I915_READ(reg
);
4482 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
4484 if (temp
& FDI_RX_SYMBOL_LOCK
||
4485 (I915_READ(reg
) & FDI_RX_SYMBOL_LOCK
)) {
4486 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
4487 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4491 udelay(2); /* should be 1.5us */
4494 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j
/ 2);
4498 DRM_DEBUG_KMS("FDI train done.\n");
4501 static void ironlake_fdi_pll_enable(const struct intel_crtc_state
*crtc_state
)
4503 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
4504 struct drm_i915_private
*dev_priv
= to_i915(intel_crtc
->base
.dev
);
4505 int pipe
= intel_crtc
->pipe
;
4509 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4510 reg
= FDI_RX_CTL(pipe
);
4511 temp
= I915_READ(reg
);
4512 temp
&= ~(FDI_DP_PORT_WIDTH_MASK
| (0x7 << 16));
4513 temp
|= FDI_DP_PORT_WIDTH(crtc_state
->fdi_lanes
);
4514 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
4515 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
4520 /* Switch from Rawclk to PCDclk */
4521 temp
= I915_READ(reg
);
4522 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
4527 /* Enable CPU FDI TX PLL, always on for Ironlake */
4528 reg
= FDI_TX_CTL(pipe
);
4529 temp
= I915_READ(reg
);
4530 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
4531 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
4538 static void ironlake_fdi_pll_disable(struct intel_crtc
*intel_crtc
)
4540 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4541 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4542 int pipe
= intel_crtc
->pipe
;
4546 /* Switch from PCDclk to Rawclk */
4547 reg
= FDI_RX_CTL(pipe
);
4548 temp
= I915_READ(reg
);
4549 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
4551 /* Disable CPU FDI TX PLL */
4552 reg
= FDI_TX_CTL(pipe
);
4553 temp
= I915_READ(reg
);
4554 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
4559 reg
= FDI_RX_CTL(pipe
);
4560 temp
= I915_READ(reg
);
4561 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
4563 /* Wait for the clocks to turn off. */
4568 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
4570 struct drm_device
*dev
= crtc
->dev
;
4571 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4572 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4573 int pipe
= intel_crtc
->pipe
;
4577 /* disable CPU FDI tx and PCH FDI rx */
4578 reg
= FDI_TX_CTL(pipe
);
4579 temp
= I915_READ(reg
);
4580 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
4583 reg
= FDI_RX_CTL(pipe
);
4584 temp
= I915_READ(reg
);
4585 temp
&= ~(0x7 << 16);
4586 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
4587 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
4592 /* Ironlake workaround, disable clock pointer after downing FDI */
4593 if (HAS_PCH_IBX(dev_priv
))
4594 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
4596 /* still set train pattern 1 */
4597 reg
= FDI_TX_CTL(pipe
);
4598 temp
= I915_READ(reg
);
4599 temp
&= ~FDI_LINK_TRAIN_NONE
;
4600 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
4601 I915_WRITE(reg
, temp
);
4603 reg
= FDI_RX_CTL(pipe
);
4604 temp
= I915_READ(reg
);
4605 if (HAS_PCH_CPT(dev_priv
)) {
4606 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
4607 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
4609 temp
&= ~FDI_LINK_TRAIN_NONE
;
4610 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
4612 /* BPC in FDI rx is consistent with that in PIPECONF */
4613 temp
&= ~(0x07 << 16);
4614 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
4615 I915_WRITE(reg
, temp
);
4621 bool intel_has_pending_fb_unpin(struct drm_i915_private
*dev_priv
)
4623 struct drm_crtc
*crtc
;
4626 drm_for_each_crtc(crtc
, &dev_priv
->drm
) {
4627 struct drm_crtc_commit
*commit
;
4628 spin_lock(&crtc
->commit_lock
);
4629 commit
= list_first_entry_or_null(&crtc
->commit_list
,
4630 struct drm_crtc_commit
, commit_entry
);
4631 cleanup_done
= commit
?
4632 try_wait_for_completion(&commit
->cleanup_done
) : true;
4633 spin_unlock(&crtc
->commit_lock
);
4638 drm_crtc_wait_one_vblank(crtc
);
4646 void lpt_disable_iclkip(struct drm_i915_private
*dev_priv
)
4650 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_GATE
);
4652 mutex_lock(&dev_priv
->sb_lock
);
4654 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
4655 temp
|= SBI_SSCCTL_DISABLE
;
4656 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
4658 mutex_unlock(&dev_priv
->sb_lock
);
4661 /* Program iCLKIP clock to the desired frequency */
4662 static void lpt_program_iclkip(const struct intel_crtc_state
*crtc_state
)
4664 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
4665 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
4666 int clock
= crtc_state
->base
.adjusted_mode
.crtc_clock
;
4667 u32 divsel
, phaseinc
, auxdiv
, phasedir
= 0;
4670 lpt_disable_iclkip(dev_priv
);
4672 /* The iCLK virtual clock root frequency is in MHz,
4673 * but the adjusted_mode->crtc_clock in in KHz. To get the
4674 * divisors, it is necessary to divide one by another, so we
4675 * convert the virtual clock precision to KHz here for higher
4678 for (auxdiv
= 0; auxdiv
< 2; auxdiv
++) {
4679 u32 iclk_virtual_root_freq
= 172800 * 1000;
4680 u32 iclk_pi_range
= 64;
4681 u32 desired_divisor
;
4683 desired_divisor
= DIV_ROUND_CLOSEST(iclk_virtual_root_freq
,
4685 divsel
= (desired_divisor
/ iclk_pi_range
) - 2;
4686 phaseinc
= desired_divisor
% iclk_pi_range
;
4689 * Near 20MHz is a corner case which is
4690 * out of range for the 7-bit divisor
4696 /* This should not happen with any sane values */
4697 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel
) &
4698 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
);
4699 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir
) &
4700 ~SBI_SSCDIVINTPHASE_INCVAL_MASK
);
4702 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4709 mutex_lock(&dev_priv
->sb_lock
);
4711 /* Program SSCDIVINTPHASE6 */
4712 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
4713 temp
&= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
;
4714 temp
|= SBI_SSCDIVINTPHASE_DIVSEL(divsel
);
4715 temp
&= ~SBI_SSCDIVINTPHASE_INCVAL_MASK
;
4716 temp
|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc
);
4717 temp
|= SBI_SSCDIVINTPHASE_DIR(phasedir
);
4718 temp
|= SBI_SSCDIVINTPHASE_PROPAGATE
;
4719 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE6
, temp
, SBI_ICLK
);
4721 /* Program SSCAUXDIV */
4722 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
4723 temp
&= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4724 temp
|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv
);
4725 intel_sbi_write(dev_priv
, SBI_SSCAUXDIV6
, temp
, SBI_ICLK
);
4727 /* Enable modulator and associated divider */
4728 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
4729 temp
&= ~SBI_SSCCTL_DISABLE
;
4730 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
4732 mutex_unlock(&dev_priv
->sb_lock
);
4734 /* Wait for initialization time */
4737 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_UNGATE
);
4740 int lpt_get_iclkip(struct drm_i915_private
*dev_priv
)
4742 u32 divsel
, phaseinc
, auxdiv
;
4743 u32 iclk_virtual_root_freq
= 172800 * 1000;
4744 u32 iclk_pi_range
= 64;
4745 u32 desired_divisor
;
4748 if ((I915_READ(PIXCLK_GATE
) & PIXCLK_GATE_UNGATE
) == 0)
4751 mutex_lock(&dev_priv
->sb_lock
);
4753 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
4754 if (temp
& SBI_SSCCTL_DISABLE
) {
4755 mutex_unlock(&dev_priv
->sb_lock
);
4759 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
4760 divsel
= (temp
& SBI_SSCDIVINTPHASE_DIVSEL_MASK
) >>
4761 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT
;
4762 phaseinc
= (temp
& SBI_SSCDIVINTPHASE_INCVAL_MASK
) >>
4763 SBI_SSCDIVINTPHASE_INCVAL_SHIFT
;
4765 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
4766 auxdiv
= (temp
& SBI_SSCAUXDIV_FINALDIV2SEL_MASK
) >>
4767 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT
;
4769 mutex_unlock(&dev_priv
->sb_lock
);
4771 desired_divisor
= (divsel
+ 2) * iclk_pi_range
+ phaseinc
;
4773 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq
,
4774 desired_divisor
<< auxdiv
);
4777 static void ironlake_pch_transcoder_set_timings(const struct intel_crtc_state
*crtc_state
,
4778 enum pipe pch_transcoder
)
4780 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
4781 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
4782 enum transcoder cpu_transcoder
= crtc_state
->cpu_transcoder
;
4784 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder
),
4785 I915_READ(HTOTAL(cpu_transcoder
)));
4786 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder
),
4787 I915_READ(HBLANK(cpu_transcoder
)));
4788 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder
),
4789 I915_READ(HSYNC(cpu_transcoder
)));
4791 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder
),
4792 I915_READ(VTOTAL(cpu_transcoder
)));
4793 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder
),
4794 I915_READ(VBLANK(cpu_transcoder
)));
4795 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder
),
4796 I915_READ(VSYNC(cpu_transcoder
)));
4797 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder
),
4798 I915_READ(VSYNCSHIFT(cpu_transcoder
)));
4801 static void cpt_set_fdi_bc_bifurcation(struct drm_i915_private
*dev_priv
, bool enable
)
4805 temp
= I915_READ(SOUTH_CHICKEN1
);
4806 if (!!(temp
& FDI_BC_BIFURCATION_SELECT
) == enable
)
4809 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
4810 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
4812 temp
&= ~FDI_BC_BIFURCATION_SELECT
;
4814 temp
|= FDI_BC_BIFURCATION_SELECT
;
4816 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable
? "en" : "dis");
4817 I915_WRITE(SOUTH_CHICKEN1
, temp
);
4818 POSTING_READ(SOUTH_CHICKEN1
);
4821 static void ivybridge_update_fdi_bc_bifurcation(const struct intel_crtc_state
*crtc_state
)
4823 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
4824 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
4826 switch (crtc
->pipe
) {
4830 if (crtc_state
->fdi_lanes
> 2)
4831 cpt_set_fdi_bc_bifurcation(dev_priv
, false);
4833 cpt_set_fdi_bc_bifurcation(dev_priv
, true);
4837 cpt_set_fdi_bc_bifurcation(dev_priv
, true);
4846 * Finds the encoder associated with the given CRTC. This can only be
4847 * used when we know that the CRTC isn't feeding multiple encoders!
4849 static struct intel_encoder
*
4850 intel_get_crtc_new_encoder(const struct intel_atomic_state
*state
,
4851 const struct intel_crtc_state
*crtc_state
)
4853 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
4854 const struct drm_connector_state
*connector_state
;
4855 const struct drm_connector
*connector
;
4856 struct intel_encoder
*encoder
= NULL
;
4857 int num_encoders
= 0;
4860 for_each_new_connector_in_state(&state
->base
, connector
, connector_state
, i
) {
4861 if (connector_state
->crtc
!= &crtc
->base
)
4864 encoder
= to_intel_encoder(connector_state
->best_encoder
);
4868 WARN(num_encoders
!= 1, "%d encoders for pipe %c\n",
4869 num_encoders
, pipe_name(crtc
->pipe
));
4875 * Enable PCH resources required for PCH ports:
4877 * - FDI training & RX/TX
4878 * - update transcoder timings
4879 * - DP transcoding bits
4882 static void ironlake_pch_enable(const struct intel_atomic_state
*state
,
4883 const struct intel_crtc_state
*crtc_state
)
4885 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
4886 struct drm_device
*dev
= crtc
->base
.dev
;
4887 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4888 int pipe
= crtc
->pipe
;
4891 assert_pch_transcoder_disabled(dev_priv
, pipe
);
4893 if (IS_IVYBRIDGE(dev_priv
))
4894 ivybridge_update_fdi_bc_bifurcation(crtc_state
);
4896 /* Write the TU size bits before fdi link training, so that error
4897 * detection works. */
4898 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
4899 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
4901 /* For PCH output, training FDI link */
4902 dev_priv
->display
.fdi_link_train(crtc
, crtc_state
);
4904 /* We need to program the right clock selection before writing the pixel
4905 * mutliplier into the DPLL. */
4906 if (HAS_PCH_CPT(dev_priv
)) {
4909 temp
= I915_READ(PCH_DPLL_SEL
);
4910 temp
|= TRANS_DPLL_ENABLE(pipe
);
4911 sel
= TRANS_DPLLB_SEL(pipe
);
4912 if (crtc_state
->shared_dpll
==
4913 intel_get_shared_dpll_by_id(dev_priv
, DPLL_ID_PCH_PLL_B
))
4917 I915_WRITE(PCH_DPLL_SEL
, temp
);
4920 /* XXX: pch pll's can be enabled any time before we enable the PCH
4921 * transcoder, and we actually should do this to not upset any PCH
4922 * transcoder that already use the clock when we share it.
4924 * Note that enable_shared_dpll tries to do the right thing, but
4925 * get_shared_dpll unconditionally resets the pll - we need that to have
4926 * the right LVDS enable sequence. */
4927 intel_enable_shared_dpll(crtc_state
);
4929 /* set transcoder timing, panel must allow it */
4930 assert_panel_unlocked(dev_priv
, pipe
);
4931 ironlake_pch_transcoder_set_timings(crtc_state
, pipe
);
4933 intel_fdi_normal_train(crtc
);
4935 /* For PCH DP, enable TRANS_DP_CTL */
4936 if (HAS_PCH_CPT(dev_priv
) &&
4937 intel_crtc_has_dp_encoder(crtc_state
)) {
4938 const struct drm_display_mode
*adjusted_mode
=
4939 &crtc_state
->base
.adjusted_mode
;
4940 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) >> 5;
4941 i915_reg_t reg
= TRANS_DP_CTL(pipe
);
4944 temp
= I915_READ(reg
);
4945 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
4946 TRANS_DP_SYNC_MASK
|
4948 temp
|= TRANS_DP_OUTPUT_ENABLE
;
4949 temp
|= bpc
<< 9; /* same format but at 11:9 */
4951 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
4952 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
4953 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
4954 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
4956 port
= intel_get_crtc_new_encoder(state
, crtc_state
)->port
;
4957 WARN_ON(port
< PORT_B
|| port
> PORT_D
);
4958 temp
|= TRANS_DP_PORT_SEL(port
);
4960 I915_WRITE(reg
, temp
);
4963 ironlake_enable_pch_transcoder(crtc_state
);
4966 static void lpt_pch_enable(const struct intel_atomic_state
*state
,
4967 const struct intel_crtc_state
*crtc_state
)
4969 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
4970 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
4971 enum transcoder cpu_transcoder
= crtc_state
->cpu_transcoder
;
4973 assert_pch_transcoder_disabled(dev_priv
, PIPE_A
);
4975 lpt_program_iclkip(crtc_state
);
4977 /* Set transcoder timing. */
4978 ironlake_pch_transcoder_set_timings(crtc_state
, PIPE_A
);
4980 lpt_enable_pch_transcoder(dev_priv
, cpu_transcoder
);
4983 static void cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
4985 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4986 i915_reg_t dslreg
= PIPEDSL(pipe
);
4989 temp
= I915_READ(dslreg
);
4991 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
4992 if (wait_for(I915_READ(dslreg
) != temp
, 5))
4993 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe
));
4998 * The hardware phase 0.0 refers to the center of the pixel.
4999 * We want to start from the top/left edge which is phase
5000 * -0.5. That matches how the hardware calculates the scaling
5001 * factors (from top-left of the first pixel to bottom-right
5002 * of the last pixel, as opposed to the pixel centers).
5004 * For 4:2:0 subsampled chroma planes we obviously have to
5005 * adjust that so that the chroma sample position lands in
5008 * Note that for packed YCbCr 4:2:2 formats there is no way to
5009 * control chroma siting. The hardware simply replicates the
5010 * chroma samples for both of the luma samples, and thus we don't
5011 * actually get the expected MPEG2 chroma siting convention :(
5012 * The same behaviour is observed on pre-SKL platforms as well.
5014 * Theory behind the formula (note that we ignore sub-pixel
5015 * source coordinates):
5016 * s = source sample position
5017 * d = destination sample position
5022 * | | 1.5 (initial phase)
5030 * | -0.375 (initial phase)
5037 u16
skl_scaler_calc_phase(int sub
, int scale
, bool chroma_cosited
)
5039 int phase
= -0x8000;
5043 phase
+= (sub
- 1) * 0x8000 / sub
;
5045 phase
+= scale
/ (2 * sub
);
5048 * Hardware initial phase limited to [-0.5:1.5].
5049 * Since the max hardware scale factor is 3.0, we
5050 * should never actually excdeed 1.0 here.
5052 WARN_ON(phase
< -0x8000 || phase
> 0x18000);
5055 phase
= 0x10000 + phase
;
5057 trip
= PS_PHASE_TRIP
;
5059 return ((phase
>> 2) & PS_PHASE_MASK
) | trip
;
5063 skl_update_scaler(struct intel_crtc_state
*crtc_state
, bool force_detach
,
5064 unsigned int scaler_user
, int *scaler_id
,
5065 int src_w
, int src_h
, int dst_w
, int dst_h
,
5066 const struct drm_format_info
*format
, bool need_scaler
)
5068 struct intel_crtc_scaler_state
*scaler_state
=
5069 &crtc_state
->scaler_state
;
5070 struct intel_crtc
*intel_crtc
=
5071 to_intel_crtc(crtc_state
->base
.crtc
);
5072 struct drm_i915_private
*dev_priv
= to_i915(intel_crtc
->base
.dev
);
5073 const struct drm_display_mode
*adjusted_mode
=
5074 &crtc_state
->base
.adjusted_mode
;
5077 * Src coordinates are already rotated by 270 degrees for
5078 * the 90/270 degree plane rotation cases (to match the
5079 * GTT mapping), hence no need to account for rotation here.
5081 if (src_w
!= dst_w
|| src_h
!= dst_h
)
5085 * Scaling/fitting not supported in IF-ID mode in GEN9+
5086 * TODO: Interlace fetch mode doesn't support YUV420 planar formats.
5087 * Once NV12 is enabled, handle it here while allocating scaler
5090 if (INTEL_GEN(dev_priv
) >= 9 && crtc_state
->base
.enable
&&
5091 need_scaler
&& adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
5092 DRM_DEBUG_KMS("Pipe/Plane scaling not supported with IF-ID mode\n");
5097 * if plane is being disabled or scaler is no more required or force detach
5098 * - free scaler binded to this plane/crtc
5099 * - in order to do this, update crtc->scaler_usage
5101 * Here scaler state in crtc_state is set free so that
5102 * scaler can be assigned to other user. Actual register
5103 * update to free the scaler is done in plane/panel-fit programming.
5104 * For this purpose crtc/plane_state->scaler_id isn't reset here.
5106 if (force_detach
|| !need_scaler
) {
5107 if (*scaler_id
>= 0) {
5108 scaler_state
->scaler_users
&= ~(1 << scaler_user
);
5109 scaler_state
->scalers
[*scaler_id
].in_use
= 0;
5111 DRM_DEBUG_KMS("scaler_user index %u.%u: "
5112 "Staged freeing scaler id %d scaler_users = 0x%x\n",
5113 intel_crtc
->pipe
, scaler_user
, *scaler_id
,
5114 scaler_state
->scaler_users
);
5120 if (format
&& is_planar_yuv_format(format
->format
) &&
5121 (src_h
< SKL_MIN_YUV_420_SRC_H
|| src_w
< SKL_MIN_YUV_420_SRC_W
)) {
5122 DRM_DEBUG_KMS("Planar YUV: src dimensions not met\n");
5127 if (src_w
< SKL_MIN_SRC_W
|| src_h
< SKL_MIN_SRC_H
||
5128 dst_w
< SKL_MIN_DST_W
|| dst_h
< SKL_MIN_DST_H
||
5129 (INTEL_GEN(dev_priv
) >= 11 &&
5130 (src_w
> ICL_MAX_SRC_W
|| src_h
> ICL_MAX_SRC_H
||
5131 dst_w
> ICL_MAX_DST_W
|| dst_h
> ICL_MAX_DST_H
)) ||
5132 (INTEL_GEN(dev_priv
) < 11 &&
5133 (src_w
> SKL_MAX_SRC_W
|| src_h
> SKL_MAX_SRC_H
||
5134 dst_w
> SKL_MAX_DST_W
|| dst_h
> SKL_MAX_DST_H
))) {
5135 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
5136 "size is out of scaler range\n",
5137 intel_crtc
->pipe
, scaler_user
, src_w
, src_h
, dst_w
, dst_h
);
5141 /* mark this plane as a scaler user in crtc_state */
5142 scaler_state
->scaler_users
|= (1 << scaler_user
);
5143 DRM_DEBUG_KMS("scaler_user index %u.%u: "
5144 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
5145 intel_crtc
->pipe
, scaler_user
, src_w
, src_h
, dst_w
, dst_h
,
5146 scaler_state
->scaler_users
);
5152 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
5154 * @state: crtc's scaler state
5157 * 0 - scaler_usage updated successfully
5158 * error - requested scaling cannot be supported or other error condition
5160 int skl_update_scaler_crtc(struct intel_crtc_state
*state
)
5162 const struct drm_display_mode
*adjusted_mode
= &state
->base
.adjusted_mode
;
5163 bool need_scaler
= false;
5165 if (state
->output_format
== INTEL_OUTPUT_FORMAT_YCBCR420
)
5168 return skl_update_scaler(state
, !state
->base
.active
, SKL_CRTC_INDEX
,
5169 &state
->scaler_state
.scaler_id
,
5170 state
->pipe_src_w
, state
->pipe_src_h
,
5171 adjusted_mode
->crtc_hdisplay
,
5172 adjusted_mode
->crtc_vdisplay
, NULL
, need_scaler
);
5176 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
5177 * @crtc_state: crtc's scaler state
5178 * @plane_state: atomic plane state to update
5181 * 0 - scaler_usage updated successfully
5182 * error - requested scaling cannot be supported or other error condition
5184 static int skl_update_scaler_plane(struct intel_crtc_state
*crtc_state
,
5185 struct intel_plane_state
*plane_state
)
5187 struct intel_plane
*intel_plane
=
5188 to_intel_plane(plane_state
->base
.plane
);
5189 struct drm_i915_private
*dev_priv
= to_i915(intel_plane
->base
.dev
);
5190 struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
5192 bool force_detach
= !fb
|| !plane_state
->base
.visible
;
5193 bool need_scaler
= false;
5195 /* Pre-gen11 and SDR planes always need a scaler for planar formats. */
5196 if (!icl_is_hdr_plane(dev_priv
, intel_plane
->id
) &&
5197 fb
&& is_planar_yuv_format(fb
->format
->format
))
5200 ret
= skl_update_scaler(crtc_state
, force_detach
,
5201 drm_plane_index(&intel_plane
->base
),
5202 &plane_state
->scaler_id
,
5203 drm_rect_width(&plane_state
->base
.src
) >> 16,
5204 drm_rect_height(&plane_state
->base
.src
) >> 16,
5205 drm_rect_width(&plane_state
->base
.dst
),
5206 drm_rect_height(&plane_state
->base
.dst
),
5207 fb
? fb
->format
: NULL
, need_scaler
);
5209 if (ret
|| plane_state
->scaler_id
< 0)
5212 /* check colorkey */
5213 if (plane_state
->ckey
.flags
) {
5214 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
5215 intel_plane
->base
.base
.id
,
5216 intel_plane
->base
.name
);
5220 /* Check src format */
5221 switch (fb
->format
->format
) {
5222 case DRM_FORMAT_RGB565
:
5223 case DRM_FORMAT_XBGR8888
:
5224 case DRM_FORMAT_XRGB8888
:
5225 case DRM_FORMAT_ABGR8888
:
5226 case DRM_FORMAT_ARGB8888
:
5227 case DRM_FORMAT_XRGB2101010
:
5228 case DRM_FORMAT_XBGR2101010
:
5229 case DRM_FORMAT_XBGR16161616F
:
5230 case DRM_FORMAT_ABGR16161616F
:
5231 case DRM_FORMAT_XRGB16161616F
:
5232 case DRM_FORMAT_ARGB16161616F
:
5233 case DRM_FORMAT_YUYV
:
5234 case DRM_FORMAT_YVYU
:
5235 case DRM_FORMAT_UYVY
:
5236 case DRM_FORMAT_VYUY
:
5237 case DRM_FORMAT_NV12
:
5238 case DRM_FORMAT_P010
:
5239 case DRM_FORMAT_P012
:
5240 case DRM_FORMAT_P016
:
5241 case DRM_FORMAT_Y210
:
5242 case DRM_FORMAT_Y212
:
5243 case DRM_FORMAT_Y216
:
5244 case DRM_FORMAT_XVYU2101010
:
5245 case DRM_FORMAT_XVYU12_16161616
:
5246 case DRM_FORMAT_XVYU16161616
:
5249 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
5250 intel_plane
->base
.base
.id
, intel_plane
->base
.name
,
5251 fb
->base
.id
, fb
->format
->format
);
5258 static void skylake_scaler_disable(struct intel_crtc
*crtc
)
5262 for (i
= 0; i
< crtc
->num_scalers
; i
++)
5263 skl_detach_scaler(crtc
, i
);
5266 static void skylake_pfit_enable(const struct intel_crtc_state
*crtc_state
)
5268 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
5269 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
5270 enum pipe pipe
= crtc
->pipe
;
5271 const struct intel_crtc_scaler_state
*scaler_state
=
5272 &crtc_state
->scaler_state
;
5274 if (crtc_state
->pch_pfit
.enabled
) {
5275 u16 uv_rgb_hphase
, uv_rgb_vphase
;
5276 int pfit_w
, pfit_h
, hscale
, vscale
;
5279 if (WARN_ON(crtc_state
->scaler_state
.scaler_id
< 0))
5282 pfit_w
= (crtc_state
->pch_pfit
.size
>> 16) & 0xFFFF;
5283 pfit_h
= crtc_state
->pch_pfit
.size
& 0xFFFF;
5285 hscale
= (crtc_state
->pipe_src_w
<< 16) / pfit_w
;
5286 vscale
= (crtc_state
->pipe_src_h
<< 16) / pfit_h
;
5288 uv_rgb_hphase
= skl_scaler_calc_phase(1, hscale
, false);
5289 uv_rgb_vphase
= skl_scaler_calc_phase(1, vscale
, false);
5291 id
= scaler_state
->scaler_id
;
5292 I915_WRITE(SKL_PS_CTRL(pipe
, id
), PS_SCALER_EN
|
5293 PS_FILTER_MEDIUM
| scaler_state
->scalers
[id
].mode
);
5294 I915_WRITE_FW(SKL_PS_VPHASE(pipe
, id
),
5295 PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase
));
5296 I915_WRITE_FW(SKL_PS_HPHASE(pipe
, id
),
5297 PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase
));
5298 I915_WRITE(SKL_PS_WIN_POS(pipe
, id
), crtc_state
->pch_pfit
.pos
);
5299 I915_WRITE(SKL_PS_WIN_SZ(pipe
, id
), crtc_state
->pch_pfit
.size
);
5303 static void ironlake_pfit_enable(const struct intel_crtc_state
*crtc_state
)
5305 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
5306 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
5307 int pipe
= crtc
->pipe
;
5309 if (crtc_state
->pch_pfit
.enabled
) {
5310 /* Force use of hard-coded filter coefficients
5311 * as some pre-programmed values are broken,
5314 if (IS_IVYBRIDGE(dev_priv
) || IS_HASWELL(dev_priv
))
5315 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
|
5316 PF_PIPE_SEL_IVB(pipe
));
5318 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
5319 I915_WRITE(PF_WIN_POS(pipe
), crtc_state
->pch_pfit
.pos
);
5320 I915_WRITE(PF_WIN_SZ(pipe
), crtc_state
->pch_pfit
.size
);
5324 void hsw_enable_ips(const struct intel_crtc_state
*crtc_state
)
5326 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
5327 struct drm_device
*dev
= crtc
->base
.dev
;
5328 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5330 if (!crtc_state
->ips_enabled
)
5334 * We can only enable IPS after we enable a plane and wait for a vblank
5335 * This function is called from post_plane_update, which is run after
5338 WARN_ON(!(crtc_state
->active_planes
& ~BIT(PLANE_CURSOR
)));
5340 if (IS_BROADWELL(dev_priv
)) {
5341 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
,
5342 IPS_ENABLE
| IPS_PCODE_CONTROL
));
5343 /* Quoting Art Runyan: "its not safe to expect any particular
5344 * value in IPS_CTL bit 31 after enabling IPS through the
5345 * mailbox." Moreover, the mailbox may return a bogus state,
5346 * so we need to just enable it and continue on.
5349 I915_WRITE(IPS_CTL
, IPS_ENABLE
);
5350 /* The bit only becomes 1 in the next vblank, so this wait here
5351 * is essentially intel_wait_for_vblank. If we don't have this
5352 * and don't wait for vblanks until the end of crtc_enable, then
5353 * the HW state readout code will complain that the expected
5354 * IPS_CTL value is not the one we read. */
5355 if (intel_wait_for_register(&dev_priv
->uncore
,
5356 IPS_CTL
, IPS_ENABLE
, IPS_ENABLE
,
5358 DRM_ERROR("Timed out waiting for IPS enable\n");
5362 void hsw_disable_ips(const struct intel_crtc_state
*crtc_state
)
5364 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
5365 struct drm_device
*dev
= crtc
->base
.dev
;
5366 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5368 if (!crtc_state
->ips_enabled
)
5371 if (IS_BROADWELL(dev_priv
)) {
5372 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0));
5374 * Wait for PCODE to finish disabling IPS. The BSpec specified
5375 * 42ms timeout value leads to occasional timeouts so use 100ms
5378 if (intel_wait_for_register(&dev_priv
->uncore
,
5379 IPS_CTL
, IPS_ENABLE
, 0,
5381 DRM_ERROR("Timed out waiting for IPS disable\n");
5383 I915_WRITE(IPS_CTL
, 0);
5384 POSTING_READ(IPS_CTL
);
5387 /* We need to wait for a vblank before we can disable the plane. */
5388 intel_wait_for_vblank(dev_priv
, crtc
->pipe
);
5391 static void intel_crtc_dpms_overlay_disable(struct intel_crtc
*intel_crtc
)
5393 if (intel_crtc
->overlay
) {
5394 struct drm_device
*dev
= intel_crtc
->base
.dev
;
5396 mutex_lock(&dev
->struct_mutex
);
5397 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
5398 mutex_unlock(&dev
->struct_mutex
);
5401 /* Let userspace switch the overlay on again. In most cases userspace
5402 * has to recompute where to put it anyway.
5407 * intel_post_enable_primary - Perform operations after enabling primary plane
5408 * @crtc: the CRTC whose primary plane was just enabled
5409 * @new_crtc_state: the enabling state
5411 * Performs potentially sleeping operations that must be done after the primary
5412 * plane is enabled, such as updating FBC and IPS. Note that this may be
5413 * called due to an explicit primary plane update, or due to an implicit
5414 * re-enable that is caused when a sprite plane is updated to no longer
5415 * completely hide the primary plane.
5418 intel_post_enable_primary(struct drm_crtc
*crtc
,
5419 const struct intel_crtc_state
*new_crtc_state
)
5421 struct drm_device
*dev
= crtc
->dev
;
5422 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5423 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5424 int pipe
= intel_crtc
->pipe
;
5427 * Gen2 reports pipe underruns whenever all planes are disabled.
5428 * So don't enable underrun reporting before at least some planes
5430 * FIXME: Need to fix the logic to work when we turn off all planes
5431 * but leave the pipe running.
5433 if (IS_GEN(dev_priv
, 2))
5434 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
5436 /* Underruns don't always raise interrupts, so check manually. */
5437 intel_check_cpu_fifo_underruns(dev_priv
);
5438 intel_check_pch_fifo_underruns(dev_priv
);
5441 /* FIXME get rid of this and use pre_plane_update */
5443 intel_pre_disable_primary_noatomic(struct drm_crtc
*crtc
)
5445 struct drm_device
*dev
= crtc
->dev
;
5446 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5447 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5448 int pipe
= intel_crtc
->pipe
;
5451 * Gen2 reports pipe underruns whenever all planes are disabled.
5452 * So disable underrun reporting before all the planes get disabled.
5454 if (IS_GEN(dev_priv
, 2))
5455 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
5457 hsw_disable_ips(to_intel_crtc_state(crtc
->state
));
5460 * Vblank time updates from the shadow to live plane control register
5461 * are blocked if the memory self-refresh mode is active at that
5462 * moment. So to make sure the plane gets truly disabled, disable
5463 * first the self-refresh mode. The self-refresh enable bit in turn
5464 * will be checked/applied by the HW only at the next frame start
5465 * event which is after the vblank start event, so we need to have a
5466 * wait-for-vblank between disabling the plane and the pipe.
5468 if (HAS_GMCH(dev_priv
) &&
5469 intel_set_memory_cxsr(dev_priv
, false))
5470 intel_wait_for_vblank(dev_priv
, pipe
);
5473 static bool hsw_pre_update_disable_ips(const struct intel_crtc_state
*old_crtc_state
,
5474 const struct intel_crtc_state
*new_crtc_state
)
5476 struct intel_crtc
*crtc
= to_intel_crtc(new_crtc_state
->base
.crtc
);
5477 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
5479 if (!old_crtc_state
->ips_enabled
)
5482 if (needs_modeset(&new_crtc_state
->base
))
5486 * Workaround : Do not read or write the pipe palette/gamma data while
5487 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
5489 * Disable IPS before we program the LUT.
5491 if (IS_HASWELL(dev_priv
) &&
5492 (new_crtc_state
->base
.color_mgmt_changed
||
5493 new_crtc_state
->update_pipe
) &&
5494 new_crtc_state
->gamma_mode
== GAMMA_MODE_MODE_SPLIT
)
5497 return !new_crtc_state
->ips_enabled
;
5500 static bool hsw_post_update_enable_ips(const struct intel_crtc_state
*old_crtc_state
,
5501 const struct intel_crtc_state
*new_crtc_state
)
5503 struct intel_crtc
*crtc
= to_intel_crtc(new_crtc_state
->base
.crtc
);
5504 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
5506 if (!new_crtc_state
->ips_enabled
)
5509 if (needs_modeset(&new_crtc_state
->base
))
5513 * Workaround : Do not read or write the pipe palette/gamma data while
5514 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
5516 * Re-enable IPS after the LUT has been programmed.
5518 if (IS_HASWELL(dev_priv
) &&
5519 (new_crtc_state
->base
.color_mgmt_changed
||
5520 new_crtc_state
->update_pipe
) &&
5521 new_crtc_state
->gamma_mode
== GAMMA_MODE_MODE_SPLIT
)
5525 * We can't read out IPS on broadwell, assume the worst and
5526 * forcibly enable IPS on the first fastset.
5528 if (new_crtc_state
->update_pipe
&&
5529 old_crtc_state
->base
.adjusted_mode
.private_flags
& I915_MODE_FLAG_INHERITED
)
5532 return !old_crtc_state
->ips_enabled
;
5535 static bool needs_nv12_wa(struct drm_i915_private
*dev_priv
,
5536 const struct intel_crtc_state
*crtc_state
)
5538 if (!crtc_state
->nv12_planes
)
5541 /* WA Display #0827: Gen9:all */
5542 if (IS_GEN(dev_priv
, 9) && !IS_GEMINILAKE(dev_priv
))
5548 static bool needs_scalerclk_wa(struct drm_i915_private
*dev_priv
,
5549 const struct intel_crtc_state
*crtc_state
)
5551 /* Wa_2006604312:icl */
5552 if (crtc_state
->scaler_state
.scaler_users
> 0 && IS_ICELAKE(dev_priv
))
5558 static void intel_post_plane_update(struct intel_crtc_state
*old_crtc_state
)
5560 struct intel_crtc
*crtc
= to_intel_crtc(old_crtc_state
->base
.crtc
);
5561 struct drm_device
*dev
= crtc
->base
.dev
;
5562 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5563 struct drm_atomic_state
*old_state
= old_crtc_state
->base
.state
;
5564 struct intel_crtc_state
*pipe_config
=
5565 intel_atomic_get_new_crtc_state(to_intel_atomic_state(old_state
),
5567 struct drm_plane
*primary
= crtc
->base
.primary
;
5568 struct drm_plane_state
*old_primary_state
=
5569 drm_atomic_get_old_plane_state(old_state
, primary
);
5571 intel_frontbuffer_flip(to_i915(crtc
->base
.dev
), pipe_config
->fb_bits
);
5573 if (pipe_config
->update_wm_post
&& pipe_config
->base
.active
)
5574 intel_update_watermarks(crtc
);
5576 if (hsw_post_update_enable_ips(old_crtc_state
, pipe_config
))
5577 hsw_enable_ips(pipe_config
);
5579 if (old_primary_state
) {
5580 struct drm_plane_state
*new_primary_state
=
5581 drm_atomic_get_new_plane_state(old_state
, primary
);
5583 intel_fbc_post_update(crtc
);
5585 if (new_primary_state
->visible
&&
5586 (needs_modeset(&pipe_config
->base
) ||
5587 !old_primary_state
->visible
))
5588 intel_post_enable_primary(&crtc
->base
, pipe_config
);
5591 if (needs_nv12_wa(dev_priv
, old_crtc_state
) &&
5592 !needs_nv12_wa(dev_priv
, pipe_config
))
5593 skl_wa_827(dev_priv
, crtc
->pipe
, false);
5595 if (needs_scalerclk_wa(dev_priv
, old_crtc_state
) &&
5596 !needs_scalerclk_wa(dev_priv
, pipe_config
))
5597 icl_wa_scalerclkgating(dev_priv
, crtc
->pipe
, false);
5600 static void intel_pre_plane_update(struct intel_crtc_state
*old_crtc_state
,
5601 struct intel_crtc_state
*pipe_config
)
5603 struct intel_crtc
*crtc
= to_intel_crtc(old_crtc_state
->base
.crtc
);
5604 struct drm_device
*dev
= crtc
->base
.dev
;
5605 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5606 struct drm_atomic_state
*old_state
= old_crtc_state
->base
.state
;
5607 struct drm_plane
*primary
= crtc
->base
.primary
;
5608 struct drm_plane_state
*old_primary_state
=
5609 drm_atomic_get_old_plane_state(old_state
, primary
);
5610 bool modeset
= needs_modeset(&pipe_config
->base
);
5611 struct intel_atomic_state
*old_intel_state
=
5612 to_intel_atomic_state(old_state
);
5614 if (hsw_pre_update_disable_ips(old_crtc_state
, pipe_config
))
5615 hsw_disable_ips(old_crtc_state
);
5617 if (old_primary_state
) {
5618 struct intel_plane_state
*new_primary_state
=
5619 intel_atomic_get_new_plane_state(old_intel_state
,
5620 to_intel_plane(primary
));
5622 intel_fbc_pre_update(crtc
, pipe_config
, new_primary_state
);
5624 * Gen2 reports pipe underruns whenever all planes are disabled.
5625 * So disable underrun reporting before all the planes get disabled.
5627 if (IS_GEN(dev_priv
, 2) && old_primary_state
->visible
&&
5628 (modeset
|| !new_primary_state
->base
.visible
))
5629 intel_set_cpu_fifo_underrun_reporting(dev_priv
, crtc
->pipe
, false);
5632 /* Display WA 827 */
5633 if (!needs_nv12_wa(dev_priv
, old_crtc_state
) &&
5634 needs_nv12_wa(dev_priv
, pipe_config
))
5635 skl_wa_827(dev_priv
, crtc
->pipe
, true);
5637 /* Wa_2006604312:icl */
5638 if (!needs_scalerclk_wa(dev_priv
, old_crtc_state
) &&
5639 needs_scalerclk_wa(dev_priv
, pipe_config
))
5640 icl_wa_scalerclkgating(dev_priv
, crtc
->pipe
, true);
5643 * Vblank time updates from the shadow to live plane control register
5644 * are blocked if the memory self-refresh mode is active at that
5645 * moment. So to make sure the plane gets truly disabled, disable
5646 * first the self-refresh mode. The self-refresh enable bit in turn
5647 * will be checked/applied by the HW only at the next frame start
5648 * event which is after the vblank start event, so we need to have a
5649 * wait-for-vblank between disabling the plane and the pipe.
5651 if (HAS_GMCH(dev_priv
) && old_crtc_state
->base
.active
&&
5652 pipe_config
->disable_cxsr
&& intel_set_memory_cxsr(dev_priv
, false))
5653 intel_wait_for_vblank(dev_priv
, crtc
->pipe
);
5656 * IVB workaround: must disable low power watermarks for at least
5657 * one frame before enabling scaling. LP watermarks can be re-enabled
5658 * when scaling is disabled.
5660 * WaCxSRDisabledForSpriteScaling:ivb
5662 if (pipe_config
->disable_lp_wm
&& ilk_disable_lp_wm(dev
) &&
5663 old_crtc_state
->base
.active
)
5664 intel_wait_for_vblank(dev_priv
, crtc
->pipe
);
5667 * If we're doing a modeset, we're done. No need to do any pre-vblank
5668 * watermark programming here.
5670 if (needs_modeset(&pipe_config
->base
))
5674 * For platforms that support atomic watermarks, program the
5675 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
5676 * will be the intermediate values that are safe for both pre- and
5677 * post- vblank; when vblank happens, the 'active' values will be set
5678 * to the final 'target' values and we'll do this again to get the
5679 * optimal watermarks. For gen9+ platforms, the values we program here
5680 * will be the final target values which will get automatically latched
5681 * at vblank time; no further programming will be necessary.
5683 * If a platform hasn't been transitioned to atomic watermarks yet,
5684 * we'll continue to update watermarks the old way, if flags tell
5687 if (dev_priv
->display
.initial_watermarks
!= NULL
)
5688 dev_priv
->display
.initial_watermarks(old_intel_state
,
5690 else if (pipe_config
->update_wm_pre
)
5691 intel_update_watermarks(crtc
);
5694 static void intel_crtc_disable_planes(struct intel_atomic_state
*state
,
5695 struct intel_crtc
*crtc
)
5697 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
5698 const struct intel_crtc_state
*new_crtc_state
=
5699 intel_atomic_get_new_crtc_state(state
, crtc
);
5700 unsigned int update_mask
= new_crtc_state
->update_planes
;
5701 const struct intel_plane_state
*old_plane_state
;
5702 struct intel_plane
*plane
;
5703 unsigned fb_bits
= 0;
5706 intel_crtc_dpms_overlay_disable(crtc
);
5708 for_each_old_intel_plane_in_state(state
, plane
, old_plane_state
, i
) {
5709 if (crtc
->pipe
!= plane
->pipe
||
5710 !(update_mask
& BIT(plane
->id
)))
5713 intel_disable_plane(plane
, new_crtc_state
);
5715 if (old_plane_state
->base
.visible
)
5716 fb_bits
|= plane
->frontbuffer_bit
;
5719 intel_frontbuffer_flip(dev_priv
, fb_bits
);
5722 static void intel_encoders_pre_pll_enable(struct drm_crtc
*crtc
,
5723 struct intel_crtc_state
*crtc_state
,
5724 struct drm_atomic_state
*old_state
)
5726 struct drm_connector_state
*conn_state
;
5727 struct drm_connector
*conn
;
5730 for_each_new_connector_in_state(old_state
, conn
, conn_state
, i
) {
5731 struct intel_encoder
*encoder
=
5732 to_intel_encoder(conn_state
->best_encoder
);
5734 if (conn_state
->crtc
!= crtc
)
5737 if (encoder
->pre_pll_enable
)
5738 encoder
->pre_pll_enable(encoder
, crtc_state
, conn_state
);
5742 static void intel_encoders_pre_enable(struct drm_crtc
*crtc
,
5743 struct intel_crtc_state
*crtc_state
,
5744 struct drm_atomic_state
*old_state
)
5746 struct drm_connector_state
*conn_state
;
5747 struct drm_connector
*conn
;
5750 for_each_new_connector_in_state(old_state
, conn
, conn_state
, i
) {
5751 struct intel_encoder
*encoder
=
5752 to_intel_encoder(conn_state
->best_encoder
);
5754 if (conn_state
->crtc
!= crtc
)
5757 if (encoder
->pre_enable
)
5758 encoder
->pre_enable(encoder
, crtc_state
, conn_state
);
5762 static void intel_encoders_enable(struct drm_crtc
*crtc
,
5763 struct intel_crtc_state
*crtc_state
,
5764 struct drm_atomic_state
*old_state
)
5766 struct drm_connector_state
*conn_state
;
5767 struct drm_connector
*conn
;
5770 for_each_new_connector_in_state(old_state
, conn
, conn_state
, i
) {
5771 struct intel_encoder
*encoder
=
5772 to_intel_encoder(conn_state
->best_encoder
);
5774 if (conn_state
->crtc
!= crtc
)
5777 if (encoder
->enable
)
5778 encoder
->enable(encoder
, crtc_state
, conn_state
);
5779 intel_opregion_notify_encoder(encoder
, true);
5783 static void intel_encoders_disable(struct drm_crtc
*crtc
,
5784 struct intel_crtc_state
*old_crtc_state
,
5785 struct drm_atomic_state
*old_state
)
5787 struct drm_connector_state
*old_conn_state
;
5788 struct drm_connector
*conn
;
5791 for_each_old_connector_in_state(old_state
, conn
, old_conn_state
, i
) {
5792 struct intel_encoder
*encoder
=
5793 to_intel_encoder(old_conn_state
->best_encoder
);
5795 if (old_conn_state
->crtc
!= crtc
)
5798 intel_opregion_notify_encoder(encoder
, false);
5799 if (encoder
->disable
)
5800 encoder
->disable(encoder
, old_crtc_state
, old_conn_state
);
5804 static void intel_encoders_post_disable(struct drm_crtc
*crtc
,
5805 struct intel_crtc_state
*old_crtc_state
,
5806 struct drm_atomic_state
*old_state
)
5808 struct drm_connector_state
*old_conn_state
;
5809 struct drm_connector
*conn
;
5812 for_each_old_connector_in_state(old_state
, conn
, old_conn_state
, i
) {
5813 struct intel_encoder
*encoder
=
5814 to_intel_encoder(old_conn_state
->best_encoder
);
5816 if (old_conn_state
->crtc
!= crtc
)
5819 if (encoder
->post_disable
)
5820 encoder
->post_disable(encoder
, old_crtc_state
, old_conn_state
);
5824 static void intel_encoders_post_pll_disable(struct drm_crtc
*crtc
,
5825 struct intel_crtc_state
*old_crtc_state
,
5826 struct drm_atomic_state
*old_state
)
5828 struct drm_connector_state
*old_conn_state
;
5829 struct drm_connector
*conn
;
5832 for_each_old_connector_in_state(old_state
, conn
, old_conn_state
, i
) {
5833 struct intel_encoder
*encoder
=
5834 to_intel_encoder(old_conn_state
->best_encoder
);
5836 if (old_conn_state
->crtc
!= crtc
)
5839 if (encoder
->post_pll_disable
)
5840 encoder
->post_pll_disable(encoder
, old_crtc_state
, old_conn_state
);
5844 static void intel_encoders_update_pipe(struct drm_crtc
*crtc
,
5845 struct intel_crtc_state
*crtc_state
,
5846 struct drm_atomic_state
*old_state
)
5848 struct drm_connector_state
*conn_state
;
5849 struct drm_connector
*conn
;
5852 for_each_new_connector_in_state(old_state
, conn
, conn_state
, i
) {
5853 struct intel_encoder
*encoder
=
5854 to_intel_encoder(conn_state
->best_encoder
);
5856 if (conn_state
->crtc
!= crtc
)
5859 if (encoder
->update_pipe
)
5860 encoder
->update_pipe(encoder
, crtc_state
, conn_state
);
5864 static void intel_disable_primary_plane(const struct intel_crtc_state
*crtc_state
)
5866 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
5867 struct intel_plane
*plane
= to_intel_plane(crtc
->base
.primary
);
5869 plane
->disable_plane(plane
, crtc_state
);
5872 static void ironlake_crtc_enable(struct intel_crtc_state
*pipe_config
,
5873 struct drm_atomic_state
*old_state
)
5875 struct drm_crtc
*crtc
= pipe_config
->base
.crtc
;
5876 struct drm_device
*dev
= crtc
->dev
;
5877 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5878 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5879 int pipe
= intel_crtc
->pipe
;
5880 struct intel_atomic_state
*old_intel_state
=
5881 to_intel_atomic_state(old_state
);
5883 if (WARN_ON(intel_crtc
->active
))
5887 * Sometimes spurious CPU pipe underruns happen during FDI
5888 * training, at least with VGA+HDMI cloning. Suppress them.
5890 * On ILK we get an occasional spurious CPU pipe underruns
5891 * between eDP port A enable and vdd enable. Also PCH port
5892 * enable seems to result in the occasional CPU pipe underrun.
5894 * Spurious PCH underruns also occur during PCH enabling.
5896 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
5897 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, false);
5899 if (pipe_config
->has_pch_encoder
)
5900 intel_prepare_shared_dpll(pipe_config
);
5902 if (intel_crtc_has_dp_encoder(pipe_config
))
5903 intel_dp_set_m_n(pipe_config
, M1_N1
);
5905 intel_set_pipe_timings(pipe_config
);
5906 intel_set_pipe_src_size(pipe_config
);
5908 if (pipe_config
->has_pch_encoder
) {
5909 intel_cpu_transcoder_set_m_n(pipe_config
,
5910 &pipe_config
->fdi_m_n
, NULL
);
5913 ironlake_set_pipeconf(pipe_config
);
5915 intel_crtc
->active
= true;
5917 intel_encoders_pre_enable(crtc
, pipe_config
, old_state
);
5919 if (pipe_config
->has_pch_encoder
) {
5920 /* Note: FDI PLL enabling _must_ be done before we enable the
5921 * cpu pipes, hence this is separate from all the other fdi/pch
5923 ironlake_fdi_pll_enable(pipe_config
);
5925 assert_fdi_tx_disabled(dev_priv
, pipe
);
5926 assert_fdi_rx_disabled(dev_priv
, pipe
);
5929 ironlake_pfit_enable(pipe_config
);
5932 * On ILK+ LUT must be loaded before the pipe is running but with
5935 intel_color_load_luts(pipe_config
);
5936 intel_color_commit(pipe_config
);
5937 /* update DSPCNTR to configure gamma for pipe bottom color */
5938 intel_disable_primary_plane(pipe_config
);
5940 if (dev_priv
->display
.initial_watermarks
!= NULL
)
5941 dev_priv
->display
.initial_watermarks(old_intel_state
, pipe_config
);
5942 intel_enable_pipe(pipe_config
);
5944 if (pipe_config
->has_pch_encoder
)
5945 ironlake_pch_enable(old_intel_state
, pipe_config
);
5947 assert_vblank_disabled(crtc
);
5948 intel_crtc_vblank_on(pipe_config
);
5950 intel_encoders_enable(crtc
, pipe_config
, old_state
);
5952 if (HAS_PCH_CPT(dev_priv
))
5953 cpt_verify_modeset(dev
, intel_crtc
->pipe
);
5956 * Must wait for vblank to avoid spurious PCH FIFO underruns.
5957 * And a second vblank wait is needed at least on ILK with
5958 * some interlaced HDMI modes. Let's do the double wait always
5959 * in case there are more corner cases we don't know about.
5961 if (pipe_config
->has_pch_encoder
) {
5962 intel_wait_for_vblank(dev_priv
, pipe
);
5963 intel_wait_for_vblank(dev_priv
, pipe
);
5965 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
5966 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, true);
5969 /* IPS only exists on ULT machines and is tied to pipe A. */
5970 static bool hsw_crtc_supports_ips(struct intel_crtc
*crtc
)
5972 return HAS_IPS(to_i915(crtc
->base
.dev
)) && crtc
->pipe
== PIPE_A
;
5975 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private
*dev_priv
,
5976 enum pipe pipe
, bool apply
)
5978 u32 val
= I915_READ(CLKGATE_DIS_PSL(pipe
));
5979 u32 mask
= DPF_GATING_DIS
| DPF_RAM_GATING_DIS
| DPFR_GATING_DIS
;
5986 I915_WRITE(CLKGATE_DIS_PSL(pipe
), val
);
5989 static void icl_pipe_mbus_enable(struct intel_crtc
*crtc
)
5991 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
5992 enum pipe pipe
= crtc
->pipe
;
5995 val
= MBUS_DBOX_A_CREDIT(2);
5996 val
|= MBUS_DBOX_BW_CREDIT(1);
5997 val
|= MBUS_DBOX_B_CREDIT(8);
5999 I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe
), val
);
6002 static void haswell_crtc_enable(struct intel_crtc_state
*pipe_config
,
6003 struct drm_atomic_state
*old_state
)
6005 struct drm_crtc
*crtc
= pipe_config
->base
.crtc
;
6006 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
6007 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6008 int pipe
= intel_crtc
->pipe
, hsw_workaround_pipe
;
6009 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
6010 struct intel_atomic_state
*old_intel_state
=
6011 to_intel_atomic_state(old_state
);
6012 bool psl_clkgate_wa
;
6014 if (WARN_ON(intel_crtc
->active
))
6017 intel_encoders_pre_pll_enable(crtc
, pipe_config
, old_state
);
6019 if (pipe_config
->shared_dpll
)
6020 intel_enable_shared_dpll(pipe_config
);
6022 intel_encoders_pre_enable(crtc
, pipe_config
, old_state
);
6024 if (intel_crtc_has_dp_encoder(pipe_config
))
6025 intel_dp_set_m_n(pipe_config
, M1_N1
);
6027 if (!transcoder_is_dsi(cpu_transcoder
))
6028 intel_set_pipe_timings(pipe_config
);
6030 intel_set_pipe_src_size(pipe_config
);
6032 if (cpu_transcoder
!= TRANSCODER_EDP
&&
6033 !transcoder_is_dsi(cpu_transcoder
)) {
6034 I915_WRITE(PIPE_MULT(cpu_transcoder
),
6035 pipe_config
->pixel_multiplier
- 1);
6038 if (pipe_config
->has_pch_encoder
) {
6039 intel_cpu_transcoder_set_m_n(pipe_config
,
6040 &pipe_config
->fdi_m_n
, NULL
);
6043 if (!transcoder_is_dsi(cpu_transcoder
))
6044 haswell_set_pipeconf(pipe_config
);
6046 haswell_set_pipemisc(pipe_config
);
6048 intel_crtc
->active
= true;
6050 /* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
6051 psl_clkgate_wa
= (IS_GEMINILAKE(dev_priv
) || IS_CANNONLAKE(dev_priv
)) &&
6052 pipe_config
->pch_pfit
.enabled
;
6054 glk_pipe_scaler_clock_gating_wa(dev_priv
, pipe
, true);
6056 if (INTEL_GEN(dev_priv
) >= 9)
6057 skylake_pfit_enable(pipe_config
);
6059 ironlake_pfit_enable(pipe_config
);
6062 * On ILK+ LUT must be loaded before the pipe is running but with
6065 intel_color_load_luts(pipe_config
);
6066 intel_color_commit(pipe_config
);
6067 /* update DSPCNTR to configure gamma/csc for pipe bottom color */
6068 if (INTEL_GEN(dev_priv
) < 9)
6069 intel_disable_primary_plane(pipe_config
);
6071 if (INTEL_GEN(dev_priv
) >= 11)
6072 icl_set_pipe_chicken(intel_crtc
);
6074 intel_ddi_set_pipe_settings(pipe_config
);
6075 if (!transcoder_is_dsi(cpu_transcoder
))
6076 intel_ddi_enable_transcoder_func(pipe_config
);
6078 if (dev_priv
->display
.initial_watermarks
!= NULL
)
6079 dev_priv
->display
.initial_watermarks(old_intel_state
, pipe_config
);
6081 if (INTEL_GEN(dev_priv
) >= 11)
6082 icl_pipe_mbus_enable(intel_crtc
);
6084 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
6085 if (!transcoder_is_dsi(cpu_transcoder
))
6086 intel_enable_pipe(pipe_config
);
6088 if (pipe_config
->has_pch_encoder
)
6089 lpt_pch_enable(old_intel_state
, pipe_config
);
6091 if (intel_crtc_has_type(pipe_config
, INTEL_OUTPUT_DP_MST
))
6092 intel_ddi_set_vc_payload_alloc(pipe_config
, true);
6094 assert_vblank_disabled(crtc
);
6095 intel_crtc_vblank_on(pipe_config
);
6097 intel_encoders_enable(crtc
, pipe_config
, old_state
);
6099 if (psl_clkgate_wa
) {
6100 intel_wait_for_vblank(dev_priv
, pipe
);
6101 glk_pipe_scaler_clock_gating_wa(dev_priv
, pipe
, false);
6104 /* If we change the relative order between pipe/planes enabling, we need
6105 * to change the workaround. */
6106 hsw_workaround_pipe
= pipe_config
->hsw_workaround_pipe
;
6107 if (IS_HASWELL(dev_priv
) && hsw_workaround_pipe
!= INVALID_PIPE
) {
6108 intel_wait_for_vblank(dev_priv
, hsw_workaround_pipe
);
6109 intel_wait_for_vblank(dev_priv
, hsw_workaround_pipe
);
6113 static void ironlake_pfit_disable(const struct intel_crtc_state
*old_crtc_state
)
6115 struct intel_crtc
*crtc
= to_intel_crtc(old_crtc_state
->base
.crtc
);
6116 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
6117 enum pipe pipe
= crtc
->pipe
;
6119 /* To avoid upsetting the power well on haswell only disable the pfit if
6120 * it's in use. The hw state code will make sure we get this right. */
6121 if (old_crtc_state
->pch_pfit
.enabled
) {
6122 I915_WRITE(PF_CTL(pipe
), 0);
6123 I915_WRITE(PF_WIN_POS(pipe
), 0);
6124 I915_WRITE(PF_WIN_SZ(pipe
), 0);
6128 static void ironlake_crtc_disable(struct intel_crtc_state
*old_crtc_state
,
6129 struct drm_atomic_state
*old_state
)
6131 struct drm_crtc
*crtc
= old_crtc_state
->base
.crtc
;
6132 struct drm_device
*dev
= crtc
->dev
;
6133 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6134 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6135 int pipe
= intel_crtc
->pipe
;
6138 * Sometimes spurious CPU pipe underruns happen when the
6139 * pipe is already disabled, but FDI RX/TX is still enabled.
6140 * Happens at least with VGA+HDMI cloning. Suppress them.
6142 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
6143 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, false);
6145 intel_encoders_disable(crtc
, old_crtc_state
, old_state
);
6147 drm_crtc_vblank_off(crtc
);
6148 assert_vblank_disabled(crtc
);
6150 intel_disable_pipe(old_crtc_state
);
6152 ironlake_pfit_disable(old_crtc_state
);
6154 if (old_crtc_state
->has_pch_encoder
)
6155 ironlake_fdi_disable(crtc
);
6157 intel_encoders_post_disable(crtc
, old_crtc_state
, old_state
);
6159 if (old_crtc_state
->has_pch_encoder
) {
6160 ironlake_disable_pch_transcoder(dev_priv
, pipe
);
6162 if (HAS_PCH_CPT(dev_priv
)) {
6166 /* disable TRANS_DP_CTL */
6167 reg
= TRANS_DP_CTL(pipe
);
6168 temp
= I915_READ(reg
);
6169 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
|
6170 TRANS_DP_PORT_SEL_MASK
);
6171 temp
|= TRANS_DP_PORT_SEL_NONE
;
6172 I915_WRITE(reg
, temp
);
6174 /* disable DPLL_SEL */
6175 temp
= I915_READ(PCH_DPLL_SEL
);
6176 temp
&= ~(TRANS_DPLL_ENABLE(pipe
) | TRANS_DPLLB_SEL(pipe
));
6177 I915_WRITE(PCH_DPLL_SEL
, temp
);
6180 ironlake_fdi_pll_disable(intel_crtc
);
6183 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
6184 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, true);
6187 static void haswell_crtc_disable(struct intel_crtc_state
*old_crtc_state
,
6188 struct drm_atomic_state
*old_state
)
6190 struct drm_crtc
*crtc
= old_crtc_state
->base
.crtc
;
6191 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
6192 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6193 enum transcoder cpu_transcoder
= old_crtc_state
->cpu_transcoder
;
6195 intel_encoders_disable(crtc
, old_crtc_state
, old_state
);
6197 drm_crtc_vblank_off(crtc
);
6198 assert_vblank_disabled(crtc
);
6200 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
6201 if (!transcoder_is_dsi(cpu_transcoder
))
6202 intel_disable_pipe(old_crtc_state
);
6204 if (intel_crtc_has_type(old_crtc_state
, INTEL_OUTPUT_DP_MST
))
6205 intel_ddi_set_vc_payload_alloc(old_crtc_state
, false);
6207 if (!transcoder_is_dsi(cpu_transcoder
))
6208 intel_ddi_disable_transcoder_func(old_crtc_state
);
6210 intel_dsc_disable(old_crtc_state
);
6212 if (INTEL_GEN(dev_priv
) >= 9)
6213 skylake_scaler_disable(intel_crtc
);
6215 ironlake_pfit_disable(old_crtc_state
);
6217 intel_encoders_post_disable(crtc
, old_crtc_state
, old_state
);
6219 intel_encoders_post_pll_disable(crtc
, old_crtc_state
, old_state
);
6222 static void i9xx_pfit_enable(const struct intel_crtc_state
*crtc_state
)
6224 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
6225 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
6227 if (!crtc_state
->gmch_pfit
.control
)
6231 * The panel fitter should only be adjusted whilst the pipe is disabled,
6232 * according to register description and PRM.
6234 WARN_ON(I915_READ(PFIT_CONTROL
) & PFIT_ENABLE
);
6235 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
6237 I915_WRITE(PFIT_PGM_RATIOS
, crtc_state
->gmch_pfit
.pgm_ratios
);
6238 I915_WRITE(PFIT_CONTROL
, crtc_state
->gmch_pfit
.control
);
6240 /* Border color in case we don't scale up to the full screen. Black by
6241 * default, change to something else for debugging. */
6242 I915_WRITE(BCLRPAT(crtc
->pipe
), 0);
6245 bool intel_port_is_combophy(struct drm_i915_private
*dev_priv
, enum port port
)
6247 if (port
== PORT_NONE
)
6250 if (IS_ELKHARTLAKE(dev_priv
))
6251 return port
<= PORT_C
;
6253 if (INTEL_GEN(dev_priv
) >= 11)
6254 return port
<= PORT_B
;
6259 bool intel_port_is_tc(struct drm_i915_private
*dev_priv
, enum port port
)
6261 if (INTEL_GEN(dev_priv
) >= 11 && !IS_ELKHARTLAKE(dev_priv
))
6262 return port
>= PORT_C
&& port
<= PORT_F
;
6267 enum tc_port
intel_port_to_tc(struct drm_i915_private
*dev_priv
, enum port port
)
6269 if (!intel_port_is_tc(dev_priv
, port
))
6270 return PORT_TC_NONE
;
6272 return port
- PORT_C
;
6275 enum intel_display_power_domain
intel_port_to_power_domain(enum port port
)
6279 return POWER_DOMAIN_PORT_DDI_A_LANES
;
6281 return POWER_DOMAIN_PORT_DDI_B_LANES
;
6283 return POWER_DOMAIN_PORT_DDI_C_LANES
;
6285 return POWER_DOMAIN_PORT_DDI_D_LANES
;
6287 return POWER_DOMAIN_PORT_DDI_E_LANES
;
6289 return POWER_DOMAIN_PORT_DDI_F_LANES
;
6292 return POWER_DOMAIN_PORT_OTHER
;
6296 enum intel_display_power_domain
6297 intel_aux_power_domain(struct intel_digital_port
*dig_port
)
6299 switch (dig_port
->aux_ch
) {
6301 return POWER_DOMAIN_AUX_A
;
6303 return POWER_DOMAIN_AUX_B
;
6305 return POWER_DOMAIN_AUX_C
;
6307 return POWER_DOMAIN_AUX_D
;
6309 return POWER_DOMAIN_AUX_E
;
6311 return POWER_DOMAIN_AUX_F
;
6313 MISSING_CASE(dig_port
->aux_ch
);
6314 return POWER_DOMAIN_AUX_A
;
6318 static u64
get_crtc_power_domains(struct drm_crtc
*crtc
,
6319 struct intel_crtc_state
*crtc_state
)
6321 struct drm_device
*dev
= crtc
->dev
;
6322 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6323 struct drm_encoder
*encoder
;
6324 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6325 enum pipe pipe
= intel_crtc
->pipe
;
6327 enum transcoder transcoder
= crtc_state
->cpu_transcoder
;
6329 if (!crtc_state
->base
.active
)
6332 mask
= BIT_ULL(POWER_DOMAIN_PIPE(pipe
));
6333 mask
|= BIT_ULL(POWER_DOMAIN_TRANSCODER(transcoder
));
6334 if (crtc_state
->pch_pfit
.enabled
||
6335 crtc_state
->pch_pfit
.force_thru
)
6336 mask
|= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe
));
6338 drm_for_each_encoder_mask(encoder
, dev
, crtc_state
->base
.encoder_mask
) {
6339 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
6341 mask
|= BIT_ULL(intel_encoder
->power_domain
);
6344 if (HAS_DDI(dev_priv
) && crtc_state
->has_audio
)
6345 mask
|= BIT_ULL(POWER_DOMAIN_AUDIO
);
6347 if (crtc_state
->shared_dpll
)
6348 mask
|= BIT_ULL(POWER_DOMAIN_PLLS
);
6354 modeset_get_crtc_power_domains(struct drm_crtc
*crtc
,
6355 struct intel_crtc_state
*crtc_state
)
6357 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
6358 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6359 enum intel_display_power_domain domain
;
6360 u64 domains
, new_domains
, old_domains
;
6362 old_domains
= intel_crtc
->enabled_power_domains
;
6363 intel_crtc
->enabled_power_domains
= new_domains
=
6364 get_crtc_power_domains(crtc
, crtc_state
);
6366 domains
= new_domains
& ~old_domains
;
6368 for_each_power_domain(domain
, domains
)
6369 intel_display_power_get(dev_priv
, domain
);
6371 return old_domains
& ~new_domains
;
6374 static void modeset_put_power_domains(struct drm_i915_private
*dev_priv
,
6377 enum intel_display_power_domain domain
;
6379 for_each_power_domain(domain
, domains
)
6380 intel_display_power_put_unchecked(dev_priv
, domain
);
6383 static void valleyview_crtc_enable(struct intel_crtc_state
*pipe_config
,
6384 struct drm_atomic_state
*old_state
)
6386 struct intel_atomic_state
*old_intel_state
=
6387 to_intel_atomic_state(old_state
);
6388 struct drm_crtc
*crtc
= pipe_config
->base
.crtc
;
6389 struct drm_device
*dev
= crtc
->dev
;
6390 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6391 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6392 int pipe
= intel_crtc
->pipe
;
6394 if (WARN_ON(intel_crtc
->active
))
6397 if (intel_crtc_has_dp_encoder(pipe_config
))
6398 intel_dp_set_m_n(pipe_config
, M1_N1
);
6400 intel_set_pipe_timings(pipe_config
);
6401 intel_set_pipe_src_size(pipe_config
);
6403 if (IS_CHERRYVIEW(dev_priv
) && pipe
== PIPE_B
) {
6404 I915_WRITE(CHV_BLEND(pipe
), CHV_BLEND_LEGACY
);
6405 I915_WRITE(CHV_CANVAS(pipe
), 0);
6408 i9xx_set_pipeconf(pipe_config
);
6410 intel_crtc
->active
= true;
6412 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
6414 intel_encoders_pre_pll_enable(crtc
, pipe_config
, old_state
);
6416 if (IS_CHERRYVIEW(dev_priv
)) {
6417 chv_prepare_pll(intel_crtc
, pipe_config
);
6418 chv_enable_pll(intel_crtc
, pipe_config
);
6420 vlv_prepare_pll(intel_crtc
, pipe_config
);
6421 vlv_enable_pll(intel_crtc
, pipe_config
);
6424 intel_encoders_pre_enable(crtc
, pipe_config
, old_state
);
6426 i9xx_pfit_enable(pipe_config
);
6428 intel_color_load_luts(pipe_config
);
6429 intel_color_commit(pipe_config
);
6430 /* update DSPCNTR to configure gamma for pipe bottom color */
6431 intel_disable_primary_plane(pipe_config
);
6433 dev_priv
->display
.initial_watermarks(old_intel_state
,
6435 intel_enable_pipe(pipe_config
);
6437 assert_vblank_disabled(crtc
);
6438 intel_crtc_vblank_on(pipe_config
);
6440 intel_encoders_enable(crtc
, pipe_config
, old_state
);
6443 static void i9xx_set_pll_dividers(const struct intel_crtc_state
*crtc_state
)
6445 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
6446 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
6448 I915_WRITE(FP0(crtc
->pipe
), crtc_state
->dpll_hw_state
.fp0
);
6449 I915_WRITE(FP1(crtc
->pipe
), crtc_state
->dpll_hw_state
.fp1
);
6452 static void i9xx_crtc_enable(struct intel_crtc_state
*pipe_config
,
6453 struct drm_atomic_state
*old_state
)
6455 struct intel_atomic_state
*old_intel_state
=
6456 to_intel_atomic_state(old_state
);
6457 struct drm_crtc
*crtc
= pipe_config
->base
.crtc
;
6458 struct drm_device
*dev
= crtc
->dev
;
6459 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6460 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6461 enum pipe pipe
= intel_crtc
->pipe
;
6463 if (WARN_ON(intel_crtc
->active
))
6466 i9xx_set_pll_dividers(pipe_config
);
6468 if (intel_crtc_has_dp_encoder(pipe_config
))
6469 intel_dp_set_m_n(pipe_config
, M1_N1
);
6471 intel_set_pipe_timings(pipe_config
);
6472 intel_set_pipe_src_size(pipe_config
);
6474 i9xx_set_pipeconf(pipe_config
);
6476 intel_crtc
->active
= true;
6478 if (!IS_GEN(dev_priv
, 2))
6479 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
6481 intel_encoders_pre_enable(crtc
, pipe_config
, old_state
);
6483 i9xx_enable_pll(intel_crtc
, pipe_config
);
6485 i9xx_pfit_enable(pipe_config
);
6487 intel_color_load_luts(pipe_config
);
6488 intel_color_commit(pipe_config
);
6489 /* update DSPCNTR to configure gamma for pipe bottom color */
6490 intel_disable_primary_plane(pipe_config
);
6492 if (dev_priv
->display
.initial_watermarks
!= NULL
)
6493 dev_priv
->display
.initial_watermarks(old_intel_state
,
6496 intel_update_watermarks(intel_crtc
);
6497 intel_enable_pipe(pipe_config
);
6499 assert_vblank_disabled(crtc
);
6500 intel_crtc_vblank_on(pipe_config
);
6502 intel_encoders_enable(crtc
, pipe_config
, old_state
);
6505 static void i9xx_pfit_disable(const struct intel_crtc_state
*old_crtc_state
)
6507 struct intel_crtc
*crtc
= to_intel_crtc(old_crtc_state
->base
.crtc
);
6508 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
6510 if (!old_crtc_state
->gmch_pfit
.control
)
6513 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
6515 DRM_DEBUG_KMS("disabling pfit, current: 0x%08x\n",
6516 I915_READ(PFIT_CONTROL
));
6517 I915_WRITE(PFIT_CONTROL
, 0);
6520 static void i9xx_crtc_disable(struct intel_crtc_state
*old_crtc_state
,
6521 struct drm_atomic_state
*old_state
)
6523 struct drm_crtc
*crtc
= old_crtc_state
->base
.crtc
;
6524 struct drm_device
*dev
= crtc
->dev
;
6525 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6526 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6527 int pipe
= intel_crtc
->pipe
;
6530 * On gen2 planes are double buffered but the pipe isn't, so we must
6531 * wait for planes to fully turn off before disabling the pipe.
6533 if (IS_GEN(dev_priv
, 2))
6534 intel_wait_for_vblank(dev_priv
, pipe
);
6536 intel_encoders_disable(crtc
, old_crtc_state
, old_state
);
6538 drm_crtc_vblank_off(crtc
);
6539 assert_vblank_disabled(crtc
);
6541 intel_disable_pipe(old_crtc_state
);
6543 i9xx_pfit_disable(old_crtc_state
);
6545 intel_encoders_post_disable(crtc
, old_crtc_state
, old_state
);
6547 if (!intel_crtc_has_type(old_crtc_state
, INTEL_OUTPUT_DSI
)) {
6548 if (IS_CHERRYVIEW(dev_priv
))
6549 chv_disable_pll(dev_priv
, pipe
);
6550 else if (IS_VALLEYVIEW(dev_priv
))
6551 vlv_disable_pll(dev_priv
, pipe
);
6553 i9xx_disable_pll(old_crtc_state
);
6556 intel_encoders_post_pll_disable(crtc
, old_crtc_state
, old_state
);
6558 if (!IS_GEN(dev_priv
, 2))
6559 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
6561 if (!dev_priv
->display
.initial_watermarks
)
6562 intel_update_watermarks(intel_crtc
);
6564 /* clock the pipe down to 640x480@60 to potentially save power */
6565 if (IS_I830(dev_priv
))
6566 i830_enable_pipe(dev_priv
, pipe
);
6569 static void intel_crtc_disable_noatomic(struct drm_crtc
*crtc
,
6570 struct drm_modeset_acquire_ctx
*ctx
)
6572 struct intel_encoder
*encoder
;
6573 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6574 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
6575 enum intel_display_power_domain domain
;
6576 struct intel_plane
*plane
;
6578 struct drm_atomic_state
*state
;
6579 struct intel_crtc_state
*crtc_state
;
6582 if (!intel_crtc
->active
)
6585 for_each_intel_plane_on_crtc(&dev_priv
->drm
, intel_crtc
, plane
) {
6586 const struct intel_plane_state
*plane_state
=
6587 to_intel_plane_state(plane
->base
.state
);
6589 if (plane_state
->base
.visible
)
6590 intel_plane_disable_noatomic(intel_crtc
, plane
);
6593 state
= drm_atomic_state_alloc(crtc
->dev
);
6595 DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory",
6596 crtc
->base
.id
, crtc
->name
);
6600 state
->acquire_ctx
= ctx
;
6602 /* Everything's already locked, -EDEADLK can't happen. */
6603 crtc_state
= intel_atomic_get_crtc_state(state
, intel_crtc
);
6604 ret
= drm_atomic_add_affected_connectors(state
, crtc
);
6606 WARN_ON(IS_ERR(crtc_state
) || ret
);
6608 dev_priv
->display
.crtc_disable(crtc_state
, state
);
6610 drm_atomic_state_put(state
);
6612 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
6613 crtc
->base
.id
, crtc
->name
);
6615 WARN_ON(drm_atomic_set_mode_for_crtc(crtc
->state
, NULL
) < 0);
6616 crtc
->state
->active
= false;
6617 intel_crtc
->active
= false;
6618 crtc
->enabled
= false;
6619 crtc
->state
->connector_mask
= 0;
6620 crtc
->state
->encoder_mask
= 0;
6622 for_each_encoder_on_crtc(crtc
->dev
, crtc
, encoder
)
6623 encoder
->base
.crtc
= NULL
;
6625 intel_fbc_disable(intel_crtc
);
6626 intel_update_watermarks(intel_crtc
);
6627 intel_disable_shared_dpll(to_intel_crtc_state(crtc
->state
));
6629 domains
= intel_crtc
->enabled_power_domains
;
6630 for_each_power_domain(domain
, domains
)
6631 intel_display_power_put_unchecked(dev_priv
, domain
);
6632 intel_crtc
->enabled_power_domains
= 0;
6634 dev_priv
->active_crtcs
&= ~(1 << intel_crtc
->pipe
);
6635 dev_priv
->min_cdclk
[intel_crtc
->pipe
] = 0;
6636 dev_priv
->min_voltage_level
[intel_crtc
->pipe
] = 0;
6640 * turn all crtc's off, but do not adjust state
6641 * This has to be paired with a call to intel_modeset_setup_hw_state.
6643 int intel_display_suspend(struct drm_device
*dev
)
6645 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6646 struct drm_atomic_state
*state
;
6649 state
= drm_atomic_helper_suspend(dev
);
6650 ret
= PTR_ERR_OR_ZERO(state
);
6652 DRM_ERROR("Suspending crtc's failed with %i\n", ret
);
6654 dev_priv
->modeset_restore_state
= state
;
6658 void intel_encoder_destroy(struct drm_encoder
*encoder
)
6660 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
6662 drm_encoder_cleanup(encoder
);
6663 kfree(intel_encoder
);
6666 /* Cross check the actual hw state with our own modeset state tracking (and it's
6667 * internal consistency). */
6668 static void intel_connector_verify_state(struct drm_crtc_state
*crtc_state
,
6669 struct drm_connector_state
*conn_state
)
6671 struct intel_connector
*connector
= to_intel_connector(conn_state
->connector
);
6673 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6674 connector
->base
.base
.id
,
6675 connector
->base
.name
);
6677 if (connector
->get_hw_state(connector
)) {
6678 struct intel_encoder
*encoder
= connector
->encoder
;
6680 I915_STATE_WARN(!crtc_state
,
6681 "connector enabled without attached crtc\n");
6686 I915_STATE_WARN(!crtc_state
->active
,
6687 "connector is active, but attached crtc isn't\n");
6689 if (!encoder
|| encoder
->type
== INTEL_OUTPUT_DP_MST
)
6692 I915_STATE_WARN(conn_state
->best_encoder
!= &encoder
->base
,
6693 "atomic encoder doesn't match attached encoder\n");
6695 I915_STATE_WARN(conn_state
->crtc
!= encoder
->base
.crtc
,
6696 "attached encoder crtc differs from connector crtc\n");
6698 I915_STATE_WARN(crtc_state
&& crtc_state
->active
,
6699 "attached crtc is active, but connector isn't\n");
6700 I915_STATE_WARN(!crtc_state
&& conn_state
->best_encoder
,
6701 "best encoder set without crtc!\n");
6705 static int pipe_required_fdi_lanes(struct intel_crtc_state
*crtc_state
)
6707 if (crtc_state
->base
.enable
&& crtc_state
->has_pch_encoder
)
6708 return crtc_state
->fdi_lanes
;
6713 static int ironlake_check_fdi_lanes(struct drm_device
*dev
, enum pipe pipe
,
6714 struct intel_crtc_state
*pipe_config
)
6716 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6717 struct drm_atomic_state
*state
= pipe_config
->base
.state
;
6718 struct intel_crtc
*other_crtc
;
6719 struct intel_crtc_state
*other_crtc_state
;
6721 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6722 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6723 if (pipe_config
->fdi_lanes
> 4) {
6724 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6725 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6729 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
6730 if (pipe_config
->fdi_lanes
> 2) {
6731 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6732 pipe_config
->fdi_lanes
);
6739 if (INTEL_INFO(dev_priv
)->num_pipes
== 2)
6742 /* Ivybridge 3 pipe is really complicated */
6747 if (pipe_config
->fdi_lanes
<= 2)
6750 other_crtc
= intel_get_crtc_for_pipe(dev_priv
, PIPE_C
);
6752 intel_atomic_get_crtc_state(state
, other_crtc
);
6753 if (IS_ERR(other_crtc_state
))
6754 return PTR_ERR(other_crtc_state
);
6756 if (pipe_required_fdi_lanes(other_crtc_state
) > 0) {
6757 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6758 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6763 if (pipe_config
->fdi_lanes
> 2) {
6764 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6765 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6769 other_crtc
= intel_get_crtc_for_pipe(dev_priv
, PIPE_B
);
6771 intel_atomic_get_crtc_state(state
, other_crtc
);
6772 if (IS_ERR(other_crtc_state
))
6773 return PTR_ERR(other_crtc_state
);
6775 if (pipe_required_fdi_lanes(other_crtc_state
) > 2) {
6776 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6786 static int ironlake_fdi_compute_config(struct intel_crtc
*intel_crtc
,
6787 struct intel_crtc_state
*pipe_config
)
6789 struct drm_device
*dev
= intel_crtc
->base
.dev
;
6790 const struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
6791 int lane
, link_bw
, fdi_dotclock
, ret
;
6792 bool needs_recompute
= false;
6795 /* FDI is a binary signal running at ~2.7GHz, encoding
6796 * each output octet as 10 bits. The actual frequency
6797 * is stored as a divider into a 100MHz clock, and the
6798 * mode pixel clock is stored in units of 1KHz.
6799 * Hence the bw of each lane in terms of the mode signal
6802 link_bw
= intel_fdi_link_freq(to_i915(dev
), pipe_config
);
6804 fdi_dotclock
= adjusted_mode
->crtc_clock
;
6806 lane
= ironlake_get_lanes_required(fdi_dotclock
, link_bw
,
6807 pipe_config
->pipe_bpp
);
6809 pipe_config
->fdi_lanes
= lane
;
6811 intel_link_compute_m_n(pipe_config
->pipe_bpp
, lane
, fdi_dotclock
,
6812 link_bw
, &pipe_config
->fdi_m_n
, false);
6814 ret
= ironlake_check_fdi_lanes(dev
, intel_crtc
->pipe
, pipe_config
);
6815 if (ret
== -EDEADLK
)
6818 if (ret
== -EINVAL
&& pipe_config
->pipe_bpp
> 6*3) {
6819 pipe_config
->pipe_bpp
-= 2*3;
6820 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6821 pipe_config
->pipe_bpp
);
6822 needs_recompute
= true;
6823 pipe_config
->bw_constrained
= true;
6828 if (needs_recompute
)
6834 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state
*crtc_state
)
6836 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
6837 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
6839 /* IPS only exists on ULT machines and is tied to pipe A. */
6840 if (!hsw_crtc_supports_ips(crtc
))
6843 if (!i915_modparams
.enable_ips
)
6846 if (crtc_state
->pipe_bpp
> 24)
6850 * We compare against max which means we must take
6851 * the increased cdclk requirement into account when
6852 * calculating the new cdclk.
6854 * Should measure whether using a lower cdclk w/o IPS
6856 if (IS_BROADWELL(dev_priv
) &&
6857 crtc_state
->pixel_rate
> dev_priv
->max_cdclk_freq
* 95 / 100)
6863 static bool hsw_compute_ips_config(struct intel_crtc_state
*crtc_state
)
6865 struct drm_i915_private
*dev_priv
=
6866 to_i915(crtc_state
->base
.crtc
->dev
);
6867 struct intel_atomic_state
*intel_state
=
6868 to_intel_atomic_state(crtc_state
->base
.state
);
6870 if (!hsw_crtc_state_ips_capable(crtc_state
))
6874 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
6875 * enabled and disabled dynamically based on package C states,
6876 * user space can't make reliable use of the CRCs, so let's just
6877 * completely disable it.
6879 if (crtc_state
->crc_enabled
)
6882 /* IPS should be fine as long as at least one plane is enabled. */
6883 if (!(crtc_state
->active_planes
& ~BIT(PLANE_CURSOR
)))
6886 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
6887 if (IS_BROADWELL(dev_priv
) &&
6888 crtc_state
->pixel_rate
> intel_state
->cdclk
.logical
.cdclk
* 95 / 100)
6894 static bool intel_crtc_supports_double_wide(const struct intel_crtc
*crtc
)
6896 const struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
6898 /* GDG double wide on either pipe, otherwise pipe A only */
6899 return INTEL_GEN(dev_priv
) < 4 &&
6900 (crtc
->pipe
== PIPE_A
|| IS_I915G(dev_priv
));
6903 static u32
ilk_pipe_pixel_rate(const struct intel_crtc_state
*pipe_config
)
6907 pixel_rate
= pipe_config
->base
.adjusted_mode
.crtc_clock
;
6910 * We only use IF-ID interlacing. If we ever use
6911 * PF-ID we'll need to adjust the pixel_rate here.
6914 if (pipe_config
->pch_pfit
.enabled
) {
6915 u64 pipe_w
, pipe_h
, pfit_w
, pfit_h
;
6916 u32 pfit_size
= pipe_config
->pch_pfit
.size
;
6918 pipe_w
= pipe_config
->pipe_src_w
;
6919 pipe_h
= pipe_config
->pipe_src_h
;
6921 pfit_w
= (pfit_size
>> 16) & 0xFFFF;
6922 pfit_h
= pfit_size
& 0xFFFF;
6923 if (pipe_w
< pfit_w
)
6925 if (pipe_h
< pfit_h
)
6928 if (WARN_ON(!pfit_w
|| !pfit_h
))
6931 pixel_rate
= div_u64((u64
)pixel_rate
* pipe_w
* pipe_h
,
6938 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state
*crtc_state
)
6940 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->base
.crtc
->dev
);
6942 if (HAS_GMCH(dev_priv
))
6943 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
6944 crtc_state
->pixel_rate
=
6945 crtc_state
->base
.adjusted_mode
.crtc_clock
;
6947 crtc_state
->pixel_rate
=
6948 ilk_pipe_pixel_rate(crtc_state
);
6951 static int intel_crtc_compute_config(struct intel_crtc
*crtc
,
6952 struct intel_crtc_state
*pipe_config
)
6954 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
6955 const struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
6956 int clock_limit
= dev_priv
->max_dotclk_freq
;
6958 if (INTEL_GEN(dev_priv
) < 4) {
6959 clock_limit
= dev_priv
->max_cdclk_freq
* 9 / 10;
6962 * Enable double wide mode when the dot clock
6963 * is > 90% of the (display) core speed.
6965 if (intel_crtc_supports_double_wide(crtc
) &&
6966 adjusted_mode
->crtc_clock
> clock_limit
) {
6967 clock_limit
= dev_priv
->max_dotclk_freq
;
6968 pipe_config
->double_wide
= true;
6972 if (adjusted_mode
->crtc_clock
> clock_limit
) {
6973 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6974 adjusted_mode
->crtc_clock
, clock_limit
,
6975 yesno(pipe_config
->double_wide
));
6979 if ((pipe_config
->output_format
== INTEL_OUTPUT_FORMAT_YCBCR420
||
6980 pipe_config
->output_format
== INTEL_OUTPUT_FORMAT_YCBCR444
) &&
6981 pipe_config
->base
.ctm
) {
6983 * There is only one pipe CSC unit per pipe, and we need that
6984 * for output conversion from RGB->YCBCR. So if CTM is already
6985 * applied we can't support YCBCR420 output.
6987 DRM_DEBUG_KMS("YCBCR420 and CTM together are not possible\n");
6992 * Pipe horizontal size must be even in:
6994 * - LVDS dual channel mode
6995 * - Double wide pipe
6997 if (pipe_config
->pipe_src_w
& 1) {
6998 if (pipe_config
->double_wide
) {
6999 DRM_DEBUG_KMS("Odd pipe source width not supported with double wide pipe\n");
7003 if (intel_crtc_has_type(pipe_config
, INTEL_OUTPUT_LVDS
) &&
7004 intel_is_dual_link_lvds(dev_priv
)) {
7005 DRM_DEBUG_KMS("Odd pipe source width not supported with dual link LVDS\n");
7010 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
7011 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
7013 if ((INTEL_GEN(dev_priv
) > 4 || IS_G4X(dev_priv
)) &&
7014 adjusted_mode
->crtc_hsync_start
== adjusted_mode
->crtc_hdisplay
)
7017 intel_crtc_compute_pixel_rate(pipe_config
);
7019 if (pipe_config
->has_pch_encoder
)
7020 return ironlake_fdi_compute_config(crtc
, pipe_config
);
7026 intel_reduce_m_n_ratio(u32
*num
, u32
*den
)
7028 while (*num
> DATA_LINK_M_N_MASK
||
7029 *den
> DATA_LINK_M_N_MASK
) {
7035 static void compute_m_n(unsigned int m
, unsigned int n
,
7036 u32
*ret_m
, u32
*ret_n
,
7040 * Several DP dongles in particular seem to be fussy about
7041 * too large link M/N values. Give N value as 0x8000 that
7042 * should be acceptable by specific devices. 0x8000 is the
7043 * specified fixed N value for asynchronous clock mode,
7044 * which the devices expect also in synchronous clock mode.
7049 *ret_n
= min_t(unsigned int, roundup_pow_of_two(n
), DATA_LINK_N_MAX
);
7051 *ret_m
= div_u64((u64
)m
* *ret_n
, n
);
7052 intel_reduce_m_n_ratio(ret_m
, ret_n
);
7056 intel_link_compute_m_n(u16 bits_per_pixel
, int nlanes
,
7057 int pixel_clock
, int link_clock
,
7058 struct intel_link_m_n
*m_n
,
7063 compute_m_n(bits_per_pixel
* pixel_clock
,
7064 link_clock
* nlanes
* 8,
7065 &m_n
->gmch_m
, &m_n
->gmch_n
,
7068 compute_m_n(pixel_clock
, link_clock
,
7069 &m_n
->link_m
, &m_n
->link_n
,
7073 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
7075 if (i915_modparams
.panel_use_ssc
>= 0)
7076 return i915_modparams
.panel_use_ssc
!= 0;
7077 return dev_priv
->vbt
.lvds_use_ssc
7078 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
7081 static u32
pnv_dpll_compute_fp(struct dpll
*dpll
)
7083 return (1 << dpll
->n
) << 16 | dpll
->m2
;
7086 static u32
i9xx_dpll_compute_fp(struct dpll
*dpll
)
7088 return dpll
->n
<< 16 | dpll
->m1
<< 8 | dpll
->m2
;
7091 static void i9xx_update_pll_dividers(struct intel_crtc
*crtc
,
7092 struct intel_crtc_state
*crtc_state
,
7093 struct dpll
*reduced_clock
)
7095 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
7098 if (IS_PINEVIEW(dev_priv
)) {
7099 fp
= pnv_dpll_compute_fp(&crtc_state
->dpll
);
7101 fp2
= pnv_dpll_compute_fp(reduced_clock
);
7103 fp
= i9xx_dpll_compute_fp(&crtc_state
->dpll
);
7105 fp2
= i9xx_dpll_compute_fp(reduced_clock
);
7108 crtc_state
->dpll_hw_state
.fp0
= fp
;
7110 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
7112 crtc_state
->dpll_hw_state
.fp1
= fp2
;
7114 crtc_state
->dpll_hw_state
.fp1
= fp
;
7118 static void vlv_pllb_recal_opamp(struct drm_i915_private
*dev_priv
, enum pipe
7124 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7125 * and set it to a reasonable value instead.
7127 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
7128 reg_val
&= 0xffffff00;
7129 reg_val
|= 0x00000030;
7130 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
7132 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
7133 reg_val
&= 0x00ffffff;
7134 reg_val
|= 0x8c000000;
7135 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
7137 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
7138 reg_val
&= 0xffffff00;
7139 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
7141 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
7142 reg_val
&= 0x00ffffff;
7143 reg_val
|= 0xb0000000;
7144 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
7147 static void intel_pch_transcoder_set_m_n(const struct intel_crtc_state
*crtc_state
,
7148 const struct intel_link_m_n
*m_n
)
7150 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
7151 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
7152 enum pipe pipe
= crtc
->pipe
;
7154 I915_WRITE(PCH_TRANS_DATA_M1(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
7155 I915_WRITE(PCH_TRANS_DATA_N1(pipe
), m_n
->gmch_n
);
7156 I915_WRITE(PCH_TRANS_LINK_M1(pipe
), m_n
->link_m
);
7157 I915_WRITE(PCH_TRANS_LINK_N1(pipe
), m_n
->link_n
);
7160 static bool transcoder_has_m2_n2(struct drm_i915_private
*dev_priv
,
7161 enum transcoder transcoder
)
7163 if (IS_HASWELL(dev_priv
))
7164 return transcoder
== TRANSCODER_EDP
;
7167 * Strictly speaking some registers are available before
7168 * gen7, but we only support DRRS on gen7+
7170 return IS_GEN(dev_priv
, 7) || IS_CHERRYVIEW(dev_priv
);
7173 static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state
*crtc_state
,
7174 const struct intel_link_m_n
*m_n
,
7175 const struct intel_link_m_n
*m2_n2
)
7177 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
7178 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
7179 enum pipe pipe
= crtc
->pipe
;
7180 enum transcoder transcoder
= crtc_state
->cpu_transcoder
;
7182 if (INTEL_GEN(dev_priv
) >= 5) {
7183 I915_WRITE(PIPE_DATA_M1(transcoder
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
7184 I915_WRITE(PIPE_DATA_N1(transcoder
), m_n
->gmch_n
);
7185 I915_WRITE(PIPE_LINK_M1(transcoder
), m_n
->link_m
);
7186 I915_WRITE(PIPE_LINK_N1(transcoder
), m_n
->link_n
);
7188 * M2_N2 registers are set only if DRRS is supported
7189 * (to make sure the registers are not unnecessarily accessed).
7191 if (m2_n2
&& crtc_state
->has_drrs
&&
7192 transcoder_has_m2_n2(dev_priv
, transcoder
)) {
7193 I915_WRITE(PIPE_DATA_M2(transcoder
),
7194 TU_SIZE(m2_n2
->tu
) | m2_n2
->gmch_m
);
7195 I915_WRITE(PIPE_DATA_N2(transcoder
), m2_n2
->gmch_n
);
7196 I915_WRITE(PIPE_LINK_M2(transcoder
), m2_n2
->link_m
);
7197 I915_WRITE(PIPE_LINK_N2(transcoder
), m2_n2
->link_n
);
7200 I915_WRITE(PIPE_DATA_M_G4X(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
7201 I915_WRITE(PIPE_DATA_N_G4X(pipe
), m_n
->gmch_n
);
7202 I915_WRITE(PIPE_LINK_M_G4X(pipe
), m_n
->link_m
);
7203 I915_WRITE(PIPE_LINK_N_G4X(pipe
), m_n
->link_n
);
7207 void intel_dp_set_m_n(const struct intel_crtc_state
*crtc_state
, enum link_m_n_set m_n
)
7209 const struct intel_link_m_n
*dp_m_n
, *dp_m2_n2
= NULL
;
7212 dp_m_n
= &crtc_state
->dp_m_n
;
7213 dp_m2_n2
= &crtc_state
->dp_m2_n2
;
7214 } else if (m_n
== M2_N2
) {
7217 * M2_N2 registers are not supported. Hence m2_n2 divider value
7218 * needs to be programmed into M1_N1.
7220 dp_m_n
= &crtc_state
->dp_m2_n2
;
7222 DRM_ERROR("Unsupported divider value\n");
7226 if (crtc_state
->has_pch_encoder
)
7227 intel_pch_transcoder_set_m_n(crtc_state
, &crtc_state
->dp_m_n
);
7229 intel_cpu_transcoder_set_m_n(crtc_state
, dp_m_n
, dp_m2_n2
);
7232 static void vlv_compute_dpll(struct intel_crtc
*crtc
,
7233 struct intel_crtc_state
*pipe_config
)
7235 pipe_config
->dpll_hw_state
.dpll
= DPLL_INTEGRATED_REF_CLK_VLV
|
7236 DPLL_REF_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
;
7237 if (crtc
->pipe
!= PIPE_A
)
7238 pipe_config
->dpll_hw_state
.dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
7240 /* DPLL not used with DSI, but still need the rest set up */
7241 if (!intel_crtc_has_type(pipe_config
, INTEL_OUTPUT_DSI
))
7242 pipe_config
->dpll_hw_state
.dpll
|= DPLL_VCO_ENABLE
|
7243 DPLL_EXT_BUFFER_ENABLE_VLV
;
7245 pipe_config
->dpll_hw_state
.dpll_md
=
7246 (pipe_config
->pixel_multiplier
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
7249 static void chv_compute_dpll(struct intel_crtc
*crtc
,
7250 struct intel_crtc_state
*pipe_config
)
7252 pipe_config
->dpll_hw_state
.dpll
= DPLL_SSC_REF_CLK_CHV
|
7253 DPLL_REF_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
;
7254 if (crtc
->pipe
!= PIPE_A
)
7255 pipe_config
->dpll_hw_state
.dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
7257 /* DPLL not used with DSI, but still need the rest set up */
7258 if (!intel_crtc_has_type(pipe_config
, INTEL_OUTPUT_DSI
))
7259 pipe_config
->dpll_hw_state
.dpll
|= DPLL_VCO_ENABLE
;
7261 pipe_config
->dpll_hw_state
.dpll_md
=
7262 (pipe_config
->pixel_multiplier
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
7265 static void vlv_prepare_pll(struct intel_crtc
*crtc
,
7266 const struct intel_crtc_state
*pipe_config
)
7268 struct drm_device
*dev
= crtc
->base
.dev
;
7269 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7270 enum pipe pipe
= crtc
->pipe
;
7272 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
7273 u32 coreclk
, reg_val
;
7276 I915_WRITE(DPLL(pipe
),
7277 pipe_config
->dpll_hw_state
.dpll
&
7278 ~(DPLL_VCO_ENABLE
| DPLL_EXT_BUFFER_ENABLE_VLV
));
7280 /* No need to actually set up the DPLL with DSI */
7281 if ((pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
) == 0)
7284 vlv_dpio_get(dev_priv
);
7286 bestn
= pipe_config
->dpll
.n
;
7287 bestm1
= pipe_config
->dpll
.m1
;
7288 bestm2
= pipe_config
->dpll
.m2
;
7289 bestp1
= pipe_config
->dpll
.p1
;
7290 bestp2
= pipe_config
->dpll
.p2
;
7292 /* See eDP HDMI DPIO driver vbios notes doc */
7294 /* PLL B needs special handling */
7296 vlv_pllb_recal_opamp(dev_priv
, pipe
);
7298 /* Set up Tx target for periodic Rcomp update */
7299 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9_BCAST
, 0x0100000f);
7301 /* Disable target IRef on PLL */
7302 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW8(pipe
));
7303 reg_val
&= 0x00ffffff;
7304 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW8(pipe
), reg_val
);
7306 /* Disable fast lock */
7307 vlv_dpio_write(dev_priv
, pipe
, VLV_CMN_DW0
, 0x610);
7309 /* Set idtafcrecal before PLL is enabled */
7310 mdiv
= ((bestm1
<< DPIO_M1DIV_SHIFT
) | (bestm2
& DPIO_M2DIV_MASK
));
7311 mdiv
|= ((bestp1
<< DPIO_P1_SHIFT
) | (bestp2
<< DPIO_P2_SHIFT
));
7312 mdiv
|= ((bestn
<< DPIO_N_SHIFT
));
7313 mdiv
|= (1 << DPIO_K_SHIFT
);
7316 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7317 * but we don't support that).
7318 * Note: don't use the DAC post divider as it seems unstable.
7320 mdiv
|= (DPIO_POST_DIV_HDMIDP
<< DPIO_POST_DIV_SHIFT
);
7321 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
7323 mdiv
|= DPIO_ENABLE_CALIBRATION
;
7324 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
7326 /* Set HBR and RBR LPF coefficients */
7327 if (pipe_config
->port_clock
== 162000 ||
7328 intel_crtc_has_type(pipe_config
, INTEL_OUTPUT_ANALOG
) ||
7329 intel_crtc_has_type(pipe_config
, INTEL_OUTPUT_HDMI
))
7330 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
7333 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
7336 if (intel_crtc_has_dp_encoder(pipe_config
)) {
7337 /* Use SSC source */
7339 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
7342 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
7344 } else { /* HDMI or VGA */
7345 /* Use bend source */
7347 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
7350 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
7354 coreclk
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW7(pipe
));
7355 coreclk
= (coreclk
& 0x0000ff00) | 0x01c00000;
7356 if (intel_crtc_has_dp_encoder(pipe_config
))
7357 coreclk
|= 0x01000000;
7358 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW7(pipe
), coreclk
);
7360 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW11(pipe
), 0x87871000);
7362 vlv_dpio_put(dev_priv
);
7365 static void chv_prepare_pll(struct intel_crtc
*crtc
,
7366 const struct intel_crtc_state
*pipe_config
)
7368 struct drm_device
*dev
= crtc
->base
.dev
;
7369 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7370 enum pipe pipe
= crtc
->pipe
;
7371 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
7372 u32 loopfilter
, tribuf_calcntr
;
7373 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
, bestm2_frac
;
7377 /* Enable Refclk and SSC */
7378 I915_WRITE(DPLL(pipe
),
7379 pipe_config
->dpll_hw_state
.dpll
& ~DPLL_VCO_ENABLE
);
7381 /* No need to actually set up the DPLL with DSI */
7382 if ((pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
) == 0)
7385 bestn
= pipe_config
->dpll
.n
;
7386 bestm2_frac
= pipe_config
->dpll
.m2
& 0x3fffff;
7387 bestm1
= pipe_config
->dpll
.m1
;
7388 bestm2
= pipe_config
->dpll
.m2
>> 22;
7389 bestp1
= pipe_config
->dpll
.p1
;
7390 bestp2
= pipe_config
->dpll
.p2
;
7391 vco
= pipe_config
->dpll
.vco
;
7395 vlv_dpio_get(dev_priv
);
7397 /* p1 and p2 divider */
7398 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW13(port
),
7399 5 << DPIO_CHV_S1_DIV_SHIFT
|
7400 bestp1
<< DPIO_CHV_P1_DIV_SHIFT
|
7401 bestp2
<< DPIO_CHV_P2_DIV_SHIFT
|
7402 1 << DPIO_CHV_K_DIV_SHIFT
);
7404 /* Feedback post-divider - m2 */
7405 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW0(port
), bestm2
);
7407 /* Feedback refclk divider - n and m1 */
7408 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW1(port
),
7409 DPIO_CHV_M1_DIV_BY_2
|
7410 1 << DPIO_CHV_N_DIV_SHIFT
);
7412 /* M2 fraction division */
7413 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW2(port
), bestm2_frac
);
7415 /* M2 fraction division enable */
7416 dpio_val
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW3(port
));
7417 dpio_val
&= ~(DPIO_CHV_FEEDFWD_GAIN_MASK
| DPIO_CHV_FRAC_DIV_EN
);
7418 dpio_val
|= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT
);
7420 dpio_val
|= DPIO_CHV_FRAC_DIV_EN
;
7421 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW3(port
), dpio_val
);
7423 /* Program digital lock detect threshold */
7424 dpio_val
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW9(port
));
7425 dpio_val
&= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK
|
7426 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE
);
7427 dpio_val
|= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT
);
7429 dpio_val
|= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE
;
7430 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW9(port
), dpio_val
);
7433 if (vco
== 5400000) {
7434 loopfilter
|= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT
);
7435 loopfilter
|= (0x8 << DPIO_CHV_INT_COEFF_SHIFT
);
7436 loopfilter
|= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7437 tribuf_calcntr
= 0x9;
7438 } else if (vco
<= 6200000) {
7439 loopfilter
|= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT
);
7440 loopfilter
|= (0xB << DPIO_CHV_INT_COEFF_SHIFT
);
7441 loopfilter
|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7442 tribuf_calcntr
= 0x9;
7443 } else if (vco
<= 6480000) {
7444 loopfilter
|= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT
);
7445 loopfilter
|= (0x9 << DPIO_CHV_INT_COEFF_SHIFT
);
7446 loopfilter
|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7447 tribuf_calcntr
= 0x8;
7449 /* Not supported. Apply the same limits as in the max case */
7450 loopfilter
|= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT
);
7451 loopfilter
|= (0x9 << DPIO_CHV_INT_COEFF_SHIFT
);
7452 loopfilter
|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7455 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW6(port
), loopfilter
);
7457 dpio_val
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW8(port
));
7458 dpio_val
&= ~DPIO_CHV_TDC_TARGET_CNT_MASK
;
7459 dpio_val
|= (tribuf_calcntr
<< DPIO_CHV_TDC_TARGET_CNT_SHIFT
);
7460 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW8(port
), dpio_val
);
7463 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
),
7464 vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
)) |
7467 vlv_dpio_put(dev_priv
);
7471 * vlv_force_pll_on - forcibly enable just the PLL
7472 * @dev_priv: i915 private structure
7473 * @pipe: pipe PLL to enable
7474 * @dpll: PLL configuration
7476 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7477 * in cases where we need the PLL enabled even when @pipe is not going to
7480 int vlv_force_pll_on(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
7481 const struct dpll
*dpll
)
7483 struct intel_crtc
*crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
7484 struct intel_crtc_state
*pipe_config
;
7486 pipe_config
= kzalloc(sizeof(*pipe_config
), GFP_KERNEL
);
7490 pipe_config
->base
.crtc
= &crtc
->base
;
7491 pipe_config
->pixel_multiplier
= 1;
7492 pipe_config
->dpll
= *dpll
;
7494 if (IS_CHERRYVIEW(dev_priv
)) {
7495 chv_compute_dpll(crtc
, pipe_config
);
7496 chv_prepare_pll(crtc
, pipe_config
);
7497 chv_enable_pll(crtc
, pipe_config
);
7499 vlv_compute_dpll(crtc
, pipe_config
);
7500 vlv_prepare_pll(crtc
, pipe_config
);
7501 vlv_enable_pll(crtc
, pipe_config
);
7510 * vlv_force_pll_off - forcibly disable just the PLL
7511 * @dev_priv: i915 private structure
7512 * @pipe: pipe PLL to disable
7514 * Disable the PLL for @pipe. To be used in cases where we need
7515 * the PLL enabled even when @pipe is not going to be enabled.
7517 void vlv_force_pll_off(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
7519 if (IS_CHERRYVIEW(dev_priv
))
7520 chv_disable_pll(dev_priv
, pipe
);
7522 vlv_disable_pll(dev_priv
, pipe
);
7525 static void i9xx_compute_dpll(struct intel_crtc
*crtc
,
7526 struct intel_crtc_state
*crtc_state
,
7527 struct dpll
*reduced_clock
)
7529 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
7531 struct dpll
*clock
= &crtc_state
->dpll
;
7533 i9xx_update_pll_dividers(crtc
, crtc_state
, reduced_clock
);
7535 dpll
= DPLL_VGA_MODE_DIS
;
7537 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
))
7538 dpll
|= DPLLB_MODE_LVDS
;
7540 dpll
|= DPLLB_MODE_DAC_SERIAL
;
7542 if (IS_I945G(dev_priv
) || IS_I945GM(dev_priv
) ||
7543 IS_G33(dev_priv
) || IS_PINEVIEW(dev_priv
)) {
7544 dpll
|= (crtc_state
->pixel_multiplier
- 1)
7545 << SDVO_MULTIPLIER_SHIFT_HIRES
;
7548 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_SDVO
) ||
7549 intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_HDMI
))
7550 dpll
|= DPLL_SDVO_HIGH_SPEED
;
7552 if (intel_crtc_has_dp_encoder(crtc_state
))
7553 dpll
|= DPLL_SDVO_HIGH_SPEED
;
7555 /* compute bitmask from p1 value */
7556 if (IS_PINEVIEW(dev_priv
))
7557 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
7559 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7560 if (IS_G4X(dev_priv
) && reduced_clock
)
7561 dpll
|= (1 << (reduced_clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
7563 switch (clock
->p2
) {
7565 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
7568 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
7571 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
7574 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
7577 if (INTEL_GEN(dev_priv
) >= 4)
7578 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
7580 if (crtc_state
->sdvo_tv_clock
)
7581 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
7582 else if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
7583 intel_panel_use_ssc(dev_priv
))
7584 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
7586 dpll
|= PLL_REF_INPUT_DREFCLK
;
7588 dpll
|= DPLL_VCO_ENABLE
;
7589 crtc_state
->dpll_hw_state
.dpll
= dpll
;
7591 if (INTEL_GEN(dev_priv
) >= 4) {
7592 u32 dpll_md
= (crtc_state
->pixel_multiplier
- 1)
7593 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
7594 crtc_state
->dpll_hw_state
.dpll_md
= dpll_md
;
7598 static void i8xx_compute_dpll(struct intel_crtc
*crtc
,
7599 struct intel_crtc_state
*crtc_state
,
7600 struct dpll
*reduced_clock
)
7602 struct drm_device
*dev
= crtc
->base
.dev
;
7603 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7605 struct dpll
*clock
= &crtc_state
->dpll
;
7607 i9xx_update_pll_dividers(crtc
, crtc_state
, reduced_clock
);
7609 dpll
= DPLL_VGA_MODE_DIS
;
7611 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
7612 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7615 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
7617 dpll
|= (clock
->p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7619 dpll
|= PLL_P2_DIVIDE_BY_4
;
7624 * "[Almador Errata}: For the correct operation of the muxed DVO pins
7625 * (GDEVSELB/I2Cdata, GIRDBY/I2CClk) and (GFRAMEB/DVI_Data,
7626 * GTRDYB/DVI_Clk): Bit 31 (DPLL VCO Enable) and Bit 30 (2X Clock
7627 * Enable) must be set to “1” in both the DPLL A Control Register
7628 * (06014h-06017h) and DPLL B Control Register (06018h-0601Bh)."
7630 * For simplicity We simply keep both bits always enabled in
7631 * both DPLLS. The spec says we should disable the DVO 2X clock
7632 * when not needed, but this seems to work fine in practice.
7634 if (IS_I830(dev_priv
) ||
7635 intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_DVO
))
7636 dpll
|= DPLL_DVO_2X_MODE
;
7638 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
7639 intel_panel_use_ssc(dev_priv
))
7640 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
7642 dpll
|= PLL_REF_INPUT_DREFCLK
;
7644 dpll
|= DPLL_VCO_ENABLE
;
7645 crtc_state
->dpll_hw_state
.dpll
= dpll
;
7648 static void intel_set_pipe_timings(const struct intel_crtc_state
*crtc_state
)
7650 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
7651 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
7652 enum pipe pipe
= crtc
->pipe
;
7653 enum transcoder cpu_transcoder
= crtc_state
->cpu_transcoder
;
7654 const struct drm_display_mode
*adjusted_mode
= &crtc_state
->base
.adjusted_mode
;
7655 u32 crtc_vtotal
, crtc_vblank_end
;
7658 /* We need to be careful not to changed the adjusted mode, for otherwise
7659 * the hw state checker will get angry at the mismatch. */
7660 crtc_vtotal
= adjusted_mode
->crtc_vtotal
;
7661 crtc_vblank_end
= adjusted_mode
->crtc_vblank_end
;
7663 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
7664 /* the chip adds 2 halflines automatically */
7666 crtc_vblank_end
-= 1;
7668 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_SDVO
))
7669 vsyncshift
= (adjusted_mode
->crtc_htotal
- 1) / 2;
7671 vsyncshift
= adjusted_mode
->crtc_hsync_start
-
7672 adjusted_mode
->crtc_htotal
/ 2;
7674 vsyncshift
+= adjusted_mode
->crtc_htotal
;
7677 if (INTEL_GEN(dev_priv
) > 3)
7678 I915_WRITE(VSYNCSHIFT(cpu_transcoder
), vsyncshift
);
7680 I915_WRITE(HTOTAL(cpu_transcoder
),
7681 (adjusted_mode
->crtc_hdisplay
- 1) |
7682 ((adjusted_mode
->crtc_htotal
- 1) << 16));
7683 I915_WRITE(HBLANK(cpu_transcoder
),
7684 (adjusted_mode
->crtc_hblank_start
- 1) |
7685 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
7686 I915_WRITE(HSYNC(cpu_transcoder
),
7687 (adjusted_mode
->crtc_hsync_start
- 1) |
7688 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
7690 I915_WRITE(VTOTAL(cpu_transcoder
),
7691 (adjusted_mode
->crtc_vdisplay
- 1) |
7692 ((crtc_vtotal
- 1) << 16));
7693 I915_WRITE(VBLANK(cpu_transcoder
),
7694 (adjusted_mode
->crtc_vblank_start
- 1) |
7695 ((crtc_vblank_end
- 1) << 16));
7696 I915_WRITE(VSYNC(cpu_transcoder
),
7697 (adjusted_mode
->crtc_vsync_start
- 1) |
7698 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
7700 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7701 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7702 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7704 if (IS_HASWELL(dev_priv
) && cpu_transcoder
== TRANSCODER_EDP
&&
7705 (pipe
== PIPE_B
|| pipe
== PIPE_C
))
7706 I915_WRITE(VTOTAL(pipe
), I915_READ(VTOTAL(cpu_transcoder
)));
7710 static void intel_set_pipe_src_size(const struct intel_crtc_state
*crtc_state
)
7712 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
7713 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
7714 enum pipe pipe
= crtc
->pipe
;
7716 /* pipesrc controls the size that is scaled from, which should
7717 * always be the user's requested size.
7719 I915_WRITE(PIPESRC(pipe
),
7720 ((crtc_state
->pipe_src_w
- 1) << 16) |
7721 (crtc_state
->pipe_src_h
- 1));
7724 static void intel_get_pipe_timings(struct intel_crtc
*crtc
,
7725 struct intel_crtc_state
*pipe_config
)
7727 struct drm_device
*dev
= crtc
->base
.dev
;
7728 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7729 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
7732 tmp
= I915_READ(HTOTAL(cpu_transcoder
));
7733 pipe_config
->base
.adjusted_mode
.crtc_hdisplay
= (tmp
& 0xffff) + 1;
7734 pipe_config
->base
.adjusted_mode
.crtc_htotal
= ((tmp
>> 16) & 0xffff) + 1;
7735 tmp
= I915_READ(HBLANK(cpu_transcoder
));
7736 pipe_config
->base
.adjusted_mode
.crtc_hblank_start
= (tmp
& 0xffff) + 1;
7737 pipe_config
->base
.adjusted_mode
.crtc_hblank_end
= ((tmp
>> 16) & 0xffff) + 1;
7738 tmp
= I915_READ(HSYNC(cpu_transcoder
));
7739 pipe_config
->base
.adjusted_mode
.crtc_hsync_start
= (tmp
& 0xffff) + 1;
7740 pipe_config
->base
.adjusted_mode
.crtc_hsync_end
= ((tmp
>> 16) & 0xffff) + 1;
7742 tmp
= I915_READ(VTOTAL(cpu_transcoder
));
7743 pipe_config
->base
.adjusted_mode
.crtc_vdisplay
= (tmp
& 0xffff) + 1;
7744 pipe_config
->base
.adjusted_mode
.crtc_vtotal
= ((tmp
>> 16) & 0xffff) + 1;
7745 tmp
= I915_READ(VBLANK(cpu_transcoder
));
7746 pipe_config
->base
.adjusted_mode
.crtc_vblank_start
= (tmp
& 0xffff) + 1;
7747 pipe_config
->base
.adjusted_mode
.crtc_vblank_end
= ((tmp
>> 16) & 0xffff) + 1;
7748 tmp
= I915_READ(VSYNC(cpu_transcoder
));
7749 pipe_config
->base
.adjusted_mode
.crtc_vsync_start
= (tmp
& 0xffff) + 1;
7750 pipe_config
->base
.adjusted_mode
.crtc_vsync_end
= ((tmp
>> 16) & 0xffff) + 1;
7752 if (I915_READ(PIPECONF(cpu_transcoder
)) & PIPECONF_INTERLACE_MASK
) {
7753 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_INTERLACE
;
7754 pipe_config
->base
.adjusted_mode
.crtc_vtotal
+= 1;
7755 pipe_config
->base
.adjusted_mode
.crtc_vblank_end
+= 1;
7759 static void intel_get_pipe_src_size(struct intel_crtc
*crtc
,
7760 struct intel_crtc_state
*pipe_config
)
7762 struct drm_device
*dev
= crtc
->base
.dev
;
7763 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7766 tmp
= I915_READ(PIPESRC(crtc
->pipe
));
7767 pipe_config
->pipe_src_h
= (tmp
& 0xffff) + 1;
7768 pipe_config
->pipe_src_w
= ((tmp
>> 16) & 0xffff) + 1;
7770 pipe_config
->base
.mode
.vdisplay
= pipe_config
->pipe_src_h
;
7771 pipe_config
->base
.mode
.hdisplay
= pipe_config
->pipe_src_w
;
7774 void intel_mode_from_pipe_config(struct drm_display_mode
*mode
,
7775 struct intel_crtc_state
*pipe_config
)
7777 mode
->hdisplay
= pipe_config
->base
.adjusted_mode
.crtc_hdisplay
;
7778 mode
->htotal
= pipe_config
->base
.adjusted_mode
.crtc_htotal
;
7779 mode
->hsync_start
= pipe_config
->base
.adjusted_mode
.crtc_hsync_start
;
7780 mode
->hsync_end
= pipe_config
->base
.adjusted_mode
.crtc_hsync_end
;
7782 mode
->vdisplay
= pipe_config
->base
.adjusted_mode
.crtc_vdisplay
;
7783 mode
->vtotal
= pipe_config
->base
.adjusted_mode
.crtc_vtotal
;
7784 mode
->vsync_start
= pipe_config
->base
.adjusted_mode
.crtc_vsync_start
;
7785 mode
->vsync_end
= pipe_config
->base
.adjusted_mode
.crtc_vsync_end
;
7787 mode
->flags
= pipe_config
->base
.adjusted_mode
.flags
;
7788 mode
->type
= DRM_MODE_TYPE_DRIVER
;
7790 mode
->clock
= pipe_config
->base
.adjusted_mode
.crtc_clock
;
7792 mode
->hsync
= drm_mode_hsync(mode
);
7793 mode
->vrefresh
= drm_mode_vrefresh(mode
);
7794 drm_mode_set_name(mode
);
7797 static void i9xx_set_pipeconf(const struct intel_crtc_state
*crtc_state
)
7799 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
7800 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
7805 /* we keep both pipes enabled on 830 */
7806 if (IS_I830(dev_priv
))
7807 pipeconf
|= I915_READ(PIPECONF(crtc
->pipe
)) & PIPECONF_ENABLE
;
7809 if (crtc_state
->double_wide
)
7810 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
7812 /* only g4x and later have fancy bpc/dither controls */
7813 if (IS_G4X(dev_priv
) || IS_VALLEYVIEW(dev_priv
) ||
7814 IS_CHERRYVIEW(dev_priv
)) {
7815 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7816 if (crtc_state
->dither
&& crtc_state
->pipe_bpp
!= 30)
7817 pipeconf
|= PIPECONF_DITHER_EN
|
7818 PIPECONF_DITHER_TYPE_SP
;
7820 switch (crtc_state
->pipe_bpp
) {
7822 pipeconf
|= PIPECONF_6BPC
;
7825 pipeconf
|= PIPECONF_8BPC
;
7828 pipeconf
|= PIPECONF_10BPC
;
7831 /* Case prevented by intel_choose_pipe_bpp_dither. */
7836 if (crtc_state
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
) {
7837 if (INTEL_GEN(dev_priv
) < 4 ||
7838 intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_SDVO
))
7839 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
7841 pipeconf
|= PIPECONF_INTERLACE_W_SYNC_SHIFT
;
7843 pipeconf
|= PIPECONF_PROGRESSIVE
;
7846 if ((IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) &&
7847 crtc_state
->limited_color_range
)
7848 pipeconf
|= PIPECONF_COLOR_RANGE_SELECT
;
7850 pipeconf
|= PIPECONF_GAMMA_MODE(crtc_state
->gamma_mode
);
7852 I915_WRITE(PIPECONF(crtc
->pipe
), pipeconf
);
7853 POSTING_READ(PIPECONF(crtc
->pipe
));
7856 static int i8xx_crtc_compute_clock(struct intel_crtc
*crtc
,
7857 struct intel_crtc_state
*crtc_state
)
7859 struct drm_device
*dev
= crtc
->base
.dev
;
7860 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7861 const struct intel_limit
*limit
;
7864 memset(&crtc_state
->dpll_hw_state
, 0,
7865 sizeof(crtc_state
->dpll_hw_state
));
7867 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
7868 if (intel_panel_use_ssc(dev_priv
)) {
7869 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
7870 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
7873 limit
= &intel_limits_i8xx_lvds
;
7874 } else if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_DVO
)) {
7875 limit
= &intel_limits_i8xx_dvo
;
7877 limit
= &intel_limits_i8xx_dac
;
7880 if (!crtc_state
->clock_set
&&
7881 !i9xx_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
7882 refclk
, NULL
, &crtc_state
->dpll
)) {
7883 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7887 i8xx_compute_dpll(crtc
, crtc_state
, NULL
);
7892 static int g4x_crtc_compute_clock(struct intel_crtc
*crtc
,
7893 struct intel_crtc_state
*crtc_state
)
7895 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
7896 const struct intel_limit
*limit
;
7899 memset(&crtc_state
->dpll_hw_state
, 0,
7900 sizeof(crtc_state
->dpll_hw_state
));
7902 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
7903 if (intel_panel_use_ssc(dev_priv
)) {
7904 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
7905 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
7908 if (intel_is_dual_link_lvds(dev_priv
))
7909 limit
= &intel_limits_g4x_dual_channel_lvds
;
7911 limit
= &intel_limits_g4x_single_channel_lvds
;
7912 } else if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_HDMI
) ||
7913 intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_ANALOG
)) {
7914 limit
= &intel_limits_g4x_hdmi
;
7915 } else if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_SDVO
)) {
7916 limit
= &intel_limits_g4x_sdvo
;
7918 /* The option is for other outputs */
7919 limit
= &intel_limits_i9xx_sdvo
;
7922 if (!crtc_state
->clock_set
&&
7923 !g4x_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
7924 refclk
, NULL
, &crtc_state
->dpll
)) {
7925 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7929 i9xx_compute_dpll(crtc
, crtc_state
, NULL
);
7934 static int pnv_crtc_compute_clock(struct intel_crtc
*crtc
,
7935 struct intel_crtc_state
*crtc_state
)
7937 struct drm_device
*dev
= crtc
->base
.dev
;
7938 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7939 const struct intel_limit
*limit
;
7942 memset(&crtc_state
->dpll_hw_state
, 0,
7943 sizeof(crtc_state
->dpll_hw_state
));
7945 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
7946 if (intel_panel_use_ssc(dev_priv
)) {
7947 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
7948 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
7951 limit
= &intel_limits_pineview_lvds
;
7953 limit
= &intel_limits_pineview_sdvo
;
7956 if (!crtc_state
->clock_set
&&
7957 !pnv_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
7958 refclk
, NULL
, &crtc_state
->dpll
)) {
7959 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7963 i9xx_compute_dpll(crtc
, crtc_state
, NULL
);
7968 static int i9xx_crtc_compute_clock(struct intel_crtc
*crtc
,
7969 struct intel_crtc_state
*crtc_state
)
7971 struct drm_device
*dev
= crtc
->base
.dev
;
7972 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7973 const struct intel_limit
*limit
;
7976 memset(&crtc_state
->dpll_hw_state
, 0,
7977 sizeof(crtc_state
->dpll_hw_state
));
7979 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
7980 if (intel_panel_use_ssc(dev_priv
)) {
7981 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
7982 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
7985 limit
= &intel_limits_i9xx_lvds
;
7987 limit
= &intel_limits_i9xx_sdvo
;
7990 if (!crtc_state
->clock_set
&&
7991 !i9xx_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
7992 refclk
, NULL
, &crtc_state
->dpll
)) {
7993 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7997 i9xx_compute_dpll(crtc
, crtc_state
, NULL
);
8002 static int chv_crtc_compute_clock(struct intel_crtc
*crtc
,
8003 struct intel_crtc_state
*crtc_state
)
8005 int refclk
= 100000;
8006 const struct intel_limit
*limit
= &intel_limits_chv
;
8008 memset(&crtc_state
->dpll_hw_state
, 0,
8009 sizeof(crtc_state
->dpll_hw_state
));
8011 if (!crtc_state
->clock_set
&&
8012 !chv_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
8013 refclk
, NULL
, &crtc_state
->dpll
)) {
8014 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8018 chv_compute_dpll(crtc
, crtc_state
);
8023 static int vlv_crtc_compute_clock(struct intel_crtc
*crtc
,
8024 struct intel_crtc_state
*crtc_state
)
8026 int refclk
= 100000;
8027 const struct intel_limit
*limit
= &intel_limits_vlv
;
8029 memset(&crtc_state
->dpll_hw_state
, 0,
8030 sizeof(crtc_state
->dpll_hw_state
));
8032 if (!crtc_state
->clock_set
&&
8033 !vlv_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
8034 refclk
, NULL
, &crtc_state
->dpll
)) {
8035 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8039 vlv_compute_dpll(crtc
, crtc_state
);
8044 static bool i9xx_has_pfit(struct drm_i915_private
*dev_priv
)
8046 if (IS_I830(dev_priv
))
8049 return INTEL_GEN(dev_priv
) >= 4 ||
8050 IS_PINEVIEW(dev_priv
) || IS_MOBILE(dev_priv
);
8053 static void i9xx_get_pfit_config(struct intel_crtc
*crtc
,
8054 struct intel_crtc_state
*pipe_config
)
8056 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
8059 if (!i9xx_has_pfit(dev_priv
))
8062 tmp
= I915_READ(PFIT_CONTROL
);
8063 if (!(tmp
& PFIT_ENABLE
))
8066 /* Check whether the pfit is attached to our pipe. */
8067 if (INTEL_GEN(dev_priv
) < 4) {
8068 if (crtc
->pipe
!= PIPE_B
)
8071 if ((tmp
& PFIT_PIPE_MASK
) != (crtc
->pipe
<< PFIT_PIPE_SHIFT
))
8075 pipe_config
->gmch_pfit
.control
= tmp
;
8076 pipe_config
->gmch_pfit
.pgm_ratios
= I915_READ(PFIT_PGM_RATIOS
);
8079 static void vlv_crtc_clock_get(struct intel_crtc
*crtc
,
8080 struct intel_crtc_state
*pipe_config
)
8082 struct drm_device
*dev
= crtc
->base
.dev
;
8083 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8084 int pipe
= pipe_config
->cpu_transcoder
;
8087 int refclk
= 100000;
8089 /* In case of DSI, DPLL will not be used */
8090 if ((pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
) == 0)
8093 vlv_dpio_get(dev_priv
);
8094 mdiv
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW3(pipe
));
8095 vlv_dpio_put(dev_priv
);
8097 clock
.m1
= (mdiv
>> DPIO_M1DIV_SHIFT
) & 7;
8098 clock
.m2
= mdiv
& DPIO_M2DIV_MASK
;
8099 clock
.n
= (mdiv
>> DPIO_N_SHIFT
) & 0xf;
8100 clock
.p1
= (mdiv
>> DPIO_P1_SHIFT
) & 7;
8101 clock
.p2
= (mdiv
>> DPIO_P2_SHIFT
) & 0x1f;
8103 pipe_config
->port_clock
= vlv_calc_dpll_params(refclk
, &clock
);
8107 i9xx_get_initial_plane_config(struct intel_crtc
*crtc
,
8108 struct intel_initial_plane_config
*plane_config
)
8110 struct drm_device
*dev
= crtc
->base
.dev
;
8111 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8112 struct intel_plane
*plane
= to_intel_plane(crtc
->base
.primary
);
8113 enum i9xx_plane_id i9xx_plane
= plane
->i9xx_plane
;
8115 u32 val
, base
, offset
;
8116 int fourcc
, pixel_format
;
8117 unsigned int aligned_height
;
8118 struct drm_framebuffer
*fb
;
8119 struct intel_framebuffer
*intel_fb
;
8121 if (!plane
->get_hw_state(plane
, &pipe
))
8124 WARN_ON(pipe
!= crtc
->pipe
);
8126 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
8128 DRM_DEBUG_KMS("failed to alloc fb\n");
8132 fb
= &intel_fb
->base
;
8136 val
= I915_READ(DSPCNTR(i9xx_plane
));
8138 if (INTEL_GEN(dev_priv
) >= 4) {
8139 if (val
& DISPPLANE_TILED
) {
8140 plane_config
->tiling
= I915_TILING_X
;
8141 fb
->modifier
= I915_FORMAT_MOD_X_TILED
;
8144 if (val
& DISPPLANE_ROTATE_180
)
8145 plane_config
->rotation
= DRM_MODE_ROTATE_180
;
8148 if (IS_CHERRYVIEW(dev_priv
) && pipe
== PIPE_B
&&
8149 val
& DISPPLANE_MIRROR
)
8150 plane_config
->rotation
|= DRM_MODE_REFLECT_X
;
8152 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
8153 fourcc
= i9xx_format_to_fourcc(pixel_format
);
8154 fb
->format
= drm_format_info(fourcc
);
8156 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
8157 offset
= I915_READ(DSPOFFSET(i9xx_plane
));
8158 base
= I915_READ(DSPSURF(i9xx_plane
)) & 0xfffff000;
8159 } else if (INTEL_GEN(dev_priv
) >= 4) {
8160 if (plane_config
->tiling
)
8161 offset
= I915_READ(DSPTILEOFF(i9xx_plane
));
8163 offset
= I915_READ(DSPLINOFF(i9xx_plane
));
8164 base
= I915_READ(DSPSURF(i9xx_plane
)) & 0xfffff000;
8166 base
= I915_READ(DSPADDR(i9xx_plane
));
8168 plane_config
->base
= base
;
8170 val
= I915_READ(PIPESRC(pipe
));
8171 fb
->width
= ((val
>> 16) & 0xfff) + 1;
8172 fb
->height
= ((val
>> 0) & 0xfff) + 1;
8174 val
= I915_READ(DSPSTRIDE(i9xx_plane
));
8175 fb
->pitches
[0] = val
& 0xffffffc0;
8177 aligned_height
= intel_fb_align_height(fb
, 0, fb
->height
);
8179 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
8181 DRM_DEBUG_KMS("%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8182 crtc
->base
.name
, plane
->base
.name
, fb
->width
, fb
->height
,
8183 fb
->format
->cpp
[0] * 8, base
, fb
->pitches
[0],
8184 plane_config
->size
);
8186 plane_config
->fb
= intel_fb
;
8189 static void chv_crtc_clock_get(struct intel_crtc
*crtc
,
8190 struct intel_crtc_state
*pipe_config
)
8192 struct drm_device
*dev
= crtc
->base
.dev
;
8193 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8194 int pipe
= pipe_config
->cpu_transcoder
;
8195 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
8197 u32 cmn_dw13
, pll_dw0
, pll_dw1
, pll_dw2
, pll_dw3
;
8198 int refclk
= 100000;
8200 /* In case of DSI, DPLL will not be used */
8201 if ((pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
) == 0)
8204 vlv_dpio_get(dev_priv
);
8205 cmn_dw13
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW13(port
));
8206 pll_dw0
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW0(port
));
8207 pll_dw1
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW1(port
));
8208 pll_dw2
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW2(port
));
8209 pll_dw3
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW3(port
));
8210 vlv_dpio_put(dev_priv
);
8212 clock
.m1
= (pll_dw1
& 0x7) == DPIO_CHV_M1_DIV_BY_2
? 2 : 0;
8213 clock
.m2
= (pll_dw0
& 0xff) << 22;
8214 if (pll_dw3
& DPIO_CHV_FRAC_DIV_EN
)
8215 clock
.m2
|= pll_dw2
& 0x3fffff;
8216 clock
.n
= (pll_dw1
>> DPIO_CHV_N_DIV_SHIFT
) & 0xf;
8217 clock
.p1
= (cmn_dw13
>> DPIO_CHV_P1_DIV_SHIFT
) & 0x7;
8218 clock
.p2
= (cmn_dw13
>> DPIO_CHV_P2_DIV_SHIFT
) & 0x1f;
8220 pipe_config
->port_clock
= chv_calc_dpll_params(refclk
, &clock
);
8223 static void intel_get_crtc_ycbcr_config(struct intel_crtc
*crtc
,
8224 struct intel_crtc_state
*pipe_config
)
8226 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
8227 enum intel_output_format output
= INTEL_OUTPUT_FORMAT_RGB
;
8229 pipe_config
->lspcon_downsampling
= false;
8231 if (IS_BROADWELL(dev_priv
) || INTEL_GEN(dev_priv
) >= 9) {
8232 u32 tmp
= I915_READ(PIPEMISC(crtc
->pipe
));
8234 if (tmp
& PIPEMISC_OUTPUT_COLORSPACE_YUV
) {
8235 bool ycbcr420_enabled
= tmp
& PIPEMISC_YUV420_ENABLE
;
8236 bool blend
= tmp
& PIPEMISC_YUV420_MODE_FULL_BLEND
;
8238 if (ycbcr420_enabled
) {
8239 /* We support 4:2:0 in full blend mode only */
8241 output
= INTEL_OUTPUT_FORMAT_INVALID
;
8242 else if (!(IS_GEMINILAKE(dev_priv
) ||
8243 INTEL_GEN(dev_priv
) >= 10))
8244 output
= INTEL_OUTPUT_FORMAT_INVALID
;
8246 output
= INTEL_OUTPUT_FORMAT_YCBCR420
;
8249 * Currently there is no interface defined to
8250 * check user preference between RGB/YCBCR444
8251 * or YCBCR420. So the only possible case for
8252 * YCBCR444 usage is driving YCBCR420 output
8253 * with LSPCON, when pipe is configured for
8254 * YCBCR444 output and LSPCON takes care of
8257 pipe_config
->lspcon_downsampling
= true;
8258 output
= INTEL_OUTPUT_FORMAT_YCBCR444
;
8263 pipe_config
->output_format
= output
;
8266 static void i9xx_get_pipe_color_config(struct intel_crtc_state
*crtc_state
)
8268 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
8269 struct intel_plane
*plane
= to_intel_plane(crtc
->base
.primary
);
8270 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
8271 enum i9xx_plane_id i9xx_plane
= plane
->i9xx_plane
;
8274 tmp
= I915_READ(DSPCNTR(i9xx_plane
));
8276 if (tmp
& DISPPLANE_GAMMA_ENABLE
)
8277 crtc_state
->gamma_enable
= true;
8279 if (!HAS_GMCH(dev_priv
) &&
8280 tmp
& DISPPLANE_PIPE_CSC_ENABLE
)
8281 crtc_state
->csc_enable
= true;
8284 static bool i9xx_get_pipe_config(struct intel_crtc
*crtc
,
8285 struct intel_crtc_state
*pipe_config
)
8287 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
8288 enum intel_display_power_domain power_domain
;
8289 intel_wakeref_t wakeref
;
8293 power_domain
= POWER_DOMAIN_PIPE(crtc
->pipe
);
8294 wakeref
= intel_display_power_get_if_enabled(dev_priv
, power_domain
);
8298 pipe_config
->output_format
= INTEL_OUTPUT_FORMAT_RGB
;
8299 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
8300 pipe_config
->shared_dpll
= NULL
;
8304 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
8305 if (!(tmp
& PIPECONF_ENABLE
))
8308 if (IS_G4X(dev_priv
) || IS_VALLEYVIEW(dev_priv
) ||
8309 IS_CHERRYVIEW(dev_priv
)) {
8310 switch (tmp
& PIPECONF_BPC_MASK
) {
8312 pipe_config
->pipe_bpp
= 18;
8315 pipe_config
->pipe_bpp
= 24;
8317 case PIPECONF_10BPC
:
8318 pipe_config
->pipe_bpp
= 30;
8325 if ((IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) &&
8326 (tmp
& PIPECONF_COLOR_RANGE_SELECT
))
8327 pipe_config
->limited_color_range
= true;
8329 pipe_config
->gamma_mode
= (tmp
& PIPECONF_GAMMA_MODE_MASK_I9XX
) >>
8330 PIPECONF_GAMMA_MODE_SHIFT
;
8332 if (IS_CHERRYVIEW(dev_priv
))
8333 pipe_config
->cgm_mode
= I915_READ(CGM_PIPE_MODE(crtc
->pipe
));
8335 i9xx_get_pipe_color_config(pipe_config
);
8337 if (INTEL_GEN(dev_priv
) < 4)
8338 pipe_config
->double_wide
= tmp
& PIPECONF_DOUBLE_WIDE
;
8340 intel_get_pipe_timings(crtc
, pipe_config
);
8341 intel_get_pipe_src_size(crtc
, pipe_config
);
8343 i9xx_get_pfit_config(crtc
, pipe_config
);
8345 if (INTEL_GEN(dev_priv
) >= 4) {
8346 /* No way to read it out on pipes B and C */
8347 if (IS_CHERRYVIEW(dev_priv
) && crtc
->pipe
!= PIPE_A
)
8348 tmp
= dev_priv
->chv_dpll_md
[crtc
->pipe
];
8350 tmp
= I915_READ(DPLL_MD(crtc
->pipe
));
8351 pipe_config
->pixel_multiplier
=
8352 ((tmp
& DPLL_MD_UDI_MULTIPLIER_MASK
)
8353 >> DPLL_MD_UDI_MULTIPLIER_SHIFT
) + 1;
8354 pipe_config
->dpll_hw_state
.dpll_md
= tmp
;
8355 } else if (IS_I945G(dev_priv
) || IS_I945GM(dev_priv
) ||
8356 IS_G33(dev_priv
) || IS_PINEVIEW(dev_priv
)) {
8357 tmp
= I915_READ(DPLL(crtc
->pipe
));
8358 pipe_config
->pixel_multiplier
=
8359 ((tmp
& SDVO_MULTIPLIER_MASK
)
8360 >> SDVO_MULTIPLIER_SHIFT_HIRES
) + 1;
8362 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8363 * port and will be fixed up in the encoder->get_config
8365 pipe_config
->pixel_multiplier
= 1;
8367 pipe_config
->dpll_hw_state
.dpll
= I915_READ(DPLL(crtc
->pipe
));
8368 if (!IS_VALLEYVIEW(dev_priv
) && !IS_CHERRYVIEW(dev_priv
)) {
8369 pipe_config
->dpll_hw_state
.fp0
= I915_READ(FP0(crtc
->pipe
));
8370 pipe_config
->dpll_hw_state
.fp1
= I915_READ(FP1(crtc
->pipe
));
8372 /* Mask out read-only status bits. */
8373 pipe_config
->dpll_hw_state
.dpll
&= ~(DPLL_LOCK_VLV
|
8374 DPLL_PORTC_READY_MASK
|
8375 DPLL_PORTB_READY_MASK
);
8378 if (IS_CHERRYVIEW(dev_priv
))
8379 chv_crtc_clock_get(crtc
, pipe_config
);
8380 else if (IS_VALLEYVIEW(dev_priv
))
8381 vlv_crtc_clock_get(crtc
, pipe_config
);
8383 i9xx_crtc_clock_get(crtc
, pipe_config
);
8386 * Normally the dotclock is filled in by the encoder .get_config()
8387 * but in case the pipe is enabled w/o any ports we need a sane
8390 pipe_config
->base
.adjusted_mode
.crtc_clock
=
8391 pipe_config
->port_clock
/ pipe_config
->pixel_multiplier
;
8396 intel_display_power_put(dev_priv
, power_domain
, wakeref
);
8401 static void ironlake_init_pch_refclk(struct drm_i915_private
*dev_priv
)
8403 struct intel_encoder
*encoder
;
8406 bool has_lvds
= false;
8407 bool has_cpu_edp
= false;
8408 bool has_panel
= false;
8409 bool has_ck505
= false;
8410 bool can_ssc
= false;
8411 bool using_ssc_source
= false;
8413 /* We need to take the global config into account */
8414 for_each_intel_encoder(&dev_priv
->drm
, encoder
) {
8415 switch (encoder
->type
) {
8416 case INTEL_OUTPUT_LVDS
:
8420 case INTEL_OUTPUT_EDP
:
8422 if (encoder
->port
== PORT_A
)
8430 if (HAS_PCH_IBX(dev_priv
)) {
8431 has_ck505
= dev_priv
->vbt
.display_clock_mode
;
8432 can_ssc
= has_ck505
;
8438 /* Check if any DPLLs are using the SSC source */
8439 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
8440 u32 temp
= I915_READ(PCH_DPLL(i
));
8442 if (!(temp
& DPLL_VCO_ENABLE
))
8445 if ((temp
& PLL_REF_INPUT_MASK
) ==
8446 PLLB_REF_INPUT_SPREADSPECTRUMIN
) {
8447 using_ssc_source
= true;
8452 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
8453 has_panel
, has_lvds
, has_ck505
, using_ssc_source
);
8455 /* Ironlake: try to setup display ref clock before DPLL
8456 * enabling. This is only under driver's control after
8457 * PCH B stepping, previous chipset stepping should be
8458 * ignoring this setting.
8460 val
= I915_READ(PCH_DREF_CONTROL
);
8462 /* As we must carefully and slowly disable/enable each source in turn,
8463 * compute the final state we want first and check if we need to
8464 * make any changes at all.
8467 final
&= ~DREF_NONSPREAD_SOURCE_MASK
;
8469 final
|= DREF_NONSPREAD_CK505_ENABLE
;
8471 final
|= DREF_NONSPREAD_SOURCE_ENABLE
;
8473 final
&= ~DREF_SSC_SOURCE_MASK
;
8474 final
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
8475 final
&= ~DREF_SSC1_ENABLE
;
8478 final
|= DREF_SSC_SOURCE_ENABLE
;
8480 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
8481 final
|= DREF_SSC1_ENABLE
;
8484 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
8485 final
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
8487 final
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
8489 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
8490 } else if (using_ssc_source
) {
8491 final
|= DREF_SSC_SOURCE_ENABLE
;
8492 final
|= DREF_SSC1_ENABLE
;
8498 /* Always enable nonspread source */
8499 val
&= ~DREF_NONSPREAD_SOURCE_MASK
;
8502 val
|= DREF_NONSPREAD_CK505_ENABLE
;
8504 val
|= DREF_NONSPREAD_SOURCE_ENABLE
;
8507 val
&= ~DREF_SSC_SOURCE_MASK
;
8508 val
|= DREF_SSC_SOURCE_ENABLE
;
8510 /* SSC must be turned on before enabling the CPU output */
8511 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
8512 DRM_DEBUG_KMS("Using SSC on panel\n");
8513 val
|= DREF_SSC1_ENABLE
;
8515 val
&= ~DREF_SSC1_ENABLE
;
8517 /* Get SSC going before enabling the outputs */
8518 I915_WRITE(PCH_DREF_CONTROL
, val
);
8519 POSTING_READ(PCH_DREF_CONTROL
);
8522 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
8524 /* Enable CPU source on CPU attached eDP */
8526 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
8527 DRM_DEBUG_KMS("Using SSC on eDP\n");
8528 val
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
8530 val
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
8532 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
8534 I915_WRITE(PCH_DREF_CONTROL
, val
);
8535 POSTING_READ(PCH_DREF_CONTROL
);
8538 DRM_DEBUG_KMS("Disabling CPU source output\n");
8540 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
8542 /* Turn off CPU output */
8543 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
8545 I915_WRITE(PCH_DREF_CONTROL
, val
);
8546 POSTING_READ(PCH_DREF_CONTROL
);
8549 if (!using_ssc_source
) {
8550 DRM_DEBUG_KMS("Disabling SSC source\n");
8552 /* Turn off the SSC source */
8553 val
&= ~DREF_SSC_SOURCE_MASK
;
8554 val
|= DREF_SSC_SOURCE_DISABLE
;
8557 val
&= ~DREF_SSC1_ENABLE
;
8559 I915_WRITE(PCH_DREF_CONTROL
, val
);
8560 POSTING_READ(PCH_DREF_CONTROL
);
8565 BUG_ON(val
!= final
);
8568 static void lpt_reset_fdi_mphy(struct drm_i915_private
*dev_priv
)
8572 tmp
= I915_READ(SOUTH_CHICKEN2
);
8573 tmp
|= FDI_MPHY_IOSFSB_RESET_CTL
;
8574 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
8576 if (wait_for_us(I915_READ(SOUTH_CHICKEN2
) &
8577 FDI_MPHY_IOSFSB_RESET_STATUS
, 100))
8578 DRM_ERROR("FDI mPHY reset assert timeout\n");
8580 tmp
= I915_READ(SOUTH_CHICKEN2
);
8581 tmp
&= ~FDI_MPHY_IOSFSB_RESET_CTL
;
8582 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
8584 if (wait_for_us((I915_READ(SOUTH_CHICKEN2
) &
8585 FDI_MPHY_IOSFSB_RESET_STATUS
) == 0, 100))
8586 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8589 /* WaMPhyProgramming:hsw */
8590 static void lpt_program_fdi_mphy(struct drm_i915_private
*dev_priv
)
8594 tmp
= intel_sbi_read(dev_priv
, 0x8008, SBI_MPHY
);
8595 tmp
&= ~(0xFF << 24);
8596 tmp
|= (0x12 << 24);
8597 intel_sbi_write(dev_priv
, 0x8008, tmp
, SBI_MPHY
);
8599 tmp
= intel_sbi_read(dev_priv
, 0x2008, SBI_MPHY
);
8601 intel_sbi_write(dev_priv
, 0x2008, tmp
, SBI_MPHY
);
8603 tmp
= intel_sbi_read(dev_priv
, 0x2108, SBI_MPHY
);
8605 intel_sbi_write(dev_priv
, 0x2108, tmp
, SBI_MPHY
);
8607 tmp
= intel_sbi_read(dev_priv
, 0x206C, SBI_MPHY
);
8608 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
8609 intel_sbi_write(dev_priv
, 0x206C, tmp
, SBI_MPHY
);
8611 tmp
= intel_sbi_read(dev_priv
, 0x216C, SBI_MPHY
);
8612 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
8613 intel_sbi_write(dev_priv
, 0x216C, tmp
, SBI_MPHY
);
8615 tmp
= intel_sbi_read(dev_priv
, 0x2080, SBI_MPHY
);
8618 intel_sbi_write(dev_priv
, 0x2080, tmp
, SBI_MPHY
);
8620 tmp
= intel_sbi_read(dev_priv
, 0x2180, SBI_MPHY
);
8623 intel_sbi_write(dev_priv
, 0x2180, tmp
, SBI_MPHY
);
8625 tmp
= intel_sbi_read(dev_priv
, 0x208C, SBI_MPHY
);
8628 intel_sbi_write(dev_priv
, 0x208C, tmp
, SBI_MPHY
);
8630 tmp
= intel_sbi_read(dev_priv
, 0x218C, SBI_MPHY
);
8633 intel_sbi_write(dev_priv
, 0x218C, tmp
, SBI_MPHY
);
8635 tmp
= intel_sbi_read(dev_priv
, 0x2098, SBI_MPHY
);
8636 tmp
&= ~(0xFF << 16);
8637 tmp
|= (0x1C << 16);
8638 intel_sbi_write(dev_priv
, 0x2098, tmp
, SBI_MPHY
);
8640 tmp
= intel_sbi_read(dev_priv
, 0x2198, SBI_MPHY
);
8641 tmp
&= ~(0xFF << 16);
8642 tmp
|= (0x1C << 16);
8643 intel_sbi_write(dev_priv
, 0x2198, tmp
, SBI_MPHY
);
8645 tmp
= intel_sbi_read(dev_priv
, 0x20C4, SBI_MPHY
);
8647 intel_sbi_write(dev_priv
, 0x20C4, tmp
, SBI_MPHY
);
8649 tmp
= intel_sbi_read(dev_priv
, 0x21C4, SBI_MPHY
);
8651 intel_sbi_write(dev_priv
, 0x21C4, tmp
, SBI_MPHY
);
8653 tmp
= intel_sbi_read(dev_priv
, 0x20EC, SBI_MPHY
);
8654 tmp
&= ~(0xF << 28);
8656 intel_sbi_write(dev_priv
, 0x20EC, tmp
, SBI_MPHY
);
8658 tmp
= intel_sbi_read(dev_priv
, 0x21EC, SBI_MPHY
);
8659 tmp
&= ~(0xF << 28);
8661 intel_sbi_write(dev_priv
, 0x21EC, tmp
, SBI_MPHY
);
8664 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8665 * Programming" based on the parameters passed:
8666 * - Sequence to enable CLKOUT_DP
8667 * - Sequence to enable CLKOUT_DP without spread
8668 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8670 static void lpt_enable_clkout_dp(struct drm_i915_private
*dev_priv
,
8671 bool with_spread
, bool with_fdi
)
8675 if (WARN(with_fdi
&& !with_spread
, "FDI requires downspread\n"))
8677 if (WARN(HAS_PCH_LPT_LP(dev_priv
) &&
8678 with_fdi
, "LP PCH doesn't have FDI\n"))
8681 mutex_lock(&dev_priv
->sb_lock
);
8683 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
8684 tmp
&= ~SBI_SSCCTL_DISABLE
;
8685 tmp
|= SBI_SSCCTL_PATHALT
;
8686 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
8691 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
8692 tmp
&= ~SBI_SSCCTL_PATHALT
;
8693 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
8696 lpt_reset_fdi_mphy(dev_priv
);
8697 lpt_program_fdi_mphy(dev_priv
);
8701 reg
= HAS_PCH_LPT_LP(dev_priv
) ? SBI_GEN0
: SBI_DBUFF0
;
8702 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
8703 tmp
|= SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
8704 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
8706 mutex_unlock(&dev_priv
->sb_lock
);
8709 /* Sequence to disable CLKOUT_DP */
8710 static void lpt_disable_clkout_dp(struct drm_i915_private
*dev_priv
)
8714 mutex_lock(&dev_priv
->sb_lock
);
8716 reg
= HAS_PCH_LPT_LP(dev_priv
) ? SBI_GEN0
: SBI_DBUFF0
;
8717 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
8718 tmp
&= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
8719 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
8721 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
8722 if (!(tmp
& SBI_SSCCTL_DISABLE
)) {
8723 if (!(tmp
& SBI_SSCCTL_PATHALT
)) {
8724 tmp
|= SBI_SSCCTL_PATHALT
;
8725 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
8728 tmp
|= SBI_SSCCTL_DISABLE
;
8729 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
8732 mutex_unlock(&dev_priv
->sb_lock
);
8735 #define BEND_IDX(steps) ((50 + (steps)) / 5)
8737 static const u16 sscdivintphase
[] = {
8738 [BEND_IDX( 50)] = 0x3B23,
8739 [BEND_IDX( 45)] = 0x3B23,
8740 [BEND_IDX( 40)] = 0x3C23,
8741 [BEND_IDX( 35)] = 0x3C23,
8742 [BEND_IDX( 30)] = 0x3D23,
8743 [BEND_IDX( 25)] = 0x3D23,
8744 [BEND_IDX( 20)] = 0x3E23,
8745 [BEND_IDX( 15)] = 0x3E23,
8746 [BEND_IDX( 10)] = 0x3F23,
8747 [BEND_IDX( 5)] = 0x3F23,
8748 [BEND_IDX( 0)] = 0x0025,
8749 [BEND_IDX( -5)] = 0x0025,
8750 [BEND_IDX(-10)] = 0x0125,
8751 [BEND_IDX(-15)] = 0x0125,
8752 [BEND_IDX(-20)] = 0x0225,
8753 [BEND_IDX(-25)] = 0x0225,
8754 [BEND_IDX(-30)] = 0x0325,
8755 [BEND_IDX(-35)] = 0x0325,
8756 [BEND_IDX(-40)] = 0x0425,
8757 [BEND_IDX(-45)] = 0x0425,
8758 [BEND_IDX(-50)] = 0x0525,
8763 * steps -50 to 50 inclusive, in steps of 5
8764 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
8765 * change in clock period = -(steps / 10) * 5.787 ps
8767 static void lpt_bend_clkout_dp(struct drm_i915_private
*dev_priv
, int steps
)
8770 int idx
= BEND_IDX(steps
);
8772 if (WARN_ON(steps
% 5 != 0))
8775 if (WARN_ON(idx
>= ARRAY_SIZE(sscdivintphase
)))
8778 mutex_lock(&dev_priv
->sb_lock
);
8780 if (steps
% 10 != 0)
8784 intel_sbi_write(dev_priv
, SBI_SSCDITHPHASE
, tmp
, SBI_ICLK
);
8786 tmp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE
, SBI_ICLK
);
8788 tmp
|= sscdivintphase
[idx
];
8789 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE
, tmp
, SBI_ICLK
);
8791 mutex_unlock(&dev_priv
->sb_lock
);
8796 static void lpt_init_pch_refclk(struct drm_i915_private
*dev_priv
)
8798 struct intel_encoder
*encoder
;
8799 bool has_vga
= false;
8801 for_each_intel_encoder(&dev_priv
->drm
, encoder
) {
8802 switch (encoder
->type
) {
8803 case INTEL_OUTPUT_ANALOG
:
8812 lpt_bend_clkout_dp(dev_priv
, 0);
8813 lpt_enable_clkout_dp(dev_priv
, true, true);
8815 lpt_disable_clkout_dp(dev_priv
);
8820 * Initialize reference clocks when the driver loads
8822 void intel_init_pch_refclk(struct drm_i915_private
*dev_priv
)
8824 if (HAS_PCH_IBX(dev_priv
) || HAS_PCH_CPT(dev_priv
))
8825 ironlake_init_pch_refclk(dev_priv
);
8826 else if (HAS_PCH_LPT(dev_priv
))
8827 lpt_init_pch_refclk(dev_priv
);
8830 static void ironlake_set_pipeconf(const struct intel_crtc_state
*crtc_state
)
8832 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
8833 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
8834 enum pipe pipe
= crtc
->pipe
;
8839 switch (crtc_state
->pipe_bpp
) {
8841 val
|= PIPECONF_6BPC
;
8844 val
|= PIPECONF_8BPC
;
8847 val
|= PIPECONF_10BPC
;
8850 val
|= PIPECONF_12BPC
;
8853 /* Case prevented by intel_choose_pipe_bpp_dither. */
8857 if (crtc_state
->dither
)
8858 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
8860 if (crtc_state
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
8861 val
|= PIPECONF_INTERLACED_ILK
;
8863 val
|= PIPECONF_PROGRESSIVE
;
8865 if (crtc_state
->limited_color_range
)
8866 val
|= PIPECONF_COLOR_RANGE_SELECT
;
8868 val
|= PIPECONF_GAMMA_MODE(crtc_state
->gamma_mode
);
8870 I915_WRITE(PIPECONF(pipe
), val
);
8871 POSTING_READ(PIPECONF(pipe
));
8874 static void haswell_set_pipeconf(const struct intel_crtc_state
*crtc_state
)
8876 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
8877 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
8878 enum transcoder cpu_transcoder
= crtc_state
->cpu_transcoder
;
8881 if (IS_HASWELL(dev_priv
) && crtc_state
->dither
)
8882 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
8884 if (crtc_state
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
8885 val
|= PIPECONF_INTERLACED_ILK
;
8887 val
|= PIPECONF_PROGRESSIVE
;
8889 I915_WRITE(PIPECONF(cpu_transcoder
), val
);
8890 POSTING_READ(PIPECONF(cpu_transcoder
));
8893 static void haswell_set_pipemisc(const struct intel_crtc_state
*crtc_state
)
8895 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
8896 struct drm_i915_private
*dev_priv
= to_i915(intel_crtc
->base
.dev
);
8898 if (IS_BROADWELL(dev_priv
) || INTEL_GEN(dev_priv
) >= 9) {
8901 switch (crtc_state
->pipe_bpp
) {
8903 val
|= PIPEMISC_DITHER_6_BPC
;
8906 val
|= PIPEMISC_DITHER_8_BPC
;
8909 val
|= PIPEMISC_DITHER_10_BPC
;
8912 val
|= PIPEMISC_DITHER_12_BPC
;
8915 /* Case prevented by pipe_config_set_bpp. */
8919 if (crtc_state
->dither
)
8920 val
|= PIPEMISC_DITHER_ENABLE
| PIPEMISC_DITHER_TYPE_SP
;
8922 if (crtc_state
->output_format
== INTEL_OUTPUT_FORMAT_YCBCR420
||
8923 crtc_state
->output_format
== INTEL_OUTPUT_FORMAT_YCBCR444
)
8924 val
|= PIPEMISC_OUTPUT_COLORSPACE_YUV
;
8926 if (crtc_state
->output_format
== INTEL_OUTPUT_FORMAT_YCBCR420
)
8927 val
|= PIPEMISC_YUV420_ENABLE
|
8928 PIPEMISC_YUV420_MODE_FULL_BLEND
;
8930 I915_WRITE(PIPEMISC(intel_crtc
->pipe
), val
);
8934 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
)
8937 * Account for spread spectrum to avoid
8938 * oversubscribing the link. Max center spread
8939 * is 2.5%; use 5% for safety's sake.
8941 u32 bps
= target_clock
* bpp
* 21 / 20;
8942 return DIV_ROUND_UP(bps
, link_bw
* 8);
8945 static bool ironlake_needs_fb_cb_tune(struct dpll
*dpll
, int factor
)
8947 return i9xx_dpll_compute_m(dpll
) < factor
* dpll
->n
;
8950 static void ironlake_compute_dpll(struct intel_crtc
*crtc
,
8951 struct intel_crtc_state
*crtc_state
,
8952 struct dpll
*reduced_clock
)
8954 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
8958 /* Enable autotuning of the PLL clock (if permissible) */
8960 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
8961 if ((intel_panel_use_ssc(dev_priv
) &&
8962 dev_priv
->vbt
.lvds_ssc_freq
== 100000) ||
8963 (HAS_PCH_IBX(dev_priv
) &&
8964 intel_is_dual_link_lvds(dev_priv
)))
8966 } else if (crtc_state
->sdvo_tv_clock
) {
8970 fp
= i9xx_dpll_compute_fp(&crtc_state
->dpll
);
8972 if (ironlake_needs_fb_cb_tune(&crtc_state
->dpll
, factor
))
8975 if (reduced_clock
) {
8976 fp2
= i9xx_dpll_compute_fp(reduced_clock
);
8978 if (reduced_clock
->m
< factor
* reduced_clock
->n
)
8986 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
))
8987 dpll
|= DPLLB_MODE_LVDS
;
8989 dpll
|= DPLLB_MODE_DAC_SERIAL
;
8991 dpll
|= (crtc_state
->pixel_multiplier
- 1)
8992 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
8994 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_SDVO
) ||
8995 intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_HDMI
))
8996 dpll
|= DPLL_SDVO_HIGH_SPEED
;
8998 if (intel_crtc_has_dp_encoder(crtc_state
))
8999 dpll
|= DPLL_SDVO_HIGH_SPEED
;
9002 * The high speed IO clock is only really required for
9003 * SDVO/HDMI/DP, but we also enable it for CRT to make it
9004 * possible to share the DPLL between CRT and HDMI. Enabling
9005 * the clock needlessly does no real harm, except use up a
9006 * bit of power potentially.
9008 * We'll limit this to IVB with 3 pipes, since it has only two
9009 * DPLLs and so DPLL sharing is the only way to get three pipes
9010 * driving PCH ports at the same time. On SNB we could do this,
9011 * and potentially avoid enabling the second DPLL, but it's not
9012 * clear if it''s a win or loss power wise. No point in doing
9013 * this on ILK at all since it has a fixed DPLL<->pipe mapping.
9015 if (INTEL_INFO(dev_priv
)->num_pipes
== 3 &&
9016 intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_ANALOG
))
9017 dpll
|= DPLL_SDVO_HIGH_SPEED
;
9019 /* compute bitmask from p1 value */
9020 dpll
|= (1 << (crtc_state
->dpll
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
9022 dpll
|= (1 << (crtc_state
->dpll
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
9024 switch (crtc_state
->dpll
.p2
) {
9026 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
9029 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
9032 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
9035 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
9039 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
9040 intel_panel_use_ssc(dev_priv
))
9041 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
9043 dpll
|= PLL_REF_INPUT_DREFCLK
;
9045 dpll
|= DPLL_VCO_ENABLE
;
9047 crtc_state
->dpll_hw_state
.dpll
= dpll
;
9048 crtc_state
->dpll_hw_state
.fp0
= fp
;
9049 crtc_state
->dpll_hw_state
.fp1
= fp2
;
9052 static int ironlake_crtc_compute_clock(struct intel_crtc
*crtc
,
9053 struct intel_crtc_state
*crtc_state
)
9055 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
9056 const struct intel_limit
*limit
;
9057 int refclk
= 120000;
9059 memset(&crtc_state
->dpll_hw_state
, 0,
9060 sizeof(crtc_state
->dpll_hw_state
));
9062 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
9063 if (!crtc_state
->has_pch_encoder
)
9066 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
9067 if (intel_panel_use_ssc(dev_priv
)) {
9068 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
9069 dev_priv
->vbt
.lvds_ssc_freq
);
9070 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
9073 if (intel_is_dual_link_lvds(dev_priv
)) {
9074 if (refclk
== 100000)
9075 limit
= &intel_limits_ironlake_dual_lvds_100m
;
9077 limit
= &intel_limits_ironlake_dual_lvds
;
9079 if (refclk
== 100000)
9080 limit
= &intel_limits_ironlake_single_lvds_100m
;
9082 limit
= &intel_limits_ironlake_single_lvds
;
9085 limit
= &intel_limits_ironlake_dac
;
9088 if (!crtc_state
->clock_set
&&
9089 !g4x_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
9090 refclk
, NULL
, &crtc_state
->dpll
)) {
9091 DRM_ERROR("Couldn't find PLL settings for mode!\n");
9095 ironlake_compute_dpll(crtc
, crtc_state
, NULL
);
9097 if (!intel_get_shared_dpll(crtc_state
, NULL
)) {
9098 DRM_DEBUG_KMS("failed to find PLL for pipe %c\n",
9099 pipe_name(crtc
->pipe
));
9106 static void intel_pch_transcoder_get_m_n(struct intel_crtc
*crtc
,
9107 struct intel_link_m_n
*m_n
)
9109 struct drm_device
*dev
= crtc
->base
.dev
;
9110 struct drm_i915_private
*dev_priv
= to_i915(dev
);
9111 enum pipe pipe
= crtc
->pipe
;
9113 m_n
->link_m
= I915_READ(PCH_TRANS_LINK_M1(pipe
));
9114 m_n
->link_n
= I915_READ(PCH_TRANS_LINK_N1(pipe
));
9115 m_n
->gmch_m
= I915_READ(PCH_TRANS_DATA_M1(pipe
))
9117 m_n
->gmch_n
= I915_READ(PCH_TRANS_DATA_N1(pipe
));
9118 m_n
->tu
= ((I915_READ(PCH_TRANS_DATA_M1(pipe
))
9119 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
9122 static void intel_cpu_transcoder_get_m_n(struct intel_crtc
*crtc
,
9123 enum transcoder transcoder
,
9124 struct intel_link_m_n
*m_n
,
9125 struct intel_link_m_n
*m2_n2
)
9127 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
9128 enum pipe pipe
= crtc
->pipe
;
9130 if (INTEL_GEN(dev_priv
) >= 5) {
9131 m_n
->link_m
= I915_READ(PIPE_LINK_M1(transcoder
));
9132 m_n
->link_n
= I915_READ(PIPE_LINK_N1(transcoder
));
9133 m_n
->gmch_m
= I915_READ(PIPE_DATA_M1(transcoder
))
9135 m_n
->gmch_n
= I915_READ(PIPE_DATA_N1(transcoder
));
9136 m_n
->tu
= ((I915_READ(PIPE_DATA_M1(transcoder
))
9137 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
9139 if (m2_n2
&& transcoder_has_m2_n2(dev_priv
, transcoder
)) {
9140 m2_n2
->link_m
= I915_READ(PIPE_LINK_M2(transcoder
));
9141 m2_n2
->link_n
= I915_READ(PIPE_LINK_N2(transcoder
));
9142 m2_n2
->gmch_m
= I915_READ(PIPE_DATA_M2(transcoder
))
9144 m2_n2
->gmch_n
= I915_READ(PIPE_DATA_N2(transcoder
));
9145 m2_n2
->tu
= ((I915_READ(PIPE_DATA_M2(transcoder
))
9146 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
9149 m_n
->link_m
= I915_READ(PIPE_LINK_M_G4X(pipe
));
9150 m_n
->link_n
= I915_READ(PIPE_LINK_N_G4X(pipe
));
9151 m_n
->gmch_m
= I915_READ(PIPE_DATA_M_G4X(pipe
))
9153 m_n
->gmch_n
= I915_READ(PIPE_DATA_N_G4X(pipe
));
9154 m_n
->tu
= ((I915_READ(PIPE_DATA_M_G4X(pipe
))
9155 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
9159 void intel_dp_get_m_n(struct intel_crtc
*crtc
,
9160 struct intel_crtc_state
*pipe_config
)
9162 if (pipe_config
->has_pch_encoder
)
9163 intel_pch_transcoder_get_m_n(crtc
, &pipe_config
->dp_m_n
);
9165 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
9166 &pipe_config
->dp_m_n
,
9167 &pipe_config
->dp_m2_n2
);
9170 static void ironlake_get_fdi_m_n_config(struct intel_crtc
*crtc
,
9171 struct intel_crtc_state
*pipe_config
)
9173 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
9174 &pipe_config
->fdi_m_n
, NULL
);
9177 static void skylake_get_pfit_config(struct intel_crtc
*crtc
,
9178 struct intel_crtc_state
*pipe_config
)
9180 struct drm_device
*dev
= crtc
->base
.dev
;
9181 struct drm_i915_private
*dev_priv
= to_i915(dev
);
9182 struct intel_crtc_scaler_state
*scaler_state
= &pipe_config
->scaler_state
;
9187 /* find scaler attached to this pipe */
9188 for (i
= 0; i
< crtc
->num_scalers
; i
++) {
9189 ps_ctrl
= I915_READ(SKL_PS_CTRL(crtc
->pipe
, i
));
9190 if (ps_ctrl
& PS_SCALER_EN
&& !(ps_ctrl
& PS_PLANE_SEL_MASK
)) {
9192 pipe_config
->pch_pfit
.enabled
= true;
9193 pipe_config
->pch_pfit
.pos
= I915_READ(SKL_PS_WIN_POS(crtc
->pipe
, i
));
9194 pipe_config
->pch_pfit
.size
= I915_READ(SKL_PS_WIN_SZ(crtc
->pipe
, i
));
9195 scaler_state
->scalers
[i
].in_use
= true;
9200 scaler_state
->scaler_id
= id
;
9202 scaler_state
->scaler_users
|= (1 << SKL_CRTC_INDEX
);
9204 scaler_state
->scaler_users
&= ~(1 << SKL_CRTC_INDEX
);
9209 skylake_get_initial_plane_config(struct intel_crtc
*crtc
,
9210 struct intel_initial_plane_config
*plane_config
)
9212 struct drm_device
*dev
= crtc
->base
.dev
;
9213 struct drm_i915_private
*dev_priv
= to_i915(dev
);
9214 struct intel_plane
*plane
= to_intel_plane(crtc
->base
.primary
);
9215 enum plane_id plane_id
= plane
->id
;
9217 u32 val
, base
, offset
, stride_mult
, tiling
, alpha
;
9218 int fourcc
, pixel_format
;
9219 unsigned int aligned_height
;
9220 struct drm_framebuffer
*fb
;
9221 struct intel_framebuffer
*intel_fb
;
9223 if (!plane
->get_hw_state(plane
, &pipe
))
9226 WARN_ON(pipe
!= crtc
->pipe
);
9228 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
9230 DRM_DEBUG_KMS("failed to alloc fb\n");
9234 fb
= &intel_fb
->base
;
9238 val
= I915_READ(PLANE_CTL(pipe
, plane_id
));
9240 if (INTEL_GEN(dev_priv
) >= 11)
9241 pixel_format
= val
& ICL_PLANE_CTL_FORMAT_MASK
;
9243 pixel_format
= val
& PLANE_CTL_FORMAT_MASK
;
9245 if (INTEL_GEN(dev_priv
) >= 10 || IS_GEMINILAKE(dev_priv
)) {
9246 alpha
= I915_READ(PLANE_COLOR_CTL(pipe
, plane_id
));
9247 alpha
&= PLANE_COLOR_ALPHA_MASK
;
9249 alpha
= val
& PLANE_CTL_ALPHA_MASK
;
9252 fourcc
= skl_format_to_fourcc(pixel_format
,
9253 val
& PLANE_CTL_ORDER_RGBX
, alpha
);
9254 fb
->format
= drm_format_info(fourcc
);
9256 tiling
= val
& PLANE_CTL_TILED_MASK
;
9258 case PLANE_CTL_TILED_LINEAR
:
9259 fb
->modifier
= DRM_FORMAT_MOD_LINEAR
;
9261 case PLANE_CTL_TILED_X
:
9262 plane_config
->tiling
= I915_TILING_X
;
9263 fb
->modifier
= I915_FORMAT_MOD_X_TILED
;
9265 case PLANE_CTL_TILED_Y
:
9266 plane_config
->tiling
= I915_TILING_Y
;
9267 if (val
& PLANE_CTL_RENDER_DECOMPRESSION_ENABLE
)
9268 fb
->modifier
= I915_FORMAT_MOD_Y_TILED_CCS
;
9270 fb
->modifier
= I915_FORMAT_MOD_Y_TILED
;
9272 case PLANE_CTL_TILED_YF
:
9273 if (val
& PLANE_CTL_RENDER_DECOMPRESSION_ENABLE
)
9274 fb
->modifier
= I915_FORMAT_MOD_Yf_TILED_CCS
;
9276 fb
->modifier
= I915_FORMAT_MOD_Yf_TILED
;
9279 MISSING_CASE(tiling
);
9284 * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
9285 * while i915 HW rotation is clockwise, thats why this swapping.
9287 switch (val
& PLANE_CTL_ROTATE_MASK
) {
9288 case PLANE_CTL_ROTATE_0
:
9289 plane_config
->rotation
= DRM_MODE_ROTATE_0
;
9291 case PLANE_CTL_ROTATE_90
:
9292 plane_config
->rotation
= DRM_MODE_ROTATE_270
;
9294 case PLANE_CTL_ROTATE_180
:
9295 plane_config
->rotation
= DRM_MODE_ROTATE_180
;
9297 case PLANE_CTL_ROTATE_270
:
9298 plane_config
->rotation
= DRM_MODE_ROTATE_90
;
9302 if (INTEL_GEN(dev_priv
) >= 10 &&
9303 val
& PLANE_CTL_FLIP_HORIZONTAL
)
9304 plane_config
->rotation
|= DRM_MODE_REFLECT_X
;
9306 base
= I915_READ(PLANE_SURF(pipe
, plane_id
)) & 0xfffff000;
9307 plane_config
->base
= base
;
9309 offset
= I915_READ(PLANE_OFFSET(pipe
, plane_id
));
9311 val
= I915_READ(PLANE_SIZE(pipe
, plane_id
));
9312 fb
->height
= ((val
>> 16) & 0xfff) + 1;
9313 fb
->width
= ((val
>> 0) & 0x1fff) + 1;
9315 val
= I915_READ(PLANE_STRIDE(pipe
, plane_id
));
9316 stride_mult
= skl_plane_stride_mult(fb
, 0, DRM_MODE_ROTATE_0
);
9317 fb
->pitches
[0] = (val
& 0x3ff) * stride_mult
;
9319 aligned_height
= intel_fb_align_height(fb
, 0, fb
->height
);
9321 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
9323 DRM_DEBUG_KMS("%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9324 crtc
->base
.name
, plane
->base
.name
, fb
->width
, fb
->height
,
9325 fb
->format
->cpp
[0] * 8, base
, fb
->pitches
[0],
9326 plane_config
->size
);
9328 plane_config
->fb
= intel_fb
;
9335 static void ironlake_get_pfit_config(struct intel_crtc
*crtc
,
9336 struct intel_crtc_state
*pipe_config
)
9338 struct drm_device
*dev
= crtc
->base
.dev
;
9339 struct drm_i915_private
*dev_priv
= to_i915(dev
);
9342 tmp
= I915_READ(PF_CTL(crtc
->pipe
));
9344 if (tmp
& PF_ENABLE
) {
9345 pipe_config
->pch_pfit
.enabled
= true;
9346 pipe_config
->pch_pfit
.pos
= I915_READ(PF_WIN_POS(crtc
->pipe
));
9347 pipe_config
->pch_pfit
.size
= I915_READ(PF_WIN_SZ(crtc
->pipe
));
9349 /* We currently do not free assignements of panel fitters on
9350 * ivb/hsw (since we don't use the higher upscaling modes which
9351 * differentiates them) so just WARN about this case for now. */
9352 if (IS_GEN(dev_priv
, 7)) {
9353 WARN_ON((tmp
& PF_PIPE_SEL_MASK_IVB
) !=
9354 PF_PIPE_SEL_IVB(crtc
->pipe
));
9359 static bool ironlake_get_pipe_config(struct intel_crtc
*crtc
,
9360 struct intel_crtc_state
*pipe_config
)
9362 struct drm_device
*dev
= crtc
->base
.dev
;
9363 struct drm_i915_private
*dev_priv
= to_i915(dev
);
9364 enum intel_display_power_domain power_domain
;
9365 intel_wakeref_t wakeref
;
9369 power_domain
= POWER_DOMAIN_PIPE(crtc
->pipe
);
9370 wakeref
= intel_display_power_get_if_enabled(dev_priv
, power_domain
);
9374 pipe_config
->output_format
= INTEL_OUTPUT_FORMAT_RGB
;
9375 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
9376 pipe_config
->shared_dpll
= NULL
;
9379 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
9380 if (!(tmp
& PIPECONF_ENABLE
))
9383 switch (tmp
& PIPECONF_BPC_MASK
) {
9385 pipe_config
->pipe_bpp
= 18;
9388 pipe_config
->pipe_bpp
= 24;
9390 case PIPECONF_10BPC
:
9391 pipe_config
->pipe_bpp
= 30;
9393 case PIPECONF_12BPC
:
9394 pipe_config
->pipe_bpp
= 36;
9400 if (tmp
& PIPECONF_COLOR_RANGE_SELECT
)
9401 pipe_config
->limited_color_range
= true;
9403 pipe_config
->gamma_mode
= (tmp
& PIPECONF_GAMMA_MODE_MASK_ILK
) >>
9404 PIPECONF_GAMMA_MODE_SHIFT
;
9406 pipe_config
->csc_mode
= I915_READ(PIPE_CSC_MODE(crtc
->pipe
));
9408 i9xx_get_pipe_color_config(pipe_config
);
9410 if (I915_READ(PCH_TRANSCONF(crtc
->pipe
)) & TRANS_ENABLE
) {
9411 struct intel_shared_dpll
*pll
;
9412 enum intel_dpll_id pll_id
;
9414 pipe_config
->has_pch_encoder
= true;
9416 tmp
= I915_READ(FDI_RX_CTL(crtc
->pipe
));
9417 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
9418 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
9420 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
9422 if (HAS_PCH_IBX(dev_priv
)) {
9424 * The pipe->pch transcoder and pch transcoder->pll
9427 pll_id
= (enum intel_dpll_id
) crtc
->pipe
;
9429 tmp
= I915_READ(PCH_DPLL_SEL
);
9430 if (tmp
& TRANS_DPLLB_SEL(crtc
->pipe
))
9431 pll_id
= DPLL_ID_PCH_PLL_B
;
9433 pll_id
= DPLL_ID_PCH_PLL_A
;
9436 pipe_config
->shared_dpll
=
9437 intel_get_shared_dpll_by_id(dev_priv
, pll_id
);
9438 pll
= pipe_config
->shared_dpll
;
9440 WARN_ON(!pll
->info
->funcs
->get_hw_state(dev_priv
, pll
,
9441 &pipe_config
->dpll_hw_state
));
9443 tmp
= pipe_config
->dpll_hw_state
.dpll
;
9444 pipe_config
->pixel_multiplier
=
9445 ((tmp
& PLL_REF_SDVO_HDMI_MULTIPLIER_MASK
)
9446 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
) + 1;
9448 ironlake_pch_clock_get(crtc
, pipe_config
);
9450 pipe_config
->pixel_multiplier
= 1;
9453 intel_get_pipe_timings(crtc
, pipe_config
);
9454 intel_get_pipe_src_size(crtc
, pipe_config
);
9456 ironlake_get_pfit_config(crtc
, pipe_config
);
9461 intel_display_power_put(dev_priv
, power_domain
, wakeref
);
9466 static void assert_can_disable_lcpll(struct drm_i915_private
*dev_priv
)
9468 struct drm_device
*dev
= &dev_priv
->drm
;
9469 struct intel_crtc
*crtc
;
9471 for_each_intel_crtc(dev
, crtc
)
9472 I915_STATE_WARN(crtc
->active
, "CRTC for pipe %c enabled\n",
9473 pipe_name(crtc
->pipe
));
9475 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_CTL2
),
9476 "Display power well on\n");
9477 I915_STATE_WARN(I915_READ(SPLL_CTL
) & SPLL_PLL_ENABLE
, "SPLL enabled\n");
9478 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE
, "WRPLL1 enabled\n");
9479 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE
, "WRPLL2 enabled\n");
9480 I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON
, "Panel power on\n");
9481 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2
) & BLM_PWM_ENABLE
,
9482 "CPU PWM1 enabled\n");
9483 if (IS_HASWELL(dev_priv
))
9484 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL
) & BLM_PWM_ENABLE
,
9485 "CPU PWM2 enabled\n");
9486 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1
) & BLM_PCH_PWM_ENABLE
,
9487 "PCH PWM1 enabled\n");
9488 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL
) & UTIL_PIN_ENABLE
,
9489 "Utility pin enabled\n");
9490 I915_STATE_WARN(I915_READ(PCH_GTC_CTL
) & PCH_GTC_ENABLE
, "PCH GTC enabled\n");
9493 * In theory we can still leave IRQs enabled, as long as only the HPD
9494 * interrupts remain enabled. We used to check for that, but since it's
9495 * gen-specific and since we only disable LCPLL after we fully disable
9496 * the interrupts, the check below should be enough.
9498 I915_STATE_WARN(intel_irqs_enabled(dev_priv
), "IRQs enabled\n");
9501 static u32
hsw_read_dcomp(struct drm_i915_private
*dev_priv
)
9503 if (IS_HASWELL(dev_priv
))
9504 return I915_READ(D_COMP_HSW
);
9506 return I915_READ(D_COMP_BDW
);
9509 static void hsw_write_dcomp(struct drm_i915_private
*dev_priv
, u32 val
)
9511 if (IS_HASWELL(dev_priv
)) {
9512 if (sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_D_COMP
,
9514 DRM_DEBUG_KMS("Failed to write to D_COMP\n");
9516 I915_WRITE(D_COMP_BDW
, val
);
9517 POSTING_READ(D_COMP_BDW
);
9522 * This function implements pieces of two sequences from BSpec:
9523 * - Sequence for display software to disable LCPLL
9524 * - Sequence for display software to allow package C8+
9525 * The steps implemented here are just the steps that actually touch the LCPLL
9526 * register. Callers should take care of disabling all the display engine
9527 * functions, doing the mode unset, fixing interrupts, etc.
9529 static void hsw_disable_lcpll(struct drm_i915_private
*dev_priv
,
9530 bool switch_to_fclk
, bool allow_power_down
)
9534 assert_can_disable_lcpll(dev_priv
);
9536 val
= I915_READ(LCPLL_CTL
);
9538 if (switch_to_fclk
) {
9539 val
|= LCPLL_CD_SOURCE_FCLK
;
9540 I915_WRITE(LCPLL_CTL
, val
);
9542 if (wait_for_us(I915_READ(LCPLL_CTL
) &
9543 LCPLL_CD_SOURCE_FCLK_DONE
, 1))
9544 DRM_ERROR("Switching to FCLK failed\n");
9546 val
= I915_READ(LCPLL_CTL
);
9549 val
|= LCPLL_PLL_DISABLE
;
9550 I915_WRITE(LCPLL_CTL
, val
);
9551 POSTING_READ(LCPLL_CTL
);
9553 if (intel_wait_for_register(&dev_priv
->uncore
,
9554 LCPLL_CTL
, LCPLL_PLL_LOCK
, 0, 1))
9555 DRM_ERROR("LCPLL still locked\n");
9557 val
= hsw_read_dcomp(dev_priv
);
9558 val
|= D_COMP_COMP_DISABLE
;
9559 hsw_write_dcomp(dev_priv
, val
);
9562 if (wait_for((hsw_read_dcomp(dev_priv
) & D_COMP_RCOMP_IN_PROGRESS
) == 0,
9564 DRM_ERROR("D_COMP RCOMP still in progress\n");
9566 if (allow_power_down
) {
9567 val
= I915_READ(LCPLL_CTL
);
9568 val
|= LCPLL_POWER_DOWN_ALLOW
;
9569 I915_WRITE(LCPLL_CTL
, val
);
9570 POSTING_READ(LCPLL_CTL
);
9575 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9578 static void hsw_restore_lcpll(struct drm_i915_private
*dev_priv
)
9582 val
= I915_READ(LCPLL_CTL
);
9584 if ((val
& (LCPLL_PLL_LOCK
| LCPLL_PLL_DISABLE
| LCPLL_CD_SOURCE_FCLK
|
9585 LCPLL_POWER_DOWN_ALLOW
)) == LCPLL_PLL_LOCK
)
9589 * Make sure we're not on PC8 state before disabling PC8, otherwise
9590 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9592 intel_uncore_forcewake_get(&dev_priv
->uncore
, FORCEWAKE_ALL
);
9594 if (val
& LCPLL_POWER_DOWN_ALLOW
) {
9595 val
&= ~LCPLL_POWER_DOWN_ALLOW
;
9596 I915_WRITE(LCPLL_CTL
, val
);
9597 POSTING_READ(LCPLL_CTL
);
9600 val
= hsw_read_dcomp(dev_priv
);
9601 val
|= D_COMP_COMP_FORCE
;
9602 val
&= ~D_COMP_COMP_DISABLE
;
9603 hsw_write_dcomp(dev_priv
, val
);
9605 val
= I915_READ(LCPLL_CTL
);
9606 val
&= ~LCPLL_PLL_DISABLE
;
9607 I915_WRITE(LCPLL_CTL
, val
);
9609 if (intel_wait_for_register(&dev_priv
->uncore
,
9610 LCPLL_CTL
, LCPLL_PLL_LOCK
, LCPLL_PLL_LOCK
,
9612 DRM_ERROR("LCPLL not locked yet\n");
9614 if (val
& LCPLL_CD_SOURCE_FCLK
) {
9615 val
= I915_READ(LCPLL_CTL
);
9616 val
&= ~LCPLL_CD_SOURCE_FCLK
;
9617 I915_WRITE(LCPLL_CTL
, val
);
9619 if (wait_for_us((I915_READ(LCPLL_CTL
) &
9620 LCPLL_CD_SOURCE_FCLK_DONE
) == 0, 1))
9621 DRM_ERROR("Switching back to LCPLL failed\n");
9624 intel_uncore_forcewake_put(&dev_priv
->uncore
, FORCEWAKE_ALL
);
9626 intel_update_cdclk(dev_priv
);
9627 intel_dump_cdclk_state(&dev_priv
->cdclk
.hw
, "Current CDCLK");
9631 * Package states C8 and deeper are really deep PC states that can only be
9632 * reached when all the devices on the system allow it, so even if the graphics
9633 * device allows PC8+, it doesn't mean the system will actually get to these
9634 * states. Our driver only allows PC8+ when going into runtime PM.
9636 * The requirements for PC8+ are that all the outputs are disabled, the power
9637 * well is disabled and most interrupts are disabled, and these are also
9638 * requirements for runtime PM. When these conditions are met, we manually do
9639 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9640 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9643 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9644 * the state of some registers, so when we come back from PC8+ we need to
9645 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9646 * need to take care of the registers kept by RC6. Notice that this happens even
9647 * if we don't put the device in PCI D3 state (which is what currently happens
9648 * because of the runtime PM support).
9650 * For more, read "Display Sequences for Package C8" on the hardware
9653 void hsw_enable_pc8(struct drm_i915_private
*dev_priv
)
9657 DRM_DEBUG_KMS("Enabling package C8+\n");
9659 if (HAS_PCH_LPT_LP(dev_priv
)) {
9660 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
9661 val
&= ~PCH_LP_PARTITION_LEVEL_DISABLE
;
9662 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
9665 lpt_disable_clkout_dp(dev_priv
);
9666 hsw_disable_lcpll(dev_priv
, true, true);
9669 void hsw_disable_pc8(struct drm_i915_private
*dev_priv
)
9673 DRM_DEBUG_KMS("Disabling package C8+\n");
9675 hsw_restore_lcpll(dev_priv
);
9676 lpt_init_pch_refclk(dev_priv
);
9678 if (HAS_PCH_LPT_LP(dev_priv
)) {
9679 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
9680 val
|= PCH_LP_PARTITION_LEVEL_DISABLE
;
9681 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
9685 static int haswell_crtc_compute_clock(struct intel_crtc
*crtc
,
9686 struct intel_crtc_state
*crtc_state
)
9688 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
9689 struct intel_atomic_state
*state
=
9690 to_intel_atomic_state(crtc_state
->base
.state
);
9692 if (!intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_DSI
) ||
9693 INTEL_GEN(dev_priv
) >= 11) {
9694 struct intel_encoder
*encoder
=
9695 intel_get_crtc_new_encoder(state
, crtc_state
);
9697 if (!intel_get_shared_dpll(crtc_state
, encoder
)) {
9698 DRM_DEBUG_KMS("failed to find PLL for pipe %c\n",
9699 pipe_name(crtc
->pipe
));
9707 static void cannonlake_get_ddi_pll(struct drm_i915_private
*dev_priv
,
9709 struct intel_crtc_state
*pipe_config
)
9711 enum intel_dpll_id id
;
9714 temp
= I915_READ(DPCLKA_CFGCR0
) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port
);
9715 id
= temp
>> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port
);
9717 if (WARN_ON(id
< SKL_DPLL0
|| id
> SKL_DPLL2
))
9720 pipe_config
->shared_dpll
= intel_get_shared_dpll_by_id(dev_priv
, id
);
9723 static void icelake_get_ddi_pll(struct drm_i915_private
*dev_priv
,
9725 struct intel_crtc_state
*pipe_config
)
9727 enum intel_dpll_id id
;
9730 /* TODO: TBT pll not implemented. */
9731 if (intel_port_is_combophy(dev_priv
, port
)) {
9732 temp
= I915_READ(DPCLKA_CFGCR0_ICL
) &
9733 DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port
);
9734 id
= temp
>> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port
);
9735 } else if (intel_port_is_tc(dev_priv
, port
)) {
9736 id
= icl_tc_port_to_pll_id(intel_port_to_tc(dev_priv
, port
));
9738 WARN(1, "Invalid port %x\n", port
);
9742 pipe_config
->shared_dpll
= intel_get_shared_dpll_by_id(dev_priv
, id
);
9745 static void bxt_get_ddi_pll(struct drm_i915_private
*dev_priv
,
9747 struct intel_crtc_state
*pipe_config
)
9749 enum intel_dpll_id id
;
9753 id
= DPLL_ID_SKL_DPLL0
;
9756 id
= DPLL_ID_SKL_DPLL1
;
9759 id
= DPLL_ID_SKL_DPLL2
;
9762 DRM_ERROR("Incorrect port type\n");
9766 pipe_config
->shared_dpll
= intel_get_shared_dpll_by_id(dev_priv
, id
);
9769 static void skylake_get_ddi_pll(struct drm_i915_private
*dev_priv
,
9771 struct intel_crtc_state
*pipe_config
)
9773 enum intel_dpll_id id
;
9776 temp
= I915_READ(DPLL_CTRL2
) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port
);
9777 id
= temp
>> (port
* 3 + 1);
9779 if (WARN_ON(id
< SKL_DPLL0
|| id
> SKL_DPLL3
))
9782 pipe_config
->shared_dpll
= intel_get_shared_dpll_by_id(dev_priv
, id
);
9785 static void haswell_get_ddi_pll(struct drm_i915_private
*dev_priv
,
9787 struct intel_crtc_state
*pipe_config
)
9789 enum intel_dpll_id id
;
9790 u32 ddi_pll_sel
= I915_READ(PORT_CLK_SEL(port
));
9792 switch (ddi_pll_sel
) {
9793 case PORT_CLK_SEL_WRPLL1
:
9794 id
= DPLL_ID_WRPLL1
;
9796 case PORT_CLK_SEL_WRPLL2
:
9797 id
= DPLL_ID_WRPLL2
;
9799 case PORT_CLK_SEL_SPLL
:
9802 case PORT_CLK_SEL_LCPLL_810
:
9803 id
= DPLL_ID_LCPLL_810
;
9805 case PORT_CLK_SEL_LCPLL_1350
:
9806 id
= DPLL_ID_LCPLL_1350
;
9808 case PORT_CLK_SEL_LCPLL_2700
:
9809 id
= DPLL_ID_LCPLL_2700
;
9812 MISSING_CASE(ddi_pll_sel
);
9814 case PORT_CLK_SEL_NONE
:
9818 pipe_config
->shared_dpll
= intel_get_shared_dpll_by_id(dev_priv
, id
);
9821 static bool hsw_get_transcoder_state(struct intel_crtc
*crtc
,
9822 struct intel_crtc_state
*pipe_config
,
9823 u64
*power_domain_mask
,
9824 intel_wakeref_t
*wakerefs
)
9826 struct drm_device
*dev
= crtc
->base
.dev
;
9827 struct drm_i915_private
*dev_priv
= to_i915(dev
);
9828 enum intel_display_power_domain power_domain
;
9829 unsigned long panel_transcoder_mask
= 0;
9830 unsigned long enabled_panel_transcoders
= 0;
9831 enum transcoder panel_transcoder
;
9835 if (INTEL_GEN(dev_priv
) >= 11)
9836 panel_transcoder_mask
|=
9837 BIT(TRANSCODER_DSI_0
) | BIT(TRANSCODER_DSI_1
);
9839 if (HAS_TRANSCODER_EDP(dev_priv
))
9840 panel_transcoder_mask
|= BIT(TRANSCODER_EDP
);
9843 * The pipe->transcoder mapping is fixed with the exception of the eDP
9844 * and DSI transcoders handled below.
9846 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
9849 * XXX: Do intel_display_power_get_if_enabled before reading this (for
9850 * consistency and less surprising code; it's in always on power).
9852 for_each_set_bit(panel_transcoder
,
9853 &panel_transcoder_mask
,
9854 ARRAY_SIZE(INTEL_INFO(dev_priv
)->trans_offsets
)) {
9855 enum pipe trans_pipe
;
9857 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(panel_transcoder
));
9858 if (!(tmp
& TRANS_DDI_FUNC_ENABLE
))
9862 * Log all enabled ones, only use the first one.
9864 * FIXME: This won't work for two separate DSI displays.
9866 enabled_panel_transcoders
|= BIT(panel_transcoder
);
9867 if (enabled_panel_transcoders
!= BIT(panel_transcoder
))
9870 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
9872 WARN(1, "unknown pipe linked to transcoder %s\n",
9873 transcoder_name(panel_transcoder
));
9875 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
9876 case TRANS_DDI_EDP_INPUT_A_ON
:
9877 trans_pipe
= PIPE_A
;
9879 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
9880 trans_pipe
= PIPE_B
;
9882 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
9883 trans_pipe
= PIPE_C
;
9887 if (trans_pipe
== crtc
->pipe
)
9888 pipe_config
->cpu_transcoder
= panel_transcoder
;
9892 * Valid combos: none, eDP, DSI0, DSI1, DSI0+DSI1
9894 WARN_ON((enabled_panel_transcoders
& BIT(TRANSCODER_EDP
)) &&
9895 enabled_panel_transcoders
!= BIT(TRANSCODER_EDP
));
9897 power_domain
= POWER_DOMAIN_TRANSCODER(pipe_config
->cpu_transcoder
);
9898 WARN_ON(*power_domain_mask
& BIT_ULL(power_domain
));
9900 wf
= intel_display_power_get_if_enabled(dev_priv
, power_domain
);
9904 wakerefs
[power_domain
] = wf
;
9905 *power_domain_mask
|= BIT_ULL(power_domain
);
9907 tmp
= I915_READ(PIPECONF(pipe_config
->cpu_transcoder
));
9909 return tmp
& PIPECONF_ENABLE
;
9912 static bool bxt_get_dsi_transcoder_state(struct intel_crtc
*crtc
,
9913 struct intel_crtc_state
*pipe_config
,
9914 u64
*power_domain_mask
,
9915 intel_wakeref_t
*wakerefs
)
9917 struct drm_device
*dev
= crtc
->base
.dev
;
9918 struct drm_i915_private
*dev_priv
= to_i915(dev
);
9919 enum intel_display_power_domain power_domain
;
9920 enum transcoder cpu_transcoder
;
9925 for_each_port_masked(port
, BIT(PORT_A
) | BIT(PORT_C
)) {
9927 cpu_transcoder
= TRANSCODER_DSI_A
;
9929 cpu_transcoder
= TRANSCODER_DSI_C
;
9931 power_domain
= POWER_DOMAIN_TRANSCODER(cpu_transcoder
);
9932 WARN_ON(*power_domain_mask
& BIT_ULL(power_domain
));
9934 wf
= intel_display_power_get_if_enabled(dev_priv
, power_domain
);
9938 wakerefs
[power_domain
] = wf
;
9939 *power_domain_mask
|= BIT_ULL(power_domain
);
9942 * The PLL needs to be enabled with a valid divider
9943 * configuration, otherwise accessing DSI registers will hang
9944 * the machine. See BSpec North Display Engine
9945 * registers/MIPI[BXT]. We can break out here early, since we
9946 * need the same DSI PLL to be enabled for both DSI ports.
9948 if (!bxt_dsi_pll_is_enabled(dev_priv
))
9951 /* XXX: this works for video mode only */
9952 tmp
= I915_READ(BXT_MIPI_PORT_CTRL(port
));
9953 if (!(tmp
& DPI_ENABLE
))
9956 tmp
= I915_READ(MIPI_CTRL(port
));
9957 if ((tmp
& BXT_PIPE_SELECT_MASK
) != BXT_PIPE_SELECT(crtc
->pipe
))
9960 pipe_config
->cpu_transcoder
= cpu_transcoder
;
9964 return transcoder_is_dsi(pipe_config
->cpu_transcoder
);
9967 static void haswell_get_ddi_port_state(struct intel_crtc
*crtc
,
9968 struct intel_crtc_state
*pipe_config
)
9970 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
9971 struct intel_shared_dpll
*pll
;
9975 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(pipe_config
->cpu_transcoder
));
9977 port
= (tmp
& TRANS_DDI_PORT_MASK
) >> TRANS_DDI_PORT_SHIFT
;
9979 if (INTEL_GEN(dev_priv
) >= 11)
9980 icelake_get_ddi_pll(dev_priv
, port
, pipe_config
);
9981 else if (IS_CANNONLAKE(dev_priv
))
9982 cannonlake_get_ddi_pll(dev_priv
, port
, pipe_config
);
9983 else if (IS_GEN9_BC(dev_priv
))
9984 skylake_get_ddi_pll(dev_priv
, port
, pipe_config
);
9985 else if (IS_GEN9_LP(dev_priv
))
9986 bxt_get_ddi_pll(dev_priv
, port
, pipe_config
);
9988 haswell_get_ddi_pll(dev_priv
, port
, pipe_config
);
9990 pll
= pipe_config
->shared_dpll
;
9992 WARN_ON(!pll
->info
->funcs
->get_hw_state(dev_priv
, pll
,
9993 &pipe_config
->dpll_hw_state
));
9997 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9998 * DDI E. So just check whether this pipe is wired to DDI E and whether
9999 * the PCH transcoder is on.
10001 if (INTEL_GEN(dev_priv
) < 9 &&
10002 (port
== PORT_E
) && I915_READ(LPT_TRANSCONF
) & TRANS_ENABLE
) {
10003 pipe_config
->has_pch_encoder
= true;
10005 tmp
= I915_READ(FDI_RX_CTL(PIPE_A
));
10006 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
10007 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
10009 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
10013 static bool haswell_get_pipe_config(struct intel_crtc
*crtc
,
10014 struct intel_crtc_state
*pipe_config
)
10016 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
10017 intel_wakeref_t wakerefs
[POWER_DOMAIN_NUM
], wf
;
10018 enum intel_display_power_domain power_domain
;
10019 u64 power_domain_mask
;
10022 intel_crtc_init_scalers(crtc
, pipe_config
);
10024 power_domain
= POWER_DOMAIN_PIPE(crtc
->pipe
);
10025 wf
= intel_display_power_get_if_enabled(dev_priv
, power_domain
);
10029 wakerefs
[power_domain
] = wf
;
10030 power_domain_mask
= BIT_ULL(power_domain
);
10032 pipe_config
->shared_dpll
= NULL
;
10034 active
= hsw_get_transcoder_state(crtc
, pipe_config
,
10035 &power_domain_mask
, wakerefs
);
10037 if (IS_GEN9_LP(dev_priv
) &&
10038 bxt_get_dsi_transcoder_state(crtc
, pipe_config
,
10039 &power_domain_mask
, wakerefs
)) {
10047 if (!transcoder_is_dsi(pipe_config
->cpu_transcoder
) ||
10048 INTEL_GEN(dev_priv
) >= 11) {
10049 haswell_get_ddi_port_state(crtc
, pipe_config
);
10050 intel_get_pipe_timings(crtc
, pipe_config
);
10053 intel_get_pipe_src_size(crtc
, pipe_config
);
10054 intel_get_crtc_ycbcr_config(crtc
, pipe_config
);
10056 pipe_config
->gamma_mode
= I915_READ(GAMMA_MODE(crtc
->pipe
));
10058 pipe_config
->csc_mode
= I915_READ(PIPE_CSC_MODE(crtc
->pipe
));
10060 if (INTEL_GEN(dev_priv
) >= 9) {
10061 u32 tmp
= I915_READ(SKL_BOTTOM_COLOR(crtc
->pipe
));
10063 if (tmp
& SKL_BOTTOM_COLOR_GAMMA_ENABLE
)
10064 pipe_config
->gamma_enable
= true;
10066 if (tmp
& SKL_BOTTOM_COLOR_CSC_ENABLE
)
10067 pipe_config
->csc_enable
= true;
10069 i9xx_get_pipe_color_config(pipe_config
);
10072 power_domain
= POWER_DOMAIN_PIPE_PANEL_FITTER(crtc
->pipe
);
10073 WARN_ON(power_domain_mask
& BIT_ULL(power_domain
));
10075 wf
= intel_display_power_get_if_enabled(dev_priv
, power_domain
);
10077 wakerefs
[power_domain
] = wf
;
10078 power_domain_mask
|= BIT_ULL(power_domain
);
10080 if (INTEL_GEN(dev_priv
) >= 9)
10081 skylake_get_pfit_config(crtc
, pipe_config
);
10083 ironlake_get_pfit_config(crtc
, pipe_config
);
10086 if (hsw_crtc_supports_ips(crtc
)) {
10087 if (IS_HASWELL(dev_priv
))
10088 pipe_config
->ips_enabled
= I915_READ(IPS_CTL
) & IPS_ENABLE
;
10091 * We cannot readout IPS state on broadwell, set to
10092 * true so we can set it to a defined state on first
10095 pipe_config
->ips_enabled
= true;
10099 if (pipe_config
->cpu_transcoder
!= TRANSCODER_EDP
&&
10100 !transcoder_is_dsi(pipe_config
->cpu_transcoder
)) {
10101 pipe_config
->pixel_multiplier
=
10102 I915_READ(PIPE_MULT(pipe_config
->cpu_transcoder
)) + 1;
10104 pipe_config
->pixel_multiplier
= 1;
10108 for_each_power_domain(power_domain
, power_domain_mask
)
10109 intel_display_power_put(dev_priv
,
10110 power_domain
, wakerefs
[power_domain
]);
10115 static u32
intel_cursor_base(const struct intel_plane_state
*plane_state
)
10117 struct drm_i915_private
*dev_priv
=
10118 to_i915(plane_state
->base
.plane
->dev
);
10119 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
10120 const struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
10123 if (INTEL_INFO(dev_priv
)->display
.cursor_needs_physical
)
10124 base
= obj
->phys_handle
->busaddr
;
10126 base
= intel_plane_ggtt_offset(plane_state
);
10128 base
+= plane_state
->color_plane
[0].offset
;
10130 /* ILK+ do this automagically */
10131 if (HAS_GMCH(dev_priv
) &&
10132 plane_state
->base
.rotation
& DRM_MODE_ROTATE_180
)
10133 base
+= (plane_state
->base
.crtc_h
*
10134 plane_state
->base
.crtc_w
- 1) * fb
->format
->cpp
[0];
10139 static u32
intel_cursor_position(const struct intel_plane_state
*plane_state
)
10141 int x
= plane_state
->base
.crtc_x
;
10142 int y
= plane_state
->base
.crtc_y
;
10146 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
10149 pos
|= x
<< CURSOR_X_SHIFT
;
10152 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
10155 pos
|= y
<< CURSOR_Y_SHIFT
;
10160 static bool intel_cursor_size_ok(const struct intel_plane_state
*plane_state
)
10162 const struct drm_mode_config
*config
=
10163 &plane_state
->base
.plane
->dev
->mode_config
;
10164 int width
= plane_state
->base
.crtc_w
;
10165 int height
= plane_state
->base
.crtc_h
;
10167 return width
> 0 && width
<= config
->cursor_width
&&
10168 height
> 0 && height
<= config
->cursor_height
;
10171 static int intel_cursor_check_surface(struct intel_plane_state
*plane_state
)
10173 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
10174 unsigned int rotation
= plane_state
->base
.rotation
;
10179 intel_fill_fb_ggtt_view(&plane_state
->view
, fb
, rotation
);
10180 plane_state
->color_plane
[0].stride
= intel_fb_pitch(fb
, 0, rotation
);
10182 ret
= intel_plane_check_stride(plane_state
);
10186 src_x
= plane_state
->base
.src_x
>> 16;
10187 src_y
= plane_state
->base
.src_y
>> 16;
10189 intel_add_fb_offsets(&src_x
, &src_y
, plane_state
, 0);
10190 offset
= intel_plane_compute_aligned_offset(&src_x
, &src_y
,
10193 if (src_x
!= 0 || src_y
!= 0) {
10194 DRM_DEBUG_KMS("Arbitrary cursor panning not supported\n");
10198 plane_state
->color_plane
[0].offset
= offset
;
10203 static int intel_check_cursor(struct intel_crtc_state
*crtc_state
,
10204 struct intel_plane_state
*plane_state
)
10206 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
10209 if (fb
&& fb
->modifier
!= DRM_FORMAT_MOD_LINEAR
) {
10210 DRM_DEBUG_KMS("cursor cannot be tiled\n");
10214 ret
= drm_atomic_helper_check_plane_state(&plane_state
->base
,
10216 DRM_PLANE_HELPER_NO_SCALING
,
10217 DRM_PLANE_HELPER_NO_SCALING
,
10222 if (!plane_state
->base
.visible
)
10225 ret
= intel_plane_check_src_coordinates(plane_state
);
10229 ret
= intel_cursor_check_surface(plane_state
);
10236 static unsigned int
10237 i845_cursor_max_stride(struct intel_plane
*plane
,
10238 u32 pixel_format
, u64 modifier
,
10239 unsigned int rotation
)
10244 static u32
i845_cursor_ctl_crtc(const struct intel_crtc_state
*crtc_state
)
10248 if (crtc_state
->gamma_enable
)
10249 cntl
|= CURSOR_GAMMA_ENABLE
;
10254 static u32
i845_cursor_ctl(const struct intel_crtc_state
*crtc_state
,
10255 const struct intel_plane_state
*plane_state
)
10257 return CURSOR_ENABLE
|
10258 CURSOR_FORMAT_ARGB
|
10259 CURSOR_STRIDE(plane_state
->color_plane
[0].stride
);
10262 static bool i845_cursor_size_ok(const struct intel_plane_state
*plane_state
)
10264 int width
= plane_state
->base
.crtc_w
;
10267 * 845g/865g are only limited by the width of their cursors,
10268 * the height is arbitrary up to the precision of the register.
10270 return intel_cursor_size_ok(plane_state
) && IS_ALIGNED(width
, 64);
10273 static int i845_check_cursor(struct intel_crtc_state
*crtc_state
,
10274 struct intel_plane_state
*plane_state
)
10276 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
10279 ret
= intel_check_cursor(crtc_state
, plane_state
);
10283 /* if we want to turn off the cursor ignore width and height */
10287 /* Check for which cursor types we support */
10288 if (!i845_cursor_size_ok(plane_state
)) {
10289 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
10290 plane_state
->base
.crtc_w
,
10291 plane_state
->base
.crtc_h
);
10295 WARN_ON(plane_state
->base
.visible
&&
10296 plane_state
->color_plane
[0].stride
!= fb
->pitches
[0]);
10298 switch (fb
->pitches
[0]) {
10305 DRM_DEBUG_KMS("Invalid cursor stride (%u)\n",
10310 plane_state
->ctl
= i845_cursor_ctl(crtc_state
, plane_state
);
10315 static void i845_update_cursor(struct intel_plane
*plane
,
10316 const struct intel_crtc_state
*crtc_state
,
10317 const struct intel_plane_state
*plane_state
)
10319 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
10320 u32 cntl
= 0, base
= 0, pos
= 0, size
= 0;
10321 unsigned long irqflags
;
10323 if (plane_state
&& plane_state
->base
.visible
) {
10324 unsigned int width
= plane_state
->base
.crtc_w
;
10325 unsigned int height
= plane_state
->base
.crtc_h
;
10327 cntl
= plane_state
->ctl
|
10328 i845_cursor_ctl_crtc(crtc_state
);
10330 size
= (height
<< 12) | width
;
10332 base
= intel_cursor_base(plane_state
);
10333 pos
= intel_cursor_position(plane_state
);
10336 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
10338 /* On these chipsets we can only modify the base/size/stride
10339 * whilst the cursor is disabled.
10341 if (plane
->cursor
.base
!= base
||
10342 plane
->cursor
.size
!= size
||
10343 plane
->cursor
.cntl
!= cntl
) {
10344 I915_WRITE_FW(CURCNTR(PIPE_A
), 0);
10345 I915_WRITE_FW(CURBASE(PIPE_A
), base
);
10346 I915_WRITE_FW(CURSIZE
, size
);
10347 I915_WRITE_FW(CURPOS(PIPE_A
), pos
);
10348 I915_WRITE_FW(CURCNTR(PIPE_A
), cntl
);
10350 plane
->cursor
.base
= base
;
10351 plane
->cursor
.size
= size
;
10352 plane
->cursor
.cntl
= cntl
;
10354 I915_WRITE_FW(CURPOS(PIPE_A
), pos
);
10357 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
10360 static void i845_disable_cursor(struct intel_plane
*plane
,
10361 const struct intel_crtc_state
*crtc_state
)
10363 i845_update_cursor(plane
, crtc_state
, NULL
);
10366 static bool i845_cursor_get_hw_state(struct intel_plane
*plane
,
10369 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
10370 enum intel_display_power_domain power_domain
;
10371 intel_wakeref_t wakeref
;
10374 power_domain
= POWER_DOMAIN_PIPE(PIPE_A
);
10375 wakeref
= intel_display_power_get_if_enabled(dev_priv
, power_domain
);
10379 ret
= I915_READ(CURCNTR(PIPE_A
)) & CURSOR_ENABLE
;
10383 intel_display_power_put(dev_priv
, power_domain
, wakeref
);
10388 static unsigned int
10389 i9xx_cursor_max_stride(struct intel_plane
*plane
,
10390 u32 pixel_format
, u64 modifier
,
10391 unsigned int rotation
)
10393 return plane
->base
.dev
->mode_config
.cursor_width
* 4;
10396 static u32
i9xx_cursor_ctl_crtc(const struct intel_crtc_state
*crtc_state
)
10398 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
10399 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
10402 if (INTEL_GEN(dev_priv
) >= 11)
10405 if (crtc_state
->gamma_enable
)
10406 cntl
= MCURSOR_GAMMA_ENABLE
;
10408 if (crtc_state
->csc_enable
)
10409 cntl
|= MCURSOR_PIPE_CSC_ENABLE
;
10411 if (INTEL_GEN(dev_priv
) < 5 && !IS_G4X(dev_priv
))
10412 cntl
|= MCURSOR_PIPE_SELECT(crtc
->pipe
);
10417 static u32
i9xx_cursor_ctl(const struct intel_crtc_state
*crtc_state
,
10418 const struct intel_plane_state
*plane_state
)
10420 struct drm_i915_private
*dev_priv
=
10421 to_i915(plane_state
->base
.plane
->dev
);
10424 if (IS_GEN(dev_priv
, 6) || IS_IVYBRIDGE(dev_priv
))
10425 cntl
|= MCURSOR_TRICKLE_FEED_DISABLE
;
10427 switch (plane_state
->base
.crtc_w
) {
10429 cntl
|= MCURSOR_MODE_64_ARGB_AX
;
10432 cntl
|= MCURSOR_MODE_128_ARGB_AX
;
10435 cntl
|= MCURSOR_MODE_256_ARGB_AX
;
10438 MISSING_CASE(plane_state
->base
.crtc_w
);
10442 if (plane_state
->base
.rotation
& DRM_MODE_ROTATE_180
)
10443 cntl
|= MCURSOR_ROTATE_180
;
10448 static bool i9xx_cursor_size_ok(const struct intel_plane_state
*plane_state
)
10450 struct drm_i915_private
*dev_priv
=
10451 to_i915(plane_state
->base
.plane
->dev
);
10452 int width
= plane_state
->base
.crtc_w
;
10453 int height
= plane_state
->base
.crtc_h
;
10455 if (!intel_cursor_size_ok(plane_state
))
10458 /* Cursor width is limited to a few power-of-two sizes */
10469 * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor
10470 * height from 8 lines up to the cursor width, when the
10471 * cursor is not rotated. Everything else requires square
10474 if (HAS_CUR_FBC(dev_priv
) &&
10475 plane_state
->base
.rotation
& DRM_MODE_ROTATE_0
) {
10476 if (height
< 8 || height
> width
)
10479 if (height
!= width
)
10486 static int i9xx_check_cursor(struct intel_crtc_state
*crtc_state
,
10487 struct intel_plane_state
*plane_state
)
10489 struct intel_plane
*plane
= to_intel_plane(plane_state
->base
.plane
);
10490 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
10491 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
10492 enum pipe pipe
= plane
->pipe
;
10495 ret
= intel_check_cursor(crtc_state
, plane_state
);
10499 /* if we want to turn off the cursor ignore width and height */
10503 /* Check for which cursor types we support */
10504 if (!i9xx_cursor_size_ok(plane_state
)) {
10505 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
10506 plane_state
->base
.crtc_w
,
10507 plane_state
->base
.crtc_h
);
10511 WARN_ON(plane_state
->base
.visible
&&
10512 plane_state
->color_plane
[0].stride
!= fb
->pitches
[0]);
10514 if (fb
->pitches
[0] != plane_state
->base
.crtc_w
* fb
->format
->cpp
[0]) {
10515 DRM_DEBUG_KMS("Invalid cursor stride (%u) (cursor width %d)\n",
10516 fb
->pitches
[0], plane_state
->base
.crtc_w
);
10521 * There's something wrong with the cursor on CHV pipe C.
10522 * If it straddles the left edge of the screen then
10523 * moving it away from the edge or disabling it often
10524 * results in a pipe underrun, and often that can lead to
10525 * dead pipe (constant underrun reported, and it scans
10526 * out just a solid color). To recover from that, the
10527 * display power well must be turned off and on again.
10528 * Refuse the put the cursor into that compromised position.
10530 if (IS_CHERRYVIEW(dev_priv
) && pipe
== PIPE_C
&&
10531 plane_state
->base
.visible
&& plane_state
->base
.crtc_x
< 0) {
10532 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
10536 plane_state
->ctl
= i9xx_cursor_ctl(crtc_state
, plane_state
);
10541 static void i9xx_update_cursor(struct intel_plane
*plane
,
10542 const struct intel_crtc_state
*crtc_state
,
10543 const struct intel_plane_state
*plane_state
)
10545 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
10546 enum pipe pipe
= plane
->pipe
;
10547 u32 cntl
= 0, base
= 0, pos
= 0, fbc_ctl
= 0;
10548 unsigned long irqflags
;
10550 if (plane_state
&& plane_state
->base
.visible
) {
10551 cntl
= plane_state
->ctl
|
10552 i9xx_cursor_ctl_crtc(crtc_state
);
10554 if (plane_state
->base
.crtc_h
!= plane_state
->base
.crtc_w
)
10555 fbc_ctl
= CUR_FBC_CTL_EN
| (plane_state
->base
.crtc_h
- 1);
10557 base
= intel_cursor_base(plane_state
);
10558 pos
= intel_cursor_position(plane_state
);
10561 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
10564 * On some platforms writing CURCNTR first will also
10565 * cause CURPOS to be armed by the CURBASE write.
10566 * Without the CURCNTR write the CURPOS write would
10567 * arm itself. Thus we always update CURCNTR before
10570 * On other platforms CURPOS always requires the
10571 * CURBASE write to arm the update. Additonally
10572 * a write to any of the cursor register will cancel
10573 * an already armed cursor update. Thus leaving out
10574 * the CURBASE write after CURPOS could lead to a
10575 * cursor that doesn't appear to move, or even change
10576 * shape. Thus we always write CURBASE.
10578 * The other registers are armed by by the CURBASE write
10579 * except when the plane is getting enabled at which time
10580 * the CURCNTR write arms the update.
10583 if (INTEL_GEN(dev_priv
) >= 9)
10584 skl_write_cursor_wm(plane
, crtc_state
);
10586 if (plane
->cursor
.base
!= base
||
10587 plane
->cursor
.size
!= fbc_ctl
||
10588 plane
->cursor
.cntl
!= cntl
) {
10589 if (HAS_CUR_FBC(dev_priv
))
10590 I915_WRITE_FW(CUR_FBC_CTL(pipe
), fbc_ctl
);
10591 I915_WRITE_FW(CURCNTR(pipe
), cntl
);
10592 I915_WRITE_FW(CURPOS(pipe
), pos
);
10593 I915_WRITE_FW(CURBASE(pipe
), base
);
10595 plane
->cursor
.base
= base
;
10596 plane
->cursor
.size
= fbc_ctl
;
10597 plane
->cursor
.cntl
= cntl
;
10599 I915_WRITE_FW(CURPOS(pipe
), pos
);
10600 I915_WRITE_FW(CURBASE(pipe
), base
);
10603 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
10606 static void i9xx_disable_cursor(struct intel_plane
*plane
,
10607 const struct intel_crtc_state
*crtc_state
)
10609 i9xx_update_cursor(plane
, crtc_state
, NULL
);
10612 static bool i9xx_cursor_get_hw_state(struct intel_plane
*plane
,
10615 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
10616 enum intel_display_power_domain power_domain
;
10617 intel_wakeref_t wakeref
;
10622 * Not 100% correct for planes that can move between pipes,
10623 * but that's only the case for gen2-3 which don't have any
10624 * display power wells.
10626 power_domain
= POWER_DOMAIN_PIPE(plane
->pipe
);
10627 wakeref
= intel_display_power_get_if_enabled(dev_priv
, power_domain
);
10631 val
= I915_READ(CURCNTR(plane
->pipe
));
10633 ret
= val
& MCURSOR_MODE
;
10635 if (INTEL_GEN(dev_priv
) >= 5 || IS_G4X(dev_priv
))
10636 *pipe
= plane
->pipe
;
10638 *pipe
= (val
& MCURSOR_PIPE_SELECT_MASK
) >>
10639 MCURSOR_PIPE_SELECT_SHIFT
;
10641 intel_display_power_put(dev_priv
, power_domain
, wakeref
);
10646 /* VESA 640x480x72Hz mode to set on the pipe */
10647 static const struct drm_display_mode load_detect_mode
= {
10648 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
10649 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
10652 struct drm_framebuffer
*
10653 intel_framebuffer_create(struct drm_i915_gem_object
*obj
,
10654 struct drm_mode_fb_cmd2
*mode_cmd
)
10656 struct intel_framebuffer
*intel_fb
;
10659 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
10661 return ERR_PTR(-ENOMEM
);
10663 ret
= intel_framebuffer_init(intel_fb
, obj
, mode_cmd
);
10667 return &intel_fb
->base
;
10671 return ERR_PTR(ret
);
10674 static int intel_modeset_disable_planes(struct drm_atomic_state
*state
,
10675 struct drm_crtc
*crtc
)
10677 struct drm_plane
*plane
;
10678 struct drm_plane_state
*plane_state
;
10681 ret
= drm_atomic_add_affected_planes(state
, crtc
);
10685 for_each_new_plane_in_state(state
, plane
, plane_state
, i
) {
10686 if (plane_state
->crtc
!= crtc
)
10689 ret
= drm_atomic_set_crtc_for_plane(plane_state
, NULL
);
10693 drm_atomic_set_fb_for_plane(plane_state
, NULL
);
10699 int intel_get_load_detect_pipe(struct drm_connector
*connector
,
10700 const struct drm_display_mode
*mode
,
10701 struct intel_load_detect_pipe
*old
,
10702 struct drm_modeset_acquire_ctx
*ctx
)
10704 struct intel_crtc
*intel_crtc
;
10705 struct intel_encoder
*intel_encoder
=
10706 intel_attached_encoder(connector
);
10707 struct drm_crtc
*possible_crtc
;
10708 struct drm_encoder
*encoder
= &intel_encoder
->base
;
10709 struct drm_crtc
*crtc
= NULL
;
10710 struct drm_device
*dev
= encoder
->dev
;
10711 struct drm_i915_private
*dev_priv
= to_i915(dev
);
10712 struct drm_mode_config
*config
= &dev
->mode_config
;
10713 struct drm_atomic_state
*state
= NULL
, *restore_state
= NULL
;
10714 struct drm_connector_state
*connector_state
;
10715 struct intel_crtc_state
*crtc_state
;
10718 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10719 connector
->base
.id
, connector
->name
,
10720 encoder
->base
.id
, encoder
->name
);
10722 old
->restore_state
= NULL
;
10724 WARN_ON(!drm_modeset_is_locked(&config
->connection_mutex
));
10727 * Algorithm gets a little messy:
10729 * - if the connector already has an assigned crtc, use it (but make
10730 * sure it's on first)
10732 * - try to find the first unused crtc that can drive this connector,
10733 * and use that if we find one
10736 /* See if we already have a CRTC for this connector */
10737 if (connector
->state
->crtc
) {
10738 crtc
= connector
->state
->crtc
;
10740 ret
= drm_modeset_lock(&crtc
->mutex
, ctx
);
10744 /* Make sure the crtc and connector are running */
10748 /* Find an unused one (if possible) */
10749 for_each_crtc(dev
, possible_crtc
) {
10751 if (!(encoder
->possible_crtcs
& (1 << i
)))
10754 ret
= drm_modeset_lock(&possible_crtc
->mutex
, ctx
);
10758 if (possible_crtc
->state
->enable
) {
10759 drm_modeset_unlock(&possible_crtc
->mutex
);
10763 crtc
= possible_crtc
;
10768 * If we didn't find an unused CRTC, don't use any.
10771 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10777 intel_crtc
= to_intel_crtc(crtc
);
10779 state
= drm_atomic_state_alloc(dev
);
10780 restore_state
= drm_atomic_state_alloc(dev
);
10781 if (!state
|| !restore_state
) {
10786 state
->acquire_ctx
= ctx
;
10787 restore_state
->acquire_ctx
= ctx
;
10789 connector_state
= drm_atomic_get_connector_state(state
, connector
);
10790 if (IS_ERR(connector_state
)) {
10791 ret
= PTR_ERR(connector_state
);
10795 ret
= drm_atomic_set_crtc_for_connector(connector_state
, crtc
);
10799 crtc_state
= intel_atomic_get_crtc_state(state
, intel_crtc
);
10800 if (IS_ERR(crtc_state
)) {
10801 ret
= PTR_ERR(crtc_state
);
10805 crtc_state
->base
.active
= crtc_state
->base
.enable
= true;
10808 mode
= &load_detect_mode
;
10810 ret
= drm_atomic_set_mode_for_crtc(&crtc_state
->base
, mode
);
10814 ret
= intel_modeset_disable_planes(state
, crtc
);
10818 ret
= PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state
, connector
));
10820 ret
= PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state
, crtc
));
10822 ret
= drm_atomic_add_affected_planes(restore_state
, crtc
);
10824 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret
);
10828 ret
= drm_atomic_commit(state
);
10830 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10834 old
->restore_state
= restore_state
;
10835 drm_atomic_state_put(state
);
10837 /* let the connector get through one full cycle before testing */
10838 intel_wait_for_vblank(dev_priv
, intel_crtc
->pipe
);
10843 drm_atomic_state_put(state
);
10846 if (restore_state
) {
10847 drm_atomic_state_put(restore_state
);
10848 restore_state
= NULL
;
10851 if (ret
== -EDEADLK
)
10857 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
10858 struct intel_load_detect_pipe
*old
,
10859 struct drm_modeset_acquire_ctx
*ctx
)
10861 struct intel_encoder
*intel_encoder
=
10862 intel_attached_encoder(connector
);
10863 struct drm_encoder
*encoder
= &intel_encoder
->base
;
10864 struct drm_atomic_state
*state
= old
->restore_state
;
10867 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10868 connector
->base
.id
, connector
->name
,
10869 encoder
->base
.id
, encoder
->name
);
10874 ret
= drm_atomic_helper_commit_duplicated_state(state
, ctx
);
10876 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret
);
10877 drm_atomic_state_put(state
);
10880 static int i9xx_pll_refclk(struct drm_device
*dev
,
10881 const struct intel_crtc_state
*pipe_config
)
10883 struct drm_i915_private
*dev_priv
= to_i915(dev
);
10884 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
10886 if ((dpll
& PLL_REF_INPUT_MASK
) == PLLB_REF_INPUT_SPREADSPECTRUMIN
)
10887 return dev_priv
->vbt
.lvds_ssc_freq
;
10888 else if (HAS_PCH_SPLIT(dev_priv
))
10890 else if (!IS_GEN(dev_priv
, 2))
10896 /* Returns the clock of the currently programmed mode of the given pipe. */
10897 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
10898 struct intel_crtc_state
*pipe_config
)
10900 struct drm_device
*dev
= crtc
->base
.dev
;
10901 struct drm_i915_private
*dev_priv
= to_i915(dev
);
10902 int pipe
= pipe_config
->cpu_transcoder
;
10903 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
10907 int refclk
= i9xx_pll_refclk(dev
, pipe_config
);
10909 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
10910 fp
= pipe_config
->dpll_hw_state
.fp0
;
10912 fp
= pipe_config
->dpll_hw_state
.fp1
;
10914 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
10915 if (IS_PINEVIEW(dev_priv
)) {
10916 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
10917 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
10919 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
10920 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
10923 if (!IS_GEN(dev_priv
, 2)) {
10924 if (IS_PINEVIEW(dev_priv
))
10925 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
10926 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
10928 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
10929 DPLL_FPA01_P1_POST_DIV_SHIFT
);
10931 switch (dpll
& DPLL_MODE_MASK
) {
10932 case DPLLB_MODE_DAC_SERIAL
:
10933 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
10936 case DPLLB_MODE_LVDS
:
10937 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
10941 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10942 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
10946 if (IS_PINEVIEW(dev_priv
))
10947 port_clock
= pnv_calc_dpll_params(refclk
, &clock
);
10949 port_clock
= i9xx_calc_dpll_params(refclk
, &clock
);
10951 u32 lvds
= IS_I830(dev_priv
) ? 0 : I915_READ(LVDS
);
10952 bool is_lvds
= (pipe
== 1) && (lvds
& LVDS_PORT_EN
);
10955 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
10956 DPLL_FPA01_P1_POST_DIV_SHIFT
);
10958 if (lvds
& LVDS_CLKB_POWER_UP
)
10963 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
10966 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
10967 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
10969 if (dpll
& PLL_P2_DIVIDE_BY_4
)
10975 port_clock
= i9xx_calc_dpll_params(refclk
, &clock
);
10979 * This value includes pixel_multiplier. We will use
10980 * port_clock to compute adjusted_mode.crtc_clock in the
10981 * encoder's get_config() function.
10983 pipe_config
->port_clock
= port_clock
;
10986 int intel_dotclock_calculate(int link_freq
,
10987 const struct intel_link_m_n
*m_n
)
10990 * The calculation for the data clock is:
10991 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10992 * But we want to avoid losing precison if possible, so:
10993 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10995 * and the link clock is simpler:
10996 * link_clock = (m * link_clock) / n
11002 return div_u64(mul_u32_u32(m_n
->link_m
, link_freq
), m_n
->link_n
);
11005 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
11006 struct intel_crtc_state
*pipe_config
)
11008 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
11010 /* read out port_clock from the DPLL */
11011 i9xx_crtc_clock_get(crtc
, pipe_config
);
11014 * In case there is an active pipe without active ports,
11015 * we may need some idea for the dotclock anyway.
11016 * Calculate one based on the FDI configuration.
11018 pipe_config
->base
.adjusted_mode
.crtc_clock
=
11019 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv
, pipe_config
),
11020 &pipe_config
->fdi_m_n
);
11023 /* Returns the currently programmed mode of the given encoder. */
11024 struct drm_display_mode
*
11025 intel_encoder_current_mode(struct intel_encoder
*encoder
)
11027 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
11028 struct intel_crtc_state
*crtc_state
;
11029 struct drm_display_mode
*mode
;
11030 struct intel_crtc
*crtc
;
11033 if (!encoder
->get_hw_state(encoder
, &pipe
))
11036 crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
11038 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
11042 crtc_state
= kzalloc(sizeof(*crtc_state
), GFP_KERNEL
);
11048 crtc_state
->base
.crtc
= &crtc
->base
;
11050 if (!dev_priv
->display
.get_pipe_config(crtc
, crtc_state
)) {
11056 encoder
->get_config(encoder
, crtc_state
);
11058 intel_mode_from_pipe_config(mode
, crtc_state
);
11065 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
11067 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11069 drm_crtc_cleanup(crtc
);
11074 * intel_wm_need_update - Check whether watermarks need updating
11075 * @cur: current plane state
11076 * @new: new plane state
11078 * Check current plane state versus the new one to determine whether
11079 * watermarks need to be recalculated.
11081 * Returns true or false.
11083 static bool intel_wm_need_update(struct intel_plane_state
*cur
,
11084 struct intel_plane_state
*new)
11086 /* Update watermarks on tiling or size changes. */
11087 if (new->base
.visible
!= cur
->base
.visible
)
11090 if (!cur
->base
.fb
|| !new->base
.fb
)
11093 if (cur
->base
.fb
->modifier
!= new->base
.fb
->modifier
||
11094 cur
->base
.rotation
!= new->base
.rotation
||
11095 drm_rect_width(&new->base
.src
) != drm_rect_width(&cur
->base
.src
) ||
11096 drm_rect_height(&new->base
.src
) != drm_rect_height(&cur
->base
.src
) ||
11097 drm_rect_width(&new->base
.dst
) != drm_rect_width(&cur
->base
.dst
) ||
11098 drm_rect_height(&new->base
.dst
) != drm_rect_height(&cur
->base
.dst
))
11104 static bool needs_scaling(const struct intel_plane_state
*state
)
11106 int src_w
= drm_rect_width(&state
->base
.src
) >> 16;
11107 int src_h
= drm_rect_height(&state
->base
.src
) >> 16;
11108 int dst_w
= drm_rect_width(&state
->base
.dst
);
11109 int dst_h
= drm_rect_height(&state
->base
.dst
);
11111 return (src_w
!= dst_w
|| src_h
!= dst_h
);
11114 int intel_plane_atomic_calc_changes(const struct intel_crtc_state
*old_crtc_state
,
11115 struct drm_crtc_state
*crtc_state
,
11116 const struct intel_plane_state
*old_plane_state
,
11117 struct drm_plane_state
*plane_state
)
11119 struct intel_crtc_state
*pipe_config
= to_intel_crtc_state(crtc_state
);
11120 struct drm_crtc
*crtc
= crtc_state
->crtc
;
11121 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11122 struct intel_plane
*plane
= to_intel_plane(plane_state
->plane
);
11123 struct drm_device
*dev
= crtc
->dev
;
11124 struct drm_i915_private
*dev_priv
= to_i915(dev
);
11125 bool mode_changed
= needs_modeset(crtc_state
);
11126 bool was_crtc_enabled
= old_crtc_state
->base
.active
;
11127 bool is_crtc_enabled
= crtc_state
->active
;
11128 bool turn_off
, turn_on
, visible
, was_visible
;
11129 struct drm_framebuffer
*fb
= plane_state
->fb
;
11132 if (INTEL_GEN(dev_priv
) >= 9 && plane
->id
!= PLANE_CURSOR
) {
11133 ret
= skl_update_scaler_plane(
11134 to_intel_crtc_state(crtc_state
),
11135 to_intel_plane_state(plane_state
));
11140 was_visible
= old_plane_state
->base
.visible
;
11141 visible
= plane_state
->visible
;
11143 if (!was_crtc_enabled
&& WARN_ON(was_visible
))
11144 was_visible
= false;
11147 * Visibility is calculated as if the crtc was on, but
11148 * after scaler setup everything depends on it being off
11149 * when the crtc isn't active.
11151 * FIXME this is wrong for watermarks. Watermarks should also
11152 * be computed as if the pipe would be active. Perhaps move
11153 * per-plane wm computation to the .check_plane() hook, and
11154 * only combine the results from all planes in the current place?
11156 if (!is_crtc_enabled
) {
11157 plane_state
->visible
= visible
= false;
11158 to_intel_crtc_state(crtc_state
)->active_planes
&= ~BIT(plane
->id
);
11161 if (!was_visible
&& !visible
)
11164 if (fb
!= old_plane_state
->base
.fb
)
11165 pipe_config
->fb_changed
= true;
11167 turn_off
= was_visible
&& (!visible
|| mode_changed
);
11168 turn_on
= visible
&& (!was_visible
|| mode_changed
);
11170 DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
11171 intel_crtc
->base
.base
.id
, intel_crtc
->base
.name
,
11172 plane
->base
.base
.id
, plane
->base
.name
,
11173 fb
? fb
->base
.id
: -1);
11175 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
11176 plane
->base
.base
.id
, plane
->base
.name
,
11177 was_visible
, visible
,
11178 turn_off
, turn_on
, mode_changed
);
11181 if (INTEL_GEN(dev_priv
) < 5 && !IS_G4X(dev_priv
))
11182 pipe_config
->update_wm_pre
= true;
11184 /* must disable cxsr around plane enable/disable */
11185 if (plane
->id
!= PLANE_CURSOR
)
11186 pipe_config
->disable_cxsr
= true;
11187 } else if (turn_off
) {
11188 if (INTEL_GEN(dev_priv
) < 5 && !IS_G4X(dev_priv
))
11189 pipe_config
->update_wm_post
= true;
11191 /* must disable cxsr around plane enable/disable */
11192 if (plane
->id
!= PLANE_CURSOR
)
11193 pipe_config
->disable_cxsr
= true;
11194 } else if (intel_wm_need_update(to_intel_plane_state(plane
->base
.state
),
11195 to_intel_plane_state(plane_state
))) {
11196 if (INTEL_GEN(dev_priv
) < 5 && !IS_G4X(dev_priv
)) {
11197 /* FIXME bollocks */
11198 pipe_config
->update_wm_pre
= true;
11199 pipe_config
->update_wm_post
= true;
11203 if (visible
|| was_visible
)
11204 pipe_config
->fb_bits
|= plane
->frontbuffer_bit
;
11207 * ILK/SNB DVSACNTR/Sprite Enable
11208 * IVB SPR_CTL/Sprite Enable
11209 * "When in Self Refresh Big FIFO mode, a write to enable the
11210 * plane will be internally buffered and delayed while Big FIFO
11211 * mode is exiting."
11213 * Which means that enabling the sprite can take an extra frame
11214 * when we start in big FIFO mode (LP1+). Thus we need to drop
11215 * down to LP0 and wait for vblank in order to make sure the
11216 * sprite gets enabled on the next vblank after the register write.
11217 * Doing otherwise would risk enabling the sprite one frame after
11218 * we've already signalled flip completion. We can resume LP1+
11219 * once the sprite has been enabled.
11222 * WaCxSRDisabledForSpriteScaling:ivb
11223 * IVB SPR_SCALE/Scaling Enable
11224 * "Low Power watermarks must be disabled for at least one
11225 * frame before enabling sprite scaling, and kept disabled
11226 * until sprite scaling is disabled."
11228 * ILK/SNB DVSASCALE/Scaling Enable
11229 * "When in Self Refresh Big FIFO mode, scaling enable will be
11230 * masked off while Big FIFO mode is exiting."
11232 * Despite the w/a only being listed for IVB we assume that
11233 * the ILK/SNB note has similar ramifications, hence we apply
11234 * the w/a on all three platforms.
11236 * With experimental results seems this is needed also for primary
11237 * plane, not only sprite plane.
11239 if (plane
->id
!= PLANE_CURSOR
&&
11240 (IS_GEN_RANGE(dev_priv
, 5, 6) ||
11241 IS_IVYBRIDGE(dev_priv
)) &&
11242 (turn_on
|| (!needs_scaling(old_plane_state
) &&
11243 needs_scaling(to_intel_plane_state(plane_state
)))))
11244 pipe_config
->disable_lp_wm
= true;
11249 static bool encoders_cloneable(const struct intel_encoder
*a
,
11250 const struct intel_encoder
*b
)
11252 /* masks could be asymmetric, so check both ways */
11253 return a
== b
|| (a
->cloneable
& (1 << b
->type
) &&
11254 b
->cloneable
& (1 << a
->type
));
11257 static bool check_single_encoder_cloning(struct drm_atomic_state
*state
,
11258 struct intel_crtc
*crtc
,
11259 struct intel_encoder
*encoder
)
11261 struct intel_encoder
*source_encoder
;
11262 struct drm_connector
*connector
;
11263 struct drm_connector_state
*connector_state
;
11266 for_each_new_connector_in_state(state
, connector
, connector_state
, i
) {
11267 if (connector_state
->crtc
!= &crtc
->base
)
11271 to_intel_encoder(connector_state
->best_encoder
);
11272 if (!encoders_cloneable(encoder
, source_encoder
))
11279 static int icl_add_linked_planes(struct intel_atomic_state
*state
)
11281 struct intel_plane
*plane
, *linked
;
11282 struct intel_plane_state
*plane_state
, *linked_plane_state
;
11285 for_each_new_intel_plane_in_state(state
, plane
, plane_state
, i
) {
11286 linked
= plane_state
->linked_plane
;
11291 linked_plane_state
= intel_atomic_get_plane_state(state
, linked
);
11292 if (IS_ERR(linked_plane_state
))
11293 return PTR_ERR(linked_plane_state
);
11295 WARN_ON(linked_plane_state
->linked_plane
!= plane
);
11296 WARN_ON(linked_plane_state
->slave
== plane_state
->slave
);
11302 static int icl_check_nv12_planes(struct intel_crtc_state
*crtc_state
)
11304 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
11305 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
11306 struct intel_atomic_state
*state
= to_intel_atomic_state(crtc_state
->base
.state
);
11307 struct intel_plane
*plane
, *linked
;
11308 struct intel_plane_state
*plane_state
;
11311 if (INTEL_GEN(dev_priv
) < 11)
11315 * Destroy all old plane links and make the slave plane invisible
11316 * in the crtc_state->active_planes mask.
11318 for_each_new_intel_plane_in_state(state
, plane
, plane_state
, i
) {
11319 if (plane
->pipe
!= crtc
->pipe
|| !plane_state
->linked_plane
)
11322 plane_state
->linked_plane
= NULL
;
11323 if (plane_state
->slave
&& !plane_state
->base
.visible
) {
11324 crtc_state
->active_planes
&= ~BIT(plane
->id
);
11325 crtc_state
->update_planes
|= BIT(plane
->id
);
11328 plane_state
->slave
= false;
11331 if (!crtc_state
->nv12_planes
)
11334 for_each_new_intel_plane_in_state(state
, plane
, plane_state
, i
) {
11335 struct intel_plane_state
*linked_state
= NULL
;
11337 if (plane
->pipe
!= crtc
->pipe
||
11338 !(crtc_state
->nv12_planes
& BIT(plane
->id
)))
11341 for_each_intel_plane_on_crtc(&dev_priv
->drm
, crtc
, linked
) {
11342 if (!icl_is_nv12_y_plane(linked
->id
))
11345 if (crtc_state
->active_planes
& BIT(linked
->id
))
11348 linked_state
= intel_atomic_get_plane_state(state
, linked
);
11349 if (IS_ERR(linked_state
))
11350 return PTR_ERR(linked_state
);
11355 if (!linked_state
) {
11356 DRM_DEBUG_KMS("Need %d free Y planes for planar YUV\n",
11357 hweight8(crtc_state
->nv12_planes
));
11362 plane_state
->linked_plane
= linked
;
11364 linked_state
->slave
= true;
11365 linked_state
->linked_plane
= plane
;
11366 crtc_state
->active_planes
|= BIT(linked
->id
);
11367 crtc_state
->update_planes
|= BIT(linked
->id
);
11368 DRM_DEBUG_KMS("Using %s as Y plane for %s\n", linked
->base
.name
, plane
->base
.name
);
11374 static int intel_crtc_atomic_check(struct drm_crtc
*crtc
,
11375 struct drm_crtc_state
*crtc_state
)
11377 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
11378 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11379 struct intel_crtc_state
*pipe_config
=
11380 to_intel_crtc_state(crtc_state
);
11382 bool mode_changed
= needs_modeset(crtc_state
);
11384 if (INTEL_GEN(dev_priv
) < 5 && !IS_G4X(dev_priv
) &&
11385 mode_changed
&& !crtc_state
->active
)
11386 pipe_config
->update_wm_post
= true;
11388 if (mode_changed
&& crtc_state
->enable
&&
11389 dev_priv
->display
.crtc_compute_clock
&&
11390 !WARN_ON(pipe_config
->shared_dpll
)) {
11391 ret
= dev_priv
->display
.crtc_compute_clock(intel_crtc
,
11397 if (mode_changed
|| pipe_config
->update_pipe
||
11398 crtc_state
->color_mgmt_changed
) {
11399 ret
= intel_color_check(pipe_config
);
11405 if (dev_priv
->display
.compute_pipe_wm
) {
11406 ret
= dev_priv
->display
.compute_pipe_wm(pipe_config
);
11408 DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
11413 if (dev_priv
->display
.compute_intermediate_wm
) {
11414 if (WARN_ON(!dev_priv
->display
.compute_pipe_wm
))
11418 * Calculate 'intermediate' watermarks that satisfy both the
11419 * old state and the new state. We can program these
11422 ret
= dev_priv
->display
.compute_intermediate_wm(pipe_config
);
11424 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
11429 if (INTEL_GEN(dev_priv
) >= 9) {
11430 if (mode_changed
|| pipe_config
->update_pipe
)
11431 ret
= skl_update_scaler_crtc(pipe_config
);
11434 ret
= icl_check_nv12_planes(pipe_config
);
11436 ret
= skl_check_pipe_max_pixel_rate(intel_crtc
,
11439 ret
= intel_atomic_setup_scalers(dev_priv
, intel_crtc
,
11443 if (HAS_IPS(dev_priv
))
11444 pipe_config
->ips_enabled
= hsw_compute_ips_config(pipe_config
);
11449 static const struct drm_crtc_helper_funcs intel_helper_funcs
= {
11450 .atomic_check
= intel_crtc_atomic_check
,
11453 static void intel_modeset_update_connector_atomic_state(struct drm_device
*dev
)
11455 struct intel_connector
*connector
;
11456 struct drm_connector_list_iter conn_iter
;
11458 drm_connector_list_iter_begin(dev
, &conn_iter
);
11459 for_each_intel_connector_iter(connector
, &conn_iter
) {
11460 if (connector
->base
.state
->crtc
)
11461 drm_connector_put(&connector
->base
);
11463 if (connector
->base
.encoder
) {
11464 connector
->base
.state
->best_encoder
=
11465 connector
->base
.encoder
;
11466 connector
->base
.state
->crtc
=
11467 connector
->base
.encoder
->crtc
;
11469 drm_connector_get(&connector
->base
);
11471 connector
->base
.state
->best_encoder
= NULL
;
11472 connector
->base
.state
->crtc
= NULL
;
11475 drm_connector_list_iter_end(&conn_iter
);
11479 compute_sink_pipe_bpp(const struct drm_connector_state
*conn_state
,
11480 struct intel_crtc_state
*pipe_config
)
11482 struct drm_connector
*connector
= conn_state
->connector
;
11483 const struct drm_display_info
*info
= &connector
->display_info
;
11486 switch (conn_state
->max_bpc
) {
11503 if (bpp
< pipe_config
->pipe_bpp
) {
11504 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Limiting display bpp to %d instead of "
11505 "EDID bpp %d, requested bpp %d, max platform bpp %d\n",
11506 connector
->base
.id
, connector
->name
,
11507 bpp
, 3 * info
->bpc
, 3 * conn_state
->max_requested_bpc
,
11508 pipe_config
->pipe_bpp
);
11510 pipe_config
->pipe_bpp
= bpp
;
11517 compute_baseline_pipe_bpp(struct intel_crtc
*crtc
,
11518 struct intel_crtc_state
*pipe_config
)
11520 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
11521 struct drm_atomic_state
*state
= pipe_config
->base
.state
;
11522 struct drm_connector
*connector
;
11523 struct drm_connector_state
*connector_state
;
11526 if ((IS_G4X(dev_priv
) || IS_VALLEYVIEW(dev_priv
) ||
11527 IS_CHERRYVIEW(dev_priv
)))
11529 else if (INTEL_GEN(dev_priv
) >= 5)
11534 pipe_config
->pipe_bpp
= bpp
;
11536 /* Clamp display bpp to connector max bpp */
11537 for_each_new_connector_in_state(state
, connector
, connector_state
, i
) {
11540 if (connector_state
->crtc
!= &crtc
->base
)
11543 ret
= compute_sink_pipe_bpp(connector_state
, pipe_config
);
11551 static void intel_dump_crtc_timings(const struct drm_display_mode
*mode
)
11553 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11554 "type: 0x%x flags: 0x%x\n",
11556 mode
->crtc_hdisplay
, mode
->crtc_hsync_start
,
11557 mode
->crtc_hsync_end
, mode
->crtc_htotal
,
11558 mode
->crtc_vdisplay
, mode
->crtc_vsync_start
,
11559 mode
->crtc_vsync_end
, mode
->crtc_vtotal
, mode
->type
, mode
->flags
);
11563 intel_dump_m_n_config(struct intel_crtc_state
*pipe_config
, char *id
,
11564 unsigned int lane_count
, struct intel_link_m_n
*m_n
)
11566 DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11568 m_n
->gmch_m
, m_n
->gmch_n
,
11569 m_n
->link_m
, m_n
->link_n
, m_n
->tu
);
11573 intel_dump_infoframe(struct drm_i915_private
*dev_priv
,
11574 const union hdmi_infoframe
*frame
)
11576 if ((drm_debug
& DRM_UT_KMS
) == 0)
11579 hdmi_infoframe_log(KERN_DEBUG
, dev_priv
->drm
.dev
, frame
);
11582 #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
11584 static const char * const output_type_str
[] = {
11585 OUTPUT_TYPE(UNUSED
),
11586 OUTPUT_TYPE(ANALOG
),
11590 OUTPUT_TYPE(TVOUT
),
11596 OUTPUT_TYPE(DP_MST
),
11601 static void snprintf_output_types(char *buf
, size_t len
,
11602 unsigned int output_types
)
11609 for (i
= 0; i
< ARRAY_SIZE(output_type_str
); i
++) {
11612 if ((output_types
& BIT(i
)) == 0)
11615 r
= snprintf(str
, len
, "%s%s",
11616 str
!= buf
? "," : "", output_type_str
[i
]);
11622 output_types
&= ~BIT(i
);
11625 WARN_ON_ONCE(output_types
!= 0);
11628 static const char * const output_format_str
[] = {
11629 [INTEL_OUTPUT_FORMAT_INVALID
] = "Invalid",
11630 [INTEL_OUTPUT_FORMAT_RGB
] = "RGB",
11631 [INTEL_OUTPUT_FORMAT_YCBCR420
] = "YCBCR4:2:0",
11632 [INTEL_OUTPUT_FORMAT_YCBCR444
] = "YCBCR4:4:4",
11635 static const char *output_formats(enum intel_output_format format
)
11637 if (format
>= ARRAY_SIZE(output_format_str
))
11638 format
= INTEL_OUTPUT_FORMAT_INVALID
;
11639 return output_format_str
[format
];
11642 static void intel_dump_pipe_config(struct intel_crtc
*crtc
,
11643 struct intel_crtc_state
*pipe_config
,
11644 const char *context
)
11646 struct drm_device
*dev
= crtc
->base
.dev
;
11647 struct drm_i915_private
*dev_priv
= to_i915(dev
);
11648 struct drm_plane
*plane
;
11649 struct intel_plane
*intel_plane
;
11650 struct intel_plane_state
*state
;
11651 struct drm_framebuffer
*fb
;
11654 DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n",
11655 crtc
->base
.base
.id
, crtc
->base
.name
, context
);
11657 snprintf_output_types(buf
, sizeof(buf
), pipe_config
->output_types
);
11658 DRM_DEBUG_KMS("output_types: %s (0x%x)\n",
11659 buf
, pipe_config
->output_types
);
11661 DRM_DEBUG_KMS("output format: %s\n",
11662 output_formats(pipe_config
->output_format
));
11664 DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
11665 transcoder_name(pipe_config
->cpu_transcoder
),
11666 pipe_config
->pipe_bpp
, pipe_config
->dither
);
11668 if (pipe_config
->has_pch_encoder
)
11669 intel_dump_m_n_config(pipe_config
, "fdi",
11670 pipe_config
->fdi_lanes
,
11671 &pipe_config
->fdi_m_n
);
11673 if (intel_crtc_has_dp_encoder(pipe_config
)) {
11674 intel_dump_m_n_config(pipe_config
, "dp m_n",
11675 pipe_config
->lane_count
, &pipe_config
->dp_m_n
);
11676 if (pipe_config
->has_drrs
)
11677 intel_dump_m_n_config(pipe_config
, "dp m2_n2",
11678 pipe_config
->lane_count
,
11679 &pipe_config
->dp_m2_n2
);
11682 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11683 pipe_config
->has_audio
, pipe_config
->has_infoframe
);
11685 DRM_DEBUG_KMS("infoframes enabled: 0x%x\n",
11686 pipe_config
->infoframes
.enable
);
11688 if (pipe_config
->infoframes
.enable
&
11689 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL
))
11690 DRM_DEBUG_KMS("GCP: 0x%x\n", pipe_config
->infoframes
.gcp
);
11691 if (pipe_config
->infoframes
.enable
&
11692 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI
))
11693 intel_dump_infoframe(dev_priv
, &pipe_config
->infoframes
.avi
);
11694 if (pipe_config
->infoframes
.enable
&
11695 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD
))
11696 intel_dump_infoframe(dev_priv
, &pipe_config
->infoframes
.spd
);
11697 if (pipe_config
->infoframes
.enable
&
11698 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR
))
11699 intel_dump_infoframe(dev_priv
, &pipe_config
->infoframes
.hdmi
);
11701 DRM_DEBUG_KMS("requested mode:\n");
11702 drm_mode_debug_printmodeline(&pipe_config
->base
.mode
);
11703 DRM_DEBUG_KMS("adjusted mode:\n");
11704 drm_mode_debug_printmodeline(&pipe_config
->base
.adjusted_mode
);
11705 intel_dump_crtc_timings(&pipe_config
->base
.adjusted_mode
);
11706 DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
11707 pipe_config
->port_clock
,
11708 pipe_config
->pipe_src_w
, pipe_config
->pipe_src_h
,
11709 pipe_config
->pixel_rate
);
11711 if (INTEL_GEN(dev_priv
) >= 9)
11712 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11714 pipe_config
->scaler_state
.scaler_users
,
11715 pipe_config
->scaler_state
.scaler_id
);
11717 if (HAS_GMCH(dev_priv
))
11718 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11719 pipe_config
->gmch_pfit
.control
,
11720 pipe_config
->gmch_pfit
.pgm_ratios
,
11721 pipe_config
->gmch_pfit
.lvds_border_bits
);
11723 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11724 pipe_config
->pch_pfit
.pos
,
11725 pipe_config
->pch_pfit
.size
,
11726 enableddisabled(pipe_config
->pch_pfit
.enabled
));
11728 DRM_DEBUG_KMS("ips: %i, double wide: %i\n",
11729 pipe_config
->ips_enabled
, pipe_config
->double_wide
);
11731 intel_dpll_dump_hw_state(dev_priv
, &pipe_config
->dpll_hw_state
);
11733 DRM_DEBUG_KMS("planes on this crtc\n");
11734 list_for_each_entry(plane
, &dev
->mode_config
.plane_list
, head
) {
11735 struct drm_format_name_buf format_name
;
11736 intel_plane
= to_intel_plane(plane
);
11737 if (intel_plane
->pipe
!= crtc
->pipe
)
11740 state
= to_intel_plane_state(plane
->state
);
11741 fb
= state
->base
.fb
;
11743 DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
11744 plane
->base
.id
, plane
->name
, state
->scaler_id
);
11748 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n",
11749 plane
->base
.id
, plane
->name
,
11750 fb
->base
.id
, fb
->width
, fb
->height
,
11751 drm_get_format_name(fb
->format
->format
, &format_name
));
11752 if (INTEL_GEN(dev_priv
) >= 9)
11753 DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
11755 state
->base
.src
.x1
>> 16,
11756 state
->base
.src
.y1
>> 16,
11757 drm_rect_width(&state
->base
.src
) >> 16,
11758 drm_rect_height(&state
->base
.src
) >> 16,
11759 state
->base
.dst
.x1
, state
->base
.dst
.y1
,
11760 drm_rect_width(&state
->base
.dst
),
11761 drm_rect_height(&state
->base
.dst
));
11765 static bool check_digital_port_conflicts(struct drm_atomic_state
*state
)
11767 struct drm_device
*dev
= state
->dev
;
11768 struct drm_connector
*connector
;
11769 struct drm_connector_list_iter conn_iter
;
11770 unsigned int used_ports
= 0;
11771 unsigned int used_mst_ports
= 0;
11775 * Walk the connector list instead of the encoder
11776 * list to detect the problem on ddi platforms
11777 * where there's just one encoder per digital port.
11779 drm_connector_list_iter_begin(dev
, &conn_iter
);
11780 drm_for_each_connector_iter(connector
, &conn_iter
) {
11781 struct drm_connector_state
*connector_state
;
11782 struct intel_encoder
*encoder
;
11784 connector_state
= drm_atomic_get_new_connector_state(state
, connector
);
11785 if (!connector_state
)
11786 connector_state
= connector
->state
;
11788 if (!connector_state
->best_encoder
)
11791 encoder
= to_intel_encoder(connector_state
->best_encoder
);
11793 WARN_ON(!connector_state
->crtc
);
11795 switch (encoder
->type
) {
11796 unsigned int port_mask
;
11797 case INTEL_OUTPUT_DDI
:
11798 if (WARN_ON(!HAS_DDI(to_i915(dev
))))
11800 /* else: fall through */
11801 case INTEL_OUTPUT_DP
:
11802 case INTEL_OUTPUT_HDMI
:
11803 case INTEL_OUTPUT_EDP
:
11804 port_mask
= 1 << encoder
->port
;
11806 /* the same port mustn't appear more than once */
11807 if (used_ports
& port_mask
)
11810 used_ports
|= port_mask
;
11812 case INTEL_OUTPUT_DP_MST
:
11814 1 << encoder
->port
;
11820 drm_connector_list_iter_end(&conn_iter
);
11822 /* can't mix MST and SST/HDMI on the same port */
11823 if (used_ports
& used_mst_ports
)
11830 clear_intel_crtc_state(struct intel_crtc_state
*crtc_state
)
11832 struct drm_i915_private
*dev_priv
=
11833 to_i915(crtc_state
->base
.crtc
->dev
);
11834 struct intel_crtc_state
*saved_state
;
11836 saved_state
= kzalloc(sizeof(*saved_state
), GFP_KERNEL
);
11840 /* FIXME: before the switch to atomic started, a new pipe_config was
11841 * kzalloc'd. Code that depends on any field being zero should be
11842 * fixed, so that the crtc_state can be safely duplicated. For now,
11843 * only fields that are know to not cause problems are preserved. */
11845 saved_state
->scaler_state
= crtc_state
->scaler_state
;
11846 saved_state
->shared_dpll
= crtc_state
->shared_dpll
;
11847 saved_state
->dpll_hw_state
= crtc_state
->dpll_hw_state
;
11848 saved_state
->pch_pfit
.force_thru
= crtc_state
->pch_pfit
.force_thru
;
11849 saved_state
->crc_enabled
= crtc_state
->crc_enabled
;
11850 if (IS_G4X(dev_priv
) ||
11851 IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
11852 saved_state
->wm
= crtc_state
->wm
;
11854 /* Keep base drm_crtc_state intact, only clear our extended struct */
11855 BUILD_BUG_ON(offsetof(struct intel_crtc_state
, base
));
11856 memcpy(&crtc_state
->base
+ 1, &saved_state
->base
+ 1,
11857 sizeof(*crtc_state
) - sizeof(crtc_state
->base
));
11859 kfree(saved_state
);
11864 intel_modeset_pipe_config(struct drm_crtc
*crtc
,
11865 struct intel_crtc_state
*pipe_config
)
11867 struct drm_atomic_state
*state
= pipe_config
->base
.state
;
11868 struct intel_encoder
*encoder
;
11869 struct drm_connector
*connector
;
11870 struct drm_connector_state
*connector_state
;
11875 ret
= clear_intel_crtc_state(pipe_config
);
11879 pipe_config
->cpu_transcoder
=
11880 (enum transcoder
) to_intel_crtc(crtc
)->pipe
;
11883 * Sanitize sync polarity flags based on requested ones. If neither
11884 * positive or negative polarity is requested, treat this as meaning
11885 * negative polarity.
11887 if (!(pipe_config
->base
.adjusted_mode
.flags
&
11888 (DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NHSYNC
)))
11889 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_NHSYNC
;
11891 if (!(pipe_config
->base
.adjusted_mode
.flags
&
11892 (DRM_MODE_FLAG_PVSYNC
| DRM_MODE_FLAG_NVSYNC
)))
11893 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_NVSYNC
;
11895 ret
= compute_baseline_pipe_bpp(to_intel_crtc(crtc
),
11900 base_bpp
= pipe_config
->pipe_bpp
;
11903 * Determine the real pipe dimensions. Note that stereo modes can
11904 * increase the actual pipe size due to the frame doubling and
11905 * insertion of additional space for blanks between the frame. This
11906 * is stored in the crtc timings. We use the requested mode to do this
11907 * computation to clearly distinguish it from the adjusted mode, which
11908 * can be changed by the connectors in the below retry loop.
11910 drm_mode_get_hv_timing(&pipe_config
->base
.mode
,
11911 &pipe_config
->pipe_src_w
,
11912 &pipe_config
->pipe_src_h
);
11914 for_each_new_connector_in_state(state
, connector
, connector_state
, i
) {
11915 if (connector_state
->crtc
!= crtc
)
11918 encoder
= to_intel_encoder(connector_state
->best_encoder
);
11920 if (!check_single_encoder_cloning(state
, to_intel_crtc(crtc
), encoder
)) {
11921 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11926 * Determine output_types before calling the .compute_config()
11927 * hooks so that the hooks can use this information safely.
11929 if (encoder
->compute_output_type
)
11930 pipe_config
->output_types
|=
11931 BIT(encoder
->compute_output_type(encoder
, pipe_config
,
11934 pipe_config
->output_types
|= BIT(encoder
->type
);
11938 /* Ensure the port clock defaults are reset when retrying. */
11939 pipe_config
->port_clock
= 0;
11940 pipe_config
->pixel_multiplier
= 1;
11942 /* Fill in default crtc timings, allow encoders to overwrite them. */
11943 drm_mode_set_crtcinfo(&pipe_config
->base
.adjusted_mode
,
11944 CRTC_STEREO_DOUBLE
);
11946 /* Pass our mode to the connectors and the CRTC to give them a chance to
11947 * adjust it according to limitations or connector properties, and also
11948 * a chance to reject the mode entirely.
11950 for_each_new_connector_in_state(state
, connector
, connector_state
, i
) {
11951 if (connector_state
->crtc
!= crtc
)
11954 encoder
= to_intel_encoder(connector_state
->best_encoder
);
11955 ret
= encoder
->compute_config(encoder
, pipe_config
,
11958 if (ret
!= -EDEADLK
)
11959 DRM_DEBUG_KMS("Encoder config failure: %d\n",
11965 /* Set default port clock if not overwritten by the encoder. Needs to be
11966 * done afterwards in case the encoder adjusts the mode. */
11967 if (!pipe_config
->port_clock
)
11968 pipe_config
->port_clock
= pipe_config
->base
.adjusted_mode
.crtc_clock
11969 * pipe_config
->pixel_multiplier
;
11971 ret
= intel_crtc_compute_config(to_intel_crtc(crtc
), pipe_config
);
11972 if (ret
== -EDEADLK
)
11975 DRM_DEBUG_KMS("CRTC fixup failed\n");
11979 if (ret
== RETRY
) {
11980 if (WARN(!retry
, "loop in pipe configuration computation\n"))
11983 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
11985 goto encoder_retry
;
11988 /* Dithering seems to not pass-through bits correctly when it should, so
11989 * only enable it on 6bpc panels and when its not a compliance
11990 * test requesting 6bpc video pattern.
11992 pipe_config
->dither
= (pipe_config
->pipe_bpp
== 6*3) &&
11993 !pipe_config
->dither_force_disable
;
11994 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
11995 base_bpp
, pipe_config
->pipe_bpp
, pipe_config
->dither
);
12000 static bool intel_fuzzy_clock_check(int clock1
, int clock2
)
12004 if (clock1
== clock2
)
12007 if (!clock1
|| !clock2
)
12010 diff
= abs(clock1
- clock2
);
12012 if (((((diff
+ clock1
+ clock2
) * 100)) / (clock1
+ clock2
)) < 105)
12019 intel_compare_m_n(unsigned int m
, unsigned int n
,
12020 unsigned int m2
, unsigned int n2
,
12023 if (m
== m2
&& n
== n2
)
12026 if (exact
|| !m
|| !n
|| !m2
|| !n2
)
12029 BUILD_BUG_ON(DATA_LINK_M_N_MASK
> INT_MAX
);
12036 } else if (n
< n2
) {
12046 return intel_fuzzy_clock_check(m
, m2
);
12050 intel_compare_link_m_n(const struct intel_link_m_n
*m_n
,
12051 struct intel_link_m_n
*m2_n2
,
12054 if (m_n
->tu
== m2_n2
->tu
&&
12055 intel_compare_m_n(m_n
->gmch_m
, m_n
->gmch_n
,
12056 m2_n2
->gmch_m
, m2_n2
->gmch_n
, !adjust
) &&
12057 intel_compare_m_n(m_n
->link_m
, m_n
->link_n
,
12058 m2_n2
->link_m
, m2_n2
->link_n
, !adjust
)) {
12069 intel_compare_infoframe(const union hdmi_infoframe
*a
,
12070 const union hdmi_infoframe
*b
)
12072 return memcmp(a
, b
, sizeof(*a
)) == 0;
12076 pipe_config_infoframe_err(struct drm_i915_private
*dev_priv
,
12077 bool adjust
, const char *name
,
12078 const union hdmi_infoframe
*a
,
12079 const union hdmi_infoframe
*b
)
12082 if ((drm_debug
& DRM_UT_KMS
) == 0)
12085 drm_dbg(DRM_UT_KMS
, "mismatch in %s infoframe", name
);
12086 drm_dbg(DRM_UT_KMS
, "expected:");
12087 hdmi_infoframe_log(KERN_DEBUG
, dev_priv
->drm
.dev
, a
);
12088 drm_dbg(DRM_UT_KMS
, "found");
12089 hdmi_infoframe_log(KERN_DEBUG
, dev_priv
->drm
.dev
, b
);
12091 drm_err("mismatch in %s infoframe", name
);
12092 drm_err("expected:");
12093 hdmi_infoframe_log(KERN_ERR
, dev_priv
->drm
.dev
, a
);
12095 hdmi_infoframe_log(KERN_ERR
, dev_priv
->drm
.dev
, b
);
12099 static void __printf(3, 4)
12100 pipe_config_err(bool adjust
, const char *name
, const char *format
, ...)
12102 struct va_format vaf
;
12105 va_start(args
, format
);
12110 drm_dbg(DRM_UT_KMS
, "mismatch in %s %pV", name
, &vaf
);
12112 drm_err("mismatch in %s %pV", name
, &vaf
);
12117 static bool fastboot_enabled(struct drm_i915_private
*dev_priv
)
12119 if (i915_modparams
.fastboot
!= -1)
12120 return i915_modparams
.fastboot
;
12122 /* Enable fastboot by default on Skylake and newer */
12123 if (INTEL_GEN(dev_priv
) >= 9)
12126 /* Enable fastboot by default on VLV and CHV */
12127 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
12130 /* Disabled by default on all others */
12135 intel_pipe_config_compare(struct drm_i915_private
*dev_priv
,
12136 struct intel_crtc_state
*current_config
,
12137 struct intel_crtc_state
*pipe_config
,
12141 bool fixup_inherited
= adjust
&&
12142 (current_config
->base
.mode
.private_flags
& I915_MODE_FLAG_INHERITED
) &&
12143 !(pipe_config
->base
.mode
.private_flags
& I915_MODE_FLAG_INHERITED
);
12145 if (fixup_inherited
&& !fastboot_enabled(dev_priv
)) {
12146 DRM_DEBUG_KMS("initial modeset and fastboot not set\n");
12150 #define PIPE_CONF_CHECK_X(name) do { \
12151 if (current_config->name != pipe_config->name) { \
12152 pipe_config_err(adjust, __stringify(name), \
12153 "(expected 0x%08x, found 0x%08x)\n", \
12154 current_config->name, \
12155 pipe_config->name); \
12160 #define PIPE_CONF_CHECK_I(name) do { \
12161 if (current_config->name != pipe_config->name) { \
12162 pipe_config_err(adjust, __stringify(name), \
12163 "(expected %i, found %i)\n", \
12164 current_config->name, \
12165 pipe_config->name); \
12170 #define PIPE_CONF_CHECK_BOOL(name) do { \
12171 if (current_config->name != pipe_config->name) { \
12172 pipe_config_err(adjust, __stringify(name), \
12173 "(expected %s, found %s)\n", \
12174 yesno(current_config->name), \
12175 yesno(pipe_config->name)); \
12181 * Checks state where we only read out the enabling, but not the entire
12182 * state itself (like full infoframes or ELD for audio). These states
12183 * require a full modeset on bootup to fix up.
12185 #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \
12186 if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \
12187 PIPE_CONF_CHECK_BOOL(name); \
12189 pipe_config_err(adjust, __stringify(name), \
12190 "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)\n", \
12191 yesno(current_config->name), \
12192 yesno(pipe_config->name)); \
12197 #define PIPE_CONF_CHECK_P(name) do { \
12198 if (current_config->name != pipe_config->name) { \
12199 pipe_config_err(adjust, __stringify(name), \
12200 "(expected %p, found %p)\n", \
12201 current_config->name, \
12202 pipe_config->name); \
12207 #define PIPE_CONF_CHECK_M_N(name) do { \
12208 if (!intel_compare_link_m_n(¤t_config->name, \
12209 &pipe_config->name,\
12211 pipe_config_err(adjust, __stringify(name), \
12212 "(expected tu %i gmch %i/%i link %i/%i, " \
12213 "found tu %i, gmch %i/%i link %i/%i)\n", \
12214 current_config->name.tu, \
12215 current_config->name.gmch_m, \
12216 current_config->name.gmch_n, \
12217 current_config->name.link_m, \
12218 current_config->name.link_n, \
12219 pipe_config->name.tu, \
12220 pipe_config->name.gmch_m, \
12221 pipe_config->name.gmch_n, \
12222 pipe_config->name.link_m, \
12223 pipe_config->name.link_n); \
12228 /* This is required for BDW+ where there is only one set of registers for
12229 * switching between high and low RR.
12230 * This macro can be used whenever a comparison has to be made between one
12231 * hw state and multiple sw state variables.
12233 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) do { \
12234 if (!intel_compare_link_m_n(¤t_config->name, \
12235 &pipe_config->name, adjust) && \
12236 !intel_compare_link_m_n(¤t_config->alt_name, \
12237 &pipe_config->name, adjust)) { \
12238 pipe_config_err(adjust, __stringify(name), \
12239 "(expected tu %i gmch %i/%i link %i/%i, " \
12240 "or tu %i gmch %i/%i link %i/%i, " \
12241 "found tu %i, gmch %i/%i link %i/%i)\n", \
12242 current_config->name.tu, \
12243 current_config->name.gmch_m, \
12244 current_config->name.gmch_n, \
12245 current_config->name.link_m, \
12246 current_config->name.link_n, \
12247 current_config->alt_name.tu, \
12248 current_config->alt_name.gmch_m, \
12249 current_config->alt_name.gmch_n, \
12250 current_config->alt_name.link_m, \
12251 current_config->alt_name.link_n, \
12252 pipe_config->name.tu, \
12253 pipe_config->name.gmch_m, \
12254 pipe_config->name.gmch_n, \
12255 pipe_config->name.link_m, \
12256 pipe_config->name.link_n); \
12261 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \
12262 if ((current_config->name ^ pipe_config->name) & (mask)) { \
12263 pipe_config_err(adjust, __stringify(name), \
12264 "(%x) (expected %i, found %i)\n", \
12266 current_config->name & (mask), \
12267 pipe_config->name & (mask)); \
12272 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) do { \
12273 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12274 pipe_config_err(adjust, __stringify(name), \
12275 "(expected %i, found %i)\n", \
12276 current_config->name, \
12277 pipe_config->name); \
12282 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \
12283 if (!intel_compare_infoframe(¤t_config->infoframes.name, \
12284 &pipe_config->infoframes.name)) { \
12285 pipe_config_infoframe_err(dev_priv, adjust, __stringify(name), \
12286 ¤t_config->infoframes.name, \
12287 &pipe_config->infoframes.name); \
12292 #define PIPE_CONF_QUIRK(quirk) \
12293 ((current_config->quirks | pipe_config->quirks) & (quirk))
12295 PIPE_CONF_CHECK_I(cpu_transcoder
);
12297 PIPE_CONF_CHECK_BOOL(has_pch_encoder
);
12298 PIPE_CONF_CHECK_I(fdi_lanes
);
12299 PIPE_CONF_CHECK_M_N(fdi_m_n
);
12301 PIPE_CONF_CHECK_I(lane_count
);
12302 PIPE_CONF_CHECK_X(lane_lat_optim_mask
);
12304 if (INTEL_GEN(dev_priv
) < 8) {
12305 PIPE_CONF_CHECK_M_N(dp_m_n
);
12307 if (current_config
->has_drrs
)
12308 PIPE_CONF_CHECK_M_N(dp_m2_n2
);
12310 PIPE_CONF_CHECK_M_N_ALT(dp_m_n
, dp_m2_n2
);
12312 PIPE_CONF_CHECK_X(output_types
);
12314 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hdisplay
);
12315 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_htotal
);
12316 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hblank_start
);
12317 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hblank_end
);
12318 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hsync_start
);
12319 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hsync_end
);
12321 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vdisplay
);
12322 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vtotal
);
12323 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vblank_start
);
12324 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vblank_end
);
12325 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vsync_start
);
12326 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vsync_end
);
12328 PIPE_CONF_CHECK_I(pixel_multiplier
);
12329 PIPE_CONF_CHECK_I(output_format
);
12330 PIPE_CONF_CHECK_BOOL(has_hdmi_sink
);
12331 if ((INTEL_GEN(dev_priv
) < 8 && !IS_HASWELL(dev_priv
)) ||
12332 IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
12333 PIPE_CONF_CHECK_BOOL(limited_color_range
);
12335 PIPE_CONF_CHECK_BOOL(hdmi_scrambling
);
12336 PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio
);
12337 PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_infoframe
);
12339 PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio
);
12341 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
12342 DRM_MODE_FLAG_INTERLACE
);
12344 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS
)) {
12345 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
12346 DRM_MODE_FLAG_PHSYNC
);
12347 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
12348 DRM_MODE_FLAG_NHSYNC
);
12349 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
12350 DRM_MODE_FLAG_PVSYNC
);
12351 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
12352 DRM_MODE_FLAG_NVSYNC
);
12355 PIPE_CONF_CHECK_X(gmch_pfit
.control
);
12356 /* pfit ratios are autocomputed by the hw on gen4+ */
12357 if (INTEL_GEN(dev_priv
) < 4)
12358 PIPE_CONF_CHECK_X(gmch_pfit
.pgm_ratios
);
12359 PIPE_CONF_CHECK_X(gmch_pfit
.lvds_border_bits
);
12362 PIPE_CONF_CHECK_I(pipe_src_w
);
12363 PIPE_CONF_CHECK_I(pipe_src_h
);
12365 PIPE_CONF_CHECK_BOOL(pch_pfit
.enabled
);
12366 if (current_config
->pch_pfit
.enabled
) {
12367 PIPE_CONF_CHECK_X(pch_pfit
.pos
);
12368 PIPE_CONF_CHECK_X(pch_pfit
.size
);
12371 PIPE_CONF_CHECK_I(scaler_state
.scaler_id
);
12372 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate
);
12374 PIPE_CONF_CHECK_X(gamma_mode
);
12375 if (IS_CHERRYVIEW(dev_priv
))
12376 PIPE_CONF_CHECK_X(cgm_mode
);
12378 PIPE_CONF_CHECK_X(csc_mode
);
12379 PIPE_CONF_CHECK_BOOL(gamma_enable
);
12380 PIPE_CONF_CHECK_BOOL(csc_enable
);
12383 PIPE_CONF_CHECK_BOOL(double_wide
);
12385 PIPE_CONF_CHECK_P(shared_dpll
);
12386 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll
);
12387 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll_md
);
12388 PIPE_CONF_CHECK_X(dpll_hw_state
.fp0
);
12389 PIPE_CONF_CHECK_X(dpll_hw_state
.fp1
);
12390 PIPE_CONF_CHECK_X(dpll_hw_state
.wrpll
);
12391 PIPE_CONF_CHECK_X(dpll_hw_state
.spll
);
12392 PIPE_CONF_CHECK_X(dpll_hw_state
.ctrl1
);
12393 PIPE_CONF_CHECK_X(dpll_hw_state
.cfgcr1
);
12394 PIPE_CONF_CHECK_X(dpll_hw_state
.cfgcr2
);
12395 PIPE_CONF_CHECK_X(dpll_hw_state
.cfgcr0
);
12396 PIPE_CONF_CHECK_X(dpll_hw_state
.ebb0
);
12397 PIPE_CONF_CHECK_X(dpll_hw_state
.ebb4
);
12398 PIPE_CONF_CHECK_X(dpll_hw_state
.pll0
);
12399 PIPE_CONF_CHECK_X(dpll_hw_state
.pll1
);
12400 PIPE_CONF_CHECK_X(dpll_hw_state
.pll2
);
12401 PIPE_CONF_CHECK_X(dpll_hw_state
.pll3
);
12402 PIPE_CONF_CHECK_X(dpll_hw_state
.pll6
);
12403 PIPE_CONF_CHECK_X(dpll_hw_state
.pll8
);
12404 PIPE_CONF_CHECK_X(dpll_hw_state
.pll9
);
12405 PIPE_CONF_CHECK_X(dpll_hw_state
.pll10
);
12406 PIPE_CONF_CHECK_X(dpll_hw_state
.pcsdw12
);
12407 PIPE_CONF_CHECK_X(dpll_hw_state
.mg_refclkin_ctl
);
12408 PIPE_CONF_CHECK_X(dpll_hw_state
.mg_clktop2_coreclkctl1
);
12409 PIPE_CONF_CHECK_X(dpll_hw_state
.mg_clktop2_hsclkctl
);
12410 PIPE_CONF_CHECK_X(dpll_hw_state
.mg_pll_div0
);
12411 PIPE_CONF_CHECK_X(dpll_hw_state
.mg_pll_div1
);
12412 PIPE_CONF_CHECK_X(dpll_hw_state
.mg_pll_lf
);
12413 PIPE_CONF_CHECK_X(dpll_hw_state
.mg_pll_frac_lock
);
12414 PIPE_CONF_CHECK_X(dpll_hw_state
.mg_pll_ssc
);
12415 PIPE_CONF_CHECK_X(dpll_hw_state
.mg_pll_bias
);
12416 PIPE_CONF_CHECK_X(dpll_hw_state
.mg_pll_tdc_coldst_bias
);
12418 PIPE_CONF_CHECK_X(dsi_pll
.ctrl
);
12419 PIPE_CONF_CHECK_X(dsi_pll
.div
);
12421 if (IS_G4X(dev_priv
) || INTEL_GEN(dev_priv
) >= 5)
12422 PIPE_CONF_CHECK_I(pipe_bpp
);
12424 PIPE_CONF_CHECK_CLOCK_FUZZY(base
.adjusted_mode
.crtc_clock
);
12425 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock
);
12427 PIPE_CONF_CHECK_I(min_voltage_level
);
12429 PIPE_CONF_CHECK_X(infoframes
.enable
);
12430 PIPE_CONF_CHECK_X(infoframes
.gcp
);
12431 PIPE_CONF_CHECK_INFOFRAME(avi
);
12432 PIPE_CONF_CHECK_INFOFRAME(spd
);
12433 PIPE_CONF_CHECK_INFOFRAME(hdmi
);
12435 #undef PIPE_CONF_CHECK_X
12436 #undef PIPE_CONF_CHECK_I
12437 #undef PIPE_CONF_CHECK_BOOL
12438 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE
12439 #undef PIPE_CONF_CHECK_P
12440 #undef PIPE_CONF_CHECK_FLAGS
12441 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12442 #undef PIPE_CONF_QUIRK
12447 static void intel_pipe_config_sanity_check(struct drm_i915_private
*dev_priv
,
12448 const struct intel_crtc_state
*pipe_config
)
12450 if (pipe_config
->has_pch_encoder
) {
12451 int fdi_dotclock
= intel_dotclock_calculate(intel_fdi_link_freq(dev_priv
, pipe_config
),
12452 &pipe_config
->fdi_m_n
);
12453 int dotclock
= pipe_config
->base
.adjusted_mode
.crtc_clock
;
12456 * FDI already provided one idea for the dotclock.
12457 * Yell if the encoder disagrees.
12459 WARN(!intel_fuzzy_clock_check(fdi_dotclock
, dotclock
),
12460 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12461 fdi_dotclock
, dotclock
);
12465 static void verify_wm_state(struct drm_crtc
*crtc
,
12466 struct drm_crtc_state
*new_state
)
12468 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
12469 struct skl_hw_state
{
12470 struct skl_ddb_entry ddb_y
[I915_MAX_PLANES
];
12471 struct skl_ddb_entry ddb_uv
[I915_MAX_PLANES
];
12472 struct skl_ddb_allocation ddb
;
12473 struct skl_pipe_wm wm
;
12475 struct skl_ddb_allocation
*sw_ddb
;
12476 struct skl_pipe_wm
*sw_wm
;
12477 struct skl_ddb_entry
*hw_ddb_entry
, *sw_ddb_entry
;
12478 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
12479 const enum pipe pipe
= intel_crtc
->pipe
;
12480 int plane
, level
, max_level
= ilk_wm_max_level(dev_priv
);
12482 if (INTEL_GEN(dev_priv
) < 9 || !new_state
->active
)
12485 hw
= kzalloc(sizeof(*hw
), GFP_KERNEL
);
12489 skl_pipe_wm_get_hw_state(intel_crtc
, &hw
->wm
);
12490 sw_wm
= &to_intel_crtc_state(new_state
)->wm
.skl
.optimal
;
12492 skl_pipe_ddb_get_hw_state(intel_crtc
, hw
->ddb_y
, hw
->ddb_uv
);
12494 skl_ddb_get_hw_state(dev_priv
, &hw
->ddb
);
12495 sw_ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
12497 if (INTEL_GEN(dev_priv
) >= 11 &&
12498 hw
->ddb
.enabled_slices
!= sw_ddb
->enabled_slices
)
12499 DRM_ERROR("mismatch in DBUF Slices (expected %u, got %u)\n",
12500 sw_ddb
->enabled_slices
,
12501 hw
->ddb
.enabled_slices
);
12504 for_each_universal_plane(dev_priv
, pipe
, plane
) {
12505 struct skl_plane_wm
*hw_plane_wm
, *sw_plane_wm
;
12507 hw_plane_wm
= &hw
->wm
.planes
[plane
];
12508 sw_plane_wm
= &sw_wm
->planes
[plane
];
12511 for (level
= 0; level
<= max_level
; level
++) {
12512 if (skl_wm_level_equals(&hw_plane_wm
->wm
[level
],
12513 &sw_plane_wm
->wm
[level
]))
12516 DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
12517 pipe_name(pipe
), plane
+ 1, level
,
12518 sw_plane_wm
->wm
[level
].plane_en
,
12519 sw_plane_wm
->wm
[level
].plane_res_b
,
12520 sw_plane_wm
->wm
[level
].plane_res_l
,
12521 hw_plane_wm
->wm
[level
].plane_en
,
12522 hw_plane_wm
->wm
[level
].plane_res_b
,
12523 hw_plane_wm
->wm
[level
].plane_res_l
);
12526 if (!skl_wm_level_equals(&hw_plane_wm
->trans_wm
,
12527 &sw_plane_wm
->trans_wm
)) {
12528 DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
12529 pipe_name(pipe
), plane
+ 1,
12530 sw_plane_wm
->trans_wm
.plane_en
,
12531 sw_plane_wm
->trans_wm
.plane_res_b
,
12532 sw_plane_wm
->trans_wm
.plane_res_l
,
12533 hw_plane_wm
->trans_wm
.plane_en
,
12534 hw_plane_wm
->trans_wm
.plane_res_b
,
12535 hw_plane_wm
->trans_wm
.plane_res_l
);
12539 hw_ddb_entry
= &hw
->ddb_y
[plane
];
12540 sw_ddb_entry
= &to_intel_crtc_state(new_state
)->wm
.skl
.plane_ddb_y
[plane
];
12542 if (!skl_ddb_entry_equal(hw_ddb_entry
, sw_ddb_entry
)) {
12543 DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
12544 pipe_name(pipe
), plane
+ 1,
12545 sw_ddb_entry
->start
, sw_ddb_entry
->end
,
12546 hw_ddb_entry
->start
, hw_ddb_entry
->end
);
12552 * If the cursor plane isn't active, we may not have updated it's ddb
12553 * allocation. In that case since the ddb allocation will be updated
12554 * once the plane becomes visible, we can skip this check
12557 struct skl_plane_wm
*hw_plane_wm
, *sw_plane_wm
;
12559 hw_plane_wm
= &hw
->wm
.planes
[PLANE_CURSOR
];
12560 sw_plane_wm
= &sw_wm
->planes
[PLANE_CURSOR
];
12563 for (level
= 0; level
<= max_level
; level
++) {
12564 if (skl_wm_level_equals(&hw_plane_wm
->wm
[level
],
12565 &sw_plane_wm
->wm
[level
]))
12568 DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
12569 pipe_name(pipe
), level
,
12570 sw_plane_wm
->wm
[level
].plane_en
,
12571 sw_plane_wm
->wm
[level
].plane_res_b
,
12572 sw_plane_wm
->wm
[level
].plane_res_l
,
12573 hw_plane_wm
->wm
[level
].plane_en
,
12574 hw_plane_wm
->wm
[level
].plane_res_b
,
12575 hw_plane_wm
->wm
[level
].plane_res_l
);
12578 if (!skl_wm_level_equals(&hw_plane_wm
->trans_wm
,
12579 &sw_plane_wm
->trans_wm
)) {
12580 DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
12582 sw_plane_wm
->trans_wm
.plane_en
,
12583 sw_plane_wm
->trans_wm
.plane_res_b
,
12584 sw_plane_wm
->trans_wm
.plane_res_l
,
12585 hw_plane_wm
->trans_wm
.plane_en
,
12586 hw_plane_wm
->trans_wm
.plane_res_b
,
12587 hw_plane_wm
->trans_wm
.plane_res_l
);
12591 hw_ddb_entry
= &hw
->ddb_y
[PLANE_CURSOR
];
12592 sw_ddb_entry
= &to_intel_crtc_state(new_state
)->wm
.skl
.plane_ddb_y
[PLANE_CURSOR
];
12594 if (!skl_ddb_entry_equal(hw_ddb_entry
, sw_ddb_entry
)) {
12595 DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
12597 sw_ddb_entry
->start
, sw_ddb_entry
->end
,
12598 hw_ddb_entry
->start
, hw_ddb_entry
->end
);
12606 verify_connector_state(struct drm_device
*dev
,
12607 struct drm_atomic_state
*state
,
12608 struct drm_crtc
*crtc
)
12610 struct drm_connector
*connector
;
12611 struct drm_connector_state
*new_conn_state
;
12614 for_each_new_connector_in_state(state
, connector
, new_conn_state
, i
) {
12615 struct drm_encoder
*encoder
= connector
->encoder
;
12616 struct drm_crtc_state
*crtc_state
= NULL
;
12618 if (new_conn_state
->crtc
!= crtc
)
12622 crtc_state
= drm_atomic_get_new_crtc_state(state
, new_conn_state
->crtc
);
12624 intel_connector_verify_state(crtc_state
, new_conn_state
);
12626 I915_STATE_WARN(new_conn_state
->best_encoder
!= encoder
,
12627 "connector's atomic encoder doesn't match legacy encoder\n");
12632 verify_encoder_state(struct drm_device
*dev
, struct drm_atomic_state
*state
)
12634 struct intel_encoder
*encoder
;
12635 struct drm_connector
*connector
;
12636 struct drm_connector_state
*old_conn_state
, *new_conn_state
;
12639 for_each_intel_encoder(dev
, encoder
) {
12640 bool enabled
= false, found
= false;
12643 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12644 encoder
->base
.base
.id
,
12645 encoder
->base
.name
);
12647 for_each_oldnew_connector_in_state(state
, connector
, old_conn_state
,
12648 new_conn_state
, i
) {
12649 if (old_conn_state
->best_encoder
== &encoder
->base
)
12652 if (new_conn_state
->best_encoder
!= &encoder
->base
)
12654 found
= enabled
= true;
12656 I915_STATE_WARN(new_conn_state
->crtc
!=
12657 encoder
->base
.crtc
,
12658 "connector's crtc doesn't match encoder crtc\n");
12664 I915_STATE_WARN(!!encoder
->base
.crtc
!= enabled
,
12665 "encoder's enabled state mismatch "
12666 "(expected %i, found %i)\n",
12667 !!encoder
->base
.crtc
, enabled
);
12669 if (!encoder
->base
.crtc
) {
12672 active
= encoder
->get_hw_state(encoder
, &pipe
);
12673 I915_STATE_WARN(active
,
12674 "encoder detached but still enabled on pipe %c.\n",
12681 verify_crtc_state(struct drm_crtc
*crtc
,
12682 struct drm_crtc_state
*old_crtc_state
,
12683 struct drm_crtc_state
*new_crtc_state
)
12685 struct drm_device
*dev
= crtc
->dev
;
12686 struct drm_i915_private
*dev_priv
= to_i915(dev
);
12687 struct intel_encoder
*encoder
;
12688 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
12689 struct intel_crtc_state
*pipe_config
, *sw_config
;
12690 struct drm_atomic_state
*old_state
;
12693 old_state
= old_crtc_state
->state
;
12694 __drm_atomic_helper_crtc_destroy_state(old_crtc_state
);
12695 pipe_config
= to_intel_crtc_state(old_crtc_state
);
12696 memset(pipe_config
, 0, sizeof(*pipe_config
));
12697 pipe_config
->base
.crtc
= crtc
;
12698 pipe_config
->base
.state
= old_state
;
12700 DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc
->base
.id
, crtc
->name
);
12702 active
= dev_priv
->display
.get_pipe_config(intel_crtc
, pipe_config
);
12704 /* we keep both pipes enabled on 830 */
12705 if (IS_I830(dev_priv
))
12706 active
= new_crtc_state
->active
;
12708 I915_STATE_WARN(new_crtc_state
->active
!= active
,
12709 "crtc active state doesn't match with hw state "
12710 "(expected %i, found %i)\n", new_crtc_state
->active
, active
);
12712 I915_STATE_WARN(intel_crtc
->active
!= new_crtc_state
->active
,
12713 "transitional active state does not match atomic hw state "
12714 "(expected %i, found %i)\n", new_crtc_state
->active
, intel_crtc
->active
);
12716 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
12719 active
= encoder
->get_hw_state(encoder
, &pipe
);
12720 I915_STATE_WARN(active
!= new_crtc_state
->active
,
12721 "[ENCODER:%i] active %i with crtc active %i\n",
12722 encoder
->base
.base
.id
, active
, new_crtc_state
->active
);
12724 I915_STATE_WARN(active
&& intel_crtc
->pipe
!= pipe
,
12725 "Encoder connected to wrong pipe %c\n",
12729 encoder
->get_config(encoder
, pipe_config
);
12732 intel_crtc_compute_pixel_rate(pipe_config
);
12734 if (!new_crtc_state
->active
)
12737 intel_pipe_config_sanity_check(dev_priv
, pipe_config
);
12739 sw_config
= to_intel_crtc_state(new_crtc_state
);
12740 if (!intel_pipe_config_compare(dev_priv
, sw_config
,
12741 pipe_config
, false)) {
12742 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12743 intel_dump_pipe_config(intel_crtc
, pipe_config
,
12745 intel_dump_pipe_config(intel_crtc
, sw_config
,
12751 intel_verify_planes(struct intel_atomic_state
*state
)
12753 struct intel_plane
*plane
;
12754 const struct intel_plane_state
*plane_state
;
12757 for_each_new_intel_plane_in_state(state
, plane
,
12759 assert_plane(plane
, plane_state
->slave
||
12760 plane_state
->base
.visible
);
12764 verify_single_dpll_state(struct drm_i915_private
*dev_priv
,
12765 struct intel_shared_dpll
*pll
,
12766 struct drm_crtc
*crtc
,
12767 struct drm_crtc_state
*new_state
)
12769 struct intel_dpll_hw_state dpll_hw_state
;
12770 unsigned int crtc_mask
;
12773 memset(&dpll_hw_state
, 0, sizeof(dpll_hw_state
));
12775 DRM_DEBUG_KMS("%s\n", pll
->info
->name
);
12777 active
= pll
->info
->funcs
->get_hw_state(dev_priv
, pll
, &dpll_hw_state
);
12779 if (!(pll
->info
->flags
& INTEL_DPLL_ALWAYS_ON
)) {
12780 I915_STATE_WARN(!pll
->on
&& pll
->active_mask
,
12781 "pll in active use but not on in sw tracking\n");
12782 I915_STATE_WARN(pll
->on
&& !pll
->active_mask
,
12783 "pll is on but not used by any active crtc\n");
12784 I915_STATE_WARN(pll
->on
!= active
,
12785 "pll on state mismatch (expected %i, found %i)\n",
12790 I915_STATE_WARN(pll
->active_mask
& ~pll
->state
.crtc_mask
,
12791 "more active pll users than references: %x vs %x\n",
12792 pll
->active_mask
, pll
->state
.crtc_mask
);
12797 crtc_mask
= drm_crtc_mask(crtc
);
12799 if (new_state
->active
)
12800 I915_STATE_WARN(!(pll
->active_mask
& crtc_mask
),
12801 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
12802 pipe_name(drm_crtc_index(crtc
)), pll
->active_mask
);
12804 I915_STATE_WARN(pll
->active_mask
& crtc_mask
,
12805 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
12806 pipe_name(drm_crtc_index(crtc
)), pll
->active_mask
);
12808 I915_STATE_WARN(!(pll
->state
.crtc_mask
& crtc_mask
),
12809 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
12810 crtc_mask
, pll
->state
.crtc_mask
);
12812 I915_STATE_WARN(pll
->on
&& memcmp(&pll
->state
.hw_state
,
12814 sizeof(dpll_hw_state
)),
12815 "pll hw state mismatch\n");
12819 verify_shared_dpll_state(struct drm_device
*dev
, struct drm_crtc
*crtc
,
12820 struct drm_crtc_state
*old_crtc_state
,
12821 struct drm_crtc_state
*new_crtc_state
)
12823 struct drm_i915_private
*dev_priv
= to_i915(dev
);
12824 struct intel_crtc_state
*old_state
= to_intel_crtc_state(old_crtc_state
);
12825 struct intel_crtc_state
*new_state
= to_intel_crtc_state(new_crtc_state
);
12827 if (new_state
->shared_dpll
)
12828 verify_single_dpll_state(dev_priv
, new_state
->shared_dpll
, crtc
, new_crtc_state
);
12830 if (old_state
->shared_dpll
&&
12831 old_state
->shared_dpll
!= new_state
->shared_dpll
) {
12832 unsigned int crtc_mask
= drm_crtc_mask(crtc
);
12833 struct intel_shared_dpll
*pll
= old_state
->shared_dpll
;
12835 I915_STATE_WARN(pll
->active_mask
& crtc_mask
,
12836 "pll active mismatch (didn't expect pipe %c in active mask)\n",
12837 pipe_name(drm_crtc_index(crtc
)));
12838 I915_STATE_WARN(pll
->state
.crtc_mask
& crtc_mask
,
12839 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
12840 pipe_name(drm_crtc_index(crtc
)));
12845 intel_modeset_verify_crtc(struct drm_crtc
*crtc
,
12846 struct drm_atomic_state
*state
,
12847 struct drm_crtc_state
*old_state
,
12848 struct drm_crtc_state
*new_state
)
12850 if (!needs_modeset(new_state
) &&
12851 !to_intel_crtc_state(new_state
)->update_pipe
)
12854 verify_wm_state(crtc
, new_state
);
12855 verify_connector_state(crtc
->dev
, state
, crtc
);
12856 verify_crtc_state(crtc
, old_state
, new_state
);
12857 verify_shared_dpll_state(crtc
->dev
, crtc
, old_state
, new_state
);
12861 verify_disabled_dpll_state(struct drm_device
*dev
)
12863 struct drm_i915_private
*dev_priv
= to_i915(dev
);
12866 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++)
12867 verify_single_dpll_state(dev_priv
, &dev_priv
->shared_dplls
[i
], NULL
, NULL
);
12871 intel_modeset_verify_disabled(struct drm_device
*dev
,
12872 struct drm_atomic_state
*state
)
12874 verify_encoder_state(dev
, state
);
12875 verify_connector_state(dev
, state
, NULL
);
12876 verify_disabled_dpll_state(dev
);
12879 static void update_scanline_offset(const struct intel_crtc_state
*crtc_state
)
12881 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
12882 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
12885 * The scanline counter increments at the leading edge of hsync.
12887 * On most platforms it starts counting from vtotal-1 on the
12888 * first active line. That means the scanline counter value is
12889 * always one less than what we would expect. Ie. just after
12890 * start of vblank, which also occurs at start of hsync (on the
12891 * last active line), the scanline counter will read vblank_start-1.
12893 * On gen2 the scanline counter starts counting from 1 instead
12894 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12895 * to keep the value positive), instead of adding one.
12897 * On HSW+ the behaviour of the scanline counter depends on the output
12898 * type. For DP ports it behaves like most other platforms, but on HDMI
12899 * there's an extra 1 line difference. So we need to add two instead of
12900 * one to the value.
12902 * On VLV/CHV DSI the scanline counter would appear to increment
12903 * approx. 1/3 of a scanline before start of vblank. Unfortunately
12904 * that means we can't tell whether we're in vblank or not while
12905 * we're on that particular line. We must still set scanline_offset
12906 * to 1 so that the vblank timestamps come out correct when we query
12907 * the scanline counter from within the vblank interrupt handler.
12908 * However if queried just before the start of vblank we'll get an
12909 * answer that's slightly in the future.
12911 if (IS_GEN(dev_priv
, 2)) {
12912 const struct drm_display_mode
*adjusted_mode
= &crtc_state
->base
.adjusted_mode
;
12915 vtotal
= adjusted_mode
->crtc_vtotal
;
12916 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
12919 crtc
->scanline_offset
= vtotal
- 1;
12920 } else if (HAS_DDI(dev_priv
) &&
12921 intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_HDMI
)) {
12922 crtc
->scanline_offset
= 2;
12924 crtc
->scanline_offset
= 1;
12927 static void intel_modeset_clear_plls(struct drm_atomic_state
*state
)
12929 struct drm_device
*dev
= state
->dev
;
12930 struct drm_i915_private
*dev_priv
= to_i915(dev
);
12931 struct drm_crtc
*crtc
;
12932 struct drm_crtc_state
*old_crtc_state
, *new_crtc_state
;
12935 if (!dev_priv
->display
.crtc_compute_clock
)
12938 for_each_oldnew_crtc_in_state(state
, crtc
, old_crtc_state
, new_crtc_state
, i
) {
12939 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
12940 struct intel_shared_dpll
*old_dpll
=
12941 to_intel_crtc_state(old_crtc_state
)->shared_dpll
;
12943 if (!needs_modeset(new_crtc_state
))
12946 to_intel_crtc_state(new_crtc_state
)->shared_dpll
= NULL
;
12951 intel_release_shared_dpll(old_dpll
, intel_crtc
, state
);
12956 * This implements the workaround described in the "notes" section of the mode
12957 * set sequence documentation. When going from no pipes or single pipe to
12958 * multiple pipes, and planes are enabled after the pipe, we need to wait at
12959 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12961 static int haswell_mode_set_planes_workaround(struct drm_atomic_state
*state
)
12963 struct drm_crtc_state
*crtc_state
;
12964 struct intel_crtc
*intel_crtc
;
12965 struct drm_crtc
*crtc
;
12966 struct intel_crtc_state
*first_crtc_state
= NULL
;
12967 struct intel_crtc_state
*other_crtc_state
= NULL
;
12968 enum pipe first_pipe
= INVALID_PIPE
, enabled_pipe
= INVALID_PIPE
;
12971 /* look at all crtc's that are going to be enabled in during modeset */
12972 for_each_new_crtc_in_state(state
, crtc
, crtc_state
, i
) {
12973 intel_crtc
= to_intel_crtc(crtc
);
12975 if (!crtc_state
->active
|| !needs_modeset(crtc_state
))
12978 if (first_crtc_state
) {
12979 other_crtc_state
= to_intel_crtc_state(crtc_state
);
12982 first_crtc_state
= to_intel_crtc_state(crtc_state
);
12983 first_pipe
= intel_crtc
->pipe
;
12987 /* No workaround needed? */
12988 if (!first_crtc_state
)
12991 /* w/a possibly needed, check how many crtc's are already enabled. */
12992 for_each_intel_crtc(state
->dev
, intel_crtc
) {
12993 struct intel_crtc_state
*pipe_config
;
12995 pipe_config
= intel_atomic_get_crtc_state(state
, intel_crtc
);
12996 if (IS_ERR(pipe_config
))
12997 return PTR_ERR(pipe_config
);
12999 pipe_config
->hsw_workaround_pipe
= INVALID_PIPE
;
13001 if (!pipe_config
->base
.active
||
13002 needs_modeset(&pipe_config
->base
))
13005 /* 2 or more enabled crtcs means no need for w/a */
13006 if (enabled_pipe
!= INVALID_PIPE
)
13009 enabled_pipe
= intel_crtc
->pipe
;
13012 if (enabled_pipe
!= INVALID_PIPE
)
13013 first_crtc_state
->hsw_workaround_pipe
= enabled_pipe
;
13014 else if (other_crtc_state
)
13015 other_crtc_state
->hsw_workaround_pipe
= first_pipe
;
13020 static int intel_lock_all_pipes(struct drm_atomic_state
*state
)
13022 struct drm_crtc
*crtc
;
13024 /* Add all pipes to the state */
13025 for_each_crtc(state
->dev
, crtc
) {
13026 struct drm_crtc_state
*crtc_state
;
13028 crtc_state
= drm_atomic_get_crtc_state(state
, crtc
);
13029 if (IS_ERR(crtc_state
))
13030 return PTR_ERR(crtc_state
);
13036 static int intel_modeset_all_pipes(struct drm_atomic_state
*state
)
13038 struct drm_crtc
*crtc
;
13041 * Add all pipes to the state, and force
13042 * a modeset on all the active ones.
13044 for_each_crtc(state
->dev
, crtc
) {
13045 struct drm_crtc_state
*crtc_state
;
13048 crtc_state
= drm_atomic_get_crtc_state(state
, crtc
);
13049 if (IS_ERR(crtc_state
))
13050 return PTR_ERR(crtc_state
);
13052 if (!crtc_state
->active
|| needs_modeset(crtc_state
))
13055 crtc_state
->mode_changed
= true;
13057 ret
= drm_atomic_add_affected_connectors(state
, crtc
);
13061 ret
= drm_atomic_add_affected_planes(state
, crtc
);
13069 static int intel_modeset_checks(struct drm_atomic_state
*state
)
13071 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
13072 struct drm_i915_private
*dev_priv
= to_i915(state
->dev
);
13073 struct drm_crtc
*crtc
;
13074 struct drm_crtc_state
*old_crtc_state
, *new_crtc_state
;
13077 if (!check_digital_port_conflicts(state
)) {
13078 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13082 /* keep the current setting */
13083 if (!intel_state
->cdclk
.force_min_cdclk_changed
)
13084 intel_state
->cdclk
.force_min_cdclk
=
13085 dev_priv
->cdclk
.force_min_cdclk
;
13087 intel_state
->modeset
= true;
13088 intel_state
->active_crtcs
= dev_priv
->active_crtcs
;
13089 intel_state
->cdclk
.logical
= dev_priv
->cdclk
.logical
;
13090 intel_state
->cdclk
.actual
= dev_priv
->cdclk
.actual
;
13091 intel_state
->cdclk
.pipe
= INVALID_PIPE
;
13093 for_each_oldnew_crtc_in_state(state
, crtc
, old_crtc_state
, new_crtc_state
, i
) {
13094 if (new_crtc_state
->active
)
13095 intel_state
->active_crtcs
|= 1 << i
;
13097 intel_state
->active_crtcs
&= ~(1 << i
);
13099 if (old_crtc_state
->active
!= new_crtc_state
->active
)
13100 intel_state
->active_pipe_changes
|= drm_crtc_mask(crtc
);
13104 * See if the config requires any additional preparation, e.g.
13105 * to adjust global state with pipes off. We need to do this
13106 * here so we can get the modeset_pipe updated config for the new
13107 * mode set on this crtc. For other crtcs we need to use the
13108 * adjusted_mode bits in the crtc directly.
13110 if (dev_priv
->display
.modeset_calc_cdclk
) {
13113 ret
= dev_priv
->display
.modeset_calc_cdclk(state
);
13118 * Writes to dev_priv->cdclk.logical must protected by
13119 * holding all the crtc locks, even if we don't end up
13120 * touching the hardware
13122 if (intel_cdclk_changed(&dev_priv
->cdclk
.logical
,
13123 &intel_state
->cdclk
.logical
)) {
13124 ret
= intel_lock_all_pipes(state
);
13129 if (is_power_of_2(intel_state
->active_crtcs
)) {
13130 struct drm_crtc
*crtc
;
13131 struct drm_crtc_state
*crtc_state
;
13133 pipe
= ilog2(intel_state
->active_crtcs
);
13134 crtc
= &intel_get_crtc_for_pipe(dev_priv
, pipe
)->base
;
13135 crtc_state
= drm_atomic_get_new_crtc_state(state
, crtc
);
13136 if (crtc_state
&& needs_modeset(crtc_state
))
13137 pipe
= INVALID_PIPE
;
13139 pipe
= INVALID_PIPE
;
13142 /* All pipes must be switched off while we change the cdclk. */
13143 if (pipe
!= INVALID_PIPE
&&
13144 intel_cdclk_needs_cd2x_update(dev_priv
,
13145 &dev_priv
->cdclk
.actual
,
13146 &intel_state
->cdclk
.actual
)) {
13147 ret
= intel_lock_all_pipes(state
);
13151 intel_state
->cdclk
.pipe
= pipe
;
13152 } else if (intel_cdclk_needs_modeset(&dev_priv
->cdclk
.actual
,
13153 &intel_state
->cdclk
.actual
)) {
13154 ret
= intel_modeset_all_pipes(state
);
13158 intel_state
->cdclk
.pipe
= INVALID_PIPE
;
13161 DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n",
13162 intel_state
->cdclk
.logical
.cdclk
,
13163 intel_state
->cdclk
.actual
.cdclk
);
13164 DRM_DEBUG_KMS("New voltage level calculated to be logical %u, actual %u\n",
13165 intel_state
->cdclk
.logical
.voltage_level
,
13166 intel_state
->cdclk
.actual
.voltage_level
);
13169 intel_modeset_clear_plls(state
);
13171 if (IS_HASWELL(dev_priv
))
13172 return haswell_mode_set_planes_workaround(state
);
13178 * Handle calculation of various watermark data at the end of the atomic check
13179 * phase. The code here should be run after the per-crtc and per-plane 'check'
13180 * handlers to ensure that all derived state has been updated.
13182 static int calc_watermark_data(struct intel_atomic_state
*state
)
13184 struct drm_device
*dev
= state
->base
.dev
;
13185 struct drm_i915_private
*dev_priv
= to_i915(dev
);
13187 /* Is there platform-specific watermark information to calculate? */
13188 if (dev_priv
->display
.compute_global_watermarks
)
13189 return dev_priv
->display
.compute_global_watermarks(state
);
13195 * intel_atomic_check - validate state object
13197 * @state: state to validate
13199 static int intel_atomic_check(struct drm_device
*dev
,
13200 struct drm_atomic_state
*state
)
13202 struct drm_i915_private
*dev_priv
= to_i915(dev
);
13203 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
13204 struct drm_crtc
*crtc
;
13205 struct drm_crtc_state
*old_crtc_state
, *crtc_state
;
13207 bool any_ms
= intel_state
->cdclk
.force_min_cdclk_changed
;
13209 /* Catch I915_MODE_FLAG_INHERITED */
13210 for_each_oldnew_crtc_in_state(state
, crtc
, old_crtc_state
,
13212 if (crtc_state
->mode
.private_flags
!=
13213 old_crtc_state
->mode
.private_flags
)
13214 crtc_state
->mode_changed
= true;
13217 ret
= drm_atomic_helper_check_modeset(dev
, state
);
13221 for_each_oldnew_crtc_in_state(state
, crtc
, old_crtc_state
, crtc_state
, i
) {
13222 struct intel_crtc_state
*pipe_config
=
13223 to_intel_crtc_state(crtc_state
);
13225 if (!needs_modeset(crtc_state
))
13228 if (!crtc_state
->enable
) {
13233 ret
= intel_modeset_pipe_config(crtc
, pipe_config
);
13234 if (ret
== -EDEADLK
)
13237 intel_dump_pipe_config(to_intel_crtc(crtc
),
13238 pipe_config
, "[failed]");
13242 if (intel_pipe_config_compare(dev_priv
,
13243 to_intel_crtc_state(old_crtc_state
),
13244 pipe_config
, true)) {
13245 crtc_state
->mode_changed
= false;
13246 pipe_config
->update_pipe
= true;
13249 if (needs_modeset(crtc_state
))
13252 intel_dump_pipe_config(to_intel_crtc(crtc
), pipe_config
,
13253 needs_modeset(crtc_state
) ?
13254 "[modeset]" : "[fastset]");
13257 ret
= drm_dp_mst_atomic_check(state
);
13262 ret
= intel_modeset_checks(state
);
13267 intel_state
->cdclk
.logical
= dev_priv
->cdclk
.logical
;
13270 ret
= icl_add_linked_planes(intel_state
);
13274 ret
= drm_atomic_helper_check_planes(dev
, state
);
13278 intel_fbc_choose_crtc(dev_priv
, intel_state
);
13279 return calc_watermark_data(intel_state
);
13282 static int intel_atomic_prepare_commit(struct drm_device
*dev
,
13283 struct drm_atomic_state
*state
)
13285 return drm_atomic_helper_prepare_planes(dev
, state
);
13288 u32
intel_crtc_get_vblank_counter(struct intel_crtc
*crtc
)
13290 struct drm_device
*dev
= crtc
->base
.dev
;
13291 struct drm_vblank_crtc
*vblank
= &dev
->vblank
[drm_crtc_index(&crtc
->base
)];
13293 if (!vblank
->max_vblank_count
)
13294 return (u32
)drm_crtc_accurate_vblank_count(&crtc
->base
);
13296 return dev
->driver
->get_vblank_counter(dev
, crtc
->pipe
);
13299 static void intel_update_crtc(struct drm_crtc
*crtc
,
13300 struct drm_atomic_state
*state
,
13301 struct drm_crtc_state
*old_crtc_state
,
13302 struct drm_crtc_state
*new_crtc_state
)
13304 struct drm_device
*dev
= crtc
->dev
;
13305 struct drm_i915_private
*dev_priv
= to_i915(dev
);
13306 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
13307 struct intel_crtc_state
*pipe_config
= to_intel_crtc_state(new_crtc_state
);
13308 bool modeset
= needs_modeset(new_crtc_state
);
13309 struct intel_plane_state
*new_plane_state
=
13310 intel_atomic_get_new_plane_state(to_intel_atomic_state(state
),
13311 to_intel_plane(crtc
->primary
));
13314 update_scanline_offset(pipe_config
);
13315 dev_priv
->display
.crtc_enable(pipe_config
, state
);
13317 /* vblanks work again, re-enable pipe CRC. */
13318 intel_crtc_enable_pipe_crc(intel_crtc
);
13320 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state
),
13323 if (pipe_config
->update_pipe
)
13324 intel_encoders_update_pipe(crtc
, pipe_config
, state
);
13327 if (pipe_config
->update_pipe
&& !pipe_config
->enable_fbc
)
13328 intel_fbc_disable(intel_crtc
);
13329 else if (new_plane_state
)
13330 intel_fbc_enable(intel_crtc
, pipe_config
, new_plane_state
);
13332 intel_begin_crtc_commit(to_intel_atomic_state(state
), intel_crtc
);
13334 if (INTEL_GEN(dev_priv
) >= 9)
13335 skl_update_planes_on_crtc(to_intel_atomic_state(state
), intel_crtc
);
13337 i9xx_update_planes_on_crtc(to_intel_atomic_state(state
), intel_crtc
);
13339 intel_finish_crtc_commit(to_intel_atomic_state(state
), intel_crtc
);
13342 static void intel_update_crtcs(struct drm_atomic_state
*state
)
13344 struct drm_crtc
*crtc
;
13345 struct drm_crtc_state
*old_crtc_state
, *new_crtc_state
;
13348 for_each_oldnew_crtc_in_state(state
, crtc
, old_crtc_state
, new_crtc_state
, i
) {
13349 if (!new_crtc_state
->active
)
13352 intel_update_crtc(crtc
, state
, old_crtc_state
,
13357 static void skl_update_crtcs(struct drm_atomic_state
*state
)
13359 struct drm_i915_private
*dev_priv
= to_i915(state
->dev
);
13360 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
13361 struct drm_crtc
*crtc
;
13362 struct intel_crtc
*intel_crtc
;
13363 struct drm_crtc_state
*old_crtc_state
, *new_crtc_state
;
13364 struct intel_crtc_state
*cstate
;
13365 unsigned int updated
= 0;
13369 u8 hw_enabled_slices
= dev_priv
->wm
.skl_hw
.ddb
.enabled_slices
;
13370 u8 required_slices
= intel_state
->wm_results
.ddb
.enabled_slices
;
13371 struct skl_ddb_entry entries
[I915_MAX_PIPES
] = {};
13373 for_each_oldnew_crtc_in_state(state
, crtc
, old_crtc_state
, new_crtc_state
, i
)
13374 /* ignore allocations for crtc's that have been turned off. */
13375 if (new_crtc_state
->active
)
13376 entries
[i
] = to_intel_crtc_state(old_crtc_state
)->wm
.skl
.ddb
;
13378 /* If 2nd DBuf slice required, enable it here */
13379 if (INTEL_GEN(dev_priv
) >= 11 && required_slices
> hw_enabled_slices
)
13380 icl_dbuf_slices_update(dev_priv
, required_slices
);
13383 * Whenever the number of active pipes changes, we need to make sure we
13384 * update the pipes in the right order so that their ddb allocations
13385 * never overlap with eachother inbetween CRTC updates. Otherwise we'll
13386 * cause pipe underruns and other bad stuff.
13391 for_each_oldnew_crtc_in_state(state
, crtc
, old_crtc_state
, new_crtc_state
, i
) {
13392 bool vbl_wait
= false;
13393 unsigned int cmask
= drm_crtc_mask(crtc
);
13395 intel_crtc
= to_intel_crtc(crtc
);
13396 cstate
= to_intel_crtc_state(new_crtc_state
);
13397 pipe
= intel_crtc
->pipe
;
13399 if (updated
& cmask
|| !cstate
->base
.active
)
13402 if (skl_ddb_allocation_overlaps(&cstate
->wm
.skl
.ddb
,
13404 INTEL_INFO(dev_priv
)->num_pipes
, i
))
13408 entries
[i
] = cstate
->wm
.skl
.ddb
;
13411 * If this is an already active pipe, it's DDB changed,
13412 * and this isn't the last pipe that needs updating
13413 * then we need to wait for a vblank to pass for the
13414 * new ddb allocation to take effect.
13416 if (!skl_ddb_entry_equal(&cstate
->wm
.skl
.ddb
,
13417 &to_intel_crtc_state(old_crtc_state
)->wm
.skl
.ddb
) &&
13418 !new_crtc_state
->active_changed
&&
13419 intel_state
->wm_results
.dirty_pipes
!= updated
)
13422 intel_update_crtc(crtc
, state
, old_crtc_state
,
13426 intel_wait_for_vblank(dev_priv
, pipe
);
13430 } while (progress
);
13432 /* If 2nd DBuf slice is no more required disable it */
13433 if (INTEL_GEN(dev_priv
) >= 11 && required_slices
< hw_enabled_slices
)
13434 icl_dbuf_slices_update(dev_priv
, required_slices
);
13437 static void intel_atomic_helper_free_state(struct drm_i915_private
*dev_priv
)
13439 struct intel_atomic_state
*state
, *next
;
13440 struct llist_node
*freed
;
13442 freed
= llist_del_all(&dev_priv
->atomic_helper
.free_list
);
13443 llist_for_each_entry_safe(state
, next
, freed
, freed
)
13444 drm_atomic_state_put(&state
->base
);
13447 static void intel_atomic_helper_free_state_worker(struct work_struct
*work
)
13449 struct drm_i915_private
*dev_priv
=
13450 container_of(work
, typeof(*dev_priv
), atomic_helper
.free_work
);
13452 intel_atomic_helper_free_state(dev_priv
);
13455 static void intel_atomic_commit_fence_wait(struct intel_atomic_state
*intel_state
)
13457 struct wait_queue_entry wait_fence
, wait_reset
;
13458 struct drm_i915_private
*dev_priv
= to_i915(intel_state
->base
.dev
);
13460 init_wait_entry(&wait_fence
, 0);
13461 init_wait_entry(&wait_reset
, 0);
13463 prepare_to_wait(&intel_state
->commit_ready
.wait
,
13464 &wait_fence
, TASK_UNINTERRUPTIBLE
);
13465 prepare_to_wait(&dev_priv
->gpu_error
.wait_queue
,
13466 &wait_reset
, TASK_UNINTERRUPTIBLE
);
13469 if (i915_sw_fence_done(&intel_state
->commit_ready
)
13470 || test_bit(I915_RESET_MODESET
, &dev_priv
->gpu_error
.flags
))
13475 finish_wait(&intel_state
->commit_ready
.wait
, &wait_fence
);
13476 finish_wait(&dev_priv
->gpu_error
.wait_queue
, &wait_reset
);
13479 static void intel_atomic_cleanup_work(struct work_struct
*work
)
13481 struct drm_atomic_state
*state
=
13482 container_of(work
, struct drm_atomic_state
, commit_work
);
13483 struct drm_i915_private
*i915
= to_i915(state
->dev
);
13485 drm_atomic_helper_cleanup_planes(&i915
->drm
, state
);
13486 drm_atomic_helper_commit_cleanup_done(state
);
13487 drm_atomic_state_put(state
);
13489 intel_atomic_helper_free_state(i915
);
13492 static void intel_atomic_commit_tail(struct drm_atomic_state
*state
)
13494 struct drm_device
*dev
= state
->dev
;
13495 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
13496 struct drm_i915_private
*dev_priv
= to_i915(dev
);
13497 struct drm_crtc_state
*old_crtc_state
, *new_crtc_state
;
13498 struct intel_crtc_state
*new_intel_crtc_state
, *old_intel_crtc_state
;
13499 struct drm_crtc
*crtc
;
13500 struct intel_crtc
*intel_crtc
;
13501 u64 put_domains
[I915_MAX_PIPES
] = {};
13502 intel_wakeref_t wakeref
= 0;
13505 intel_atomic_commit_fence_wait(intel_state
);
13507 drm_atomic_helper_wait_for_dependencies(state
);
13509 if (intel_state
->modeset
)
13510 wakeref
= intel_display_power_get(dev_priv
, POWER_DOMAIN_MODESET
);
13512 for_each_oldnew_crtc_in_state(state
, crtc
, old_crtc_state
, new_crtc_state
, i
) {
13513 old_intel_crtc_state
= to_intel_crtc_state(old_crtc_state
);
13514 new_intel_crtc_state
= to_intel_crtc_state(new_crtc_state
);
13515 intel_crtc
= to_intel_crtc(crtc
);
13517 if (needs_modeset(new_crtc_state
) ||
13518 to_intel_crtc_state(new_crtc_state
)->update_pipe
) {
13520 put_domains
[intel_crtc
->pipe
] =
13521 modeset_get_crtc_power_domains(crtc
,
13522 new_intel_crtc_state
);
13525 if (!needs_modeset(new_crtc_state
))
13528 intel_pre_plane_update(old_intel_crtc_state
, new_intel_crtc_state
);
13530 if (old_crtc_state
->active
) {
13531 intel_crtc_disable_planes(intel_state
, intel_crtc
);
13534 * We need to disable pipe CRC before disabling the pipe,
13535 * or we race against vblank off.
13537 intel_crtc_disable_pipe_crc(intel_crtc
);
13539 dev_priv
->display
.crtc_disable(old_intel_crtc_state
, state
);
13540 intel_crtc
->active
= false;
13541 intel_fbc_disable(intel_crtc
);
13542 intel_disable_shared_dpll(old_intel_crtc_state
);
13545 * Underruns don't always raise
13546 * interrupts, so check manually.
13548 intel_check_cpu_fifo_underruns(dev_priv
);
13549 intel_check_pch_fifo_underruns(dev_priv
);
13551 /* FIXME unify this for all platforms */
13552 if (!new_crtc_state
->active
&&
13553 !HAS_GMCH(dev_priv
) &&
13554 dev_priv
->display
.initial_watermarks
)
13555 dev_priv
->display
.initial_watermarks(intel_state
,
13556 new_intel_crtc_state
);
13560 /* FIXME: Eventually get rid of our intel_crtc->config pointer */
13561 for_each_new_crtc_in_state(state
, crtc
, new_crtc_state
, i
)
13562 to_intel_crtc(crtc
)->config
= to_intel_crtc_state(new_crtc_state
);
13564 if (intel_state
->modeset
) {
13565 drm_atomic_helper_update_legacy_modeset_state(state
->dev
, state
);
13567 intel_set_cdclk_pre_plane_update(dev_priv
,
13568 &intel_state
->cdclk
.actual
,
13569 &dev_priv
->cdclk
.actual
,
13570 intel_state
->cdclk
.pipe
);
13573 * SKL workaround: bspec recommends we disable the SAGV when we
13574 * have more then one pipe enabled
13576 if (!intel_can_enable_sagv(state
))
13577 intel_disable_sagv(dev_priv
);
13579 intel_modeset_verify_disabled(dev
, state
);
13582 /* Complete the events for pipes that have now been disabled */
13583 for_each_new_crtc_in_state(state
, crtc
, new_crtc_state
, i
) {
13584 bool modeset
= needs_modeset(new_crtc_state
);
13586 /* Complete events for now disable pipes here. */
13587 if (modeset
&& !new_crtc_state
->active
&& new_crtc_state
->event
) {
13588 spin_lock_irq(&dev
->event_lock
);
13589 drm_crtc_send_vblank_event(crtc
, new_crtc_state
->event
);
13590 spin_unlock_irq(&dev
->event_lock
);
13592 new_crtc_state
->event
= NULL
;
13596 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13597 dev_priv
->display
.update_crtcs(state
);
13599 if (intel_state
->modeset
)
13600 intel_set_cdclk_post_plane_update(dev_priv
,
13601 &intel_state
->cdclk
.actual
,
13602 &dev_priv
->cdclk
.actual
,
13603 intel_state
->cdclk
.pipe
);
13605 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
13606 * already, but still need the state for the delayed optimization. To
13608 * - wrap the optimization/post_plane_update stuff into a per-crtc work.
13609 * - schedule that vblank worker _before_ calling hw_done
13610 * - at the start of commit_tail, cancel it _synchrously
13611 * - switch over to the vblank wait helper in the core after that since
13612 * we don't need out special handling any more.
13614 drm_atomic_helper_wait_for_flip_done(dev
, state
);
13616 for_each_new_crtc_in_state(state
, crtc
, new_crtc_state
, i
) {
13617 new_intel_crtc_state
= to_intel_crtc_state(new_crtc_state
);
13619 if (new_crtc_state
->active
&&
13620 !needs_modeset(new_crtc_state
) &&
13621 (new_intel_crtc_state
->base
.color_mgmt_changed
||
13622 new_intel_crtc_state
->update_pipe
))
13623 intel_color_load_luts(new_intel_crtc_state
);
13627 * Now that the vblank has passed, we can go ahead and program the
13628 * optimal watermarks on platforms that need two-step watermark
13631 * TODO: Move this (and other cleanup) to an async worker eventually.
13633 for_each_new_crtc_in_state(state
, crtc
, new_crtc_state
, i
) {
13634 new_intel_crtc_state
= to_intel_crtc_state(new_crtc_state
);
13636 if (dev_priv
->display
.optimize_watermarks
)
13637 dev_priv
->display
.optimize_watermarks(intel_state
,
13638 new_intel_crtc_state
);
13641 for_each_oldnew_crtc_in_state(state
, crtc
, old_crtc_state
, new_crtc_state
, i
) {
13642 intel_post_plane_update(to_intel_crtc_state(old_crtc_state
));
13644 if (put_domains
[i
])
13645 modeset_put_power_domains(dev_priv
, put_domains
[i
]);
13647 intel_modeset_verify_crtc(crtc
, state
, old_crtc_state
, new_crtc_state
);
13650 if (intel_state
->modeset
)
13651 intel_verify_planes(intel_state
);
13653 if (intel_state
->modeset
&& intel_can_enable_sagv(state
))
13654 intel_enable_sagv(dev_priv
);
13656 drm_atomic_helper_commit_hw_done(state
);
13658 if (intel_state
->modeset
) {
13659 /* As one of the primary mmio accessors, KMS has a high
13660 * likelihood of triggering bugs in unclaimed access. After we
13661 * finish modesetting, see if an error has been flagged, and if
13662 * so enable debugging for the next modeset - and hope we catch
13665 intel_uncore_arm_unclaimed_mmio_detection(&dev_priv
->uncore
);
13666 intel_display_power_put(dev_priv
, POWER_DOMAIN_MODESET
, wakeref
);
13670 * Defer the cleanup of the old state to a separate worker to not
13671 * impede the current task (userspace for blocking modesets) that
13672 * are executed inline. For out-of-line asynchronous modesets/flips,
13673 * deferring to a new worker seems overkill, but we would place a
13674 * schedule point (cond_resched()) here anyway to keep latencies
13677 INIT_WORK(&state
->commit_work
, intel_atomic_cleanup_work
);
13678 queue_work(system_highpri_wq
, &state
->commit_work
);
13681 static void intel_atomic_commit_work(struct work_struct
*work
)
13683 struct drm_atomic_state
*state
=
13684 container_of(work
, struct drm_atomic_state
, commit_work
);
13686 intel_atomic_commit_tail(state
);
13689 static int __i915_sw_fence_call
13690 intel_atomic_commit_ready(struct i915_sw_fence
*fence
,
13691 enum i915_sw_fence_notify notify
)
13693 struct intel_atomic_state
*state
=
13694 container_of(fence
, struct intel_atomic_state
, commit_ready
);
13697 case FENCE_COMPLETE
:
13698 /* we do blocking waits in the worker, nothing to do here */
13702 struct intel_atomic_helper
*helper
=
13703 &to_i915(state
->base
.dev
)->atomic_helper
;
13705 if (llist_add(&state
->freed
, &helper
->free_list
))
13706 schedule_work(&helper
->free_work
);
13711 return NOTIFY_DONE
;
13714 static void intel_atomic_track_fbs(struct drm_atomic_state
*state
)
13716 struct drm_plane_state
*old_plane_state
, *new_plane_state
;
13717 struct drm_plane
*plane
;
13720 for_each_oldnew_plane_in_state(state
, plane
, old_plane_state
, new_plane_state
, i
)
13721 i915_gem_track_fb(intel_fb_obj(old_plane_state
->fb
),
13722 intel_fb_obj(new_plane_state
->fb
),
13723 to_intel_plane(plane
)->frontbuffer_bit
);
13727 * intel_atomic_commit - commit validated state object
13729 * @state: the top-level driver state object
13730 * @nonblock: nonblocking commit
13732 * This function commits a top-level state object that has been validated
13733 * with drm_atomic_helper_check().
13736 * Zero for success or -errno.
13738 static int intel_atomic_commit(struct drm_device
*dev
,
13739 struct drm_atomic_state
*state
,
13742 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
13743 struct drm_i915_private
*dev_priv
= to_i915(dev
);
13746 drm_atomic_state_get(state
);
13747 i915_sw_fence_init(&intel_state
->commit_ready
,
13748 intel_atomic_commit_ready
);
13751 * The intel_legacy_cursor_update() fast path takes care
13752 * of avoiding the vblank waits for simple cursor
13753 * movement and flips. For cursor on/off and size changes,
13754 * we want to perform the vblank waits so that watermark
13755 * updates happen during the correct frames. Gen9+ have
13756 * double buffered watermarks and so shouldn't need this.
13758 * Unset state->legacy_cursor_update before the call to
13759 * drm_atomic_helper_setup_commit() because otherwise
13760 * drm_atomic_helper_wait_for_flip_done() is a noop and
13761 * we get FIFO underruns because we didn't wait
13764 * FIXME doing watermarks and fb cleanup from a vblank worker
13765 * (assuming we had any) would solve these problems.
13767 if (INTEL_GEN(dev_priv
) < 9 && state
->legacy_cursor_update
) {
13768 struct intel_crtc_state
*new_crtc_state
;
13769 struct intel_crtc
*crtc
;
13772 for_each_new_intel_crtc_in_state(intel_state
, crtc
, new_crtc_state
, i
)
13773 if (new_crtc_state
->wm
.need_postvbl_update
||
13774 new_crtc_state
->update_wm_post
)
13775 state
->legacy_cursor_update
= false;
13778 ret
= intel_atomic_prepare_commit(dev
, state
);
13780 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret
);
13781 i915_sw_fence_commit(&intel_state
->commit_ready
);
13785 ret
= drm_atomic_helper_setup_commit(state
, nonblock
);
13787 ret
= drm_atomic_helper_swap_state(state
, true);
13790 i915_sw_fence_commit(&intel_state
->commit_ready
);
13792 drm_atomic_helper_cleanup_planes(dev
, state
);
13795 dev_priv
->wm
.distrust_bios_wm
= false;
13796 intel_shared_dpll_swap_state(state
);
13797 intel_atomic_track_fbs(state
);
13799 if (intel_state
->modeset
) {
13800 memcpy(dev_priv
->min_cdclk
, intel_state
->min_cdclk
,
13801 sizeof(intel_state
->min_cdclk
));
13802 memcpy(dev_priv
->min_voltage_level
,
13803 intel_state
->min_voltage_level
,
13804 sizeof(intel_state
->min_voltage_level
));
13805 dev_priv
->active_crtcs
= intel_state
->active_crtcs
;
13806 dev_priv
->cdclk
.force_min_cdclk
=
13807 intel_state
->cdclk
.force_min_cdclk
;
13809 intel_cdclk_swap_state(intel_state
);
13812 drm_atomic_state_get(state
);
13813 INIT_WORK(&state
->commit_work
, intel_atomic_commit_work
);
13815 i915_sw_fence_commit(&intel_state
->commit_ready
);
13816 if (nonblock
&& intel_state
->modeset
) {
13817 queue_work(dev_priv
->modeset_wq
, &state
->commit_work
);
13818 } else if (nonblock
) {
13819 queue_work(system_unbound_wq
, &state
->commit_work
);
13821 if (intel_state
->modeset
)
13822 flush_workqueue(dev_priv
->modeset_wq
);
13823 intel_atomic_commit_tail(state
);
13829 static const struct drm_crtc_funcs intel_crtc_funcs
= {
13830 .gamma_set
= drm_atomic_helper_legacy_gamma_set
,
13831 .set_config
= drm_atomic_helper_set_config
,
13832 .destroy
= intel_crtc_destroy
,
13833 .page_flip
= drm_atomic_helper_page_flip
,
13834 .atomic_duplicate_state
= intel_crtc_duplicate_state
,
13835 .atomic_destroy_state
= intel_crtc_destroy_state
,
13836 .set_crc_source
= intel_crtc_set_crc_source
,
13837 .verify_crc_source
= intel_crtc_verify_crc_source
,
13838 .get_crc_sources
= intel_crtc_get_crc_sources
,
13841 struct wait_rps_boost
{
13842 struct wait_queue_entry wait
;
13844 struct drm_crtc
*crtc
;
13845 struct i915_request
*request
;
13848 static int do_rps_boost(struct wait_queue_entry
*_wait
,
13849 unsigned mode
, int sync
, void *key
)
13851 struct wait_rps_boost
*wait
= container_of(_wait
, typeof(*wait
), wait
);
13852 struct i915_request
*rq
= wait
->request
;
13855 * If we missed the vblank, but the request is already running it
13856 * is reasonable to assume that it will complete before the next
13857 * vblank without our intervention, so leave RPS alone.
13859 if (!i915_request_started(rq
))
13860 gen6_rps_boost(rq
);
13861 i915_request_put(rq
);
13863 drm_crtc_vblank_put(wait
->crtc
);
13865 list_del(&wait
->wait
.entry
);
13870 static void add_rps_boost_after_vblank(struct drm_crtc
*crtc
,
13871 struct dma_fence
*fence
)
13873 struct wait_rps_boost
*wait
;
13875 if (!dma_fence_is_i915(fence
))
13878 if (INTEL_GEN(to_i915(crtc
->dev
)) < 6)
13881 if (drm_crtc_vblank_get(crtc
))
13884 wait
= kmalloc(sizeof(*wait
), GFP_KERNEL
);
13886 drm_crtc_vblank_put(crtc
);
13890 wait
->request
= to_request(dma_fence_get(fence
));
13893 wait
->wait
.func
= do_rps_boost
;
13894 wait
->wait
.flags
= 0;
13896 add_wait_queue(drm_crtc_vblank_waitqueue(crtc
), &wait
->wait
);
13899 static int intel_plane_pin_fb(struct intel_plane_state
*plane_state
)
13901 struct intel_plane
*plane
= to_intel_plane(plane_state
->base
.plane
);
13902 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
13903 struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
13904 struct i915_vma
*vma
;
13906 if (plane
->id
== PLANE_CURSOR
&&
13907 INTEL_INFO(dev_priv
)->display
.cursor_needs_physical
) {
13908 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
13909 const int align
= intel_cursor_alignment(dev_priv
);
13912 err
= i915_gem_object_attach_phys(obj
, align
);
13917 vma
= intel_pin_and_fence_fb_obj(fb
,
13918 &plane_state
->view
,
13919 intel_plane_uses_fence(plane_state
),
13920 &plane_state
->flags
);
13922 return PTR_ERR(vma
);
13924 plane_state
->vma
= vma
;
13929 static void intel_plane_unpin_fb(struct intel_plane_state
*old_plane_state
)
13931 struct i915_vma
*vma
;
13933 vma
= fetch_and_zero(&old_plane_state
->vma
);
13935 intel_unpin_fb_vma(vma
, old_plane_state
->flags
);
13938 static void fb_obj_bump_render_priority(struct drm_i915_gem_object
*obj
)
13940 struct i915_sched_attr attr
= {
13941 .priority
= I915_PRIORITY_DISPLAY
,
13944 i915_gem_object_wait_priority(obj
, 0, &attr
);
13948 * intel_prepare_plane_fb - Prepare fb for usage on plane
13949 * @plane: drm plane to prepare for
13950 * @new_state: the plane state being prepared
13952 * Prepares a framebuffer for usage on a display plane. Generally this
13953 * involves pinning the underlying object and updating the frontbuffer tracking
13954 * bits. Some older platforms need special physical address handling for
13957 * Must be called with struct_mutex held.
13959 * Returns 0 on success, negative error code on failure.
13962 intel_prepare_plane_fb(struct drm_plane
*plane
,
13963 struct drm_plane_state
*new_state
)
13965 struct intel_atomic_state
*intel_state
=
13966 to_intel_atomic_state(new_state
->state
);
13967 struct drm_i915_private
*dev_priv
= to_i915(plane
->dev
);
13968 struct drm_framebuffer
*fb
= new_state
->fb
;
13969 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
13970 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(plane
->state
->fb
);
13974 struct drm_crtc_state
*crtc_state
=
13975 drm_atomic_get_new_crtc_state(new_state
->state
,
13976 plane
->state
->crtc
);
13978 /* Big Hammer, we also need to ensure that any pending
13979 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13980 * current scanout is retired before unpinning the old
13981 * framebuffer. Note that we rely on userspace rendering
13982 * into the buffer attached to the pipe they are waiting
13983 * on. If not, userspace generates a GPU hang with IPEHR
13984 * point to the MI_WAIT_FOR_EVENT.
13986 * This should only fail upon a hung GPU, in which case we
13987 * can safely continue.
13989 if (needs_modeset(crtc_state
)) {
13990 ret
= i915_sw_fence_await_reservation(&intel_state
->commit_ready
,
13991 old_obj
->resv
, NULL
,
13999 if (new_state
->fence
) { /* explicit fencing */
14000 ret
= i915_sw_fence_await_dma_fence(&intel_state
->commit_ready
,
14002 I915_FENCE_TIMEOUT
,
14011 ret
= i915_gem_object_pin_pages(obj
);
14015 ret
= mutex_lock_interruptible(&dev_priv
->drm
.struct_mutex
);
14017 i915_gem_object_unpin_pages(obj
);
14021 ret
= intel_plane_pin_fb(to_intel_plane_state(new_state
));
14023 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
14024 i915_gem_object_unpin_pages(obj
);
14028 fb_obj_bump_render_priority(obj
);
14029 intel_fb_obj_flush(obj
, ORIGIN_DIRTYFB
);
14031 if (!new_state
->fence
) { /* implicit fencing */
14032 struct dma_fence
*fence
;
14034 ret
= i915_sw_fence_await_reservation(&intel_state
->commit_ready
,
14036 false, I915_FENCE_TIMEOUT
,
14041 fence
= reservation_object_get_excl_rcu(obj
->resv
);
14043 add_rps_boost_after_vblank(new_state
->crtc
, fence
);
14044 dma_fence_put(fence
);
14047 add_rps_boost_after_vblank(new_state
->crtc
, new_state
->fence
);
14051 * We declare pageflips to be interactive and so merit a small bias
14052 * towards upclocking to deliver the frame on time. By only changing
14053 * the RPS thresholds to sample more regularly and aim for higher
14054 * clocks we can hopefully deliver low power workloads (like kodi)
14055 * that are not quite steady state without resorting to forcing
14056 * maximum clocks following a vblank miss (see do_rps_boost()).
14058 if (!intel_state
->rps_interactive
) {
14059 intel_rps_mark_interactive(dev_priv
, true);
14060 intel_state
->rps_interactive
= true;
14067 * intel_cleanup_plane_fb - Cleans up an fb after plane use
14068 * @plane: drm plane to clean up for
14069 * @old_state: the state from the previous modeset
14071 * Cleans up a framebuffer that has just been removed from a plane.
14073 * Must be called with struct_mutex held.
14076 intel_cleanup_plane_fb(struct drm_plane
*plane
,
14077 struct drm_plane_state
*old_state
)
14079 struct intel_atomic_state
*intel_state
=
14080 to_intel_atomic_state(old_state
->state
);
14081 struct drm_i915_private
*dev_priv
= to_i915(plane
->dev
);
14083 if (intel_state
->rps_interactive
) {
14084 intel_rps_mark_interactive(dev_priv
, false);
14085 intel_state
->rps_interactive
= false;
14088 /* Should only be called after a successful intel_prepare_plane_fb()! */
14089 mutex_lock(&dev_priv
->drm
.struct_mutex
);
14090 intel_plane_unpin_fb(to_intel_plane_state(old_state
));
14091 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
14095 skl_max_scale(const struct intel_crtc_state
*crtc_state
,
14098 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
14099 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
14100 int max_scale
, mult
;
14101 int crtc_clock
, max_dotclk
, tmpclk1
, tmpclk2
;
14103 if (!crtc_state
->base
.enable
)
14104 return DRM_PLANE_HELPER_NO_SCALING
;
14106 crtc_clock
= crtc_state
->base
.adjusted_mode
.crtc_clock
;
14107 max_dotclk
= to_intel_atomic_state(crtc_state
->base
.state
)->cdclk
.logical
.cdclk
;
14109 if (IS_GEMINILAKE(dev_priv
) || INTEL_GEN(dev_priv
) >= 10)
14112 if (WARN_ON_ONCE(!crtc_clock
|| max_dotclk
< crtc_clock
))
14113 return DRM_PLANE_HELPER_NO_SCALING
;
14116 * skl max scale is lower of:
14117 * close to 3 but not 3, -1 is for that purpose
14121 mult
= is_planar_yuv_format(pixel_format
) ? 2 : 3;
14122 tmpclk1
= (1 << 16) * mult
- 1;
14123 tmpclk2
= (1 << 8) * ((max_dotclk
<< 8) / crtc_clock
);
14124 max_scale
= min(tmpclk1
, tmpclk2
);
14129 static void intel_begin_crtc_commit(struct intel_atomic_state
*state
,
14130 struct intel_crtc
*crtc
)
14132 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
14133 struct intel_crtc_state
*old_crtc_state
=
14134 intel_atomic_get_old_crtc_state(state
, crtc
);
14135 struct intel_crtc_state
*new_crtc_state
=
14136 intel_atomic_get_new_crtc_state(state
, crtc
);
14137 bool modeset
= needs_modeset(&new_crtc_state
->base
);
14139 /* Perform vblank evasion around commit operation */
14140 intel_pipe_update_start(new_crtc_state
);
14145 if (new_crtc_state
->base
.color_mgmt_changed
||
14146 new_crtc_state
->update_pipe
)
14147 intel_color_commit(new_crtc_state
);
14149 if (new_crtc_state
->update_pipe
)
14150 intel_update_pipe_config(old_crtc_state
, new_crtc_state
);
14151 else if (INTEL_GEN(dev_priv
) >= 9)
14152 skl_detach_scalers(new_crtc_state
);
14155 if (dev_priv
->display
.atomic_update_watermarks
)
14156 dev_priv
->display
.atomic_update_watermarks(state
,
14160 void intel_crtc_arm_fifo_underrun(struct intel_crtc
*crtc
,
14161 struct intel_crtc_state
*crtc_state
)
14163 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
14165 if (!IS_GEN(dev_priv
, 2))
14166 intel_set_cpu_fifo_underrun_reporting(dev_priv
, crtc
->pipe
, true);
14168 if (crtc_state
->has_pch_encoder
) {
14169 enum pipe pch_transcoder
=
14170 intel_crtc_pch_transcoder(crtc
);
14172 intel_set_pch_fifo_underrun_reporting(dev_priv
, pch_transcoder
, true);
14176 static void intel_finish_crtc_commit(struct intel_atomic_state
*state
,
14177 struct intel_crtc
*crtc
)
14179 struct intel_crtc_state
*old_crtc_state
=
14180 intel_atomic_get_old_crtc_state(state
, crtc
);
14181 struct intel_crtc_state
*new_crtc_state
=
14182 intel_atomic_get_new_crtc_state(state
, crtc
);
14184 intel_pipe_update_end(new_crtc_state
);
14186 if (new_crtc_state
->update_pipe
&&
14187 !needs_modeset(&new_crtc_state
->base
) &&
14188 old_crtc_state
->base
.mode
.private_flags
& I915_MODE_FLAG_INHERITED
)
14189 intel_crtc_arm_fifo_underrun(crtc
, new_crtc_state
);
14193 * intel_plane_destroy - destroy a plane
14194 * @plane: plane to destroy
14196 * Common destruction function for all types of planes (primary, cursor,
14199 void intel_plane_destroy(struct drm_plane
*plane
)
14201 drm_plane_cleanup(plane
);
14202 kfree(to_intel_plane(plane
));
14205 static bool i8xx_plane_format_mod_supported(struct drm_plane
*_plane
,
14206 u32 format
, u64 modifier
)
14208 switch (modifier
) {
14209 case DRM_FORMAT_MOD_LINEAR
:
14210 case I915_FORMAT_MOD_X_TILED
:
14217 case DRM_FORMAT_C8
:
14218 case DRM_FORMAT_RGB565
:
14219 case DRM_FORMAT_XRGB1555
:
14220 case DRM_FORMAT_XRGB8888
:
14221 return modifier
== DRM_FORMAT_MOD_LINEAR
||
14222 modifier
== I915_FORMAT_MOD_X_TILED
;
14228 static bool i965_plane_format_mod_supported(struct drm_plane
*_plane
,
14229 u32 format
, u64 modifier
)
14231 switch (modifier
) {
14232 case DRM_FORMAT_MOD_LINEAR
:
14233 case I915_FORMAT_MOD_X_TILED
:
14240 case DRM_FORMAT_C8
:
14241 case DRM_FORMAT_RGB565
:
14242 case DRM_FORMAT_XRGB8888
:
14243 case DRM_FORMAT_XBGR8888
:
14244 case DRM_FORMAT_XRGB2101010
:
14245 case DRM_FORMAT_XBGR2101010
:
14246 return modifier
== DRM_FORMAT_MOD_LINEAR
||
14247 modifier
== I915_FORMAT_MOD_X_TILED
;
14253 static bool intel_cursor_format_mod_supported(struct drm_plane
*_plane
,
14254 u32 format
, u64 modifier
)
14256 return modifier
== DRM_FORMAT_MOD_LINEAR
&&
14257 format
== DRM_FORMAT_ARGB8888
;
14260 static const struct drm_plane_funcs i965_plane_funcs
= {
14261 .update_plane
= drm_atomic_helper_update_plane
,
14262 .disable_plane
= drm_atomic_helper_disable_plane
,
14263 .destroy
= intel_plane_destroy
,
14264 .atomic_get_property
= intel_plane_atomic_get_property
,
14265 .atomic_set_property
= intel_plane_atomic_set_property
,
14266 .atomic_duplicate_state
= intel_plane_duplicate_state
,
14267 .atomic_destroy_state
= intel_plane_destroy_state
,
14268 .format_mod_supported
= i965_plane_format_mod_supported
,
14271 static const struct drm_plane_funcs i8xx_plane_funcs
= {
14272 .update_plane
= drm_atomic_helper_update_plane
,
14273 .disable_plane
= drm_atomic_helper_disable_plane
,
14274 .destroy
= intel_plane_destroy
,
14275 .atomic_get_property
= intel_plane_atomic_get_property
,
14276 .atomic_set_property
= intel_plane_atomic_set_property
,
14277 .atomic_duplicate_state
= intel_plane_duplicate_state
,
14278 .atomic_destroy_state
= intel_plane_destroy_state
,
14279 .format_mod_supported
= i8xx_plane_format_mod_supported
,
14283 intel_legacy_cursor_update(struct drm_plane
*plane
,
14284 struct drm_crtc
*crtc
,
14285 struct drm_framebuffer
*fb
,
14286 int crtc_x
, int crtc_y
,
14287 unsigned int crtc_w
, unsigned int crtc_h
,
14288 u32 src_x
, u32 src_y
,
14289 u32 src_w
, u32 src_h
,
14290 struct drm_modeset_acquire_ctx
*ctx
)
14292 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
14294 struct drm_plane_state
*old_plane_state
, *new_plane_state
;
14295 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
14296 struct drm_framebuffer
*old_fb
;
14297 struct intel_crtc_state
*crtc_state
=
14298 to_intel_crtc_state(crtc
->state
);
14299 struct intel_crtc_state
*new_crtc_state
;
14302 * When crtc is inactive or there is a modeset pending,
14303 * wait for it to complete in the slowpath
14305 if (!crtc_state
->base
.active
|| needs_modeset(&crtc_state
->base
) ||
14306 crtc_state
->update_pipe
)
14309 old_plane_state
= plane
->state
;
14311 * Don't do an async update if there is an outstanding commit modifying
14312 * the plane. This prevents our async update's changes from getting
14313 * overridden by a previous synchronous update's state.
14315 if (old_plane_state
->commit
&&
14316 !try_wait_for_completion(&old_plane_state
->commit
->hw_done
))
14320 * If any parameters change that may affect watermarks,
14321 * take the slowpath. Only changing fb or position should be
14324 if (old_plane_state
->crtc
!= crtc
||
14325 old_plane_state
->src_w
!= src_w
||
14326 old_plane_state
->src_h
!= src_h
||
14327 old_plane_state
->crtc_w
!= crtc_w
||
14328 old_plane_state
->crtc_h
!= crtc_h
||
14329 !old_plane_state
->fb
!= !fb
)
14332 new_plane_state
= intel_plane_duplicate_state(plane
);
14333 if (!new_plane_state
)
14336 new_crtc_state
= to_intel_crtc_state(intel_crtc_duplicate_state(crtc
));
14337 if (!new_crtc_state
) {
14342 drm_atomic_set_fb_for_plane(new_plane_state
, fb
);
14344 new_plane_state
->src_x
= src_x
;
14345 new_plane_state
->src_y
= src_y
;
14346 new_plane_state
->src_w
= src_w
;
14347 new_plane_state
->src_h
= src_h
;
14348 new_plane_state
->crtc_x
= crtc_x
;
14349 new_plane_state
->crtc_y
= crtc_y
;
14350 new_plane_state
->crtc_w
= crtc_w
;
14351 new_plane_state
->crtc_h
= crtc_h
;
14353 ret
= intel_plane_atomic_check_with_state(crtc_state
, new_crtc_state
,
14354 to_intel_plane_state(old_plane_state
),
14355 to_intel_plane_state(new_plane_state
));
14359 ret
= mutex_lock_interruptible(&dev_priv
->drm
.struct_mutex
);
14363 ret
= intel_plane_pin_fb(to_intel_plane_state(new_plane_state
));
14367 intel_fb_obj_flush(intel_fb_obj(fb
), ORIGIN_FLIP
);
14369 old_fb
= old_plane_state
->fb
;
14370 i915_gem_track_fb(intel_fb_obj(old_fb
), intel_fb_obj(fb
),
14371 intel_plane
->frontbuffer_bit
);
14373 /* Swap plane state */
14374 plane
->state
= new_plane_state
;
14377 * We cannot swap crtc_state as it may be in use by an atomic commit or
14378 * page flip that's running simultaneously. If we swap crtc_state and
14379 * destroy the old state, we will cause a use-after-free there.
14381 * Only update active_planes, which is needed for our internal
14382 * bookkeeping. Either value will do the right thing when updating
14383 * planes atomically. If the cursor was part of the atomic update then
14384 * we would have taken the slowpath.
14386 crtc_state
->active_planes
= new_crtc_state
->active_planes
;
14388 if (plane
->state
->visible
)
14389 intel_update_plane(intel_plane
, crtc_state
,
14390 to_intel_plane_state(plane
->state
));
14392 intel_disable_plane(intel_plane
, crtc_state
);
14394 intel_plane_unpin_fb(to_intel_plane_state(old_plane_state
));
14397 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
14399 if (new_crtc_state
)
14400 intel_crtc_destroy_state(crtc
, &new_crtc_state
->base
);
14402 intel_plane_destroy_state(plane
, new_plane_state
);
14404 intel_plane_destroy_state(plane
, old_plane_state
);
14408 return drm_atomic_helper_update_plane(plane
, crtc
, fb
,
14409 crtc_x
, crtc_y
, crtc_w
, crtc_h
,
14410 src_x
, src_y
, src_w
, src_h
, ctx
);
14413 static const struct drm_plane_funcs intel_cursor_plane_funcs
= {
14414 .update_plane
= intel_legacy_cursor_update
,
14415 .disable_plane
= drm_atomic_helper_disable_plane
,
14416 .destroy
= intel_plane_destroy
,
14417 .atomic_get_property
= intel_plane_atomic_get_property
,
14418 .atomic_set_property
= intel_plane_atomic_set_property
,
14419 .atomic_duplicate_state
= intel_plane_duplicate_state
,
14420 .atomic_destroy_state
= intel_plane_destroy_state
,
14421 .format_mod_supported
= intel_cursor_format_mod_supported
,
14424 static bool i9xx_plane_has_fbc(struct drm_i915_private
*dev_priv
,
14425 enum i9xx_plane_id i9xx_plane
)
14427 if (!HAS_FBC(dev_priv
))
14430 if (IS_BROADWELL(dev_priv
) || IS_HASWELL(dev_priv
))
14431 return i9xx_plane
== PLANE_A
; /* tied to pipe A */
14432 else if (IS_IVYBRIDGE(dev_priv
))
14433 return i9xx_plane
== PLANE_A
|| i9xx_plane
== PLANE_B
||
14434 i9xx_plane
== PLANE_C
;
14435 else if (INTEL_GEN(dev_priv
) >= 4)
14436 return i9xx_plane
== PLANE_A
|| i9xx_plane
== PLANE_B
;
14438 return i9xx_plane
== PLANE_A
;
14441 static struct intel_plane
*
14442 intel_primary_plane_create(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
14444 struct intel_plane
*plane
;
14445 const struct drm_plane_funcs
*plane_funcs
;
14446 unsigned int supported_rotations
;
14447 unsigned int possible_crtcs
;
14448 const u64
*modifiers
;
14449 const u32
*formats
;
14453 if (INTEL_GEN(dev_priv
) >= 9)
14454 return skl_universal_plane_create(dev_priv
, pipe
,
14457 plane
= intel_plane_alloc();
14461 plane
->pipe
= pipe
;
14463 * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
14464 * port is hooked to pipe B. Hence we want plane A feeding pipe B.
14466 if (HAS_FBC(dev_priv
) && INTEL_GEN(dev_priv
) < 4)
14467 plane
->i9xx_plane
= (enum i9xx_plane_id
) !pipe
;
14469 plane
->i9xx_plane
= (enum i9xx_plane_id
) pipe
;
14470 plane
->id
= PLANE_PRIMARY
;
14471 plane
->frontbuffer_bit
= INTEL_FRONTBUFFER(pipe
, plane
->id
);
14473 plane
->has_fbc
= i9xx_plane_has_fbc(dev_priv
, plane
->i9xx_plane
);
14474 if (plane
->has_fbc
) {
14475 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
14477 fbc
->possible_framebuffer_bits
|= plane
->frontbuffer_bit
;
14480 if (INTEL_GEN(dev_priv
) >= 4) {
14481 formats
= i965_primary_formats
;
14482 num_formats
= ARRAY_SIZE(i965_primary_formats
);
14483 modifiers
= i9xx_format_modifiers
;
14485 plane
->max_stride
= i9xx_plane_max_stride
;
14486 plane
->update_plane
= i9xx_update_plane
;
14487 plane
->disable_plane
= i9xx_disable_plane
;
14488 plane
->get_hw_state
= i9xx_plane_get_hw_state
;
14489 plane
->check_plane
= i9xx_plane_check
;
14491 plane_funcs
= &i965_plane_funcs
;
14493 formats
= i8xx_primary_formats
;
14494 num_formats
= ARRAY_SIZE(i8xx_primary_formats
);
14495 modifiers
= i9xx_format_modifiers
;
14497 plane
->max_stride
= i9xx_plane_max_stride
;
14498 plane
->update_plane
= i9xx_update_plane
;
14499 plane
->disable_plane
= i9xx_disable_plane
;
14500 plane
->get_hw_state
= i9xx_plane_get_hw_state
;
14501 plane
->check_plane
= i9xx_plane_check
;
14503 plane_funcs
= &i8xx_plane_funcs
;
14506 possible_crtcs
= BIT(pipe
);
14508 if (INTEL_GEN(dev_priv
) >= 5 || IS_G4X(dev_priv
))
14509 ret
= drm_universal_plane_init(&dev_priv
->drm
, &plane
->base
,
14510 possible_crtcs
, plane_funcs
,
14511 formats
, num_formats
, modifiers
,
14512 DRM_PLANE_TYPE_PRIMARY
,
14513 "primary %c", pipe_name(pipe
));
14515 ret
= drm_universal_plane_init(&dev_priv
->drm
, &plane
->base
,
14516 possible_crtcs
, plane_funcs
,
14517 formats
, num_formats
, modifiers
,
14518 DRM_PLANE_TYPE_PRIMARY
,
14520 plane_name(plane
->i9xx_plane
));
14524 if (IS_CHERRYVIEW(dev_priv
) && pipe
== PIPE_B
) {
14525 supported_rotations
=
14526 DRM_MODE_ROTATE_0
| DRM_MODE_ROTATE_180
|
14527 DRM_MODE_REFLECT_X
;
14528 } else if (INTEL_GEN(dev_priv
) >= 4) {
14529 supported_rotations
=
14530 DRM_MODE_ROTATE_0
| DRM_MODE_ROTATE_180
;
14532 supported_rotations
= DRM_MODE_ROTATE_0
;
14535 if (INTEL_GEN(dev_priv
) >= 4)
14536 drm_plane_create_rotation_property(&plane
->base
,
14538 supported_rotations
);
14540 drm_plane_helper_add(&plane
->base
, &intel_plane_helper_funcs
);
14545 intel_plane_free(plane
);
14547 return ERR_PTR(ret
);
14550 static struct intel_plane
*
14551 intel_cursor_plane_create(struct drm_i915_private
*dev_priv
,
14554 unsigned int possible_crtcs
;
14555 struct intel_plane
*cursor
;
14558 cursor
= intel_plane_alloc();
14559 if (IS_ERR(cursor
))
14562 cursor
->pipe
= pipe
;
14563 cursor
->i9xx_plane
= (enum i9xx_plane_id
) pipe
;
14564 cursor
->id
= PLANE_CURSOR
;
14565 cursor
->frontbuffer_bit
= INTEL_FRONTBUFFER(pipe
, cursor
->id
);
14567 if (IS_I845G(dev_priv
) || IS_I865G(dev_priv
)) {
14568 cursor
->max_stride
= i845_cursor_max_stride
;
14569 cursor
->update_plane
= i845_update_cursor
;
14570 cursor
->disable_plane
= i845_disable_cursor
;
14571 cursor
->get_hw_state
= i845_cursor_get_hw_state
;
14572 cursor
->check_plane
= i845_check_cursor
;
14574 cursor
->max_stride
= i9xx_cursor_max_stride
;
14575 cursor
->update_plane
= i9xx_update_cursor
;
14576 cursor
->disable_plane
= i9xx_disable_cursor
;
14577 cursor
->get_hw_state
= i9xx_cursor_get_hw_state
;
14578 cursor
->check_plane
= i9xx_check_cursor
;
14581 cursor
->cursor
.base
= ~0;
14582 cursor
->cursor
.cntl
= ~0;
14584 if (IS_I845G(dev_priv
) || IS_I865G(dev_priv
) || HAS_CUR_FBC(dev_priv
))
14585 cursor
->cursor
.size
= ~0;
14587 possible_crtcs
= BIT(pipe
);
14589 ret
= drm_universal_plane_init(&dev_priv
->drm
, &cursor
->base
,
14590 possible_crtcs
, &intel_cursor_plane_funcs
,
14591 intel_cursor_formats
,
14592 ARRAY_SIZE(intel_cursor_formats
),
14593 cursor_format_modifiers
,
14594 DRM_PLANE_TYPE_CURSOR
,
14595 "cursor %c", pipe_name(pipe
));
14599 if (INTEL_GEN(dev_priv
) >= 4)
14600 drm_plane_create_rotation_property(&cursor
->base
,
14602 DRM_MODE_ROTATE_0
|
14603 DRM_MODE_ROTATE_180
);
14605 drm_plane_helper_add(&cursor
->base
, &intel_plane_helper_funcs
);
14610 intel_plane_free(cursor
);
14612 return ERR_PTR(ret
);
14615 static void intel_crtc_init_scalers(struct intel_crtc
*crtc
,
14616 struct intel_crtc_state
*crtc_state
)
14618 struct intel_crtc_scaler_state
*scaler_state
=
14619 &crtc_state
->scaler_state
;
14620 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
14623 crtc
->num_scalers
= RUNTIME_INFO(dev_priv
)->num_scalers
[crtc
->pipe
];
14624 if (!crtc
->num_scalers
)
14627 for (i
= 0; i
< crtc
->num_scalers
; i
++) {
14628 struct intel_scaler
*scaler
= &scaler_state
->scalers
[i
];
14630 scaler
->in_use
= 0;
14634 scaler_state
->scaler_id
= -1;
14637 static int intel_crtc_init(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
14639 struct intel_crtc
*intel_crtc
;
14640 struct intel_crtc_state
*crtc_state
= NULL
;
14641 struct intel_plane
*primary
= NULL
;
14642 struct intel_plane
*cursor
= NULL
;
14645 intel_crtc
= kzalloc(sizeof(*intel_crtc
), GFP_KERNEL
);
14649 crtc_state
= kzalloc(sizeof(*crtc_state
), GFP_KERNEL
);
14654 intel_crtc
->config
= crtc_state
;
14655 intel_crtc
->base
.state
= &crtc_state
->base
;
14656 crtc_state
->base
.crtc
= &intel_crtc
->base
;
14658 primary
= intel_primary_plane_create(dev_priv
, pipe
);
14659 if (IS_ERR(primary
)) {
14660 ret
= PTR_ERR(primary
);
14663 intel_crtc
->plane_ids_mask
|= BIT(primary
->id
);
14665 for_each_sprite(dev_priv
, pipe
, sprite
) {
14666 struct intel_plane
*plane
;
14668 plane
= intel_sprite_plane_create(dev_priv
, pipe
, sprite
);
14669 if (IS_ERR(plane
)) {
14670 ret
= PTR_ERR(plane
);
14673 intel_crtc
->plane_ids_mask
|= BIT(plane
->id
);
14676 cursor
= intel_cursor_plane_create(dev_priv
, pipe
);
14677 if (IS_ERR(cursor
)) {
14678 ret
= PTR_ERR(cursor
);
14681 intel_crtc
->plane_ids_mask
|= BIT(cursor
->id
);
14683 ret
= drm_crtc_init_with_planes(&dev_priv
->drm
, &intel_crtc
->base
,
14684 &primary
->base
, &cursor
->base
,
14686 "pipe %c", pipe_name(pipe
));
14690 intel_crtc
->pipe
= pipe
;
14692 /* initialize shared scalers */
14693 intel_crtc_init_scalers(intel_crtc
, crtc_state
);
14695 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->pipe_to_crtc_mapping
) ||
14696 dev_priv
->pipe_to_crtc_mapping
[pipe
] != NULL
);
14697 dev_priv
->pipe_to_crtc_mapping
[pipe
] = intel_crtc
;
14699 if (INTEL_GEN(dev_priv
) < 9) {
14700 enum i9xx_plane_id i9xx_plane
= primary
->i9xx_plane
;
14702 BUG_ON(i9xx_plane
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
14703 dev_priv
->plane_to_crtc_mapping
[i9xx_plane
] != NULL
);
14704 dev_priv
->plane_to_crtc_mapping
[i9xx_plane
] = intel_crtc
;
14707 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
14709 intel_color_init(intel_crtc
);
14711 WARN_ON(drm_crtc_index(&intel_crtc
->base
) != intel_crtc
->pipe
);
14717 * drm_mode_config_cleanup() will free up any
14718 * crtcs/planes already initialized.
14726 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device
*dev
, void *data
,
14727 struct drm_file
*file
)
14729 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
14730 struct drm_crtc
*drmmode_crtc
;
14731 struct intel_crtc
*crtc
;
14733 drmmode_crtc
= drm_crtc_find(dev
, file
, pipe_from_crtc_id
->crtc_id
);
14737 crtc
= to_intel_crtc(drmmode_crtc
);
14738 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
14743 static int intel_encoder_clones(struct intel_encoder
*encoder
)
14745 struct drm_device
*dev
= encoder
->base
.dev
;
14746 struct intel_encoder
*source_encoder
;
14747 int index_mask
= 0;
14750 for_each_intel_encoder(dev
, source_encoder
) {
14751 if (encoders_cloneable(encoder
, source_encoder
))
14752 index_mask
|= (1 << entry
);
14760 static bool ilk_has_edp_a(struct drm_i915_private
*dev_priv
)
14762 if (!IS_MOBILE(dev_priv
))
14765 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
14768 if (IS_GEN(dev_priv
, 5) && (I915_READ(FUSE_STRAP
) & ILK_eDP_A_DISABLE
))
14774 static bool intel_ddi_crt_present(struct drm_i915_private
*dev_priv
)
14776 if (INTEL_GEN(dev_priv
) >= 9)
14779 if (IS_HSW_ULT(dev_priv
) || IS_BDW_ULT(dev_priv
))
14782 if (HAS_PCH_LPT_H(dev_priv
) &&
14783 I915_READ(SFUSE_STRAP
) & SFUSE_STRAP_CRT_DISABLED
)
14786 /* DDI E can't be used if DDI A requires 4 lanes */
14787 if (I915_READ(DDI_BUF_CTL(PORT_A
)) & DDI_A_4_LANES
)
14790 if (!dev_priv
->vbt
.int_crt_support
)
14796 void intel_pps_unlock_regs_wa(struct drm_i915_private
*dev_priv
)
14801 if (HAS_DDI(dev_priv
))
14804 * This w/a is needed at least on CPT/PPT, but to be sure apply it
14805 * everywhere where registers can be write protected.
14807 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
14812 for (pps_idx
= 0; pps_idx
< pps_num
; pps_idx
++) {
14813 u32 val
= I915_READ(PP_CONTROL(pps_idx
));
14815 val
= (val
& ~PANEL_UNLOCK_MASK
) | PANEL_UNLOCK_REGS
;
14816 I915_WRITE(PP_CONTROL(pps_idx
), val
);
14820 static void intel_pps_init(struct drm_i915_private
*dev_priv
)
14822 if (HAS_PCH_SPLIT(dev_priv
) || IS_GEN9_LP(dev_priv
))
14823 dev_priv
->pps_mmio_base
= PCH_PPS_BASE
;
14824 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
14825 dev_priv
->pps_mmio_base
= VLV_PPS_BASE
;
14827 dev_priv
->pps_mmio_base
= PPS_BASE
;
14829 intel_pps_unlock_regs_wa(dev_priv
);
14832 static void intel_setup_outputs(struct drm_i915_private
*dev_priv
)
14834 struct intel_encoder
*encoder
;
14835 bool dpd_is_edp
= false;
14837 intel_pps_init(dev_priv
);
14839 if (!HAS_DISPLAY(dev_priv
))
14842 if (IS_ELKHARTLAKE(dev_priv
)) {
14843 intel_ddi_init(dev_priv
, PORT_A
);
14844 intel_ddi_init(dev_priv
, PORT_B
);
14845 intel_ddi_init(dev_priv
, PORT_C
);
14846 icl_dsi_init(dev_priv
);
14847 } else if (INTEL_GEN(dev_priv
) >= 11) {
14848 intel_ddi_init(dev_priv
, PORT_A
);
14849 intel_ddi_init(dev_priv
, PORT_B
);
14850 intel_ddi_init(dev_priv
, PORT_C
);
14851 intel_ddi_init(dev_priv
, PORT_D
);
14852 intel_ddi_init(dev_priv
, PORT_E
);
14854 * On some ICL SKUs port F is not present. No strap bits for
14855 * this, so rely on VBT.
14856 * Work around broken VBTs on SKUs known to have no port F.
14858 if (IS_ICL_WITH_PORT_F(dev_priv
) &&
14859 intel_bios_is_port_present(dev_priv
, PORT_F
))
14860 intel_ddi_init(dev_priv
, PORT_F
);
14862 icl_dsi_init(dev_priv
);
14863 } else if (IS_GEN9_LP(dev_priv
)) {
14865 * FIXME: Broxton doesn't support port detection via the
14866 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14867 * detect the ports.
14869 intel_ddi_init(dev_priv
, PORT_A
);
14870 intel_ddi_init(dev_priv
, PORT_B
);
14871 intel_ddi_init(dev_priv
, PORT_C
);
14873 vlv_dsi_init(dev_priv
);
14874 } else if (HAS_DDI(dev_priv
)) {
14877 if (intel_ddi_crt_present(dev_priv
))
14878 intel_crt_init(dev_priv
);
14881 * Haswell uses DDI functions to detect digital outputs.
14882 * On SKL pre-D0 the strap isn't connected, so we assume
14885 found
= I915_READ(DDI_BUF_CTL(PORT_A
)) & DDI_INIT_DISPLAY_DETECTED
;
14886 /* WaIgnoreDDIAStrap: skl */
14887 if (found
|| IS_GEN9_BC(dev_priv
))
14888 intel_ddi_init(dev_priv
, PORT_A
);
14890 /* DDI B, C, D, and F detection is indicated by the SFUSE_STRAP
14892 found
= I915_READ(SFUSE_STRAP
);
14894 if (found
& SFUSE_STRAP_DDIB_DETECTED
)
14895 intel_ddi_init(dev_priv
, PORT_B
);
14896 if (found
& SFUSE_STRAP_DDIC_DETECTED
)
14897 intel_ddi_init(dev_priv
, PORT_C
);
14898 if (found
& SFUSE_STRAP_DDID_DETECTED
)
14899 intel_ddi_init(dev_priv
, PORT_D
);
14900 if (found
& SFUSE_STRAP_DDIF_DETECTED
)
14901 intel_ddi_init(dev_priv
, PORT_F
);
14903 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14905 if (IS_GEN9_BC(dev_priv
) &&
14906 intel_bios_is_port_present(dev_priv
, PORT_E
))
14907 intel_ddi_init(dev_priv
, PORT_E
);
14909 } else if (HAS_PCH_SPLIT(dev_priv
)) {
14913 * intel_edp_init_connector() depends on this completing first,
14914 * to prevent the registration of both eDP and LVDS and the
14915 * incorrect sharing of the PPS.
14917 intel_lvds_init(dev_priv
);
14918 intel_crt_init(dev_priv
);
14920 dpd_is_edp
= intel_dp_is_port_edp(dev_priv
, PORT_D
);
14922 if (ilk_has_edp_a(dev_priv
))
14923 intel_dp_init(dev_priv
, DP_A
, PORT_A
);
14925 if (I915_READ(PCH_HDMIB
) & SDVO_DETECTED
) {
14926 /* PCH SDVOB multiplex with HDMIB */
14927 found
= intel_sdvo_init(dev_priv
, PCH_SDVOB
, PORT_B
);
14929 intel_hdmi_init(dev_priv
, PCH_HDMIB
, PORT_B
);
14930 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
14931 intel_dp_init(dev_priv
, PCH_DP_B
, PORT_B
);
14934 if (I915_READ(PCH_HDMIC
) & SDVO_DETECTED
)
14935 intel_hdmi_init(dev_priv
, PCH_HDMIC
, PORT_C
);
14937 if (!dpd_is_edp
&& I915_READ(PCH_HDMID
) & SDVO_DETECTED
)
14938 intel_hdmi_init(dev_priv
, PCH_HDMID
, PORT_D
);
14940 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
14941 intel_dp_init(dev_priv
, PCH_DP_C
, PORT_C
);
14943 if (I915_READ(PCH_DP_D
) & DP_DETECTED
)
14944 intel_dp_init(dev_priv
, PCH_DP_D
, PORT_D
);
14945 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
14946 bool has_edp
, has_port
;
14948 if (IS_VALLEYVIEW(dev_priv
) && dev_priv
->vbt
.int_crt_support
)
14949 intel_crt_init(dev_priv
);
14952 * The DP_DETECTED bit is the latched state of the DDC
14953 * SDA pin at boot. However since eDP doesn't require DDC
14954 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14955 * eDP ports may have been muxed to an alternate function.
14956 * Thus we can't rely on the DP_DETECTED bit alone to detect
14957 * eDP ports. Consult the VBT as well as DP_DETECTED to
14958 * detect eDP ports.
14960 * Sadly the straps seem to be missing sometimes even for HDMI
14961 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
14962 * and VBT for the presence of the port. Additionally we can't
14963 * trust the port type the VBT declares as we've seen at least
14964 * HDMI ports that the VBT claim are DP or eDP.
14966 has_edp
= intel_dp_is_port_edp(dev_priv
, PORT_B
);
14967 has_port
= intel_bios_is_port_present(dev_priv
, PORT_B
);
14968 if (I915_READ(VLV_DP_B
) & DP_DETECTED
|| has_port
)
14969 has_edp
&= intel_dp_init(dev_priv
, VLV_DP_B
, PORT_B
);
14970 if ((I915_READ(VLV_HDMIB
) & SDVO_DETECTED
|| has_port
) && !has_edp
)
14971 intel_hdmi_init(dev_priv
, VLV_HDMIB
, PORT_B
);
14973 has_edp
= intel_dp_is_port_edp(dev_priv
, PORT_C
);
14974 has_port
= intel_bios_is_port_present(dev_priv
, PORT_C
);
14975 if (I915_READ(VLV_DP_C
) & DP_DETECTED
|| has_port
)
14976 has_edp
&= intel_dp_init(dev_priv
, VLV_DP_C
, PORT_C
);
14977 if ((I915_READ(VLV_HDMIC
) & SDVO_DETECTED
|| has_port
) && !has_edp
)
14978 intel_hdmi_init(dev_priv
, VLV_HDMIC
, PORT_C
);
14980 if (IS_CHERRYVIEW(dev_priv
)) {
14982 * eDP not supported on port D,
14983 * so no need to worry about it
14985 has_port
= intel_bios_is_port_present(dev_priv
, PORT_D
);
14986 if (I915_READ(CHV_DP_D
) & DP_DETECTED
|| has_port
)
14987 intel_dp_init(dev_priv
, CHV_DP_D
, PORT_D
);
14988 if (I915_READ(CHV_HDMID
) & SDVO_DETECTED
|| has_port
)
14989 intel_hdmi_init(dev_priv
, CHV_HDMID
, PORT_D
);
14992 vlv_dsi_init(dev_priv
);
14993 } else if (IS_PINEVIEW(dev_priv
)) {
14994 intel_lvds_init(dev_priv
);
14995 intel_crt_init(dev_priv
);
14996 } else if (IS_GEN_RANGE(dev_priv
, 3, 4)) {
14997 bool found
= false;
14999 if (IS_MOBILE(dev_priv
))
15000 intel_lvds_init(dev_priv
);
15002 intel_crt_init(dev_priv
);
15004 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
15005 DRM_DEBUG_KMS("probing SDVOB\n");
15006 found
= intel_sdvo_init(dev_priv
, GEN3_SDVOB
, PORT_B
);
15007 if (!found
&& IS_G4X(dev_priv
)) {
15008 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
15009 intel_hdmi_init(dev_priv
, GEN4_HDMIB
, PORT_B
);
15012 if (!found
&& IS_G4X(dev_priv
))
15013 intel_dp_init(dev_priv
, DP_B
, PORT_B
);
15016 /* Before G4X SDVOC doesn't have its own detect register */
15018 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
15019 DRM_DEBUG_KMS("probing SDVOC\n");
15020 found
= intel_sdvo_init(dev_priv
, GEN3_SDVOC
, PORT_C
);
15023 if (!found
&& (I915_READ(GEN3_SDVOC
) & SDVO_DETECTED
)) {
15025 if (IS_G4X(dev_priv
)) {
15026 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
15027 intel_hdmi_init(dev_priv
, GEN4_HDMIC
, PORT_C
);
15029 if (IS_G4X(dev_priv
))
15030 intel_dp_init(dev_priv
, DP_C
, PORT_C
);
15033 if (IS_G4X(dev_priv
) && (I915_READ(DP_D
) & DP_DETECTED
))
15034 intel_dp_init(dev_priv
, DP_D
, PORT_D
);
15036 if (SUPPORTS_TV(dev_priv
))
15037 intel_tv_init(dev_priv
);
15038 } else if (IS_GEN(dev_priv
, 2)) {
15039 if (IS_I85X(dev_priv
))
15040 intel_lvds_init(dev_priv
);
15042 intel_crt_init(dev_priv
);
15043 intel_dvo_init(dev_priv
);
15046 intel_psr_init(dev_priv
);
15048 for_each_intel_encoder(&dev_priv
->drm
, encoder
) {
15049 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
15050 encoder
->base
.possible_clones
=
15051 intel_encoder_clones(encoder
);
15054 intel_init_pch_refclk(dev_priv
);
15056 drm_helper_move_panel_connectors_to_head(&dev_priv
->drm
);
15059 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
15061 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
15062 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
15064 drm_framebuffer_cleanup(fb
);
15066 i915_gem_object_lock(obj
);
15067 WARN_ON(!obj
->framebuffer_references
--);
15068 i915_gem_object_unlock(obj
);
15070 i915_gem_object_put(obj
);
15075 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
15076 struct drm_file
*file
,
15077 unsigned int *handle
)
15079 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
15081 if (obj
->userptr
.mm
) {
15082 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
15086 return drm_gem_handle_create(file
, &obj
->base
, handle
);
15089 static int intel_user_framebuffer_dirty(struct drm_framebuffer
*fb
,
15090 struct drm_file
*file
,
15091 unsigned flags
, unsigned color
,
15092 struct drm_clip_rect
*clips
,
15093 unsigned num_clips
)
15095 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
15097 i915_gem_object_flush_if_display(obj
);
15098 intel_fb_obj_flush(obj
, ORIGIN_DIRTYFB
);
15103 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
15104 .destroy
= intel_user_framebuffer_destroy
,
15105 .create_handle
= intel_user_framebuffer_create_handle
,
15106 .dirty
= intel_user_framebuffer_dirty
,
15110 u32
intel_fb_pitch_limit(struct drm_i915_private
*dev_priv
,
15111 u32 pixel_format
, u64 fb_modifier
)
15113 struct intel_crtc
*crtc
;
15114 struct intel_plane
*plane
;
15117 * We assume the primary plane for pipe A has
15118 * the highest stride limits of them all.
15120 crtc
= intel_get_crtc_for_pipe(dev_priv
, PIPE_A
);
15121 plane
= to_intel_plane(crtc
->base
.primary
);
15123 return plane
->max_stride(plane
, pixel_format
, fb_modifier
,
15124 DRM_MODE_ROTATE_0
);
15127 static int intel_framebuffer_init(struct intel_framebuffer
*intel_fb
,
15128 struct drm_i915_gem_object
*obj
,
15129 struct drm_mode_fb_cmd2
*mode_cmd
)
15131 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
15132 struct drm_framebuffer
*fb
= &intel_fb
->base
;
15134 unsigned int tiling
, stride
;
15138 i915_gem_object_lock(obj
);
15139 obj
->framebuffer_references
++;
15140 tiling
= i915_gem_object_get_tiling(obj
);
15141 stride
= i915_gem_object_get_stride(obj
);
15142 i915_gem_object_unlock(obj
);
15144 if (mode_cmd
->flags
& DRM_MODE_FB_MODIFIERS
) {
15146 * If there's a fence, enforce that
15147 * the fb modifier and tiling mode match.
15149 if (tiling
!= I915_TILING_NONE
&&
15150 tiling
!= intel_fb_modifier_to_tiling(mode_cmd
->modifier
[0])) {
15151 DRM_DEBUG_KMS("tiling_mode doesn't match fb modifier\n");
15155 if (tiling
== I915_TILING_X
) {
15156 mode_cmd
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
15157 } else if (tiling
== I915_TILING_Y
) {
15158 DRM_DEBUG_KMS("No Y tiling for legacy addfb\n");
15163 if (!drm_any_plane_has_format(&dev_priv
->drm
,
15164 mode_cmd
->pixel_format
,
15165 mode_cmd
->modifier
[0])) {
15166 struct drm_format_name_buf format_name
;
15168 DRM_DEBUG_KMS("unsupported pixel format %s / modifier 0x%llx\n",
15169 drm_get_format_name(mode_cmd
->pixel_format
,
15171 mode_cmd
->modifier
[0]);
15176 * gen2/3 display engine uses the fence if present,
15177 * so the tiling mode must match the fb modifier exactly.
15179 if (INTEL_GEN(dev_priv
) < 4 &&
15180 tiling
!= intel_fb_modifier_to_tiling(mode_cmd
->modifier
[0])) {
15181 DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n");
15185 pitch_limit
= intel_fb_pitch_limit(dev_priv
, mode_cmd
->pixel_format
,
15186 mode_cmd
->modifier
[0]);
15187 if (mode_cmd
->pitches
[0] > pitch_limit
) {
15188 DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n",
15189 mode_cmd
->modifier
[0] != DRM_FORMAT_MOD_LINEAR
?
15190 "tiled" : "linear",
15191 mode_cmd
->pitches
[0], pitch_limit
);
15196 * If there's a fence, enforce that
15197 * the fb pitch and fence stride match.
15199 if (tiling
!= I915_TILING_NONE
&& mode_cmd
->pitches
[0] != stride
) {
15200 DRM_DEBUG_KMS("pitch (%d) must match tiling stride (%d)\n",
15201 mode_cmd
->pitches
[0], stride
);
15205 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
15206 if (mode_cmd
->offsets
[0] != 0)
15209 drm_helper_mode_fill_fb_struct(&dev_priv
->drm
, fb
, mode_cmd
);
15211 for (i
= 0; i
< fb
->format
->num_planes
; i
++) {
15212 u32 stride_alignment
;
15214 if (mode_cmd
->handles
[i
] != mode_cmd
->handles
[0]) {
15215 DRM_DEBUG_KMS("bad plane %d handle\n", i
);
15219 stride_alignment
= intel_fb_stride_alignment(fb
, i
);
15222 * Display WA #0531: skl,bxt,kbl,glk
15224 * Render decompression and plane width > 3840
15225 * combined with horizontal panning requires the
15226 * plane stride to be a multiple of 4. We'll just
15227 * require the entire fb to accommodate that to avoid
15228 * potential runtime errors at plane configuration time.
15230 if (IS_GEN(dev_priv
, 9) && i
== 0 && fb
->width
> 3840 &&
15231 is_ccs_modifier(fb
->modifier
))
15232 stride_alignment
*= 4;
15234 if (fb
->pitches
[i
] & (stride_alignment
- 1)) {
15235 DRM_DEBUG_KMS("plane %d pitch (%d) must be at least %u byte aligned\n",
15236 i
, fb
->pitches
[i
], stride_alignment
);
15240 fb
->obj
[i
] = &obj
->base
;
15243 ret
= intel_fill_fb_info(dev_priv
, fb
);
15247 ret
= drm_framebuffer_init(&dev_priv
->drm
, fb
, &intel_fb_funcs
);
15249 DRM_ERROR("framebuffer init failed %d\n", ret
);
15256 i915_gem_object_lock(obj
);
15257 obj
->framebuffer_references
--;
15258 i915_gem_object_unlock(obj
);
15262 static struct drm_framebuffer
*
15263 intel_user_framebuffer_create(struct drm_device
*dev
,
15264 struct drm_file
*filp
,
15265 const struct drm_mode_fb_cmd2
*user_mode_cmd
)
15267 struct drm_framebuffer
*fb
;
15268 struct drm_i915_gem_object
*obj
;
15269 struct drm_mode_fb_cmd2 mode_cmd
= *user_mode_cmd
;
15271 obj
= i915_gem_object_lookup(filp
, mode_cmd
.handles
[0]);
15273 return ERR_PTR(-ENOENT
);
15275 fb
= intel_framebuffer_create(obj
, &mode_cmd
);
15277 i915_gem_object_put(obj
);
15282 static void intel_atomic_state_free(struct drm_atomic_state
*state
)
15284 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
15286 drm_atomic_state_default_release(state
);
15288 i915_sw_fence_fini(&intel_state
->commit_ready
);
15293 static enum drm_mode_status
15294 intel_mode_valid(struct drm_device
*dev
,
15295 const struct drm_display_mode
*mode
)
15297 struct drm_i915_private
*dev_priv
= to_i915(dev
);
15298 int hdisplay_max
, htotal_max
;
15299 int vdisplay_max
, vtotal_max
;
15302 * Can't reject DBLSCAN here because Xorg ddxen can add piles
15303 * of DBLSCAN modes to the output's mode list when they detect
15304 * the scaling mode property on the connector. And they don't
15305 * ask the kernel to validate those modes in any way until
15306 * modeset time at which point the client gets a protocol error.
15307 * So in order to not upset those clients we silently ignore the
15308 * DBLSCAN flag on such connectors. For other connectors we will
15309 * reject modes with the DBLSCAN flag in encoder->compute_config().
15310 * And we always reject DBLSCAN modes in connector->mode_valid()
15311 * as we never want such modes on the connector's mode list.
15314 if (mode
->vscan
> 1)
15315 return MODE_NO_VSCAN
;
15317 if (mode
->flags
& DRM_MODE_FLAG_HSKEW
)
15318 return MODE_H_ILLEGAL
;
15320 if (mode
->flags
& (DRM_MODE_FLAG_CSYNC
|
15321 DRM_MODE_FLAG_NCSYNC
|
15322 DRM_MODE_FLAG_PCSYNC
))
15325 if (mode
->flags
& (DRM_MODE_FLAG_BCAST
|
15326 DRM_MODE_FLAG_PIXMUX
|
15327 DRM_MODE_FLAG_CLKDIV2
))
15330 if (INTEL_GEN(dev_priv
) >= 9 ||
15331 IS_BROADWELL(dev_priv
) || IS_HASWELL(dev_priv
)) {
15332 hdisplay_max
= 8192; /* FDI max 4096 handled elsewhere */
15333 vdisplay_max
= 4096;
15336 } else if (INTEL_GEN(dev_priv
) >= 3) {
15337 hdisplay_max
= 4096;
15338 vdisplay_max
= 4096;
15342 hdisplay_max
= 2048;
15343 vdisplay_max
= 2048;
15348 if (mode
->hdisplay
> hdisplay_max
||
15349 mode
->hsync_start
> htotal_max
||
15350 mode
->hsync_end
> htotal_max
||
15351 mode
->htotal
> htotal_max
)
15352 return MODE_H_ILLEGAL
;
15354 if (mode
->vdisplay
> vdisplay_max
||
15355 mode
->vsync_start
> vtotal_max
||
15356 mode
->vsync_end
> vtotal_max
||
15357 mode
->vtotal
> vtotal_max
)
15358 return MODE_V_ILLEGAL
;
15363 static const struct drm_mode_config_funcs intel_mode_funcs
= {
15364 .fb_create
= intel_user_framebuffer_create
,
15365 .get_format_info
= intel_get_format_info
,
15366 .output_poll_changed
= intel_fbdev_output_poll_changed
,
15367 .mode_valid
= intel_mode_valid
,
15368 .atomic_check
= intel_atomic_check
,
15369 .atomic_commit
= intel_atomic_commit
,
15370 .atomic_state_alloc
= intel_atomic_state_alloc
,
15371 .atomic_state_clear
= intel_atomic_state_clear
,
15372 .atomic_state_free
= intel_atomic_state_free
,
15376 * intel_init_display_hooks - initialize the display modesetting hooks
15377 * @dev_priv: device private
15379 void intel_init_display_hooks(struct drm_i915_private
*dev_priv
)
15381 intel_init_cdclk_hooks(dev_priv
);
15383 if (INTEL_GEN(dev_priv
) >= 9) {
15384 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
15385 dev_priv
->display
.get_initial_plane_config
=
15386 skylake_get_initial_plane_config
;
15387 dev_priv
->display
.crtc_compute_clock
=
15388 haswell_crtc_compute_clock
;
15389 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
15390 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
15391 } else if (HAS_DDI(dev_priv
)) {
15392 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
15393 dev_priv
->display
.get_initial_plane_config
=
15394 i9xx_get_initial_plane_config
;
15395 dev_priv
->display
.crtc_compute_clock
=
15396 haswell_crtc_compute_clock
;
15397 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
15398 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
15399 } else if (HAS_PCH_SPLIT(dev_priv
)) {
15400 dev_priv
->display
.get_pipe_config
= ironlake_get_pipe_config
;
15401 dev_priv
->display
.get_initial_plane_config
=
15402 i9xx_get_initial_plane_config
;
15403 dev_priv
->display
.crtc_compute_clock
=
15404 ironlake_crtc_compute_clock
;
15405 dev_priv
->display
.crtc_enable
= ironlake_crtc_enable
;
15406 dev_priv
->display
.crtc_disable
= ironlake_crtc_disable
;
15407 } else if (IS_CHERRYVIEW(dev_priv
)) {
15408 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
15409 dev_priv
->display
.get_initial_plane_config
=
15410 i9xx_get_initial_plane_config
;
15411 dev_priv
->display
.crtc_compute_clock
= chv_crtc_compute_clock
;
15412 dev_priv
->display
.crtc_enable
= valleyview_crtc_enable
;
15413 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
15414 } else if (IS_VALLEYVIEW(dev_priv
)) {
15415 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
15416 dev_priv
->display
.get_initial_plane_config
=
15417 i9xx_get_initial_plane_config
;
15418 dev_priv
->display
.crtc_compute_clock
= vlv_crtc_compute_clock
;
15419 dev_priv
->display
.crtc_enable
= valleyview_crtc_enable
;
15420 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
15421 } else if (IS_G4X(dev_priv
)) {
15422 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
15423 dev_priv
->display
.get_initial_plane_config
=
15424 i9xx_get_initial_plane_config
;
15425 dev_priv
->display
.crtc_compute_clock
= g4x_crtc_compute_clock
;
15426 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
15427 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
15428 } else if (IS_PINEVIEW(dev_priv
)) {
15429 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
15430 dev_priv
->display
.get_initial_plane_config
=
15431 i9xx_get_initial_plane_config
;
15432 dev_priv
->display
.crtc_compute_clock
= pnv_crtc_compute_clock
;
15433 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
15434 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
15435 } else if (!IS_GEN(dev_priv
, 2)) {
15436 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
15437 dev_priv
->display
.get_initial_plane_config
=
15438 i9xx_get_initial_plane_config
;
15439 dev_priv
->display
.crtc_compute_clock
= i9xx_crtc_compute_clock
;
15440 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
15441 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
15443 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
15444 dev_priv
->display
.get_initial_plane_config
=
15445 i9xx_get_initial_plane_config
;
15446 dev_priv
->display
.crtc_compute_clock
= i8xx_crtc_compute_clock
;
15447 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
15448 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
15451 if (IS_GEN(dev_priv
, 5)) {
15452 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
15453 } else if (IS_GEN(dev_priv
, 6)) {
15454 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
15455 } else if (IS_IVYBRIDGE(dev_priv
)) {
15456 /* FIXME: detect B0+ stepping and use auto training */
15457 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
15458 } else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
15459 dev_priv
->display
.fdi_link_train
= hsw_fdi_link_train
;
15462 if (INTEL_GEN(dev_priv
) >= 9)
15463 dev_priv
->display
.update_crtcs
= skl_update_crtcs
;
15465 dev_priv
->display
.update_crtcs
= intel_update_crtcs
;
15468 /* Disable the VGA plane that we never use */
15469 static void i915_disable_vga(struct drm_i915_private
*dev_priv
)
15471 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
15473 i915_reg_t vga_reg
= i915_vgacntrl_reg(dev_priv
);
15475 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15476 vga_get_uninterruptible(pdev
, VGA_RSRC_LEGACY_IO
);
15477 outb(SR01
, VGA_SR_INDEX
);
15478 sr1
= inb(VGA_SR_DATA
);
15479 outb(sr1
| 1<<5, VGA_SR_DATA
);
15480 vga_put(pdev
, VGA_RSRC_LEGACY_IO
);
15483 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
15484 POSTING_READ(vga_reg
);
15487 void intel_modeset_init_hw(struct drm_device
*dev
)
15489 struct drm_i915_private
*dev_priv
= to_i915(dev
);
15491 intel_update_cdclk(dev_priv
);
15492 intel_dump_cdclk_state(&dev_priv
->cdclk
.hw
, "Current CDCLK");
15493 dev_priv
->cdclk
.logical
= dev_priv
->cdclk
.actual
= dev_priv
->cdclk
.hw
;
15497 * Calculate what we think the watermarks should be for the state we've read
15498 * out of the hardware and then immediately program those watermarks so that
15499 * we ensure the hardware settings match our internal state.
15501 * We can calculate what we think WM's should be by creating a duplicate of the
15502 * current state (which was constructed during hardware readout) and running it
15503 * through the atomic check code to calculate new watermark values in the
15506 static void sanitize_watermarks(struct drm_device
*dev
)
15508 struct drm_i915_private
*dev_priv
= to_i915(dev
);
15509 struct drm_atomic_state
*state
;
15510 struct intel_atomic_state
*intel_state
;
15511 struct drm_crtc
*crtc
;
15512 struct drm_crtc_state
*cstate
;
15513 struct drm_modeset_acquire_ctx ctx
;
15517 /* Only supported on platforms that use atomic watermark design */
15518 if (!dev_priv
->display
.optimize_watermarks
)
15522 * We need to hold connection_mutex before calling duplicate_state so
15523 * that the connector loop is protected.
15525 drm_modeset_acquire_init(&ctx
, 0);
15527 ret
= drm_modeset_lock_all_ctx(dev
, &ctx
);
15528 if (ret
== -EDEADLK
) {
15529 drm_modeset_backoff(&ctx
);
15531 } else if (WARN_ON(ret
)) {
15535 state
= drm_atomic_helper_duplicate_state(dev
, &ctx
);
15536 if (WARN_ON(IS_ERR(state
)))
15539 intel_state
= to_intel_atomic_state(state
);
15542 * Hardware readout is the only time we don't want to calculate
15543 * intermediate watermarks (since we don't trust the current
15546 if (!HAS_GMCH(dev_priv
))
15547 intel_state
->skip_intermediate_wm
= true;
15549 ret
= intel_atomic_check(dev
, state
);
15552 * If we fail here, it means that the hardware appears to be
15553 * programmed in a way that shouldn't be possible, given our
15554 * understanding of watermark requirements. This might mean a
15555 * mistake in the hardware readout code or a mistake in the
15556 * watermark calculations for a given platform. Raise a WARN
15557 * so that this is noticeable.
15559 * If this actually happens, we'll have to just leave the
15560 * BIOS-programmed watermarks untouched and hope for the best.
15562 WARN(true, "Could not determine valid watermarks for inherited state\n");
15566 /* Write calculated watermark values back */
15567 for_each_new_crtc_in_state(state
, crtc
, cstate
, i
) {
15568 struct intel_crtc_state
*cs
= to_intel_crtc_state(cstate
);
15570 cs
->wm
.need_postvbl_update
= true;
15571 dev_priv
->display
.optimize_watermarks(intel_state
, cs
);
15573 to_intel_crtc_state(crtc
->state
)->wm
= cs
->wm
;
15577 drm_atomic_state_put(state
);
15579 drm_modeset_drop_locks(&ctx
);
15580 drm_modeset_acquire_fini(&ctx
);
15583 static void intel_update_fdi_pll_freq(struct drm_i915_private
*dev_priv
)
15585 if (IS_GEN(dev_priv
, 5)) {
15587 I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
;
15589 dev_priv
->fdi_pll_freq
= (fdi_pll_clk
+ 2) * 10000;
15590 } else if (IS_GEN(dev_priv
, 6) || IS_IVYBRIDGE(dev_priv
)) {
15591 dev_priv
->fdi_pll_freq
= 270000;
15596 DRM_DEBUG_DRIVER("FDI PLL freq=%d\n", dev_priv
->fdi_pll_freq
);
15599 static int intel_initial_commit(struct drm_device
*dev
)
15601 struct drm_atomic_state
*state
= NULL
;
15602 struct drm_modeset_acquire_ctx ctx
;
15603 struct drm_crtc
*crtc
;
15604 struct drm_crtc_state
*crtc_state
;
15607 state
= drm_atomic_state_alloc(dev
);
15611 drm_modeset_acquire_init(&ctx
, 0);
15614 state
->acquire_ctx
= &ctx
;
15616 drm_for_each_crtc(crtc
, dev
) {
15617 crtc_state
= drm_atomic_get_crtc_state(state
, crtc
);
15618 if (IS_ERR(crtc_state
)) {
15619 ret
= PTR_ERR(crtc_state
);
15623 if (crtc_state
->active
) {
15624 ret
= drm_atomic_add_affected_planes(state
, crtc
);
15629 * FIXME hack to force a LUT update to avoid the
15630 * plane update forcing the pipe gamma on without
15631 * having a proper LUT loaded. Remove once we
15632 * have readout for pipe gamma enable.
15634 crtc_state
->color_mgmt_changed
= true;
15638 ret
= drm_atomic_commit(state
);
15641 if (ret
== -EDEADLK
) {
15642 drm_atomic_state_clear(state
);
15643 drm_modeset_backoff(&ctx
);
15647 drm_atomic_state_put(state
);
15649 drm_modeset_drop_locks(&ctx
);
15650 drm_modeset_acquire_fini(&ctx
);
15655 int intel_modeset_init(struct drm_device
*dev
)
15657 struct drm_i915_private
*dev_priv
= to_i915(dev
);
15658 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
15660 struct intel_crtc
*crtc
;
15663 dev_priv
->modeset_wq
= alloc_ordered_workqueue("i915_modeset", 0);
15665 drm_mode_config_init(dev
);
15667 dev
->mode_config
.min_width
= 0;
15668 dev
->mode_config
.min_height
= 0;
15670 dev
->mode_config
.preferred_depth
= 24;
15671 dev
->mode_config
.prefer_shadow
= 1;
15673 dev
->mode_config
.allow_fb_modifiers
= true;
15675 dev
->mode_config
.funcs
= &intel_mode_funcs
;
15677 init_llist_head(&dev_priv
->atomic_helper
.free_list
);
15678 INIT_WORK(&dev_priv
->atomic_helper
.free_work
,
15679 intel_atomic_helper_free_state_worker
);
15681 intel_init_quirks(dev_priv
);
15683 intel_fbc_init(dev_priv
);
15685 intel_init_pm(dev_priv
);
15688 * There may be no VBT; and if the BIOS enabled SSC we can
15689 * just keep using it to avoid unnecessary flicker. Whereas if the
15690 * BIOS isn't using it, don't assume it will work even if the VBT
15691 * indicates as much.
15693 if (HAS_PCH_IBX(dev_priv
) || HAS_PCH_CPT(dev_priv
)) {
15694 bool bios_lvds_use_ssc
= !!(I915_READ(PCH_DREF_CONTROL
) &
15697 if (dev_priv
->vbt
.lvds_use_ssc
!= bios_lvds_use_ssc
) {
15698 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15699 bios_lvds_use_ssc
? "en" : "dis",
15700 dev_priv
->vbt
.lvds_use_ssc
? "en" : "dis");
15701 dev_priv
->vbt
.lvds_use_ssc
= bios_lvds_use_ssc
;
15705 /* maximum framebuffer dimensions */
15706 if (IS_GEN(dev_priv
, 2)) {
15707 dev
->mode_config
.max_width
= 2048;
15708 dev
->mode_config
.max_height
= 2048;
15709 } else if (IS_GEN(dev_priv
, 3)) {
15710 dev
->mode_config
.max_width
= 4096;
15711 dev
->mode_config
.max_height
= 4096;
15713 dev
->mode_config
.max_width
= 8192;
15714 dev
->mode_config
.max_height
= 8192;
15717 if (IS_I845G(dev_priv
) || IS_I865G(dev_priv
)) {
15718 dev
->mode_config
.cursor_width
= IS_I845G(dev_priv
) ? 64 : 512;
15719 dev
->mode_config
.cursor_height
= 1023;
15720 } else if (IS_GEN(dev_priv
, 2)) {
15721 dev
->mode_config
.cursor_width
= 64;
15722 dev
->mode_config
.cursor_height
= 64;
15724 dev
->mode_config
.cursor_width
= 256;
15725 dev
->mode_config
.cursor_height
= 256;
15728 dev
->mode_config
.fb_base
= ggtt
->gmadr
.start
;
15730 DRM_DEBUG_KMS("%d display pipe%s available.\n",
15731 INTEL_INFO(dev_priv
)->num_pipes
,
15732 INTEL_INFO(dev_priv
)->num_pipes
> 1 ? "s" : "");
15734 for_each_pipe(dev_priv
, pipe
) {
15735 ret
= intel_crtc_init(dev_priv
, pipe
);
15737 drm_mode_config_cleanup(dev
);
15742 intel_shared_dpll_init(dev
);
15743 intel_update_fdi_pll_freq(dev_priv
);
15745 intel_update_czclk(dev_priv
);
15746 intel_modeset_init_hw(dev
);
15748 intel_hdcp_component_init(dev_priv
);
15750 if (dev_priv
->max_cdclk_freq
== 0)
15751 intel_update_max_cdclk(dev_priv
);
15753 /* Just disable it once at startup */
15754 i915_disable_vga(dev_priv
);
15755 intel_setup_outputs(dev_priv
);
15757 drm_modeset_lock_all(dev
);
15758 intel_modeset_setup_hw_state(dev
, dev
->mode_config
.acquire_ctx
);
15759 drm_modeset_unlock_all(dev
);
15761 for_each_intel_crtc(dev
, crtc
) {
15762 struct intel_initial_plane_config plane_config
= {};
15768 * Note that reserving the BIOS fb up front prevents us
15769 * from stuffing other stolen allocations like the ring
15770 * on top. This prevents some ugliness at boot time, and
15771 * can even allow for smooth boot transitions if the BIOS
15772 * fb is large enough for the active pipe configuration.
15774 dev_priv
->display
.get_initial_plane_config(crtc
,
15778 * If the fb is shared between multiple heads, we'll
15779 * just get the first one.
15781 intel_find_initial_plane_obj(crtc
, &plane_config
);
15785 * Make sure hardware watermarks really match the state we read out.
15786 * Note that we need to do this after reconstructing the BIOS fb's
15787 * since the watermark calculation done here will use pstate->fb.
15789 if (!HAS_GMCH(dev_priv
))
15790 sanitize_watermarks(dev
);
15793 * Force all active planes to recompute their states. So that on
15794 * mode_setcrtc after probe, all the intel_plane_state variables
15795 * are already calculated and there is no assert_plane warnings
15798 ret
= intel_initial_commit(dev
);
15800 DRM_DEBUG_KMS("Initial commit in probe failed.\n");
15805 void i830_enable_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
15807 struct intel_crtc
*crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
15808 /* 640x480@60Hz, ~25175 kHz */
15809 struct dpll clock
= {
15819 WARN_ON(i9xx_calc_dpll_params(48000, &clock
) != 25154);
15821 DRM_DEBUG_KMS("enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
15822 pipe_name(pipe
), clock
.vco
, clock
.dot
);
15824 fp
= i9xx_dpll_compute_fp(&clock
);
15825 dpll
= DPLL_DVO_2X_MODE
|
15826 DPLL_VGA_MODE_DIS
|
15827 ((clock
.p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
) |
15828 PLL_P2_DIVIDE_BY_4
|
15829 PLL_REF_INPUT_DREFCLK
|
15832 I915_WRITE(FP0(pipe
), fp
);
15833 I915_WRITE(FP1(pipe
), fp
);
15835 I915_WRITE(HTOTAL(pipe
), (640 - 1) | ((800 - 1) << 16));
15836 I915_WRITE(HBLANK(pipe
), (640 - 1) | ((800 - 1) << 16));
15837 I915_WRITE(HSYNC(pipe
), (656 - 1) | ((752 - 1) << 16));
15838 I915_WRITE(VTOTAL(pipe
), (480 - 1) | ((525 - 1) << 16));
15839 I915_WRITE(VBLANK(pipe
), (480 - 1) | ((525 - 1) << 16));
15840 I915_WRITE(VSYNC(pipe
), (490 - 1) | ((492 - 1) << 16));
15841 I915_WRITE(PIPESRC(pipe
), ((640 - 1) << 16) | (480 - 1));
15844 * Apparently we need to have VGA mode enabled prior to changing
15845 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
15846 * dividers, even though the register value does change.
15848 I915_WRITE(DPLL(pipe
), dpll
& ~DPLL_VGA_MODE_DIS
);
15849 I915_WRITE(DPLL(pipe
), dpll
);
15851 /* Wait for the clocks to stabilize. */
15852 POSTING_READ(DPLL(pipe
));
15855 /* The pixel multiplier can only be updated once the
15856 * DPLL is enabled and the clocks are stable.
15858 * So write it again.
15860 I915_WRITE(DPLL(pipe
), dpll
);
15862 /* We do this three times for luck */
15863 for (i
= 0; i
< 3 ; i
++) {
15864 I915_WRITE(DPLL(pipe
), dpll
);
15865 POSTING_READ(DPLL(pipe
));
15866 udelay(150); /* wait for warmup */
15869 I915_WRITE(PIPECONF(pipe
), PIPECONF_ENABLE
| PIPECONF_PROGRESSIVE
);
15870 POSTING_READ(PIPECONF(pipe
));
15872 intel_wait_for_pipe_scanline_moving(crtc
);
15875 void i830_disable_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
15877 struct intel_crtc
*crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
15879 DRM_DEBUG_KMS("disabling pipe %c due to force quirk\n",
15882 WARN_ON(I915_READ(DSPCNTR(PLANE_A
)) & DISPLAY_PLANE_ENABLE
);
15883 WARN_ON(I915_READ(DSPCNTR(PLANE_B
)) & DISPLAY_PLANE_ENABLE
);
15884 WARN_ON(I915_READ(DSPCNTR(PLANE_C
)) & DISPLAY_PLANE_ENABLE
);
15885 WARN_ON(I915_READ(CURCNTR(PIPE_A
)) & MCURSOR_MODE
);
15886 WARN_ON(I915_READ(CURCNTR(PIPE_B
)) & MCURSOR_MODE
);
15888 I915_WRITE(PIPECONF(pipe
), 0);
15889 POSTING_READ(PIPECONF(pipe
));
15891 intel_wait_for_pipe_scanline_stopped(crtc
);
15893 I915_WRITE(DPLL(pipe
), DPLL_VGA_MODE_DIS
);
15894 POSTING_READ(DPLL(pipe
));
15898 intel_sanitize_plane_mapping(struct drm_i915_private
*dev_priv
)
15900 struct intel_crtc
*crtc
;
15902 if (INTEL_GEN(dev_priv
) >= 4)
15905 for_each_intel_crtc(&dev_priv
->drm
, crtc
) {
15906 struct intel_plane
*plane
=
15907 to_intel_plane(crtc
->base
.primary
);
15908 struct intel_crtc
*plane_crtc
;
15911 if (!plane
->get_hw_state(plane
, &pipe
))
15914 if (pipe
== crtc
->pipe
)
15917 DRM_DEBUG_KMS("[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n",
15918 plane
->base
.base
.id
, plane
->base
.name
);
15920 plane_crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
15921 intel_plane_disable_noatomic(plane_crtc
, plane
);
15925 static bool intel_crtc_has_encoders(struct intel_crtc
*crtc
)
15927 struct drm_device
*dev
= crtc
->base
.dev
;
15928 struct intel_encoder
*encoder
;
15930 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
)
15936 static struct intel_connector
*intel_encoder_find_connector(struct intel_encoder
*encoder
)
15938 struct drm_device
*dev
= encoder
->base
.dev
;
15939 struct intel_connector
*connector
;
15941 for_each_connector_on_encoder(dev
, &encoder
->base
, connector
)
15947 static bool has_pch_trancoder(struct drm_i915_private
*dev_priv
,
15948 enum pipe pch_transcoder
)
15950 return HAS_PCH_IBX(dev_priv
) || HAS_PCH_CPT(dev_priv
) ||
15951 (HAS_PCH_LPT_H(dev_priv
) && pch_transcoder
== PIPE_A
);
15954 static void intel_sanitize_crtc(struct intel_crtc
*crtc
,
15955 struct drm_modeset_acquire_ctx
*ctx
)
15957 struct drm_device
*dev
= crtc
->base
.dev
;
15958 struct drm_i915_private
*dev_priv
= to_i915(dev
);
15959 struct intel_crtc_state
*crtc_state
= to_intel_crtc_state(crtc
->base
.state
);
15960 enum transcoder cpu_transcoder
= crtc_state
->cpu_transcoder
;
15962 /* Clear any frame start delays used for debugging left by the BIOS */
15963 if (crtc
->active
&& !transcoder_is_dsi(cpu_transcoder
)) {
15964 i915_reg_t reg
= PIPECONF(cpu_transcoder
);
15967 I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
15970 if (crtc_state
->base
.active
) {
15971 struct intel_plane
*plane
;
15973 /* Disable everything but the primary plane */
15974 for_each_intel_plane_on_crtc(dev
, crtc
, plane
) {
15975 const struct intel_plane_state
*plane_state
=
15976 to_intel_plane_state(plane
->base
.state
);
15978 if (plane_state
->base
.visible
&&
15979 plane
->base
.type
!= DRM_PLANE_TYPE_PRIMARY
)
15980 intel_plane_disable_noatomic(crtc
, plane
);
15984 * Disable any background color set by the BIOS, but enable the
15985 * gamma and CSC to match how we program our planes.
15987 if (INTEL_GEN(dev_priv
) >= 9)
15988 I915_WRITE(SKL_BOTTOM_COLOR(crtc
->pipe
),
15989 SKL_BOTTOM_COLOR_GAMMA_ENABLE
|
15990 SKL_BOTTOM_COLOR_CSC_ENABLE
);
15993 /* Adjust the state of the output pipe according to whether we
15994 * have active connectors/encoders. */
15995 if (crtc_state
->base
.active
&& !intel_crtc_has_encoders(crtc
))
15996 intel_crtc_disable_noatomic(&crtc
->base
, ctx
);
15998 if (crtc_state
->base
.active
|| HAS_GMCH(dev_priv
)) {
16000 * We start out with underrun reporting disabled to avoid races.
16001 * For correct bookkeeping mark this on active crtcs.
16003 * Also on gmch platforms we dont have any hardware bits to
16004 * disable the underrun reporting. Which means we need to start
16005 * out with underrun reporting disabled also on inactive pipes,
16006 * since otherwise we'll complain about the garbage we read when
16007 * e.g. coming up after runtime pm.
16009 * No protection against concurrent access is required - at
16010 * worst a fifo underrun happens which also sets this to false.
16012 crtc
->cpu_fifo_underrun_disabled
= true;
16014 * We track the PCH trancoder underrun reporting state
16015 * within the crtc. With crtc for pipe A housing the underrun
16016 * reporting state for PCH transcoder A, crtc for pipe B housing
16017 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
16018 * and marking underrun reporting as disabled for the non-existing
16019 * PCH transcoders B and C would prevent enabling the south
16020 * error interrupt (see cpt_can_enable_serr_int()).
16022 if (has_pch_trancoder(dev_priv
, crtc
->pipe
))
16023 crtc
->pch_fifo_underrun_disabled
= true;
16027 static bool has_bogus_dpll_config(const struct intel_crtc_state
*crtc_state
)
16029 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->base
.crtc
->dev
);
16032 * Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram
16033 * the hardware when a high res displays plugged in. DPLL P
16034 * divider is zero, and the pipe timings are bonkers. We'll
16035 * try to disable everything in that case.
16037 * FIXME would be nice to be able to sanitize this state
16038 * without several WARNs, but for now let's take the easy
16041 return IS_GEN(dev_priv
, 6) &&
16042 crtc_state
->base
.active
&&
16043 crtc_state
->shared_dpll
&&
16044 crtc_state
->port_clock
== 0;
16047 static void intel_sanitize_encoder(struct intel_encoder
*encoder
)
16049 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
16050 struct intel_connector
*connector
;
16051 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
16052 struct intel_crtc_state
*crtc_state
= crtc
?
16053 to_intel_crtc_state(crtc
->base
.state
) : NULL
;
16055 /* We need to check both for a crtc link (meaning that the
16056 * encoder is active and trying to read from a pipe) and the
16057 * pipe itself being active. */
16058 bool has_active_crtc
= crtc_state
&&
16059 crtc_state
->base
.active
;
16061 if (crtc_state
&& has_bogus_dpll_config(crtc_state
)) {
16062 DRM_DEBUG_KMS("BIOS has misprogrammed the hardware. Disabling pipe %c\n",
16063 pipe_name(crtc
->pipe
));
16064 has_active_crtc
= false;
16067 connector
= intel_encoder_find_connector(encoder
);
16068 if (connector
&& !has_active_crtc
) {
16069 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
16070 encoder
->base
.base
.id
,
16071 encoder
->base
.name
);
16073 /* Connector is active, but has no active pipe. This is
16074 * fallout from our resume register restoring. Disable
16075 * the encoder manually again. */
16077 struct drm_encoder
*best_encoder
;
16079 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
16080 encoder
->base
.base
.id
,
16081 encoder
->base
.name
);
16083 /* avoid oopsing in case the hooks consult best_encoder */
16084 best_encoder
= connector
->base
.state
->best_encoder
;
16085 connector
->base
.state
->best_encoder
= &encoder
->base
;
16087 if (encoder
->disable
)
16088 encoder
->disable(encoder
, crtc_state
,
16089 connector
->base
.state
);
16090 if (encoder
->post_disable
)
16091 encoder
->post_disable(encoder
, crtc_state
,
16092 connector
->base
.state
);
16094 connector
->base
.state
->best_encoder
= best_encoder
;
16096 encoder
->base
.crtc
= NULL
;
16098 /* Inconsistent output/port/pipe state happens presumably due to
16099 * a bug in one of the get_hw_state functions. Or someplace else
16100 * in our code, like the register restore mess on resume. Clamp
16101 * things to off as a safer default. */
16103 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
16104 connector
->base
.encoder
= NULL
;
16107 /* notify opregion of the sanitized encoder state */
16108 intel_opregion_notify_encoder(encoder
, connector
&& has_active_crtc
);
16110 if (INTEL_GEN(dev_priv
) >= 11)
16111 icl_sanitize_encoder_pll_mapping(encoder
);
16114 void i915_redisable_vga_power_on(struct drm_i915_private
*dev_priv
)
16116 i915_reg_t vga_reg
= i915_vgacntrl_reg(dev_priv
);
16118 if (!(I915_READ(vga_reg
) & VGA_DISP_DISABLE
)) {
16119 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
16120 i915_disable_vga(dev_priv
);
16124 void i915_redisable_vga(struct drm_i915_private
*dev_priv
)
16126 intel_wakeref_t wakeref
;
16129 * This function can be called both from intel_modeset_setup_hw_state or
16130 * at a very early point in our resume sequence, where the power well
16131 * structures are not yet restored. Since this function is at a very
16132 * paranoid "someone might have enabled VGA while we were not looking"
16133 * level, just check if the power well is enabled instead of trying to
16134 * follow the "don't touch the power well if we don't need it" policy
16135 * the rest of the driver uses.
16137 wakeref
= intel_display_power_get_if_enabled(dev_priv
,
16142 i915_redisable_vga_power_on(dev_priv
);
16144 intel_display_power_put(dev_priv
, POWER_DOMAIN_VGA
, wakeref
);
16147 /* FIXME read out full plane state for all planes */
16148 static void readout_plane_state(struct drm_i915_private
*dev_priv
)
16150 struct intel_plane
*plane
;
16151 struct intel_crtc
*crtc
;
16153 for_each_intel_plane(&dev_priv
->drm
, plane
) {
16154 struct intel_plane_state
*plane_state
=
16155 to_intel_plane_state(plane
->base
.state
);
16156 struct intel_crtc_state
*crtc_state
;
16157 enum pipe pipe
= PIPE_A
;
16160 visible
= plane
->get_hw_state(plane
, &pipe
);
16162 crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
16163 crtc_state
= to_intel_crtc_state(crtc
->base
.state
);
16165 intel_set_plane_visible(crtc_state
, plane_state
, visible
);
16167 DRM_DEBUG_KMS("[PLANE:%d:%s] hw state readout: %s, pipe %c\n",
16168 plane
->base
.base
.id
, plane
->base
.name
,
16169 enableddisabled(visible
), pipe_name(pipe
));
16172 for_each_intel_crtc(&dev_priv
->drm
, crtc
) {
16173 struct intel_crtc_state
*crtc_state
=
16174 to_intel_crtc_state(crtc
->base
.state
);
16176 fixup_active_planes(crtc_state
);
16180 static void intel_modeset_readout_hw_state(struct drm_device
*dev
)
16182 struct drm_i915_private
*dev_priv
= to_i915(dev
);
16184 struct intel_crtc
*crtc
;
16185 struct intel_encoder
*encoder
;
16186 struct intel_connector
*connector
;
16187 struct drm_connector_list_iter conn_iter
;
16190 dev_priv
->active_crtcs
= 0;
16192 for_each_intel_crtc(dev
, crtc
) {
16193 struct intel_crtc_state
*crtc_state
=
16194 to_intel_crtc_state(crtc
->base
.state
);
16196 __drm_atomic_helper_crtc_destroy_state(&crtc_state
->base
);
16197 memset(crtc_state
, 0, sizeof(*crtc_state
));
16198 crtc_state
->base
.crtc
= &crtc
->base
;
16200 crtc_state
->base
.active
= crtc_state
->base
.enable
=
16201 dev_priv
->display
.get_pipe_config(crtc
, crtc_state
);
16203 crtc
->base
.enabled
= crtc_state
->base
.enable
;
16204 crtc
->active
= crtc_state
->base
.active
;
16206 if (crtc_state
->base
.active
)
16207 dev_priv
->active_crtcs
|= 1 << crtc
->pipe
;
16209 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
16210 crtc
->base
.base
.id
, crtc
->base
.name
,
16211 enableddisabled(crtc_state
->base
.active
));
16214 readout_plane_state(dev_priv
);
16216 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
16217 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
16219 pll
->on
= pll
->info
->funcs
->get_hw_state(dev_priv
, pll
,
16220 &pll
->state
.hw_state
);
16221 pll
->state
.crtc_mask
= 0;
16222 for_each_intel_crtc(dev
, crtc
) {
16223 struct intel_crtc_state
*crtc_state
=
16224 to_intel_crtc_state(crtc
->base
.state
);
16226 if (crtc_state
->base
.active
&&
16227 crtc_state
->shared_dpll
== pll
)
16228 pll
->state
.crtc_mask
|= 1 << crtc
->pipe
;
16230 pll
->active_mask
= pll
->state
.crtc_mask
;
16232 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
16233 pll
->info
->name
, pll
->state
.crtc_mask
, pll
->on
);
16236 for_each_intel_encoder(dev
, encoder
) {
16239 if (encoder
->get_hw_state(encoder
, &pipe
)) {
16240 struct intel_crtc_state
*crtc_state
;
16242 crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
16243 crtc_state
= to_intel_crtc_state(crtc
->base
.state
);
16245 encoder
->base
.crtc
= &crtc
->base
;
16246 encoder
->get_config(encoder
, crtc_state
);
16248 encoder
->base
.crtc
= NULL
;
16251 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
16252 encoder
->base
.base
.id
, encoder
->base
.name
,
16253 enableddisabled(encoder
->base
.crtc
),
16257 drm_connector_list_iter_begin(dev
, &conn_iter
);
16258 for_each_intel_connector_iter(connector
, &conn_iter
) {
16259 if (connector
->get_hw_state(connector
)) {
16260 connector
->base
.dpms
= DRM_MODE_DPMS_ON
;
16262 encoder
= connector
->encoder
;
16263 connector
->base
.encoder
= &encoder
->base
;
16265 if (encoder
->base
.crtc
&&
16266 encoder
->base
.crtc
->state
->active
) {
16268 * This has to be done during hardware readout
16269 * because anything calling .crtc_disable may
16270 * rely on the connector_mask being accurate.
16272 encoder
->base
.crtc
->state
->connector_mask
|=
16273 drm_connector_mask(&connector
->base
);
16274 encoder
->base
.crtc
->state
->encoder_mask
|=
16275 drm_encoder_mask(&encoder
->base
);
16279 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
16280 connector
->base
.encoder
= NULL
;
16282 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
16283 connector
->base
.base
.id
, connector
->base
.name
,
16284 enableddisabled(connector
->base
.encoder
));
16286 drm_connector_list_iter_end(&conn_iter
);
16288 for_each_intel_crtc(dev
, crtc
) {
16289 struct intel_crtc_state
*crtc_state
=
16290 to_intel_crtc_state(crtc
->base
.state
);
16293 memset(&crtc
->base
.mode
, 0, sizeof(crtc
->base
.mode
));
16294 if (crtc_state
->base
.active
) {
16295 intel_mode_from_pipe_config(&crtc
->base
.mode
, crtc_state
);
16296 crtc
->base
.mode
.hdisplay
= crtc_state
->pipe_src_w
;
16297 crtc
->base
.mode
.vdisplay
= crtc_state
->pipe_src_h
;
16298 intel_mode_from_pipe_config(&crtc_state
->base
.adjusted_mode
, crtc_state
);
16299 WARN_ON(drm_atomic_set_mode_for_crtc(crtc
->base
.state
, &crtc
->base
.mode
));
16302 * The initial mode needs to be set in order to keep
16303 * the atomic core happy. It wants a valid mode if the
16304 * crtc's enabled, so we do the above call.
16306 * But we don't set all the derived state fully, hence
16307 * set a flag to indicate that a full recalculation is
16308 * needed on the next commit.
16310 crtc_state
->base
.mode
.private_flags
= I915_MODE_FLAG_INHERITED
;
16312 intel_crtc_compute_pixel_rate(crtc_state
);
16314 if (dev_priv
->display
.modeset_calc_cdclk
) {
16315 min_cdclk
= intel_crtc_compute_min_cdclk(crtc_state
);
16316 if (WARN_ON(min_cdclk
< 0))
16320 drm_calc_timestamping_constants(&crtc
->base
,
16321 &crtc_state
->base
.adjusted_mode
);
16322 update_scanline_offset(crtc_state
);
16325 dev_priv
->min_cdclk
[crtc
->pipe
] = min_cdclk
;
16326 dev_priv
->min_voltage_level
[crtc
->pipe
] =
16327 crtc_state
->min_voltage_level
;
16329 intel_pipe_config_sanity_check(dev_priv
, crtc_state
);
16334 get_encoder_power_domains(struct drm_i915_private
*dev_priv
)
16336 struct intel_encoder
*encoder
;
16338 for_each_intel_encoder(&dev_priv
->drm
, encoder
) {
16339 struct intel_crtc_state
*crtc_state
;
16341 if (!encoder
->get_power_domains
)
16345 * MST-primary and inactive encoders don't have a crtc state
16346 * and neither of these require any power domain references.
16348 if (!encoder
->base
.crtc
)
16351 crtc_state
= to_intel_crtc_state(encoder
->base
.crtc
->state
);
16352 encoder
->get_power_domains(encoder
, crtc_state
);
16356 static void intel_early_display_was(struct drm_i915_private
*dev_priv
)
16358 /* Display WA #1185 WaDisableDARBFClkGating:cnl,glk */
16359 if (IS_CANNONLAKE(dev_priv
) || IS_GEMINILAKE(dev_priv
))
16360 I915_WRITE(GEN9_CLKGATE_DIS_0
, I915_READ(GEN9_CLKGATE_DIS_0
) |
16363 if (IS_HASWELL(dev_priv
)) {
16365 * WaRsPkgCStateDisplayPMReq:hsw
16366 * System hang if this isn't done before disabling all planes!
16368 I915_WRITE(CHICKEN_PAR1_1
,
16369 I915_READ(CHICKEN_PAR1_1
) | FORCE_ARB_IDLE_PLANES
);
16373 static void ibx_sanitize_pch_hdmi_port(struct drm_i915_private
*dev_priv
,
16374 enum port port
, i915_reg_t hdmi_reg
)
16376 u32 val
= I915_READ(hdmi_reg
);
16378 if (val
& SDVO_ENABLE
||
16379 (val
& SDVO_PIPE_SEL_MASK
) == SDVO_PIPE_SEL(PIPE_A
))
16382 DRM_DEBUG_KMS("Sanitizing transcoder select for HDMI %c\n",
16385 val
&= ~SDVO_PIPE_SEL_MASK
;
16386 val
|= SDVO_PIPE_SEL(PIPE_A
);
16388 I915_WRITE(hdmi_reg
, val
);
16391 static void ibx_sanitize_pch_dp_port(struct drm_i915_private
*dev_priv
,
16392 enum port port
, i915_reg_t dp_reg
)
16394 u32 val
= I915_READ(dp_reg
);
16396 if (val
& DP_PORT_EN
||
16397 (val
& DP_PIPE_SEL_MASK
) == DP_PIPE_SEL(PIPE_A
))
16400 DRM_DEBUG_KMS("Sanitizing transcoder select for DP %c\n",
16403 val
&= ~DP_PIPE_SEL_MASK
;
16404 val
|= DP_PIPE_SEL(PIPE_A
);
16406 I915_WRITE(dp_reg
, val
);
16409 static void ibx_sanitize_pch_ports(struct drm_i915_private
*dev_priv
)
16412 * The BIOS may select transcoder B on some of the PCH
16413 * ports even it doesn't enable the port. This would trip
16414 * assert_pch_dp_disabled() and assert_pch_hdmi_disabled().
16415 * Sanitize the transcoder select bits to prevent that. We
16416 * assume that the BIOS never actually enabled the port,
16417 * because if it did we'd actually have to toggle the port
16418 * on and back off to make the transcoder A select stick
16419 * (see. intel_dp_link_down(), intel_disable_hdmi(),
16420 * intel_disable_sdvo()).
16422 ibx_sanitize_pch_dp_port(dev_priv
, PORT_B
, PCH_DP_B
);
16423 ibx_sanitize_pch_dp_port(dev_priv
, PORT_C
, PCH_DP_C
);
16424 ibx_sanitize_pch_dp_port(dev_priv
, PORT_D
, PCH_DP_D
);
16426 /* PCH SDVOB multiplex with HDMIB */
16427 ibx_sanitize_pch_hdmi_port(dev_priv
, PORT_B
, PCH_HDMIB
);
16428 ibx_sanitize_pch_hdmi_port(dev_priv
, PORT_C
, PCH_HDMIC
);
16429 ibx_sanitize_pch_hdmi_port(dev_priv
, PORT_D
, PCH_HDMID
);
16432 /* Scan out the current hw modeset state,
16433 * and sanitizes it to the current state
16436 intel_modeset_setup_hw_state(struct drm_device
*dev
,
16437 struct drm_modeset_acquire_ctx
*ctx
)
16439 struct drm_i915_private
*dev_priv
= to_i915(dev
);
16440 struct intel_crtc_state
*crtc_state
;
16441 struct intel_encoder
*encoder
;
16442 struct intel_crtc
*crtc
;
16443 intel_wakeref_t wakeref
;
16446 wakeref
= intel_display_power_get(dev_priv
, POWER_DOMAIN_INIT
);
16448 intel_early_display_was(dev_priv
);
16449 intel_modeset_readout_hw_state(dev
);
16451 /* HW state is read out, now we need to sanitize this mess. */
16452 get_encoder_power_domains(dev_priv
);
16454 if (HAS_PCH_IBX(dev_priv
))
16455 ibx_sanitize_pch_ports(dev_priv
);
16458 * intel_sanitize_plane_mapping() may need to do vblank
16459 * waits, so we need vblank interrupts restored beforehand.
16461 for_each_intel_crtc(&dev_priv
->drm
, crtc
) {
16462 crtc_state
= to_intel_crtc_state(crtc
->base
.state
);
16464 drm_crtc_vblank_reset(&crtc
->base
);
16466 if (crtc_state
->base
.active
)
16467 intel_crtc_vblank_on(crtc_state
);
16470 intel_sanitize_plane_mapping(dev_priv
);
16472 for_each_intel_encoder(dev
, encoder
)
16473 intel_sanitize_encoder(encoder
);
16475 for_each_intel_crtc(&dev_priv
->drm
, crtc
) {
16476 crtc_state
= to_intel_crtc_state(crtc
->base
.state
);
16477 intel_sanitize_crtc(crtc
, ctx
);
16478 intel_dump_pipe_config(crtc
, crtc_state
,
16479 "[setup_hw_state]");
16482 intel_modeset_update_connector_atomic_state(dev
);
16484 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
16485 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
16487 if (!pll
->on
|| pll
->active_mask
)
16490 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n",
16493 pll
->info
->funcs
->disable(dev_priv
, pll
);
16497 if (IS_G4X(dev_priv
)) {
16498 g4x_wm_get_hw_state(dev_priv
);
16499 g4x_wm_sanitize(dev_priv
);
16500 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
16501 vlv_wm_get_hw_state(dev_priv
);
16502 vlv_wm_sanitize(dev_priv
);
16503 } else if (INTEL_GEN(dev_priv
) >= 9) {
16504 skl_wm_get_hw_state(dev_priv
);
16505 } else if (HAS_PCH_SPLIT(dev_priv
)) {
16506 ilk_wm_get_hw_state(dev_priv
);
16509 for_each_intel_crtc(dev
, crtc
) {
16512 crtc_state
= to_intel_crtc_state(crtc
->base
.state
);
16513 put_domains
= modeset_get_crtc_power_domains(&crtc
->base
, crtc_state
);
16514 if (WARN_ON(put_domains
))
16515 modeset_put_power_domains(dev_priv
, put_domains
);
16518 intel_display_power_put(dev_priv
, POWER_DOMAIN_INIT
, wakeref
);
16520 intel_fbc_init_pipe_state(dev_priv
);
16523 void intel_display_resume(struct drm_device
*dev
)
16525 struct drm_i915_private
*dev_priv
= to_i915(dev
);
16526 struct drm_atomic_state
*state
= dev_priv
->modeset_restore_state
;
16527 struct drm_modeset_acquire_ctx ctx
;
16530 dev_priv
->modeset_restore_state
= NULL
;
16532 state
->acquire_ctx
= &ctx
;
16534 drm_modeset_acquire_init(&ctx
, 0);
16537 ret
= drm_modeset_lock_all_ctx(dev
, &ctx
);
16538 if (ret
!= -EDEADLK
)
16541 drm_modeset_backoff(&ctx
);
16545 ret
= __intel_display_resume(dev
, state
, &ctx
);
16547 intel_enable_ipc(dev_priv
);
16548 drm_modeset_drop_locks(&ctx
);
16549 drm_modeset_acquire_fini(&ctx
);
16552 DRM_ERROR("Restoring old state failed with %i\n", ret
);
16554 drm_atomic_state_put(state
);
16557 static void intel_hpd_poll_fini(struct drm_device
*dev
)
16559 struct intel_connector
*connector
;
16560 struct drm_connector_list_iter conn_iter
;
16562 /* Kill all the work that may have been queued by hpd. */
16563 drm_connector_list_iter_begin(dev
, &conn_iter
);
16564 for_each_intel_connector_iter(connector
, &conn_iter
) {
16565 if (connector
->modeset_retry_work
.func
)
16566 cancel_work_sync(&connector
->modeset_retry_work
);
16567 if (connector
->hdcp
.shim
) {
16568 cancel_delayed_work_sync(&connector
->hdcp
.check_work
);
16569 cancel_work_sync(&connector
->hdcp
.prop_work
);
16572 drm_connector_list_iter_end(&conn_iter
);
16575 void intel_modeset_cleanup(struct drm_device
*dev
)
16577 struct drm_i915_private
*dev_priv
= to_i915(dev
);
16579 flush_workqueue(dev_priv
->modeset_wq
);
16581 flush_work(&dev_priv
->atomic_helper
.free_work
);
16582 WARN_ON(!llist_empty(&dev_priv
->atomic_helper
.free_list
));
16585 * Interrupts and polling as the first thing to avoid creating havoc.
16586 * Too much stuff here (turning of connectors, ...) would
16587 * experience fancy races otherwise.
16589 intel_irq_uninstall(dev_priv
);
16592 * Due to the hpd irq storm handling the hotplug work can re-arm the
16593 * poll handlers. Hence disable polling after hpd handling is shut down.
16595 intel_hpd_poll_fini(dev
);
16597 /* poll work can call into fbdev, hence clean that up afterwards */
16598 intel_fbdev_fini(dev_priv
);
16600 intel_unregister_dsm_handler();
16602 intel_fbc_global_disable(dev_priv
);
16604 /* flush any delayed tasks or pending work */
16605 flush_scheduled_work();
16607 intel_hdcp_component_fini(dev_priv
);
16609 drm_mode_config_cleanup(dev
);
16611 intel_overlay_cleanup(dev_priv
);
16613 intel_teardown_gmbus(dev_priv
);
16615 destroy_workqueue(dev_priv
->modeset_wq
);
16617 intel_fbc_cleanup_cfb(dev_priv
);
16621 * set vga decode state - true == enable VGA decode
16623 int intel_modeset_vga_set_state(struct drm_i915_private
*dev_priv
, bool state
)
16625 unsigned reg
= INTEL_GEN(dev_priv
) >= 6 ? SNB_GMCH_CTRL
: INTEL_GMCH_CTRL
;
16628 if (pci_read_config_word(dev_priv
->bridge_dev
, reg
, &gmch_ctrl
)) {
16629 DRM_ERROR("failed to read control word\n");
16633 if (!!(gmch_ctrl
& INTEL_GMCH_VGA_DISABLE
) == !state
)
16637 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
16639 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
16641 if (pci_write_config_word(dev_priv
->bridge_dev
, reg
, gmch_ctrl
)) {
16642 DRM_ERROR("failed to write control word\n");
16649 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
16651 struct intel_display_error_state
{
16653 u32 power_well_driver
;
16655 struct intel_cursor_error_state
{
16660 } cursor
[I915_MAX_PIPES
];
16662 struct intel_pipe_error_state
{
16663 bool power_domain_on
;
16666 } pipe
[I915_MAX_PIPES
];
16668 struct intel_plane_error_state
{
16676 } plane
[I915_MAX_PIPES
];
16678 struct intel_transcoder_error_state
{
16680 bool power_domain_on
;
16681 enum transcoder cpu_transcoder
;
16694 struct intel_display_error_state
*
16695 intel_display_capture_error_state(struct drm_i915_private
*dev_priv
)
16697 struct intel_display_error_state
*error
;
16698 int transcoders
[] = {
16706 BUILD_BUG_ON(ARRAY_SIZE(transcoders
) != ARRAY_SIZE(error
->transcoder
));
16708 if (!HAS_DISPLAY(dev_priv
))
16711 error
= kzalloc(sizeof(*error
), GFP_ATOMIC
);
16715 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
16716 error
->power_well_driver
= I915_READ(HSW_PWR_WELL_CTL2
);
16718 for_each_pipe(dev_priv
, i
) {
16719 error
->pipe
[i
].power_domain_on
=
16720 __intel_display_power_is_enabled(dev_priv
,
16721 POWER_DOMAIN_PIPE(i
));
16722 if (!error
->pipe
[i
].power_domain_on
)
16725 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
16726 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
16727 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
16729 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
16730 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
16731 if (INTEL_GEN(dev_priv
) <= 3) {
16732 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
16733 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
16735 if (INTEL_GEN(dev_priv
) <= 7 && !IS_HASWELL(dev_priv
))
16736 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
16737 if (INTEL_GEN(dev_priv
) >= 4) {
16738 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
16739 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
16742 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
16744 if (HAS_GMCH(dev_priv
))
16745 error
->pipe
[i
].stat
= I915_READ(PIPESTAT(i
));
16748 for (i
= 0; i
< ARRAY_SIZE(error
->transcoder
); i
++) {
16749 enum transcoder cpu_transcoder
= transcoders
[i
];
16751 if (!INTEL_INFO(dev_priv
)->trans_offsets
[cpu_transcoder
])
16754 error
->transcoder
[i
].available
= true;
16755 error
->transcoder
[i
].power_domain_on
=
16756 __intel_display_power_is_enabled(dev_priv
,
16757 POWER_DOMAIN_TRANSCODER(cpu_transcoder
));
16758 if (!error
->transcoder
[i
].power_domain_on
)
16761 error
->transcoder
[i
].cpu_transcoder
= cpu_transcoder
;
16763 error
->transcoder
[i
].conf
= I915_READ(PIPECONF(cpu_transcoder
));
16764 error
->transcoder
[i
].htotal
= I915_READ(HTOTAL(cpu_transcoder
));
16765 error
->transcoder
[i
].hblank
= I915_READ(HBLANK(cpu_transcoder
));
16766 error
->transcoder
[i
].hsync
= I915_READ(HSYNC(cpu_transcoder
));
16767 error
->transcoder
[i
].vtotal
= I915_READ(VTOTAL(cpu_transcoder
));
16768 error
->transcoder
[i
].vblank
= I915_READ(VBLANK(cpu_transcoder
));
16769 error
->transcoder
[i
].vsync
= I915_READ(VSYNC(cpu_transcoder
));
16775 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
16778 intel_display_print_error_state(struct drm_i915_error_state_buf
*m
,
16779 struct intel_display_error_state
*error
)
16781 struct drm_i915_private
*dev_priv
= m
->i915
;
16787 err_printf(m
, "Num Pipes: %d\n", INTEL_INFO(dev_priv
)->num_pipes
);
16788 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
16789 err_printf(m
, "PWR_WELL_CTL2: %08x\n",
16790 error
->power_well_driver
);
16791 for_each_pipe(dev_priv
, i
) {
16792 err_printf(m
, "Pipe [%d]:\n", i
);
16793 err_printf(m
, " Power: %s\n",
16794 onoff(error
->pipe
[i
].power_domain_on
));
16795 err_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
16796 err_printf(m
, " STAT: %08x\n", error
->pipe
[i
].stat
);
16798 err_printf(m
, "Plane [%d]:\n", i
);
16799 err_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
16800 err_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
16801 if (INTEL_GEN(dev_priv
) <= 3) {
16802 err_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
16803 err_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
16805 if (INTEL_GEN(dev_priv
) <= 7 && !IS_HASWELL(dev_priv
))
16806 err_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
16807 if (INTEL_GEN(dev_priv
) >= 4) {
16808 err_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
16809 err_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
16812 err_printf(m
, "Cursor [%d]:\n", i
);
16813 err_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
16814 err_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
16815 err_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);
16818 for (i
= 0; i
< ARRAY_SIZE(error
->transcoder
); i
++) {
16819 if (!error
->transcoder
[i
].available
)
16822 err_printf(m
, "CPU transcoder: %s\n",
16823 transcoder_name(error
->transcoder
[i
].cpu_transcoder
));
16824 err_printf(m
, " Power: %s\n",
16825 onoff(error
->transcoder
[i
].power_domain_on
));
16826 err_printf(m
, " CONF: %08x\n", error
->transcoder
[i
].conf
);
16827 err_printf(m
, " HTOTAL: %08x\n", error
->transcoder
[i
].htotal
);
16828 err_printf(m
, " HBLANK: %08x\n", error
->transcoder
[i
].hblank
);
16829 err_printf(m
, " HSYNC: %08x\n", error
->transcoder
[i
].hsync
);
16830 err_printf(m
, " VTOTAL: %08x\n", error
->transcoder
[i
].vtotal
);
16831 err_printf(m
, " VBLANK: %08x\n", error
->transcoder
[i
].vblank
);
16832 err_printf(m
, " VSYNC: %08x\n", error
->transcoder
[i
].vsync
);