2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/i2c.h>
28 #include <linux/input.h>
29 #include <linux/intel-iommu.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/reservation.h>
33 #include <linux/slab.h>
34 #include <linux/vgaarb.h>
36 #include <drm/drm_atomic.h>
37 #include <drm/drm_atomic_helper.h>
38 #include <drm/drm_atomic_uapi.h>
39 #include <drm/drm_dp_helper.h>
40 #include <drm/drm_edid.h>
41 #include <drm/drm_fourcc.h>
42 #include <drm/drm_plane_helper.h>
43 #include <drm/drm_probe_helper.h>
44 #include <drm/drm_rect.h>
45 #include <drm/i915_drm.h>
48 #include "i915_gem_clflush.h"
49 #include "i915_reset.h"
50 #include "i915_trace.h"
51 #include "intel_atomic_plane.h"
52 #include "intel_color.h"
53 #include "intel_cdclk.h"
54 #include "intel_crt.h"
55 #include "intel_ddi.h"
57 #include "intel_drv.h"
58 #include "intel_dsi.h"
59 #include "intel_dvo.h"
60 #include "intel_fbc.h"
61 #include "intel_fbdev.h"
62 #include "intel_frontbuffer.h"
63 #include "intel_hdcp.h"
64 #include "intel_hdmi.h"
65 #include "intel_lvds.h"
66 #include "intel_pipe_crc.h"
68 #include "intel_psr.h"
69 #include "intel_sdvo.h"
70 #include "intel_sprite.h"
73 /* Primary plane formats for gen <= 3 */
74 static const u32 i8xx_primary_formats
[] = {
81 /* Primary plane formats for gen >= 4 */
82 static const u32 i965_primary_formats
[] = {
87 DRM_FORMAT_XRGB2101010
,
88 DRM_FORMAT_XBGR2101010
,
91 static const u64 i9xx_format_modifiers
[] = {
92 I915_FORMAT_MOD_X_TILED
,
93 DRM_FORMAT_MOD_LINEAR
,
94 DRM_FORMAT_MOD_INVALID
98 static const u32 intel_cursor_formats
[] = {
102 static const u64 cursor_format_modifiers
[] = {
103 DRM_FORMAT_MOD_LINEAR
,
104 DRM_FORMAT_MOD_INVALID
107 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
108 struct intel_crtc_state
*pipe_config
);
109 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
110 struct intel_crtc_state
*pipe_config
);
112 static int intel_framebuffer_init(struct intel_framebuffer
*ifb
,
113 struct drm_i915_gem_object
*obj
,
114 struct drm_mode_fb_cmd2
*mode_cmd
);
115 static void intel_set_pipe_timings(const struct intel_crtc_state
*crtc_state
);
116 static void intel_set_pipe_src_size(const struct intel_crtc_state
*crtc_state
);
117 static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state
*crtc_state
,
118 const struct intel_link_m_n
*m_n
,
119 const struct intel_link_m_n
*m2_n2
);
120 static void i9xx_set_pipeconf(const struct intel_crtc_state
*crtc_state
);
121 static void ironlake_set_pipeconf(const struct intel_crtc_state
*crtc_state
);
122 static void haswell_set_pipeconf(const struct intel_crtc_state
*crtc_state
);
123 static void haswell_set_pipemisc(const struct intel_crtc_state
*crtc_state
);
124 static void vlv_prepare_pll(struct intel_crtc
*crtc
,
125 const struct intel_crtc_state
*pipe_config
);
126 static void chv_prepare_pll(struct intel_crtc
*crtc
,
127 const struct intel_crtc_state
*pipe_config
);
128 static void intel_begin_crtc_commit(struct intel_atomic_state
*, struct intel_crtc
*);
129 static void intel_finish_crtc_commit(struct intel_atomic_state
*, struct intel_crtc
*);
130 static void intel_crtc_init_scalers(struct intel_crtc
*crtc
,
131 struct intel_crtc_state
*crtc_state
);
132 static void skylake_pfit_enable(const struct intel_crtc_state
*crtc_state
);
133 static void ironlake_pfit_disable(const struct intel_crtc_state
*old_crtc_state
);
134 static void ironlake_pfit_enable(const struct intel_crtc_state
*crtc_state
);
135 static void intel_modeset_setup_hw_state(struct drm_device
*dev
,
136 struct drm_modeset_acquire_ctx
*ctx
);
137 static void intel_pre_disable_primary_noatomic(struct drm_crtc
*crtc
);
142 } dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
146 int p2_slow
, p2_fast
;
150 /* returns HPLL frequency in kHz */
151 int vlv_get_hpll_vco(struct drm_i915_private
*dev_priv
)
153 int hpll_freq
, vco_freq
[] = { 800, 1600, 2000, 2400 };
155 /* Obtain SKU information */
156 mutex_lock(&dev_priv
->sb_lock
);
157 hpll_freq
= vlv_cck_read(dev_priv
, CCK_FUSE_REG
) &
158 CCK_FUSE_HPLL_FREQ_MASK
;
159 mutex_unlock(&dev_priv
->sb_lock
);
161 return vco_freq
[hpll_freq
] * 1000;
164 int vlv_get_cck_clock(struct drm_i915_private
*dev_priv
,
165 const char *name
, u32 reg
, int ref_freq
)
170 mutex_lock(&dev_priv
->sb_lock
);
171 val
= vlv_cck_read(dev_priv
, reg
);
172 mutex_unlock(&dev_priv
->sb_lock
);
174 divider
= val
& CCK_FREQUENCY_VALUES
;
176 WARN((val
& CCK_FREQUENCY_STATUS
) !=
177 (divider
<< CCK_FREQUENCY_STATUS_SHIFT
),
178 "%s change in progress\n", name
);
180 return DIV_ROUND_CLOSEST(ref_freq
<< 1, divider
+ 1);
183 int vlv_get_cck_clock_hpll(struct drm_i915_private
*dev_priv
,
184 const char *name
, u32 reg
)
186 if (dev_priv
->hpll_freq
== 0)
187 dev_priv
->hpll_freq
= vlv_get_hpll_vco(dev_priv
);
189 return vlv_get_cck_clock(dev_priv
, name
, reg
,
190 dev_priv
->hpll_freq
);
193 static void intel_update_czclk(struct drm_i915_private
*dev_priv
)
195 if (!(IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)))
198 dev_priv
->czclk_freq
= vlv_get_cck_clock_hpll(dev_priv
, "czclk",
199 CCK_CZ_CLOCK_CONTROL
);
201 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv
->czclk_freq
);
204 static inline u32
/* units of 100MHz */
205 intel_fdi_link_freq(struct drm_i915_private
*dev_priv
,
206 const struct intel_crtc_state
*pipe_config
)
208 if (HAS_DDI(dev_priv
))
209 return pipe_config
->port_clock
; /* SPLL */
211 return dev_priv
->fdi_pll_freq
;
214 static const struct intel_limit intel_limits_i8xx_dac
= {
215 .dot
= { .min
= 25000, .max
= 350000 },
216 .vco
= { .min
= 908000, .max
= 1512000 },
217 .n
= { .min
= 2, .max
= 16 },
218 .m
= { .min
= 96, .max
= 140 },
219 .m1
= { .min
= 18, .max
= 26 },
220 .m2
= { .min
= 6, .max
= 16 },
221 .p
= { .min
= 4, .max
= 128 },
222 .p1
= { .min
= 2, .max
= 33 },
223 .p2
= { .dot_limit
= 165000,
224 .p2_slow
= 4, .p2_fast
= 2 },
227 static const struct intel_limit intel_limits_i8xx_dvo
= {
228 .dot
= { .min
= 25000, .max
= 350000 },
229 .vco
= { .min
= 908000, .max
= 1512000 },
230 .n
= { .min
= 2, .max
= 16 },
231 .m
= { .min
= 96, .max
= 140 },
232 .m1
= { .min
= 18, .max
= 26 },
233 .m2
= { .min
= 6, .max
= 16 },
234 .p
= { .min
= 4, .max
= 128 },
235 .p1
= { .min
= 2, .max
= 33 },
236 .p2
= { .dot_limit
= 165000,
237 .p2_slow
= 4, .p2_fast
= 4 },
240 static const struct intel_limit intel_limits_i8xx_lvds
= {
241 .dot
= { .min
= 25000, .max
= 350000 },
242 .vco
= { .min
= 908000, .max
= 1512000 },
243 .n
= { .min
= 2, .max
= 16 },
244 .m
= { .min
= 96, .max
= 140 },
245 .m1
= { .min
= 18, .max
= 26 },
246 .m2
= { .min
= 6, .max
= 16 },
247 .p
= { .min
= 4, .max
= 128 },
248 .p1
= { .min
= 1, .max
= 6 },
249 .p2
= { .dot_limit
= 165000,
250 .p2_slow
= 14, .p2_fast
= 7 },
253 static const struct intel_limit intel_limits_i9xx_sdvo
= {
254 .dot
= { .min
= 20000, .max
= 400000 },
255 .vco
= { .min
= 1400000, .max
= 2800000 },
256 .n
= { .min
= 1, .max
= 6 },
257 .m
= { .min
= 70, .max
= 120 },
258 .m1
= { .min
= 8, .max
= 18 },
259 .m2
= { .min
= 3, .max
= 7 },
260 .p
= { .min
= 5, .max
= 80 },
261 .p1
= { .min
= 1, .max
= 8 },
262 .p2
= { .dot_limit
= 200000,
263 .p2_slow
= 10, .p2_fast
= 5 },
266 static const struct intel_limit intel_limits_i9xx_lvds
= {
267 .dot
= { .min
= 20000, .max
= 400000 },
268 .vco
= { .min
= 1400000, .max
= 2800000 },
269 .n
= { .min
= 1, .max
= 6 },
270 .m
= { .min
= 70, .max
= 120 },
271 .m1
= { .min
= 8, .max
= 18 },
272 .m2
= { .min
= 3, .max
= 7 },
273 .p
= { .min
= 7, .max
= 98 },
274 .p1
= { .min
= 1, .max
= 8 },
275 .p2
= { .dot_limit
= 112000,
276 .p2_slow
= 14, .p2_fast
= 7 },
280 static const struct intel_limit intel_limits_g4x_sdvo
= {
281 .dot
= { .min
= 25000, .max
= 270000 },
282 .vco
= { .min
= 1750000, .max
= 3500000},
283 .n
= { .min
= 1, .max
= 4 },
284 .m
= { .min
= 104, .max
= 138 },
285 .m1
= { .min
= 17, .max
= 23 },
286 .m2
= { .min
= 5, .max
= 11 },
287 .p
= { .min
= 10, .max
= 30 },
288 .p1
= { .min
= 1, .max
= 3},
289 .p2
= { .dot_limit
= 270000,
295 static const struct intel_limit intel_limits_g4x_hdmi
= {
296 .dot
= { .min
= 22000, .max
= 400000 },
297 .vco
= { .min
= 1750000, .max
= 3500000},
298 .n
= { .min
= 1, .max
= 4 },
299 .m
= { .min
= 104, .max
= 138 },
300 .m1
= { .min
= 16, .max
= 23 },
301 .m2
= { .min
= 5, .max
= 11 },
302 .p
= { .min
= 5, .max
= 80 },
303 .p1
= { .min
= 1, .max
= 8},
304 .p2
= { .dot_limit
= 165000,
305 .p2_slow
= 10, .p2_fast
= 5 },
308 static const struct intel_limit intel_limits_g4x_single_channel_lvds
= {
309 .dot
= { .min
= 20000, .max
= 115000 },
310 .vco
= { .min
= 1750000, .max
= 3500000 },
311 .n
= { .min
= 1, .max
= 3 },
312 .m
= { .min
= 104, .max
= 138 },
313 .m1
= { .min
= 17, .max
= 23 },
314 .m2
= { .min
= 5, .max
= 11 },
315 .p
= { .min
= 28, .max
= 112 },
316 .p1
= { .min
= 2, .max
= 8 },
317 .p2
= { .dot_limit
= 0,
318 .p2_slow
= 14, .p2_fast
= 14
322 static const struct intel_limit intel_limits_g4x_dual_channel_lvds
= {
323 .dot
= { .min
= 80000, .max
= 224000 },
324 .vco
= { .min
= 1750000, .max
= 3500000 },
325 .n
= { .min
= 1, .max
= 3 },
326 .m
= { .min
= 104, .max
= 138 },
327 .m1
= { .min
= 17, .max
= 23 },
328 .m2
= { .min
= 5, .max
= 11 },
329 .p
= { .min
= 14, .max
= 42 },
330 .p1
= { .min
= 2, .max
= 6 },
331 .p2
= { .dot_limit
= 0,
332 .p2_slow
= 7, .p2_fast
= 7
336 static const struct intel_limit intel_limits_pineview_sdvo
= {
337 .dot
= { .min
= 20000, .max
= 400000},
338 .vco
= { .min
= 1700000, .max
= 3500000 },
339 /* Pineview's Ncounter is a ring counter */
340 .n
= { .min
= 3, .max
= 6 },
341 .m
= { .min
= 2, .max
= 256 },
342 /* Pineview only has one combined m divider, which we treat as m2. */
343 .m1
= { .min
= 0, .max
= 0 },
344 .m2
= { .min
= 0, .max
= 254 },
345 .p
= { .min
= 5, .max
= 80 },
346 .p1
= { .min
= 1, .max
= 8 },
347 .p2
= { .dot_limit
= 200000,
348 .p2_slow
= 10, .p2_fast
= 5 },
351 static const struct intel_limit intel_limits_pineview_lvds
= {
352 .dot
= { .min
= 20000, .max
= 400000 },
353 .vco
= { .min
= 1700000, .max
= 3500000 },
354 .n
= { .min
= 3, .max
= 6 },
355 .m
= { .min
= 2, .max
= 256 },
356 .m1
= { .min
= 0, .max
= 0 },
357 .m2
= { .min
= 0, .max
= 254 },
358 .p
= { .min
= 7, .max
= 112 },
359 .p1
= { .min
= 1, .max
= 8 },
360 .p2
= { .dot_limit
= 112000,
361 .p2_slow
= 14, .p2_fast
= 14 },
364 /* Ironlake / Sandybridge
366 * We calculate clock using (register_value + 2) for N/M1/M2, so here
367 * the range value for them is (actual_value - 2).
369 static const struct intel_limit intel_limits_ironlake_dac
= {
370 .dot
= { .min
= 25000, .max
= 350000 },
371 .vco
= { .min
= 1760000, .max
= 3510000 },
372 .n
= { .min
= 1, .max
= 5 },
373 .m
= { .min
= 79, .max
= 127 },
374 .m1
= { .min
= 12, .max
= 22 },
375 .m2
= { .min
= 5, .max
= 9 },
376 .p
= { .min
= 5, .max
= 80 },
377 .p1
= { .min
= 1, .max
= 8 },
378 .p2
= { .dot_limit
= 225000,
379 .p2_slow
= 10, .p2_fast
= 5 },
382 static const struct intel_limit intel_limits_ironlake_single_lvds
= {
383 .dot
= { .min
= 25000, .max
= 350000 },
384 .vco
= { .min
= 1760000, .max
= 3510000 },
385 .n
= { .min
= 1, .max
= 3 },
386 .m
= { .min
= 79, .max
= 118 },
387 .m1
= { .min
= 12, .max
= 22 },
388 .m2
= { .min
= 5, .max
= 9 },
389 .p
= { .min
= 28, .max
= 112 },
390 .p1
= { .min
= 2, .max
= 8 },
391 .p2
= { .dot_limit
= 225000,
392 .p2_slow
= 14, .p2_fast
= 14 },
395 static const struct intel_limit intel_limits_ironlake_dual_lvds
= {
396 .dot
= { .min
= 25000, .max
= 350000 },
397 .vco
= { .min
= 1760000, .max
= 3510000 },
398 .n
= { .min
= 1, .max
= 3 },
399 .m
= { .min
= 79, .max
= 127 },
400 .m1
= { .min
= 12, .max
= 22 },
401 .m2
= { .min
= 5, .max
= 9 },
402 .p
= { .min
= 14, .max
= 56 },
403 .p1
= { .min
= 2, .max
= 8 },
404 .p2
= { .dot_limit
= 225000,
405 .p2_slow
= 7, .p2_fast
= 7 },
408 /* LVDS 100mhz refclk limits. */
409 static const struct intel_limit intel_limits_ironlake_single_lvds_100m
= {
410 .dot
= { .min
= 25000, .max
= 350000 },
411 .vco
= { .min
= 1760000, .max
= 3510000 },
412 .n
= { .min
= 1, .max
= 2 },
413 .m
= { .min
= 79, .max
= 126 },
414 .m1
= { .min
= 12, .max
= 22 },
415 .m2
= { .min
= 5, .max
= 9 },
416 .p
= { .min
= 28, .max
= 112 },
417 .p1
= { .min
= 2, .max
= 8 },
418 .p2
= { .dot_limit
= 225000,
419 .p2_slow
= 14, .p2_fast
= 14 },
422 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m
= {
423 .dot
= { .min
= 25000, .max
= 350000 },
424 .vco
= { .min
= 1760000, .max
= 3510000 },
425 .n
= { .min
= 1, .max
= 3 },
426 .m
= { .min
= 79, .max
= 126 },
427 .m1
= { .min
= 12, .max
= 22 },
428 .m2
= { .min
= 5, .max
= 9 },
429 .p
= { .min
= 14, .max
= 42 },
430 .p1
= { .min
= 2, .max
= 6 },
431 .p2
= { .dot_limit
= 225000,
432 .p2_slow
= 7, .p2_fast
= 7 },
435 static const struct intel_limit intel_limits_vlv
= {
437 * These are the data rate limits (measured in fast clocks)
438 * since those are the strictest limits we have. The fast
439 * clock and actual rate limits are more relaxed, so checking
440 * them would make no difference.
442 .dot
= { .min
= 25000 * 5, .max
= 270000 * 5 },
443 .vco
= { .min
= 4000000, .max
= 6000000 },
444 .n
= { .min
= 1, .max
= 7 },
445 .m1
= { .min
= 2, .max
= 3 },
446 .m2
= { .min
= 11, .max
= 156 },
447 .p1
= { .min
= 2, .max
= 3 },
448 .p2
= { .p2_slow
= 2, .p2_fast
= 20 }, /* slow=min, fast=max */
451 static const struct intel_limit intel_limits_chv
= {
453 * These are the data rate limits (measured in fast clocks)
454 * since those are the strictest limits we have. The fast
455 * clock and actual rate limits are more relaxed, so checking
456 * them would make no difference.
458 .dot
= { .min
= 25000 * 5, .max
= 540000 * 5},
459 .vco
= { .min
= 4800000, .max
= 6480000 },
460 .n
= { .min
= 1, .max
= 1 },
461 .m1
= { .min
= 2, .max
= 2 },
462 .m2
= { .min
= 24 << 22, .max
= 175 << 22 },
463 .p1
= { .min
= 2, .max
= 4 },
464 .p2
= { .p2_slow
= 1, .p2_fast
= 14 },
467 static const struct intel_limit intel_limits_bxt
= {
468 /* FIXME: find real dot limits */
469 .dot
= { .min
= 0, .max
= INT_MAX
},
470 .vco
= { .min
= 4800000, .max
= 6700000 },
471 .n
= { .min
= 1, .max
= 1 },
472 .m1
= { .min
= 2, .max
= 2 },
473 /* FIXME: find real m2 limits */
474 .m2
= { .min
= 2 << 22, .max
= 255 << 22 },
475 .p1
= { .min
= 2, .max
= 4 },
476 .p2
= { .p2_slow
= 1, .p2_fast
= 20 },
480 skl_wa_827(struct drm_i915_private
*dev_priv
, int pipe
, bool enable
)
483 I915_WRITE(CLKGATE_DIS_PSL(pipe
),
484 I915_READ(CLKGATE_DIS_PSL(pipe
)) |
485 DUPS1_GATING_DIS
| DUPS2_GATING_DIS
);
487 I915_WRITE(CLKGATE_DIS_PSL(pipe
),
488 I915_READ(CLKGATE_DIS_PSL(pipe
)) &
489 ~(DUPS1_GATING_DIS
| DUPS2_GATING_DIS
));
493 needs_modeset(const struct drm_crtc_state
*state
)
495 return drm_atomic_crtc_needs_modeset(state
);
499 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
500 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
501 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
502 * The helpers' return value is the rate of the clock that is fed to the
503 * display engine's pipe which can be the above fast dot clock rate or a
504 * divided-down version of it.
506 /* m1 is reserved as 0 in Pineview, n is a ring counter */
507 static int pnv_calc_dpll_params(int refclk
, struct dpll
*clock
)
509 clock
->m
= clock
->m2
+ 2;
510 clock
->p
= clock
->p1
* clock
->p2
;
511 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
513 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
514 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
519 static u32
i9xx_dpll_compute_m(struct dpll
*dpll
)
521 return 5 * (dpll
->m1
+ 2) + (dpll
->m2
+ 2);
524 static int i9xx_calc_dpll_params(int refclk
, struct dpll
*clock
)
526 clock
->m
= i9xx_dpll_compute_m(clock
);
527 clock
->p
= clock
->p1
* clock
->p2
;
528 if (WARN_ON(clock
->n
+ 2 == 0 || clock
->p
== 0))
530 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
+ 2);
531 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
536 static int vlv_calc_dpll_params(int refclk
, struct dpll
*clock
)
538 clock
->m
= clock
->m1
* clock
->m2
;
539 clock
->p
= clock
->p1
* clock
->p2
;
540 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
542 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
543 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
545 return clock
->dot
/ 5;
548 int chv_calc_dpll_params(int refclk
, struct dpll
*clock
)
550 clock
->m
= clock
->m1
* clock
->m2
;
551 clock
->p
= clock
->p1
* clock
->p2
;
552 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
554 clock
->vco
= DIV_ROUND_CLOSEST_ULL((u64
)refclk
* clock
->m
,
556 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
558 return clock
->dot
/ 5;
561 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
564 * Returns whether the given set of divisors are valid for a given refclk with
565 * the given connectors.
567 static bool intel_PLL_is_valid(struct drm_i915_private
*dev_priv
,
568 const struct intel_limit
*limit
,
569 const struct dpll
*clock
)
571 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
572 INTELPllInvalid("n out of range\n");
573 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
574 INTELPllInvalid("p1 out of range\n");
575 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
576 INTELPllInvalid("m2 out of range\n");
577 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
578 INTELPllInvalid("m1 out of range\n");
580 if (!IS_PINEVIEW(dev_priv
) && !IS_VALLEYVIEW(dev_priv
) &&
581 !IS_CHERRYVIEW(dev_priv
) && !IS_GEN9_LP(dev_priv
))
582 if (clock
->m1
<= clock
->m2
)
583 INTELPllInvalid("m1 <= m2\n");
585 if (!IS_VALLEYVIEW(dev_priv
) && !IS_CHERRYVIEW(dev_priv
) &&
586 !IS_GEN9_LP(dev_priv
)) {
587 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
588 INTELPllInvalid("p out of range\n");
589 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
590 INTELPllInvalid("m out of range\n");
593 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
594 INTELPllInvalid("vco out of range\n");
595 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
596 * connector, etc., rather than just a single range.
598 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
599 INTELPllInvalid("dot out of range\n");
605 i9xx_select_p2_div(const struct intel_limit
*limit
,
606 const struct intel_crtc_state
*crtc_state
,
609 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->base
.crtc
->dev
);
611 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
613 * For LVDS just rely on its current settings for dual-channel.
614 * We haven't figured out how to reliably set up different
615 * single/dual channel state, if we even can.
617 if (intel_is_dual_link_lvds(dev_priv
))
618 return limit
->p2
.p2_fast
;
620 return limit
->p2
.p2_slow
;
622 if (target
< limit
->p2
.dot_limit
)
623 return limit
->p2
.p2_slow
;
625 return limit
->p2
.p2_fast
;
630 * Returns a set of divisors for the desired target clock with the given
631 * refclk, or FALSE. The returned values represent the clock equation:
632 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
634 * Target and reference clocks are specified in kHz.
636 * If match_clock is provided, then best_clock P divider must match the P
637 * divider from @match_clock used for LVDS downclocking.
640 i9xx_find_best_dpll(const struct intel_limit
*limit
,
641 struct intel_crtc_state
*crtc_state
,
642 int target
, int refclk
, struct dpll
*match_clock
,
643 struct dpll
*best_clock
)
645 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
649 memset(best_clock
, 0, sizeof(*best_clock
));
651 clock
.p2
= i9xx_select_p2_div(limit
, crtc_state
, target
);
653 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
655 for (clock
.m2
= limit
->m2
.min
;
656 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
657 if (clock
.m2
>= clock
.m1
)
659 for (clock
.n
= limit
->n
.min
;
660 clock
.n
<= limit
->n
.max
; clock
.n
++) {
661 for (clock
.p1
= limit
->p1
.min
;
662 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
665 i9xx_calc_dpll_params(refclk
, &clock
);
666 if (!intel_PLL_is_valid(to_i915(dev
),
671 clock
.p
!= match_clock
->p
)
674 this_err
= abs(clock
.dot
- target
);
675 if (this_err
< err
) {
684 return (err
!= target
);
688 * Returns a set of divisors for the desired target clock with the given
689 * refclk, or FALSE. The returned values represent the clock equation:
690 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
692 * Target and reference clocks are specified in kHz.
694 * If match_clock is provided, then best_clock P divider must match the P
695 * divider from @match_clock used for LVDS downclocking.
698 pnv_find_best_dpll(const struct intel_limit
*limit
,
699 struct intel_crtc_state
*crtc_state
,
700 int target
, int refclk
, struct dpll
*match_clock
,
701 struct dpll
*best_clock
)
703 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
707 memset(best_clock
, 0, sizeof(*best_clock
));
709 clock
.p2
= i9xx_select_p2_div(limit
, crtc_state
, target
);
711 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
713 for (clock
.m2
= limit
->m2
.min
;
714 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
715 for (clock
.n
= limit
->n
.min
;
716 clock
.n
<= limit
->n
.max
; clock
.n
++) {
717 for (clock
.p1
= limit
->p1
.min
;
718 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
721 pnv_calc_dpll_params(refclk
, &clock
);
722 if (!intel_PLL_is_valid(to_i915(dev
),
727 clock
.p
!= match_clock
->p
)
730 this_err
= abs(clock
.dot
- target
);
731 if (this_err
< err
) {
740 return (err
!= target
);
744 * Returns a set of divisors for the desired target clock with the given
745 * refclk, or FALSE. The returned values represent the clock equation:
746 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
748 * Target and reference clocks are specified in kHz.
750 * If match_clock is provided, then best_clock P divider must match the P
751 * divider from @match_clock used for LVDS downclocking.
754 g4x_find_best_dpll(const struct intel_limit
*limit
,
755 struct intel_crtc_state
*crtc_state
,
756 int target
, int refclk
, struct dpll
*match_clock
,
757 struct dpll
*best_clock
)
759 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
763 /* approximately equals target * 0.00585 */
764 int err_most
= (target
>> 8) + (target
>> 9);
766 memset(best_clock
, 0, sizeof(*best_clock
));
768 clock
.p2
= i9xx_select_p2_div(limit
, crtc_state
, target
);
770 max_n
= limit
->n
.max
;
771 /* based on hardware requirement, prefer smaller n to precision */
772 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
773 /* based on hardware requirement, prefere larger m1,m2 */
774 for (clock
.m1
= limit
->m1
.max
;
775 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
776 for (clock
.m2
= limit
->m2
.max
;
777 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
778 for (clock
.p1
= limit
->p1
.max
;
779 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
782 i9xx_calc_dpll_params(refclk
, &clock
);
783 if (!intel_PLL_is_valid(to_i915(dev
),
788 this_err
= abs(clock
.dot
- target
);
789 if (this_err
< err_most
) {
803 * Check if the calculated PLL configuration is more optimal compared to the
804 * best configuration and error found so far. Return the calculated error.
806 static bool vlv_PLL_is_optimal(struct drm_device
*dev
, int target_freq
,
807 const struct dpll
*calculated_clock
,
808 const struct dpll
*best_clock
,
809 unsigned int best_error_ppm
,
810 unsigned int *error_ppm
)
813 * For CHV ignore the error and consider only the P value.
814 * Prefer a bigger P value based on HW requirements.
816 if (IS_CHERRYVIEW(to_i915(dev
))) {
819 return calculated_clock
->p
> best_clock
->p
;
822 if (WARN_ON_ONCE(!target_freq
))
825 *error_ppm
= div_u64(1000000ULL *
826 abs(target_freq
- calculated_clock
->dot
),
829 * Prefer a better P value over a better (smaller) error if the error
830 * is small. Ensure this preference for future configurations too by
831 * setting the error to 0.
833 if (*error_ppm
< 100 && calculated_clock
->p
> best_clock
->p
) {
839 return *error_ppm
+ 10 < best_error_ppm
;
843 * Returns a set of divisors for the desired target clock with the given
844 * refclk, or FALSE. The returned values represent the clock equation:
845 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
848 vlv_find_best_dpll(const struct intel_limit
*limit
,
849 struct intel_crtc_state
*crtc_state
,
850 int target
, int refclk
, struct dpll
*match_clock
,
851 struct dpll
*best_clock
)
853 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
854 struct drm_device
*dev
= crtc
->base
.dev
;
856 unsigned int bestppm
= 1000000;
857 /* min update 19.2 MHz */
858 int max_n
= min(limit
->n
.max
, refclk
/ 19200);
861 target
*= 5; /* fast clock */
863 memset(best_clock
, 0, sizeof(*best_clock
));
865 /* based on hardware requirement, prefer smaller n to precision */
866 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
867 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
868 for (clock
.p2
= limit
->p2
.p2_fast
; clock
.p2
>= limit
->p2
.p2_slow
;
869 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
870 clock
.p
= clock
.p1
* clock
.p2
;
871 /* based on hardware requirement, prefer bigger m1,m2 values */
872 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
; clock
.m1
++) {
875 clock
.m2
= DIV_ROUND_CLOSEST(target
* clock
.p
* clock
.n
,
878 vlv_calc_dpll_params(refclk
, &clock
);
880 if (!intel_PLL_is_valid(to_i915(dev
),
885 if (!vlv_PLL_is_optimal(dev
, target
,
903 * Returns a set of divisors for the desired target clock with the given
904 * refclk, or FALSE. The returned values represent the clock equation:
905 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
908 chv_find_best_dpll(const struct intel_limit
*limit
,
909 struct intel_crtc_state
*crtc_state
,
910 int target
, int refclk
, struct dpll
*match_clock
,
911 struct dpll
*best_clock
)
913 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
914 struct drm_device
*dev
= crtc
->base
.dev
;
915 unsigned int best_error_ppm
;
920 memset(best_clock
, 0, sizeof(*best_clock
));
921 best_error_ppm
= 1000000;
924 * Based on hardware doc, the n always set to 1, and m1 always
925 * set to 2. If requires to support 200Mhz refclk, we need to
926 * revisit this because n may not 1 anymore.
928 clock
.n
= 1, clock
.m1
= 2;
929 target
*= 5; /* fast clock */
931 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
932 for (clock
.p2
= limit
->p2
.p2_fast
;
933 clock
.p2
>= limit
->p2
.p2_slow
;
934 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
935 unsigned int error_ppm
;
937 clock
.p
= clock
.p1
* clock
.p2
;
939 m2
= DIV_ROUND_CLOSEST_ULL(((u64
)target
* clock
.p
*
940 clock
.n
) << 22, refclk
* clock
.m1
);
942 if (m2
> INT_MAX
/clock
.m1
)
947 chv_calc_dpll_params(refclk
, &clock
);
949 if (!intel_PLL_is_valid(to_i915(dev
), limit
, &clock
))
952 if (!vlv_PLL_is_optimal(dev
, target
, &clock
, best_clock
,
953 best_error_ppm
, &error_ppm
))
957 best_error_ppm
= error_ppm
;
965 bool bxt_find_best_dpll(struct intel_crtc_state
*crtc_state
,
966 struct dpll
*best_clock
)
969 const struct intel_limit
*limit
= &intel_limits_bxt
;
971 return chv_find_best_dpll(limit
, crtc_state
,
972 crtc_state
->port_clock
, refclk
,
976 bool intel_crtc_active(struct intel_crtc
*crtc
)
978 /* Be paranoid as we can arrive here with only partial
979 * state retrieved from the hardware during setup.
981 * We can ditch the adjusted_mode.crtc_clock check as soon
982 * as Haswell has gained clock readout/fastboot support.
984 * We can ditch the crtc->primary->state->fb check as soon as we can
985 * properly reconstruct framebuffers.
987 * FIXME: The intel_crtc->active here should be switched to
988 * crtc->state->active once we have proper CRTC states wired up
991 return crtc
->active
&& crtc
->base
.primary
->state
->fb
&&
992 crtc
->config
->base
.adjusted_mode
.crtc_clock
;
995 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
998 struct intel_crtc
*crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
1000 return crtc
->config
->cpu_transcoder
;
1003 static bool pipe_scanline_is_moving(struct drm_i915_private
*dev_priv
,
1006 i915_reg_t reg
= PIPEDSL(pipe
);
1010 if (IS_GEN(dev_priv
, 2))
1011 line_mask
= DSL_LINEMASK_GEN2
;
1013 line_mask
= DSL_LINEMASK_GEN3
;
1015 line1
= I915_READ(reg
) & line_mask
;
1017 line2
= I915_READ(reg
) & line_mask
;
1019 return line1
!= line2
;
1022 static void wait_for_pipe_scanline_moving(struct intel_crtc
*crtc
, bool state
)
1024 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1025 enum pipe pipe
= crtc
->pipe
;
1027 /* Wait for the display line to settle/start moving */
1028 if (wait_for(pipe_scanline_is_moving(dev_priv
, pipe
) == state
, 100))
1029 DRM_ERROR("pipe %c scanline %s wait timed out\n",
1030 pipe_name(pipe
), onoff(state
));
1033 static void intel_wait_for_pipe_scanline_stopped(struct intel_crtc
*crtc
)
1035 wait_for_pipe_scanline_moving(crtc
, false);
1038 static void intel_wait_for_pipe_scanline_moving(struct intel_crtc
*crtc
)
1040 wait_for_pipe_scanline_moving(crtc
, true);
1044 intel_wait_for_pipe_off(const struct intel_crtc_state
*old_crtc_state
)
1046 struct intel_crtc
*crtc
= to_intel_crtc(old_crtc_state
->base
.crtc
);
1047 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1049 if (INTEL_GEN(dev_priv
) >= 4) {
1050 enum transcoder cpu_transcoder
= old_crtc_state
->cpu_transcoder
;
1051 i915_reg_t reg
= PIPECONF(cpu_transcoder
);
1053 /* Wait for the Pipe State to go off */
1054 if (intel_wait_for_register(&dev_priv
->uncore
,
1055 reg
, I965_PIPECONF_ACTIVE
, 0,
1057 WARN(1, "pipe_off wait timed out\n");
1059 intel_wait_for_pipe_scanline_stopped(crtc
);
1063 /* Only for pre-ILK configs */
1064 void assert_pll(struct drm_i915_private
*dev_priv
,
1065 enum pipe pipe
, bool state
)
1070 val
= I915_READ(DPLL(pipe
));
1071 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1072 I915_STATE_WARN(cur_state
!= state
,
1073 "PLL state assertion failure (expected %s, current %s)\n",
1074 onoff(state
), onoff(cur_state
));
1077 /* XXX: the dsi pll is shared between MIPI DSI ports */
1078 void assert_dsi_pll(struct drm_i915_private
*dev_priv
, bool state
)
1083 mutex_lock(&dev_priv
->sb_lock
);
1084 val
= vlv_cck_read(dev_priv
, CCK_REG_DSI_PLL_CONTROL
);
1085 mutex_unlock(&dev_priv
->sb_lock
);
1087 cur_state
= val
& DSI_PLL_VCO_EN
;
1088 I915_STATE_WARN(cur_state
!= state
,
1089 "DSI PLL state assertion failure (expected %s, current %s)\n",
1090 onoff(state
), onoff(cur_state
));
1093 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
1094 enum pipe pipe
, bool state
)
1097 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1100 if (HAS_DDI(dev_priv
)) {
1101 /* DDI does not have a specific FDI_TX register */
1102 u32 val
= I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder
));
1103 cur_state
= !!(val
& TRANS_DDI_FUNC_ENABLE
);
1105 u32 val
= I915_READ(FDI_TX_CTL(pipe
));
1106 cur_state
= !!(val
& FDI_TX_ENABLE
);
1108 I915_STATE_WARN(cur_state
!= state
,
1109 "FDI TX state assertion failure (expected %s, current %s)\n",
1110 onoff(state
), onoff(cur_state
));
1112 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1113 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1115 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
1116 enum pipe pipe
, bool state
)
1121 val
= I915_READ(FDI_RX_CTL(pipe
));
1122 cur_state
= !!(val
& FDI_RX_ENABLE
);
1123 I915_STATE_WARN(cur_state
!= state
,
1124 "FDI RX state assertion failure (expected %s, current %s)\n",
1125 onoff(state
), onoff(cur_state
));
1127 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1128 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1130 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
1135 /* ILK FDI PLL is always enabled */
1136 if (IS_GEN(dev_priv
, 5))
1139 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1140 if (HAS_DDI(dev_priv
))
1143 val
= I915_READ(FDI_TX_CTL(pipe
));
1144 I915_STATE_WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1147 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
1148 enum pipe pipe
, bool state
)
1153 val
= I915_READ(FDI_RX_CTL(pipe
));
1154 cur_state
= !!(val
& FDI_RX_PLL_ENABLE
);
1155 I915_STATE_WARN(cur_state
!= state
,
1156 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1157 onoff(state
), onoff(cur_state
));
1160 void assert_panel_unlocked(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1164 enum pipe panel_pipe
= INVALID_PIPE
;
1167 if (WARN_ON(HAS_DDI(dev_priv
)))
1170 if (HAS_PCH_SPLIT(dev_priv
)) {
1173 pp_reg
= PP_CONTROL(0);
1174 port_sel
= I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK
;
1177 case PANEL_PORT_SELECT_LVDS
:
1178 intel_lvds_port_enabled(dev_priv
, PCH_LVDS
, &panel_pipe
);
1180 case PANEL_PORT_SELECT_DPA
:
1181 intel_dp_port_enabled(dev_priv
, DP_A
, PORT_A
, &panel_pipe
);
1183 case PANEL_PORT_SELECT_DPC
:
1184 intel_dp_port_enabled(dev_priv
, PCH_DP_C
, PORT_C
, &panel_pipe
);
1186 case PANEL_PORT_SELECT_DPD
:
1187 intel_dp_port_enabled(dev_priv
, PCH_DP_D
, PORT_D
, &panel_pipe
);
1190 MISSING_CASE(port_sel
);
1193 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
1194 /* presumably write lock depends on pipe, not port select */
1195 pp_reg
= PP_CONTROL(pipe
);
1200 pp_reg
= PP_CONTROL(0);
1201 port_sel
= I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK
;
1203 WARN_ON(port_sel
!= PANEL_PORT_SELECT_LVDS
);
1204 intel_lvds_port_enabled(dev_priv
, LVDS
, &panel_pipe
);
1207 val
= I915_READ(pp_reg
);
1208 if (!(val
& PANEL_POWER_ON
) ||
1209 ((val
& PANEL_UNLOCK_MASK
) == PANEL_UNLOCK_REGS
))
1212 I915_STATE_WARN(panel_pipe
== pipe
&& locked
,
1213 "panel assertion failure, pipe %c regs locked\n",
1217 void assert_pipe(struct drm_i915_private
*dev_priv
,
1218 enum pipe pipe
, bool state
)
1221 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1223 enum intel_display_power_domain power_domain
;
1224 intel_wakeref_t wakeref
;
1226 /* we keep both pipes enabled on 830 */
1227 if (IS_I830(dev_priv
))
1230 power_domain
= POWER_DOMAIN_TRANSCODER(cpu_transcoder
);
1231 wakeref
= intel_display_power_get_if_enabled(dev_priv
, power_domain
);
1233 u32 val
= I915_READ(PIPECONF(cpu_transcoder
));
1234 cur_state
= !!(val
& PIPECONF_ENABLE
);
1236 intel_display_power_put(dev_priv
, power_domain
, wakeref
);
1241 I915_STATE_WARN(cur_state
!= state
,
1242 "pipe %c assertion failure (expected %s, current %s)\n",
1243 pipe_name(pipe
), onoff(state
), onoff(cur_state
));
1246 static void assert_plane(struct intel_plane
*plane
, bool state
)
1251 cur_state
= plane
->get_hw_state(plane
, &pipe
);
1253 I915_STATE_WARN(cur_state
!= state
,
1254 "%s assertion failure (expected %s, current %s)\n",
1255 plane
->base
.name
, onoff(state
), onoff(cur_state
));
1258 #define assert_plane_enabled(p) assert_plane(p, true)
1259 #define assert_plane_disabled(p) assert_plane(p, false)
1261 static void assert_planes_disabled(struct intel_crtc
*crtc
)
1263 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1264 struct intel_plane
*plane
;
1266 for_each_intel_plane_on_crtc(&dev_priv
->drm
, crtc
, plane
)
1267 assert_plane_disabled(plane
);
1270 static void assert_vblank_disabled(struct drm_crtc
*crtc
)
1272 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc
) == 0))
1273 drm_crtc_vblank_put(crtc
);
1276 void assert_pch_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1282 val
= I915_READ(PCH_TRANSCONF(pipe
));
1283 enabled
= !!(val
& TRANS_ENABLE
);
1284 I915_STATE_WARN(enabled
,
1285 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1289 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1290 enum pipe pipe
, enum port port
,
1293 enum pipe port_pipe
;
1296 state
= intel_dp_port_enabled(dev_priv
, dp_reg
, port
, &port_pipe
);
1298 I915_STATE_WARN(state
&& port_pipe
== pipe
,
1299 "PCH DP %c enabled on transcoder %c, should be disabled\n",
1300 port_name(port
), pipe_name(pipe
));
1302 I915_STATE_WARN(HAS_PCH_IBX(dev_priv
) && !state
&& port_pipe
== PIPE_B
,
1303 "IBX PCH DP %c still using transcoder B\n",
1307 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1308 enum pipe pipe
, enum port port
,
1309 i915_reg_t hdmi_reg
)
1311 enum pipe port_pipe
;
1314 state
= intel_sdvo_port_enabled(dev_priv
, hdmi_reg
, &port_pipe
);
1316 I915_STATE_WARN(state
&& port_pipe
== pipe
,
1317 "PCH HDMI %c enabled on transcoder %c, should be disabled\n",
1318 port_name(port
), pipe_name(pipe
));
1320 I915_STATE_WARN(HAS_PCH_IBX(dev_priv
) && !state
&& port_pipe
== PIPE_B
,
1321 "IBX PCH HDMI %c still using transcoder B\n",
1325 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1328 enum pipe port_pipe
;
1330 assert_pch_dp_disabled(dev_priv
, pipe
, PORT_B
, PCH_DP_B
);
1331 assert_pch_dp_disabled(dev_priv
, pipe
, PORT_C
, PCH_DP_C
);
1332 assert_pch_dp_disabled(dev_priv
, pipe
, PORT_D
, PCH_DP_D
);
1334 I915_STATE_WARN(intel_crt_port_enabled(dev_priv
, PCH_ADPA
, &port_pipe
) &&
1336 "PCH VGA enabled on transcoder %c, should be disabled\n",
1339 I915_STATE_WARN(intel_lvds_port_enabled(dev_priv
, PCH_LVDS
, &port_pipe
) &&
1341 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1344 /* PCH SDVOB multiplex with HDMIB */
1345 assert_pch_hdmi_disabled(dev_priv
, pipe
, PORT_B
, PCH_HDMIB
);
1346 assert_pch_hdmi_disabled(dev_priv
, pipe
, PORT_C
, PCH_HDMIC
);
1347 assert_pch_hdmi_disabled(dev_priv
, pipe
, PORT_D
, PCH_HDMID
);
1350 static void _vlv_enable_pll(struct intel_crtc
*crtc
,
1351 const struct intel_crtc_state
*pipe_config
)
1353 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1354 enum pipe pipe
= crtc
->pipe
;
1356 I915_WRITE(DPLL(pipe
), pipe_config
->dpll_hw_state
.dpll
);
1357 POSTING_READ(DPLL(pipe
));
1360 if (intel_wait_for_register(&dev_priv
->uncore
,
1365 DRM_ERROR("DPLL %d failed to lock\n", pipe
);
1368 static void vlv_enable_pll(struct intel_crtc
*crtc
,
1369 const struct intel_crtc_state
*pipe_config
)
1371 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1372 enum pipe pipe
= crtc
->pipe
;
1374 assert_pipe_disabled(dev_priv
, pipe
);
1376 /* PLL is protected by panel, make sure we can write it */
1377 assert_panel_unlocked(dev_priv
, pipe
);
1379 if (pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
)
1380 _vlv_enable_pll(crtc
, pipe_config
);
1382 I915_WRITE(DPLL_MD(pipe
), pipe_config
->dpll_hw_state
.dpll_md
);
1383 POSTING_READ(DPLL_MD(pipe
));
1387 static void _chv_enable_pll(struct intel_crtc
*crtc
,
1388 const struct intel_crtc_state
*pipe_config
)
1390 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1391 enum pipe pipe
= crtc
->pipe
;
1392 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1395 mutex_lock(&dev_priv
->sb_lock
);
1397 /* Enable back the 10bit clock to display controller */
1398 tmp
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1399 tmp
|= DPIO_DCLKP_EN
;
1400 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), tmp
);
1402 mutex_unlock(&dev_priv
->sb_lock
);
1405 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1410 I915_WRITE(DPLL(pipe
), pipe_config
->dpll_hw_state
.dpll
);
1412 /* Check PLL is locked */
1413 if (intel_wait_for_register(&dev_priv
->uncore
,
1414 DPLL(pipe
), DPLL_LOCK_VLV
, DPLL_LOCK_VLV
,
1416 DRM_ERROR("PLL %d failed to lock\n", pipe
);
1419 static void chv_enable_pll(struct intel_crtc
*crtc
,
1420 const struct intel_crtc_state
*pipe_config
)
1422 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1423 enum pipe pipe
= crtc
->pipe
;
1425 assert_pipe_disabled(dev_priv
, pipe
);
1427 /* PLL is protected by panel, make sure we can write it */
1428 assert_panel_unlocked(dev_priv
, pipe
);
1430 if (pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
)
1431 _chv_enable_pll(crtc
, pipe_config
);
1433 if (pipe
!= PIPE_A
) {
1435 * WaPixelRepeatModeFixForC0:chv
1437 * DPLLCMD is AWOL. Use chicken bits to propagate
1438 * the value from DPLLBMD to either pipe B or C.
1440 I915_WRITE(CBR4_VLV
, CBR_DPLLBMD_PIPE(pipe
));
1441 I915_WRITE(DPLL_MD(PIPE_B
), pipe_config
->dpll_hw_state
.dpll_md
);
1442 I915_WRITE(CBR4_VLV
, 0);
1443 dev_priv
->chv_dpll_md
[pipe
] = pipe_config
->dpll_hw_state
.dpll_md
;
1446 * DPLLB VGA mode also seems to cause problems.
1447 * We should always have it disabled.
1449 WARN_ON((I915_READ(DPLL(PIPE_B
)) & DPLL_VGA_MODE_DIS
) == 0);
1451 I915_WRITE(DPLL_MD(pipe
), pipe_config
->dpll_hw_state
.dpll_md
);
1452 POSTING_READ(DPLL_MD(pipe
));
1456 static bool i9xx_has_pps(struct drm_i915_private
*dev_priv
)
1458 if (IS_I830(dev_priv
))
1461 return IS_PINEVIEW(dev_priv
) || IS_MOBILE(dev_priv
);
1464 static void i9xx_enable_pll(struct intel_crtc
*crtc
,
1465 const struct intel_crtc_state
*crtc_state
)
1467 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1468 i915_reg_t reg
= DPLL(crtc
->pipe
);
1469 u32 dpll
= crtc_state
->dpll_hw_state
.dpll
;
1472 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1474 /* PLL is protected by panel, make sure we can write it */
1475 if (i9xx_has_pps(dev_priv
))
1476 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1479 * Apparently we need to have VGA mode enabled prior to changing
1480 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1481 * dividers, even though the register value does change.
1483 I915_WRITE(reg
, dpll
& ~DPLL_VGA_MODE_DIS
);
1484 I915_WRITE(reg
, dpll
);
1486 /* Wait for the clocks to stabilize. */
1490 if (INTEL_GEN(dev_priv
) >= 4) {
1491 I915_WRITE(DPLL_MD(crtc
->pipe
),
1492 crtc_state
->dpll_hw_state
.dpll_md
);
1494 /* The pixel multiplier can only be updated once the
1495 * DPLL is enabled and the clocks are stable.
1497 * So write it again.
1499 I915_WRITE(reg
, dpll
);
1502 /* We do this three times for luck */
1503 for (i
= 0; i
< 3; i
++) {
1504 I915_WRITE(reg
, dpll
);
1506 udelay(150); /* wait for warmup */
1510 static void i9xx_disable_pll(const struct intel_crtc_state
*crtc_state
)
1512 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
1513 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1514 enum pipe pipe
= crtc
->pipe
;
1516 /* Don't disable pipe or pipe PLLs if needed */
1517 if (IS_I830(dev_priv
))
1520 /* Make sure the pipe isn't still relying on us */
1521 assert_pipe_disabled(dev_priv
, pipe
);
1523 I915_WRITE(DPLL(pipe
), DPLL_VGA_MODE_DIS
);
1524 POSTING_READ(DPLL(pipe
));
1527 static void vlv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1531 /* Make sure the pipe isn't still relying on us */
1532 assert_pipe_disabled(dev_priv
, pipe
);
1534 val
= DPLL_INTEGRATED_REF_CLK_VLV
|
1535 DPLL_REF_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
;
1537 val
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
1539 I915_WRITE(DPLL(pipe
), val
);
1540 POSTING_READ(DPLL(pipe
));
1543 static void chv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1545 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1548 /* Make sure the pipe isn't still relying on us */
1549 assert_pipe_disabled(dev_priv
, pipe
);
1551 val
= DPLL_SSC_REF_CLK_CHV
|
1552 DPLL_REF_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
;
1554 val
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
1556 I915_WRITE(DPLL(pipe
), val
);
1557 POSTING_READ(DPLL(pipe
));
1559 mutex_lock(&dev_priv
->sb_lock
);
1561 /* Disable 10bit clock to display controller */
1562 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1563 val
&= ~DPIO_DCLKP_EN
;
1564 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), val
);
1566 mutex_unlock(&dev_priv
->sb_lock
);
1569 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
,
1570 struct intel_digital_port
*dport
,
1571 unsigned int expected_mask
)
1574 i915_reg_t dpll_reg
;
1576 switch (dport
->base
.port
) {
1578 port_mask
= DPLL_PORTB_READY_MASK
;
1582 port_mask
= DPLL_PORTC_READY_MASK
;
1584 expected_mask
<<= 4;
1587 port_mask
= DPLL_PORTD_READY_MASK
;
1588 dpll_reg
= DPIO_PHY_STATUS
;
1594 if (intel_wait_for_register(&dev_priv
->uncore
,
1595 dpll_reg
, port_mask
, expected_mask
,
1597 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1598 port_name(dport
->base
.port
),
1599 I915_READ(dpll_reg
) & port_mask
, expected_mask
);
1602 static void ironlake_enable_pch_transcoder(const struct intel_crtc_state
*crtc_state
)
1604 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
1605 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1606 enum pipe pipe
= crtc
->pipe
;
1608 u32 val
, pipeconf_val
;
1610 /* Make sure PCH DPLL is enabled */
1611 assert_shared_dpll_enabled(dev_priv
, crtc_state
->shared_dpll
);
1613 /* FDI must be feeding us bits for PCH ports */
1614 assert_fdi_tx_enabled(dev_priv
, pipe
);
1615 assert_fdi_rx_enabled(dev_priv
, pipe
);
1617 if (HAS_PCH_CPT(dev_priv
)) {
1618 /* Workaround: Set the timing override bit before enabling the
1619 * pch transcoder. */
1620 reg
= TRANS_CHICKEN2(pipe
);
1621 val
= I915_READ(reg
);
1622 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1623 I915_WRITE(reg
, val
);
1626 reg
= PCH_TRANSCONF(pipe
);
1627 val
= I915_READ(reg
);
1628 pipeconf_val
= I915_READ(PIPECONF(pipe
));
1630 if (HAS_PCH_IBX(dev_priv
)) {
1632 * Make the BPC in transcoder be consistent with
1633 * that in pipeconf reg. For HDMI we must use 8bpc
1634 * here for both 8bpc and 12bpc.
1636 val
&= ~PIPECONF_BPC_MASK
;
1637 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_HDMI
))
1638 val
|= PIPECONF_8BPC
;
1640 val
|= pipeconf_val
& PIPECONF_BPC_MASK
;
1643 val
&= ~TRANS_INTERLACE_MASK
;
1644 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
) {
1645 if (HAS_PCH_IBX(dev_priv
) &&
1646 intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_SDVO
))
1647 val
|= TRANS_LEGACY_INTERLACED_ILK
;
1649 val
|= TRANS_INTERLACED
;
1651 val
|= TRANS_PROGRESSIVE
;
1654 I915_WRITE(reg
, val
| TRANS_ENABLE
);
1655 if (intel_wait_for_register(&dev_priv
->uncore
,
1656 reg
, TRANS_STATE_ENABLE
, TRANS_STATE_ENABLE
,
1658 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe
));
1661 static void lpt_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1662 enum transcoder cpu_transcoder
)
1664 u32 val
, pipeconf_val
;
1666 /* FDI must be feeding us bits for PCH ports */
1667 assert_fdi_tx_enabled(dev_priv
, (enum pipe
) cpu_transcoder
);
1668 assert_fdi_rx_enabled(dev_priv
, PIPE_A
);
1670 /* Workaround: set timing override bit. */
1671 val
= I915_READ(TRANS_CHICKEN2(PIPE_A
));
1672 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1673 I915_WRITE(TRANS_CHICKEN2(PIPE_A
), val
);
1676 pipeconf_val
= I915_READ(PIPECONF(cpu_transcoder
));
1678 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK_HSW
) ==
1679 PIPECONF_INTERLACED_ILK
)
1680 val
|= TRANS_INTERLACED
;
1682 val
|= TRANS_PROGRESSIVE
;
1684 I915_WRITE(LPT_TRANSCONF
, val
);
1685 if (intel_wait_for_register(&dev_priv
->uncore
,
1690 DRM_ERROR("Failed to enable PCH transcoder\n");
1693 static void ironlake_disable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1699 /* FDI relies on the transcoder */
1700 assert_fdi_tx_disabled(dev_priv
, pipe
);
1701 assert_fdi_rx_disabled(dev_priv
, pipe
);
1703 /* Ports must be off as well */
1704 assert_pch_ports_disabled(dev_priv
, pipe
);
1706 reg
= PCH_TRANSCONF(pipe
);
1707 val
= I915_READ(reg
);
1708 val
&= ~TRANS_ENABLE
;
1709 I915_WRITE(reg
, val
);
1710 /* wait for PCH transcoder off, transcoder state */
1711 if (intel_wait_for_register(&dev_priv
->uncore
,
1712 reg
, TRANS_STATE_ENABLE
, 0,
1714 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe
));
1716 if (HAS_PCH_CPT(dev_priv
)) {
1717 /* Workaround: Clear the timing override chicken bit again. */
1718 reg
= TRANS_CHICKEN2(pipe
);
1719 val
= I915_READ(reg
);
1720 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1721 I915_WRITE(reg
, val
);
1725 void lpt_disable_pch_transcoder(struct drm_i915_private
*dev_priv
)
1729 val
= I915_READ(LPT_TRANSCONF
);
1730 val
&= ~TRANS_ENABLE
;
1731 I915_WRITE(LPT_TRANSCONF
, val
);
1732 /* wait for PCH transcoder off, transcoder state */
1733 if (intel_wait_for_register(&dev_priv
->uncore
,
1734 LPT_TRANSCONF
, TRANS_STATE_ENABLE
, 0,
1736 DRM_ERROR("Failed to disable PCH transcoder\n");
1738 /* Workaround: clear timing override bit. */
1739 val
= I915_READ(TRANS_CHICKEN2(PIPE_A
));
1740 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1741 I915_WRITE(TRANS_CHICKEN2(PIPE_A
), val
);
1744 enum pipe
intel_crtc_pch_transcoder(struct intel_crtc
*crtc
)
1746 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1748 if (HAS_PCH_LPT(dev_priv
))
1754 static u32
intel_crtc_max_vblank_count(const struct intel_crtc_state
*crtc_state
)
1756 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->base
.crtc
->dev
);
1759 * On i965gm the hardware frame counter reads
1760 * zero when the TV encoder is enabled :(
1762 if (IS_I965GM(dev_priv
) &&
1763 (crtc_state
->output_types
& BIT(INTEL_OUTPUT_TVOUT
)))
1766 if (INTEL_GEN(dev_priv
) >= 5 || IS_G4X(dev_priv
))
1767 return 0xffffffff; /* full 32 bit counter */
1768 else if (INTEL_GEN(dev_priv
) >= 3)
1769 return 0xffffff; /* only 24 bits of frame count */
1771 return 0; /* Gen2 doesn't have a hardware frame counter */
1774 static void intel_crtc_vblank_on(const struct intel_crtc_state
*crtc_state
)
1776 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
1778 drm_crtc_set_max_vblank_count(&crtc
->base
,
1779 intel_crtc_max_vblank_count(crtc_state
));
1780 drm_crtc_vblank_on(&crtc
->base
);
1783 static void intel_enable_pipe(const struct intel_crtc_state
*new_crtc_state
)
1785 struct intel_crtc
*crtc
= to_intel_crtc(new_crtc_state
->base
.crtc
);
1786 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1787 enum transcoder cpu_transcoder
= new_crtc_state
->cpu_transcoder
;
1788 enum pipe pipe
= crtc
->pipe
;
1792 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe
));
1794 assert_planes_disabled(crtc
);
1797 * A pipe without a PLL won't actually be able to drive bits from
1798 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1801 if (HAS_GMCH(dev_priv
)) {
1802 if (intel_crtc_has_type(new_crtc_state
, INTEL_OUTPUT_DSI
))
1803 assert_dsi_pll_enabled(dev_priv
);
1805 assert_pll_enabled(dev_priv
, pipe
);
1807 if (new_crtc_state
->has_pch_encoder
) {
1808 /* if driving the PCH, we need FDI enabled */
1809 assert_fdi_rx_pll_enabled(dev_priv
,
1810 intel_crtc_pch_transcoder(crtc
));
1811 assert_fdi_tx_pll_enabled(dev_priv
,
1812 (enum pipe
) cpu_transcoder
);
1814 /* FIXME: assert CPU port conditions for SNB+ */
1817 trace_intel_pipe_enable(dev_priv
, pipe
);
1819 reg
= PIPECONF(cpu_transcoder
);
1820 val
= I915_READ(reg
);
1821 if (val
& PIPECONF_ENABLE
) {
1822 /* we keep both pipes enabled on 830 */
1823 WARN_ON(!IS_I830(dev_priv
));
1827 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
1831 * Until the pipe starts PIPEDSL reads will return a stale value,
1832 * which causes an apparent vblank timestamp jump when PIPEDSL
1833 * resets to its proper value. That also messes up the frame count
1834 * when it's derived from the timestamps. So let's wait for the
1835 * pipe to start properly before we call drm_crtc_vblank_on()
1837 if (intel_crtc_max_vblank_count(new_crtc_state
) == 0)
1838 intel_wait_for_pipe_scanline_moving(crtc
);
1841 static void intel_disable_pipe(const struct intel_crtc_state
*old_crtc_state
)
1843 struct intel_crtc
*crtc
= to_intel_crtc(old_crtc_state
->base
.crtc
);
1844 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1845 enum transcoder cpu_transcoder
= old_crtc_state
->cpu_transcoder
;
1846 enum pipe pipe
= crtc
->pipe
;
1850 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe
));
1853 * Make sure planes won't keep trying to pump pixels to us,
1854 * or we might hang the display.
1856 assert_planes_disabled(crtc
);
1858 trace_intel_pipe_disable(dev_priv
, pipe
);
1860 reg
= PIPECONF(cpu_transcoder
);
1861 val
= I915_READ(reg
);
1862 if ((val
& PIPECONF_ENABLE
) == 0)
1866 * Double wide has implications for planes
1867 * so best keep it disabled when not needed.
1869 if (old_crtc_state
->double_wide
)
1870 val
&= ~PIPECONF_DOUBLE_WIDE
;
1872 /* Don't disable pipe or pipe PLLs if needed */
1873 if (!IS_I830(dev_priv
))
1874 val
&= ~PIPECONF_ENABLE
;
1876 I915_WRITE(reg
, val
);
1877 if ((val
& PIPECONF_ENABLE
) == 0)
1878 intel_wait_for_pipe_off(old_crtc_state
);
1881 static unsigned int intel_tile_size(const struct drm_i915_private
*dev_priv
)
1883 return IS_GEN(dev_priv
, 2) ? 2048 : 4096;
1887 intel_tile_width_bytes(const struct drm_framebuffer
*fb
, int color_plane
)
1889 struct drm_i915_private
*dev_priv
= to_i915(fb
->dev
);
1890 unsigned int cpp
= fb
->format
->cpp
[color_plane
];
1892 switch (fb
->modifier
) {
1893 case DRM_FORMAT_MOD_LINEAR
:
1895 case I915_FORMAT_MOD_X_TILED
:
1896 if (IS_GEN(dev_priv
, 2))
1900 case I915_FORMAT_MOD_Y_TILED_CCS
:
1901 if (color_plane
== 1)
1904 case I915_FORMAT_MOD_Y_TILED
:
1905 if (IS_GEN(dev_priv
, 2) || HAS_128_BYTE_Y_TILING(dev_priv
))
1909 case I915_FORMAT_MOD_Yf_TILED_CCS
:
1910 if (color_plane
== 1)
1913 case I915_FORMAT_MOD_Yf_TILED
:
1929 MISSING_CASE(fb
->modifier
);
1935 intel_tile_height(const struct drm_framebuffer
*fb
, int color_plane
)
1937 if (fb
->modifier
== DRM_FORMAT_MOD_LINEAR
)
1940 return intel_tile_size(to_i915(fb
->dev
)) /
1941 intel_tile_width_bytes(fb
, color_plane
);
1944 /* Return the tile dimensions in pixel units */
1945 static void intel_tile_dims(const struct drm_framebuffer
*fb
, int color_plane
,
1946 unsigned int *tile_width
,
1947 unsigned int *tile_height
)
1949 unsigned int tile_width_bytes
= intel_tile_width_bytes(fb
, color_plane
);
1950 unsigned int cpp
= fb
->format
->cpp
[color_plane
];
1952 *tile_width
= tile_width_bytes
/ cpp
;
1953 *tile_height
= intel_tile_size(to_i915(fb
->dev
)) / tile_width_bytes
;
1957 intel_fb_align_height(const struct drm_framebuffer
*fb
,
1958 int color_plane
, unsigned int height
)
1960 unsigned int tile_height
= intel_tile_height(fb
, color_plane
);
1962 return ALIGN(height
, tile_height
);
1965 unsigned int intel_rotation_info_size(const struct intel_rotation_info
*rot_info
)
1967 unsigned int size
= 0;
1970 for (i
= 0 ; i
< ARRAY_SIZE(rot_info
->plane
); i
++)
1971 size
+= rot_info
->plane
[i
].width
* rot_info
->plane
[i
].height
;
1977 intel_fill_fb_ggtt_view(struct i915_ggtt_view
*view
,
1978 const struct drm_framebuffer
*fb
,
1979 unsigned int rotation
)
1981 view
->type
= I915_GGTT_VIEW_NORMAL
;
1982 if (drm_rotation_90_or_270(rotation
)) {
1983 view
->type
= I915_GGTT_VIEW_ROTATED
;
1984 view
->rotated
= to_intel_framebuffer(fb
)->rot_info
;
1988 static unsigned int intel_cursor_alignment(const struct drm_i915_private
*dev_priv
)
1990 if (IS_I830(dev_priv
))
1992 else if (IS_I85X(dev_priv
))
1994 else if (IS_I845G(dev_priv
) || IS_I865G(dev_priv
))
2000 static unsigned int intel_linear_alignment(const struct drm_i915_private
*dev_priv
)
2002 if (INTEL_GEN(dev_priv
) >= 9)
2004 else if (IS_I965G(dev_priv
) || IS_I965GM(dev_priv
) ||
2005 IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
2007 else if (INTEL_GEN(dev_priv
) >= 4)
2013 static unsigned int intel_surf_alignment(const struct drm_framebuffer
*fb
,
2016 struct drm_i915_private
*dev_priv
= to_i915(fb
->dev
);
2018 /* AUX_DIST needs only 4K alignment */
2019 if (color_plane
== 1)
2022 switch (fb
->modifier
) {
2023 case DRM_FORMAT_MOD_LINEAR
:
2024 return intel_linear_alignment(dev_priv
);
2025 case I915_FORMAT_MOD_X_TILED
:
2026 if (INTEL_GEN(dev_priv
) >= 9)
2029 case I915_FORMAT_MOD_Y_TILED_CCS
:
2030 case I915_FORMAT_MOD_Yf_TILED_CCS
:
2031 case I915_FORMAT_MOD_Y_TILED
:
2032 case I915_FORMAT_MOD_Yf_TILED
:
2033 return 1 * 1024 * 1024;
2035 MISSING_CASE(fb
->modifier
);
2040 static bool intel_plane_uses_fence(const struct intel_plane_state
*plane_state
)
2042 struct intel_plane
*plane
= to_intel_plane(plane_state
->base
.plane
);
2043 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
2045 return INTEL_GEN(dev_priv
) < 4 || plane
->has_fbc
;
2049 intel_pin_and_fence_fb_obj(struct drm_framebuffer
*fb
,
2050 const struct i915_ggtt_view
*view
,
2052 unsigned long *out_flags
)
2054 struct drm_device
*dev
= fb
->dev
;
2055 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2056 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2057 intel_wakeref_t wakeref
;
2058 struct i915_vma
*vma
;
2059 unsigned int pinctl
;
2062 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
2064 alignment
= intel_surf_alignment(fb
, 0);
2066 /* Note that the w/a also requires 64 PTE of padding following the
2067 * bo. We currently fill all unused PTE with the shadow page and so
2068 * we should always have valid PTE following the scanout preventing
2071 if (intel_scanout_needs_vtd_wa(dev_priv
) && alignment
< 256 * 1024)
2072 alignment
= 256 * 1024;
2075 * Global gtt pte registers are special registers which actually forward
2076 * writes to a chunk of system memory. Which means that there is no risk
2077 * that the register values disappear as soon as we call
2078 * intel_runtime_pm_put(), so it is correct to wrap only the
2079 * pin/unpin/fence and not more.
2081 wakeref
= intel_runtime_pm_get(dev_priv
);
2083 atomic_inc(&dev_priv
->gpu_error
.pending_fb_pin
);
2087 /* Valleyview is definitely limited to scanning out the first
2088 * 512MiB. Lets presume this behaviour was inherited from the
2089 * g4x display engine and that all earlier gen are similarly
2090 * limited. Testing suggests that it is a little more
2091 * complicated than this. For example, Cherryview appears quite
2092 * happy to scanout from anywhere within its global aperture.
2094 if (HAS_GMCH(dev_priv
))
2095 pinctl
|= PIN_MAPPABLE
;
2097 vma
= i915_gem_object_pin_to_display_plane(obj
,
2098 alignment
, view
, pinctl
);
2102 if (uses_fence
&& i915_vma_is_map_and_fenceable(vma
)) {
2105 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2106 * fence, whereas 965+ only requires a fence if using
2107 * framebuffer compression. For simplicity, we always, when
2108 * possible, install a fence as the cost is not that onerous.
2110 * If we fail to fence the tiled scanout, then either the
2111 * modeset will reject the change (which is highly unlikely as
2112 * the affected systems, all but one, do not have unmappable
2113 * space) or we will not be able to enable full powersaving
2114 * techniques (also likely not to apply due to various limits
2115 * FBC and the like impose on the size of the buffer, which
2116 * presumably we violated anyway with this unmappable buffer).
2117 * Anyway, it is presumably better to stumble onwards with
2118 * something and try to run the system in a "less than optimal"
2119 * mode that matches the user configuration.
2121 ret
= i915_vma_pin_fence(vma
);
2122 if (ret
!= 0 && INTEL_GEN(dev_priv
) < 4) {
2123 i915_gem_object_unpin_from_display_plane(vma
);
2128 if (ret
== 0 && vma
->fence
)
2129 *out_flags
|= PLANE_HAS_FENCE
;
2134 atomic_dec(&dev_priv
->gpu_error
.pending_fb_pin
);
2136 intel_runtime_pm_put(dev_priv
, wakeref
);
2140 void intel_unpin_fb_vma(struct i915_vma
*vma
, unsigned long flags
)
2142 lockdep_assert_held(&vma
->vm
->i915
->drm
.struct_mutex
);
2144 if (flags
& PLANE_HAS_FENCE
)
2145 i915_vma_unpin_fence(vma
);
2146 i915_gem_object_unpin_from_display_plane(vma
);
2150 static int intel_fb_pitch(const struct drm_framebuffer
*fb
, int color_plane
,
2151 unsigned int rotation
)
2153 if (drm_rotation_90_or_270(rotation
))
2154 return to_intel_framebuffer(fb
)->rotated
[color_plane
].pitch
;
2156 return fb
->pitches
[color_plane
];
2160 * Convert the x/y offsets into a linear offset.
2161 * Only valid with 0/180 degree rotation, which is fine since linear
2162 * offset is only used with linear buffers on pre-hsw and tiled buffers
2163 * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2165 u32
intel_fb_xy_to_linear(int x
, int y
,
2166 const struct intel_plane_state
*state
,
2169 const struct drm_framebuffer
*fb
= state
->base
.fb
;
2170 unsigned int cpp
= fb
->format
->cpp
[color_plane
];
2171 unsigned int pitch
= state
->color_plane
[color_plane
].stride
;
2173 return y
* pitch
+ x
* cpp
;
2177 * Add the x/y offsets derived from fb->offsets[] to the user
2178 * specified plane src x/y offsets. The resulting x/y offsets
2179 * specify the start of scanout from the beginning of the gtt mapping.
2181 void intel_add_fb_offsets(int *x
, int *y
,
2182 const struct intel_plane_state
*state
,
2186 const struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(state
->base
.fb
);
2187 unsigned int rotation
= state
->base
.rotation
;
2189 if (drm_rotation_90_or_270(rotation
)) {
2190 *x
+= intel_fb
->rotated
[color_plane
].x
;
2191 *y
+= intel_fb
->rotated
[color_plane
].y
;
2193 *x
+= intel_fb
->normal
[color_plane
].x
;
2194 *y
+= intel_fb
->normal
[color_plane
].y
;
2198 static u32
intel_adjust_tile_offset(int *x
, int *y
,
2199 unsigned int tile_width
,
2200 unsigned int tile_height
,
2201 unsigned int tile_size
,
2202 unsigned int pitch_tiles
,
2206 unsigned int pitch_pixels
= pitch_tiles
* tile_width
;
2209 WARN_ON(old_offset
& (tile_size
- 1));
2210 WARN_ON(new_offset
& (tile_size
- 1));
2211 WARN_ON(new_offset
> old_offset
);
2213 tiles
= (old_offset
- new_offset
) / tile_size
;
2215 *y
+= tiles
/ pitch_tiles
* tile_height
;
2216 *x
+= tiles
% pitch_tiles
* tile_width
;
2218 /* minimize x in case it got needlessly big */
2219 *y
+= *x
/ pitch_pixels
* tile_height
;
2225 static bool is_surface_linear(u64 modifier
, int color_plane
)
2227 return modifier
== DRM_FORMAT_MOD_LINEAR
;
2230 static u32
intel_adjust_aligned_offset(int *x
, int *y
,
2231 const struct drm_framebuffer
*fb
,
2233 unsigned int rotation
,
2235 u32 old_offset
, u32 new_offset
)
2237 struct drm_i915_private
*dev_priv
= to_i915(fb
->dev
);
2238 unsigned int cpp
= fb
->format
->cpp
[color_plane
];
2240 WARN_ON(new_offset
> old_offset
);
2242 if (!is_surface_linear(fb
->modifier
, color_plane
)) {
2243 unsigned int tile_size
, tile_width
, tile_height
;
2244 unsigned int pitch_tiles
;
2246 tile_size
= intel_tile_size(dev_priv
);
2247 intel_tile_dims(fb
, color_plane
, &tile_width
, &tile_height
);
2249 if (drm_rotation_90_or_270(rotation
)) {
2250 pitch_tiles
= pitch
/ tile_height
;
2251 swap(tile_width
, tile_height
);
2253 pitch_tiles
= pitch
/ (tile_width
* cpp
);
2256 intel_adjust_tile_offset(x
, y
, tile_width
, tile_height
,
2257 tile_size
, pitch_tiles
,
2258 old_offset
, new_offset
);
2260 old_offset
+= *y
* pitch
+ *x
* cpp
;
2262 *y
= (old_offset
- new_offset
) / pitch
;
2263 *x
= ((old_offset
- new_offset
) - *y
* pitch
) / cpp
;
2270 * Adjust the tile offset by moving the difference into
2273 static u32
intel_plane_adjust_aligned_offset(int *x
, int *y
,
2274 const struct intel_plane_state
*state
,
2276 u32 old_offset
, u32 new_offset
)
2278 return intel_adjust_aligned_offset(x
, y
, state
->base
.fb
, color_plane
,
2279 state
->base
.rotation
,
2280 state
->color_plane
[color_plane
].stride
,
2281 old_offset
, new_offset
);
2285 * Computes the aligned offset to the base tile and adjusts
2286 * x, y. bytes per pixel is assumed to be a power-of-two.
2288 * In the 90/270 rotated case, x and y are assumed
2289 * to be already rotated to match the rotated GTT view, and
2290 * pitch is the tile_height aligned framebuffer height.
2292 * This function is used when computing the derived information
2293 * under intel_framebuffer, so using any of that information
2294 * here is not allowed. Anything under drm_framebuffer can be
2295 * used. This is why the user has to pass in the pitch since it
2296 * is specified in the rotated orientation.
2298 static u32
intel_compute_aligned_offset(struct drm_i915_private
*dev_priv
,
2300 const struct drm_framebuffer
*fb
,
2303 unsigned int rotation
,
2306 unsigned int cpp
= fb
->format
->cpp
[color_plane
];
2307 u32 offset
, offset_aligned
;
2312 if (!is_surface_linear(fb
->modifier
, color_plane
)) {
2313 unsigned int tile_size
, tile_width
, tile_height
;
2314 unsigned int tile_rows
, tiles
, pitch_tiles
;
2316 tile_size
= intel_tile_size(dev_priv
);
2317 intel_tile_dims(fb
, color_plane
, &tile_width
, &tile_height
);
2319 if (drm_rotation_90_or_270(rotation
)) {
2320 pitch_tiles
= pitch
/ tile_height
;
2321 swap(tile_width
, tile_height
);
2323 pitch_tiles
= pitch
/ (tile_width
* cpp
);
2326 tile_rows
= *y
/ tile_height
;
2329 tiles
= *x
/ tile_width
;
2332 offset
= (tile_rows
* pitch_tiles
+ tiles
) * tile_size
;
2333 offset_aligned
= offset
& ~alignment
;
2335 intel_adjust_tile_offset(x
, y
, tile_width
, tile_height
,
2336 tile_size
, pitch_tiles
,
2337 offset
, offset_aligned
);
2339 offset
= *y
* pitch
+ *x
* cpp
;
2340 offset_aligned
= offset
& ~alignment
;
2342 *y
= (offset
& alignment
) / pitch
;
2343 *x
= ((offset
& alignment
) - *y
* pitch
) / cpp
;
2346 return offset_aligned
;
2349 static u32
intel_plane_compute_aligned_offset(int *x
, int *y
,
2350 const struct intel_plane_state
*state
,
2353 struct intel_plane
*intel_plane
= to_intel_plane(state
->base
.plane
);
2354 struct drm_i915_private
*dev_priv
= to_i915(intel_plane
->base
.dev
);
2355 const struct drm_framebuffer
*fb
= state
->base
.fb
;
2356 unsigned int rotation
= state
->base
.rotation
;
2357 int pitch
= state
->color_plane
[color_plane
].stride
;
2360 if (intel_plane
->id
== PLANE_CURSOR
)
2361 alignment
= intel_cursor_alignment(dev_priv
);
2363 alignment
= intel_surf_alignment(fb
, color_plane
);
2365 return intel_compute_aligned_offset(dev_priv
, x
, y
, fb
, color_plane
,
2366 pitch
, rotation
, alignment
);
2369 /* Convert the fb->offset[] into x/y offsets */
2370 static int intel_fb_offset_to_xy(int *x
, int *y
,
2371 const struct drm_framebuffer
*fb
,
2374 struct drm_i915_private
*dev_priv
= to_i915(fb
->dev
);
2375 unsigned int height
;
2377 if (fb
->modifier
!= DRM_FORMAT_MOD_LINEAR
&&
2378 fb
->offsets
[color_plane
] % intel_tile_size(dev_priv
)) {
2379 DRM_DEBUG_KMS("Misaligned offset 0x%08x for color plane %d\n",
2380 fb
->offsets
[color_plane
], color_plane
);
2384 height
= drm_framebuffer_plane_height(fb
->height
, fb
, color_plane
);
2385 height
= ALIGN(height
, intel_tile_height(fb
, color_plane
));
2387 /* Catch potential overflows early */
2388 if (add_overflows_t(u32
, mul_u32_u32(height
, fb
->pitches
[color_plane
]),
2389 fb
->offsets
[color_plane
])) {
2390 DRM_DEBUG_KMS("Bad offset 0x%08x or pitch %d for color plane %d\n",
2391 fb
->offsets
[color_plane
], fb
->pitches
[color_plane
],
2399 intel_adjust_aligned_offset(x
, y
,
2400 fb
, color_plane
, DRM_MODE_ROTATE_0
,
2401 fb
->pitches
[color_plane
],
2402 fb
->offsets
[color_plane
], 0);
2407 static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier
)
2409 switch (fb_modifier
) {
2410 case I915_FORMAT_MOD_X_TILED
:
2411 return I915_TILING_X
;
2412 case I915_FORMAT_MOD_Y_TILED
:
2413 case I915_FORMAT_MOD_Y_TILED_CCS
:
2414 return I915_TILING_Y
;
2416 return I915_TILING_NONE
;
2421 * From the Sky Lake PRM:
2422 * "The Color Control Surface (CCS) contains the compression status of
2423 * the cache-line pairs. The compression state of the cache-line pair
2424 * is specified by 2 bits in the CCS. Each CCS cache-line represents
2425 * an area on the main surface of 16 x16 sets of 128 byte Y-tiled
2426 * cache-line-pairs. CCS is always Y tiled."
2428 * Since cache line pairs refers to horizontally adjacent cache lines,
2429 * each cache line in the CCS corresponds to an area of 32x16 cache
2430 * lines on the main surface. Since each pixel is 4 bytes, this gives
2431 * us a ratio of one byte in the CCS for each 8x16 pixels in the
2434 static const struct drm_format_info ccs_formats
[] = {
2435 { .format
= DRM_FORMAT_XRGB8888
, .depth
= 24, .num_planes
= 2, .cpp
= { 4, 1, }, .hsub
= 8, .vsub
= 16, },
2436 { .format
= DRM_FORMAT_XBGR8888
, .depth
= 24, .num_planes
= 2, .cpp
= { 4, 1, }, .hsub
= 8, .vsub
= 16, },
2437 { .format
= DRM_FORMAT_ARGB8888
, .depth
= 32, .num_planes
= 2, .cpp
= { 4, 1, }, .hsub
= 8, .vsub
= 16, },
2438 { .format
= DRM_FORMAT_ABGR8888
, .depth
= 32, .num_planes
= 2, .cpp
= { 4, 1, }, .hsub
= 8, .vsub
= 16, },
2441 static const struct drm_format_info
*
2442 lookup_format_info(const struct drm_format_info formats
[],
2443 int num_formats
, u32 format
)
2447 for (i
= 0; i
< num_formats
; i
++) {
2448 if (formats
[i
].format
== format
)
2455 static const struct drm_format_info
*
2456 intel_get_format_info(const struct drm_mode_fb_cmd2
*cmd
)
2458 switch (cmd
->modifier
[0]) {
2459 case I915_FORMAT_MOD_Y_TILED_CCS
:
2460 case I915_FORMAT_MOD_Yf_TILED_CCS
:
2461 return lookup_format_info(ccs_formats
,
2462 ARRAY_SIZE(ccs_formats
),
2469 bool is_ccs_modifier(u64 modifier
)
2471 return modifier
== I915_FORMAT_MOD_Y_TILED_CCS
||
2472 modifier
== I915_FORMAT_MOD_Yf_TILED_CCS
;
2476 intel_fill_fb_info(struct drm_i915_private
*dev_priv
,
2477 struct drm_framebuffer
*fb
)
2479 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
2480 struct intel_rotation_info
*rot_info
= &intel_fb
->rot_info
;
2481 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2482 u32 gtt_offset_rotated
= 0;
2483 unsigned int max_size
= 0;
2484 int i
, num_planes
= fb
->format
->num_planes
;
2485 unsigned int tile_size
= intel_tile_size(dev_priv
);
2487 for (i
= 0; i
< num_planes
; i
++) {
2488 unsigned int width
, height
;
2489 unsigned int cpp
, size
;
2494 cpp
= fb
->format
->cpp
[i
];
2495 width
= drm_framebuffer_plane_width(fb
->width
, fb
, i
);
2496 height
= drm_framebuffer_plane_height(fb
->height
, fb
, i
);
2498 ret
= intel_fb_offset_to_xy(&x
, &y
, fb
, i
);
2500 DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2505 if (is_ccs_modifier(fb
->modifier
) && i
== 1) {
2506 int hsub
= fb
->format
->hsub
;
2507 int vsub
= fb
->format
->vsub
;
2508 int tile_width
, tile_height
;
2512 intel_tile_dims(fb
, i
, &tile_width
, &tile_height
);
2514 tile_height
*= vsub
;
2516 ccs_x
= (x
* hsub
) % tile_width
;
2517 ccs_y
= (y
* vsub
) % tile_height
;
2518 main_x
= intel_fb
->normal
[0].x
% tile_width
;
2519 main_y
= intel_fb
->normal
[0].y
% tile_height
;
2522 * CCS doesn't have its own x/y offset register, so the intra CCS tile
2523 * x/y offsets must match between CCS and the main surface.
2525 if (main_x
!= ccs_x
|| main_y
!= ccs_y
) {
2526 DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
2529 intel_fb
->normal
[0].x
,
2530 intel_fb
->normal
[0].y
,
2537 * The fence (if used) is aligned to the start of the object
2538 * so having the framebuffer wrap around across the edge of the
2539 * fenced region doesn't really work. We have no API to configure
2540 * the fence start offset within the object (nor could we probably
2541 * on gen2/3). So it's just easier if we just require that the
2542 * fb layout agrees with the fence layout. We already check that the
2543 * fb stride matches the fence stride elsewhere.
2545 if (i
== 0 && i915_gem_object_is_tiled(obj
) &&
2546 (x
+ width
) * cpp
> fb
->pitches
[i
]) {
2547 DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2553 * First pixel of the framebuffer from
2554 * the start of the normal gtt mapping.
2556 intel_fb
->normal
[i
].x
= x
;
2557 intel_fb
->normal
[i
].y
= y
;
2559 offset
= intel_compute_aligned_offset(dev_priv
, &x
, &y
, fb
, i
,
2563 offset
/= tile_size
;
2565 if (!is_surface_linear(fb
->modifier
, i
)) {
2566 unsigned int tile_width
, tile_height
;
2567 unsigned int pitch_tiles
;
2570 intel_tile_dims(fb
, i
, &tile_width
, &tile_height
);
2572 rot_info
->plane
[i
].offset
= offset
;
2573 rot_info
->plane
[i
].stride
= DIV_ROUND_UP(fb
->pitches
[i
], tile_width
* cpp
);
2574 rot_info
->plane
[i
].width
= DIV_ROUND_UP(x
+ width
, tile_width
);
2575 rot_info
->plane
[i
].height
= DIV_ROUND_UP(y
+ height
, tile_height
);
2577 intel_fb
->rotated
[i
].pitch
=
2578 rot_info
->plane
[i
].height
* tile_height
;
2580 /* how many tiles does this plane need */
2581 size
= rot_info
->plane
[i
].stride
* rot_info
->plane
[i
].height
;
2583 * If the plane isn't horizontally tile aligned,
2584 * we need one more tile.
2589 /* rotate the x/y offsets to match the GTT view */
2595 rot_info
->plane
[i
].width
* tile_width
,
2596 rot_info
->plane
[i
].height
* tile_height
,
2597 DRM_MODE_ROTATE_270
);
2601 /* rotate the tile dimensions to match the GTT view */
2602 pitch_tiles
= intel_fb
->rotated
[i
].pitch
/ tile_height
;
2603 swap(tile_width
, tile_height
);
2606 * We only keep the x/y offsets, so push all of the
2607 * gtt offset into the x/y offsets.
2609 intel_adjust_tile_offset(&x
, &y
,
2610 tile_width
, tile_height
,
2611 tile_size
, pitch_tiles
,
2612 gtt_offset_rotated
* tile_size
, 0);
2614 gtt_offset_rotated
+= rot_info
->plane
[i
].width
* rot_info
->plane
[i
].height
;
2617 * First pixel of the framebuffer from
2618 * the start of the rotated gtt mapping.
2620 intel_fb
->rotated
[i
].x
= x
;
2621 intel_fb
->rotated
[i
].y
= y
;
2623 size
= DIV_ROUND_UP((y
+ height
) * fb
->pitches
[i
] +
2624 x
* cpp
, tile_size
);
2627 /* how many tiles in total needed in the bo */
2628 max_size
= max(max_size
, offset
+ size
);
2631 if (mul_u32_u32(max_size
, tile_size
) > obj
->base
.size
) {
2632 DRM_DEBUG_KMS("fb too big for bo (need %llu bytes, have %zu bytes)\n",
2633 mul_u32_u32(max_size
, tile_size
), obj
->base
.size
);
2640 static int i9xx_format_to_fourcc(int format
)
2643 case DISPPLANE_8BPP
:
2644 return DRM_FORMAT_C8
;
2645 case DISPPLANE_BGRX555
:
2646 return DRM_FORMAT_XRGB1555
;
2647 case DISPPLANE_BGRX565
:
2648 return DRM_FORMAT_RGB565
;
2650 case DISPPLANE_BGRX888
:
2651 return DRM_FORMAT_XRGB8888
;
2652 case DISPPLANE_RGBX888
:
2653 return DRM_FORMAT_XBGR8888
;
2654 case DISPPLANE_BGRX101010
:
2655 return DRM_FORMAT_XRGB2101010
;
2656 case DISPPLANE_RGBX101010
:
2657 return DRM_FORMAT_XBGR2101010
;
2661 int skl_format_to_fourcc(int format
, bool rgb_order
, bool alpha
)
2664 case PLANE_CTL_FORMAT_RGB_565
:
2665 return DRM_FORMAT_RGB565
;
2666 case PLANE_CTL_FORMAT_NV12
:
2667 return DRM_FORMAT_NV12
;
2668 case PLANE_CTL_FORMAT_P010
:
2669 return DRM_FORMAT_P010
;
2670 case PLANE_CTL_FORMAT_P012
:
2671 return DRM_FORMAT_P012
;
2672 case PLANE_CTL_FORMAT_P016
:
2673 return DRM_FORMAT_P016
;
2674 case PLANE_CTL_FORMAT_Y210
:
2675 return DRM_FORMAT_Y210
;
2676 case PLANE_CTL_FORMAT_Y212
:
2677 return DRM_FORMAT_Y212
;
2678 case PLANE_CTL_FORMAT_Y216
:
2679 return DRM_FORMAT_Y216
;
2680 case PLANE_CTL_FORMAT_Y410
:
2681 return DRM_FORMAT_XVYU2101010
;
2682 case PLANE_CTL_FORMAT_Y412
:
2683 return DRM_FORMAT_XVYU12_16161616
;
2684 case PLANE_CTL_FORMAT_Y416
:
2685 return DRM_FORMAT_XVYU16161616
;
2687 case PLANE_CTL_FORMAT_XRGB_8888
:
2690 return DRM_FORMAT_ABGR8888
;
2692 return DRM_FORMAT_XBGR8888
;
2695 return DRM_FORMAT_ARGB8888
;
2697 return DRM_FORMAT_XRGB8888
;
2699 case PLANE_CTL_FORMAT_XRGB_2101010
:
2701 return DRM_FORMAT_XBGR2101010
;
2703 return DRM_FORMAT_XRGB2101010
;
2704 case PLANE_CTL_FORMAT_XRGB_16161616F
:
2707 return DRM_FORMAT_ABGR16161616F
;
2709 return DRM_FORMAT_XBGR16161616F
;
2712 return DRM_FORMAT_ARGB16161616F
;
2714 return DRM_FORMAT_XRGB16161616F
;
2720 intel_alloc_initial_plane_obj(struct intel_crtc
*crtc
,
2721 struct intel_initial_plane_config
*plane_config
)
2723 struct drm_device
*dev
= crtc
->base
.dev
;
2724 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2725 struct drm_i915_gem_object
*obj
= NULL
;
2726 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
2727 struct drm_framebuffer
*fb
= &plane_config
->fb
->base
;
2728 u32 base_aligned
= round_down(plane_config
->base
, PAGE_SIZE
);
2729 u32 size_aligned
= round_up(plane_config
->base
+ plane_config
->size
,
2732 size_aligned
-= base_aligned
;
2734 if (plane_config
->size
== 0)
2737 /* If the FB is too big, just don't use it since fbdev is not very
2738 * important and we should probably use that space with FBC or other
2740 if (size_aligned
* 2 > dev_priv
->stolen_usable_size
)
2743 switch (fb
->modifier
) {
2744 case DRM_FORMAT_MOD_LINEAR
:
2745 case I915_FORMAT_MOD_X_TILED
:
2746 case I915_FORMAT_MOD_Y_TILED
:
2749 DRM_DEBUG_DRIVER("Unsupported modifier for initial FB: 0x%llx\n",
2754 mutex_lock(&dev
->struct_mutex
);
2755 obj
= i915_gem_object_create_stolen_for_preallocated(dev_priv
,
2759 mutex_unlock(&dev
->struct_mutex
);
2763 switch (plane_config
->tiling
) {
2764 case I915_TILING_NONE
:
2768 obj
->tiling_and_stride
= fb
->pitches
[0] | plane_config
->tiling
;
2771 MISSING_CASE(plane_config
->tiling
);
2775 mode_cmd
.pixel_format
= fb
->format
->format
;
2776 mode_cmd
.width
= fb
->width
;
2777 mode_cmd
.height
= fb
->height
;
2778 mode_cmd
.pitches
[0] = fb
->pitches
[0];
2779 mode_cmd
.modifier
[0] = fb
->modifier
;
2780 mode_cmd
.flags
= DRM_MODE_FB_MODIFIERS
;
2782 if (intel_framebuffer_init(to_intel_framebuffer(fb
), obj
, &mode_cmd
)) {
2783 DRM_DEBUG_KMS("intel fb init failed\n");
2788 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj
);
2792 i915_gem_object_put(obj
);
2797 intel_set_plane_visible(struct intel_crtc_state
*crtc_state
,
2798 struct intel_plane_state
*plane_state
,
2801 struct intel_plane
*plane
= to_intel_plane(plane_state
->base
.plane
);
2803 plane_state
->base
.visible
= visible
;
2806 crtc_state
->base
.plane_mask
|= drm_plane_mask(&plane
->base
);
2808 crtc_state
->base
.plane_mask
&= ~drm_plane_mask(&plane
->base
);
2811 static void fixup_active_planes(struct intel_crtc_state
*crtc_state
)
2813 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->base
.crtc
->dev
);
2814 struct drm_plane
*plane
;
2817 * Active_planes aliases if multiple "primary" or cursor planes
2818 * have been used on the same (or wrong) pipe. plane_mask uses
2819 * unique ids, hence we can use that to reconstruct active_planes.
2821 crtc_state
->active_planes
= 0;
2823 drm_for_each_plane_mask(plane
, &dev_priv
->drm
,
2824 crtc_state
->base
.plane_mask
)
2825 crtc_state
->active_planes
|= BIT(to_intel_plane(plane
)->id
);
2828 static void intel_plane_disable_noatomic(struct intel_crtc
*crtc
,
2829 struct intel_plane
*plane
)
2831 struct intel_crtc_state
*crtc_state
=
2832 to_intel_crtc_state(crtc
->base
.state
);
2833 struct intel_plane_state
*plane_state
=
2834 to_intel_plane_state(plane
->base
.state
);
2836 DRM_DEBUG_KMS("Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n",
2837 plane
->base
.base
.id
, plane
->base
.name
,
2838 crtc
->base
.base
.id
, crtc
->base
.name
);
2840 intel_set_plane_visible(crtc_state
, plane_state
, false);
2841 fixup_active_planes(crtc_state
);
2843 if (plane
->id
== PLANE_PRIMARY
)
2844 intel_pre_disable_primary_noatomic(&crtc
->base
);
2846 intel_disable_plane(plane
, crtc_state
);
2850 intel_find_initial_plane_obj(struct intel_crtc
*intel_crtc
,
2851 struct intel_initial_plane_config
*plane_config
)
2853 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2854 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2856 struct drm_i915_gem_object
*obj
;
2857 struct drm_plane
*primary
= intel_crtc
->base
.primary
;
2858 struct drm_plane_state
*plane_state
= primary
->state
;
2859 struct intel_plane
*intel_plane
= to_intel_plane(primary
);
2860 struct intel_plane_state
*intel_state
=
2861 to_intel_plane_state(plane_state
);
2862 struct drm_framebuffer
*fb
;
2864 if (!plane_config
->fb
)
2867 if (intel_alloc_initial_plane_obj(intel_crtc
, plane_config
)) {
2868 fb
= &plane_config
->fb
->base
;
2872 kfree(plane_config
->fb
);
2875 * Failed to alloc the obj, check to see if we should share
2876 * an fb with another CRTC instead
2878 for_each_crtc(dev
, c
) {
2879 struct intel_plane_state
*state
;
2881 if (c
== &intel_crtc
->base
)
2884 if (!to_intel_crtc(c
)->active
)
2887 state
= to_intel_plane_state(c
->primary
->state
);
2891 if (intel_plane_ggtt_offset(state
) == plane_config
->base
) {
2892 fb
= state
->base
.fb
;
2893 drm_framebuffer_get(fb
);
2899 * We've failed to reconstruct the BIOS FB. Current display state
2900 * indicates that the primary plane is visible, but has a NULL FB,
2901 * which will lead to problems later if we don't fix it up. The
2902 * simplest solution is to just disable the primary plane now and
2903 * pretend the BIOS never had it enabled.
2905 intel_plane_disable_noatomic(intel_crtc
, intel_plane
);
2910 intel_state
->base
.rotation
= plane_config
->rotation
;
2911 intel_fill_fb_ggtt_view(&intel_state
->view
, fb
,
2912 intel_state
->base
.rotation
);
2913 intel_state
->color_plane
[0].stride
=
2914 intel_fb_pitch(fb
, 0, intel_state
->base
.rotation
);
2916 mutex_lock(&dev
->struct_mutex
);
2918 intel_pin_and_fence_fb_obj(fb
,
2920 intel_plane_uses_fence(intel_state
),
2921 &intel_state
->flags
);
2922 mutex_unlock(&dev
->struct_mutex
);
2923 if (IS_ERR(intel_state
->vma
)) {
2924 DRM_ERROR("failed to pin boot fb on pipe %d: %li\n",
2925 intel_crtc
->pipe
, PTR_ERR(intel_state
->vma
));
2927 intel_state
->vma
= NULL
;
2928 drm_framebuffer_put(fb
);
2932 obj
= intel_fb_obj(fb
);
2933 intel_fb_obj_flush(obj
, ORIGIN_DIRTYFB
);
2935 plane_state
->src_x
= 0;
2936 plane_state
->src_y
= 0;
2937 plane_state
->src_w
= fb
->width
<< 16;
2938 plane_state
->src_h
= fb
->height
<< 16;
2940 plane_state
->crtc_x
= 0;
2941 plane_state
->crtc_y
= 0;
2942 plane_state
->crtc_w
= fb
->width
;
2943 plane_state
->crtc_h
= fb
->height
;
2945 intel_state
->base
.src
= drm_plane_state_src(plane_state
);
2946 intel_state
->base
.dst
= drm_plane_state_dest(plane_state
);
2948 if (i915_gem_object_is_tiled(obj
))
2949 dev_priv
->preserve_bios_swizzle
= true;
2951 plane_state
->fb
= fb
;
2952 plane_state
->crtc
= &intel_crtc
->base
;
2954 atomic_or(to_intel_plane(primary
)->frontbuffer_bit
,
2955 &obj
->frontbuffer_bits
);
2958 static int skl_max_plane_width(const struct drm_framebuffer
*fb
,
2960 unsigned int rotation
)
2962 int cpp
= fb
->format
->cpp
[color_plane
];
2964 switch (fb
->modifier
) {
2965 case DRM_FORMAT_MOD_LINEAR
:
2966 case I915_FORMAT_MOD_X_TILED
:
2968 case I915_FORMAT_MOD_Y_TILED_CCS
:
2969 case I915_FORMAT_MOD_Yf_TILED_CCS
:
2970 /* FIXME AUX plane? */
2971 case I915_FORMAT_MOD_Y_TILED
:
2972 case I915_FORMAT_MOD_Yf_TILED
:
2978 MISSING_CASE(fb
->modifier
);
2983 static int glk_max_plane_width(const struct drm_framebuffer
*fb
,
2985 unsigned int rotation
)
2987 int cpp
= fb
->format
->cpp
[color_plane
];
2989 switch (fb
->modifier
) {
2990 case DRM_FORMAT_MOD_LINEAR
:
2991 case I915_FORMAT_MOD_X_TILED
:
2996 case I915_FORMAT_MOD_Y_TILED_CCS
:
2997 case I915_FORMAT_MOD_Yf_TILED_CCS
:
2998 /* FIXME AUX plane? */
2999 case I915_FORMAT_MOD_Y_TILED
:
3000 case I915_FORMAT_MOD_Yf_TILED
:
3006 MISSING_CASE(fb
->modifier
);
3011 static int icl_max_plane_width(const struct drm_framebuffer
*fb
,
3013 unsigned int rotation
)
3018 static bool skl_check_main_ccs_coordinates(struct intel_plane_state
*plane_state
,
3019 int main_x
, int main_y
, u32 main_offset
)
3021 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
3022 int hsub
= fb
->format
->hsub
;
3023 int vsub
= fb
->format
->vsub
;
3024 int aux_x
= plane_state
->color_plane
[1].x
;
3025 int aux_y
= plane_state
->color_plane
[1].y
;
3026 u32 aux_offset
= plane_state
->color_plane
[1].offset
;
3027 u32 alignment
= intel_surf_alignment(fb
, 1);
3029 while (aux_offset
>= main_offset
&& aux_y
<= main_y
) {
3032 if (aux_x
== main_x
&& aux_y
== main_y
)
3035 if (aux_offset
== 0)
3040 aux_offset
= intel_plane_adjust_aligned_offset(&x
, &y
, plane_state
, 1,
3041 aux_offset
, aux_offset
- alignment
);
3042 aux_x
= x
* hsub
+ aux_x
% hsub
;
3043 aux_y
= y
* vsub
+ aux_y
% vsub
;
3046 if (aux_x
!= main_x
|| aux_y
!= main_y
)
3049 plane_state
->color_plane
[1].offset
= aux_offset
;
3050 plane_state
->color_plane
[1].x
= aux_x
;
3051 plane_state
->color_plane
[1].y
= aux_y
;
3056 static int skl_check_main_surface(struct intel_plane_state
*plane_state
)
3058 struct drm_i915_private
*dev_priv
= to_i915(plane_state
->base
.plane
->dev
);
3059 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
3060 unsigned int rotation
= plane_state
->base
.rotation
;
3061 int x
= plane_state
->base
.src
.x1
>> 16;
3062 int y
= plane_state
->base
.src
.y1
>> 16;
3063 int w
= drm_rect_width(&plane_state
->base
.src
) >> 16;
3064 int h
= drm_rect_height(&plane_state
->base
.src
) >> 16;
3066 int max_height
= 4096;
3067 u32 alignment
, offset
, aux_offset
= plane_state
->color_plane
[1].offset
;
3069 if (INTEL_GEN(dev_priv
) >= 11)
3070 max_width
= icl_max_plane_width(fb
, 0, rotation
);
3071 else if (INTEL_GEN(dev_priv
) >= 10 || IS_GEMINILAKE(dev_priv
))
3072 max_width
= glk_max_plane_width(fb
, 0, rotation
);
3074 max_width
= skl_max_plane_width(fb
, 0, rotation
);
3076 if (w
> max_width
|| h
> max_height
) {
3077 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
3078 w
, h
, max_width
, max_height
);
3082 intel_add_fb_offsets(&x
, &y
, plane_state
, 0);
3083 offset
= intel_plane_compute_aligned_offset(&x
, &y
, plane_state
, 0);
3084 alignment
= intel_surf_alignment(fb
, 0);
3087 * AUX surface offset is specified as the distance from the
3088 * main surface offset, and it must be non-negative. Make
3089 * sure that is what we will get.
3091 if (offset
> aux_offset
)
3092 offset
= intel_plane_adjust_aligned_offset(&x
, &y
, plane_state
, 0,
3093 offset
, aux_offset
& ~(alignment
- 1));
3096 * When using an X-tiled surface, the plane blows up
3097 * if the x offset + width exceed the stride.
3099 * TODO: linear and Y-tiled seem fine, Yf untested,
3101 if (fb
->modifier
== I915_FORMAT_MOD_X_TILED
) {
3102 int cpp
= fb
->format
->cpp
[0];
3104 while ((x
+ w
) * cpp
> plane_state
->color_plane
[0].stride
) {
3106 DRM_DEBUG_KMS("Unable to find suitable display surface offset due to X-tiling\n");
3110 offset
= intel_plane_adjust_aligned_offset(&x
, &y
, plane_state
, 0,
3111 offset
, offset
- alignment
);
3116 * CCS AUX surface doesn't have its own x/y offsets, we must make sure
3117 * they match with the main surface x/y offsets.
3119 if (is_ccs_modifier(fb
->modifier
)) {
3120 while (!skl_check_main_ccs_coordinates(plane_state
, x
, y
, offset
)) {
3124 offset
= intel_plane_adjust_aligned_offset(&x
, &y
, plane_state
, 0,
3125 offset
, offset
- alignment
);
3128 if (x
!= plane_state
->color_plane
[1].x
|| y
!= plane_state
->color_plane
[1].y
) {
3129 DRM_DEBUG_KMS("Unable to find suitable display surface offset due to CCS\n");
3134 plane_state
->color_plane
[0].offset
= offset
;
3135 plane_state
->color_plane
[0].x
= x
;
3136 plane_state
->color_plane
[0].y
= y
;
3141 static int skl_check_nv12_aux_surface(struct intel_plane_state
*plane_state
)
3143 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
3144 unsigned int rotation
= plane_state
->base
.rotation
;
3145 int max_width
= skl_max_plane_width(fb
, 1, rotation
);
3146 int max_height
= 4096;
3147 int x
= plane_state
->base
.src
.x1
>> 17;
3148 int y
= plane_state
->base
.src
.y1
>> 17;
3149 int w
= drm_rect_width(&plane_state
->base
.src
) >> 17;
3150 int h
= drm_rect_height(&plane_state
->base
.src
) >> 17;
3153 intel_add_fb_offsets(&x
, &y
, plane_state
, 1);
3154 offset
= intel_plane_compute_aligned_offset(&x
, &y
, plane_state
, 1);
3156 /* FIXME not quite sure how/if these apply to the chroma plane */
3157 if (w
> max_width
|| h
> max_height
) {
3158 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
3159 w
, h
, max_width
, max_height
);
3163 plane_state
->color_plane
[1].offset
= offset
;
3164 plane_state
->color_plane
[1].x
= x
;
3165 plane_state
->color_plane
[1].y
= y
;
3170 static int skl_check_ccs_aux_surface(struct intel_plane_state
*plane_state
)
3172 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
3173 int src_x
= plane_state
->base
.src
.x1
>> 16;
3174 int src_y
= plane_state
->base
.src
.y1
>> 16;
3175 int hsub
= fb
->format
->hsub
;
3176 int vsub
= fb
->format
->vsub
;
3177 int x
= src_x
/ hsub
;
3178 int y
= src_y
/ vsub
;
3181 intel_add_fb_offsets(&x
, &y
, plane_state
, 1);
3182 offset
= intel_plane_compute_aligned_offset(&x
, &y
, plane_state
, 1);
3184 plane_state
->color_plane
[1].offset
= offset
;
3185 plane_state
->color_plane
[1].x
= x
* hsub
+ src_x
% hsub
;
3186 plane_state
->color_plane
[1].y
= y
* vsub
+ src_y
% vsub
;
3191 int skl_check_plane_surface(struct intel_plane_state
*plane_state
)
3193 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
3194 unsigned int rotation
= plane_state
->base
.rotation
;
3197 intel_fill_fb_ggtt_view(&plane_state
->view
, fb
, rotation
);
3198 plane_state
->color_plane
[0].stride
= intel_fb_pitch(fb
, 0, rotation
);
3199 plane_state
->color_plane
[1].stride
= intel_fb_pitch(fb
, 1, rotation
);
3201 ret
= intel_plane_check_stride(plane_state
);
3205 if (!plane_state
->base
.visible
)
3208 /* Rotate src coordinates to match rotated GTT view */
3209 if (drm_rotation_90_or_270(rotation
))
3210 drm_rect_rotate(&plane_state
->base
.src
,
3211 fb
->width
<< 16, fb
->height
<< 16,
3212 DRM_MODE_ROTATE_270
);
3215 * Handle the AUX surface first since
3216 * the main surface setup depends on it.
3218 if (is_planar_yuv_format(fb
->format
->format
)) {
3219 ret
= skl_check_nv12_aux_surface(plane_state
);
3222 } else if (is_ccs_modifier(fb
->modifier
)) {
3223 ret
= skl_check_ccs_aux_surface(plane_state
);
3227 plane_state
->color_plane
[1].offset
= ~0xfff;
3228 plane_state
->color_plane
[1].x
= 0;
3229 plane_state
->color_plane
[1].y
= 0;
3232 ret
= skl_check_main_surface(plane_state
);
3240 i9xx_plane_max_stride(struct intel_plane
*plane
,
3241 u32 pixel_format
, u64 modifier
,
3242 unsigned int rotation
)
3244 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
3246 if (!HAS_GMCH(dev_priv
)) {
3248 } else if (INTEL_GEN(dev_priv
) >= 4) {
3249 if (modifier
== I915_FORMAT_MOD_X_TILED
)
3253 } else if (INTEL_GEN(dev_priv
) >= 3) {
3254 if (modifier
== I915_FORMAT_MOD_X_TILED
)
3259 if (plane
->i9xx_plane
== PLANE_C
)
3266 static u32
i9xx_plane_ctl_crtc(const struct intel_crtc_state
*crtc_state
)
3268 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
3269 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
3272 if (crtc_state
->gamma_enable
)
3273 dspcntr
|= DISPPLANE_GAMMA_ENABLE
;
3275 if (crtc_state
->csc_enable
)
3276 dspcntr
|= DISPPLANE_PIPE_CSC_ENABLE
;
3278 if (INTEL_GEN(dev_priv
) < 5)
3279 dspcntr
|= DISPPLANE_SEL_PIPE(crtc
->pipe
);
3284 static u32
i9xx_plane_ctl(const struct intel_crtc_state
*crtc_state
,
3285 const struct intel_plane_state
*plane_state
)
3287 struct drm_i915_private
*dev_priv
=
3288 to_i915(plane_state
->base
.plane
->dev
);
3289 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
3290 unsigned int rotation
= plane_state
->base
.rotation
;
3293 dspcntr
= DISPLAY_PLANE_ENABLE
;
3295 if (IS_G4X(dev_priv
) || IS_GEN(dev_priv
, 5) ||
3296 IS_GEN(dev_priv
, 6) || IS_IVYBRIDGE(dev_priv
))
3297 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
3299 switch (fb
->format
->format
) {
3301 dspcntr
|= DISPPLANE_8BPP
;
3303 case DRM_FORMAT_XRGB1555
:
3304 dspcntr
|= DISPPLANE_BGRX555
;
3306 case DRM_FORMAT_RGB565
:
3307 dspcntr
|= DISPPLANE_BGRX565
;
3309 case DRM_FORMAT_XRGB8888
:
3310 dspcntr
|= DISPPLANE_BGRX888
;
3312 case DRM_FORMAT_XBGR8888
:
3313 dspcntr
|= DISPPLANE_RGBX888
;
3315 case DRM_FORMAT_XRGB2101010
:
3316 dspcntr
|= DISPPLANE_BGRX101010
;
3318 case DRM_FORMAT_XBGR2101010
:
3319 dspcntr
|= DISPPLANE_RGBX101010
;
3322 MISSING_CASE(fb
->format
->format
);
3326 if (INTEL_GEN(dev_priv
) >= 4 &&
3327 fb
->modifier
== I915_FORMAT_MOD_X_TILED
)
3328 dspcntr
|= DISPPLANE_TILED
;
3330 if (rotation
& DRM_MODE_ROTATE_180
)
3331 dspcntr
|= DISPPLANE_ROTATE_180
;
3333 if (rotation
& DRM_MODE_REFLECT_X
)
3334 dspcntr
|= DISPPLANE_MIRROR
;
3339 int i9xx_check_plane_surface(struct intel_plane_state
*plane_state
)
3341 struct drm_i915_private
*dev_priv
=
3342 to_i915(plane_state
->base
.plane
->dev
);
3343 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
3344 unsigned int rotation
= plane_state
->base
.rotation
;
3345 int src_x
= plane_state
->base
.src
.x1
>> 16;
3346 int src_y
= plane_state
->base
.src
.y1
>> 16;
3350 intel_fill_fb_ggtt_view(&plane_state
->view
, fb
, rotation
);
3351 plane_state
->color_plane
[0].stride
= intel_fb_pitch(fb
, 0, rotation
);
3353 ret
= intel_plane_check_stride(plane_state
);
3357 intel_add_fb_offsets(&src_x
, &src_y
, plane_state
, 0);
3359 if (INTEL_GEN(dev_priv
) >= 4)
3360 offset
= intel_plane_compute_aligned_offset(&src_x
, &src_y
,
3365 /* HSW/BDW do this automagically in hardware */
3366 if (!IS_HASWELL(dev_priv
) && !IS_BROADWELL(dev_priv
)) {
3367 int src_w
= drm_rect_width(&plane_state
->base
.src
) >> 16;
3368 int src_h
= drm_rect_height(&plane_state
->base
.src
) >> 16;
3370 if (rotation
& DRM_MODE_ROTATE_180
) {
3373 } else if (rotation
& DRM_MODE_REFLECT_X
) {
3378 plane_state
->color_plane
[0].offset
= offset
;
3379 plane_state
->color_plane
[0].x
= src_x
;
3380 plane_state
->color_plane
[0].y
= src_y
;
3386 i9xx_plane_check(struct intel_crtc_state
*crtc_state
,
3387 struct intel_plane_state
*plane_state
)
3391 ret
= chv_plane_check_rotation(plane_state
);
3395 ret
= drm_atomic_helper_check_plane_state(&plane_state
->base
,
3397 DRM_PLANE_HELPER_NO_SCALING
,
3398 DRM_PLANE_HELPER_NO_SCALING
,
3403 if (!plane_state
->base
.visible
)
3406 ret
= intel_plane_check_src_coordinates(plane_state
);
3410 ret
= i9xx_check_plane_surface(plane_state
);
3414 plane_state
->ctl
= i9xx_plane_ctl(crtc_state
, plane_state
);
3419 static void i9xx_update_plane(struct intel_plane
*plane
,
3420 const struct intel_crtc_state
*crtc_state
,
3421 const struct intel_plane_state
*plane_state
)
3423 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
3424 enum i9xx_plane_id i9xx_plane
= plane
->i9xx_plane
;
3426 int x
= plane_state
->color_plane
[0].x
;
3427 int y
= plane_state
->color_plane
[0].y
;
3428 unsigned long irqflags
;
3432 dspcntr
= plane_state
->ctl
| i9xx_plane_ctl_crtc(crtc_state
);
3434 linear_offset
= intel_fb_xy_to_linear(x
, y
, plane_state
, 0);
3436 if (INTEL_GEN(dev_priv
) >= 4)
3437 dspaddr_offset
= plane_state
->color_plane
[0].offset
;
3439 dspaddr_offset
= linear_offset
;
3441 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
3443 I915_WRITE_FW(DSPSTRIDE(i9xx_plane
), plane_state
->color_plane
[0].stride
);
3445 if (INTEL_GEN(dev_priv
) < 4) {
3446 /* pipesrc and dspsize control the size that is scaled from,
3447 * which should always be the user's requested size.
3449 I915_WRITE_FW(DSPPOS(i9xx_plane
), 0);
3450 I915_WRITE_FW(DSPSIZE(i9xx_plane
),
3451 ((crtc_state
->pipe_src_h
- 1) << 16) |
3452 (crtc_state
->pipe_src_w
- 1));
3453 } else if (IS_CHERRYVIEW(dev_priv
) && i9xx_plane
== PLANE_B
) {
3454 I915_WRITE_FW(PRIMPOS(i9xx_plane
), 0);
3455 I915_WRITE_FW(PRIMSIZE(i9xx_plane
),
3456 ((crtc_state
->pipe_src_h
- 1) << 16) |
3457 (crtc_state
->pipe_src_w
- 1));
3458 I915_WRITE_FW(PRIMCNSTALPHA(i9xx_plane
), 0);
3461 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
3462 I915_WRITE_FW(DSPOFFSET(i9xx_plane
), (y
<< 16) | x
);
3463 } else if (INTEL_GEN(dev_priv
) >= 4) {
3464 I915_WRITE_FW(DSPLINOFF(i9xx_plane
), linear_offset
);
3465 I915_WRITE_FW(DSPTILEOFF(i9xx_plane
), (y
<< 16) | x
);
3469 * The control register self-arms if the plane was previously
3470 * disabled. Try to make the plane enable atomic by writing
3471 * the control register just before the surface register.
3473 I915_WRITE_FW(DSPCNTR(i9xx_plane
), dspcntr
);
3474 if (INTEL_GEN(dev_priv
) >= 4)
3475 I915_WRITE_FW(DSPSURF(i9xx_plane
),
3476 intel_plane_ggtt_offset(plane_state
) +
3479 I915_WRITE_FW(DSPADDR(i9xx_plane
),
3480 intel_plane_ggtt_offset(plane_state
) +
3483 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
3486 static void i9xx_disable_plane(struct intel_plane
*plane
,
3487 const struct intel_crtc_state
*crtc_state
)
3489 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
3490 enum i9xx_plane_id i9xx_plane
= plane
->i9xx_plane
;
3491 unsigned long irqflags
;
3495 * DSPCNTR pipe gamma enable on g4x+ and pipe csc
3496 * enable on ilk+ affect the pipe bottom color as
3497 * well, so we must configure them even if the plane
3500 * On pre-g4x there is no way to gamma correct the
3501 * pipe bottom color but we'll keep on doing this
3502 * anyway so that the crtc state readout works correctly.
3504 dspcntr
= i9xx_plane_ctl_crtc(crtc_state
);
3506 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
3508 I915_WRITE_FW(DSPCNTR(i9xx_plane
), dspcntr
);
3509 if (INTEL_GEN(dev_priv
) >= 4)
3510 I915_WRITE_FW(DSPSURF(i9xx_plane
), 0);
3512 I915_WRITE_FW(DSPADDR(i9xx_plane
), 0);
3514 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
3517 static bool i9xx_plane_get_hw_state(struct intel_plane
*plane
,
3520 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
3521 enum intel_display_power_domain power_domain
;
3522 enum i9xx_plane_id i9xx_plane
= plane
->i9xx_plane
;
3523 intel_wakeref_t wakeref
;
3528 * Not 100% correct for planes that can move between pipes,
3529 * but that's only the case for gen2-4 which don't have any
3530 * display power wells.
3532 power_domain
= POWER_DOMAIN_PIPE(plane
->pipe
);
3533 wakeref
= intel_display_power_get_if_enabled(dev_priv
, power_domain
);
3537 val
= I915_READ(DSPCNTR(i9xx_plane
));
3539 ret
= val
& DISPLAY_PLANE_ENABLE
;
3541 if (INTEL_GEN(dev_priv
) >= 5)
3542 *pipe
= plane
->pipe
;
3544 *pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
3545 DISPPLANE_SEL_PIPE_SHIFT
;
3547 intel_display_power_put(dev_priv
, power_domain
, wakeref
);
3553 intel_fb_stride_alignment(const struct drm_framebuffer
*fb
, int color_plane
)
3555 if (fb
->modifier
== DRM_FORMAT_MOD_LINEAR
)
3558 return intel_tile_width_bytes(fb
, color_plane
);
3561 static void skl_detach_scaler(struct intel_crtc
*intel_crtc
, int id
)
3563 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3564 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3566 I915_WRITE(SKL_PS_CTRL(intel_crtc
->pipe
, id
), 0);
3567 I915_WRITE(SKL_PS_WIN_POS(intel_crtc
->pipe
, id
), 0);
3568 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc
->pipe
, id
), 0);
3572 * This function detaches (aka. unbinds) unused scalers in hardware
3574 static void skl_detach_scalers(const struct intel_crtc_state
*crtc_state
)
3576 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
3577 const struct intel_crtc_scaler_state
*scaler_state
=
3578 &crtc_state
->scaler_state
;
3581 /* loop through and disable scalers that aren't in use */
3582 for (i
= 0; i
< intel_crtc
->num_scalers
; i
++) {
3583 if (!scaler_state
->scalers
[i
].in_use
)
3584 skl_detach_scaler(intel_crtc
, i
);
3588 static unsigned int skl_plane_stride_mult(const struct drm_framebuffer
*fb
,
3589 int color_plane
, unsigned int rotation
)
3592 * The stride is either expressed as a multiple of 64 bytes chunks for
3593 * linear buffers or in number of tiles for tiled buffers.
3595 if (fb
->modifier
== DRM_FORMAT_MOD_LINEAR
)
3597 else if (drm_rotation_90_or_270(rotation
))
3598 return intel_tile_height(fb
, color_plane
);
3600 return intel_tile_width_bytes(fb
, color_plane
);
3603 u32
skl_plane_stride(const struct intel_plane_state
*plane_state
,
3606 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
3607 unsigned int rotation
= plane_state
->base
.rotation
;
3608 u32 stride
= plane_state
->color_plane
[color_plane
].stride
;
3610 if (color_plane
>= fb
->format
->num_planes
)
3613 return stride
/ skl_plane_stride_mult(fb
, color_plane
, rotation
);
3616 static u32
skl_plane_ctl_format(u32 pixel_format
)
3618 switch (pixel_format
) {
3620 return PLANE_CTL_FORMAT_INDEXED
;
3621 case DRM_FORMAT_RGB565
:
3622 return PLANE_CTL_FORMAT_RGB_565
;
3623 case DRM_FORMAT_XBGR8888
:
3624 case DRM_FORMAT_ABGR8888
:
3625 return PLANE_CTL_FORMAT_XRGB_8888
| PLANE_CTL_ORDER_RGBX
;
3626 case DRM_FORMAT_XRGB8888
:
3627 case DRM_FORMAT_ARGB8888
:
3628 return PLANE_CTL_FORMAT_XRGB_8888
;
3629 case DRM_FORMAT_XRGB2101010
:
3630 return PLANE_CTL_FORMAT_XRGB_2101010
;
3631 case DRM_FORMAT_XBGR2101010
:
3632 return PLANE_CTL_ORDER_RGBX
| PLANE_CTL_FORMAT_XRGB_2101010
;
3633 case DRM_FORMAT_XBGR16161616F
:
3634 case DRM_FORMAT_ABGR16161616F
:
3635 return PLANE_CTL_FORMAT_XRGB_16161616F
| PLANE_CTL_ORDER_RGBX
;
3636 case DRM_FORMAT_XRGB16161616F
:
3637 case DRM_FORMAT_ARGB16161616F
:
3638 return PLANE_CTL_FORMAT_XRGB_16161616F
;
3639 case DRM_FORMAT_YUYV
:
3640 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_YUYV
;
3641 case DRM_FORMAT_YVYU
:
3642 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_YVYU
;
3643 case DRM_FORMAT_UYVY
:
3644 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_UYVY
;
3645 case DRM_FORMAT_VYUY
:
3646 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_VYUY
;
3647 case DRM_FORMAT_NV12
:
3648 return PLANE_CTL_FORMAT_NV12
;
3649 case DRM_FORMAT_P010
:
3650 return PLANE_CTL_FORMAT_P010
;
3651 case DRM_FORMAT_P012
:
3652 return PLANE_CTL_FORMAT_P012
;
3653 case DRM_FORMAT_P016
:
3654 return PLANE_CTL_FORMAT_P016
;
3655 case DRM_FORMAT_Y210
:
3656 return PLANE_CTL_FORMAT_Y210
;
3657 case DRM_FORMAT_Y212
:
3658 return PLANE_CTL_FORMAT_Y212
;
3659 case DRM_FORMAT_Y216
:
3660 return PLANE_CTL_FORMAT_Y216
;
3661 case DRM_FORMAT_XVYU2101010
:
3662 return PLANE_CTL_FORMAT_Y410
;
3663 case DRM_FORMAT_XVYU12_16161616
:
3664 return PLANE_CTL_FORMAT_Y412
;
3665 case DRM_FORMAT_XVYU16161616
:
3666 return PLANE_CTL_FORMAT_Y416
;
3668 MISSING_CASE(pixel_format
);
3674 static u32
skl_plane_ctl_alpha(const struct intel_plane_state
*plane_state
)
3676 if (!plane_state
->base
.fb
->format
->has_alpha
)
3677 return PLANE_CTL_ALPHA_DISABLE
;
3679 switch (plane_state
->base
.pixel_blend_mode
) {
3680 case DRM_MODE_BLEND_PIXEL_NONE
:
3681 return PLANE_CTL_ALPHA_DISABLE
;
3682 case DRM_MODE_BLEND_PREMULTI
:
3683 return PLANE_CTL_ALPHA_SW_PREMULTIPLY
;
3684 case DRM_MODE_BLEND_COVERAGE
:
3685 return PLANE_CTL_ALPHA_HW_PREMULTIPLY
;
3687 MISSING_CASE(plane_state
->base
.pixel_blend_mode
);
3688 return PLANE_CTL_ALPHA_DISABLE
;
3692 static u32
glk_plane_color_ctl_alpha(const struct intel_plane_state
*plane_state
)
3694 if (!plane_state
->base
.fb
->format
->has_alpha
)
3695 return PLANE_COLOR_ALPHA_DISABLE
;
3697 switch (plane_state
->base
.pixel_blend_mode
) {
3698 case DRM_MODE_BLEND_PIXEL_NONE
:
3699 return PLANE_COLOR_ALPHA_DISABLE
;
3700 case DRM_MODE_BLEND_PREMULTI
:
3701 return PLANE_COLOR_ALPHA_SW_PREMULTIPLY
;
3702 case DRM_MODE_BLEND_COVERAGE
:
3703 return PLANE_COLOR_ALPHA_HW_PREMULTIPLY
;
3705 MISSING_CASE(plane_state
->base
.pixel_blend_mode
);
3706 return PLANE_COLOR_ALPHA_DISABLE
;
3710 static u32
skl_plane_ctl_tiling(u64 fb_modifier
)
3712 switch (fb_modifier
) {
3713 case DRM_FORMAT_MOD_LINEAR
:
3715 case I915_FORMAT_MOD_X_TILED
:
3716 return PLANE_CTL_TILED_X
;
3717 case I915_FORMAT_MOD_Y_TILED
:
3718 return PLANE_CTL_TILED_Y
;
3719 case I915_FORMAT_MOD_Y_TILED_CCS
:
3720 return PLANE_CTL_TILED_Y
| PLANE_CTL_RENDER_DECOMPRESSION_ENABLE
;
3721 case I915_FORMAT_MOD_Yf_TILED
:
3722 return PLANE_CTL_TILED_YF
;
3723 case I915_FORMAT_MOD_Yf_TILED_CCS
:
3724 return PLANE_CTL_TILED_YF
| PLANE_CTL_RENDER_DECOMPRESSION_ENABLE
;
3726 MISSING_CASE(fb_modifier
);
3732 static u32
skl_plane_ctl_rotate(unsigned int rotate
)
3735 case DRM_MODE_ROTATE_0
:
3738 * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
3739 * while i915 HW rotation is clockwise, thats why this swapping.
3741 case DRM_MODE_ROTATE_90
:
3742 return PLANE_CTL_ROTATE_270
;
3743 case DRM_MODE_ROTATE_180
:
3744 return PLANE_CTL_ROTATE_180
;
3745 case DRM_MODE_ROTATE_270
:
3746 return PLANE_CTL_ROTATE_90
;
3748 MISSING_CASE(rotate
);
3754 static u32
cnl_plane_ctl_flip(unsigned int reflect
)
3759 case DRM_MODE_REFLECT_X
:
3760 return PLANE_CTL_FLIP_HORIZONTAL
;
3761 case DRM_MODE_REFLECT_Y
:
3763 MISSING_CASE(reflect
);
3769 u32
skl_plane_ctl_crtc(const struct intel_crtc_state
*crtc_state
)
3771 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->base
.crtc
->dev
);
3774 if (INTEL_GEN(dev_priv
) >= 10 || IS_GEMINILAKE(dev_priv
))
3777 if (crtc_state
->gamma_enable
)
3778 plane_ctl
|= PLANE_CTL_PIPE_GAMMA_ENABLE
;
3780 if (crtc_state
->csc_enable
)
3781 plane_ctl
|= PLANE_CTL_PIPE_CSC_ENABLE
;
3786 u32
skl_plane_ctl(const struct intel_crtc_state
*crtc_state
,
3787 const struct intel_plane_state
*plane_state
)
3789 struct drm_i915_private
*dev_priv
=
3790 to_i915(plane_state
->base
.plane
->dev
);
3791 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
3792 unsigned int rotation
= plane_state
->base
.rotation
;
3793 const struct drm_intel_sprite_colorkey
*key
= &plane_state
->ckey
;
3796 plane_ctl
= PLANE_CTL_ENABLE
;
3798 if (INTEL_GEN(dev_priv
) < 10 && !IS_GEMINILAKE(dev_priv
)) {
3799 plane_ctl
|= skl_plane_ctl_alpha(plane_state
);
3800 plane_ctl
|= PLANE_CTL_PLANE_GAMMA_DISABLE
;
3802 if (plane_state
->base
.color_encoding
== DRM_COLOR_YCBCR_BT709
)
3803 plane_ctl
|= PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709
;
3805 if (plane_state
->base
.color_range
== DRM_COLOR_YCBCR_FULL_RANGE
)
3806 plane_ctl
|= PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE
;
3809 plane_ctl
|= skl_plane_ctl_format(fb
->format
->format
);
3810 plane_ctl
|= skl_plane_ctl_tiling(fb
->modifier
);
3811 plane_ctl
|= skl_plane_ctl_rotate(rotation
& DRM_MODE_ROTATE_MASK
);
3813 if (INTEL_GEN(dev_priv
) >= 10)
3814 plane_ctl
|= cnl_plane_ctl_flip(rotation
&
3815 DRM_MODE_REFLECT_MASK
);
3817 if (key
->flags
& I915_SET_COLORKEY_DESTINATION
)
3818 plane_ctl
|= PLANE_CTL_KEY_ENABLE_DESTINATION
;
3819 else if (key
->flags
& I915_SET_COLORKEY_SOURCE
)
3820 plane_ctl
|= PLANE_CTL_KEY_ENABLE_SOURCE
;
3825 u32
glk_plane_color_ctl_crtc(const struct intel_crtc_state
*crtc_state
)
3827 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->base
.crtc
->dev
);
3828 u32 plane_color_ctl
= 0;
3830 if (INTEL_GEN(dev_priv
) >= 11)
3831 return plane_color_ctl
;
3833 if (crtc_state
->gamma_enable
)
3834 plane_color_ctl
|= PLANE_COLOR_PIPE_GAMMA_ENABLE
;
3836 if (crtc_state
->csc_enable
)
3837 plane_color_ctl
|= PLANE_COLOR_PIPE_CSC_ENABLE
;
3839 return plane_color_ctl
;
3842 u32
glk_plane_color_ctl(const struct intel_crtc_state
*crtc_state
,
3843 const struct intel_plane_state
*plane_state
)
3845 struct drm_i915_private
*dev_priv
=
3846 to_i915(plane_state
->base
.plane
->dev
);
3847 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
3848 struct intel_plane
*plane
= to_intel_plane(plane_state
->base
.plane
);
3849 u32 plane_color_ctl
= 0;
3851 plane_color_ctl
|= PLANE_COLOR_PLANE_GAMMA_DISABLE
;
3852 plane_color_ctl
|= glk_plane_color_ctl_alpha(plane_state
);
3854 if (fb
->format
->is_yuv
&& !icl_is_hdr_plane(dev_priv
, plane
->id
)) {
3855 if (plane_state
->base
.color_encoding
== DRM_COLOR_YCBCR_BT709
)
3856 plane_color_ctl
|= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709
;
3858 plane_color_ctl
|= PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709
;
3860 if (plane_state
->base
.color_range
== DRM_COLOR_YCBCR_FULL_RANGE
)
3861 plane_color_ctl
|= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE
;
3862 } else if (fb
->format
->is_yuv
) {
3863 plane_color_ctl
|= PLANE_COLOR_INPUT_CSC_ENABLE
;
3866 return plane_color_ctl
;
3870 __intel_display_resume(struct drm_device
*dev
,
3871 struct drm_atomic_state
*state
,
3872 struct drm_modeset_acquire_ctx
*ctx
)
3874 struct drm_crtc_state
*crtc_state
;
3875 struct drm_crtc
*crtc
;
3878 intel_modeset_setup_hw_state(dev
, ctx
);
3879 i915_redisable_vga(to_i915(dev
));
3885 * We've duplicated the state, pointers to the old state are invalid.
3887 * Don't attempt to use the old state until we commit the duplicated state.
3889 for_each_new_crtc_in_state(state
, crtc
, crtc_state
, i
) {
3891 * Force recalculation even if we restore
3892 * current state. With fast modeset this may not result
3893 * in a modeset when the state is compatible.
3895 crtc_state
->mode_changed
= true;
3898 /* ignore any reset values/BIOS leftovers in the WM registers */
3899 if (!HAS_GMCH(to_i915(dev
)))
3900 to_intel_atomic_state(state
)->skip_intermediate_wm
= true;
3902 ret
= drm_atomic_helper_commit_duplicated_state(state
, ctx
);
3904 WARN_ON(ret
== -EDEADLK
);
3908 static bool gpu_reset_clobbers_display(struct drm_i915_private
*dev_priv
)
3910 return (INTEL_INFO(dev_priv
)->gpu_reset_clobbers_display
&&
3911 intel_has_gpu_reset(dev_priv
));
3914 void intel_prepare_reset(struct drm_i915_private
*dev_priv
)
3916 struct drm_device
*dev
= &dev_priv
->drm
;
3917 struct drm_modeset_acquire_ctx
*ctx
= &dev_priv
->reset_ctx
;
3918 struct drm_atomic_state
*state
;
3921 /* reset doesn't touch the display */
3922 if (!i915_modparams
.force_reset_modeset_test
&&
3923 !gpu_reset_clobbers_display(dev_priv
))
3926 /* We have a modeset vs reset deadlock, defensively unbreak it. */
3927 set_bit(I915_RESET_MODESET
, &dev_priv
->gpu_error
.flags
);
3928 wake_up_all(&dev_priv
->gpu_error
.wait_queue
);
3930 if (atomic_read(&dev_priv
->gpu_error
.pending_fb_pin
)) {
3931 DRM_DEBUG_KMS("Modeset potentially stuck, unbreaking through wedging\n");
3932 i915_gem_set_wedged(dev_priv
);
3936 * Need mode_config.mutex so that we don't
3937 * trample ongoing ->detect() and whatnot.
3939 mutex_lock(&dev
->mode_config
.mutex
);
3940 drm_modeset_acquire_init(ctx
, 0);
3942 ret
= drm_modeset_lock_all_ctx(dev
, ctx
);
3943 if (ret
!= -EDEADLK
)
3946 drm_modeset_backoff(ctx
);
3949 * Disabling the crtcs gracefully seems nicer. Also the
3950 * g33 docs say we should at least disable all the planes.
3952 state
= drm_atomic_helper_duplicate_state(dev
, ctx
);
3953 if (IS_ERR(state
)) {
3954 ret
= PTR_ERR(state
);
3955 DRM_ERROR("Duplicating state failed with %i\n", ret
);
3959 ret
= drm_atomic_helper_disable_all(dev
, ctx
);
3961 DRM_ERROR("Suspending crtc's failed with %i\n", ret
);
3962 drm_atomic_state_put(state
);
3966 dev_priv
->modeset_restore_state
= state
;
3967 state
->acquire_ctx
= ctx
;
3970 void intel_finish_reset(struct drm_i915_private
*dev_priv
)
3972 struct drm_device
*dev
= &dev_priv
->drm
;
3973 struct drm_modeset_acquire_ctx
*ctx
= &dev_priv
->reset_ctx
;
3974 struct drm_atomic_state
*state
;
3977 /* reset doesn't touch the display */
3978 if (!test_bit(I915_RESET_MODESET
, &dev_priv
->gpu_error
.flags
))
3981 state
= fetch_and_zero(&dev_priv
->modeset_restore_state
);
3985 /* reset doesn't touch the display */
3986 if (!gpu_reset_clobbers_display(dev_priv
)) {
3987 /* for testing only restore the display */
3988 ret
= __intel_display_resume(dev
, state
, ctx
);
3990 DRM_ERROR("Restoring old state failed with %i\n", ret
);
3993 * The display has been reset as well,
3994 * so need a full re-initialization.
3996 intel_pps_unlock_regs_wa(dev_priv
);
3997 intel_modeset_init_hw(dev
);
3998 intel_init_clock_gating(dev_priv
);
4000 spin_lock_irq(&dev_priv
->irq_lock
);
4001 if (dev_priv
->display
.hpd_irq_setup
)
4002 dev_priv
->display
.hpd_irq_setup(dev_priv
);
4003 spin_unlock_irq(&dev_priv
->irq_lock
);
4005 ret
= __intel_display_resume(dev
, state
, ctx
);
4007 DRM_ERROR("Restoring old state failed with %i\n", ret
);
4009 intel_hpd_init(dev_priv
);
4012 drm_atomic_state_put(state
);
4014 drm_modeset_drop_locks(ctx
);
4015 drm_modeset_acquire_fini(ctx
);
4016 mutex_unlock(&dev
->mode_config
.mutex
);
4018 clear_bit(I915_RESET_MODESET
, &dev_priv
->gpu_error
.flags
);
4021 static void icl_set_pipe_chicken(struct intel_crtc
*crtc
)
4023 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
4024 enum pipe pipe
= crtc
->pipe
;
4027 tmp
= I915_READ(PIPE_CHICKEN(pipe
));
4030 * Display WA #1153: icl
4031 * enable hardware to bypass the alpha math
4032 * and rounding for per-pixel values 00 and 0xff
4034 tmp
|= PER_PIXEL_ALPHA_BYPASS_EN
;
4036 * Display WA # 1605353570: icl
4037 * Set the pixel rounding bit to 1 for allowing
4038 * passthrough of Frame buffer pixels unmodified
4041 tmp
|= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU
;
4042 I915_WRITE(PIPE_CHICKEN(pipe
), tmp
);
4045 static void intel_update_pipe_config(const struct intel_crtc_state
*old_crtc_state
,
4046 const struct intel_crtc_state
*new_crtc_state
)
4048 struct intel_crtc
*crtc
= to_intel_crtc(new_crtc_state
->base
.crtc
);
4049 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
4051 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
4052 crtc
->base
.mode
= new_crtc_state
->base
.mode
;
4055 * Update pipe size and adjust fitter if needed: the reason for this is
4056 * that in compute_mode_changes we check the native mode (not the pfit
4057 * mode) to see if we can flip rather than do a full mode set. In the
4058 * fastboot case, we'll flip, but if we don't update the pipesrc and
4059 * pfit state, we'll end up with a big fb scanned out into the wrong
4063 I915_WRITE(PIPESRC(crtc
->pipe
),
4064 ((new_crtc_state
->pipe_src_w
- 1) << 16) |
4065 (new_crtc_state
->pipe_src_h
- 1));
4067 /* on skylake this is done by detaching scalers */
4068 if (INTEL_GEN(dev_priv
) >= 9) {
4069 skl_detach_scalers(new_crtc_state
);
4071 if (new_crtc_state
->pch_pfit
.enabled
)
4072 skylake_pfit_enable(new_crtc_state
);
4073 } else if (HAS_PCH_SPLIT(dev_priv
)) {
4074 if (new_crtc_state
->pch_pfit
.enabled
)
4075 ironlake_pfit_enable(new_crtc_state
);
4076 else if (old_crtc_state
->pch_pfit
.enabled
)
4077 ironlake_pfit_disable(old_crtc_state
);
4080 if (INTEL_GEN(dev_priv
) >= 11)
4081 icl_set_pipe_chicken(crtc
);
4084 static void intel_fdi_normal_train(struct intel_crtc
*crtc
)
4086 struct drm_device
*dev
= crtc
->base
.dev
;
4087 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4088 int pipe
= crtc
->pipe
;
4092 /* enable normal train */
4093 reg
= FDI_TX_CTL(pipe
);
4094 temp
= I915_READ(reg
);
4095 if (IS_IVYBRIDGE(dev_priv
)) {
4096 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
4097 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
4099 temp
&= ~FDI_LINK_TRAIN_NONE
;
4100 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
4102 I915_WRITE(reg
, temp
);
4104 reg
= FDI_RX_CTL(pipe
);
4105 temp
= I915_READ(reg
);
4106 if (HAS_PCH_CPT(dev_priv
)) {
4107 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
4108 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
4110 temp
&= ~FDI_LINK_TRAIN_NONE
;
4111 temp
|= FDI_LINK_TRAIN_NONE
;
4113 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
4115 /* wait one idle pattern time */
4119 /* IVB wants error correction enabled */
4120 if (IS_IVYBRIDGE(dev_priv
))
4121 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
4122 FDI_FE_ERRC_ENABLE
);
4125 /* The FDI link training functions for ILK/Ibexpeak. */
4126 static void ironlake_fdi_link_train(struct intel_crtc
*crtc
,
4127 const struct intel_crtc_state
*crtc_state
)
4129 struct drm_device
*dev
= crtc
->base
.dev
;
4130 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4131 int pipe
= crtc
->pipe
;
4135 /* FDI needs bits from pipe first */
4136 assert_pipe_enabled(dev_priv
, pipe
);
4138 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4140 reg
= FDI_RX_IMR(pipe
);
4141 temp
= I915_READ(reg
);
4142 temp
&= ~FDI_RX_SYMBOL_LOCK
;
4143 temp
&= ~FDI_RX_BIT_LOCK
;
4144 I915_WRITE(reg
, temp
);
4148 /* enable CPU FDI TX and PCH FDI RX */
4149 reg
= FDI_TX_CTL(pipe
);
4150 temp
= I915_READ(reg
);
4151 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
4152 temp
|= FDI_DP_PORT_WIDTH(crtc_state
->fdi_lanes
);
4153 temp
&= ~FDI_LINK_TRAIN_NONE
;
4154 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
4155 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
4157 reg
= FDI_RX_CTL(pipe
);
4158 temp
= I915_READ(reg
);
4159 temp
&= ~FDI_LINK_TRAIN_NONE
;
4160 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
4161 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
4166 /* Ironlake workaround, enable clock pointer after FDI enable*/
4167 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
4168 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
4169 FDI_RX_PHASE_SYNC_POINTER_EN
);
4171 reg
= FDI_RX_IIR(pipe
);
4172 for (tries
= 0; tries
< 5; tries
++) {
4173 temp
= I915_READ(reg
);
4174 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
4176 if ((temp
& FDI_RX_BIT_LOCK
)) {
4177 DRM_DEBUG_KMS("FDI train 1 done.\n");
4178 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
4183 DRM_ERROR("FDI train 1 fail!\n");
4186 reg
= FDI_TX_CTL(pipe
);
4187 temp
= I915_READ(reg
);
4188 temp
&= ~FDI_LINK_TRAIN_NONE
;
4189 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
4190 I915_WRITE(reg
, temp
);
4192 reg
= FDI_RX_CTL(pipe
);
4193 temp
= I915_READ(reg
);
4194 temp
&= ~FDI_LINK_TRAIN_NONE
;
4195 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
4196 I915_WRITE(reg
, temp
);
4201 reg
= FDI_RX_IIR(pipe
);
4202 for (tries
= 0; tries
< 5; tries
++) {
4203 temp
= I915_READ(reg
);
4204 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
4206 if (temp
& FDI_RX_SYMBOL_LOCK
) {
4207 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
4208 DRM_DEBUG_KMS("FDI train 2 done.\n");
4213 DRM_ERROR("FDI train 2 fail!\n");
4215 DRM_DEBUG_KMS("FDI train done\n");
4219 static const int snb_b_fdi_train_param
[] = {
4220 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
4221 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
4222 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
4223 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
4226 /* The FDI link training functions for SNB/Cougarpoint. */
4227 static void gen6_fdi_link_train(struct intel_crtc
*crtc
,
4228 const struct intel_crtc_state
*crtc_state
)
4230 struct drm_device
*dev
= crtc
->base
.dev
;
4231 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4232 int pipe
= crtc
->pipe
;
4236 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4238 reg
= FDI_RX_IMR(pipe
);
4239 temp
= I915_READ(reg
);
4240 temp
&= ~FDI_RX_SYMBOL_LOCK
;
4241 temp
&= ~FDI_RX_BIT_LOCK
;
4242 I915_WRITE(reg
, temp
);
4247 /* enable CPU FDI TX and PCH FDI RX */
4248 reg
= FDI_TX_CTL(pipe
);
4249 temp
= I915_READ(reg
);
4250 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
4251 temp
|= FDI_DP_PORT_WIDTH(crtc_state
->fdi_lanes
);
4252 temp
&= ~FDI_LINK_TRAIN_NONE
;
4253 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
4254 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
4256 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
4257 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
4259 I915_WRITE(FDI_RX_MISC(pipe
),
4260 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
4262 reg
= FDI_RX_CTL(pipe
);
4263 temp
= I915_READ(reg
);
4264 if (HAS_PCH_CPT(dev_priv
)) {
4265 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
4266 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
4268 temp
&= ~FDI_LINK_TRAIN_NONE
;
4269 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
4271 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
4276 for (i
= 0; i
< 4; i
++) {
4277 reg
= FDI_TX_CTL(pipe
);
4278 temp
= I915_READ(reg
);
4279 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
4280 temp
|= snb_b_fdi_train_param
[i
];
4281 I915_WRITE(reg
, temp
);
4286 for (retry
= 0; retry
< 5; retry
++) {
4287 reg
= FDI_RX_IIR(pipe
);
4288 temp
= I915_READ(reg
);
4289 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
4290 if (temp
& FDI_RX_BIT_LOCK
) {
4291 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
4292 DRM_DEBUG_KMS("FDI train 1 done.\n");
4301 DRM_ERROR("FDI train 1 fail!\n");
4304 reg
= FDI_TX_CTL(pipe
);
4305 temp
= I915_READ(reg
);
4306 temp
&= ~FDI_LINK_TRAIN_NONE
;
4307 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
4308 if (IS_GEN(dev_priv
, 6)) {
4309 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
4311 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
4313 I915_WRITE(reg
, temp
);
4315 reg
= FDI_RX_CTL(pipe
);
4316 temp
= I915_READ(reg
);
4317 if (HAS_PCH_CPT(dev_priv
)) {
4318 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
4319 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
4321 temp
&= ~FDI_LINK_TRAIN_NONE
;
4322 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
4324 I915_WRITE(reg
, temp
);
4329 for (i
= 0; i
< 4; i
++) {
4330 reg
= FDI_TX_CTL(pipe
);
4331 temp
= I915_READ(reg
);
4332 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
4333 temp
|= snb_b_fdi_train_param
[i
];
4334 I915_WRITE(reg
, temp
);
4339 for (retry
= 0; retry
< 5; retry
++) {
4340 reg
= FDI_RX_IIR(pipe
);
4341 temp
= I915_READ(reg
);
4342 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
4343 if (temp
& FDI_RX_SYMBOL_LOCK
) {
4344 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
4345 DRM_DEBUG_KMS("FDI train 2 done.\n");
4354 DRM_ERROR("FDI train 2 fail!\n");
4356 DRM_DEBUG_KMS("FDI train done.\n");
4359 /* Manual link training for Ivy Bridge A0 parts */
4360 static void ivb_manual_fdi_link_train(struct intel_crtc
*crtc
,
4361 const struct intel_crtc_state
*crtc_state
)
4363 struct drm_device
*dev
= crtc
->base
.dev
;
4364 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4365 int pipe
= crtc
->pipe
;
4369 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4371 reg
= FDI_RX_IMR(pipe
);
4372 temp
= I915_READ(reg
);
4373 temp
&= ~FDI_RX_SYMBOL_LOCK
;
4374 temp
&= ~FDI_RX_BIT_LOCK
;
4375 I915_WRITE(reg
, temp
);
4380 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
4381 I915_READ(FDI_RX_IIR(pipe
)));
4383 /* Try each vswing and preemphasis setting twice before moving on */
4384 for (j
= 0; j
< ARRAY_SIZE(snb_b_fdi_train_param
) * 2; j
++) {
4385 /* disable first in case we need to retry */
4386 reg
= FDI_TX_CTL(pipe
);
4387 temp
= I915_READ(reg
);
4388 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
4389 temp
&= ~FDI_TX_ENABLE
;
4390 I915_WRITE(reg
, temp
);
4392 reg
= FDI_RX_CTL(pipe
);
4393 temp
= I915_READ(reg
);
4394 temp
&= ~FDI_LINK_TRAIN_AUTO
;
4395 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
4396 temp
&= ~FDI_RX_ENABLE
;
4397 I915_WRITE(reg
, temp
);
4399 /* enable CPU FDI TX and PCH FDI RX */
4400 reg
= FDI_TX_CTL(pipe
);
4401 temp
= I915_READ(reg
);
4402 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
4403 temp
|= FDI_DP_PORT_WIDTH(crtc_state
->fdi_lanes
);
4404 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
4405 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
4406 temp
|= snb_b_fdi_train_param
[j
/2];
4407 temp
|= FDI_COMPOSITE_SYNC
;
4408 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
4410 I915_WRITE(FDI_RX_MISC(pipe
),
4411 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
4413 reg
= FDI_RX_CTL(pipe
);
4414 temp
= I915_READ(reg
);
4415 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
4416 temp
|= FDI_COMPOSITE_SYNC
;
4417 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
4420 udelay(1); /* should be 0.5us */
4422 for (i
= 0; i
< 4; i
++) {
4423 reg
= FDI_RX_IIR(pipe
);
4424 temp
= I915_READ(reg
);
4425 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
4427 if (temp
& FDI_RX_BIT_LOCK
||
4428 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
4429 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
4430 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4434 udelay(1); /* should be 0.5us */
4437 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j
/ 2);
4442 reg
= FDI_TX_CTL(pipe
);
4443 temp
= I915_READ(reg
);
4444 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
4445 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
4446 I915_WRITE(reg
, temp
);
4448 reg
= FDI_RX_CTL(pipe
);
4449 temp
= I915_READ(reg
);
4450 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
4451 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
4452 I915_WRITE(reg
, temp
);
4455 udelay(2); /* should be 1.5us */
4457 for (i
= 0; i
< 4; i
++) {
4458 reg
= FDI_RX_IIR(pipe
);
4459 temp
= I915_READ(reg
);
4460 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
4462 if (temp
& FDI_RX_SYMBOL_LOCK
||
4463 (I915_READ(reg
) & FDI_RX_SYMBOL_LOCK
)) {
4464 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
4465 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4469 udelay(2); /* should be 1.5us */
4472 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j
/ 2);
4476 DRM_DEBUG_KMS("FDI train done.\n");
4479 static void ironlake_fdi_pll_enable(const struct intel_crtc_state
*crtc_state
)
4481 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
4482 struct drm_i915_private
*dev_priv
= to_i915(intel_crtc
->base
.dev
);
4483 int pipe
= intel_crtc
->pipe
;
4487 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4488 reg
= FDI_RX_CTL(pipe
);
4489 temp
= I915_READ(reg
);
4490 temp
&= ~(FDI_DP_PORT_WIDTH_MASK
| (0x7 << 16));
4491 temp
|= FDI_DP_PORT_WIDTH(crtc_state
->fdi_lanes
);
4492 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
4493 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
4498 /* Switch from Rawclk to PCDclk */
4499 temp
= I915_READ(reg
);
4500 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
4505 /* Enable CPU FDI TX PLL, always on for Ironlake */
4506 reg
= FDI_TX_CTL(pipe
);
4507 temp
= I915_READ(reg
);
4508 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
4509 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
4516 static void ironlake_fdi_pll_disable(struct intel_crtc
*intel_crtc
)
4518 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4519 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4520 int pipe
= intel_crtc
->pipe
;
4524 /* Switch from PCDclk to Rawclk */
4525 reg
= FDI_RX_CTL(pipe
);
4526 temp
= I915_READ(reg
);
4527 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
4529 /* Disable CPU FDI TX PLL */
4530 reg
= FDI_TX_CTL(pipe
);
4531 temp
= I915_READ(reg
);
4532 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
4537 reg
= FDI_RX_CTL(pipe
);
4538 temp
= I915_READ(reg
);
4539 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
4541 /* Wait for the clocks to turn off. */
4546 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
4548 struct drm_device
*dev
= crtc
->dev
;
4549 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4550 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4551 int pipe
= intel_crtc
->pipe
;
4555 /* disable CPU FDI tx and PCH FDI rx */
4556 reg
= FDI_TX_CTL(pipe
);
4557 temp
= I915_READ(reg
);
4558 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
4561 reg
= FDI_RX_CTL(pipe
);
4562 temp
= I915_READ(reg
);
4563 temp
&= ~(0x7 << 16);
4564 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
4565 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
4570 /* Ironlake workaround, disable clock pointer after downing FDI */
4571 if (HAS_PCH_IBX(dev_priv
))
4572 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
4574 /* still set train pattern 1 */
4575 reg
= FDI_TX_CTL(pipe
);
4576 temp
= I915_READ(reg
);
4577 temp
&= ~FDI_LINK_TRAIN_NONE
;
4578 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
4579 I915_WRITE(reg
, temp
);
4581 reg
= FDI_RX_CTL(pipe
);
4582 temp
= I915_READ(reg
);
4583 if (HAS_PCH_CPT(dev_priv
)) {
4584 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
4585 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
4587 temp
&= ~FDI_LINK_TRAIN_NONE
;
4588 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
4590 /* BPC in FDI rx is consistent with that in PIPECONF */
4591 temp
&= ~(0x07 << 16);
4592 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
4593 I915_WRITE(reg
, temp
);
4599 bool intel_has_pending_fb_unpin(struct drm_i915_private
*dev_priv
)
4601 struct drm_crtc
*crtc
;
4604 drm_for_each_crtc(crtc
, &dev_priv
->drm
) {
4605 struct drm_crtc_commit
*commit
;
4606 spin_lock(&crtc
->commit_lock
);
4607 commit
= list_first_entry_or_null(&crtc
->commit_list
,
4608 struct drm_crtc_commit
, commit_entry
);
4609 cleanup_done
= commit
?
4610 try_wait_for_completion(&commit
->cleanup_done
) : true;
4611 spin_unlock(&crtc
->commit_lock
);
4616 drm_crtc_wait_one_vblank(crtc
);
4624 void lpt_disable_iclkip(struct drm_i915_private
*dev_priv
)
4628 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_GATE
);
4630 mutex_lock(&dev_priv
->sb_lock
);
4632 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
4633 temp
|= SBI_SSCCTL_DISABLE
;
4634 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
4636 mutex_unlock(&dev_priv
->sb_lock
);
4639 /* Program iCLKIP clock to the desired frequency */
4640 static void lpt_program_iclkip(const struct intel_crtc_state
*crtc_state
)
4642 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
4643 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
4644 int clock
= crtc_state
->base
.adjusted_mode
.crtc_clock
;
4645 u32 divsel
, phaseinc
, auxdiv
, phasedir
= 0;
4648 lpt_disable_iclkip(dev_priv
);
4650 /* The iCLK virtual clock root frequency is in MHz,
4651 * but the adjusted_mode->crtc_clock in in KHz. To get the
4652 * divisors, it is necessary to divide one by another, so we
4653 * convert the virtual clock precision to KHz here for higher
4656 for (auxdiv
= 0; auxdiv
< 2; auxdiv
++) {
4657 u32 iclk_virtual_root_freq
= 172800 * 1000;
4658 u32 iclk_pi_range
= 64;
4659 u32 desired_divisor
;
4661 desired_divisor
= DIV_ROUND_CLOSEST(iclk_virtual_root_freq
,
4663 divsel
= (desired_divisor
/ iclk_pi_range
) - 2;
4664 phaseinc
= desired_divisor
% iclk_pi_range
;
4667 * Near 20MHz is a corner case which is
4668 * out of range for the 7-bit divisor
4674 /* This should not happen with any sane values */
4675 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel
) &
4676 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
);
4677 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir
) &
4678 ~SBI_SSCDIVINTPHASE_INCVAL_MASK
);
4680 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4687 mutex_lock(&dev_priv
->sb_lock
);
4689 /* Program SSCDIVINTPHASE6 */
4690 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
4691 temp
&= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
;
4692 temp
|= SBI_SSCDIVINTPHASE_DIVSEL(divsel
);
4693 temp
&= ~SBI_SSCDIVINTPHASE_INCVAL_MASK
;
4694 temp
|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc
);
4695 temp
|= SBI_SSCDIVINTPHASE_DIR(phasedir
);
4696 temp
|= SBI_SSCDIVINTPHASE_PROPAGATE
;
4697 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE6
, temp
, SBI_ICLK
);
4699 /* Program SSCAUXDIV */
4700 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
4701 temp
&= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4702 temp
|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv
);
4703 intel_sbi_write(dev_priv
, SBI_SSCAUXDIV6
, temp
, SBI_ICLK
);
4705 /* Enable modulator and associated divider */
4706 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
4707 temp
&= ~SBI_SSCCTL_DISABLE
;
4708 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
4710 mutex_unlock(&dev_priv
->sb_lock
);
4712 /* Wait for initialization time */
4715 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_UNGATE
);
4718 int lpt_get_iclkip(struct drm_i915_private
*dev_priv
)
4720 u32 divsel
, phaseinc
, auxdiv
;
4721 u32 iclk_virtual_root_freq
= 172800 * 1000;
4722 u32 iclk_pi_range
= 64;
4723 u32 desired_divisor
;
4726 if ((I915_READ(PIXCLK_GATE
) & PIXCLK_GATE_UNGATE
) == 0)
4729 mutex_lock(&dev_priv
->sb_lock
);
4731 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
4732 if (temp
& SBI_SSCCTL_DISABLE
) {
4733 mutex_unlock(&dev_priv
->sb_lock
);
4737 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
4738 divsel
= (temp
& SBI_SSCDIVINTPHASE_DIVSEL_MASK
) >>
4739 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT
;
4740 phaseinc
= (temp
& SBI_SSCDIVINTPHASE_INCVAL_MASK
) >>
4741 SBI_SSCDIVINTPHASE_INCVAL_SHIFT
;
4743 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
4744 auxdiv
= (temp
& SBI_SSCAUXDIV_FINALDIV2SEL_MASK
) >>
4745 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT
;
4747 mutex_unlock(&dev_priv
->sb_lock
);
4749 desired_divisor
= (divsel
+ 2) * iclk_pi_range
+ phaseinc
;
4751 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq
,
4752 desired_divisor
<< auxdiv
);
4755 static void ironlake_pch_transcoder_set_timings(const struct intel_crtc_state
*crtc_state
,
4756 enum pipe pch_transcoder
)
4758 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
4759 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
4760 enum transcoder cpu_transcoder
= crtc_state
->cpu_transcoder
;
4762 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder
),
4763 I915_READ(HTOTAL(cpu_transcoder
)));
4764 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder
),
4765 I915_READ(HBLANK(cpu_transcoder
)));
4766 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder
),
4767 I915_READ(HSYNC(cpu_transcoder
)));
4769 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder
),
4770 I915_READ(VTOTAL(cpu_transcoder
)));
4771 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder
),
4772 I915_READ(VBLANK(cpu_transcoder
)));
4773 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder
),
4774 I915_READ(VSYNC(cpu_transcoder
)));
4775 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder
),
4776 I915_READ(VSYNCSHIFT(cpu_transcoder
)));
4779 static void cpt_set_fdi_bc_bifurcation(struct drm_i915_private
*dev_priv
, bool enable
)
4783 temp
= I915_READ(SOUTH_CHICKEN1
);
4784 if (!!(temp
& FDI_BC_BIFURCATION_SELECT
) == enable
)
4787 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
4788 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
4790 temp
&= ~FDI_BC_BIFURCATION_SELECT
;
4792 temp
|= FDI_BC_BIFURCATION_SELECT
;
4794 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable
? "en" : "dis");
4795 I915_WRITE(SOUTH_CHICKEN1
, temp
);
4796 POSTING_READ(SOUTH_CHICKEN1
);
4799 static void ivybridge_update_fdi_bc_bifurcation(const struct intel_crtc_state
*crtc_state
)
4801 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
4802 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
4804 switch (crtc
->pipe
) {
4808 if (crtc_state
->fdi_lanes
> 2)
4809 cpt_set_fdi_bc_bifurcation(dev_priv
, false);
4811 cpt_set_fdi_bc_bifurcation(dev_priv
, true);
4815 cpt_set_fdi_bc_bifurcation(dev_priv
, true);
4824 * Finds the encoder associated with the given CRTC. This can only be
4825 * used when we know that the CRTC isn't feeding multiple encoders!
4827 static struct intel_encoder
*
4828 intel_get_crtc_new_encoder(const struct intel_atomic_state
*state
,
4829 const struct intel_crtc_state
*crtc_state
)
4831 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
4832 const struct drm_connector_state
*connector_state
;
4833 const struct drm_connector
*connector
;
4834 struct intel_encoder
*encoder
= NULL
;
4835 int num_encoders
= 0;
4838 for_each_new_connector_in_state(&state
->base
, connector
, connector_state
, i
) {
4839 if (connector_state
->crtc
!= &crtc
->base
)
4842 encoder
= to_intel_encoder(connector_state
->best_encoder
);
4846 WARN(num_encoders
!= 1, "%d encoders for pipe %c\n",
4847 num_encoders
, pipe_name(crtc
->pipe
));
4853 * Enable PCH resources required for PCH ports:
4855 * - FDI training & RX/TX
4856 * - update transcoder timings
4857 * - DP transcoding bits
4860 static void ironlake_pch_enable(const struct intel_atomic_state
*state
,
4861 const struct intel_crtc_state
*crtc_state
)
4863 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
4864 struct drm_device
*dev
= crtc
->base
.dev
;
4865 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4866 int pipe
= crtc
->pipe
;
4869 assert_pch_transcoder_disabled(dev_priv
, pipe
);
4871 if (IS_IVYBRIDGE(dev_priv
))
4872 ivybridge_update_fdi_bc_bifurcation(crtc_state
);
4874 /* Write the TU size bits before fdi link training, so that error
4875 * detection works. */
4876 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
4877 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
4879 /* For PCH output, training FDI link */
4880 dev_priv
->display
.fdi_link_train(crtc
, crtc_state
);
4882 /* We need to program the right clock selection before writing the pixel
4883 * mutliplier into the DPLL. */
4884 if (HAS_PCH_CPT(dev_priv
)) {
4887 temp
= I915_READ(PCH_DPLL_SEL
);
4888 temp
|= TRANS_DPLL_ENABLE(pipe
);
4889 sel
= TRANS_DPLLB_SEL(pipe
);
4890 if (crtc_state
->shared_dpll
==
4891 intel_get_shared_dpll_by_id(dev_priv
, DPLL_ID_PCH_PLL_B
))
4895 I915_WRITE(PCH_DPLL_SEL
, temp
);
4898 /* XXX: pch pll's can be enabled any time before we enable the PCH
4899 * transcoder, and we actually should do this to not upset any PCH
4900 * transcoder that already use the clock when we share it.
4902 * Note that enable_shared_dpll tries to do the right thing, but
4903 * get_shared_dpll unconditionally resets the pll - we need that to have
4904 * the right LVDS enable sequence. */
4905 intel_enable_shared_dpll(crtc_state
);
4907 /* set transcoder timing, panel must allow it */
4908 assert_panel_unlocked(dev_priv
, pipe
);
4909 ironlake_pch_transcoder_set_timings(crtc_state
, pipe
);
4911 intel_fdi_normal_train(crtc
);
4913 /* For PCH DP, enable TRANS_DP_CTL */
4914 if (HAS_PCH_CPT(dev_priv
) &&
4915 intel_crtc_has_dp_encoder(crtc_state
)) {
4916 const struct drm_display_mode
*adjusted_mode
=
4917 &crtc_state
->base
.adjusted_mode
;
4918 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) >> 5;
4919 i915_reg_t reg
= TRANS_DP_CTL(pipe
);
4922 temp
= I915_READ(reg
);
4923 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
4924 TRANS_DP_SYNC_MASK
|
4926 temp
|= TRANS_DP_OUTPUT_ENABLE
;
4927 temp
|= bpc
<< 9; /* same format but at 11:9 */
4929 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
4930 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
4931 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
4932 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
4934 port
= intel_get_crtc_new_encoder(state
, crtc_state
)->port
;
4935 WARN_ON(port
< PORT_B
|| port
> PORT_D
);
4936 temp
|= TRANS_DP_PORT_SEL(port
);
4938 I915_WRITE(reg
, temp
);
4941 ironlake_enable_pch_transcoder(crtc_state
);
4944 static void lpt_pch_enable(const struct intel_atomic_state
*state
,
4945 const struct intel_crtc_state
*crtc_state
)
4947 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
4948 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
4949 enum transcoder cpu_transcoder
= crtc_state
->cpu_transcoder
;
4951 assert_pch_transcoder_disabled(dev_priv
, PIPE_A
);
4953 lpt_program_iclkip(crtc_state
);
4955 /* Set transcoder timing. */
4956 ironlake_pch_transcoder_set_timings(crtc_state
, PIPE_A
);
4958 lpt_enable_pch_transcoder(dev_priv
, cpu_transcoder
);
4961 static void cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
4963 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4964 i915_reg_t dslreg
= PIPEDSL(pipe
);
4967 temp
= I915_READ(dslreg
);
4969 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
4970 if (wait_for(I915_READ(dslreg
) != temp
, 5))
4971 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe
));
4976 * The hardware phase 0.0 refers to the center of the pixel.
4977 * We want to start from the top/left edge which is phase
4978 * -0.5. That matches how the hardware calculates the scaling
4979 * factors (from top-left of the first pixel to bottom-right
4980 * of the last pixel, as opposed to the pixel centers).
4982 * For 4:2:0 subsampled chroma planes we obviously have to
4983 * adjust that so that the chroma sample position lands in
4986 * Note that for packed YCbCr 4:2:2 formats there is no way to
4987 * control chroma siting. The hardware simply replicates the
4988 * chroma samples for both of the luma samples, and thus we don't
4989 * actually get the expected MPEG2 chroma siting convention :(
4990 * The same behaviour is observed on pre-SKL platforms as well.
4992 * Theory behind the formula (note that we ignore sub-pixel
4993 * source coordinates):
4994 * s = source sample position
4995 * d = destination sample position
5000 * | | 1.5 (initial phase)
5008 * | -0.375 (initial phase)
5015 u16
skl_scaler_calc_phase(int sub
, int scale
, bool chroma_cosited
)
5017 int phase
= -0x8000;
5021 phase
+= (sub
- 1) * 0x8000 / sub
;
5023 phase
+= scale
/ (2 * sub
);
5026 * Hardware initial phase limited to [-0.5:1.5].
5027 * Since the max hardware scale factor is 3.0, we
5028 * should never actually excdeed 1.0 here.
5030 WARN_ON(phase
< -0x8000 || phase
> 0x18000);
5033 phase
= 0x10000 + phase
;
5035 trip
= PS_PHASE_TRIP
;
5037 return ((phase
>> 2) & PS_PHASE_MASK
) | trip
;
5041 skl_update_scaler(struct intel_crtc_state
*crtc_state
, bool force_detach
,
5042 unsigned int scaler_user
, int *scaler_id
,
5043 int src_w
, int src_h
, int dst_w
, int dst_h
,
5044 const struct drm_format_info
*format
, bool need_scaler
)
5046 struct intel_crtc_scaler_state
*scaler_state
=
5047 &crtc_state
->scaler_state
;
5048 struct intel_crtc
*intel_crtc
=
5049 to_intel_crtc(crtc_state
->base
.crtc
);
5050 struct drm_i915_private
*dev_priv
= to_i915(intel_crtc
->base
.dev
);
5051 const struct drm_display_mode
*adjusted_mode
=
5052 &crtc_state
->base
.adjusted_mode
;
5055 * Src coordinates are already rotated by 270 degrees for
5056 * the 90/270 degree plane rotation cases (to match the
5057 * GTT mapping), hence no need to account for rotation here.
5059 if (src_w
!= dst_w
|| src_h
!= dst_h
)
5063 * Scaling/fitting not supported in IF-ID mode in GEN9+
5064 * TODO: Interlace fetch mode doesn't support YUV420 planar formats.
5065 * Once NV12 is enabled, handle it here while allocating scaler
5068 if (INTEL_GEN(dev_priv
) >= 9 && crtc_state
->base
.enable
&&
5069 need_scaler
&& adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
5070 DRM_DEBUG_KMS("Pipe/Plane scaling not supported with IF-ID mode\n");
5075 * if plane is being disabled or scaler is no more required or force detach
5076 * - free scaler binded to this plane/crtc
5077 * - in order to do this, update crtc->scaler_usage
5079 * Here scaler state in crtc_state is set free so that
5080 * scaler can be assigned to other user. Actual register
5081 * update to free the scaler is done in plane/panel-fit programming.
5082 * For this purpose crtc/plane_state->scaler_id isn't reset here.
5084 if (force_detach
|| !need_scaler
) {
5085 if (*scaler_id
>= 0) {
5086 scaler_state
->scaler_users
&= ~(1 << scaler_user
);
5087 scaler_state
->scalers
[*scaler_id
].in_use
= 0;
5089 DRM_DEBUG_KMS("scaler_user index %u.%u: "
5090 "Staged freeing scaler id %d scaler_users = 0x%x\n",
5091 intel_crtc
->pipe
, scaler_user
, *scaler_id
,
5092 scaler_state
->scaler_users
);
5098 if (format
&& is_planar_yuv_format(format
->format
) &&
5099 (src_h
< SKL_MIN_YUV_420_SRC_H
|| src_w
< SKL_MIN_YUV_420_SRC_W
)) {
5100 DRM_DEBUG_KMS("Planar YUV: src dimensions not met\n");
5105 if (src_w
< SKL_MIN_SRC_W
|| src_h
< SKL_MIN_SRC_H
||
5106 dst_w
< SKL_MIN_DST_W
|| dst_h
< SKL_MIN_DST_H
||
5107 (INTEL_GEN(dev_priv
) >= 11 &&
5108 (src_w
> ICL_MAX_SRC_W
|| src_h
> ICL_MAX_SRC_H
||
5109 dst_w
> ICL_MAX_DST_W
|| dst_h
> ICL_MAX_DST_H
)) ||
5110 (INTEL_GEN(dev_priv
) < 11 &&
5111 (src_w
> SKL_MAX_SRC_W
|| src_h
> SKL_MAX_SRC_H
||
5112 dst_w
> SKL_MAX_DST_W
|| dst_h
> SKL_MAX_DST_H
))) {
5113 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
5114 "size is out of scaler range\n",
5115 intel_crtc
->pipe
, scaler_user
, src_w
, src_h
, dst_w
, dst_h
);
5119 /* mark this plane as a scaler user in crtc_state */
5120 scaler_state
->scaler_users
|= (1 << scaler_user
);
5121 DRM_DEBUG_KMS("scaler_user index %u.%u: "
5122 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
5123 intel_crtc
->pipe
, scaler_user
, src_w
, src_h
, dst_w
, dst_h
,
5124 scaler_state
->scaler_users
);
5130 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
5132 * @state: crtc's scaler state
5135 * 0 - scaler_usage updated successfully
5136 * error - requested scaling cannot be supported or other error condition
5138 int skl_update_scaler_crtc(struct intel_crtc_state
*state
)
5140 const struct drm_display_mode
*adjusted_mode
= &state
->base
.adjusted_mode
;
5141 bool need_scaler
= false;
5143 if (state
->output_format
== INTEL_OUTPUT_FORMAT_YCBCR420
)
5146 return skl_update_scaler(state
, !state
->base
.active
, SKL_CRTC_INDEX
,
5147 &state
->scaler_state
.scaler_id
,
5148 state
->pipe_src_w
, state
->pipe_src_h
,
5149 adjusted_mode
->crtc_hdisplay
,
5150 adjusted_mode
->crtc_vdisplay
, NULL
, need_scaler
);
5154 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
5155 * @crtc_state: crtc's scaler state
5156 * @plane_state: atomic plane state to update
5159 * 0 - scaler_usage updated successfully
5160 * error - requested scaling cannot be supported or other error condition
5162 static int skl_update_scaler_plane(struct intel_crtc_state
*crtc_state
,
5163 struct intel_plane_state
*plane_state
)
5165 struct intel_plane
*intel_plane
=
5166 to_intel_plane(plane_state
->base
.plane
);
5167 struct drm_i915_private
*dev_priv
= to_i915(intel_plane
->base
.dev
);
5168 struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
5170 bool force_detach
= !fb
|| !plane_state
->base
.visible
;
5171 bool need_scaler
= false;
5173 /* Pre-gen11 and SDR planes always need a scaler for planar formats. */
5174 if (!icl_is_hdr_plane(dev_priv
, intel_plane
->id
) &&
5175 fb
&& is_planar_yuv_format(fb
->format
->format
))
5178 ret
= skl_update_scaler(crtc_state
, force_detach
,
5179 drm_plane_index(&intel_plane
->base
),
5180 &plane_state
->scaler_id
,
5181 drm_rect_width(&plane_state
->base
.src
) >> 16,
5182 drm_rect_height(&plane_state
->base
.src
) >> 16,
5183 drm_rect_width(&plane_state
->base
.dst
),
5184 drm_rect_height(&plane_state
->base
.dst
),
5185 fb
? fb
->format
: NULL
, need_scaler
);
5187 if (ret
|| plane_state
->scaler_id
< 0)
5190 /* check colorkey */
5191 if (plane_state
->ckey
.flags
) {
5192 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
5193 intel_plane
->base
.base
.id
,
5194 intel_plane
->base
.name
);
5198 /* Check src format */
5199 switch (fb
->format
->format
) {
5200 case DRM_FORMAT_RGB565
:
5201 case DRM_FORMAT_XBGR8888
:
5202 case DRM_FORMAT_XRGB8888
:
5203 case DRM_FORMAT_ABGR8888
:
5204 case DRM_FORMAT_ARGB8888
:
5205 case DRM_FORMAT_XRGB2101010
:
5206 case DRM_FORMAT_XBGR2101010
:
5207 case DRM_FORMAT_XBGR16161616F
:
5208 case DRM_FORMAT_ABGR16161616F
:
5209 case DRM_FORMAT_XRGB16161616F
:
5210 case DRM_FORMAT_ARGB16161616F
:
5211 case DRM_FORMAT_YUYV
:
5212 case DRM_FORMAT_YVYU
:
5213 case DRM_FORMAT_UYVY
:
5214 case DRM_FORMAT_VYUY
:
5215 case DRM_FORMAT_NV12
:
5216 case DRM_FORMAT_P010
:
5217 case DRM_FORMAT_P012
:
5218 case DRM_FORMAT_P016
:
5219 case DRM_FORMAT_Y210
:
5220 case DRM_FORMAT_Y212
:
5221 case DRM_FORMAT_Y216
:
5222 case DRM_FORMAT_XVYU2101010
:
5223 case DRM_FORMAT_XVYU12_16161616
:
5224 case DRM_FORMAT_XVYU16161616
:
5227 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
5228 intel_plane
->base
.base
.id
, intel_plane
->base
.name
,
5229 fb
->base
.id
, fb
->format
->format
);
5236 static void skylake_scaler_disable(struct intel_crtc
*crtc
)
5240 for (i
= 0; i
< crtc
->num_scalers
; i
++)
5241 skl_detach_scaler(crtc
, i
);
5244 static void skylake_pfit_enable(const struct intel_crtc_state
*crtc_state
)
5246 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
5247 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
5248 enum pipe pipe
= crtc
->pipe
;
5249 const struct intel_crtc_scaler_state
*scaler_state
=
5250 &crtc_state
->scaler_state
;
5252 if (crtc_state
->pch_pfit
.enabled
) {
5253 u16 uv_rgb_hphase
, uv_rgb_vphase
;
5254 int pfit_w
, pfit_h
, hscale
, vscale
;
5257 if (WARN_ON(crtc_state
->scaler_state
.scaler_id
< 0))
5260 pfit_w
= (crtc_state
->pch_pfit
.size
>> 16) & 0xFFFF;
5261 pfit_h
= crtc_state
->pch_pfit
.size
& 0xFFFF;
5263 hscale
= (crtc_state
->pipe_src_w
<< 16) / pfit_w
;
5264 vscale
= (crtc_state
->pipe_src_h
<< 16) / pfit_h
;
5266 uv_rgb_hphase
= skl_scaler_calc_phase(1, hscale
, false);
5267 uv_rgb_vphase
= skl_scaler_calc_phase(1, vscale
, false);
5269 id
= scaler_state
->scaler_id
;
5270 I915_WRITE(SKL_PS_CTRL(pipe
, id
), PS_SCALER_EN
|
5271 PS_FILTER_MEDIUM
| scaler_state
->scalers
[id
].mode
);
5272 I915_WRITE_FW(SKL_PS_VPHASE(pipe
, id
),
5273 PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase
));
5274 I915_WRITE_FW(SKL_PS_HPHASE(pipe
, id
),
5275 PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase
));
5276 I915_WRITE(SKL_PS_WIN_POS(pipe
, id
), crtc_state
->pch_pfit
.pos
);
5277 I915_WRITE(SKL_PS_WIN_SZ(pipe
, id
), crtc_state
->pch_pfit
.size
);
5281 static void ironlake_pfit_enable(const struct intel_crtc_state
*crtc_state
)
5283 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
5284 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
5285 int pipe
= crtc
->pipe
;
5287 if (crtc_state
->pch_pfit
.enabled
) {
5288 /* Force use of hard-coded filter coefficients
5289 * as some pre-programmed values are broken,
5292 if (IS_IVYBRIDGE(dev_priv
) || IS_HASWELL(dev_priv
))
5293 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
|
5294 PF_PIPE_SEL_IVB(pipe
));
5296 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
5297 I915_WRITE(PF_WIN_POS(pipe
), crtc_state
->pch_pfit
.pos
);
5298 I915_WRITE(PF_WIN_SZ(pipe
), crtc_state
->pch_pfit
.size
);
5302 void hsw_enable_ips(const struct intel_crtc_state
*crtc_state
)
5304 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
5305 struct drm_device
*dev
= crtc
->base
.dev
;
5306 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5308 if (!crtc_state
->ips_enabled
)
5312 * We can only enable IPS after we enable a plane and wait for a vblank
5313 * This function is called from post_plane_update, which is run after
5316 WARN_ON(!(crtc_state
->active_planes
& ~BIT(PLANE_CURSOR
)));
5318 if (IS_BROADWELL(dev_priv
)) {
5319 mutex_lock(&dev_priv
->pcu_lock
);
5320 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
,
5321 IPS_ENABLE
| IPS_PCODE_CONTROL
));
5322 mutex_unlock(&dev_priv
->pcu_lock
);
5323 /* Quoting Art Runyan: "its not safe to expect any particular
5324 * value in IPS_CTL bit 31 after enabling IPS through the
5325 * mailbox." Moreover, the mailbox may return a bogus state,
5326 * so we need to just enable it and continue on.
5329 I915_WRITE(IPS_CTL
, IPS_ENABLE
);
5330 /* The bit only becomes 1 in the next vblank, so this wait here
5331 * is essentially intel_wait_for_vblank. If we don't have this
5332 * and don't wait for vblanks until the end of crtc_enable, then
5333 * the HW state readout code will complain that the expected
5334 * IPS_CTL value is not the one we read. */
5335 if (intel_wait_for_register(&dev_priv
->uncore
,
5336 IPS_CTL
, IPS_ENABLE
, IPS_ENABLE
,
5338 DRM_ERROR("Timed out waiting for IPS enable\n");
5342 void hsw_disable_ips(const struct intel_crtc_state
*crtc_state
)
5344 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
5345 struct drm_device
*dev
= crtc
->base
.dev
;
5346 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5348 if (!crtc_state
->ips_enabled
)
5351 if (IS_BROADWELL(dev_priv
)) {
5352 mutex_lock(&dev_priv
->pcu_lock
);
5353 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0));
5354 mutex_unlock(&dev_priv
->pcu_lock
);
5356 * Wait for PCODE to finish disabling IPS. The BSpec specified
5357 * 42ms timeout value leads to occasional timeouts so use 100ms
5360 if (intel_wait_for_register(&dev_priv
->uncore
,
5361 IPS_CTL
, IPS_ENABLE
, 0,
5363 DRM_ERROR("Timed out waiting for IPS disable\n");
5365 I915_WRITE(IPS_CTL
, 0);
5366 POSTING_READ(IPS_CTL
);
5369 /* We need to wait for a vblank before we can disable the plane. */
5370 intel_wait_for_vblank(dev_priv
, crtc
->pipe
);
5373 static void intel_crtc_dpms_overlay_disable(struct intel_crtc
*intel_crtc
)
5375 if (intel_crtc
->overlay
) {
5376 struct drm_device
*dev
= intel_crtc
->base
.dev
;
5378 mutex_lock(&dev
->struct_mutex
);
5379 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
5380 mutex_unlock(&dev
->struct_mutex
);
5383 /* Let userspace switch the overlay on again. In most cases userspace
5384 * has to recompute where to put it anyway.
5389 * intel_post_enable_primary - Perform operations after enabling primary plane
5390 * @crtc: the CRTC whose primary plane was just enabled
5391 * @new_crtc_state: the enabling state
5393 * Performs potentially sleeping operations that must be done after the primary
5394 * plane is enabled, such as updating FBC and IPS. Note that this may be
5395 * called due to an explicit primary plane update, or due to an implicit
5396 * re-enable that is caused when a sprite plane is updated to no longer
5397 * completely hide the primary plane.
5400 intel_post_enable_primary(struct drm_crtc
*crtc
,
5401 const struct intel_crtc_state
*new_crtc_state
)
5403 struct drm_device
*dev
= crtc
->dev
;
5404 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5405 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5406 int pipe
= intel_crtc
->pipe
;
5409 * Gen2 reports pipe underruns whenever all planes are disabled.
5410 * So don't enable underrun reporting before at least some planes
5412 * FIXME: Need to fix the logic to work when we turn off all planes
5413 * but leave the pipe running.
5415 if (IS_GEN(dev_priv
, 2))
5416 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
5418 /* Underruns don't always raise interrupts, so check manually. */
5419 intel_check_cpu_fifo_underruns(dev_priv
);
5420 intel_check_pch_fifo_underruns(dev_priv
);
5423 /* FIXME get rid of this and use pre_plane_update */
5425 intel_pre_disable_primary_noatomic(struct drm_crtc
*crtc
)
5427 struct drm_device
*dev
= crtc
->dev
;
5428 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5429 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5430 int pipe
= intel_crtc
->pipe
;
5433 * Gen2 reports pipe underruns whenever all planes are disabled.
5434 * So disable underrun reporting before all the planes get disabled.
5436 if (IS_GEN(dev_priv
, 2))
5437 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
5439 hsw_disable_ips(to_intel_crtc_state(crtc
->state
));
5442 * Vblank time updates from the shadow to live plane control register
5443 * are blocked if the memory self-refresh mode is active at that
5444 * moment. So to make sure the plane gets truly disabled, disable
5445 * first the self-refresh mode. The self-refresh enable bit in turn
5446 * will be checked/applied by the HW only at the next frame start
5447 * event which is after the vblank start event, so we need to have a
5448 * wait-for-vblank between disabling the plane and the pipe.
5450 if (HAS_GMCH(dev_priv
) &&
5451 intel_set_memory_cxsr(dev_priv
, false))
5452 intel_wait_for_vblank(dev_priv
, pipe
);
5455 static bool hsw_pre_update_disable_ips(const struct intel_crtc_state
*old_crtc_state
,
5456 const struct intel_crtc_state
*new_crtc_state
)
5458 struct intel_crtc
*crtc
= to_intel_crtc(new_crtc_state
->base
.crtc
);
5459 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
5461 if (!old_crtc_state
->ips_enabled
)
5464 if (needs_modeset(&new_crtc_state
->base
))
5468 * Workaround : Do not read or write the pipe palette/gamma data while
5469 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
5471 * Disable IPS before we program the LUT.
5473 if (IS_HASWELL(dev_priv
) &&
5474 (new_crtc_state
->base
.color_mgmt_changed
||
5475 new_crtc_state
->update_pipe
) &&
5476 new_crtc_state
->gamma_mode
== GAMMA_MODE_MODE_SPLIT
)
5479 return !new_crtc_state
->ips_enabled
;
5482 static bool hsw_post_update_enable_ips(const struct intel_crtc_state
*old_crtc_state
,
5483 const struct intel_crtc_state
*new_crtc_state
)
5485 struct intel_crtc
*crtc
= to_intel_crtc(new_crtc_state
->base
.crtc
);
5486 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
5488 if (!new_crtc_state
->ips_enabled
)
5491 if (needs_modeset(&new_crtc_state
->base
))
5495 * Workaround : Do not read or write the pipe palette/gamma data while
5496 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
5498 * Re-enable IPS after the LUT has been programmed.
5500 if (IS_HASWELL(dev_priv
) &&
5501 (new_crtc_state
->base
.color_mgmt_changed
||
5502 new_crtc_state
->update_pipe
) &&
5503 new_crtc_state
->gamma_mode
== GAMMA_MODE_MODE_SPLIT
)
5507 * We can't read out IPS on broadwell, assume the worst and
5508 * forcibly enable IPS on the first fastset.
5510 if (new_crtc_state
->update_pipe
&&
5511 old_crtc_state
->base
.adjusted_mode
.private_flags
& I915_MODE_FLAG_INHERITED
)
5514 return !old_crtc_state
->ips_enabled
;
5517 static bool needs_nv12_wa(struct drm_i915_private
*dev_priv
,
5518 const struct intel_crtc_state
*crtc_state
)
5520 if (!crtc_state
->nv12_planes
)
5523 /* WA Display #0827: Gen9:all */
5524 if (IS_GEN(dev_priv
, 9) && !IS_GEMINILAKE(dev_priv
))
5530 static void intel_post_plane_update(struct intel_crtc_state
*old_crtc_state
)
5532 struct intel_crtc
*crtc
= to_intel_crtc(old_crtc_state
->base
.crtc
);
5533 struct drm_device
*dev
= crtc
->base
.dev
;
5534 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5535 struct drm_atomic_state
*old_state
= old_crtc_state
->base
.state
;
5536 struct intel_crtc_state
*pipe_config
=
5537 intel_atomic_get_new_crtc_state(to_intel_atomic_state(old_state
),
5539 struct drm_plane
*primary
= crtc
->base
.primary
;
5540 struct drm_plane_state
*old_primary_state
=
5541 drm_atomic_get_old_plane_state(old_state
, primary
);
5543 intel_frontbuffer_flip(to_i915(crtc
->base
.dev
), pipe_config
->fb_bits
);
5545 if (pipe_config
->update_wm_post
&& pipe_config
->base
.active
)
5546 intel_update_watermarks(crtc
);
5548 if (hsw_post_update_enable_ips(old_crtc_state
, pipe_config
))
5549 hsw_enable_ips(pipe_config
);
5551 if (old_primary_state
) {
5552 struct drm_plane_state
*new_primary_state
=
5553 drm_atomic_get_new_plane_state(old_state
, primary
);
5555 intel_fbc_post_update(crtc
);
5557 if (new_primary_state
->visible
&&
5558 (needs_modeset(&pipe_config
->base
) ||
5559 !old_primary_state
->visible
))
5560 intel_post_enable_primary(&crtc
->base
, pipe_config
);
5563 /* Display WA 827 */
5564 if (needs_nv12_wa(dev_priv
, old_crtc_state
) &&
5565 !needs_nv12_wa(dev_priv
, pipe_config
)) {
5566 skl_wa_827(dev_priv
, crtc
->pipe
, false);
5570 static void intel_pre_plane_update(struct intel_crtc_state
*old_crtc_state
,
5571 struct intel_crtc_state
*pipe_config
)
5573 struct intel_crtc
*crtc
= to_intel_crtc(old_crtc_state
->base
.crtc
);
5574 struct drm_device
*dev
= crtc
->base
.dev
;
5575 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5576 struct drm_atomic_state
*old_state
= old_crtc_state
->base
.state
;
5577 struct drm_plane
*primary
= crtc
->base
.primary
;
5578 struct drm_plane_state
*old_primary_state
=
5579 drm_atomic_get_old_plane_state(old_state
, primary
);
5580 bool modeset
= needs_modeset(&pipe_config
->base
);
5581 struct intel_atomic_state
*old_intel_state
=
5582 to_intel_atomic_state(old_state
);
5584 if (hsw_pre_update_disable_ips(old_crtc_state
, pipe_config
))
5585 hsw_disable_ips(old_crtc_state
);
5587 if (old_primary_state
) {
5588 struct intel_plane_state
*new_primary_state
=
5589 intel_atomic_get_new_plane_state(old_intel_state
,
5590 to_intel_plane(primary
));
5592 intel_fbc_pre_update(crtc
, pipe_config
, new_primary_state
);
5594 * Gen2 reports pipe underruns whenever all planes are disabled.
5595 * So disable underrun reporting before all the planes get disabled.
5597 if (IS_GEN(dev_priv
, 2) && old_primary_state
->visible
&&
5598 (modeset
|| !new_primary_state
->base
.visible
))
5599 intel_set_cpu_fifo_underrun_reporting(dev_priv
, crtc
->pipe
, false);
5602 /* Display WA 827 */
5603 if (!needs_nv12_wa(dev_priv
, old_crtc_state
) &&
5604 needs_nv12_wa(dev_priv
, pipe_config
)) {
5605 skl_wa_827(dev_priv
, crtc
->pipe
, true);
5609 * Vblank time updates from the shadow to live plane control register
5610 * are blocked if the memory self-refresh mode is active at that
5611 * moment. So to make sure the plane gets truly disabled, disable
5612 * first the self-refresh mode. The self-refresh enable bit in turn
5613 * will be checked/applied by the HW only at the next frame start
5614 * event which is after the vblank start event, so we need to have a
5615 * wait-for-vblank between disabling the plane and the pipe.
5617 if (HAS_GMCH(dev_priv
) && old_crtc_state
->base
.active
&&
5618 pipe_config
->disable_cxsr
&& intel_set_memory_cxsr(dev_priv
, false))
5619 intel_wait_for_vblank(dev_priv
, crtc
->pipe
);
5622 * IVB workaround: must disable low power watermarks for at least
5623 * one frame before enabling scaling. LP watermarks can be re-enabled
5624 * when scaling is disabled.
5626 * WaCxSRDisabledForSpriteScaling:ivb
5628 if (pipe_config
->disable_lp_wm
&& ilk_disable_lp_wm(dev
) &&
5629 old_crtc_state
->base
.active
)
5630 intel_wait_for_vblank(dev_priv
, crtc
->pipe
);
5633 * If we're doing a modeset, we're done. No need to do any pre-vblank
5634 * watermark programming here.
5636 if (needs_modeset(&pipe_config
->base
))
5640 * For platforms that support atomic watermarks, program the
5641 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
5642 * will be the intermediate values that are safe for both pre- and
5643 * post- vblank; when vblank happens, the 'active' values will be set
5644 * to the final 'target' values and we'll do this again to get the
5645 * optimal watermarks. For gen9+ platforms, the values we program here
5646 * will be the final target values which will get automatically latched
5647 * at vblank time; no further programming will be necessary.
5649 * If a platform hasn't been transitioned to atomic watermarks yet,
5650 * we'll continue to update watermarks the old way, if flags tell
5653 if (dev_priv
->display
.initial_watermarks
!= NULL
)
5654 dev_priv
->display
.initial_watermarks(old_intel_state
,
5656 else if (pipe_config
->update_wm_pre
)
5657 intel_update_watermarks(crtc
);
5660 static void intel_crtc_disable_planes(struct intel_atomic_state
*state
,
5661 struct intel_crtc
*crtc
)
5663 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
5664 const struct intel_crtc_state
*new_crtc_state
=
5665 intel_atomic_get_new_crtc_state(state
, crtc
);
5666 unsigned int update_mask
= new_crtc_state
->update_planes
;
5667 const struct intel_plane_state
*old_plane_state
;
5668 struct intel_plane
*plane
;
5669 unsigned fb_bits
= 0;
5672 intel_crtc_dpms_overlay_disable(crtc
);
5674 for_each_old_intel_plane_in_state(state
, plane
, old_plane_state
, i
) {
5675 if (crtc
->pipe
!= plane
->pipe
||
5676 !(update_mask
& BIT(plane
->id
)))
5679 intel_disable_plane(plane
, new_crtc_state
);
5681 if (old_plane_state
->base
.visible
)
5682 fb_bits
|= plane
->frontbuffer_bit
;
5685 intel_frontbuffer_flip(dev_priv
, fb_bits
);
5688 static void intel_encoders_pre_pll_enable(struct drm_crtc
*crtc
,
5689 struct intel_crtc_state
*crtc_state
,
5690 struct drm_atomic_state
*old_state
)
5692 struct drm_connector_state
*conn_state
;
5693 struct drm_connector
*conn
;
5696 for_each_new_connector_in_state(old_state
, conn
, conn_state
, i
) {
5697 struct intel_encoder
*encoder
=
5698 to_intel_encoder(conn_state
->best_encoder
);
5700 if (conn_state
->crtc
!= crtc
)
5703 if (encoder
->pre_pll_enable
)
5704 encoder
->pre_pll_enable(encoder
, crtc_state
, conn_state
);
5708 static void intel_encoders_pre_enable(struct drm_crtc
*crtc
,
5709 struct intel_crtc_state
*crtc_state
,
5710 struct drm_atomic_state
*old_state
)
5712 struct drm_connector_state
*conn_state
;
5713 struct drm_connector
*conn
;
5716 for_each_new_connector_in_state(old_state
, conn
, conn_state
, i
) {
5717 struct intel_encoder
*encoder
=
5718 to_intel_encoder(conn_state
->best_encoder
);
5720 if (conn_state
->crtc
!= crtc
)
5723 if (encoder
->pre_enable
)
5724 encoder
->pre_enable(encoder
, crtc_state
, conn_state
);
5728 static void intel_encoders_enable(struct drm_crtc
*crtc
,
5729 struct intel_crtc_state
*crtc_state
,
5730 struct drm_atomic_state
*old_state
)
5732 struct drm_connector_state
*conn_state
;
5733 struct drm_connector
*conn
;
5736 for_each_new_connector_in_state(old_state
, conn
, conn_state
, i
) {
5737 struct intel_encoder
*encoder
=
5738 to_intel_encoder(conn_state
->best_encoder
);
5740 if (conn_state
->crtc
!= crtc
)
5743 if (encoder
->enable
)
5744 encoder
->enable(encoder
, crtc_state
, conn_state
);
5745 intel_opregion_notify_encoder(encoder
, true);
5749 static void intel_encoders_disable(struct drm_crtc
*crtc
,
5750 struct intel_crtc_state
*old_crtc_state
,
5751 struct drm_atomic_state
*old_state
)
5753 struct drm_connector_state
*old_conn_state
;
5754 struct drm_connector
*conn
;
5757 for_each_old_connector_in_state(old_state
, conn
, old_conn_state
, i
) {
5758 struct intel_encoder
*encoder
=
5759 to_intel_encoder(old_conn_state
->best_encoder
);
5761 if (old_conn_state
->crtc
!= crtc
)
5764 intel_opregion_notify_encoder(encoder
, false);
5765 if (encoder
->disable
)
5766 encoder
->disable(encoder
, old_crtc_state
, old_conn_state
);
5770 static void intel_encoders_post_disable(struct drm_crtc
*crtc
,
5771 struct intel_crtc_state
*old_crtc_state
,
5772 struct drm_atomic_state
*old_state
)
5774 struct drm_connector_state
*old_conn_state
;
5775 struct drm_connector
*conn
;
5778 for_each_old_connector_in_state(old_state
, conn
, old_conn_state
, i
) {
5779 struct intel_encoder
*encoder
=
5780 to_intel_encoder(old_conn_state
->best_encoder
);
5782 if (old_conn_state
->crtc
!= crtc
)
5785 if (encoder
->post_disable
)
5786 encoder
->post_disable(encoder
, old_crtc_state
, old_conn_state
);
5790 static void intel_encoders_post_pll_disable(struct drm_crtc
*crtc
,
5791 struct intel_crtc_state
*old_crtc_state
,
5792 struct drm_atomic_state
*old_state
)
5794 struct drm_connector_state
*old_conn_state
;
5795 struct drm_connector
*conn
;
5798 for_each_old_connector_in_state(old_state
, conn
, old_conn_state
, i
) {
5799 struct intel_encoder
*encoder
=
5800 to_intel_encoder(old_conn_state
->best_encoder
);
5802 if (old_conn_state
->crtc
!= crtc
)
5805 if (encoder
->post_pll_disable
)
5806 encoder
->post_pll_disable(encoder
, old_crtc_state
, old_conn_state
);
5810 static void intel_encoders_update_pipe(struct drm_crtc
*crtc
,
5811 struct intel_crtc_state
*crtc_state
,
5812 struct drm_atomic_state
*old_state
)
5814 struct drm_connector_state
*conn_state
;
5815 struct drm_connector
*conn
;
5818 for_each_new_connector_in_state(old_state
, conn
, conn_state
, i
) {
5819 struct intel_encoder
*encoder
=
5820 to_intel_encoder(conn_state
->best_encoder
);
5822 if (conn_state
->crtc
!= crtc
)
5825 if (encoder
->update_pipe
)
5826 encoder
->update_pipe(encoder
, crtc_state
, conn_state
);
5830 static void intel_disable_primary_plane(const struct intel_crtc_state
*crtc_state
)
5832 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
5833 struct intel_plane
*plane
= to_intel_plane(crtc
->base
.primary
);
5835 plane
->disable_plane(plane
, crtc_state
);
5838 static void ironlake_crtc_enable(struct intel_crtc_state
*pipe_config
,
5839 struct drm_atomic_state
*old_state
)
5841 struct drm_crtc
*crtc
= pipe_config
->base
.crtc
;
5842 struct drm_device
*dev
= crtc
->dev
;
5843 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5844 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5845 int pipe
= intel_crtc
->pipe
;
5846 struct intel_atomic_state
*old_intel_state
=
5847 to_intel_atomic_state(old_state
);
5849 if (WARN_ON(intel_crtc
->active
))
5853 * Sometimes spurious CPU pipe underruns happen during FDI
5854 * training, at least with VGA+HDMI cloning. Suppress them.
5856 * On ILK we get an occasional spurious CPU pipe underruns
5857 * between eDP port A enable and vdd enable. Also PCH port
5858 * enable seems to result in the occasional CPU pipe underrun.
5860 * Spurious PCH underruns also occur during PCH enabling.
5862 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
5863 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, false);
5865 if (pipe_config
->has_pch_encoder
)
5866 intel_prepare_shared_dpll(pipe_config
);
5868 if (intel_crtc_has_dp_encoder(pipe_config
))
5869 intel_dp_set_m_n(pipe_config
, M1_N1
);
5871 intel_set_pipe_timings(pipe_config
);
5872 intel_set_pipe_src_size(pipe_config
);
5874 if (pipe_config
->has_pch_encoder
) {
5875 intel_cpu_transcoder_set_m_n(pipe_config
,
5876 &pipe_config
->fdi_m_n
, NULL
);
5879 ironlake_set_pipeconf(pipe_config
);
5881 intel_crtc
->active
= true;
5883 intel_encoders_pre_enable(crtc
, pipe_config
, old_state
);
5885 if (pipe_config
->has_pch_encoder
) {
5886 /* Note: FDI PLL enabling _must_ be done before we enable the
5887 * cpu pipes, hence this is separate from all the other fdi/pch
5889 ironlake_fdi_pll_enable(pipe_config
);
5891 assert_fdi_tx_disabled(dev_priv
, pipe
);
5892 assert_fdi_rx_disabled(dev_priv
, pipe
);
5895 ironlake_pfit_enable(pipe_config
);
5898 * On ILK+ LUT must be loaded before the pipe is running but with
5901 intel_color_load_luts(pipe_config
);
5902 intel_color_commit(pipe_config
);
5903 /* update DSPCNTR to configure gamma for pipe bottom color */
5904 intel_disable_primary_plane(pipe_config
);
5906 if (dev_priv
->display
.initial_watermarks
!= NULL
)
5907 dev_priv
->display
.initial_watermarks(old_intel_state
, pipe_config
);
5908 intel_enable_pipe(pipe_config
);
5910 if (pipe_config
->has_pch_encoder
)
5911 ironlake_pch_enable(old_intel_state
, pipe_config
);
5913 assert_vblank_disabled(crtc
);
5914 intel_crtc_vblank_on(pipe_config
);
5916 intel_encoders_enable(crtc
, pipe_config
, old_state
);
5918 if (HAS_PCH_CPT(dev_priv
))
5919 cpt_verify_modeset(dev
, intel_crtc
->pipe
);
5922 * Must wait for vblank to avoid spurious PCH FIFO underruns.
5923 * And a second vblank wait is needed at least on ILK with
5924 * some interlaced HDMI modes. Let's do the double wait always
5925 * in case there are more corner cases we don't know about.
5927 if (pipe_config
->has_pch_encoder
) {
5928 intel_wait_for_vblank(dev_priv
, pipe
);
5929 intel_wait_for_vblank(dev_priv
, pipe
);
5931 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
5932 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, true);
5935 /* IPS only exists on ULT machines and is tied to pipe A. */
5936 static bool hsw_crtc_supports_ips(struct intel_crtc
*crtc
)
5938 return HAS_IPS(to_i915(crtc
->base
.dev
)) && crtc
->pipe
== PIPE_A
;
5941 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private
*dev_priv
,
5942 enum pipe pipe
, bool apply
)
5944 u32 val
= I915_READ(CLKGATE_DIS_PSL(pipe
));
5945 u32 mask
= DPF_GATING_DIS
| DPF_RAM_GATING_DIS
| DPFR_GATING_DIS
;
5952 I915_WRITE(CLKGATE_DIS_PSL(pipe
), val
);
5955 static void icl_pipe_mbus_enable(struct intel_crtc
*crtc
)
5957 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
5958 enum pipe pipe
= crtc
->pipe
;
5961 val
= MBUS_DBOX_A_CREDIT(2);
5962 val
|= MBUS_DBOX_BW_CREDIT(1);
5963 val
|= MBUS_DBOX_B_CREDIT(8);
5965 I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe
), val
);
5968 static void haswell_crtc_enable(struct intel_crtc_state
*pipe_config
,
5969 struct drm_atomic_state
*old_state
)
5971 struct drm_crtc
*crtc
= pipe_config
->base
.crtc
;
5972 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
5973 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5974 int pipe
= intel_crtc
->pipe
, hsw_workaround_pipe
;
5975 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
5976 struct intel_atomic_state
*old_intel_state
=
5977 to_intel_atomic_state(old_state
);
5978 bool psl_clkgate_wa
;
5980 if (WARN_ON(intel_crtc
->active
))
5983 intel_encoders_pre_pll_enable(crtc
, pipe_config
, old_state
);
5985 if (pipe_config
->shared_dpll
)
5986 intel_enable_shared_dpll(pipe_config
);
5988 intel_encoders_pre_enable(crtc
, pipe_config
, old_state
);
5990 if (intel_crtc_has_dp_encoder(pipe_config
))
5991 intel_dp_set_m_n(pipe_config
, M1_N1
);
5993 if (!transcoder_is_dsi(cpu_transcoder
))
5994 intel_set_pipe_timings(pipe_config
);
5996 intel_set_pipe_src_size(pipe_config
);
5998 if (cpu_transcoder
!= TRANSCODER_EDP
&&
5999 !transcoder_is_dsi(cpu_transcoder
)) {
6000 I915_WRITE(PIPE_MULT(cpu_transcoder
),
6001 pipe_config
->pixel_multiplier
- 1);
6004 if (pipe_config
->has_pch_encoder
) {
6005 intel_cpu_transcoder_set_m_n(pipe_config
,
6006 &pipe_config
->fdi_m_n
, NULL
);
6009 if (!transcoder_is_dsi(cpu_transcoder
))
6010 haswell_set_pipeconf(pipe_config
);
6012 haswell_set_pipemisc(pipe_config
);
6014 intel_crtc
->active
= true;
6016 /* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
6017 psl_clkgate_wa
= (IS_GEMINILAKE(dev_priv
) || IS_CANNONLAKE(dev_priv
)) &&
6018 pipe_config
->pch_pfit
.enabled
;
6020 glk_pipe_scaler_clock_gating_wa(dev_priv
, pipe
, true);
6022 if (INTEL_GEN(dev_priv
) >= 9)
6023 skylake_pfit_enable(pipe_config
);
6025 ironlake_pfit_enable(pipe_config
);
6028 * On ILK+ LUT must be loaded before the pipe is running but with
6031 intel_color_load_luts(pipe_config
);
6032 intel_color_commit(pipe_config
);
6033 /* update DSPCNTR to configure gamma/csc for pipe bottom color */
6034 if (INTEL_GEN(dev_priv
) < 9)
6035 intel_disable_primary_plane(pipe_config
);
6037 if (INTEL_GEN(dev_priv
) >= 11)
6038 icl_set_pipe_chicken(intel_crtc
);
6040 intel_ddi_set_pipe_settings(pipe_config
);
6041 if (!transcoder_is_dsi(cpu_transcoder
))
6042 intel_ddi_enable_transcoder_func(pipe_config
);
6044 if (dev_priv
->display
.initial_watermarks
!= NULL
)
6045 dev_priv
->display
.initial_watermarks(old_intel_state
, pipe_config
);
6047 if (INTEL_GEN(dev_priv
) >= 11)
6048 icl_pipe_mbus_enable(intel_crtc
);
6050 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
6051 if (!transcoder_is_dsi(cpu_transcoder
))
6052 intel_enable_pipe(pipe_config
);
6054 if (pipe_config
->has_pch_encoder
)
6055 lpt_pch_enable(old_intel_state
, pipe_config
);
6057 if (intel_crtc_has_type(pipe_config
, INTEL_OUTPUT_DP_MST
))
6058 intel_ddi_set_vc_payload_alloc(pipe_config
, true);
6060 assert_vblank_disabled(crtc
);
6061 intel_crtc_vblank_on(pipe_config
);
6063 intel_encoders_enable(crtc
, pipe_config
, old_state
);
6065 if (psl_clkgate_wa
) {
6066 intel_wait_for_vblank(dev_priv
, pipe
);
6067 glk_pipe_scaler_clock_gating_wa(dev_priv
, pipe
, false);
6070 /* If we change the relative order between pipe/planes enabling, we need
6071 * to change the workaround. */
6072 hsw_workaround_pipe
= pipe_config
->hsw_workaround_pipe
;
6073 if (IS_HASWELL(dev_priv
) && hsw_workaround_pipe
!= INVALID_PIPE
) {
6074 intel_wait_for_vblank(dev_priv
, hsw_workaround_pipe
);
6075 intel_wait_for_vblank(dev_priv
, hsw_workaround_pipe
);
6079 static void ironlake_pfit_disable(const struct intel_crtc_state
*old_crtc_state
)
6081 struct intel_crtc
*crtc
= to_intel_crtc(old_crtc_state
->base
.crtc
);
6082 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
6083 enum pipe pipe
= crtc
->pipe
;
6085 /* To avoid upsetting the power well on haswell only disable the pfit if
6086 * it's in use. The hw state code will make sure we get this right. */
6087 if (old_crtc_state
->pch_pfit
.enabled
) {
6088 I915_WRITE(PF_CTL(pipe
), 0);
6089 I915_WRITE(PF_WIN_POS(pipe
), 0);
6090 I915_WRITE(PF_WIN_SZ(pipe
), 0);
6094 static void ironlake_crtc_disable(struct intel_crtc_state
*old_crtc_state
,
6095 struct drm_atomic_state
*old_state
)
6097 struct drm_crtc
*crtc
= old_crtc_state
->base
.crtc
;
6098 struct drm_device
*dev
= crtc
->dev
;
6099 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6100 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6101 int pipe
= intel_crtc
->pipe
;
6104 * Sometimes spurious CPU pipe underruns happen when the
6105 * pipe is already disabled, but FDI RX/TX is still enabled.
6106 * Happens at least with VGA+HDMI cloning. Suppress them.
6108 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
6109 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, false);
6111 intel_encoders_disable(crtc
, old_crtc_state
, old_state
);
6113 drm_crtc_vblank_off(crtc
);
6114 assert_vblank_disabled(crtc
);
6116 intel_disable_pipe(old_crtc_state
);
6118 ironlake_pfit_disable(old_crtc_state
);
6120 if (old_crtc_state
->has_pch_encoder
)
6121 ironlake_fdi_disable(crtc
);
6123 intel_encoders_post_disable(crtc
, old_crtc_state
, old_state
);
6125 if (old_crtc_state
->has_pch_encoder
) {
6126 ironlake_disable_pch_transcoder(dev_priv
, pipe
);
6128 if (HAS_PCH_CPT(dev_priv
)) {
6132 /* disable TRANS_DP_CTL */
6133 reg
= TRANS_DP_CTL(pipe
);
6134 temp
= I915_READ(reg
);
6135 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
|
6136 TRANS_DP_PORT_SEL_MASK
);
6137 temp
|= TRANS_DP_PORT_SEL_NONE
;
6138 I915_WRITE(reg
, temp
);
6140 /* disable DPLL_SEL */
6141 temp
= I915_READ(PCH_DPLL_SEL
);
6142 temp
&= ~(TRANS_DPLL_ENABLE(pipe
) | TRANS_DPLLB_SEL(pipe
));
6143 I915_WRITE(PCH_DPLL_SEL
, temp
);
6146 ironlake_fdi_pll_disable(intel_crtc
);
6149 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
6150 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, true);
6153 static void haswell_crtc_disable(struct intel_crtc_state
*old_crtc_state
,
6154 struct drm_atomic_state
*old_state
)
6156 struct drm_crtc
*crtc
= old_crtc_state
->base
.crtc
;
6157 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
6158 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6159 enum transcoder cpu_transcoder
= old_crtc_state
->cpu_transcoder
;
6161 intel_encoders_disable(crtc
, old_crtc_state
, old_state
);
6163 drm_crtc_vblank_off(crtc
);
6164 assert_vblank_disabled(crtc
);
6166 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
6167 if (!transcoder_is_dsi(cpu_transcoder
))
6168 intel_disable_pipe(old_crtc_state
);
6170 if (intel_crtc_has_type(old_crtc_state
, INTEL_OUTPUT_DP_MST
))
6171 intel_ddi_set_vc_payload_alloc(old_crtc_state
, false);
6173 if (!transcoder_is_dsi(cpu_transcoder
))
6174 intel_ddi_disable_transcoder_func(old_crtc_state
);
6176 intel_dsc_disable(old_crtc_state
);
6178 if (INTEL_GEN(dev_priv
) >= 9)
6179 skylake_scaler_disable(intel_crtc
);
6181 ironlake_pfit_disable(old_crtc_state
);
6183 intel_encoders_post_disable(crtc
, old_crtc_state
, old_state
);
6185 intel_encoders_post_pll_disable(crtc
, old_crtc_state
, old_state
);
6188 static void i9xx_pfit_enable(const struct intel_crtc_state
*crtc_state
)
6190 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
6191 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
6193 if (!crtc_state
->gmch_pfit
.control
)
6197 * The panel fitter should only be adjusted whilst the pipe is disabled,
6198 * according to register description and PRM.
6200 WARN_ON(I915_READ(PFIT_CONTROL
) & PFIT_ENABLE
);
6201 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
6203 I915_WRITE(PFIT_PGM_RATIOS
, crtc_state
->gmch_pfit
.pgm_ratios
);
6204 I915_WRITE(PFIT_CONTROL
, crtc_state
->gmch_pfit
.control
);
6206 /* Border color in case we don't scale up to the full screen. Black by
6207 * default, change to something else for debugging. */
6208 I915_WRITE(BCLRPAT(crtc
->pipe
), 0);
6211 bool intel_port_is_combophy(struct drm_i915_private
*dev_priv
, enum port port
)
6213 if (port
== PORT_NONE
)
6216 if (IS_ELKHARTLAKE(dev_priv
))
6217 return port
<= PORT_C
;
6219 if (INTEL_GEN(dev_priv
) >= 11)
6220 return port
<= PORT_B
;
6225 bool intel_port_is_tc(struct drm_i915_private
*dev_priv
, enum port port
)
6227 if (INTEL_GEN(dev_priv
) >= 11 && !IS_ELKHARTLAKE(dev_priv
))
6228 return port
>= PORT_C
&& port
<= PORT_F
;
6233 enum tc_port
intel_port_to_tc(struct drm_i915_private
*dev_priv
, enum port port
)
6235 if (!intel_port_is_tc(dev_priv
, port
))
6236 return PORT_TC_NONE
;
6238 return port
- PORT_C
;
6241 enum intel_display_power_domain
intel_port_to_power_domain(enum port port
)
6245 return POWER_DOMAIN_PORT_DDI_A_LANES
;
6247 return POWER_DOMAIN_PORT_DDI_B_LANES
;
6249 return POWER_DOMAIN_PORT_DDI_C_LANES
;
6251 return POWER_DOMAIN_PORT_DDI_D_LANES
;
6253 return POWER_DOMAIN_PORT_DDI_E_LANES
;
6255 return POWER_DOMAIN_PORT_DDI_F_LANES
;
6258 return POWER_DOMAIN_PORT_OTHER
;
6262 enum intel_display_power_domain
6263 intel_aux_power_domain(struct intel_digital_port
*dig_port
)
6265 switch (dig_port
->aux_ch
) {
6267 return POWER_DOMAIN_AUX_A
;
6269 return POWER_DOMAIN_AUX_B
;
6271 return POWER_DOMAIN_AUX_C
;
6273 return POWER_DOMAIN_AUX_D
;
6275 return POWER_DOMAIN_AUX_E
;
6277 return POWER_DOMAIN_AUX_F
;
6279 MISSING_CASE(dig_port
->aux_ch
);
6280 return POWER_DOMAIN_AUX_A
;
6284 static u64
get_crtc_power_domains(struct drm_crtc
*crtc
,
6285 struct intel_crtc_state
*crtc_state
)
6287 struct drm_device
*dev
= crtc
->dev
;
6288 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6289 struct drm_encoder
*encoder
;
6290 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6291 enum pipe pipe
= intel_crtc
->pipe
;
6293 enum transcoder transcoder
= crtc_state
->cpu_transcoder
;
6295 if (!crtc_state
->base
.active
)
6298 mask
= BIT_ULL(POWER_DOMAIN_PIPE(pipe
));
6299 mask
|= BIT_ULL(POWER_DOMAIN_TRANSCODER(transcoder
));
6300 if (crtc_state
->pch_pfit
.enabled
||
6301 crtc_state
->pch_pfit
.force_thru
)
6302 mask
|= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe
));
6304 drm_for_each_encoder_mask(encoder
, dev
, crtc_state
->base
.encoder_mask
) {
6305 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
6307 mask
|= BIT_ULL(intel_encoder
->power_domain
);
6310 if (HAS_DDI(dev_priv
) && crtc_state
->has_audio
)
6311 mask
|= BIT_ULL(POWER_DOMAIN_AUDIO
);
6313 if (crtc_state
->shared_dpll
)
6314 mask
|= BIT_ULL(POWER_DOMAIN_PLLS
);
6320 modeset_get_crtc_power_domains(struct drm_crtc
*crtc
,
6321 struct intel_crtc_state
*crtc_state
)
6323 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
6324 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6325 enum intel_display_power_domain domain
;
6326 u64 domains
, new_domains
, old_domains
;
6328 old_domains
= intel_crtc
->enabled_power_domains
;
6329 intel_crtc
->enabled_power_domains
= new_domains
=
6330 get_crtc_power_domains(crtc
, crtc_state
);
6332 domains
= new_domains
& ~old_domains
;
6334 for_each_power_domain(domain
, domains
)
6335 intel_display_power_get(dev_priv
, domain
);
6337 return old_domains
& ~new_domains
;
6340 static void modeset_put_power_domains(struct drm_i915_private
*dev_priv
,
6343 enum intel_display_power_domain domain
;
6345 for_each_power_domain(domain
, domains
)
6346 intel_display_power_put_unchecked(dev_priv
, domain
);
6349 static void valleyview_crtc_enable(struct intel_crtc_state
*pipe_config
,
6350 struct drm_atomic_state
*old_state
)
6352 struct intel_atomic_state
*old_intel_state
=
6353 to_intel_atomic_state(old_state
);
6354 struct drm_crtc
*crtc
= pipe_config
->base
.crtc
;
6355 struct drm_device
*dev
= crtc
->dev
;
6356 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6357 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6358 int pipe
= intel_crtc
->pipe
;
6360 if (WARN_ON(intel_crtc
->active
))
6363 if (intel_crtc_has_dp_encoder(pipe_config
))
6364 intel_dp_set_m_n(pipe_config
, M1_N1
);
6366 intel_set_pipe_timings(pipe_config
);
6367 intel_set_pipe_src_size(pipe_config
);
6369 if (IS_CHERRYVIEW(dev_priv
) && pipe
== PIPE_B
) {
6370 I915_WRITE(CHV_BLEND(pipe
), CHV_BLEND_LEGACY
);
6371 I915_WRITE(CHV_CANVAS(pipe
), 0);
6374 i9xx_set_pipeconf(pipe_config
);
6376 intel_crtc
->active
= true;
6378 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
6380 intel_encoders_pre_pll_enable(crtc
, pipe_config
, old_state
);
6382 if (IS_CHERRYVIEW(dev_priv
)) {
6383 chv_prepare_pll(intel_crtc
, pipe_config
);
6384 chv_enable_pll(intel_crtc
, pipe_config
);
6386 vlv_prepare_pll(intel_crtc
, pipe_config
);
6387 vlv_enable_pll(intel_crtc
, pipe_config
);
6390 intel_encoders_pre_enable(crtc
, pipe_config
, old_state
);
6392 i9xx_pfit_enable(pipe_config
);
6394 intel_color_load_luts(pipe_config
);
6395 intel_color_commit(pipe_config
);
6396 /* update DSPCNTR to configure gamma for pipe bottom color */
6397 intel_disable_primary_plane(pipe_config
);
6399 dev_priv
->display
.initial_watermarks(old_intel_state
,
6401 intel_enable_pipe(pipe_config
);
6403 assert_vblank_disabled(crtc
);
6404 intel_crtc_vblank_on(pipe_config
);
6406 intel_encoders_enable(crtc
, pipe_config
, old_state
);
6409 static void i9xx_set_pll_dividers(const struct intel_crtc_state
*crtc_state
)
6411 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
6412 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
6414 I915_WRITE(FP0(crtc
->pipe
), crtc_state
->dpll_hw_state
.fp0
);
6415 I915_WRITE(FP1(crtc
->pipe
), crtc_state
->dpll_hw_state
.fp1
);
6418 static void i9xx_crtc_enable(struct intel_crtc_state
*pipe_config
,
6419 struct drm_atomic_state
*old_state
)
6421 struct intel_atomic_state
*old_intel_state
=
6422 to_intel_atomic_state(old_state
);
6423 struct drm_crtc
*crtc
= pipe_config
->base
.crtc
;
6424 struct drm_device
*dev
= crtc
->dev
;
6425 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6426 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6427 enum pipe pipe
= intel_crtc
->pipe
;
6429 if (WARN_ON(intel_crtc
->active
))
6432 i9xx_set_pll_dividers(pipe_config
);
6434 if (intel_crtc_has_dp_encoder(pipe_config
))
6435 intel_dp_set_m_n(pipe_config
, M1_N1
);
6437 intel_set_pipe_timings(pipe_config
);
6438 intel_set_pipe_src_size(pipe_config
);
6440 i9xx_set_pipeconf(pipe_config
);
6442 intel_crtc
->active
= true;
6444 if (!IS_GEN(dev_priv
, 2))
6445 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
6447 intel_encoders_pre_enable(crtc
, pipe_config
, old_state
);
6449 i9xx_enable_pll(intel_crtc
, pipe_config
);
6451 i9xx_pfit_enable(pipe_config
);
6453 intel_color_load_luts(pipe_config
);
6454 intel_color_commit(pipe_config
);
6455 /* update DSPCNTR to configure gamma for pipe bottom color */
6456 intel_disable_primary_plane(pipe_config
);
6458 if (dev_priv
->display
.initial_watermarks
!= NULL
)
6459 dev_priv
->display
.initial_watermarks(old_intel_state
,
6462 intel_update_watermarks(intel_crtc
);
6463 intel_enable_pipe(pipe_config
);
6465 assert_vblank_disabled(crtc
);
6466 intel_crtc_vblank_on(pipe_config
);
6468 intel_encoders_enable(crtc
, pipe_config
, old_state
);
6471 static void i9xx_pfit_disable(const struct intel_crtc_state
*old_crtc_state
)
6473 struct intel_crtc
*crtc
= to_intel_crtc(old_crtc_state
->base
.crtc
);
6474 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
6476 if (!old_crtc_state
->gmch_pfit
.control
)
6479 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
6481 DRM_DEBUG_KMS("disabling pfit, current: 0x%08x\n",
6482 I915_READ(PFIT_CONTROL
));
6483 I915_WRITE(PFIT_CONTROL
, 0);
6486 static void i9xx_crtc_disable(struct intel_crtc_state
*old_crtc_state
,
6487 struct drm_atomic_state
*old_state
)
6489 struct drm_crtc
*crtc
= old_crtc_state
->base
.crtc
;
6490 struct drm_device
*dev
= crtc
->dev
;
6491 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6492 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6493 int pipe
= intel_crtc
->pipe
;
6496 * On gen2 planes are double buffered but the pipe isn't, so we must
6497 * wait for planes to fully turn off before disabling the pipe.
6499 if (IS_GEN(dev_priv
, 2))
6500 intel_wait_for_vblank(dev_priv
, pipe
);
6502 intel_encoders_disable(crtc
, old_crtc_state
, old_state
);
6504 drm_crtc_vblank_off(crtc
);
6505 assert_vblank_disabled(crtc
);
6507 intel_disable_pipe(old_crtc_state
);
6509 i9xx_pfit_disable(old_crtc_state
);
6511 intel_encoders_post_disable(crtc
, old_crtc_state
, old_state
);
6513 if (!intel_crtc_has_type(old_crtc_state
, INTEL_OUTPUT_DSI
)) {
6514 if (IS_CHERRYVIEW(dev_priv
))
6515 chv_disable_pll(dev_priv
, pipe
);
6516 else if (IS_VALLEYVIEW(dev_priv
))
6517 vlv_disable_pll(dev_priv
, pipe
);
6519 i9xx_disable_pll(old_crtc_state
);
6522 intel_encoders_post_pll_disable(crtc
, old_crtc_state
, old_state
);
6524 if (!IS_GEN(dev_priv
, 2))
6525 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
6527 if (!dev_priv
->display
.initial_watermarks
)
6528 intel_update_watermarks(intel_crtc
);
6530 /* clock the pipe down to 640x480@60 to potentially save power */
6531 if (IS_I830(dev_priv
))
6532 i830_enable_pipe(dev_priv
, pipe
);
6535 static void intel_crtc_disable_noatomic(struct drm_crtc
*crtc
,
6536 struct drm_modeset_acquire_ctx
*ctx
)
6538 struct intel_encoder
*encoder
;
6539 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6540 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
6541 enum intel_display_power_domain domain
;
6542 struct intel_plane
*plane
;
6544 struct drm_atomic_state
*state
;
6545 struct intel_crtc_state
*crtc_state
;
6548 if (!intel_crtc
->active
)
6551 for_each_intel_plane_on_crtc(&dev_priv
->drm
, intel_crtc
, plane
) {
6552 const struct intel_plane_state
*plane_state
=
6553 to_intel_plane_state(plane
->base
.state
);
6555 if (plane_state
->base
.visible
)
6556 intel_plane_disable_noatomic(intel_crtc
, plane
);
6559 state
= drm_atomic_state_alloc(crtc
->dev
);
6561 DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory",
6562 crtc
->base
.id
, crtc
->name
);
6566 state
->acquire_ctx
= ctx
;
6568 /* Everything's already locked, -EDEADLK can't happen. */
6569 crtc_state
= intel_atomic_get_crtc_state(state
, intel_crtc
);
6570 ret
= drm_atomic_add_affected_connectors(state
, crtc
);
6572 WARN_ON(IS_ERR(crtc_state
) || ret
);
6574 dev_priv
->display
.crtc_disable(crtc_state
, state
);
6576 drm_atomic_state_put(state
);
6578 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
6579 crtc
->base
.id
, crtc
->name
);
6581 WARN_ON(drm_atomic_set_mode_for_crtc(crtc
->state
, NULL
) < 0);
6582 crtc
->state
->active
= false;
6583 intel_crtc
->active
= false;
6584 crtc
->enabled
= false;
6585 crtc
->state
->connector_mask
= 0;
6586 crtc
->state
->encoder_mask
= 0;
6588 for_each_encoder_on_crtc(crtc
->dev
, crtc
, encoder
)
6589 encoder
->base
.crtc
= NULL
;
6591 intel_fbc_disable(intel_crtc
);
6592 intel_update_watermarks(intel_crtc
);
6593 intel_disable_shared_dpll(to_intel_crtc_state(crtc
->state
));
6595 domains
= intel_crtc
->enabled_power_domains
;
6596 for_each_power_domain(domain
, domains
)
6597 intel_display_power_put_unchecked(dev_priv
, domain
);
6598 intel_crtc
->enabled_power_domains
= 0;
6600 dev_priv
->active_crtcs
&= ~(1 << intel_crtc
->pipe
);
6601 dev_priv
->min_cdclk
[intel_crtc
->pipe
] = 0;
6602 dev_priv
->min_voltage_level
[intel_crtc
->pipe
] = 0;
6606 * turn all crtc's off, but do not adjust state
6607 * This has to be paired with a call to intel_modeset_setup_hw_state.
6609 int intel_display_suspend(struct drm_device
*dev
)
6611 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6612 struct drm_atomic_state
*state
;
6615 state
= drm_atomic_helper_suspend(dev
);
6616 ret
= PTR_ERR_OR_ZERO(state
);
6618 DRM_ERROR("Suspending crtc's failed with %i\n", ret
);
6620 dev_priv
->modeset_restore_state
= state
;
6624 void intel_encoder_destroy(struct drm_encoder
*encoder
)
6626 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
6628 drm_encoder_cleanup(encoder
);
6629 kfree(intel_encoder
);
6632 /* Cross check the actual hw state with our own modeset state tracking (and it's
6633 * internal consistency). */
6634 static void intel_connector_verify_state(struct drm_crtc_state
*crtc_state
,
6635 struct drm_connector_state
*conn_state
)
6637 struct intel_connector
*connector
= to_intel_connector(conn_state
->connector
);
6639 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6640 connector
->base
.base
.id
,
6641 connector
->base
.name
);
6643 if (connector
->get_hw_state(connector
)) {
6644 struct intel_encoder
*encoder
= connector
->encoder
;
6646 I915_STATE_WARN(!crtc_state
,
6647 "connector enabled without attached crtc\n");
6652 I915_STATE_WARN(!crtc_state
->active
,
6653 "connector is active, but attached crtc isn't\n");
6655 if (!encoder
|| encoder
->type
== INTEL_OUTPUT_DP_MST
)
6658 I915_STATE_WARN(conn_state
->best_encoder
!= &encoder
->base
,
6659 "atomic encoder doesn't match attached encoder\n");
6661 I915_STATE_WARN(conn_state
->crtc
!= encoder
->base
.crtc
,
6662 "attached encoder crtc differs from connector crtc\n");
6664 I915_STATE_WARN(crtc_state
&& crtc_state
->active
,
6665 "attached crtc is active, but connector isn't\n");
6666 I915_STATE_WARN(!crtc_state
&& conn_state
->best_encoder
,
6667 "best encoder set without crtc!\n");
6671 static int pipe_required_fdi_lanes(struct intel_crtc_state
*crtc_state
)
6673 if (crtc_state
->base
.enable
&& crtc_state
->has_pch_encoder
)
6674 return crtc_state
->fdi_lanes
;
6679 static int ironlake_check_fdi_lanes(struct drm_device
*dev
, enum pipe pipe
,
6680 struct intel_crtc_state
*pipe_config
)
6682 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6683 struct drm_atomic_state
*state
= pipe_config
->base
.state
;
6684 struct intel_crtc
*other_crtc
;
6685 struct intel_crtc_state
*other_crtc_state
;
6687 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6688 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6689 if (pipe_config
->fdi_lanes
> 4) {
6690 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6691 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6695 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
6696 if (pipe_config
->fdi_lanes
> 2) {
6697 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6698 pipe_config
->fdi_lanes
);
6705 if (INTEL_INFO(dev_priv
)->num_pipes
== 2)
6708 /* Ivybridge 3 pipe is really complicated */
6713 if (pipe_config
->fdi_lanes
<= 2)
6716 other_crtc
= intel_get_crtc_for_pipe(dev_priv
, PIPE_C
);
6718 intel_atomic_get_crtc_state(state
, other_crtc
);
6719 if (IS_ERR(other_crtc_state
))
6720 return PTR_ERR(other_crtc_state
);
6722 if (pipe_required_fdi_lanes(other_crtc_state
) > 0) {
6723 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6724 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6729 if (pipe_config
->fdi_lanes
> 2) {
6730 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6731 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6735 other_crtc
= intel_get_crtc_for_pipe(dev_priv
, PIPE_B
);
6737 intel_atomic_get_crtc_state(state
, other_crtc
);
6738 if (IS_ERR(other_crtc_state
))
6739 return PTR_ERR(other_crtc_state
);
6741 if (pipe_required_fdi_lanes(other_crtc_state
) > 2) {
6742 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6752 static int ironlake_fdi_compute_config(struct intel_crtc
*intel_crtc
,
6753 struct intel_crtc_state
*pipe_config
)
6755 struct drm_device
*dev
= intel_crtc
->base
.dev
;
6756 const struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
6757 int lane
, link_bw
, fdi_dotclock
, ret
;
6758 bool needs_recompute
= false;
6761 /* FDI is a binary signal running at ~2.7GHz, encoding
6762 * each output octet as 10 bits. The actual frequency
6763 * is stored as a divider into a 100MHz clock, and the
6764 * mode pixel clock is stored in units of 1KHz.
6765 * Hence the bw of each lane in terms of the mode signal
6768 link_bw
= intel_fdi_link_freq(to_i915(dev
), pipe_config
);
6770 fdi_dotclock
= adjusted_mode
->crtc_clock
;
6772 lane
= ironlake_get_lanes_required(fdi_dotclock
, link_bw
,
6773 pipe_config
->pipe_bpp
);
6775 pipe_config
->fdi_lanes
= lane
;
6777 intel_link_compute_m_n(pipe_config
->pipe_bpp
, lane
, fdi_dotclock
,
6778 link_bw
, &pipe_config
->fdi_m_n
, false);
6780 ret
= ironlake_check_fdi_lanes(dev
, intel_crtc
->pipe
, pipe_config
);
6781 if (ret
== -EDEADLK
)
6784 if (ret
== -EINVAL
&& pipe_config
->pipe_bpp
> 6*3) {
6785 pipe_config
->pipe_bpp
-= 2*3;
6786 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6787 pipe_config
->pipe_bpp
);
6788 needs_recompute
= true;
6789 pipe_config
->bw_constrained
= true;
6794 if (needs_recompute
)
6800 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state
*crtc_state
)
6802 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
6803 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
6805 /* IPS only exists on ULT machines and is tied to pipe A. */
6806 if (!hsw_crtc_supports_ips(crtc
))
6809 if (!i915_modparams
.enable_ips
)
6812 if (crtc_state
->pipe_bpp
> 24)
6816 * We compare against max which means we must take
6817 * the increased cdclk requirement into account when
6818 * calculating the new cdclk.
6820 * Should measure whether using a lower cdclk w/o IPS
6822 if (IS_BROADWELL(dev_priv
) &&
6823 crtc_state
->pixel_rate
> dev_priv
->max_cdclk_freq
* 95 / 100)
6829 static bool hsw_compute_ips_config(struct intel_crtc_state
*crtc_state
)
6831 struct drm_i915_private
*dev_priv
=
6832 to_i915(crtc_state
->base
.crtc
->dev
);
6833 struct intel_atomic_state
*intel_state
=
6834 to_intel_atomic_state(crtc_state
->base
.state
);
6836 if (!hsw_crtc_state_ips_capable(crtc_state
))
6840 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
6841 * enabled and disabled dynamically based on package C states,
6842 * user space can't make reliable use of the CRCs, so let's just
6843 * completely disable it.
6845 if (crtc_state
->crc_enabled
)
6848 /* IPS should be fine as long as at least one plane is enabled. */
6849 if (!(crtc_state
->active_planes
& ~BIT(PLANE_CURSOR
)))
6852 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
6853 if (IS_BROADWELL(dev_priv
) &&
6854 crtc_state
->pixel_rate
> intel_state
->cdclk
.logical
.cdclk
* 95 / 100)
6860 static bool intel_crtc_supports_double_wide(const struct intel_crtc
*crtc
)
6862 const struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
6864 /* GDG double wide on either pipe, otherwise pipe A only */
6865 return INTEL_GEN(dev_priv
) < 4 &&
6866 (crtc
->pipe
== PIPE_A
|| IS_I915G(dev_priv
));
6869 static u32
ilk_pipe_pixel_rate(const struct intel_crtc_state
*pipe_config
)
6873 pixel_rate
= pipe_config
->base
.adjusted_mode
.crtc_clock
;
6876 * We only use IF-ID interlacing. If we ever use
6877 * PF-ID we'll need to adjust the pixel_rate here.
6880 if (pipe_config
->pch_pfit
.enabled
) {
6881 u64 pipe_w
, pipe_h
, pfit_w
, pfit_h
;
6882 u32 pfit_size
= pipe_config
->pch_pfit
.size
;
6884 pipe_w
= pipe_config
->pipe_src_w
;
6885 pipe_h
= pipe_config
->pipe_src_h
;
6887 pfit_w
= (pfit_size
>> 16) & 0xFFFF;
6888 pfit_h
= pfit_size
& 0xFFFF;
6889 if (pipe_w
< pfit_w
)
6891 if (pipe_h
< pfit_h
)
6894 if (WARN_ON(!pfit_w
|| !pfit_h
))
6897 pixel_rate
= div_u64((u64
)pixel_rate
* pipe_w
* pipe_h
,
6904 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state
*crtc_state
)
6906 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->base
.crtc
->dev
);
6908 if (HAS_GMCH(dev_priv
))
6909 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
6910 crtc_state
->pixel_rate
=
6911 crtc_state
->base
.adjusted_mode
.crtc_clock
;
6913 crtc_state
->pixel_rate
=
6914 ilk_pipe_pixel_rate(crtc_state
);
6917 static int intel_crtc_compute_config(struct intel_crtc
*crtc
,
6918 struct intel_crtc_state
*pipe_config
)
6920 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
6921 const struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
6922 int clock_limit
= dev_priv
->max_dotclk_freq
;
6924 if (INTEL_GEN(dev_priv
) < 4) {
6925 clock_limit
= dev_priv
->max_cdclk_freq
* 9 / 10;
6928 * Enable double wide mode when the dot clock
6929 * is > 90% of the (display) core speed.
6931 if (intel_crtc_supports_double_wide(crtc
) &&
6932 adjusted_mode
->crtc_clock
> clock_limit
) {
6933 clock_limit
= dev_priv
->max_dotclk_freq
;
6934 pipe_config
->double_wide
= true;
6938 if (adjusted_mode
->crtc_clock
> clock_limit
) {
6939 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6940 adjusted_mode
->crtc_clock
, clock_limit
,
6941 yesno(pipe_config
->double_wide
));
6945 if ((pipe_config
->output_format
== INTEL_OUTPUT_FORMAT_YCBCR420
||
6946 pipe_config
->output_format
== INTEL_OUTPUT_FORMAT_YCBCR444
) &&
6947 pipe_config
->base
.ctm
) {
6949 * There is only one pipe CSC unit per pipe, and we need that
6950 * for output conversion from RGB->YCBCR. So if CTM is already
6951 * applied we can't support YCBCR420 output.
6953 DRM_DEBUG_KMS("YCBCR420 and CTM together are not possible\n");
6958 * Pipe horizontal size must be even in:
6960 * - LVDS dual channel mode
6961 * - Double wide pipe
6963 if (pipe_config
->pipe_src_w
& 1) {
6964 if (pipe_config
->double_wide
) {
6965 DRM_DEBUG_KMS("Odd pipe source width not supported with double wide pipe\n");
6969 if (intel_crtc_has_type(pipe_config
, INTEL_OUTPUT_LVDS
) &&
6970 intel_is_dual_link_lvds(dev_priv
)) {
6971 DRM_DEBUG_KMS("Odd pipe source width not supported with dual link LVDS\n");
6976 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6977 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6979 if ((INTEL_GEN(dev_priv
) > 4 || IS_G4X(dev_priv
)) &&
6980 adjusted_mode
->crtc_hsync_start
== adjusted_mode
->crtc_hdisplay
)
6983 intel_crtc_compute_pixel_rate(pipe_config
);
6985 if (pipe_config
->has_pch_encoder
)
6986 return ironlake_fdi_compute_config(crtc
, pipe_config
);
6992 intel_reduce_m_n_ratio(u32
*num
, u32
*den
)
6994 while (*num
> DATA_LINK_M_N_MASK
||
6995 *den
> DATA_LINK_M_N_MASK
) {
7001 static void compute_m_n(unsigned int m
, unsigned int n
,
7002 u32
*ret_m
, u32
*ret_n
,
7006 * Several DP dongles in particular seem to be fussy about
7007 * too large link M/N values. Give N value as 0x8000 that
7008 * should be acceptable by specific devices. 0x8000 is the
7009 * specified fixed N value for asynchronous clock mode,
7010 * which the devices expect also in synchronous clock mode.
7015 *ret_n
= min_t(unsigned int, roundup_pow_of_two(n
), DATA_LINK_N_MAX
);
7017 *ret_m
= div_u64((u64
)m
* *ret_n
, n
);
7018 intel_reduce_m_n_ratio(ret_m
, ret_n
);
7022 intel_link_compute_m_n(u16 bits_per_pixel
, int nlanes
,
7023 int pixel_clock
, int link_clock
,
7024 struct intel_link_m_n
*m_n
,
7029 compute_m_n(bits_per_pixel
* pixel_clock
,
7030 link_clock
* nlanes
* 8,
7031 &m_n
->gmch_m
, &m_n
->gmch_n
,
7034 compute_m_n(pixel_clock
, link_clock
,
7035 &m_n
->link_m
, &m_n
->link_n
,
7039 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
7041 if (i915_modparams
.panel_use_ssc
>= 0)
7042 return i915_modparams
.panel_use_ssc
!= 0;
7043 return dev_priv
->vbt
.lvds_use_ssc
7044 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
7047 static u32
pnv_dpll_compute_fp(struct dpll
*dpll
)
7049 return (1 << dpll
->n
) << 16 | dpll
->m2
;
7052 static u32
i9xx_dpll_compute_fp(struct dpll
*dpll
)
7054 return dpll
->n
<< 16 | dpll
->m1
<< 8 | dpll
->m2
;
7057 static void i9xx_update_pll_dividers(struct intel_crtc
*crtc
,
7058 struct intel_crtc_state
*crtc_state
,
7059 struct dpll
*reduced_clock
)
7061 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
7064 if (IS_PINEVIEW(dev_priv
)) {
7065 fp
= pnv_dpll_compute_fp(&crtc_state
->dpll
);
7067 fp2
= pnv_dpll_compute_fp(reduced_clock
);
7069 fp
= i9xx_dpll_compute_fp(&crtc_state
->dpll
);
7071 fp2
= i9xx_dpll_compute_fp(reduced_clock
);
7074 crtc_state
->dpll_hw_state
.fp0
= fp
;
7076 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
7078 crtc_state
->dpll_hw_state
.fp1
= fp2
;
7080 crtc_state
->dpll_hw_state
.fp1
= fp
;
7084 static void vlv_pllb_recal_opamp(struct drm_i915_private
*dev_priv
, enum pipe
7090 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7091 * and set it to a reasonable value instead.
7093 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
7094 reg_val
&= 0xffffff00;
7095 reg_val
|= 0x00000030;
7096 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
7098 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
7099 reg_val
&= 0x00ffffff;
7100 reg_val
|= 0x8c000000;
7101 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
7103 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
7104 reg_val
&= 0xffffff00;
7105 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
7107 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
7108 reg_val
&= 0x00ffffff;
7109 reg_val
|= 0xb0000000;
7110 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
7113 static void intel_pch_transcoder_set_m_n(const struct intel_crtc_state
*crtc_state
,
7114 const struct intel_link_m_n
*m_n
)
7116 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
7117 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
7118 enum pipe pipe
= crtc
->pipe
;
7120 I915_WRITE(PCH_TRANS_DATA_M1(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
7121 I915_WRITE(PCH_TRANS_DATA_N1(pipe
), m_n
->gmch_n
);
7122 I915_WRITE(PCH_TRANS_LINK_M1(pipe
), m_n
->link_m
);
7123 I915_WRITE(PCH_TRANS_LINK_N1(pipe
), m_n
->link_n
);
7126 static bool transcoder_has_m2_n2(struct drm_i915_private
*dev_priv
,
7127 enum transcoder transcoder
)
7129 if (IS_HASWELL(dev_priv
))
7130 return transcoder
== TRANSCODER_EDP
;
7133 * Strictly speaking some registers are available before
7134 * gen7, but we only support DRRS on gen7+
7136 return IS_GEN(dev_priv
, 7) || IS_CHERRYVIEW(dev_priv
);
7139 static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state
*crtc_state
,
7140 const struct intel_link_m_n
*m_n
,
7141 const struct intel_link_m_n
*m2_n2
)
7143 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
7144 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
7145 enum pipe pipe
= crtc
->pipe
;
7146 enum transcoder transcoder
= crtc_state
->cpu_transcoder
;
7148 if (INTEL_GEN(dev_priv
) >= 5) {
7149 I915_WRITE(PIPE_DATA_M1(transcoder
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
7150 I915_WRITE(PIPE_DATA_N1(transcoder
), m_n
->gmch_n
);
7151 I915_WRITE(PIPE_LINK_M1(transcoder
), m_n
->link_m
);
7152 I915_WRITE(PIPE_LINK_N1(transcoder
), m_n
->link_n
);
7154 * M2_N2 registers are set only if DRRS is supported
7155 * (to make sure the registers are not unnecessarily accessed).
7157 if (m2_n2
&& crtc_state
->has_drrs
&&
7158 transcoder_has_m2_n2(dev_priv
, transcoder
)) {
7159 I915_WRITE(PIPE_DATA_M2(transcoder
),
7160 TU_SIZE(m2_n2
->tu
) | m2_n2
->gmch_m
);
7161 I915_WRITE(PIPE_DATA_N2(transcoder
), m2_n2
->gmch_n
);
7162 I915_WRITE(PIPE_LINK_M2(transcoder
), m2_n2
->link_m
);
7163 I915_WRITE(PIPE_LINK_N2(transcoder
), m2_n2
->link_n
);
7166 I915_WRITE(PIPE_DATA_M_G4X(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
7167 I915_WRITE(PIPE_DATA_N_G4X(pipe
), m_n
->gmch_n
);
7168 I915_WRITE(PIPE_LINK_M_G4X(pipe
), m_n
->link_m
);
7169 I915_WRITE(PIPE_LINK_N_G4X(pipe
), m_n
->link_n
);
7173 void intel_dp_set_m_n(const struct intel_crtc_state
*crtc_state
, enum link_m_n_set m_n
)
7175 const struct intel_link_m_n
*dp_m_n
, *dp_m2_n2
= NULL
;
7178 dp_m_n
= &crtc_state
->dp_m_n
;
7179 dp_m2_n2
= &crtc_state
->dp_m2_n2
;
7180 } else if (m_n
== M2_N2
) {
7183 * M2_N2 registers are not supported. Hence m2_n2 divider value
7184 * needs to be programmed into M1_N1.
7186 dp_m_n
= &crtc_state
->dp_m2_n2
;
7188 DRM_ERROR("Unsupported divider value\n");
7192 if (crtc_state
->has_pch_encoder
)
7193 intel_pch_transcoder_set_m_n(crtc_state
, &crtc_state
->dp_m_n
);
7195 intel_cpu_transcoder_set_m_n(crtc_state
, dp_m_n
, dp_m2_n2
);
7198 static void vlv_compute_dpll(struct intel_crtc
*crtc
,
7199 struct intel_crtc_state
*pipe_config
)
7201 pipe_config
->dpll_hw_state
.dpll
= DPLL_INTEGRATED_REF_CLK_VLV
|
7202 DPLL_REF_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
;
7203 if (crtc
->pipe
!= PIPE_A
)
7204 pipe_config
->dpll_hw_state
.dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
7206 /* DPLL not used with DSI, but still need the rest set up */
7207 if (!intel_crtc_has_type(pipe_config
, INTEL_OUTPUT_DSI
))
7208 pipe_config
->dpll_hw_state
.dpll
|= DPLL_VCO_ENABLE
|
7209 DPLL_EXT_BUFFER_ENABLE_VLV
;
7211 pipe_config
->dpll_hw_state
.dpll_md
=
7212 (pipe_config
->pixel_multiplier
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
7215 static void chv_compute_dpll(struct intel_crtc
*crtc
,
7216 struct intel_crtc_state
*pipe_config
)
7218 pipe_config
->dpll_hw_state
.dpll
= DPLL_SSC_REF_CLK_CHV
|
7219 DPLL_REF_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
;
7220 if (crtc
->pipe
!= PIPE_A
)
7221 pipe_config
->dpll_hw_state
.dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
7223 /* DPLL not used with DSI, but still need the rest set up */
7224 if (!intel_crtc_has_type(pipe_config
, INTEL_OUTPUT_DSI
))
7225 pipe_config
->dpll_hw_state
.dpll
|= DPLL_VCO_ENABLE
;
7227 pipe_config
->dpll_hw_state
.dpll_md
=
7228 (pipe_config
->pixel_multiplier
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
7231 static void vlv_prepare_pll(struct intel_crtc
*crtc
,
7232 const struct intel_crtc_state
*pipe_config
)
7234 struct drm_device
*dev
= crtc
->base
.dev
;
7235 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7236 enum pipe pipe
= crtc
->pipe
;
7238 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
7239 u32 coreclk
, reg_val
;
7242 I915_WRITE(DPLL(pipe
),
7243 pipe_config
->dpll_hw_state
.dpll
&
7244 ~(DPLL_VCO_ENABLE
| DPLL_EXT_BUFFER_ENABLE_VLV
));
7246 /* No need to actually set up the DPLL with DSI */
7247 if ((pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
) == 0)
7250 mutex_lock(&dev_priv
->sb_lock
);
7252 bestn
= pipe_config
->dpll
.n
;
7253 bestm1
= pipe_config
->dpll
.m1
;
7254 bestm2
= pipe_config
->dpll
.m2
;
7255 bestp1
= pipe_config
->dpll
.p1
;
7256 bestp2
= pipe_config
->dpll
.p2
;
7258 /* See eDP HDMI DPIO driver vbios notes doc */
7260 /* PLL B needs special handling */
7262 vlv_pllb_recal_opamp(dev_priv
, pipe
);
7264 /* Set up Tx target for periodic Rcomp update */
7265 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9_BCAST
, 0x0100000f);
7267 /* Disable target IRef on PLL */
7268 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW8(pipe
));
7269 reg_val
&= 0x00ffffff;
7270 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW8(pipe
), reg_val
);
7272 /* Disable fast lock */
7273 vlv_dpio_write(dev_priv
, pipe
, VLV_CMN_DW0
, 0x610);
7275 /* Set idtafcrecal before PLL is enabled */
7276 mdiv
= ((bestm1
<< DPIO_M1DIV_SHIFT
) | (bestm2
& DPIO_M2DIV_MASK
));
7277 mdiv
|= ((bestp1
<< DPIO_P1_SHIFT
) | (bestp2
<< DPIO_P2_SHIFT
));
7278 mdiv
|= ((bestn
<< DPIO_N_SHIFT
));
7279 mdiv
|= (1 << DPIO_K_SHIFT
);
7282 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7283 * but we don't support that).
7284 * Note: don't use the DAC post divider as it seems unstable.
7286 mdiv
|= (DPIO_POST_DIV_HDMIDP
<< DPIO_POST_DIV_SHIFT
);
7287 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
7289 mdiv
|= DPIO_ENABLE_CALIBRATION
;
7290 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
7292 /* Set HBR and RBR LPF coefficients */
7293 if (pipe_config
->port_clock
== 162000 ||
7294 intel_crtc_has_type(pipe_config
, INTEL_OUTPUT_ANALOG
) ||
7295 intel_crtc_has_type(pipe_config
, INTEL_OUTPUT_HDMI
))
7296 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
7299 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
7302 if (intel_crtc_has_dp_encoder(pipe_config
)) {
7303 /* Use SSC source */
7305 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
7308 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
7310 } else { /* HDMI or VGA */
7311 /* Use bend source */
7313 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
7316 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
7320 coreclk
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW7(pipe
));
7321 coreclk
= (coreclk
& 0x0000ff00) | 0x01c00000;
7322 if (intel_crtc_has_dp_encoder(pipe_config
))
7323 coreclk
|= 0x01000000;
7324 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW7(pipe
), coreclk
);
7326 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW11(pipe
), 0x87871000);
7327 mutex_unlock(&dev_priv
->sb_lock
);
7330 static void chv_prepare_pll(struct intel_crtc
*crtc
,
7331 const struct intel_crtc_state
*pipe_config
)
7333 struct drm_device
*dev
= crtc
->base
.dev
;
7334 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7335 enum pipe pipe
= crtc
->pipe
;
7336 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
7337 u32 loopfilter
, tribuf_calcntr
;
7338 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
, bestm2_frac
;
7342 /* Enable Refclk and SSC */
7343 I915_WRITE(DPLL(pipe
),
7344 pipe_config
->dpll_hw_state
.dpll
& ~DPLL_VCO_ENABLE
);
7346 /* No need to actually set up the DPLL with DSI */
7347 if ((pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
) == 0)
7350 bestn
= pipe_config
->dpll
.n
;
7351 bestm2_frac
= pipe_config
->dpll
.m2
& 0x3fffff;
7352 bestm1
= pipe_config
->dpll
.m1
;
7353 bestm2
= pipe_config
->dpll
.m2
>> 22;
7354 bestp1
= pipe_config
->dpll
.p1
;
7355 bestp2
= pipe_config
->dpll
.p2
;
7356 vco
= pipe_config
->dpll
.vco
;
7360 mutex_lock(&dev_priv
->sb_lock
);
7362 /* p1 and p2 divider */
7363 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW13(port
),
7364 5 << DPIO_CHV_S1_DIV_SHIFT
|
7365 bestp1
<< DPIO_CHV_P1_DIV_SHIFT
|
7366 bestp2
<< DPIO_CHV_P2_DIV_SHIFT
|
7367 1 << DPIO_CHV_K_DIV_SHIFT
);
7369 /* Feedback post-divider - m2 */
7370 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW0(port
), bestm2
);
7372 /* Feedback refclk divider - n and m1 */
7373 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW1(port
),
7374 DPIO_CHV_M1_DIV_BY_2
|
7375 1 << DPIO_CHV_N_DIV_SHIFT
);
7377 /* M2 fraction division */
7378 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW2(port
), bestm2_frac
);
7380 /* M2 fraction division enable */
7381 dpio_val
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW3(port
));
7382 dpio_val
&= ~(DPIO_CHV_FEEDFWD_GAIN_MASK
| DPIO_CHV_FRAC_DIV_EN
);
7383 dpio_val
|= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT
);
7385 dpio_val
|= DPIO_CHV_FRAC_DIV_EN
;
7386 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW3(port
), dpio_val
);
7388 /* Program digital lock detect threshold */
7389 dpio_val
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW9(port
));
7390 dpio_val
&= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK
|
7391 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE
);
7392 dpio_val
|= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT
);
7394 dpio_val
|= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE
;
7395 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW9(port
), dpio_val
);
7398 if (vco
== 5400000) {
7399 loopfilter
|= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT
);
7400 loopfilter
|= (0x8 << DPIO_CHV_INT_COEFF_SHIFT
);
7401 loopfilter
|= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7402 tribuf_calcntr
= 0x9;
7403 } else if (vco
<= 6200000) {
7404 loopfilter
|= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT
);
7405 loopfilter
|= (0xB << DPIO_CHV_INT_COEFF_SHIFT
);
7406 loopfilter
|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7407 tribuf_calcntr
= 0x9;
7408 } else if (vco
<= 6480000) {
7409 loopfilter
|= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT
);
7410 loopfilter
|= (0x9 << DPIO_CHV_INT_COEFF_SHIFT
);
7411 loopfilter
|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7412 tribuf_calcntr
= 0x8;
7414 /* Not supported. Apply the same limits as in the max case */
7415 loopfilter
|= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT
);
7416 loopfilter
|= (0x9 << DPIO_CHV_INT_COEFF_SHIFT
);
7417 loopfilter
|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7420 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW6(port
), loopfilter
);
7422 dpio_val
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW8(port
));
7423 dpio_val
&= ~DPIO_CHV_TDC_TARGET_CNT_MASK
;
7424 dpio_val
|= (tribuf_calcntr
<< DPIO_CHV_TDC_TARGET_CNT_SHIFT
);
7425 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW8(port
), dpio_val
);
7428 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
),
7429 vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
)) |
7432 mutex_unlock(&dev_priv
->sb_lock
);
7436 * vlv_force_pll_on - forcibly enable just the PLL
7437 * @dev_priv: i915 private structure
7438 * @pipe: pipe PLL to enable
7439 * @dpll: PLL configuration
7441 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7442 * in cases where we need the PLL enabled even when @pipe is not going to
7445 int vlv_force_pll_on(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
7446 const struct dpll
*dpll
)
7448 struct intel_crtc
*crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
7449 struct intel_crtc_state
*pipe_config
;
7451 pipe_config
= kzalloc(sizeof(*pipe_config
), GFP_KERNEL
);
7455 pipe_config
->base
.crtc
= &crtc
->base
;
7456 pipe_config
->pixel_multiplier
= 1;
7457 pipe_config
->dpll
= *dpll
;
7459 if (IS_CHERRYVIEW(dev_priv
)) {
7460 chv_compute_dpll(crtc
, pipe_config
);
7461 chv_prepare_pll(crtc
, pipe_config
);
7462 chv_enable_pll(crtc
, pipe_config
);
7464 vlv_compute_dpll(crtc
, pipe_config
);
7465 vlv_prepare_pll(crtc
, pipe_config
);
7466 vlv_enable_pll(crtc
, pipe_config
);
7475 * vlv_force_pll_off - forcibly disable just the PLL
7476 * @dev_priv: i915 private structure
7477 * @pipe: pipe PLL to disable
7479 * Disable the PLL for @pipe. To be used in cases where we need
7480 * the PLL enabled even when @pipe is not going to be enabled.
7482 void vlv_force_pll_off(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
7484 if (IS_CHERRYVIEW(dev_priv
))
7485 chv_disable_pll(dev_priv
, pipe
);
7487 vlv_disable_pll(dev_priv
, pipe
);
7490 static void i9xx_compute_dpll(struct intel_crtc
*crtc
,
7491 struct intel_crtc_state
*crtc_state
,
7492 struct dpll
*reduced_clock
)
7494 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
7496 struct dpll
*clock
= &crtc_state
->dpll
;
7498 i9xx_update_pll_dividers(crtc
, crtc_state
, reduced_clock
);
7500 dpll
= DPLL_VGA_MODE_DIS
;
7502 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
))
7503 dpll
|= DPLLB_MODE_LVDS
;
7505 dpll
|= DPLLB_MODE_DAC_SERIAL
;
7507 if (IS_I945G(dev_priv
) || IS_I945GM(dev_priv
) ||
7508 IS_G33(dev_priv
) || IS_PINEVIEW(dev_priv
)) {
7509 dpll
|= (crtc_state
->pixel_multiplier
- 1)
7510 << SDVO_MULTIPLIER_SHIFT_HIRES
;
7513 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_SDVO
) ||
7514 intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_HDMI
))
7515 dpll
|= DPLL_SDVO_HIGH_SPEED
;
7517 if (intel_crtc_has_dp_encoder(crtc_state
))
7518 dpll
|= DPLL_SDVO_HIGH_SPEED
;
7520 /* compute bitmask from p1 value */
7521 if (IS_PINEVIEW(dev_priv
))
7522 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
7524 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7525 if (IS_G4X(dev_priv
) && reduced_clock
)
7526 dpll
|= (1 << (reduced_clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
7528 switch (clock
->p2
) {
7530 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
7533 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
7536 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
7539 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
7542 if (INTEL_GEN(dev_priv
) >= 4)
7543 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
7545 if (crtc_state
->sdvo_tv_clock
)
7546 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
7547 else if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
7548 intel_panel_use_ssc(dev_priv
))
7549 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
7551 dpll
|= PLL_REF_INPUT_DREFCLK
;
7553 dpll
|= DPLL_VCO_ENABLE
;
7554 crtc_state
->dpll_hw_state
.dpll
= dpll
;
7556 if (INTEL_GEN(dev_priv
) >= 4) {
7557 u32 dpll_md
= (crtc_state
->pixel_multiplier
- 1)
7558 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
7559 crtc_state
->dpll_hw_state
.dpll_md
= dpll_md
;
7563 static void i8xx_compute_dpll(struct intel_crtc
*crtc
,
7564 struct intel_crtc_state
*crtc_state
,
7565 struct dpll
*reduced_clock
)
7567 struct drm_device
*dev
= crtc
->base
.dev
;
7568 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7570 struct dpll
*clock
= &crtc_state
->dpll
;
7572 i9xx_update_pll_dividers(crtc
, crtc_state
, reduced_clock
);
7574 dpll
= DPLL_VGA_MODE_DIS
;
7576 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
7577 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7580 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
7582 dpll
|= (clock
->p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7584 dpll
|= PLL_P2_DIVIDE_BY_4
;
7589 * "[Almador Errata}: For the correct operation of the muxed DVO pins
7590 * (GDEVSELB/I2Cdata, GIRDBY/I2CClk) and (GFRAMEB/DVI_Data,
7591 * GTRDYB/DVI_Clk): Bit 31 (DPLL VCO Enable) and Bit 30 (2X Clock
7592 * Enable) must be set to “1” in both the DPLL A Control Register
7593 * (06014h-06017h) and DPLL B Control Register (06018h-0601Bh)."
7595 * For simplicity We simply keep both bits always enabled in
7596 * both DPLLS. The spec says we should disable the DVO 2X clock
7597 * when not needed, but this seems to work fine in practice.
7599 if (IS_I830(dev_priv
) ||
7600 intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_DVO
))
7601 dpll
|= DPLL_DVO_2X_MODE
;
7603 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
7604 intel_panel_use_ssc(dev_priv
))
7605 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
7607 dpll
|= PLL_REF_INPUT_DREFCLK
;
7609 dpll
|= DPLL_VCO_ENABLE
;
7610 crtc_state
->dpll_hw_state
.dpll
= dpll
;
7613 static void intel_set_pipe_timings(const struct intel_crtc_state
*crtc_state
)
7615 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
7616 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
7617 enum pipe pipe
= crtc
->pipe
;
7618 enum transcoder cpu_transcoder
= crtc_state
->cpu_transcoder
;
7619 const struct drm_display_mode
*adjusted_mode
= &crtc_state
->base
.adjusted_mode
;
7620 u32 crtc_vtotal
, crtc_vblank_end
;
7623 /* We need to be careful not to changed the adjusted mode, for otherwise
7624 * the hw state checker will get angry at the mismatch. */
7625 crtc_vtotal
= adjusted_mode
->crtc_vtotal
;
7626 crtc_vblank_end
= adjusted_mode
->crtc_vblank_end
;
7628 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
7629 /* the chip adds 2 halflines automatically */
7631 crtc_vblank_end
-= 1;
7633 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_SDVO
))
7634 vsyncshift
= (adjusted_mode
->crtc_htotal
- 1) / 2;
7636 vsyncshift
= adjusted_mode
->crtc_hsync_start
-
7637 adjusted_mode
->crtc_htotal
/ 2;
7639 vsyncshift
+= adjusted_mode
->crtc_htotal
;
7642 if (INTEL_GEN(dev_priv
) > 3)
7643 I915_WRITE(VSYNCSHIFT(cpu_transcoder
), vsyncshift
);
7645 I915_WRITE(HTOTAL(cpu_transcoder
),
7646 (adjusted_mode
->crtc_hdisplay
- 1) |
7647 ((adjusted_mode
->crtc_htotal
- 1) << 16));
7648 I915_WRITE(HBLANK(cpu_transcoder
),
7649 (adjusted_mode
->crtc_hblank_start
- 1) |
7650 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
7651 I915_WRITE(HSYNC(cpu_transcoder
),
7652 (adjusted_mode
->crtc_hsync_start
- 1) |
7653 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
7655 I915_WRITE(VTOTAL(cpu_transcoder
),
7656 (adjusted_mode
->crtc_vdisplay
- 1) |
7657 ((crtc_vtotal
- 1) << 16));
7658 I915_WRITE(VBLANK(cpu_transcoder
),
7659 (adjusted_mode
->crtc_vblank_start
- 1) |
7660 ((crtc_vblank_end
- 1) << 16));
7661 I915_WRITE(VSYNC(cpu_transcoder
),
7662 (adjusted_mode
->crtc_vsync_start
- 1) |
7663 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
7665 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7666 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7667 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7669 if (IS_HASWELL(dev_priv
) && cpu_transcoder
== TRANSCODER_EDP
&&
7670 (pipe
== PIPE_B
|| pipe
== PIPE_C
))
7671 I915_WRITE(VTOTAL(pipe
), I915_READ(VTOTAL(cpu_transcoder
)));
7675 static void intel_set_pipe_src_size(const struct intel_crtc_state
*crtc_state
)
7677 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
7678 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
7679 enum pipe pipe
= crtc
->pipe
;
7681 /* pipesrc controls the size that is scaled from, which should
7682 * always be the user's requested size.
7684 I915_WRITE(PIPESRC(pipe
),
7685 ((crtc_state
->pipe_src_w
- 1) << 16) |
7686 (crtc_state
->pipe_src_h
- 1));
7689 static void intel_get_pipe_timings(struct intel_crtc
*crtc
,
7690 struct intel_crtc_state
*pipe_config
)
7692 struct drm_device
*dev
= crtc
->base
.dev
;
7693 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7694 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
7697 tmp
= I915_READ(HTOTAL(cpu_transcoder
));
7698 pipe_config
->base
.adjusted_mode
.crtc_hdisplay
= (tmp
& 0xffff) + 1;
7699 pipe_config
->base
.adjusted_mode
.crtc_htotal
= ((tmp
>> 16) & 0xffff) + 1;
7700 tmp
= I915_READ(HBLANK(cpu_transcoder
));
7701 pipe_config
->base
.adjusted_mode
.crtc_hblank_start
= (tmp
& 0xffff) + 1;
7702 pipe_config
->base
.adjusted_mode
.crtc_hblank_end
= ((tmp
>> 16) & 0xffff) + 1;
7703 tmp
= I915_READ(HSYNC(cpu_transcoder
));
7704 pipe_config
->base
.adjusted_mode
.crtc_hsync_start
= (tmp
& 0xffff) + 1;
7705 pipe_config
->base
.adjusted_mode
.crtc_hsync_end
= ((tmp
>> 16) & 0xffff) + 1;
7707 tmp
= I915_READ(VTOTAL(cpu_transcoder
));
7708 pipe_config
->base
.adjusted_mode
.crtc_vdisplay
= (tmp
& 0xffff) + 1;
7709 pipe_config
->base
.adjusted_mode
.crtc_vtotal
= ((tmp
>> 16) & 0xffff) + 1;
7710 tmp
= I915_READ(VBLANK(cpu_transcoder
));
7711 pipe_config
->base
.adjusted_mode
.crtc_vblank_start
= (tmp
& 0xffff) + 1;
7712 pipe_config
->base
.adjusted_mode
.crtc_vblank_end
= ((tmp
>> 16) & 0xffff) + 1;
7713 tmp
= I915_READ(VSYNC(cpu_transcoder
));
7714 pipe_config
->base
.adjusted_mode
.crtc_vsync_start
= (tmp
& 0xffff) + 1;
7715 pipe_config
->base
.adjusted_mode
.crtc_vsync_end
= ((tmp
>> 16) & 0xffff) + 1;
7717 if (I915_READ(PIPECONF(cpu_transcoder
)) & PIPECONF_INTERLACE_MASK
) {
7718 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_INTERLACE
;
7719 pipe_config
->base
.adjusted_mode
.crtc_vtotal
+= 1;
7720 pipe_config
->base
.adjusted_mode
.crtc_vblank_end
+= 1;
7724 static void intel_get_pipe_src_size(struct intel_crtc
*crtc
,
7725 struct intel_crtc_state
*pipe_config
)
7727 struct drm_device
*dev
= crtc
->base
.dev
;
7728 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7731 tmp
= I915_READ(PIPESRC(crtc
->pipe
));
7732 pipe_config
->pipe_src_h
= (tmp
& 0xffff) + 1;
7733 pipe_config
->pipe_src_w
= ((tmp
>> 16) & 0xffff) + 1;
7735 pipe_config
->base
.mode
.vdisplay
= pipe_config
->pipe_src_h
;
7736 pipe_config
->base
.mode
.hdisplay
= pipe_config
->pipe_src_w
;
7739 void intel_mode_from_pipe_config(struct drm_display_mode
*mode
,
7740 struct intel_crtc_state
*pipe_config
)
7742 mode
->hdisplay
= pipe_config
->base
.adjusted_mode
.crtc_hdisplay
;
7743 mode
->htotal
= pipe_config
->base
.adjusted_mode
.crtc_htotal
;
7744 mode
->hsync_start
= pipe_config
->base
.adjusted_mode
.crtc_hsync_start
;
7745 mode
->hsync_end
= pipe_config
->base
.adjusted_mode
.crtc_hsync_end
;
7747 mode
->vdisplay
= pipe_config
->base
.adjusted_mode
.crtc_vdisplay
;
7748 mode
->vtotal
= pipe_config
->base
.adjusted_mode
.crtc_vtotal
;
7749 mode
->vsync_start
= pipe_config
->base
.adjusted_mode
.crtc_vsync_start
;
7750 mode
->vsync_end
= pipe_config
->base
.adjusted_mode
.crtc_vsync_end
;
7752 mode
->flags
= pipe_config
->base
.adjusted_mode
.flags
;
7753 mode
->type
= DRM_MODE_TYPE_DRIVER
;
7755 mode
->clock
= pipe_config
->base
.adjusted_mode
.crtc_clock
;
7757 mode
->hsync
= drm_mode_hsync(mode
);
7758 mode
->vrefresh
= drm_mode_vrefresh(mode
);
7759 drm_mode_set_name(mode
);
7762 static void i9xx_set_pipeconf(const struct intel_crtc_state
*crtc_state
)
7764 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
7765 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
7770 /* we keep both pipes enabled on 830 */
7771 if (IS_I830(dev_priv
))
7772 pipeconf
|= I915_READ(PIPECONF(crtc
->pipe
)) & PIPECONF_ENABLE
;
7774 if (crtc_state
->double_wide
)
7775 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
7777 /* only g4x and later have fancy bpc/dither controls */
7778 if (IS_G4X(dev_priv
) || IS_VALLEYVIEW(dev_priv
) ||
7779 IS_CHERRYVIEW(dev_priv
)) {
7780 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7781 if (crtc_state
->dither
&& crtc_state
->pipe_bpp
!= 30)
7782 pipeconf
|= PIPECONF_DITHER_EN
|
7783 PIPECONF_DITHER_TYPE_SP
;
7785 switch (crtc_state
->pipe_bpp
) {
7787 pipeconf
|= PIPECONF_6BPC
;
7790 pipeconf
|= PIPECONF_8BPC
;
7793 pipeconf
|= PIPECONF_10BPC
;
7796 /* Case prevented by intel_choose_pipe_bpp_dither. */
7801 if (crtc_state
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
) {
7802 if (INTEL_GEN(dev_priv
) < 4 ||
7803 intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_SDVO
))
7804 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
7806 pipeconf
|= PIPECONF_INTERLACE_W_SYNC_SHIFT
;
7808 pipeconf
|= PIPECONF_PROGRESSIVE
;
7811 if ((IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) &&
7812 crtc_state
->limited_color_range
)
7813 pipeconf
|= PIPECONF_COLOR_RANGE_SELECT
;
7815 pipeconf
|= PIPECONF_GAMMA_MODE(crtc_state
->gamma_mode
);
7817 I915_WRITE(PIPECONF(crtc
->pipe
), pipeconf
);
7818 POSTING_READ(PIPECONF(crtc
->pipe
));
7821 static int i8xx_crtc_compute_clock(struct intel_crtc
*crtc
,
7822 struct intel_crtc_state
*crtc_state
)
7824 struct drm_device
*dev
= crtc
->base
.dev
;
7825 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7826 const struct intel_limit
*limit
;
7829 memset(&crtc_state
->dpll_hw_state
, 0,
7830 sizeof(crtc_state
->dpll_hw_state
));
7832 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
7833 if (intel_panel_use_ssc(dev_priv
)) {
7834 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
7835 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
7838 limit
= &intel_limits_i8xx_lvds
;
7839 } else if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_DVO
)) {
7840 limit
= &intel_limits_i8xx_dvo
;
7842 limit
= &intel_limits_i8xx_dac
;
7845 if (!crtc_state
->clock_set
&&
7846 !i9xx_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
7847 refclk
, NULL
, &crtc_state
->dpll
)) {
7848 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7852 i8xx_compute_dpll(crtc
, crtc_state
, NULL
);
7857 static int g4x_crtc_compute_clock(struct intel_crtc
*crtc
,
7858 struct intel_crtc_state
*crtc_state
)
7860 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
7861 const struct intel_limit
*limit
;
7864 memset(&crtc_state
->dpll_hw_state
, 0,
7865 sizeof(crtc_state
->dpll_hw_state
));
7867 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
7868 if (intel_panel_use_ssc(dev_priv
)) {
7869 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
7870 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
7873 if (intel_is_dual_link_lvds(dev_priv
))
7874 limit
= &intel_limits_g4x_dual_channel_lvds
;
7876 limit
= &intel_limits_g4x_single_channel_lvds
;
7877 } else if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_HDMI
) ||
7878 intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_ANALOG
)) {
7879 limit
= &intel_limits_g4x_hdmi
;
7880 } else if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_SDVO
)) {
7881 limit
= &intel_limits_g4x_sdvo
;
7883 /* The option is for other outputs */
7884 limit
= &intel_limits_i9xx_sdvo
;
7887 if (!crtc_state
->clock_set
&&
7888 !g4x_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
7889 refclk
, NULL
, &crtc_state
->dpll
)) {
7890 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7894 i9xx_compute_dpll(crtc
, crtc_state
, NULL
);
7899 static int pnv_crtc_compute_clock(struct intel_crtc
*crtc
,
7900 struct intel_crtc_state
*crtc_state
)
7902 struct drm_device
*dev
= crtc
->base
.dev
;
7903 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7904 const struct intel_limit
*limit
;
7907 memset(&crtc_state
->dpll_hw_state
, 0,
7908 sizeof(crtc_state
->dpll_hw_state
));
7910 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
7911 if (intel_panel_use_ssc(dev_priv
)) {
7912 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
7913 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
7916 limit
= &intel_limits_pineview_lvds
;
7918 limit
= &intel_limits_pineview_sdvo
;
7921 if (!crtc_state
->clock_set
&&
7922 !pnv_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
7923 refclk
, NULL
, &crtc_state
->dpll
)) {
7924 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7928 i9xx_compute_dpll(crtc
, crtc_state
, NULL
);
7933 static int i9xx_crtc_compute_clock(struct intel_crtc
*crtc
,
7934 struct intel_crtc_state
*crtc_state
)
7936 struct drm_device
*dev
= crtc
->base
.dev
;
7937 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7938 const struct intel_limit
*limit
;
7941 memset(&crtc_state
->dpll_hw_state
, 0,
7942 sizeof(crtc_state
->dpll_hw_state
));
7944 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
7945 if (intel_panel_use_ssc(dev_priv
)) {
7946 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
7947 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
7950 limit
= &intel_limits_i9xx_lvds
;
7952 limit
= &intel_limits_i9xx_sdvo
;
7955 if (!crtc_state
->clock_set
&&
7956 !i9xx_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
7957 refclk
, NULL
, &crtc_state
->dpll
)) {
7958 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7962 i9xx_compute_dpll(crtc
, crtc_state
, NULL
);
7967 static int chv_crtc_compute_clock(struct intel_crtc
*crtc
,
7968 struct intel_crtc_state
*crtc_state
)
7970 int refclk
= 100000;
7971 const struct intel_limit
*limit
= &intel_limits_chv
;
7973 memset(&crtc_state
->dpll_hw_state
, 0,
7974 sizeof(crtc_state
->dpll_hw_state
));
7976 if (!crtc_state
->clock_set
&&
7977 !chv_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
7978 refclk
, NULL
, &crtc_state
->dpll
)) {
7979 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7983 chv_compute_dpll(crtc
, crtc_state
);
7988 static int vlv_crtc_compute_clock(struct intel_crtc
*crtc
,
7989 struct intel_crtc_state
*crtc_state
)
7991 int refclk
= 100000;
7992 const struct intel_limit
*limit
= &intel_limits_vlv
;
7994 memset(&crtc_state
->dpll_hw_state
, 0,
7995 sizeof(crtc_state
->dpll_hw_state
));
7997 if (!crtc_state
->clock_set
&&
7998 !vlv_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
7999 refclk
, NULL
, &crtc_state
->dpll
)) {
8000 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8004 vlv_compute_dpll(crtc
, crtc_state
);
8009 static bool i9xx_has_pfit(struct drm_i915_private
*dev_priv
)
8011 if (IS_I830(dev_priv
))
8014 return INTEL_GEN(dev_priv
) >= 4 ||
8015 IS_PINEVIEW(dev_priv
) || IS_MOBILE(dev_priv
);
8018 static void i9xx_get_pfit_config(struct intel_crtc
*crtc
,
8019 struct intel_crtc_state
*pipe_config
)
8021 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
8024 if (!i9xx_has_pfit(dev_priv
))
8027 tmp
= I915_READ(PFIT_CONTROL
);
8028 if (!(tmp
& PFIT_ENABLE
))
8031 /* Check whether the pfit is attached to our pipe. */
8032 if (INTEL_GEN(dev_priv
) < 4) {
8033 if (crtc
->pipe
!= PIPE_B
)
8036 if ((tmp
& PFIT_PIPE_MASK
) != (crtc
->pipe
<< PFIT_PIPE_SHIFT
))
8040 pipe_config
->gmch_pfit
.control
= tmp
;
8041 pipe_config
->gmch_pfit
.pgm_ratios
= I915_READ(PFIT_PGM_RATIOS
);
8044 static void vlv_crtc_clock_get(struct intel_crtc
*crtc
,
8045 struct intel_crtc_state
*pipe_config
)
8047 struct drm_device
*dev
= crtc
->base
.dev
;
8048 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8049 int pipe
= pipe_config
->cpu_transcoder
;
8052 int refclk
= 100000;
8054 /* In case of DSI, DPLL will not be used */
8055 if ((pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
) == 0)
8058 mutex_lock(&dev_priv
->sb_lock
);
8059 mdiv
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW3(pipe
));
8060 mutex_unlock(&dev_priv
->sb_lock
);
8062 clock
.m1
= (mdiv
>> DPIO_M1DIV_SHIFT
) & 7;
8063 clock
.m2
= mdiv
& DPIO_M2DIV_MASK
;
8064 clock
.n
= (mdiv
>> DPIO_N_SHIFT
) & 0xf;
8065 clock
.p1
= (mdiv
>> DPIO_P1_SHIFT
) & 7;
8066 clock
.p2
= (mdiv
>> DPIO_P2_SHIFT
) & 0x1f;
8068 pipe_config
->port_clock
= vlv_calc_dpll_params(refclk
, &clock
);
8072 i9xx_get_initial_plane_config(struct intel_crtc
*crtc
,
8073 struct intel_initial_plane_config
*plane_config
)
8075 struct drm_device
*dev
= crtc
->base
.dev
;
8076 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8077 struct intel_plane
*plane
= to_intel_plane(crtc
->base
.primary
);
8078 enum i9xx_plane_id i9xx_plane
= plane
->i9xx_plane
;
8080 u32 val
, base
, offset
;
8081 int fourcc
, pixel_format
;
8082 unsigned int aligned_height
;
8083 struct drm_framebuffer
*fb
;
8084 struct intel_framebuffer
*intel_fb
;
8086 if (!plane
->get_hw_state(plane
, &pipe
))
8089 WARN_ON(pipe
!= crtc
->pipe
);
8091 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
8093 DRM_DEBUG_KMS("failed to alloc fb\n");
8097 fb
= &intel_fb
->base
;
8101 val
= I915_READ(DSPCNTR(i9xx_plane
));
8103 if (INTEL_GEN(dev_priv
) >= 4) {
8104 if (val
& DISPPLANE_TILED
) {
8105 plane_config
->tiling
= I915_TILING_X
;
8106 fb
->modifier
= I915_FORMAT_MOD_X_TILED
;
8109 if (val
& DISPPLANE_ROTATE_180
)
8110 plane_config
->rotation
= DRM_MODE_ROTATE_180
;
8113 if (IS_CHERRYVIEW(dev_priv
) && pipe
== PIPE_B
&&
8114 val
& DISPPLANE_MIRROR
)
8115 plane_config
->rotation
|= DRM_MODE_REFLECT_X
;
8117 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
8118 fourcc
= i9xx_format_to_fourcc(pixel_format
);
8119 fb
->format
= drm_format_info(fourcc
);
8121 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
8122 offset
= I915_READ(DSPOFFSET(i9xx_plane
));
8123 base
= I915_READ(DSPSURF(i9xx_plane
)) & 0xfffff000;
8124 } else if (INTEL_GEN(dev_priv
) >= 4) {
8125 if (plane_config
->tiling
)
8126 offset
= I915_READ(DSPTILEOFF(i9xx_plane
));
8128 offset
= I915_READ(DSPLINOFF(i9xx_plane
));
8129 base
= I915_READ(DSPSURF(i9xx_plane
)) & 0xfffff000;
8131 base
= I915_READ(DSPADDR(i9xx_plane
));
8133 plane_config
->base
= base
;
8135 val
= I915_READ(PIPESRC(pipe
));
8136 fb
->width
= ((val
>> 16) & 0xfff) + 1;
8137 fb
->height
= ((val
>> 0) & 0xfff) + 1;
8139 val
= I915_READ(DSPSTRIDE(i9xx_plane
));
8140 fb
->pitches
[0] = val
& 0xffffffc0;
8142 aligned_height
= intel_fb_align_height(fb
, 0, fb
->height
);
8144 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
8146 DRM_DEBUG_KMS("%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8147 crtc
->base
.name
, plane
->base
.name
, fb
->width
, fb
->height
,
8148 fb
->format
->cpp
[0] * 8, base
, fb
->pitches
[0],
8149 plane_config
->size
);
8151 plane_config
->fb
= intel_fb
;
8154 static void chv_crtc_clock_get(struct intel_crtc
*crtc
,
8155 struct intel_crtc_state
*pipe_config
)
8157 struct drm_device
*dev
= crtc
->base
.dev
;
8158 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8159 int pipe
= pipe_config
->cpu_transcoder
;
8160 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
8162 u32 cmn_dw13
, pll_dw0
, pll_dw1
, pll_dw2
, pll_dw3
;
8163 int refclk
= 100000;
8165 /* In case of DSI, DPLL will not be used */
8166 if ((pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
) == 0)
8169 mutex_lock(&dev_priv
->sb_lock
);
8170 cmn_dw13
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW13(port
));
8171 pll_dw0
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW0(port
));
8172 pll_dw1
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW1(port
));
8173 pll_dw2
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW2(port
));
8174 pll_dw3
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW3(port
));
8175 mutex_unlock(&dev_priv
->sb_lock
);
8177 clock
.m1
= (pll_dw1
& 0x7) == DPIO_CHV_M1_DIV_BY_2
? 2 : 0;
8178 clock
.m2
= (pll_dw0
& 0xff) << 22;
8179 if (pll_dw3
& DPIO_CHV_FRAC_DIV_EN
)
8180 clock
.m2
|= pll_dw2
& 0x3fffff;
8181 clock
.n
= (pll_dw1
>> DPIO_CHV_N_DIV_SHIFT
) & 0xf;
8182 clock
.p1
= (cmn_dw13
>> DPIO_CHV_P1_DIV_SHIFT
) & 0x7;
8183 clock
.p2
= (cmn_dw13
>> DPIO_CHV_P2_DIV_SHIFT
) & 0x1f;
8185 pipe_config
->port_clock
= chv_calc_dpll_params(refclk
, &clock
);
8188 static void intel_get_crtc_ycbcr_config(struct intel_crtc
*crtc
,
8189 struct intel_crtc_state
*pipe_config
)
8191 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
8192 enum intel_output_format output
= INTEL_OUTPUT_FORMAT_RGB
;
8194 pipe_config
->lspcon_downsampling
= false;
8196 if (IS_BROADWELL(dev_priv
) || INTEL_GEN(dev_priv
) >= 9) {
8197 u32 tmp
= I915_READ(PIPEMISC(crtc
->pipe
));
8199 if (tmp
& PIPEMISC_OUTPUT_COLORSPACE_YUV
) {
8200 bool ycbcr420_enabled
= tmp
& PIPEMISC_YUV420_ENABLE
;
8201 bool blend
= tmp
& PIPEMISC_YUV420_MODE_FULL_BLEND
;
8203 if (ycbcr420_enabled
) {
8204 /* We support 4:2:0 in full blend mode only */
8206 output
= INTEL_OUTPUT_FORMAT_INVALID
;
8207 else if (!(IS_GEMINILAKE(dev_priv
) ||
8208 INTEL_GEN(dev_priv
) >= 10))
8209 output
= INTEL_OUTPUT_FORMAT_INVALID
;
8211 output
= INTEL_OUTPUT_FORMAT_YCBCR420
;
8214 * Currently there is no interface defined to
8215 * check user preference between RGB/YCBCR444
8216 * or YCBCR420. So the only possible case for
8217 * YCBCR444 usage is driving YCBCR420 output
8218 * with LSPCON, when pipe is configured for
8219 * YCBCR444 output and LSPCON takes care of
8222 pipe_config
->lspcon_downsampling
= true;
8223 output
= INTEL_OUTPUT_FORMAT_YCBCR444
;
8228 pipe_config
->output_format
= output
;
8231 static void i9xx_get_pipe_color_config(struct intel_crtc_state
*crtc_state
)
8233 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
8234 struct intel_plane
*plane
= to_intel_plane(crtc
->base
.primary
);
8235 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
8236 enum i9xx_plane_id i9xx_plane
= plane
->i9xx_plane
;
8239 tmp
= I915_READ(DSPCNTR(i9xx_plane
));
8241 if (tmp
& DISPPLANE_GAMMA_ENABLE
)
8242 crtc_state
->gamma_enable
= true;
8244 if (!HAS_GMCH(dev_priv
) &&
8245 tmp
& DISPPLANE_PIPE_CSC_ENABLE
)
8246 crtc_state
->csc_enable
= true;
8249 static bool i9xx_get_pipe_config(struct intel_crtc
*crtc
,
8250 struct intel_crtc_state
*pipe_config
)
8252 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
8253 enum intel_display_power_domain power_domain
;
8254 intel_wakeref_t wakeref
;
8258 power_domain
= POWER_DOMAIN_PIPE(crtc
->pipe
);
8259 wakeref
= intel_display_power_get_if_enabled(dev_priv
, power_domain
);
8263 pipe_config
->output_format
= INTEL_OUTPUT_FORMAT_RGB
;
8264 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
8265 pipe_config
->shared_dpll
= NULL
;
8269 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
8270 if (!(tmp
& PIPECONF_ENABLE
))
8273 if (IS_G4X(dev_priv
) || IS_VALLEYVIEW(dev_priv
) ||
8274 IS_CHERRYVIEW(dev_priv
)) {
8275 switch (tmp
& PIPECONF_BPC_MASK
) {
8277 pipe_config
->pipe_bpp
= 18;
8280 pipe_config
->pipe_bpp
= 24;
8282 case PIPECONF_10BPC
:
8283 pipe_config
->pipe_bpp
= 30;
8290 if ((IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) &&
8291 (tmp
& PIPECONF_COLOR_RANGE_SELECT
))
8292 pipe_config
->limited_color_range
= true;
8294 pipe_config
->gamma_mode
= (tmp
& PIPECONF_GAMMA_MODE_MASK_I9XX
) >>
8295 PIPECONF_GAMMA_MODE_SHIFT
;
8297 if (IS_CHERRYVIEW(dev_priv
))
8298 pipe_config
->cgm_mode
= I915_READ(CGM_PIPE_MODE(crtc
->pipe
));
8300 i9xx_get_pipe_color_config(pipe_config
);
8302 if (INTEL_GEN(dev_priv
) < 4)
8303 pipe_config
->double_wide
= tmp
& PIPECONF_DOUBLE_WIDE
;
8305 intel_get_pipe_timings(crtc
, pipe_config
);
8306 intel_get_pipe_src_size(crtc
, pipe_config
);
8308 i9xx_get_pfit_config(crtc
, pipe_config
);
8310 if (INTEL_GEN(dev_priv
) >= 4) {
8311 /* No way to read it out on pipes B and C */
8312 if (IS_CHERRYVIEW(dev_priv
) && crtc
->pipe
!= PIPE_A
)
8313 tmp
= dev_priv
->chv_dpll_md
[crtc
->pipe
];
8315 tmp
= I915_READ(DPLL_MD(crtc
->pipe
));
8316 pipe_config
->pixel_multiplier
=
8317 ((tmp
& DPLL_MD_UDI_MULTIPLIER_MASK
)
8318 >> DPLL_MD_UDI_MULTIPLIER_SHIFT
) + 1;
8319 pipe_config
->dpll_hw_state
.dpll_md
= tmp
;
8320 } else if (IS_I945G(dev_priv
) || IS_I945GM(dev_priv
) ||
8321 IS_G33(dev_priv
) || IS_PINEVIEW(dev_priv
)) {
8322 tmp
= I915_READ(DPLL(crtc
->pipe
));
8323 pipe_config
->pixel_multiplier
=
8324 ((tmp
& SDVO_MULTIPLIER_MASK
)
8325 >> SDVO_MULTIPLIER_SHIFT_HIRES
) + 1;
8327 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8328 * port and will be fixed up in the encoder->get_config
8330 pipe_config
->pixel_multiplier
= 1;
8332 pipe_config
->dpll_hw_state
.dpll
= I915_READ(DPLL(crtc
->pipe
));
8333 if (!IS_VALLEYVIEW(dev_priv
) && !IS_CHERRYVIEW(dev_priv
)) {
8334 pipe_config
->dpll_hw_state
.fp0
= I915_READ(FP0(crtc
->pipe
));
8335 pipe_config
->dpll_hw_state
.fp1
= I915_READ(FP1(crtc
->pipe
));
8337 /* Mask out read-only status bits. */
8338 pipe_config
->dpll_hw_state
.dpll
&= ~(DPLL_LOCK_VLV
|
8339 DPLL_PORTC_READY_MASK
|
8340 DPLL_PORTB_READY_MASK
);
8343 if (IS_CHERRYVIEW(dev_priv
))
8344 chv_crtc_clock_get(crtc
, pipe_config
);
8345 else if (IS_VALLEYVIEW(dev_priv
))
8346 vlv_crtc_clock_get(crtc
, pipe_config
);
8348 i9xx_crtc_clock_get(crtc
, pipe_config
);
8351 * Normally the dotclock is filled in by the encoder .get_config()
8352 * but in case the pipe is enabled w/o any ports we need a sane
8355 pipe_config
->base
.adjusted_mode
.crtc_clock
=
8356 pipe_config
->port_clock
/ pipe_config
->pixel_multiplier
;
8361 intel_display_power_put(dev_priv
, power_domain
, wakeref
);
8366 static void ironlake_init_pch_refclk(struct drm_i915_private
*dev_priv
)
8368 struct intel_encoder
*encoder
;
8371 bool has_lvds
= false;
8372 bool has_cpu_edp
= false;
8373 bool has_panel
= false;
8374 bool has_ck505
= false;
8375 bool can_ssc
= false;
8376 bool using_ssc_source
= false;
8378 /* We need to take the global config into account */
8379 for_each_intel_encoder(&dev_priv
->drm
, encoder
) {
8380 switch (encoder
->type
) {
8381 case INTEL_OUTPUT_LVDS
:
8385 case INTEL_OUTPUT_EDP
:
8387 if (encoder
->port
== PORT_A
)
8395 if (HAS_PCH_IBX(dev_priv
)) {
8396 has_ck505
= dev_priv
->vbt
.display_clock_mode
;
8397 can_ssc
= has_ck505
;
8403 /* Check if any DPLLs are using the SSC source */
8404 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
8405 u32 temp
= I915_READ(PCH_DPLL(i
));
8407 if (!(temp
& DPLL_VCO_ENABLE
))
8410 if ((temp
& PLL_REF_INPUT_MASK
) ==
8411 PLLB_REF_INPUT_SPREADSPECTRUMIN
) {
8412 using_ssc_source
= true;
8417 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
8418 has_panel
, has_lvds
, has_ck505
, using_ssc_source
);
8420 /* Ironlake: try to setup display ref clock before DPLL
8421 * enabling. This is only under driver's control after
8422 * PCH B stepping, previous chipset stepping should be
8423 * ignoring this setting.
8425 val
= I915_READ(PCH_DREF_CONTROL
);
8427 /* As we must carefully and slowly disable/enable each source in turn,
8428 * compute the final state we want first and check if we need to
8429 * make any changes at all.
8432 final
&= ~DREF_NONSPREAD_SOURCE_MASK
;
8434 final
|= DREF_NONSPREAD_CK505_ENABLE
;
8436 final
|= DREF_NONSPREAD_SOURCE_ENABLE
;
8438 final
&= ~DREF_SSC_SOURCE_MASK
;
8439 final
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
8440 final
&= ~DREF_SSC1_ENABLE
;
8443 final
|= DREF_SSC_SOURCE_ENABLE
;
8445 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
8446 final
|= DREF_SSC1_ENABLE
;
8449 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
8450 final
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
8452 final
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
8454 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
8455 } else if (using_ssc_source
) {
8456 final
|= DREF_SSC_SOURCE_ENABLE
;
8457 final
|= DREF_SSC1_ENABLE
;
8463 /* Always enable nonspread source */
8464 val
&= ~DREF_NONSPREAD_SOURCE_MASK
;
8467 val
|= DREF_NONSPREAD_CK505_ENABLE
;
8469 val
|= DREF_NONSPREAD_SOURCE_ENABLE
;
8472 val
&= ~DREF_SSC_SOURCE_MASK
;
8473 val
|= DREF_SSC_SOURCE_ENABLE
;
8475 /* SSC must be turned on before enabling the CPU output */
8476 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
8477 DRM_DEBUG_KMS("Using SSC on panel\n");
8478 val
|= DREF_SSC1_ENABLE
;
8480 val
&= ~DREF_SSC1_ENABLE
;
8482 /* Get SSC going before enabling the outputs */
8483 I915_WRITE(PCH_DREF_CONTROL
, val
);
8484 POSTING_READ(PCH_DREF_CONTROL
);
8487 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
8489 /* Enable CPU source on CPU attached eDP */
8491 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
8492 DRM_DEBUG_KMS("Using SSC on eDP\n");
8493 val
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
8495 val
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
8497 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
8499 I915_WRITE(PCH_DREF_CONTROL
, val
);
8500 POSTING_READ(PCH_DREF_CONTROL
);
8503 DRM_DEBUG_KMS("Disabling CPU source output\n");
8505 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
8507 /* Turn off CPU output */
8508 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
8510 I915_WRITE(PCH_DREF_CONTROL
, val
);
8511 POSTING_READ(PCH_DREF_CONTROL
);
8514 if (!using_ssc_source
) {
8515 DRM_DEBUG_KMS("Disabling SSC source\n");
8517 /* Turn off the SSC source */
8518 val
&= ~DREF_SSC_SOURCE_MASK
;
8519 val
|= DREF_SSC_SOURCE_DISABLE
;
8522 val
&= ~DREF_SSC1_ENABLE
;
8524 I915_WRITE(PCH_DREF_CONTROL
, val
);
8525 POSTING_READ(PCH_DREF_CONTROL
);
8530 BUG_ON(val
!= final
);
8533 static void lpt_reset_fdi_mphy(struct drm_i915_private
*dev_priv
)
8537 tmp
= I915_READ(SOUTH_CHICKEN2
);
8538 tmp
|= FDI_MPHY_IOSFSB_RESET_CTL
;
8539 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
8541 if (wait_for_us(I915_READ(SOUTH_CHICKEN2
) &
8542 FDI_MPHY_IOSFSB_RESET_STATUS
, 100))
8543 DRM_ERROR("FDI mPHY reset assert timeout\n");
8545 tmp
= I915_READ(SOUTH_CHICKEN2
);
8546 tmp
&= ~FDI_MPHY_IOSFSB_RESET_CTL
;
8547 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
8549 if (wait_for_us((I915_READ(SOUTH_CHICKEN2
) &
8550 FDI_MPHY_IOSFSB_RESET_STATUS
) == 0, 100))
8551 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8554 /* WaMPhyProgramming:hsw */
8555 static void lpt_program_fdi_mphy(struct drm_i915_private
*dev_priv
)
8559 tmp
= intel_sbi_read(dev_priv
, 0x8008, SBI_MPHY
);
8560 tmp
&= ~(0xFF << 24);
8561 tmp
|= (0x12 << 24);
8562 intel_sbi_write(dev_priv
, 0x8008, tmp
, SBI_MPHY
);
8564 tmp
= intel_sbi_read(dev_priv
, 0x2008, SBI_MPHY
);
8566 intel_sbi_write(dev_priv
, 0x2008, tmp
, SBI_MPHY
);
8568 tmp
= intel_sbi_read(dev_priv
, 0x2108, SBI_MPHY
);
8570 intel_sbi_write(dev_priv
, 0x2108, tmp
, SBI_MPHY
);
8572 tmp
= intel_sbi_read(dev_priv
, 0x206C, SBI_MPHY
);
8573 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
8574 intel_sbi_write(dev_priv
, 0x206C, tmp
, SBI_MPHY
);
8576 tmp
= intel_sbi_read(dev_priv
, 0x216C, SBI_MPHY
);
8577 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
8578 intel_sbi_write(dev_priv
, 0x216C, tmp
, SBI_MPHY
);
8580 tmp
= intel_sbi_read(dev_priv
, 0x2080, SBI_MPHY
);
8583 intel_sbi_write(dev_priv
, 0x2080, tmp
, SBI_MPHY
);
8585 tmp
= intel_sbi_read(dev_priv
, 0x2180, SBI_MPHY
);
8588 intel_sbi_write(dev_priv
, 0x2180, tmp
, SBI_MPHY
);
8590 tmp
= intel_sbi_read(dev_priv
, 0x208C, SBI_MPHY
);
8593 intel_sbi_write(dev_priv
, 0x208C, tmp
, SBI_MPHY
);
8595 tmp
= intel_sbi_read(dev_priv
, 0x218C, SBI_MPHY
);
8598 intel_sbi_write(dev_priv
, 0x218C, tmp
, SBI_MPHY
);
8600 tmp
= intel_sbi_read(dev_priv
, 0x2098, SBI_MPHY
);
8601 tmp
&= ~(0xFF << 16);
8602 tmp
|= (0x1C << 16);
8603 intel_sbi_write(dev_priv
, 0x2098, tmp
, SBI_MPHY
);
8605 tmp
= intel_sbi_read(dev_priv
, 0x2198, SBI_MPHY
);
8606 tmp
&= ~(0xFF << 16);
8607 tmp
|= (0x1C << 16);
8608 intel_sbi_write(dev_priv
, 0x2198, tmp
, SBI_MPHY
);
8610 tmp
= intel_sbi_read(dev_priv
, 0x20C4, SBI_MPHY
);
8612 intel_sbi_write(dev_priv
, 0x20C4, tmp
, SBI_MPHY
);
8614 tmp
= intel_sbi_read(dev_priv
, 0x21C4, SBI_MPHY
);
8616 intel_sbi_write(dev_priv
, 0x21C4, tmp
, SBI_MPHY
);
8618 tmp
= intel_sbi_read(dev_priv
, 0x20EC, SBI_MPHY
);
8619 tmp
&= ~(0xF << 28);
8621 intel_sbi_write(dev_priv
, 0x20EC, tmp
, SBI_MPHY
);
8623 tmp
= intel_sbi_read(dev_priv
, 0x21EC, SBI_MPHY
);
8624 tmp
&= ~(0xF << 28);
8626 intel_sbi_write(dev_priv
, 0x21EC, tmp
, SBI_MPHY
);
8629 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8630 * Programming" based on the parameters passed:
8631 * - Sequence to enable CLKOUT_DP
8632 * - Sequence to enable CLKOUT_DP without spread
8633 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8635 static void lpt_enable_clkout_dp(struct drm_i915_private
*dev_priv
,
8636 bool with_spread
, bool with_fdi
)
8640 if (WARN(with_fdi
&& !with_spread
, "FDI requires downspread\n"))
8642 if (WARN(HAS_PCH_LPT_LP(dev_priv
) &&
8643 with_fdi
, "LP PCH doesn't have FDI\n"))
8646 mutex_lock(&dev_priv
->sb_lock
);
8648 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
8649 tmp
&= ~SBI_SSCCTL_DISABLE
;
8650 tmp
|= SBI_SSCCTL_PATHALT
;
8651 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
8656 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
8657 tmp
&= ~SBI_SSCCTL_PATHALT
;
8658 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
8661 lpt_reset_fdi_mphy(dev_priv
);
8662 lpt_program_fdi_mphy(dev_priv
);
8666 reg
= HAS_PCH_LPT_LP(dev_priv
) ? SBI_GEN0
: SBI_DBUFF0
;
8667 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
8668 tmp
|= SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
8669 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
8671 mutex_unlock(&dev_priv
->sb_lock
);
8674 /* Sequence to disable CLKOUT_DP */
8675 static void lpt_disable_clkout_dp(struct drm_i915_private
*dev_priv
)
8679 mutex_lock(&dev_priv
->sb_lock
);
8681 reg
= HAS_PCH_LPT_LP(dev_priv
) ? SBI_GEN0
: SBI_DBUFF0
;
8682 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
8683 tmp
&= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
8684 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
8686 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
8687 if (!(tmp
& SBI_SSCCTL_DISABLE
)) {
8688 if (!(tmp
& SBI_SSCCTL_PATHALT
)) {
8689 tmp
|= SBI_SSCCTL_PATHALT
;
8690 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
8693 tmp
|= SBI_SSCCTL_DISABLE
;
8694 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
8697 mutex_unlock(&dev_priv
->sb_lock
);
8700 #define BEND_IDX(steps) ((50 + (steps)) / 5)
8702 static const u16 sscdivintphase
[] = {
8703 [BEND_IDX( 50)] = 0x3B23,
8704 [BEND_IDX( 45)] = 0x3B23,
8705 [BEND_IDX( 40)] = 0x3C23,
8706 [BEND_IDX( 35)] = 0x3C23,
8707 [BEND_IDX( 30)] = 0x3D23,
8708 [BEND_IDX( 25)] = 0x3D23,
8709 [BEND_IDX( 20)] = 0x3E23,
8710 [BEND_IDX( 15)] = 0x3E23,
8711 [BEND_IDX( 10)] = 0x3F23,
8712 [BEND_IDX( 5)] = 0x3F23,
8713 [BEND_IDX( 0)] = 0x0025,
8714 [BEND_IDX( -5)] = 0x0025,
8715 [BEND_IDX(-10)] = 0x0125,
8716 [BEND_IDX(-15)] = 0x0125,
8717 [BEND_IDX(-20)] = 0x0225,
8718 [BEND_IDX(-25)] = 0x0225,
8719 [BEND_IDX(-30)] = 0x0325,
8720 [BEND_IDX(-35)] = 0x0325,
8721 [BEND_IDX(-40)] = 0x0425,
8722 [BEND_IDX(-45)] = 0x0425,
8723 [BEND_IDX(-50)] = 0x0525,
8728 * steps -50 to 50 inclusive, in steps of 5
8729 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
8730 * change in clock period = -(steps / 10) * 5.787 ps
8732 static void lpt_bend_clkout_dp(struct drm_i915_private
*dev_priv
, int steps
)
8735 int idx
= BEND_IDX(steps
);
8737 if (WARN_ON(steps
% 5 != 0))
8740 if (WARN_ON(idx
>= ARRAY_SIZE(sscdivintphase
)))
8743 mutex_lock(&dev_priv
->sb_lock
);
8745 if (steps
% 10 != 0)
8749 intel_sbi_write(dev_priv
, SBI_SSCDITHPHASE
, tmp
, SBI_ICLK
);
8751 tmp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE
, SBI_ICLK
);
8753 tmp
|= sscdivintphase
[idx
];
8754 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE
, tmp
, SBI_ICLK
);
8756 mutex_unlock(&dev_priv
->sb_lock
);
8761 static void lpt_init_pch_refclk(struct drm_i915_private
*dev_priv
)
8763 struct intel_encoder
*encoder
;
8764 bool has_vga
= false;
8766 for_each_intel_encoder(&dev_priv
->drm
, encoder
) {
8767 switch (encoder
->type
) {
8768 case INTEL_OUTPUT_ANALOG
:
8777 lpt_bend_clkout_dp(dev_priv
, 0);
8778 lpt_enable_clkout_dp(dev_priv
, true, true);
8780 lpt_disable_clkout_dp(dev_priv
);
8785 * Initialize reference clocks when the driver loads
8787 void intel_init_pch_refclk(struct drm_i915_private
*dev_priv
)
8789 if (HAS_PCH_IBX(dev_priv
) || HAS_PCH_CPT(dev_priv
))
8790 ironlake_init_pch_refclk(dev_priv
);
8791 else if (HAS_PCH_LPT(dev_priv
))
8792 lpt_init_pch_refclk(dev_priv
);
8795 static void ironlake_set_pipeconf(const struct intel_crtc_state
*crtc_state
)
8797 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
8798 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
8799 enum pipe pipe
= crtc
->pipe
;
8804 switch (crtc_state
->pipe_bpp
) {
8806 val
|= PIPECONF_6BPC
;
8809 val
|= PIPECONF_8BPC
;
8812 val
|= PIPECONF_10BPC
;
8815 val
|= PIPECONF_12BPC
;
8818 /* Case prevented by intel_choose_pipe_bpp_dither. */
8822 if (crtc_state
->dither
)
8823 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
8825 if (crtc_state
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
8826 val
|= PIPECONF_INTERLACED_ILK
;
8828 val
|= PIPECONF_PROGRESSIVE
;
8830 if (crtc_state
->limited_color_range
)
8831 val
|= PIPECONF_COLOR_RANGE_SELECT
;
8833 val
|= PIPECONF_GAMMA_MODE(crtc_state
->gamma_mode
);
8835 I915_WRITE(PIPECONF(pipe
), val
);
8836 POSTING_READ(PIPECONF(pipe
));
8839 static void haswell_set_pipeconf(const struct intel_crtc_state
*crtc_state
)
8841 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
8842 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
8843 enum transcoder cpu_transcoder
= crtc_state
->cpu_transcoder
;
8846 if (IS_HASWELL(dev_priv
) && crtc_state
->dither
)
8847 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
8849 if (crtc_state
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
8850 val
|= PIPECONF_INTERLACED_ILK
;
8852 val
|= PIPECONF_PROGRESSIVE
;
8854 I915_WRITE(PIPECONF(cpu_transcoder
), val
);
8855 POSTING_READ(PIPECONF(cpu_transcoder
));
8858 static void haswell_set_pipemisc(const struct intel_crtc_state
*crtc_state
)
8860 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
8861 struct drm_i915_private
*dev_priv
= to_i915(intel_crtc
->base
.dev
);
8863 if (IS_BROADWELL(dev_priv
) || INTEL_GEN(dev_priv
) >= 9) {
8866 switch (crtc_state
->pipe_bpp
) {
8868 val
|= PIPEMISC_DITHER_6_BPC
;
8871 val
|= PIPEMISC_DITHER_8_BPC
;
8874 val
|= PIPEMISC_DITHER_10_BPC
;
8877 val
|= PIPEMISC_DITHER_12_BPC
;
8880 /* Case prevented by pipe_config_set_bpp. */
8884 if (crtc_state
->dither
)
8885 val
|= PIPEMISC_DITHER_ENABLE
| PIPEMISC_DITHER_TYPE_SP
;
8887 if (crtc_state
->output_format
== INTEL_OUTPUT_FORMAT_YCBCR420
||
8888 crtc_state
->output_format
== INTEL_OUTPUT_FORMAT_YCBCR444
)
8889 val
|= PIPEMISC_OUTPUT_COLORSPACE_YUV
;
8891 if (crtc_state
->output_format
== INTEL_OUTPUT_FORMAT_YCBCR420
)
8892 val
|= PIPEMISC_YUV420_ENABLE
|
8893 PIPEMISC_YUV420_MODE_FULL_BLEND
;
8895 I915_WRITE(PIPEMISC(intel_crtc
->pipe
), val
);
8899 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
)
8902 * Account for spread spectrum to avoid
8903 * oversubscribing the link. Max center spread
8904 * is 2.5%; use 5% for safety's sake.
8906 u32 bps
= target_clock
* bpp
* 21 / 20;
8907 return DIV_ROUND_UP(bps
, link_bw
* 8);
8910 static bool ironlake_needs_fb_cb_tune(struct dpll
*dpll
, int factor
)
8912 return i9xx_dpll_compute_m(dpll
) < factor
* dpll
->n
;
8915 static void ironlake_compute_dpll(struct intel_crtc
*crtc
,
8916 struct intel_crtc_state
*crtc_state
,
8917 struct dpll
*reduced_clock
)
8919 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
8923 /* Enable autotuning of the PLL clock (if permissible) */
8925 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
8926 if ((intel_panel_use_ssc(dev_priv
) &&
8927 dev_priv
->vbt
.lvds_ssc_freq
== 100000) ||
8928 (HAS_PCH_IBX(dev_priv
) &&
8929 intel_is_dual_link_lvds(dev_priv
)))
8931 } else if (crtc_state
->sdvo_tv_clock
) {
8935 fp
= i9xx_dpll_compute_fp(&crtc_state
->dpll
);
8937 if (ironlake_needs_fb_cb_tune(&crtc_state
->dpll
, factor
))
8940 if (reduced_clock
) {
8941 fp2
= i9xx_dpll_compute_fp(reduced_clock
);
8943 if (reduced_clock
->m
< factor
* reduced_clock
->n
)
8951 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
))
8952 dpll
|= DPLLB_MODE_LVDS
;
8954 dpll
|= DPLLB_MODE_DAC_SERIAL
;
8956 dpll
|= (crtc_state
->pixel_multiplier
- 1)
8957 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
8959 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_SDVO
) ||
8960 intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_HDMI
))
8961 dpll
|= DPLL_SDVO_HIGH_SPEED
;
8963 if (intel_crtc_has_dp_encoder(crtc_state
))
8964 dpll
|= DPLL_SDVO_HIGH_SPEED
;
8967 * The high speed IO clock is only really required for
8968 * SDVO/HDMI/DP, but we also enable it for CRT to make it
8969 * possible to share the DPLL between CRT and HDMI. Enabling
8970 * the clock needlessly does no real harm, except use up a
8971 * bit of power potentially.
8973 * We'll limit this to IVB with 3 pipes, since it has only two
8974 * DPLLs and so DPLL sharing is the only way to get three pipes
8975 * driving PCH ports at the same time. On SNB we could do this,
8976 * and potentially avoid enabling the second DPLL, but it's not
8977 * clear if it''s a win or loss power wise. No point in doing
8978 * this on ILK at all since it has a fixed DPLL<->pipe mapping.
8980 if (INTEL_INFO(dev_priv
)->num_pipes
== 3 &&
8981 intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_ANALOG
))
8982 dpll
|= DPLL_SDVO_HIGH_SPEED
;
8984 /* compute bitmask from p1 value */
8985 dpll
|= (1 << (crtc_state
->dpll
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
8987 dpll
|= (1 << (crtc_state
->dpll
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
8989 switch (crtc_state
->dpll
.p2
) {
8991 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
8994 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
8997 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
9000 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
9004 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
9005 intel_panel_use_ssc(dev_priv
))
9006 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
9008 dpll
|= PLL_REF_INPUT_DREFCLK
;
9010 dpll
|= DPLL_VCO_ENABLE
;
9012 crtc_state
->dpll_hw_state
.dpll
= dpll
;
9013 crtc_state
->dpll_hw_state
.fp0
= fp
;
9014 crtc_state
->dpll_hw_state
.fp1
= fp2
;
9017 static int ironlake_crtc_compute_clock(struct intel_crtc
*crtc
,
9018 struct intel_crtc_state
*crtc_state
)
9020 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
9021 const struct intel_limit
*limit
;
9022 int refclk
= 120000;
9024 memset(&crtc_state
->dpll_hw_state
, 0,
9025 sizeof(crtc_state
->dpll_hw_state
));
9027 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
9028 if (!crtc_state
->has_pch_encoder
)
9031 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
9032 if (intel_panel_use_ssc(dev_priv
)) {
9033 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
9034 dev_priv
->vbt
.lvds_ssc_freq
);
9035 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
9038 if (intel_is_dual_link_lvds(dev_priv
)) {
9039 if (refclk
== 100000)
9040 limit
= &intel_limits_ironlake_dual_lvds_100m
;
9042 limit
= &intel_limits_ironlake_dual_lvds
;
9044 if (refclk
== 100000)
9045 limit
= &intel_limits_ironlake_single_lvds_100m
;
9047 limit
= &intel_limits_ironlake_single_lvds
;
9050 limit
= &intel_limits_ironlake_dac
;
9053 if (!crtc_state
->clock_set
&&
9054 !g4x_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
9055 refclk
, NULL
, &crtc_state
->dpll
)) {
9056 DRM_ERROR("Couldn't find PLL settings for mode!\n");
9060 ironlake_compute_dpll(crtc
, crtc_state
, NULL
);
9062 if (!intel_get_shared_dpll(crtc_state
, NULL
)) {
9063 DRM_DEBUG_KMS("failed to find PLL for pipe %c\n",
9064 pipe_name(crtc
->pipe
));
9071 static void intel_pch_transcoder_get_m_n(struct intel_crtc
*crtc
,
9072 struct intel_link_m_n
*m_n
)
9074 struct drm_device
*dev
= crtc
->base
.dev
;
9075 struct drm_i915_private
*dev_priv
= to_i915(dev
);
9076 enum pipe pipe
= crtc
->pipe
;
9078 m_n
->link_m
= I915_READ(PCH_TRANS_LINK_M1(pipe
));
9079 m_n
->link_n
= I915_READ(PCH_TRANS_LINK_N1(pipe
));
9080 m_n
->gmch_m
= I915_READ(PCH_TRANS_DATA_M1(pipe
))
9082 m_n
->gmch_n
= I915_READ(PCH_TRANS_DATA_N1(pipe
));
9083 m_n
->tu
= ((I915_READ(PCH_TRANS_DATA_M1(pipe
))
9084 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
9087 static void intel_cpu_transcoder_get_m_n(struct intel_crtc
*crtc
,
9088 enum transcoder transcoder
,
9089 struct intel_link_m_n
*m_n
,
9090 struct intel_link_m_n
*m2_n2
)
9092 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
9093 enum pipe pipe
= crtc
->pipe
;
9095 if (INTEL_GEN(dev_priv
) >= 5) {
9096 m_n
->link_m
= I915_READ(PIPE_LINK_M1(transcoder
));
9097 m_n
->link_n
= I915_READ(PIPE_LINK_N1(transcoder
));
9098 m_n
->gmch_m
= I915_READ(PIPE_DATA_M1(transcoder
))
9100 m_n
->gmch_n
= I915_READ(PIPE_DATA_N1(transcoder
));
9101 m_n
->tu
= ((I915_READ(PIPE_DATA_M1(transcoder
))
9102 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
9104 if (m2_n2
&& transcoder_has_m2_n2(dev_priv
, transcoder
)) {
9105 m2_n2
->link_m
= I915_READ(PIPE_LINK_M2(transcoder
));
9106 m2_n2
->link_n
= I915_READ(PIPE_LINK_N2(transcoder
));
9107 m2_n2
->gmch_m
= I915_READ(PIPE_DATA_M2(transcoder
))
9109 m2_n2
->gmch_n
= I915_READ(PIPE_DATA_N2(transcoder
));
9110 m2_n2
->tu
= ((I915_READ(PIPE_DATA_M2(transcoder
))
9111 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
9114 m_n
->link_m
= I915_READ(PIPE_LINK_M_G4X(pipe
));
9115 m_n
->link_n
= I915_READ(PIPE_LINK_N_G4X(pipe
));
9116 m_n
->gmch_m
= I915_READ(PIPE_DATA_M_G4X(pipe
))
9118 m_n
->gmch_n
= I915_READ(PIPE_DATA_N_G4X(pipe
));
9119 m_n
->tu
= ((I915_READ(PIPE_DATA_M_G4X(pipe
))
9120 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
9124 void intel_dp_get_m_n(struct intel_crtc
*crtc
,
9125 struct intel_crtc_state
*pipe_config
)
9127 if (pipe_config
->has_pch_encoder
)
9128 intel_pch_transcoder_get_m_n(crtc
, &pipe_config
->dp_m_n
);
9130 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
9131 &pipe_config
->dp_m_n
,
9132 &pipe_config
->dp_m2_n2
);
9135 static void ironlake_get_fdi_m_n_config(struct intel_crtc
*crtc
,
9136 struct intel_crtc_state
*pipe_config
)
9138 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
9139 &pipe_config
->fdi_m_n
, NULL
);
9142 static void skylake_get_pfit_config(struct intel_crtc
*crtc
,
9143 struct intel_crtc_state
*pipe_config
)
9145 struct drm_device
*dev
= crtc
->base
.dev
;
9146 struct drm_i915_private
*dev_priv
= to_i915(dev
);
9147 struct intel_crtc_scaler_state
*scaler_state
= &pipe_config
->scaler_state
;
9152 /* find scaler attached to this pipe */
9153 for (i
= 0; i
< crtc
->num_scalers
; i
++) {
9154 ps_ctrl
= I915_READ(SKL_PS_CTRL(crtc
->pipe
, i
));
9155 if (ps_ctrl
& PS_SCALER_EN
&& !(ps_ctrl
& PS_PLANE_SEL_MASK
)) {
9157 pipe_config
->pch_pfit
.enabled
= true;
9158 pipe_config
->pch_pfit
.pos
= I915_READ(SKL_PS_WIN_POS(crtc
->pipe
, i
));
9159 pipe_config
->pch_pfit
.size
= I915_READ(SKL_PS_WIN_SZ(crtc
->pipe
, i
));
9160 scaler_state
->scalers
[i
].in_use
= true;
9165 scaler_state
->scaler_id
= id
;
9167 scaler_state
->scaler_users
|= (1 << SKL_CRTC_INDEX
);
9169 scaler_state
->scaler_users
&= ~(1 << SKL_CRTC_INDEX
);
9174 skylake_get_initial_plane_config(struct intel_crtc
*crtc
,
9175 struct intel_initial_plane_config
*plane_config
)
9177 struct drm_device
*dev
= crtc
->base
.dev
;
9178 struct drm_i915_private
*dev_priv
= to_i915(dev
);
9179 struct intel_plane
*plane
= to_intel_plane(crtc
->base
.primary
);
9180 enum plane_id plane_id
= plane
->id
;
9182 u32 val
, base
, offset
, stride_mult
, tiling
, alpha
;
9183 int fourcc
, pixel_format
;
9184 unsigned int aligned_height
;
9185 struct drm_framebuffer
*fb
;
9186 struct intel_framebuffer
*intel_fb
;
9188 if (!plane
->get_hw_state(plane
, &pipe
))
9191 WARN_ON(pipe
!= crtc
->pipe
);
9193 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
9195 DRM_DEBUG_KMS("failed to alloc fb\n");
9199 fb
= &intel_fb
->base
;
9203 val
= I915_READ(PLANE_CTL(pipe
, plane_id
));
9205 if (INTEL_GEN(dev_priv
) >= 11)
9206 pixel_format
= val
& ICL_PLANE_CTL_FORMAT_MASK
;
9208 pixel_format
= val
& PLANE_CTL_FORMAT_MASK
;
9210 if (INTEL_GEN(dev_priv
) >= 10 || IS_GEMINILAKE(dev_priv
)) {
9211 alpha
= I915_READ(PLANE_COLOR_CTL(pipe
, plane_id
));
9212 alpha
&= PLANE_COLOR_ALPHA_MASK
;
9214 alpha
= val
& PLANE_CTL_ALPHA_MASK
;
9217 fourcc
= skl_format_to_fourcc(pixel_format
,
9218 val
& PLANE_CTL_ORDER_RGBX
, alpha
);
9219 fb
->format
= drm_format_info(fourcc
);
9221 tiling
= val
& PLANE_CTL_TILED_MASK
;
9223 case PLANE_CTL_TILED_LINEAR
:
9224 fb
->modifier
= DRM_FORMAT_MOD_LINEAR
;
9226 case PLANE_CTL_TILED_X
:
9227 plane_config
->tiling
= I915_TILING_X
;
9228 fb
->modifier
= I915_FORMAT_MOD_X_TILED
;
9230 case PLANE_CTL_TILED_Y
:
9231 plane_config
->tiling
= I915_TILING_Y
;
9232 if (val
& PLANE_CTL_RENDER_DECOMPRESSION_ENABLE
)
9233 fb
->modifier
= I915_FORMAT_MOD_Y_TILED_CCS
;
9235 fb
->modifier
= I915_FORMAT_MOD_Y_TILED
;
9237 case PLANE_CTL_TILED_YF
:
9238 if (val
& PLANE_CTL_RENDER_DECOMPRESSION_ENABLE
)
9239 fb
->modifier
= I915_FORMAT_MOD_Yf_TILED_CCS
;
9241 fb
->modifier
= I915_FORMAT_MOD_Yf_TILED
;
9244 MISSING_CASE(tiling
);
9249 * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
9250 * while i915 HW rotation is clockwise, thats why this swapping.
9252 switch (val
& PLANE_CTL_ROTATE_MASK
) {
9253 case PLANE_CTL_ROTATE_0
:
9254 plane_config
->rotation
= DRM_MODE_ROTATE_0
;
9256 case PLANE_CTL_ROTATE_90
:
9257 plane_config
->rotation
= DRM_MODE_ROTATE_270
;
9259 case PLANE_CTL_ROTATE_180
:
9260 plane_config
->rotation
= DRM_MODE_ROTATE_180
;
9262 case PLANE_CTL_ROTATE_270
:
9263 plane_config
->rotation
= DRM_MODE_ROTATE_90
;
9267 if (INTEL_GEN(dev_priv
) >= 10 &&
9268 val
& PLANE_CTL_FLIP_HORIZONTAL
)
9269 plane_config
->rotation
|= DRM_MODE_REFLECT_X
;
9271 base
= I915_READ(PLANE_SURF(pipe
, plane_id
)) & 0xfffff000;
9272 plane_config
->base
= base
;
9274 offset
= I915_READ(PLANE_OFFSET(pipe
, plane_id
));
9276 val
= I915_READ(PLANE_SIZE(pipe
, plane_id
));
9277 fb
->height
= ((val
>> 16) & 0xfff) + 1;
9278 fb
->width
= ((val
>> 0) & 0x1fff) + 1;
9280 val
= I915_READ(PLANE_STRIDE(pipe
, plane_id
));
9281 stride_mult
= skl_plane_stride_mult(fb
, 0, DRM_MODE_ROTATE_0
);
9282 fb
->pitches
[0] = (val
& 0x3ff) * stride_mult
;
9284 aligned_height
= intel_fb_align_height(fb
, 0, fb
->height
);
9286 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
9288 DRM_DEBUG_KMS("%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9289 crtc
->base
.name
, plane
->base
.name
, fb
->width
, fb
->height
,
9290 fb
->format
->cpp
[0] * 8, base
, fb
->pitches
[0],
9291 plane_config
->size
);
9293 plane_config
->fb
= intel_fb
;
9300 static void ironlake_get_pfit_config(struct intel_crtc
*crtc
,
9301 struct intel_crtc_state
*pipe_config
)
9303 struct drm_device
*dev
= crtc
->base
.dev
;
9304 struct drm_i915_private
*dev_priv
= to_i915(dev
);
9307 tmp
= I915_READ(PF_CTL(crtc
->pipe
));
9309 if (tmp
& PF_ENABLE
) {
9310 pipe_config
->pch_pfit
.enabled
= true;
9311 pipe_config
->pch_pfit
.pos
= I915_READ(PF_WIN_POS(crtc
->pipe
));
9312 pipe_config
->pch_pfit
.size
= I915_READ(PF_WIN_SZ(crtc
->pipe
));
9314 /* We currently do not free assignements of panel fitters on
9315 * ivb/hsw (since we don't use the higher upscaling modes which
9316 * differentiates them) so just WARN about this case for now. */
9317 if (IS_GEN(dev_priv
, 7)) {
9318 WARN_ON((tmp
& PF_PIPE_SEL_MASK_IVB
) !=
9319 PF_PIPE_SEL_IVB(crtc
->pipe
));
9324 static bool ironlake_get_pipe_config(struct intel_crtc
*crtc
,
9325 struct intel_crtc_state
*pipe_config
)
9327 struct drm_device
*dev
= crtc
->base
.dev
;
9328 struct drm_i915_private
*dev_priv
= to_i915(dev
);
9329 enum intel_display_power_domain power_domain
;
9330 intel_wakeref_t wakeref
;
9334 power_domain
= POWER_DOMAIN_PIPE(crtc
->pipe
);
9335 wakeref
= intel_display_power_get_if_enabled(dev_priv
, power_domain
);
9339 pipe_config
->output_format
= INTEL_OUTPUT_FORMAT_RGB
;
9340 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
9341 pipe_config
->shared_dpll
= NULL
;
9344 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
9345 if (!(tmp
& PIPECONF_ENABLE
))
9348 switch (tmp
& PIPECONF_BPC_MASK
) {
9350 pipe_config
->pipe_bpp
= 18;
9353 pipe_config
->pipe_bpp
= 24;
9355 case PIPECONF_10BPC
:
9356 pipe_config
->pipe_bpp
= 30;
9358 case PIPECONF_12BPC
:
9359 pipe_config
->pipe_bpp
= 36;
9365 if (tmp
& PIPECONF_COLOR_RANGE_SELECT
)
9366 pipe_config
->limited_color_range
= true;
9368 pipe_config
->gamma_mode
= (tmp
& PIPECONF_GAMMA_MODE_MASK_ILK
) >>
9369 PIPECONF_GAMMA_MODE_SHIFT
;
9371 pipe_config
->csc_mode
= I915_READ(PIPE_CSC_MODE(crtc
->pipe
));
9373 i9xx_get_pipe_color_config(pipe_config
);
9375 if (I915_READ(PCH_TRANSCONF(crtc
->pipe
)) & TRANS_ENABLE
) {
9376 struct intel_shared_dpll
*pll
;
9377 enum intel_dpll_id pll_id
;
9379 pipe_config
->has_pch_encoder
= true;
9381 tmp
= I915_READ(FDI_RX_CTL(crtc
->pipe
));
9382 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
9383 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
9385 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
9387 if (HAS_PCH_IBX(dev_priv
)) {
9389 * The pipe->pch transcoder and pch transcoder->pll
9392 pll_id
= (enum intel_dpll_id
) crtc
->pipe
;
9394 tmp
= I915_READ(PCH_DPLL_SEL
);
9395 if (tmp
& TRANS_DPLLB_SEL(crtc
->pipe
))
9396 pll_id
= DPLL_ID_PCH_PLL_B
;
9398 pll_id
= DPLL_ID_PCH_PLL_A
;
9401 pipe_config
->shared_dpll
=
9402 intel_get_shared_dpll_by_id(dev_priv
, pll_id
);
9403 pll
= pipe_config
->shared_dpll
;
9405 WARN_ON(!pll
->info
->funcs
->get_hw_state(dev_priv
, pll
,
9406 &pipe_config
->dpll_hw_state
));
9408 tmp
= pipe_config
->dpll_hw_state
.dpll
;
9409 pipe_config
->pixel_multiplier
=
9410 ((tmp
& PLL_REF_SDVO_HDMI_MULTIPLIER_MASK
)
9411 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
) + 1;
9413 ironlake_pch_clock_get(crtc
, pipe_config
);
9415 pipe_config
->pixel_multiplier
= 1;
9418 intel_get_pipe_timings(crtc
, pipe_config
);
9419 intel_get_pipe_src_size(crtc
, pipe_config
);
9421 ironlake_get_pfit_config(crtc
, pipe_config
);
9426 intel_display_power_put(dev_priv
, power_domain
, wakeref
);
9431 static void assert_can_disable_lcpll(struct drm_i915_private
*dev_priv
)
9433 struct drm_device
*dev
= &dev_priv
->drm
;
9434 struct intel_crtc
*crtc
;
9436 for_each_intel_crtc(dev
, crtc
)
9437 I915_STATE_WARN(crtc
->active
, "CRTC for pipe %c enabled\n",
9438 pipe_name(crtc
->pipe
));
9440 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_CTL2
),
9441 "Display power well on\n");
9442 I915_STATE_WARN(I915_READ(SPLL_CTL
) & SPLL_PLL_ENABLE
, "SPLL enabled\n");
9443 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE
, "WRPLL1 enabled\n");
9444 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE
, "WRPLL2 enabled\n");
9445 I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON
, "Panel power on\n");
9446 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2
) & BLM_PWM_ENABLE
,
9447 "CPU PWM1 enabled\n");
9448 if (IS_HASWELL(dev_priv
))
9449 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL
) & BLM_PWM_ENABLE
,
9450 "CPU PWM2 enabled\n");
9451 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1
) & BLM_PCH_PWM_ENABLE
,
9452 "PCH PWM1 enabled\n");
9453 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL
) & UTIL_PIN_ENABLE
,
9454 "Utility pin enabled\n");
9455 I915_STATE_WARN(I915_READ(PCH_GTC_CTL
) & PCH_GTC_ENABLE
, "PCH GTC enabled\n");
9458 * In theory we can still leave IRQs enabled, as long as only the HPD
9459 * interrupts remain enabled. We used to check for that, but since it's
9460 * gen-specific and since we only disable LCPLL after we fully disable
9461 * the interrupts, the check below should be enough.
9463 I915_STATE_WARN(intel_irqs_enabled(dev_priv
), "IRQs enabled\n");
9466 static u32
hsw_read_dcomp(struct drm_i915_private
*dev_priv
)
9468 if (IS_HASWELL(dev_priv
))
9469 return I915_READ(D_COMP_HSW
);
9471 return I915_READ(D_COMP_BDW
);
9474 static void hsw_write_dcomp(struct drm_i915_private
*dev_priv
, u32 val
)
9476 if (IS_HASWELL(dev_priv
)) {
9477 mutex_lock(&dev_priv
->pcu_lock
);
9478 if (sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_D_COMP
,
9480 DRM_DEBUG_KMS("Failed to write to D_COMP\n");
9481 mutex_unlock(&dev_priv
->pcu_lock
);
9483 I915_WRITE(D_COMP_BDW
, val
);
9484 POSTING_READ(D_COMP_BDW
);
9489 * This function implements pieces of two sequences from BSpec:
9490 * - Sequence for display software to disable LCPLL
9491 * - Sequence for display software to allow package C8+
9492 * The steps implemented here are just the steps that actually touch the LCPLL
9493 * register. Callers should take care of disabling all the display engine
9494 * functions, doing the mode unset, fixing interrupts, etc.
9496 static void hsw_disable_lcpll(struct drm_i915_private
*dev_priv
,
9497 bool switch_to_fclk
, bool allow_power_down
)
9501 assert_can_disable_lcpll(dev_priv
);
9503 val
= I915_READ(LCPLL_CTL
);
9505 if (switch_to_fclk
) {
9506 val
|= LCPLL_CD_SOURCE_FCLK
;
9507 I915_WRITE(LCPLL_CTL
, val
);
9509 if (wait_for_us(I915_READ(LCPLL_CTL
) &
9510 LCPLL_CD_SOURCE_FCLK_DONE
, 1))
9511 DRM_ERROR("Switching to FCLK failed\n");
9513 val
= I915_READ(LCPLL_CTL
);
9516 val
|= LCPLL_PLL_DISABLE
;
9517 I915_WRITE(LCPLL_CTL
, val
);
9518 POSTING_READ(LCPLL_CTL
);
9520 if (intel_wait_for_register(&dev_priv
->uncore
,
9521 LCPLL_CTL
, LCPLL_PLL_LOCK
, 0, 1))
9522 DRM_ERROR("LCPLL still locked\n");
9524 val
= hsw_read_dcomp(dev_priv
);
9525 val
|= D_COMP_COMP_DISABLE
;
9526 hsw_write_dcomp(dev_priv
, val
);
9529 if (wait_for((hsw_read_dcomp(dev_priv
) & D_COMP_RCOMP_IN_PROGRESS
) == 0,
9531 DRM_ERROR("D_COMP RCOMP still in progress\n");
9533 if (allow_power_down
) {
9534 val
= I915_READ(LCPLL_CTL
);
9535 val
|= LCPLL_POWER_DOWN_ALLOW
;
9536 I915_WRITE(LCPLL_CTL
, val
);
9537 POSTING_READ(LCPLL_CTL
);
9542 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9545 static void hsw_restore_lcpll(struct drm_i915_private
*dev_priv
)
9549 val
= I915_READ(LCPLL_CTL
);
9551 if ((val
& (LCPLL_PLL_LOCK
| LCPLL_PLL_DISABLE
| LCPLL_CD_SOURCE_FCLK
|
9552 LCPLL_POWER_DOWN_ALLOW
)) == LCPLL_PLL_LOCK
)
9556 * Make sure we're not on PC8 state before disabling PC8, otherwise
9557 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9559 intel_uncore_forcewake_get(&dev_priv
->uncore
, FORCEWAKE_ALL
);
9561 if (val
& LCPLL_POWER_DOWN_ALLOW
) {
9562 val
&= ~LCPLL_POWER_DOWN_ALLOW
;
9563 I915_WRITE(LCPLL_CTL
, val
);
9564 POSTING_READ(LCPLL_CTL
);
9567 val
= hsw_read_dcomp(dev_priv
);
9568 val
|= D_COMP_COMP_FORCE
;
9569 val
&= ~D_COMP_COMP_DISABLE
;
9570 hsw_write_dcomp(dev_priv
, val
);
9572 val
= I915_READ(LCPLL_CTL
);
9573 val
&= ~LCPLL_PLL_DISABLE
;
9574 I915_WRITE(LCPLL_CTL
, val
);
9576 if (intel_wait_for_register(&dev_priv
->uncore
,
9577 LCPLL_CTL
, LCPLL_PLL_LOCK
, LCPLL_PLL_LOCK
,
9579 DRM_ERROR("LCPLL not locked yet\n");
9581 if (val
& LCPLL_CD_SOURCE_FCLK
) {
9582 val
= I915_READ(LCPLL_CTL
);
9583 val
&= ~LCPLL_CD_SOURCE_FCLK
;
9584 I915_WRITE(LCPLL_CTL
, val
);
9586 if (wait_for_us((I915_READ(LCPLL_CTL
) &
9587 LCPLL_CD_SOURCE_FCLK_DONE
) == 0, 1))
9588 DRM_ERROR("Switching back to LCPLL failed\n");
9591 intel_uncore_forcewake_put(&dev_priv
->uncore
, FORCEWAKE_ALL
);
9593 intel_update_cdclk(dev_priv
);
9594 intel_dump_cdclk_state(&dev_priv
->cdclk
.hw
, "Current CDCLK");
9598 * Package states C8 and deeper are really deep PC states that can only be
9599 * reached when all the devices on the system allow it, so even if the graphics
9600 * device allows PC8+, it doesn't mean the system will actually get to these
9601 * states. Our driver only allows PC8+ when going into runtime PM.
9603 * The requirements for PC8+ are that all the outputs are disabled, the power
9604 * well is disabled and most interrupts are disabled, and these are also
9605 * requirements for runtime PM. When these conditions are met, we manually do
9606 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9607 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9610 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9611 * the state of some registers, so when we come back from PC8+ we need to
9612 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9613 * need to take care of the registers kept by RC6. Notice that this happens even
9614 * if we don't put the device in PCI D3 state (which is what currently happens
9615 * because of the runtime PM support).
9617 * For more, read "Display Sequences for Package C8" on the hardware
9620 void hsw_enable_pc8(struct drm_i915_private
*dev_priv
)
9624 DRM_DEBUG_KMS("Enabling package C8+\n");
9626 if (HAS_PCH_LPT_LP(dev_priv
)) {
9627 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
9628 val
&= ~PCH_LP_PARTITION_LEVEL_DISABLE
;
9629 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
9632 lpt_disable_clkout_dp(dev_priv
);
9633 hsw_disable_lcpll(dev_priv
, true, true);
9636 void hsw_disable_pc8(struct drm_i915_private
*dev_priv
)
9640 DRM_DEBUG_KMS("Disabling package C8+\n");
9642 hsw_restore_lcpll(dev_priv
);
9643 lpt_init_pch_refclk(dev_priv
);
9645 if (HAS_PCH_LPT_LP(dev_priv
)) {
9646 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
9647 val
|= PCH_LP_PARTITION_LEVEL_DISABLE
;
9648 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
9652 static int haswell_crtc_compute_clock(struct intel_crtc
*crtc
,
9653 struct intel_crtc_state
*crtc_state
)
9655 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
9656 struct intel_atomic_state
*state
=
9657 to_intel_atomic_state(crtc_state
->base
.state
);
9659 if (!intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_DSI
) ||
9660 INTEL_GEN(dev_priv
) >= 11) {
9661 struct intel_encoder
*encoder
=
9662 intel_get_crtc_new_encoder(state
, crtc_state
);
9664 if (!intel_get_shared_dpll(crtc_state
, encoder
)) {
9665 DRM_DEBUG_KMS("failed to find PLL for pipe %c\n",
9666 pipe_name(crtc
->pipe
));
9674 static void cannonlake_get_ddi_pll(struct drm_i915_private
*dev_priv
,
9676 struct intel_crtc_state
*pipe_config
)
9678 enum intel_dpll_id id
;
9681 temp
= I915_READ(DPCLKA_CFGCR0
) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port
);
9682 id
= temp
>> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port
);
9684 if (WARN_ON(id
< SKL_DPLL0
|| id
> SKL_DPLL2
))
9687 pipe_config
->shared_dpll
= intel_get_shared_dpll_by_id(dev_priv
, id
);
9690 static void icelake_get_ddi_pll(struct drm_i915_private
*dev_priv
,
9692 struct intel_crtc_state
*pipe_config
)
9694 enum intel_dpll_id id
;
9697 /* TODO: TBT pll not implemented. */
9698 if (intel_port_is_combophy(dev_priv
, port
)) {
9699 temp
= I915_READ(DPCLKA_CFGCR0_ICL
) &
9700 DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port
);
9701 id
= temp
>> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port
);
9702 } else if (intel_port_is_tc(dev_priv
, port
)) {
9703 id
= icl_tc_port_to_pll_id(intel_port_to_tc(dev_priv
, port
));
9705 WARN(1, "Invalid port %x\n", port
);
9709 pipe_config
->shared_dpll
= intel_get_shared_dpll_by_id(dev_priv
, id
);
9712 static void bxt_get_ddi_pll(struct drm_i915_private
*dev_priv
,
9714 struct intel_crtc_state
*pipe_config
)
9716 enum intel_dpll_id id
;
9720 id
= DPLL_ID_SKL_DPLL0
;
9723 id
= DPLL_ID_SKL_DPLL1
;
9726 id
= DPLL_ID_SKL_DPLL2
;
9729 DRM_ERROR("Incorrect port type\n");
9733 pipe_config
->shared_dpll
= intel_get_shared_dpll_by_id(dev_priv
, id
);
9736 static void skylake_get_ddi_pll(struct drm_i915_private
*dev_priv
,
9738 struct intel_crtc_state
*pipe_config
)
9740 enum intel_dpll_id id
;
9743 temp
= I915_READ(DPLL_CTRL2
) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port
);
9744 id
= temp
>> (port
* 3 + 1);
9746 if (WARN_ON(id
< SKL_DPLL0
|| id
> SKL_DPLL3
))
9749 pipe_config
->shared_dpll
= intel_get_shared_dpll_by_id(dev_priv
, id
);
9752 static void haswell_get_ddi_pll(struct drm_i915_private
*dev_priv
,
9754 struct intel_crtc_state
*pipe_config
)
9756 enum intel_dpll_id id
;
9757 u32 ddi_pll_sel
= I915_READ(PORT_CLK_SEL(port
));
9759 switch (ddi_pll_sel
) {
9760 case PORT_CLK_SEL_WRPLL1
:
9761 id
= DPLL_ID_WRPLL1
;
9763 case PORT_CLK_SEL_WRPLL2
:
9764 id
= DPLL_ID_WRPLL2
;
9766 case PORT_CLK_SEL_SPLL
:
9769 case PORT_CLK_SEL_LCPLL_810
:
9770 id
= DPLL_ID_LCPLL_810
;
9772 case PORT_CLK_SEL_LCPLL_1350
:
9773 id
= DPLL_ID_LCPLL_1350
;
9775 case PORT_CLK_SEL_LCPLL_2700
:
9776 id
= DPLL_ID_LCPLL_2700
;
9779 MISSING_CASE(ddi_pll_sel
);
9781 case PORT_CLK_SEL_NONE
:
9785 pipe_config
->shared_dpll
= intel_get_shared_dpll_by_id(dev_priv
, id
);
9788 static bool hsw_get_transcoder_state(struct intel_crtc
*crtc
,
9789 struct intel_crtc_state
*pipe_config
,
9790 u64
*power_domain_mask
,
9791 intel_wakeref_t
*wakerefs
)
9793 struct drm_device
*dev
= crtc
->base
.dev
;
9794 struct drm_i915_private
*dev_priv
= to_i915(dev
);
9795 enum intel_display_power_domain power_domain
;
9796 unsigned long panel_transcoder_mask
= 0;
9797 unsigned long enabled_panel_transcoders
= 0;
9798 enum transcoder panel_transcoder
;
9802 if (INTEL_GEN(dev_priv
) >= 11)
9803 panel_transcoder_mask
|=
9804 BIT(TRANSCODER_DSI_0
) | BIT(TRANSCODER_DSI_1
);
9806 if (HAS_TRANSCODER_EDP(dev_priv
))
9807 panel_transcoder_mask
|= BIT(TRANSCODER_EDP
);
9810 * The pipe->transcoder mapping is fixed with the exception of the eDP
9811 * and DSI transcoders handled below.
9813 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
9816 * XXX: Do intel_display_power_get_if_enabled before reading this (for
9817 * consistency and less surprising code; it's in always on power).
9819 for_each_set_bit(panel_transcoder
,
9820 &panel_transcoder_mask
,
9821 ARRAY_SIZE(INTEL_INFO(dev_priv
)->trans_offsets
)) {
9822 enum pipe trans_pipe
;
9824 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(panel_transcoder
));
9825 if (!(tmp
& TRANS_DDI_FUNC_ENABLE
))
9829 * Log all enabled ones, only use the first one.
9831 * FIXME: This won't work for two separate DSI displays.
9833 enabled_panel_transcoders
|= BIT(panel_transcoder
);
9834 if (enabled_panel_transcoders
!= BIT(panel_transcoder
))
9837 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
9839 WARN(1, "unknown pipe linked to transcoder %s\n",
9840 transcoder_name(panel_transcoder
));
9842 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
9843 case TRANS_DDI_EDP_INPUT_A_ON
:
9844 trans_pipe
= PIPE_A
;
9846 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
9847 trans_pipe
= PIPE_B
;
9849 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
9850 trans_pipe
= PIPE_C
;
9854 if (trans_pipe
== crtc
->pipe
)
9855 pipe_config
->cpu_transcoder
= panel_transcoder
;
9859 * Valid combos: none, eDP, DSI0, DSI1, DSI0+DSI1
9861 WARN_ON((enabled_panel_transcoders
& BIT(TRANSCODER_EDP
)) &&
9862 enabled_panel_transcoders
!= BIT(TRANSCODER_EDP
));
9864 power_domain
= POWER_DOMAIN_TRANSCODER(pipe_config
->cpu_transcoder
);
9865 WARN_ON(*power_domain_mask
& BIT_ULL(power_domain
));
9867 wf
= intel_display_power_get_if_enabled(dev_priv
, power_domain
);
9871 wakerefs
[power_domain
] = wf
;
9872 *power_domain_mask
|= BIT_ULL(power_domain
);
9874 tmp
= I915_READ(PIPECONF(pipe_config
->cpu_transcoder
));
9876 return tmp
& PIPECONF_ENABLE
;
9879 static bool bxt_get_dsi_transcoder_state(struct intel_crtc
*crtc
,
9880 struct intel_crtc_state
*pipe_config
,
9881 u64
*power_domain_mask
,
9882 intel_wakeref_t
*wakerefs
)
9884 struct drm_device
*dev
= crtc
->base
.dev
;
9885 struct drm_i915_private
*dev_priv
= to_i915(dev
);
9886 enum intel_display_power_domain power_domain
;
9887 enum transcoder cpu_transcoder
;
9892 for_each_port_masked(port
, BIT(PORT_A
) | BIT(PORT_C
)) {
9894 cpu_transcoder
= TRANSCODER_DSI_A
;
9896 cpu_transcoder
= TRANSCODER_DSI_C
;
9898 power_domain
= POWER_DOMAIN_TRANSCODER(cpu_transcoder
);
9899 WARN_ON(*power_domain_mask
& BIT_ULL(power_domain
));
9901 wf
= intel_display_power_get_if_enabled(dev_priv
, power_domain
);
9905 wakerefs
[power_domain
] = wf
;
9906 *power_domain_mask
|= BIT_ULL(power_domain
);
9909 * The PLL needs to be enabled with a valid divider
9910 * configuration, otherwise accessing DSI registers will hang
9911 * the machine. See BSpec North Display Engine
9912 * registers/MIPI[BXT]. We can break out here early, since we
9913 * need the same DSI PLL to be enabled for both DSI ports.
9915 if (!bxt_dsi_pll_is_enabled(dev_priv
))
9918 /* XXX: this works for video mode only */
9919 tmp
= I915_READ(BXT_MIPI_PORT_CTRL(port
));
9920 if (!(tmp
& DPI_ENABLE
))
9923 tmp
= I915_READ(MIPI_CTRL(port
));
9924 if ((tmp
& BXT_PIPE_SELECT_MASK
) != BXT_PIPE_SELECT(crtc
->pipe
))
9927 pipe_config
->cpu_transcoder
= cpu_transcoder
;
9931 return transcoder_is_dsi(pipe_config
->cpu_transcoder
);
9934 static void haswell_get_ddi_port_state(struct intel_crtc
*crtc
,
9935 struct intel_crtc_state
*pipe_config
)
9937 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
9938 struct intel_shared_dpll
*pll
;
9942 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(pipe_config
->cpu_transcoder
));
9944 port
= (tmp
& TRANS_DDI_PORT_MASK
) >> TRANS_DDI_PORT_SHIFT
;
9946 if (INTEL_GEN(dev_priv
) >= 11)
9947 icelake_get_ddi_pll(dev_priv
, port
, pipe_config
);
9948 else if (IS_CANNONLAKE(dev_priv
))
9949 cannonlake_get_ddi_pll(dev_priv
, port
, pipe_config
);
9950 else if (IS_GEN9_BC(dev_priv
))
9951 skylake_get_ddi_pll(dev_priv
, port
, pipe_config
);
9952 else if (IS_GEN9_LP(dev_priv
))
9953 bxt_get_ddi_pll(dev_priv
, port
, pipe_config
);
9955 haswell_get_ddi_pll(dev_priv
, port
, pipe_config
);
9957 pll
= pipe_config
->shared_dpll
;
9959 WARN_ON(!pll
->info
->funcs
->get_hw_state(dev_priv
, pll
,
9960 &pipe_config
->dpll_hw_state
));
9964 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9965 * DDI E. So just check whether this pipe is wired to DDI E and whether
9966 * the PCH transcoder is on.
9968 if (INTEL_GEN(dev_priv
) < 9 &&
9969 (port
== PORT_E
) && I915_READ(LPT_TRANSCONF
) & TRANS_ENABLE
) {
9970 pipe_config
->has_pch_encoder
= true;
9972 tmp
= I915_READ(FDI_RX_CTL(PIPE_A
));
9973 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
9974 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
9976 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
9980 static bool haswell_get_pipe_config(struct intel_crtc
*crtc
,
9981 struct intel_crtc_state
*pipe_config
)
9983 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
9984 intel_wakeref_t wakerefs
[POWER_DOMAIN_NUM
], wf
;
9985 enum intel_display_power_domain power_domain
;
9986 u64 power_domain_mask
;
9989 intel_crtc_init_scalers(crtc
, pipe_config
);
9991 power_domain
= POWER_DOMAIN_PIPE(crtc
->pipe
);
9992 wf
= intel_display_power_get_if_enabled(dev_priv
, power_domain
);
9996 wakerefs
[power_domain
] = wf
;
9997 power_domain_mask
= BIT_ULL(power_domain
);
9999 pipe_config
->shared_dpll
= NULL
;
10001 active
= hsw_get_transcoder_state(crtc
, pipe_config
,
10002 &power_domain_mask
, wakerefs
);
10004 if (IS_GEN9_LP(dev_priv
) &&
10005 bxt_get_dsi_transcoder_state(crtc
, pipe_config
,
10006 &power_domain_mask
, wakerefs
)) {
10014 if (!transcoder_is_dsi(pipe_config
->cpu_transcoder
) ||
10015 INTEL_GEN(dev_priv
) >= 11) {
10016 haswell_get_ddi_port_state(crtc
, pipe_config
);
10017 intel_get_pipe_timings(crtc
, pipe_config
);
10020 intel_get_pipe_src_size(crtc
, pipe_config
);
10021 intel_get_crtc_ycbcr_config(crtc
, pipe_config
);
10023 pipe_config
->gamma_mode
= I915_READ(GAMMA_MODE(crtc
->pipe
));
10025 pipe_config
->csc_mode
= I915_READ(PIPE_CSC_MODE(crtc
->pipe
));
10027 if (INTEL_GEN(dev_priv
) >= 9) {
10028 u32 tmp
= I915_READ(SKL_BOTTOM_COLOR(crtc
->pipe
));
10030 if (tmp
& SKL_BOTTOM_COLOR_GAMMA_ENABLE
)
10031 pipe_config
->gamma_enable
= true;
10033 if (tmp
& SKL_BOTTOM_COLOR_CSC_ENABLE
)
10034 pipe_config
->csc_enable
= true;
10036 i9xx_get_pipe_color_config(pipe_config
);
10039 power_domain
= POWER_DOMAIN_PIPE_PANEL_FITTER(crtc
->pipe
);
10040 WARN_ON(power_domain_mask
& BIT_ULL(power_domain
));
10042 wf
= intel_display_power_get_if_enabled(dev_priv
, power_domain
);
10044 wakerefs
[power_domain
] = wf
;
10045 power_domain_mask
|= BIT_ULL(power_domain
);
10047 if (INTEL_GEN(dev_priv
) >= 9)
10048 skylake_get_pfit_config(crtc
, pipe_config
);
10050 ironlake_get_pfit_config(crtc
, pipe_config
);
10053 if (hsw_crtc_supports_ips(crtc
)) {
10054 if (IS_HASWELL(dev_priv
))
10055 pipe_config
->ips_enabled
= I915_READ(IPS_CTL
) & IPS_ENABLE
;
10058 * We cannot readout IPS state on broadwell, set to
10059 * true so we can set it to a defined state on first
10062 pipe_config
->ips_enabled
= true;
10066 if (pipe_config
->cpu_transcoder
!= TRANSCODER_EDP
&&
10067 !transcoder_is_dsi(pipe_config
->cpu_transcoder
)) {
10068 pipe_config
->pixel_multiplier
=
10069 I915_READ(PIPE_MULT(pipe_config
->cpu_transcoder
)) + 1;
10071 pipe_config
->pixel_multiplier
= 1;
10075 for_each_power_domain(power_domain
, power_domain_mask
)
10076 intel_display_power_put(dev_priv
,
10077 power_domain
, wakerefs
[power_domain
]);
10082 static u32
intel_cursor_base(const struct intel_plane_state
*plane_state
)
10084 struct drm_i915_private
*dev_priv
=
10085 to_i915(plane_state
->base
.plane
->dev
);
10086 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
10087 const struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
10090 if (INTEL_INFO(dev_priv
)->display
.cursor_needs_physical
)
10091 base
= obj
->phys_handle
->busaddr
;
10093 base
= intel_plane_ggtt_offset(plane_state
);
10095 base
+= plane_state
->color_plane
[0].offset
;
10097 /* ILK+ do this automagically */
10098 if (HAS_GMCH(dev_priv
) &&
10099 plane_state
->base
.rotation
& DRM_MODE_ROTATE_180
)
10100 base
+= (plane_state
->base
.crtc_h
*
10101 plane_state
->base
.crtc_w
- 1) * fb
->format
->cpp
[0];
10106 static u32
intel_cursor_position(const struct intel_plane_state
*plane_state
)
10108 int x
= plane_state
->base
.crtc_x
;
10109 int y
= plane_state
->base
.crtc_y
;
10113 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
10116 pos
|= x
<< CURSOR_X_SHIFT
;
10119 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
10122 pos
|= y
<< CURSOR_Y_SHIFT
;
10127 static bool intel_cursor_size_ok(const struct intel_plane_state
*plane_state
)
10129 const struct drm_mode_config
*config
=
10130 &plane_state
->base
.plane
->dev
->mode_config
;
10131 int width
= plane_state
->base
.crtc_w
;
10132 int height
= plane_state
->base
.crtc_h
;
10134 return width
> 0 && width
<= config
->cursor_width
&&
10135 height
> 0 && height
<= config
->cursor_height
;
10138 static int intel_cursor_check_surface(struct intel_plane_state
*plane_state
)
10140 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
10141 unsigned int rotation
= plane_state
->base
.rotation
;
10146 intel_fill_fb_ggtt_view(&plane_state
->view
, fb
, rotation
);
10147 plane_state
->color_plane
[0].stride
= intel_fb_pitch(fb
, 0, rotation
);
10149 ret
= intel_plane_check_stride(plane_state
);
10153 src_x
= plane_state
->base
.src_x
>> 16;
10154 src_y
= plane_state
->base
.src_y
>> 16;
10156 intel_add_fb_offsets(&src_x
, &src_y
, plane_state
, 0);
10157 offset
= intel_plane_compute_aligned_offset(&src_x
, &src_y
,
10160 if (src_x
!= 0 || src_y
!= 0) {
10161 DRM_DEBUG_KMS("Arbitrary cursor panning not supported\n");
10165 plane_state
->color_plane
[0].offset
= offset
;
10170 static int intel_check_cursor(struct intel_crtc_state
*crtc_state
,
10171 struct intel_plane_state
*plane_state
)
10173 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
10176 if (fb
&& fb
->modifier
!= DRM_FORMAT_MOD_LINEAR
) {
10177 DRM_DEBUG_KMS("cursor cannot be tiled\n");
10181 ret
= drm_atomic_helper_check_plane_state(&plane_state
->base
,
10183 DRM_PLANE_HELPER_NO_SCALING
,
10184 DRM_PLANE_HELPER_NO_SCALING
,
10189 if (!plane_state
->base
.visible
)
10192 ret
= intel_plane_check_src_coordinates(plane_state
);
10196 ret
= intel_cursor_check_surface(plane_state
);
10203 static unsigned int
10204 i845_cursor_max_stride(struct intel_plane
*plane
,
10205 u32 pixel_format
, u64 modifier
,
10206 unsigned int rotation
)
10211 static u32
i845_cursor_ctl_crtc(const struct intel_crtc_state
*crtc_state
)
10215 if (crtc_state
->gamma_enable
)
10216 cntl
|= CURSOR_GAMMA_ENABLE
;
10221 static u32
i845_cursor_ctl(const struct intel_crtc_state
*crtc_state
,
10222 const struct intel_plane_state
*plane_state
)
10224 return CURSOR_ENABLE
|
10225 CURSOR_FORMAT_ARGB
|
10226 CURSOR_STRIDE(plane_state
->color_plane
[0].stride
);
10229 static bool i845_cursor_size_ok(const struct intel_plane_state
*plane_state
)
10231 int width
= plane_state
->base
.crtc_w
;
10234 * 845g/865g are only limited by the width of their cursors,
10235 * the height is arbitrary up to the precision of the register.
10237 return intel_cursor_size_ok(plane_state
) && IS_ALIGNED(width
, 64);
10240 static int i845_check_cursor(struct intel_crtc_state
*crtc_state
,
10241 struct intel_plane_state
*plane_state
)
10243 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
10246 ret
= intel_check_cursor(crtc_state
, plane_state
);
10250 /* if we want to turn off the cursor ignore width and height */
10254 /* Check for which cursor types we support */
10255 if (!i845_cursor_size_ok(plane_state
)) {
10256 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
10257 plane_state
->base
.crtc_w
,
10258 plane_state
->base
.crtc_h
);
10262 WARN_ON(plane_state
->base
.visible
&&
10263 plane_state
->color_plane
[0].stride
!= fb
->pitches
[0]);
10265 switch (fb
->pitches
[0]) {
10272 DRM_DEBUG_KMS("Invalid cursor stride (%u)\n",
10277 plane_state
->ctl
= i845_cursor_ctl(crtc_state
, plane_state
);
10282 static void i845_update_cursor(struct intel_plane
*plane
,
10283 const struct intel_crtc_state
*crtc_state
,
10284 const struct intel_plane_state
*plane_state
)
10286 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
10287 u32 cntl
= 0, base
= 0, pos
= 0, size
= 0;
10288 unsigned long irqflags
;
10290 if (plane_state
&& plane_state
->base
.visible
) {
10291 unsigned int width
= plane_state
->base
.crtc_w
;
10292 unsigned int height
= plane_state
->base
.crtc_h
;
10294 cntl
= plane_state
->ctl
|
10295 i845_cursor_ctl_crtc(crtc_state
);
10297 size
= (height
<< 12) | width
;
10299 base
= intel_cursor_base(plane_state
);
10300 pos
= intel_cursor_position(plane_state
);
10303 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
10305 /* On these chipsets we can only modify the base/size/stride
10306 * whilst the cursor is disabled.
10308 if (plane
->cursor
.base
!= base
||
10309 plane
->cursor
.size
!= size
||
10310 plane
->cursor
.cntl
!= cntl
) {
10311 I915_WRITE_FW(CURCNTR(PIPE_A
), 0);
10312 I915_WRITE_FW(CURBASE(PIPE_A
), base
);
10313 I915_WRITE_FW(CURSIZE
, size
);
10314 I915_WRITE_FW(CURPOS(PIPE_A
), pos
);
10315 I915_WRITE_FW(CURCNTR(PIPE_A
), cntl
);
10317 plane
->cursor
.base
= base
;
10318 plane
->cursor
.size
= size
;
10319 plane
->cursor
.cntl
= cntl
;
10321 I915_WRITE_FW(CURPOS(PIPE_A
), pos
);
10324 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
10327 static void i845_disable_cursor(struct intel_plane
*plane
,
10328 const struct intel_crtc_state
*crtc_state
)
10330 i845_update_cursor(plane
, crtc_state
, NULL
);
10333 static bool i845_cursor_get_hw_state(struct intel_plane
*plane
,
10336 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
10337 enum intel_display_power_domain power_domain
;
10338 intel_wakeref_t wakeref
;
10341 power_domain
= POWER_DOMAIN_PIPE(PIPE_A
);
10342 wakeref
= intel_display_power_get_if_enabled(dev_priv
, power_domain
);
10346 ret
= I915_READ(CURCNTR(PIPE_A
)) & CURSOR_ENABLE
;
10350 intel_display_power_put(dev_priv
, power_domain
, wakeref
);
10355 static unsigned int
10356 i9xx_cursor_max_stride(struct intel_plane
*plane
,
10357 u32 pixel_format
, u64 modifier
,
10358 unsigned int rotation
)
10360 return plane
->base
.dev
->mode_config
.cursor_width
* 4;
10363 static u32
i9xx_cursor_ctl_crtc(const struct intel_crtc_state
*crtc_state
)
10365 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
10366 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
10369 if (INTEL_GEN(dev_priv
) >= 11)
10372 if (crtc_state
->gamma_enable
)
10373 cntl
= MCURSOR_GAMMA_ENABLE
;
10375 if (crtc_state
->csc_enable
)
10376 cntl
|= MCURSOR_PIPE_CSC_ENABLE
;
10378 if (INTEL_GEN(dev_priv
) < 5 && !IS_G4X(dev_priv
))
10379 cntl
|= MCURSOR_PIPE_SELECT(crtc
->pipe
);
10384 static u32
i9xx_cursor_ctl(const struct intel_crtc_state
*crtc_state
,
10385 const struct intel_plane_state
*plane_state
)
10387 struct drm_i915_private
*dev_priv
=
10388 to_i915(plane_state
->base
.plane
->dev
);
10391 if (IS_GEN(dev_priv
, 6) || IS_IVYBRIDGE(dev_priv
))
10392 cntl
|= MCURSOR_TRICKLE_FEED_DISABLE
;
10394 switch (plane_state
->base
.crtc_w
) {
10396 cntl
|= MCURSOR_MODE_64_ARGB_AX
;
10399 cntl
|= MCURSOR_MODE_128_ARGB_AX
;
10402 cntl
|= MCURSOR_MODE_256_ARGB_AX
;
10405 MISSING_CASE(plane_state
->base
.crtc_w
);
10409 if (plane_state
->base
.rotation
& DRM_MODE_ROTATE_180
)
10410 cntl
|= MCURSOR_ROTATE_180
;
10415 static bool i9xx_cursor_size_ok(const struct intel_plane_state
*plane_state
)
10417 struct drm_i915_private
*dev_priv
=
10418 to_i915(plane_state
->base
.plane
->dev
);
10419 int width
= plane_state
->base
.crtc_w
;
10420 int height
= plane_state
->base
.crtc_h
;
10422 if (!intel_cursor_size_ok(plane_state
))
10425 /* Cursor width is limited to a few power-of-two sizes */
10436 * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor
10437 * height from 8 lines up to the cursor width, when the
10438 * cursor is not rotated. Everything else requires square
10441 if (HAS_CUR_FBC(dev_priv
) &&
10442 plane_state
->base
.rotation
& DRM_MODE_ROTATE_0
) {
10443 if (height
< 8 || height
> width
)
10446 if (height
!= width
)
10453 static int i9xx_check_cursor(struct intel_crtc_state
*crtc_state
,
10454 struct intel_plane_state
*plane_state
)
10456 struct intel_plane
*plane
= to_intel_plane(plane_state
->base
.plane
);
10457 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
10458 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
10459 enum pipe pipe
= plane
->pipe
;
10462 ret
= intel_check_cursor(crtc_state
, plane_state
);
10466 /* if we want to turn off the cursor ignore width and height */
10470 /* Check for which cursor types we support */
10471 if (!i9xx_cursor_size_ok(plane_state
)) {
10472 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
10473 plane_state
->base
.crtc_w
,
10474 plane_state
->base
.crtc_h
);
10478 WARN_ON(plane_state
->base
.visible
&&
10479 plane_state
->color_plane
[0].stride
!= fb
->pitches
[0]);
10481 if (fb
->pitches
[0] != plane_state
->base
.crtc_w
* fb
->format
->cpp
[0]) {
10482 DRM_DEBUG_KMS("Invalid cursor stride (%u) (cursor width %d)\n",
10483 fb
->pitches
[0], plane_state
->base
.crtc_w
);
10488 * There's something wrong with the cursor on CHV pipe C.
10489 * If it straddles the left edge of the screen then
10490 * moving it away from the edge or disabling it often
10491 * results in a pipe underrun, and often that can lead to
10492 * dead pipe (constant underrun reported, and it scans
10493 * out just a solid color). To recover from that, the
10494 * display power well must be turned off and on again.
10495 * Refuse the put the cursor into that compromised position.
10497 if (IS_CHERRYVIEW(dev_priv
) && pipe
== PIPE_C
&&
10498 plane_state
->base
.visible
&& plane_state
->base
.crtc_x
< 0) {
10499 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
10503 plane_state
->ctl
= i9xx_cursor_ctl(crtc_state
, plane_state
);
10508 static void i9xx_update_cursor(struct intel_plane
*plane
,
10509 const struct intel_crtc_state
*crtc_state
,
10510 const struct intel_plane_state
*plane_state
)
10512 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
10513 enum pipe pipe
= plane
->pipe
;
10514 u32 cntl
= 0, base
= 0, pos
= 0, fbc_ctl
= 0;
10515 unsigned long irqflags
;
10517 if (plane_state
&& plane_state
->base
.visible
) {
10518 cntl
= plane_state
->ctl
|
10519 i9xx_cursor_ctl_crtc(crtc_state
);
10521 if (plane_state
->base
.crtc_h
!= plane_state
->base
.crtc_w
)
10522 fbc_ctl
= CUR_FBC_CTL_EN
| (plane_state
->base
.crtc_h
- 1);
10524 base
= intel_cursor_base(plane_state
);
10525 pos
= intel_cursor_position(plane_state
);
10528 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
10531 * On some platforms writing CURCNTR first will also
10532 * cause CURPOS to be armed by the CURBASE write.
10533 * Without the CURCNTR write the CURPOS write would
10534 * arm itself. Thus we always update CURCNTR before
10537 * On other platforms CURPOS always requires the
10538 * CURBASE write to arm the update. Additonally
10539 * a write to any of the cursor register will cancel
10540 * an already armed cursor update. Thus leaving out
10541 * the CURBASE write after CURPOS could lead to a
10542 * cursor that doesn't appear to move, or even change
10543 * shape. Thus we always write CURBASE.
10545 * The other registers are armed by by the CURBASE write
10546 * except when the plane is getting enabled at which time
10547 * the CURCNTR write arms the update.
10550 if (INTEL_GEN(dev_priv
) >= 9)
10551 skl_write_cursor_wm(plane
, crtc_state
);
10553 if (plane
->cursor
.base
!= base
||
10554 plane
->cursor
.size
!= fbc_ctl
||
10555 plane
->cursor
.cntl
!= cntl
) {
10556 if (HAS_CUR_FBC(dev_priv
))
10557 I915_WRITE_FW(CUR_FBC_CTL(pipe
), fbc_ctl
);
10558 I915_WRITE_FW(CURCNTR(pipe
), cntl
);
10559 I915_WRITE_FW(CURPOS(pipe
), pos
);
10560 I915_WRITE_FW(CURBASE(pipe
), base
);
10562 plane
->cursor
.base
= base
;
10563 plane
->cursor
.size
= fbc_ctl
;
10564 plane
->cursor
.cntl
= cntl
;
10566 I915_WRITE_FW(CURPOS(pipe
), pos
);
10567 I915_WRITE_FW(CURBASE(pipe
), base
);
10570 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
10573 static void i9xx_disable_cursor(struct intel_plane
*plane
,
10574 const struct intel_crtc_state
*crtc_state
)
10576 i9xx_update_cursor(plane
, crtc_state
, NULL
);
10579 static bool i9xx_cursor_get_hw_state(struct intel_plane
*plane
,
10582 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
10583 enum intel_display_power_domain power_domain
;
10584 intel_wakeref_t wakeref
;
10589 * Not 100% correct for planes that can move between pipes,
10590 * but that's only the case for gen2-3 which don't have any
10591 * display power wells.
10593 power_domain
= POWER_DOMAIN_PIPE(plane
->pipe
);
10594 wakeref
= intel_display_power_get_if_enabled(dev_priv
, power_domain
);
10598 val
= I915_READ(CURCNTR(plane
->pipe
));
10600 ret
= val
& MCURSOR_MODE
;
10602 if (INTEL_GEN(dev_priv
) >= 5 || IS_G4X(dev_priv
))
10603 *pipe
= plane
->pipe
;
10605 *pipe
= (val
& MCURSOR_PIPE_SELECT_MASK
) >>
10606 MCURSOR_PIPE_SELECT_SHIFT
;
10608 intel_display_power_put(dev_priv
, power_domain
, wakeref
);
10613 /* VESA 640x480x72Hz mode to set on the pipe */
10614 static const struct drm_display_mode load_detect_mode
= {
10615 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
10616 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
10619 struct drm_framebuffer
*
10620 intel_framebuffer_create(struct drm_i915_gem_object
*obj
,
10621 struct drm_mode_fb_cmd2
*mode_cmd
)
10623 struct intel_framebuffer
*intel_fb
;
10626 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
10628 return ERR_PTR(-ENOMEM
);
10630 ret
= intel_framebuffer_init(intel_fb
, obj
, mode_cmd
);
10634 return &intel_fb
->base
;
10638 return ERR_PTR(ret
);
10641 static int intel_modeset_disable_planes(struct drm_atomic_state
*state
,
10642 struct drm_crtc
*crtc
)
10644 struct drm_plane
*plane
;
10645 struct drm_plane_state
*plane_state
;
10648 ret
= drm_atomic_add_affected_planes(state
, crtc
);
10652 for_each_new_plane_in_state(state
, plane
, plane_state
, i
) {
10653 if (plane_state
->crtc
!= crtc
)
10656 ret
= drm_atomic_set_crtc_for_plane(plane_state
, NULL
);
10660 drm_atomic_set_fb_for_plane(plane_state
, NULL
);
10666 int intel_get_load_detect_pipe(struct drm_connector
*connector
,
10667 const struct drm_display_mode
*mode
,
10668 struct intel_load_detect_pipe
*old
,
10669 struct drm_modeset_acquire_ctx
*ctx
)
10671 struct intel_crtc
*intel_crtc
;
10672 struct intel_encoder
*intel_encoder
=
10673 intel_attached_encoder(connector
);
10674 struct drm_crtc
*possible_crtc
;
10675 struct drm_encoder
*encoder
= &intel_encoder
->base
;
10676 struct drm_crtc
*crtc
= NULL
;
10677 struct drm_device
*dev
= encoder
->dev
;
10678 struct drm_i915_private
*dev_priv
= to_i915(dev
);
10679 struct drm_mode_config
*config
= &dev
->mode_config
;
10680 struct drm_atomic_state
*state
= NULL
, *restore_state
= NULL
;
10681 struct drm_connector_state
*connector_state
;
10682 struct intel_crtc_state
*crtc_state
;
10685 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10686 connector
->base
.id
, connector
->name
,
10687 encoder
->base
.id
, encoder
->name
);
10689 old
->restore_state
= NULL
;
10691 WARN_ON(!drm_modeset_is_locked(&config
->connection_mutex
));
10694 * Algorithm gets a little messy:
10696 * - if the connector already has an assigned crtc, use it (but make
10697 * sure it's on first)
10699 * - try to find the first unused crtc that can drive this connector,
10700 * and use that if we find one
10703 /* See if we already have a CRTC for this connector */
10704 if (connector
->state
->crtc
) {
10705 crtc
= connector
->state
->crtc
;
10707 ret
= drm_modeset_lock(&crtc
->mutex
, ctx
);
10711 /* Make sure the crtc and connector are running */
10715 /* Find an unused one (if possible) */
10716 for_each_crtc(dev
, possible_crtc
) {
10718 if (!(encoder
->possible_crtcs
& (1 << i
)))
10721 ret
= drm_modeset_lock(&possible_crtc
->mutex
, ctx
);
10725 if (possible_crtc
->state
->enable
) {
10726 drm_modeset_unlock(&possible_crtc
->mutex
);
10730 crtc
= possible_crtc
;
10735 * If we didn't find an unused CRTC, don't use any.
10738 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10744 intel_crtc
= to_intel_crtc(crtc
);
10746 state
= drm_atomic_state_alloc(dev
);
10747 restore_state
= drm_atomic_state_alloc(dev
);
10748 if (!state
|| !restore_state
) {
10753 state
->acquire_ctx
= ctx
;
10754 restore_state
->acquire_ctx
= ctx
;
10756 connector_state
= drm_atomic_get_connector_state(state
, connector
);
10757 if (IS_ERR(connector_state
)) {
10758 ret
= PTR_ERR(connector_state
);
10762 ret
= drm_atomic_set_crtc_for_connector(connector_state
, crtc
);
10766 crtc_state
= intel_atomic_get_crtc_state(state
, intel_crtc
);
10767 if (IS_ERR(crtc_state
)) {
10768 ret
= PTR_ERR(crtc_state
);
10772 crtc_state
->base
.active
= crtc_state
->base
.enable
= true;
10775 mode
= &load_detect_mode
;
10777 ret
= drm_atomic_set_mode_for_crtc(&crtc_state
->base
, mode
);
10781 ret
= intel_modeset_disable_planes(state
, crtc
);
10785 ret
= PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state
, connector
));
10787 ret
= PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state
, crtc
));
10789 ret
= drm_atomic_add_affected_planes(restore_state
, crtc
);
10791 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret
);
10795 ret
= drm_atomic_commit(state
);
10797 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10801 old
->restore_state
= restore_state
;
10802 drm_atomic_state_put(state
);
10804 /* let the connector get through one full cycle before testing */
10805 intel_wait_for_vblank(dev_priv
, intel_crtc
->pipe
);
10810 drm_atomic_state_put(state
);
10813 if (restore_state
) {
10814 drm_atomic_state_put(restore_state
);
10815 restore_state
= NULL
;
10818 if (ret
== -EDEADLK
)
10824 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
10825 struct intel_load_detect_pipe
*old
,
10826 struct drm_modeset_acquire_ctx
*ctx
)
10828 struct intel_encoder
*intel_encoder
=
10829 intel_attached_encoder(connector
);
10830 struct drm_encoder
*encoder
= &intel_encoder
->base
;
10831 struct drm_atomic_state
*state
= old
->restore_state
;
10834 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10835 connector
->base
.id
, connector
->name
,
10836 encoder
->base
.id
, encoder
->name
);
10841 ret
= drm_atomic_helper_commit_duplicated_state(state
, ctx
);
10843 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret
);
10844 drm_atomic_state_put(state
);
10847 static int i9xx_pll_refclk(struct drm_device
*dev
,
10848 const struct intel_crtc_state
*pipe_config
)
10850 struct drm_i915_private
*dev_priv
= to_i915(dev
);
10851 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
10853 if ((dpll
& PLL_REF_INPUT_MASK
) == PLLB_REF_INPUT_SPREADSPECTRUMIN
)
10854 return dev_priv
->vbt
.lvds_ssc_freq
;
10855 else if (HAS_PCH_SPLIT(dev_priv
))
10857 else if (!IS_GEN(dev_priv
, 2))
10863 /* Returns the clock of the currently programmed mode of the given pipe. */
10864 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
10865 struct intel_crtc_state
*pipe_config
)
10867 struct drm_device
*dev
= crtc
->base
.dev
;
10868 struct drm_i915_private
*dev_priv
= to_i915(dev
);
10869 int pipe
= pipe_config
->cpu_transcoder
;
10870 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
10874 int refclk
= i9xx_pll_refclk(dev
, pipe_config
);
10876 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
10877 fp
= pipe_config
->dpll_hw_state
.fp0
;
10879 fp
= pipe_config
->dpll_hw_state
.fp1
;
10881 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
10882 if (IS_PINEVIEW(dev_priv
)) {
10883 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
10884 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
10886 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
10887 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
10890 if (!IS_GEN(dev_priv
, 2)) {
10891 if (IS_PINEVIEW(dev_priv
))
10892 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
10893 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
10895 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
10896 DPLL_FPA01_P1_POST_DIV_SHIFT
);
10898 switch (dpll
& DPLL_MODE_MASK
) {
10899 case DPLLB_MODE_DAC_SERIAL
:
10900 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
10903 case DPLLB_MODE_LVDS
:
10904 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
10908 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10909 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
10913 if (IS_PINEVIEW(dev_priv
))
10914 port_clock
= pnv_calc_dpll_params(refclk
, &clock
);
10916 port_clock
= i9xx_calc_dpll_params(refclk
, &clock
);
10918 u32 lvds
= IS_I830(dev_priv
) ? 0 : I915_READ(LVDS
);
10919 bool is_lvds
= (pipe
== 1) && (lvds
& LVDS_PORT_EN
);
10922 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
10923 DPLL_FPA01_P1_POST_DIV_SHIFT
);
10925 if (lvds
& LVDS_CLKB_POWER_UP
)
10930 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
10933 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
10934 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
10936 if (dpll
& PLL_P2_DIVIDE_BY_4
)
10942 port_clock
= i9xx_calc_dpll_params(refclk
, &clock
);
10946 * This value includes pixel_multiplier. We will use
10947 * port_clock to compute adjusted_mode.crtc_clock in the
10948 * encoder's get_config() function.
10950 pipe_config
->port_clock
= port_clock
;
10953 int intel_dotclock_calculate(int link_freq
,
10954 const struct intel_link_m_n
*m_n
)
10957 * The calculation for the data clock is:
10958 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10959 * But we want to avoid losing precison if possible, so:
10960 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10962 * and the link clock is simpler:
10963 * link_clock = (m * link_clock) / n
10969 return div_u64(mul_u32_u32(m_n
->link_m
, link_freq
), m_n
->link_n
);
10972 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
10973 struct intel_crtc_state
*pipe_config
)
10975 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
10977 /* read out port_clock from the DPLL */
10978 i9xx_crtc_clock_get(crtc
, pipe_config
);
10981 * In case there is an active pipe without active ports,
10982 * we may need some idea for the dotclock anyway.
10983 * Calculate one based on the FDI configuration.
10985 pipe_config
->base
.adjusted_mode
.crtc_clock
=
10986 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv
, pipe_config
),
10987 &pipe_config
->fdi_m_n
);
10990 /* Returns the currently programmed mode of the given encoder. */
10991 struct drm_display_mode
*
10992 intel_encoder_current_mode(struct intel_encoder
*encoder
)
10994 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
10995 struct intel_crtc_state
*crtc_state
;
10996 struct drm_display_mode
*mode
;
10997 struct intel_crtc
*crtc
;
11000 if (!encoder
->get_hw_state(encoder
, &pipe
))
11003 crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
11005 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
11009 crtc_state
= kzalloc(sizeof(*crtc_state
), GFP_KERNEL
);
11015 crtc_state
->base
.crtc
= &crtc
->base
;
11017 if (!dev_priv
->display
.get_pipe_config(crtc
, crtc_state
)) {
11023 encoder
->get_config(encoder
, crtc_state
);
11025 intel_mode_from_pipe_config(mode
, crtc_state
);
11032 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
11034 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11036 drm_crtc_cleanup(crtc
);
11041 * intel_wm_need_update - Check whether watermarks need updating
11042 * @cur: current plane state
11043 * @new: new plane state
11045 * Check current plane state versus the new one to determine whether
11046 * watermarks need to be recalculated.
11048 * Returns true or false.
11050 static bool intel_wm_need_update(struct intel_plane_state
*cur
,
11051 struct intel_plane_state
*new)
11053 /* Update watermarks on tiling or size changes. */
11054 if (new->base
.visible
!= cur
->base
.visible
)
11057 if (!cur
->base
.fb
|| !new->base
.fb
)
11060 if (cur
->base
.fb
->modifier
!= new->base
.fb
->modifier
||
11061 cur
->base
.rotation
!= new->base
.rotation
||
11062 drm_rect_width(&new->base
.src
) != drm_rect_width(&cur
->base
.src
) ||
11063 drm_rect_height(&new->base
.src
) != drm_rect_height(&cur
->base
.src
) ||
11064 drm_rect_width(&new->base
.dst
) != drm_rect_width(&cur
->base
.dst
) ||
11065 drm_rect_height(&new->base
.dst
) != drm_rect_height(&cur
->base
.dst
))
11071 static bool needs_scaling(const struct intel_plane_state
*state
)
11073 int src_w
= drm_rect_width(&state
->base
.src
) >> 16;
11074 int src_h
= drm_rect_height(&state
->base
.src
) >> 16;
11075 int dst_w
= drm_rect_width(&state
->base
.dst
);
11076 int dst_h
= drm_rect_height(&state
->base
.dst
);
11078 return (src_w
!= dst_w
|| src_h
!= dst_h
);
11081 int intel_plane_atomic_calc_changes(const struct intel_crtc_state
*old_crtc_state
,
11082 struct drm_crtc_state
*crtc_state
,
11083 const struct intel_plane_state
*old_plane_state
,
11084 struct drm_plane_state
*plane_state
)
11086 struct intel_crtc_state
*pipe_config
= to_intel_crtc_state(crtc_state
);
11087 struct drm_crtc
*crtc
= crtc_state
->crtc
;
11088 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11089 struct intel_plane
*plane
= to_intel_plane(plane_state
->plane
);
11090 struct drm_device
*dev
= crtc
->dev
;
11091 struct drm_i915_private
*dev_priv
= to_i915(dev
);
11092 bool mode_changed
= needs_modeset(crtc_state
);
11093 bool was_crtc_enabled
= old_crtc_state
->base
.active
;
11094 bool is_crtc_enabled
= crtc_state
->active
;
11095 bool turn_off
, turn_on
, visible
, was_visible
;
11096 struct drm_framebuffer
*fb
= plane_state
->fb
;
11099 if (INTEL_GEN(dev_priv
) >= 9 && plane
->id
!= PLANE_CURSOR
) {
11100 ret
= skl_update_scaler_plane(
11101 to_intel_crtc_state(crtc_state
),
11102 to_intel_plane_state(plane_state
));
11107 was_visible
= old_plane_state
->base
.visible
;
11108 visible
= plane_state
->visible
;
11110 if (!was_crtc_enabled
&& WARN_ON(was_visible
))
11111 was_visible
= false;
11114 * Visibility is calculated as if the crtc was on, but
11115 * after scaler setup everything depends on it being off
11116 * when the crtc isn't active.
11118 * FIXME this is wrong for watermarks. Watermarks should also
11119 * be computed as if the pipe would be active. Perhaps move
11120 * per-plane wm computation to the .check_plane() hook, and
11121 * only combine the results from all planes in the current place?
11123 if (!is_crtc_enabled
) {
11124 plane_state
->visible
= visible
= false;
11125 to_intel_crtc_state(crtc_state
)->active_planes
&= ~BIT(plane
->id
);
11128 if (!was_visible
&& !visible
)
11131 if (fb
!= old_plane_state
->base
.fb
)
11132 pipe_config
->fb_changed
= true;
11134 turn_off
= was_visible
&& (!visible
|| mode_changed
);
11135 turn_on
= visible
&& (!was_visible
|| mode_changed
);
11137 DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
11138 intel_crtc
->base
.base
.id
, intel_crtc
->base
.name
,
11139 plane
->base
.base
.id
, plane
->base
.name
,
11140 fb
? fb
->base
.id
: -1);
11142 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
11143 plane
->base
.base
.id
, plane
->base
.name
,
11144 was_visible
, visible
,
11145 turn_off
, turn_on
, mode_changed
);
11148 if (INTEL_GEN(dev_priv
) < 5 && !IS_G4X(dev_priv
))
11149 pipe_config
->update_wm_pre
= true;
11151 /* must disable cxsr around plane enable/disable */
11152 if (plane
->id
!= PLANE_CURSOR
)
11153 pipe_config
->disable_cxsr
= true;
11154 } else if (turn_off
) {
11155 if (INTEL_GEN(dev_priv
) < 5 && !IS_G4X(dev_priv
))
11156 pipe_config
->update_wm_post
= true;
11158 /* must disable cxsr around plane enable/disable */
11159 if (plane
->id
!= PLANE_CURSOR
)
11160 pipe_config
->disable_cxsr
= true;
11161 } else if (intel_wm_need_update(to_intel_plane_state(plane
->base
.state
),
11162 to_intel_plane_state(plane_state
))) {
11163 if (INTEL_GEN(dev_priv
) < 5 && !IS_G4X(dev_priv
)) {
11164 /* FIXME bollocks */
11165 pipe_config
->update_wm_pre
= true;
11166 pipe_config
->update_wm_post
= true;
11170 if (visible
|| was_visible
)
11171 pipe_config
->fb_bits
|= plane
->frontbuffer_bit
;
11174 * ILK/SNB DVSACNTR/Sprite Enable
11175 * IVB SPR_CTL/Sprite Enable
11176 * "When in Self Refresh Big FIFO mode, a write to enable the
11177 * plane will be internally buffered and delayed while Big FIFO
11178 * mode is exiting."
11180 * Which means that enabling the sprite can take an extra frame
11181 * when we start in big FIFO mode (LP1+). Thus we need to drop
11182 * down to LP0 and wait for vblank in order to make sure the
11183 * sprite gets enabled on the next vblank after the register write.
11184 * Doing otherwise would risk enabling the sprite one frame after
11185 * we've already signalled flip completion. We can resume LP1+
11186 * once the sprite has been enabled.
11189 * WaCxSRDisabledForSpriteScaling:ivb
11190 * IVB SPR_SCALE/Scaling Enable
11191 * "Low Power watermarks must be disabled for at least one
11192 * frame before enabling sprite scaling, and kept disabled
11193 * until sprite scaling is disabled."
11195 * ILK/SNB DVSASCALE/Scaling Enable
11196 * "When in Self Refresh Big FIFO mode, scaling enable will be
11197 * masked off while Big FIFO mode is exiting."
11199 * Despite the w/a only being listed for IVB we assume that
11200 * the ILK/SNB note has similar ramifications, hence we apply
11201 * the w/a on all three platforms.
11203 * With experimental results seems this is needed also for primary
11204 * plane, not only sprite plane.
11206 if (plane
->id
!= PLANE_CURSOR
&&
11207 (IS_GEN_RANGE(dev_priv
, 5, 6) ||
11208 IS_IVYBRIDGE(dev_priv
)) &&
11209 (turn_on
|| (!needs_scaling(old_plane_state
) &&
11210 needs_scaling(to_intel_plane_state(plane_state
)))))
11211 pipe_config
->disable_lp_wm
= true;
11216 static bool encoders_cloneable(const struct intel_encoder
*a
,
11217 const struct intel_encoder
*b
)
11219 /* masks could be asymmetric, so check both ways */
11220 return a
== b
|| (a
->cloneable
& (1 << b
->type
) &&
11221 b
->cloneable
& (1 << a
->type
));
11224 static bool check_single_encoder_cloning(struct drm_atomic_state
*state
,
11225 struct intel_crtc
*crtc
,
11226 struct intel_encoder
*encoder
)
11228 struct intel_encoder
*source_encoder
;
11229 struct drm_connector
*connector
;
11230 struct drm_connector_state
*connector_state
;
11233 for_each_new_connector_in_state(state
, connector
, connector_state
, i
) {
11234 if (connector_state
->crtc
!= &crtc
->base
)
11238 to_intel_encoder(connector_state
->best_encoder
);
11239 if (!encoders_cloneable(encoder
, source_encoder
))
11246 static int icl_add_linked_planes(struct intel_atomic_state
*state
)
11248 struct intel_plane
*plane
, *linked
;
11249 struct intel_plane_state
*plane_state
, *linked_plane_state
;
11252 for_each_new_intel_plane_in_state(state
, plane
, plane_state
, i
) {
11253 linked
= plane_state
->linked_plane
;
11258 linked_plane_state
= intel_atomic_get_plane_state(state
, linked
);
11259 if (IS_ERR(linked_plane_state
))
11260 return PTR_ERR(linked_plane_state
);
11262 WARN_ON(linked_plane_state
->linked_plane
!= plane
);
11263 WARN_ON(linked_plane_state
->slave
== plane_state
->slave
);
11269 static int icl_check_nv12_planes(struct intel_crtc_state
*crtc_state
)
11271 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
11272 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
11273 struct intel_atomic_state
*state
= to_intel_atomic_state(crtc_state
->base
.state
);
11274 struct intel_plane
*plane
, *linked
;
11275 struct intel_plane_state
*plane_state
;
11278 if (INTEL_GEN(dev_priv
) < 11)
11282 * Destroy all old plane links and make the slave plane invisible
11283 * in the crtc_state->active_planes mask.
11285 for_each_new_intel_plane_in_state(state
, plane
, plane_state
, i
) {
11286 if (plane
->pipe
!= crtc
->pipe
|| !plane_state
->linked_plane
)
11289 plane_state
->linked_plane
= NULL
;
11290 if (plane_state
->slave
&& !plane_state
->base
.visible
) {
11291 crtc_state
->active_planes
&= ~BIT(plane
->id
);
11292 crtc_state
->update_planes
|= BIT(plane
->id
);
11295 plane_state
->slave
= false;
11298 if (!crtc_state
->nv12_planes
)
11301 for_each_new_intel_plane_in_state(state
, plane
, plane_state
, i
) {
11302 struct intel_plane_state
*linked_state
= NULL
;
11304 if (plane
->pipe
!= crtc
->pipe
||
11305 !(crtc_state
->nv12_planes
& BIT(plane
->id
)))
11308 for_each_intel_plane_on_crtc(&dev_priv
->drm
, crtc
, linked
) {
11309 if (!icl_is_nv12_y_plane(linked
->id
))
11312 if (crtc_state
->active_planes
& BIT(linked
->id
))
11315 linked_state
= intel_atomic_get_plane_state(state
, linked
);
11316 if (IS_ERR(linked_state
))
11317 return PTR_ERR(linked_state
);
11322 if (!linked_state
) {
11323 DRM_DEBUG_KMS("Need %d free Y planes for planar YUV\n",
11324 hweight8(crtc_state
->nv12_planes
));
11329 plane_state
->linked_plane
= linked
;
11331 linked_state
->slave
= true;
11332 linked_state
->linked_plane
= plane
;
11333 crtc_state
->active_planes
|= BIT(linked
->id
);
11334 crtc_state
->update_planes
|= BIT(linked
->id
);
11335 DRM_DEBUG_KMS("Using %s as Y plane for %s\n", linked
->base
.name
, plane
->base
.name
);
11341 static int intel_crtc_atomic_check(struct drm_crtc
*crtc
,
11342 struct drm_crtc_state
*crtc_state
)
11344 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
11345 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11346 struct intel_crtc_state
*pipe_config
=
11347 to_intel_crtc_state(crtc_state
);
11349 bool mode_changed
= needs_modeset(crtc_state
);
11351 if (INTEL_GEN(dev_priv
) < 5 && !IS_G4X(dev_priv
) &&
11352 mode_changed
&& !crtc_state
->active
)
11353 pipe_config
->update_wm_post
= true;
11355 if (mode_changed
&& crtc_state
->enable
&&
11356 dev_priv
->display
.crtc_compute_clock
&&
11357 !WARN_ON(pipe_config
->shared_dpll
)) {
11358 ret
= dev_priv
->display
.crtc_compute_clock(intel_crtc
,
11364 if (mode_changed
|| pipe_config
->update_pipe
||
11365 crtc_state
->color_mgmt_changed
) {
11366 ret
= intel_color_check(pipe_config
);
11372 if (dev_priv
->display
.compute_pipe_wm
) {
11373 ret
= dev_priv
->display
.compute_pipe_wm(pipe_config
);
11375 DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
11380 if (dev_priv
->display
.compute_intermediate_wm
) {
11381 if (WARN_ON(!dev_priv
->display
.compute_pipe_wm
))
11385 * Calculate 'intermediate' watermarks that satisfy both the
11386 * old state and the new state. We can program these
11389 ret
= dev_priv
->display
.compute_intermediate_wm(pipe_config
);
11391 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
11396 if (INTEL_GEN(dev_priv
) >= 9) {
11397 if (mode_changed
|| pipe_config
->update_pipe
)
11398 ret
= skl_update_scaler_crtc(pipe_config
);
11401 ret
= icl_check_nv12_planes(pipe_config
);
11403 ret
= skl_check_pipe_max_pixel_rate(intel_crtc
,
11406 ret
= intel_atomic_setup_scalers(dev_priv
, intel_crtc
,
11410 if (HAS_IPS(dev_priv
))
11411 pipe_config
->ips_enabled
= hsw_compute_ips_config(pipe_config
);
11416 static const struct drm_crtc_helper_funcs intel_helper_funcs
= {
11417 .atomic_check
= intel_crtc_atomic_check
,
11420 static void intel_modeset_update_connector_atomic_state(struct drm_device
*dev
)
11422 struct intel_connector
*connector
;
11423 struct drm_connector_list_iter conn_iter
;
11425 drm_connector_list_iter_begin(dev
, &conn_iter
);
11426 for_each_intel_connector_iter(connector
, &conn_iter
) {
11427 if (connector
->base
.state
->crtc
)
11428 drm_connector_put(&connector
->base
);
11430 if (connector
->base
.encoder
) {
11431 connector
->base
.state
->best_encoder
=
11432 connector
->base
.encoder
;
11433 connector
->base
.state
->crtc
=
11434 connector
->base
.encoder
->crtc
;
11436 drm_connector_get(&connector
->base
);
11438 connector
->base
.state
->best_encoder
= NULL
;
11439 connector
->base
.state
->crtc
= NULL
;
11442 drm_connector_list_iter_end(&conn_iter
);
11446 compute_sink_pipe_bpp(const struct drm_connector_state
*conn_state
,
11447 struct intel_crtc_state
*pipe_config
)
11449 struct drm_connector
*connector
= conn_state
->connector
;
11450 const struct drm_display_info
*info
= &connector
->display_info
;
11453 switch (conn_state
->max_bpc
) {
11470 if (bpp
< pipe_config
->pipe_bpp
) {
11471 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Limiting display bpp to %d instead of "
11472 "EDID bpp %d, requested bpp %d, max platform bpp %d\n",
11473 connector
->base
.id
, connector
->name
,
11474 bpp
, 3 * info
->bpc
, 3 * conn_state
->max_requested_bpc
,
11475 pipe_config
->pipe_bpp
);
11477 pipe_config
->pipe_bpp
= bpp
;
11484 compute_baseline_pipe_bpp(struct intel_crtc
*crtc
,
11485 struct intel_crtc_state
*pipe_config
)
11487 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
11488 struct drm_atomic_state
*state
= pipe_config
->base
.state
;
11489 struct drm_connector
*connector
;
11490 struct drm_connector_state
*connector_state
;
11493 if ((IS_G4X(dev_priv
) || IS_VALLEYVIEW(dev_priv
) ||
11494 IS_CHERRYVIEW(dev_priv
)))
11496 else if (INTEL_GEN(dev_priv
) >= 5)
11501 pipe_config
->pipe_bpp
= bpp
;
11503 /* Clamp display bpp to connector max bpp */
11504 for_each_new_connector_in_state(state
, connector
, connector_state
, i
) {
11507 if (connector_state
->crtc
!= &crtc
->base
)
11510 ret
= compute_sink_pipe_bpp(connector_state
, pipe_config
);
11518 static void intel_dump_crtc_timings(const struct drm_display_mode
*mode
)
11520 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11521 "type: 0x%x flags: 0x%x\n",
11523 mode
->crtc_hdisplay
, mode
->crtc_hsync_start
,
11524 mode
->crtc_hsync_end
, mode
->crtc_htotal
,
11525 mode
->crtc_vdisplay
, mode
->crtc_vsync_start
,
11526 mode
->crtc_vsync_end
, mode
->crtc_vtotal
, mode
->type
, mode
->flags
);
11530 intel_dump_m_n_config(struct intel_crtc_state
*pipe_config
, char *id
,
11531 unsigned int lane_count
, struct intel_link_m_n
*m_n
)
11533 DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11535 m_n
->gmch_m
, m_n
->gmch_n
,
11536 m_n
->link_m
, m_n
->link_n
, m_n
->tu
);
11540 intel_dump_infoframe(struct drm_i915_private
*dev_priv
,
11541 const union hdmi_infoframe
*frame
)
11543 if ((drm_debug
& DRM_UT_KMS
) == 0)
11546 hdmi_infoframe_log(KERN_DEBUG
, dev_priv
->drm
.dev
, frame
);
11549 #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
11551 static const char * const output_type_str
[] = {
11552 OUTPUT_TYPE(UNUSED
),
11553 OUTPUT_TYPE(ANALOG
),
11557 OUTPUT_TYPE(TVOUT
),
11563 OUTPUT_TYPE(DP_MST
),
11568 static void snprintf_output_types(char *buf
, size_t len
,
11569 unsigned int output_types
)
11576 for (i
= 0; i
< ARRAY_SIZE(output_type_str
); i
++) {
11579 if ((output_types
& BIT(i
)) == 0)
11582 r
= snprintf(str
, len
, "%s%s",
11583 str
!= buf
? "," : "", output_type_str
[i
]);
11589 output_types
&= ~BIT(i
);
11592 WARN_ON_ONCE(output_types
!= 0);
11595 static const char * const output_format_str
[] = {
11596 [INTEL_OUTPUT_FORMAT_INVALID
] = "Invalid",
11597 [INTEL_OUTPUT_FORMAT_RGB
] = "RGB",
11598 [INTEL_OUTPUT_FORMAT_YCBCR420
] = "YCBCR4:2:0",
11599 [INTEL_OUTPUT_FORMAT_YCBCR444
] = "YCBCR4:4:4",
11602 static const char *output_formats(enum intel_output_format format
)
11604 if (format
>= ARRAY_SIZE(output_format_str
))
11605 format
= INTEL_OUTPUT_FORMAT_INVALID
;
11606 return output_format_str
[format
];
11609 static void intel_dump_pipe_config(struct intel_crtc
*crtc
,
11610 struct intel_crtc_state
*pipe_config
,
11611 const char *context
)
11613 struct drm_device
*dev
= crtc
->base
.dev
;
11614 struct drm_i915_private
*dev_priv
= to_i915(dev
);
11615 struct drm_plane
*plane
;
11616 struct intel_plane
*intel_plane
;
11617 struct intel_plane_state
*state
;
11618 struct drm_framebuffer
*fb
;
11621 DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n",
11622 crtc
->base
.base
.id
, crtc
->base
.name
, context
);
11624 snprintf_output_types(buf
, sizeof(buf
), pipe_config
->output_types
);
11625 DRM_DEBUG_KMS("output_types: %s (0x%x)\n",
11626 buf
, pipe_config
->output_types
);
11628 DRM_DEBUG_KMS("output format: %s\n",
11629 output_formats(pipe_config
->output_format
));
11631 DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
11632 transcoder_name(pipe_config
->cpu_transcoder
),
11633 pipe_config
->pipe_bpp
, pipe_config
->dither
);
11635 if (pipe_config
->has_pch_encoder
)
11636 intel_dump_m_n_config(pipe_config
, "fdi",
11637 pipe_config
->fdi_lanes
,
11638 &pipe_config
->fdi_m_n
);
11640 if (intel_crtc_has_dp_encoder(pipe_config
)) {
11641 intel_dump_m_n_config(pipe_config
, "dp m_n",
11642 pipe_config
->lane_count
, &pipe_config
->dp_m_n
);
11643 if (pipe_config
->has_drrs
)
11644 intel_dump_m_n_config(pipe_config
, "dp m2_n2",
11645 pipe_config
->lane_count
,
11646 &pipe_config
->dp_m2_n2
);
11649 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11650 pipe_config
->has_audio
, pipe_config
->has_infoframe
);
11652 DRM_DEBUG_KMS("infoframes enabled: 0x%x\n",
11653 pipe_config
->infoframes
.enable
);
11655 if (pipe_config
->infoframes
.enable
&
11656 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL
))
11657 DRM_DEBUG_KMS("GCP: 0x%x\n", pipe_config
->infoframes
.gcp
);
11658 if (pipe_config
->infoframes
.enable
&
11659 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI
))
11660 intel_dump_infoframe(dev_priv
, &pipe_config
->infoframes
.avi
);
11661 if (pipe_config
->infoframes
.enable
&
11662 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD
))
11663 intel_dump_infoframe(dev_priv
, &pipe_config
->infoframes
.spd
);
11664 if (pipe_config
->infoframes
.enable
&
11665 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR
))
11666 intel_dump_infoframe(dev_priv
, &pipe_config
->infoframes
.hdmi
);
11668 DRM_DEBUG_KMS("requested mode:\n");
11669 drm_mode_debug_printmodeline(&pipe_config
->base
.mode
);
11670 DRM_DEBUG_KMS("adjusted mode:\n");
11671 drm_mode_debug_printmodeline(&pipe_config
->base
.adjusted_mode
);
11672 intel_dump_crtc_timings(&pipe_config
->base
.adjusted_mode
);
11673 DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
11674 pipe_config
->port_clock
,
11675 pipe_config
->pipe_src_w
, pipe_config
->pipe_src_h
,
11676 pipe_config
->pixel_rate
);
11678 if (INTEL_GEN(dev_priv
) >= 9)
11679 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11681 pipe_config
->scaler_state
.scaler_users
,
11682 pipe_config
->scaler_state
.scaler_id
);
11684 if (HAS_GMCH(dev_priv
))
11685 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11686 pipe_config
->gmch_pfit
.control
,
11687 pipe_config
->gmch_pfit
.pgm_ratios
,
11688 pipe_config
->gmch_pfit
.lvds_border_bits
);
11690 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11691 pipe_config
->pch_pfit
.pos
,
11692 pipe_config
->pch_pfit
.size
,
11693 enableddisabled(pipe_config
->pch_pfit
.enabled
));
11695 DRM_DEBUG_KMS("ips: %i, double wide: %i\n",
11696 pipe_config
->ips_enabled
, pipe_config
->double_wide
);
11698 intel_dpll_dump_hw_state(dev_priv
, &pipe_config
->dpll_hw_state
);
11700 DRM_DEBUG_KMS("planes on this crtc\n");
11701 list_for_each_entry(plane
, &dev
->mode_config
.plane_list
, head
) {
11702 struct drm_format_name_buf format_name
;
11703 intel_plane
= to_intel_plane(plane
);
11704 if (intel_plane
->pipe
!= crtc
->pipe
)
11707 state
= to_intel_plane_state(plane
->state
);
11708 fb
= state
->base
.fb
;
11710 DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
11711 plane
->base
.id
, plane
->name
, state
->scaler_id
);
11715 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n",
11716 plane
->base
.id
, plane
->name
,
11717 fb
->base
.id
, fb
->width
, fb
->height
,
11718 drm_get_format_name(fb
->format
->format
, &format_name
));
11719 if (INTEL_GEN(dev_priv
) >= 9)
11720 DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
11722 state
->base
.src
.x1
>> 16,
11723 state
->base
.src
.y1
>> 16,
11724 drm_rect_width(&state
->base
.src
) >> 16,
11725 drm_rect_height(&state
->base
.src
) >> 16,
11726 state
->base
.dst
.x1
, state
->base
.dst
.y1
,
11727 drm_rect_width(&state
->base
.dst
),
11728 drm_rect_height(&state
->base
.dst
));
11732 static bool check_digital_port_conflicts(struct drm_atomic_state
*state
)
11734 struct drm_device
*dev
= state
->dev
;
11735 struct drm_connector
*connector
;
11736 struct drm_connector_list_iter conn_iter
;
11737 unsigned int used_ports
= 0;
11738 unsigned int used_mst_ports
= 0;
11742 * Walk the connector list instead of the encoder
11743 * list to detect the problem on ddi platforms
11744 * where there's just one encoder per digital port.
11746 drm_connector_list_iter_begin(dev
, &conn_iter
);
11747 drm_for_each_connector_iter(connector
, &conn_iter
) {
11748 struct drm_connector_state
*connector_state
;
11749 struct intel_encoder
*encoder
;
11751 connector_state
= drm_atomic_get_new_connector_state(state
, connector
);
11752 if (!connector_state
)
11753 connector_state
= connector
->state
;
11755 if (!connector_state
->best_encoder
)
11758 encoder
= to_intel_encoder(connector_state
->best_encoder
);
11760 WARN_ON(!connector_state
->crtc
);
11762 switch (encoder
->type
) {
11763 unsigned int port_mask
;
11764 case INTEL_OUTPUT_DDI
:
11765 if (WARN_ON(!HAS_DDI(to_i915(dev
))))
11767 /* else: fall through */
11768 case INTEL_OUTPUT_DP
:
11769 case INTEL_OUTPUT_HDMI
:
11770 case INTEL_OUTPUT_EDP
:
11771 port_mask
= 1 << encoder
->port
;
11773 /* the same port mustn't appear more than once */
11774 if (used_ports
& port_mask
)
11777 used_ports
|= port_mask
;
11779 case INTEL_OUTPUT_DP_MST
:
11781 1 << encoder
->port
;
11787 drm_connector_list_iter_end(&conn_iter
);
11789 /* can't mix MST and SST/HDMI on the same port */
11790 if (used_ports
& used_mst_ports
)
11797 clear_intel_crtc_state(struct intel_crtc_state
*crtc_state
)
11799 struct drm_i915_private
*dev_priv
=
11800 to_i915(crtc_state
->base
.crtc
->dev
);
11801 struct intel_crtc_state
*saved_state
;
11803 saved_state
= kzalloc(sizeof(*saved_state
), GFP_KERNEL
);
11807 /* FIXME: before the switch to atomic started, a new pipe_config was
11808 * kzalloc'd. Code that depends on any field being zero should be
11809 * fixed, so that the crtc_state can be safely duplicated. For now,
11810 * only fields that are know to not cause problems are preserved. */
11812 saved_state
->scaler_state
= crtc_state
->scaler_state
;
11813 saved_state
->shared_dpll
= crtc_state
->shared_dpll
;
11814 saved_state
->dpll_hw_state
= crtc_state
->dpll_hw_state
;
11815 saved_state
->pch_pfit
.force_thru
= crtc_state
->pch_pfit
.force_thru
;
11816 saved_state
->crc_enabled
= crtc_state
->crc_enabled
;
11817 if (IS_G4X(dev_priv
) ||
11818 IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
11819 saved_state
->wm
= crtc_state
->wm
;
11821 /* Keep base drm_crtc_state intact, only clear our extended struct */
11822 BUILD_BUG_ON(offsetof(struct intel_crtc_state
, base
));
11823 memcpy(&crtc_state
->base
+ 1, &saved_state
->base
+ 1,
11824 sizeof(*crtc_state
) - sizeof(crtc_state
->base
));
11826 kfree(saved_state
);
11831 intel_modeset_pipe_config(struct drm_crtc
*crtc
,
11832 struct intel_crtc_state
*pipe_config
)
11834 struct drm_atomic_state
*state
= pipe_config
->base
.state
;
11835 struct intel_encoder
*encoder
;
11836 struct drm_connector
*connector
;
11837 struct drm_connector_state
*connector_state
;
11842 ret
= clear_intel_crtc_state(pipe_config
);
11846 pipe_config
->cpu_transcoder
=
11847 (enum transcoder
) to_intel_crtc(crtc
)->pipe
;
11850 * Sanitize sync polarity flags based on requested ones. If neither
11851 * positive or negative polarity is requested, treat this as meaning
11852 * negative polarity.
11854 if (!(pipe_config
->base
.adjusted_mode
.flags
&
11855 (DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NHSYNC
)))
11856 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_NHSYNC
;
11858 if (!(pipe_config
->base
.adjusted_mode
.flags
&
11859 (DRM_MODE_FLAG_PVSYNC
| DRM_MODE_FLAG_NVSYNC
)))
11860 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_NVSYNC
;
11862 ret
= compute_baseline_pipe_bpp(to_intel_crtc(crtc
),
11867 base_bpp
= pipe_config
->pipe_bpp
;
11870 * Determine the real pipe dimensions. Note that stereo modes can
11871 * increase the actual pipe size due to the frame doubling and
11872 * insertion of additional space for blanks between the frame. This
11873 * is stored in the crtc timings. We use the requested mode to do this
11874 * computation to clearly distinguish it from the adjusted mode, which
11875 * can be changed by the connectors in the below retry loop.
11877 drm_mode_get_hv_timing(&pipe_config
->base
.mode
,
11878 &pipe_config
->pipe_src_w
,
11879 &pipe_config
->pipe_src_h
);
11881 for_each_new_connector_in_state(state
, connector
, connector_state
, i
) {
11882 if (connector_state
->crtc
!= crtc
)
11885 encoder
= to_intel_encoder(connector_state
->best_encoder
);
11887 if (!check_single_encoder_cloning(state
, to_intel_crtc(crtc
), encoder
)) {
11888 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11893 * Determine output_types before calling the .compute_config()
11894 * hooks so that the hooks can use this information safely.
11896 if (encoder
->compute_output_type
)
11897 pipe_config
->output_types
|=
11898 BIT(encoder
->compute_output_type(encoder
, pipe_config
,
11901 pipe_config
->output_types
|= BIT(encoder
->type
);
11905 /* Ensure the port clock defaults are reset when retrying. */
11906 pipe_config
->port_clock
= 0;
11907 pipe_config
->pixel_multiplier
= 1;
11909 /* Fill in default crtc timings, allow encoders to overwrite them. */
11910 drm_mode_set_crtcinfo(&pipe_config
->base
.adjusted_mode
,
11911 CRTC_STEREO_DOUBLE
);
11913 /* Pass our mode to the connectors and the CRTC to give them a chance to
11914 * adjust it according to limitations or connector properties, and also
11915 * a chance to reject the mode entirely.
11917 for_each_new_connector_in_state(state
, connector
, connector_state
, i
) {
11918 if (connector_state
->crtc
!= crtc
)
11921 encoder
= to_intel_encoder(connector_state
->best_encoder
);
11922 ret
= encoder
->compute_config(encoder
, pipe_config
,
11925 if (ret
!= -EDEADLK
)
11926 DRM_DEBUG_KMS("Encoder config failure: %d\n",
11932 /* Set default port clock if not overwritten by the encoder. Needs to be
11933 * done afterwards in case the encoder adjusts the mode. */
11934 if (!pipe_config
->port_clock
)
11935 pipe_config
->port_clock
= pipe_config
->base
.adjusted_mode
.crtc_clock
11936 * pipe_config
->pixel_multiplier
;
11938 ret
= intel_crtc_compute_config(to_intel_crtc(crtc
), pipe_config
);
11939 if (ret
== -EDEADLK
)
11942 DRM_DEBUG_KMS("CRTC fixup failed\n");
11946 if (ret
== RETRY
) {
11947 if (WARN(!retry
, "loop in pipe configuration computation\n"))
11950 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
11952 goto encoder_retry
;
11955 /* Dithering seems to not pass-through bits correctly when it should, so
11956 * only enable it on 6bpc panels and when its not a compliance
11957 * test requesting 6bpc video pattern.
11959 pipe_config
->dither
= (pipe_config
->pipe_bpp
== 6*3) &&
11960 !pipe_config
->dither_force_disable
;
11961 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
11962 base_bpp
, pipe_config
->pipe_bpp
, pipe_config
->dither
);
11967 static bool intel_fuzzy_clock_check(int clock1
, int clock2
)
11971 if (clock1
== clock2
)
11974 if (!clock1
|| !clock2
)
11977 diff
= abs(clock1
- clock2
);
11979 if (((((diff
+ clock1
+ clock2
) * 100)) / (clock1
+ clock2
)) < 105)
11986 intel_compare_m_n(unsigned int m
, unsigned int n
,
11987 unsigned int m2
, unsigned int n2
,
11990 if (m
== m2
&& n
== n2
)
11993 if (exact
|| !m
|| !n
|| !m2
|| !n2
)
11996 BUILD_BUG_ON(DATA_LINK_M_N_MASK
> INT_MAX
);
12003 } else if (n
< n2
) {
12013 return intel_fuzzy_clock_check(m
, m2
);
12017 intel_compare_link_m_n(const struct intel_link_m_n
*m_n
,
12018 struct intel_link_m_n
*m2_n2
,
12021 if (m_n
->tu
== m2_n2
->tu
&&
12022 intel_compare_m_n(m_n
->gmch_m
, m_n
->gmch_n
,
12023 m2_n2
->gmch_m
, m2_n2
->gmch_n
, !adjust
) &&
12024 intel_compare_m_n(m_n
->link_m
, m_n
->link_n
,
12025 m2_n2
->link_m
, m2_n2
->link_n
, !adjust
)) {
12036 intel_compare_infoframe(const union hdmi_infoframe
*a
,
12037 const union hdmi_infoframe
*b
)
12039 return memcmp(a
, b
, sizeof(*a
)) == 0;
12043 pipe_config_infoframe_err(struct drm_i915_private
*dev_priv
,
12044 bool adjust
, const char *name
,
12045 const union hdmi_infoframe
*a
,
12046 const union hdmi_infoframe
*b
)
12049 if ((drm_debug
& DRM_UT_KMS
) == 0)
12052 drm_dbg(DRM_UT_KMS
, "mismatch in %s infoframe", name
);
12053 drm_dbg(DRM_UT_KMS
, "expected:");
12054 hdmi_infoframe_log(KERN_DEBUG
, dev_priv
->drm
.dev
, a
);
12055 drm_dbg(DRM_UT_KMS
, "found");
12056 hdmi_infoframe_log(KERN_DEBUG
, dev_priv
->drm
.dev
, b
);
12058 drm_err("mismatch in %s infoframe", name
);
12059 drm_err("expected:");
12060 hdmi_infoframe_log(KERN_ERR
, dev_priv
->drm
.dev
, a
);
12062 hdmi_infoframe_log(KERN_ERR
, dev_priv
->drm
.dev
, b
);
12066 static void __printf(3, 4)
12067 pipe_config_err(bool adjust
, const char *name
, const char *format
, ...)
12069 struct va_format vaf
;
12072 va_start(args
, format
);
12077 drm_dbg(DRM_UT_KMS
, "mismatch in %s %pV", name
, &vaf
);
12079 drm_err("mismatch in %s %pV", name
, &vaf
);
12084 static bool fastboot_enabled(struct drm_i915_private
*dev_priv
)
12086 if (i915_modparams
.fastboot
!= -1)
12087 return i915_modparams
.fastboot
;
12089 /* Enable fastboot by default on Skylake and newer */
12090 if (INTEL_GEN(dev_priv
) >= 9)
12093 /* Enable fastboot by default on VLV and CHV */
12094 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
12097 /* Disabled by default on all others */
12102 intel_pipe_config_compare(struct drm_i915_private
*dev_priv
,
12103 struct intel_crtc_state
*current_config
,
12104 struct intel_crtc_state
*pipe_config
,
12108 bool fixup_inherited
= adjust
&&
12109 (current_config
->base
.mode
.private_flags
& I915_MODE_FLAG_INHERITED
) &&
12110 !(pipe_config
->base
.mode
.private_flags
& I915_MODE_FLAG_INHERITED
);
12112 if (fixup_inherited
&& !fastboot_enabled(dev_priv
)) {
12113 DRM_DEBUG_KMS("initial modeset and fastboot not set\n");
12117 #define PIPE_CONF_CHECK_X(name) do { \
12118 if (current_config->name != pipe_config->name) { \
12119 pipe_config_err(adjust, __stringify(name), \
12120 "(expected 0x%08x, found 0x%08x)\n", \
12121 current_config->name, \
12122 pipe_config->name); \
12127 #define PIPE_CONF_CHECK_I(name) do { \
12128 if (current_config->name != pipe_config->name) { \
12129 pipe_config_err(adjust, __stringify(name), \
12130 "(expected %i, found %i)\n", \
12131 current_config->name, \
12132 pipe_config->name); \
12137 #define PIPE_CONF_CHECK_BOOL(name) do { \
12138 if (current_config->name != pipe_config->name) { \
12139 pipe_config_err(adjust, __stringify(name), \
12140 "(expected %s, found %s)\n", \
12141 yesno(current_config->name), \
12142 yesno(pipe_config->name)); \
12148 * Checks state where we only read out the enabling, but not the entire
12149 * state itself (like full infoframes or ELD for audio). These states
12150 * require a full modeset on bootup to fix up.
12152 #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \
12153 if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \
12154 PIPE_CONF_CHECK_BOOL(name); \
12156 pipe_config_err(adjust, __stringify(name), \
12157 "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)\n", \
12158 yesno(current_config->name), \
12159 yesno(pipe_config->name)); \
12164 #define PIPE_CONF_CHECK_P(name) do { \
12165 if (current_config->name != pipe_config->name) { \
12166 pipe_config_err(adjust, __stringify(name), \
12167 "(expected %p, found %p)\n", \
12168 current_config->name, \
12169 pipe_config->name); \
12174 #define PIPE_CONF_CHECK_M_N(name) do { \
12175 if (!intel_compare_link_m_n(¤t_config->name, \
12176 &pipe_config->name,\
12178 pipe_config_err(adjust, __stringify(name), \
12179 "(expected tu %i gmch %i/%i link %i/%i, " \
12180 "found tu %i, gmch %i/%i link %i/%i)\n", \
12181 current_config->name.tu, \
12182 current_config->name.gmch_m, \
12183 current_config->name.gmch_n, \
12184 current_config->name.link_m, \
12185 current_config->name.link_n, \
12186 pipe_config->name.tu, \
12187 pipe_config->name.gmch_m, \
12188 pipe_config->name.gmch_n, \
12189 pipe_config->name.link_m, \
12190 pipe_config->name.link_n); \
12195 /* This is required for BDW+ where there is only one set of registers for
12196 * switching between high and low RR.
12197 * This macro can be used whenever a comparison has to be made between one
12198 * hw state and multiple sw state variables.
12200 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) do { \
12201 if (!intel_compare_link_m_n(¤t_config->name, \
12202 &pipe_config->name, adjust) && \
12203 !intel_compare_link_m_n(¤t_config->alt_name, \
12204 &pipe_config->name, adjust)) { \
12205 pipe_config_err(adjust, __stringify(name), \
12206 "(expected tu %i gmch %i/%i link %i/%i, " \
12207 "or tu %i gmch %i/%i link %i/%i, " \
12208 "found tu %i, gmch %i/%i link %i/%i)\n", \
12209 current_config->name.tu, \
12210 current_config->name.gmch_m, \
12211 current_config->name.gmch_n, \
12212 current_config->name.link_m, \
12213 current_config->name.link_n, \
12214 current_config->alt_name.tu, \
12215 current_config->alt_name.gmch_m, \
12216 current_config->alt_name.gmch_n, \
12217 current_config->alt_name.link_m, \
12218 current_config->alt_name.link_n, \
12219 pipe_config->name.tu, \
12220 pipe_config->name.gmch_m, \
12221 pipe_config->name.gmch_n, \
12222 pipe_config->name.link_m, \
12223 pipe_config->name.link_n); \
12228 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \
12229 if ((current_config->name ^ pipe_config->name) & (mask)) { \
12230 pipe_config_err(adjust, __stringify(name), \
12231 "(%x) (expected %i, found %i)\n", \
12233 current_config->name & (mask), \
12234 pipe_config->name & (mask)); \
12239 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) do { \
12240 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12241 pipe_config_err(adjust, __stringify(name), \
12242 "(expected %i, found %i)\n", \
12243 current_config->name, \
12244 pipe_config->name); \
12249 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \
12250 if (!intel_compare_infoframe(¤t_config->infoframes.name, \
12251 &pipe_config->infoframes.name)) { \
12252 pipe_config_infoframe_err(dev_priv, adjust, __stringify(name), \
12253 ¤t_config->infoframes.name, \
12254 &pipe_config->infoframes.name); \
12259 #define PIPE_CONF_QUIRK(quirk) \
12260 ((current_config->quirks | pipe_config->quirks) & (quirk))
12262 PIPE_CONF_CHECK_I(cpu_transcoder
);
12264 PIPE_CONF_CHECK_BOOL(has_pch_encoder
);
12265 PIPE_CONF_CHECK_I(fdi_lanes
);
12266 PIPE_CONF_CHECK_M_N(fdi_m_n
);
12268 PIPE_CONF_CHECK_I(lane_count
);
12269 PIPE_CONF_CHECK_X(lane_lat_optim_mask
);
12271 if (INTEL_GEN(dev_priv
) < 8) {
12272 PIPE_CONF_CHECK_M_N(dp_m_n
);
12274 if (current_config
->has_drrs
)
12275 PIPE_CONF_CHECK_M_N(dp_m2_n2
);
12277 PIPE_CONF_CHECK_M_N_ALT(dp_m_n
, dp_m2_n2
);
12279 PIPE_CONF_CHECK_X(output_types
);
12281 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hdisplay
);
12282 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_htotal
);
12283 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hblank_start
);
12284 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hblank_end
);
12285 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hsync_start
);
12286 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hsync_end
);
12288 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vdisplay
);
12289 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vtotal
);
12290 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vblank_start
);
12291 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vblank_end
);
12292 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vsync_start
);
12293 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vsync_end
);
12295 PIPE_CONF_CHECK_I(pixel_multiplier
);
12296 PIPE_CONF_CHECK_I(output_format
);
12297 PIPE_CONF_CHECK_BOOL(has_hdmi_sink
);
12298 if ((INTEL_GEN(dev_priv
) < 8 && !IS_HASWELL(dev_priv
)) ||
12299 IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
12300 PIPE_CONF_CHECK_BOOL(limited_color_range
);
12302 PIPE_CONF_CHECK_BOOL(hdmi_scrambling
);
12303 PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio
);
12304 PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_infoframe
);
12306 PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio
);
12308 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
12309 DRM_MODE_FLAG_INTERLACE
);
12311 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS
)) {
12312 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
12313 DRM_MODE_FLAG_PHSYNC
);
12314 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
12315 DRM_MODE_FLAG_NHSYNC
);
12316 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
12317 DRM_MODE_FLAG_PVSYNC
);
12318 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
12319 DRM_MODE_FLAG_NVSYNC
);
12322 PIPE_CONF_CHECK_X(gmch_pfit
.control
);
12323 /* pfit ratios are autocomputed by the hw on gen4+ */
12324 if (INTEL_GEN(dev_priv
) < 4)
12325 PIPE_CONF_CHECK_X(gmch_pfit
.pgm_ratios
);
12326 PIPE_CONF_CHECK_X(gmch_pfit
.lvds_border_bits
);
12329 PIPE_CONF_CHECK_I(pipe_src_w
);
12330 PIPE_CONF_CHECK_I(pipe_src_h
);
12332 PIPE_CONF_CHECK_BOOL(pch_pfit
.enabled
);
12333 if (current_config
->pch_pfit
.enabled
) {
12334 PIPE_CONF_CHECK_X(pch_pfit
.pos
);
12335 PIPE_CONF_CHECK_X(pch_pfit
.size
);
12338 PIPE_CONF_CHECK_I(scaler_state
.scaler_id
);
12339 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate
);
12341 PIPE_CONF_CHECK_X(gamma_mode
);
12342 if (IS_CHERRYVIEW(dev_priv
))
12343 PIPE_CONF_CHECK_X(cgm_mode
);
12345 PIPE_CONF_CHECK_X(csc_mode
);
12346 PIPE_CONF_CHECK_BOOL(gamma_enable
);
12347 PIPE_CONF_CHECK_BOOL(csc_enable
);
12350 PIPE_CONF_CHECK_BOOL(double_wide
);
12352 PIPE_CONF_CHECK_P(shared_dpll
);
12353 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll
);
12354 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll_md
);
12355 PIPE_CONF_CHECK_X(dpll_hw_state
.fp0
);
12356 PIPE_CONF_CHECK_X(dpll_hw_state
.fp1
);
12357 PIPE_CONF_CHECK_X(dpll_hw_state
.wrpll
);
12358 PIPE_CONF_CHECK_X(dpll_hw_state
.spll
);
12359 PIPE_CONF_CHECK_X(dpll_hw_state
.ctrl1
);
12360 PIPE_CONF_CHECK_X(dpll_hw_state
.cfgcr1
);
12361 PIPE_CONF_CHECK_X(dpll_hw_state
.cfgcr2
);
12362 PIPE_CONF_CHECK_X(dpll_hw_state
.cfgcr0
);
12363 PIPE_CONF_CHECK_X(dpll_hw_state
.ebb0
);
12364 PIPE_CONF_CHECK_X(dpll_hw_state
.ebb4
);
12365 PIPE_CONF_CHECK_X(dpll_hw_state
.pll0
);
12366 PIPE_CONF_CHECK_X(dpll_hw_state
.pll1
);
12367 PIPE_CONF_CHECK_X(dpll_hw_state
.pll2
);
12368 PIPE_CONF_CHECK_X(dpll_hw_state
.pll3
);
12369 PIPE_CONF_CHECK_X(dpll_hw_state
.pll6
);
12370 PIPE_CONF_CHECK_X(dpll_hw_state
.pll8
);
12371 PIPE_CONF_CHECK_X(dpll_hw_state
.pll9
);
12372 PIPE_CONF_CHECK_X(dpll_hw_state
.pll10
);
12373 PIPE_CONF_CHECK_X(dpll_hw_state
.pcsdw12
);
12374 PIPE_CONF_CHECK_X(dpll_hw_state
.mg_refclkin_ctl
);
12375 PIPE_CONF_CHECK_X(dpll_hw_state
.mg_clktop2_coreclkctl1
);
12376 PIPE_CONF_CHECK_X(dpll_hw_state
.mg_clktop2_hsclkctl
);
12377 PIPE_CONF_CHECK_X(dpll_hw_state
.mg_pll_div0
);
12378 PIPE_CONF_CHECK_X(dpll_hw_state
.mg_pll_div1
);
12379 PIPE_CONF_CHECK_X(dpll_hw_state
.mg_pll_lf
);
12380 PIPE_CONF_CHECK_X(dpll_hw_state
.mg_pll_frac_lock
);
12381 PIPE_CONF_CHECK_X(dpll_hw_state
.mg_pll_ssc
);
12382 PIPE_CONF_CHECK_X(dpll_hw_state
.mg_pll_bias
);
12383 PIPE_CONF_CHECK_X(dpll_hw_state
.mg_pll_tdc_coldst_bias
);
12385 PIPE_CONF_CHECK_X(dsi_pll
.ctrl
);
12386 PIPE_CONF_CHECK_X(dsi_pll
.div
);
12388 if (IS_G4X(dev_priv
) || INTEL_GEN(dev_priv
) >= 5)
12389 PIPE_CONF_CHECK_I(pipe_bpp
);
12391 PIPE_CONF_CHECK_CLOCK_FUZZY(base
.adjusted_mode
.crtc_clock
);
12392 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock
);
12394 PIPE_CONF_CHECK_I(min_voltage_level
);
12396 PIPE_CONF_CHECK_X(infoframes
.enable
);
12397 PIPE_CONF_CHECK_X(infoframes
.gcp
);
12398 PIPE_CONF_CHECK_INFOFRAME(avi
);
12399 PIPE_CONF_CHECK_INFOFRAME(spd
);
12400 PIPE_CONF_CHECK_INFOFRAME(hdmi
);
12402 #undef PIPE_CONF_CHECK_X
12403 #undef PIPE_CONF_CHECK_I
12404 #undef PIPE_CONF_CHECK_BOOL
12405 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE
12406 #undef PIPE_CONF_CHECK_P
12407 #undef PIPE_CONF_CHECK_FLAGS
12408 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12409 #undef PIPE_CONF_QUIRK
12414 static void intel_pipe_config_sanity_check(struct drm_i915_private
*dev_priv
,
12415 const struct intel_crtc_state
*pipe_config
)
12417 if (pipe_config
->has_pch_encoder
) {
12418 int fdi_dotclock
= intel_dotclock_calculate(intel_fdi_link_freq(dev_priv
, pipe_config
),
12419 &pipe_config
->fdi_m_n
);
12420 int dotclock
= pipe_config
->base
.adjusted_mode
.crtc_clock
;
12423 * FDI already provided one idea for the dotclock.
12424 * Yell if the encoder disagrees.
12426 WARN(!intel_fuzzy_clock_check(fdi_dotclock
, dotclock
),
12427 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12428 fdi_dotclock
, dotclock
);
12432 static void verify_wm_state(struct drm_crtc
*crtc
,
12433 struct drm_crtc_state
*new_state
)
12435 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
12436 struct skl_hw_state
{
12437 struct skl_ddb_entry ddb_y
[I915_MAX_PLANES
];
12438 struct skl_ddb_entry ddb_uv
[I915_MAX_PLANES
];
12439 struct skl_ddb_allocation ddb
;
12440 struct skl_pipe_wm wm
;
12442 struct skl_ddb_allocation
*sw_ddb
;
12443 struct skl_pipe_wm
*sw_wm
;
12444 struct skl_ddb_entry
*hw_ddb_entry
, *sw_ddb_entry
;
12445 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
12446 const enum pipe pipe
= intel_crtc
->pipe
;
12447 int plane
, level
, max_level
= ilk_wm_max_level(dev_priv
);
12449 if (INTEL_GEN(dev_priv
) < 9 || !new_state
->active
)
12452 hw
= kzalloc(sizeof(*hw
), GFP_KERNEL
);
12456 skl_pipe_wm_get_hw_state(intel_crtc
, &hw
->wm
);
12457 sw_wm
= &to_intel_crtc_state(new_state
)->wm
.skl
.optimal
;
12459 skl_pipe_ddb_get_hw_state(intel_crtc
, hw
->ddb_y
, hw
->ddb_uv
);
12461 skl_ddb_get_hw_state(dev_priv
, &hw
->ddb
);
12462 sw_ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
12464 if (INTEL_GEN(dev_priv
) >= 11 &&
12465 hw
->ddb
.enabled_slices
!= sw_ddb
->enabled_slices
)
12466 DRM_ERROR("mismatch in DBUF Slices (expected %u, got %u)\n",
12467 sw_ddb
->enabled_slices
,
12468 hw
->ddb
.enabled_slices
);
12471 for_each_universal_plane(dev_priv
, pipe
, plane
) {
12472 struct skl_plane_wm
*hw_plane_wm
, *sw_plane_wm
;
12474 hw_plane_wm
= &hw
->wm
.planes
[plane
];
12475 sw_plane_wm
= &sw_wm
->planes
[plane
];
12478 for (level
= 0; level
<= max_level
; level
++) {
12479 if (skl_wm_level_equals(&hw_plane_wm
->wm
[level
],
12480 &sw_plane_wm
->wm
[level
]))
12483 DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
12484 pipe_name(pipe
), plane
+ 1, level
,
12485 sw_plane_wm
->wm
[level
].plane_en
,
12486 sw_plane_wm
->wm
[level
].plane_res_b
,
12487 sw_plane_wm
->wm
[level
].plane_res_l
,
12488 hw_plane_wm
->wm
[level
].plane_en
,
12489 hw_plane_wm
->wm
[level
].plane_res_b
,
12490 hw_plane_wm
->wm
[level
].plane_res_l
);
12493 if (!skl_wm_level_equals(&hw_plane_wm
->trans_wm
,
12494 &sw_plane_wm
->trans_wm
)) {
12495 DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
12496 pipe_name(pipe
), plane
+ 1,
12497 sw_plane_wm
->trans_wm
.plane_en
,
12498 sw_plane_wm
->trans_wm
.plane_res_b
,
12499 sw_plane_wm
->trans_wm
.plane_res_l
,
12500 hw_plane_wm
->trans_wm
.plane_en
,
12501 hw_plane_wm
->trans_wm
.plane_res_b
,
12502 hw_plane_wm
->trans_wm
.plane_res_l
);
12506 hw_ddb_entry
= &hw
->ddb_y
[plane
];
12507 sw_ddb_entry
= &to_intel_crtc_state(new_state
)->wm
.skl
.plane_ddb_y
[plane
];
12509 if (!skl_ddb_entry_equal(hw_ddb_entry
, sw_ddb_entry
)) {
12510 DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
12511 pipe_name(pipe
), plane
+ 1,
12512 sw_ddb_entry
->start
, sw_ddb_entry
->end
,
12513 hw_ddb_entry
->start
, hw_ddb_entry
->end
);
12519 * If the cursor plane isn't active, we may not have updated it's ddb
12520 * allocation. In that case since the ddb allocation will be updated
12521 * once the plane becomes visible, we can skip this check
12524 struct skl_plane_wm
*hw_plane_wm
, *sw_plane_wm
;
12526 hw_plane_wm
= &hw
->wm
.planes
[PLANE_CURSOR
];
12527 sw_plane_wm
= &sw_wm
->planes
[PLANE_CURSOR
];
12530 for (level
= 0; level
<= max_level
; level
++) {
12531 if (skl_wm_level_equals(&hw_plane_wm
->wm
[level
],
12532 &sw_plane_wm
->wm
[level
]))
12535 DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
12536 pipe_name(pipe
), level
,
12537 sw_plane_wm
->wm
[level
].plane_en
,
12538 sw_plane_wm
->wm
[level
].plane_res_b
,
12539 sw_plane_wm
->wm
[level
].plane_res_l
,
12540 hw_plane_wm
->wm
[level
].plane_en
,
12541 hw_plane_wm
->wm
[level
].plane_res_b
,
12542 hw_plane_wm
->wm
[level
].plane_res_l
);
12545 if (!skl_wm_level_equals(&hw_plane_wm
->trans_wm
,
12546 &sw_plane_wm
->trans_wm
)) {
12547 DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
12549 sw_plane_wm
->trans_wm
.plane_en
,
12550 sw_plane_wm
->trans_wm
.plane_res_b
,
12551 sw_plane_wm
->trans_wm
.plane_res_l
,
12552 hw_plane_wm
->trans_wm
.plane_en
,
12553 hw_plane_wm
->trans_wm
.plane_res_b
,
12554 hw_plane_wm
->trans_wm
.plane_res_l
);
12558 hw_ddb_entry
= &hw
->ddb_y
[PLANE_CURSOR
];
12559 sw_ddb_entry
= &to_intel_crtc_state(new_state
)->wm
.skl
.plane_ddb_y
[PLANE_CURSOR
];
12561 if (!skl_ddb_entry_equal(hw_ddb_entry
, sw_ddb_entry
)) {
12562 DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
12564 sw_ddb_entry
->start
, sw_ddb_entry
->end
,
12565 hw_ddb_entry
->start
, hw_ddb_entry
->end
);
12573 verify_connector_state(struct drm_device
*dev
,
12574 struct drm_atomic_state
*state
,
12575 struct drm_crtc
*crtc
)
12577 struct drm_connector
*connector
;
12578 struct drm_connector_state
*new_conn_state
;
12581 for_each_new_connector_in_state(state
, connector
, new_conn_state
, i
) {
12582 struct drm_encoder
*encoder
= connector
->encoder
;
12583 struct drm_crtc_state
*crtc_state
= NULL
;
12585 if (new_conn_state
->crtc
!= crtc
)
12589 crtc_state
= drm_atomic_get_new_crtc_state(state
, new_conn_state
->crtc
);
12591 intel_connector_verify_state(crtc_state
, new_conn_state
);
12593 I915_STATE_WARN(new_conn_state
->best_encoder
!= encoder
,
12594 "connector's atomic encoder doesn't match legacy encoder\n");
12599 verify_encoder_state(struct drm_device
*dev
, struct drm_atomic_state
*state
)
12601 struct intel_encoder
*encoder
;
12602 struct drm_connector
*connector
;
12603 struct drm_connector_state
*old_conn_state
, *new_conn_state
;
12606 for_each_intel_encoder(dev
, encoder
) {
12607 bool enabled
= false, found
= false;
12610 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12611 encoder
->base
.base
.id
,
12612 encoder
->base
.name
);
12614 for_each_oldnew_connector_in_state(state
, connector
, old_conn_state
,
12615 new_conn_state
, i
) {
12616 if (old_conn_state
->best_encoder
== &encoder
->base
)
12619 if (new_conn_state
->best_encoder
!= &encoder
->base
)
12621 found
= enabled
= true;
12623 I915_STATE_WARN(new_conn_state
->crtc
!=
12624 encoder
->base
.crtc
,
12625 "connector's crtc doesn't match encoder crtc\n");
12631 I915_STATE_WARN(!!encoder
->base
.crtc
!= enabled
,
12632 "encoder's enabled state mismatch "
12633 "(expected %i, found %i)\n",
12634 !!encoder
->base
.crtc
, enabled
);
12636 if (!encoder
->base
.crtc
) {
12639 active
= encoder
->get_hw_state(encoder
, &pipe
);
12640 I915_STATE_WARN(active
,
12641 "encoder detached but still enabled on pipe %c.\n",
12648 verify_crtc_state(struct drm_crtc
*crtc
,
12649 struct drm_crtc_state
*old_crtc_state
,
12650 struct drm_crtc_state
*new_crtc_state
)
12652 struct drm_device
*dev
= crtc
->dev
;
12653 struct drm_i915_private
*dev_priv
= to_i915(dev
);
12654 struct intel_encoder
*encoder
;
12655 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
12656 struct intel_crtc_state
*pipe_config
, *sw_config
;
12657 struct drm_atomic_state
*old_state
;
12660 old_state
= old_crtc_state
->state
;
12661 __drm_atomic_helper_crtc_destroy_state(old_crtc_state
);
12662 pipe_config
= to_intel_crtc_state(old_crtc_state
);
12663 memset(pipe_config
, 0, sizeof(*pipe_config
));
12664 pipe_config
->base
.crtc
= crtc
;
12665 pipe_config
->base
.state
= old_state
;
12667 DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc
->base
.id
, crtc
->name
);
12669 active
= dev_priv
->display
.get_pipe_config(intel_crtc
, pipe_config
);
12671 /* we keep both pipes enabled on 830 */
12672 if (IS_I830(dev_priv
))
12673 active
= new_crtc_state
->active
;
12675 I915_STATE_WARN(new_crtc_state
->active
!= active
,
12676 "crtc active state doesn't match with hw state "
12677 "(expected %i, found %i)\n", new_crtc_state
->active
, active
);
12679 I915_STATE_WARN(intel_crtc
->active
!= new_crtc_state
->active
,
12680 "transitional active state does not match atomic hw state "
12681 "(expected %i, found %i)\n", new_crtc_state
->active
, intel_crtc
->active
);
12683 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
12686 active
= encoder
->get_hw_state(encoder
, &pipe
);
12687 I915_STATE_WARN(active
!= new_crtc_state
->active
,
12688 "[ENCODER:%i] active %i with crtc active %i\n",
12689 encoder
->base
.base
.id
, active
, new_crtc_state
->active
);
12691 I915_STATE_WARN(active
&& intel_crtc
->pipe
!= pipe
,
12692 "Encoder connected to wrong pipe %c\n",
12696 encoder
->get_config(encoder
, pipe_config
);
12699 intel_crtc_compute_pixel_rate(pipe_config
);
12701 if (!new_crtc_state
->active
)
12704 intel_pipe_config_sanity_check(dev_priv
, pipe_config
);
12706 sw_config
= to_intel_crtc_state(new_crtc_state
);
12707 if (!intel_pipe_config_compare(dev_priv
, sw_config
,
12708 pipe_config
, false)) {
12709 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12710 intel_dump_pipe_config(intel_crtc
, pipe_config
,
12712 intel_dump_pipe_config(intel_crtc
, sw_config
,
12718 intel_verify_planes(struct intel_atomic_state
*state
)
12720 struct intel_plane
*plane
;
12721 const struct intel_plane_state
*plane_state
;
12724 for_each_new_intel_plane_in_state(state
, plane
,
12726 assert_plane(plane
, plane_state
->slave
||
12727 plane_state
->base
.visible
);
12731 verify_single_dpll_state(struct drm_i915_private
*dev_priv
,
12732 struct intel_shared_dpll
*pll
,
12733 struct drm_crtc
*crtc
,
12734 struct drm_crtc_state
*new_state
)
12736 struct intel_dpll_hw_state dpll_hw_state
;
12737 unsigned int crtc_mask
;
12740 memset(&dpll_hw_state
, 0, sizeof(dpll_hw_state
));
12742 DRM_DEBUG_KMS("%s\n", pll
->info
->name
);
12744 active
= pll
->info
->funcs
->get_hw_state(dev_priv
, pll
, &dpll_hw_state
);
12746 if (!(pll
->info
->flags
& INTEL_DPLL_ALWAYS_ON
)) {
12747 I915_STATE_WARN(!pll
->on
&& pll
->active_mask
,
12748 "pll in active use but not on in sw tracking\n");
12749 I915_STATE_WARN(pll
->on
&& !pll
->active_mask
,
12750 "pll is on but not used by any active crtc\n");
12751 I915_STATE_WARN(pll
->on
!= active
,
12752 "pll on state mismatch (expected %i, found %i)\n",
12757 I915_STATE_WARN(pll
->active_mask
& ~pll
->state
.crtc_mask
,
12758 "more active pll users than references: %x vs %x\n",
12759 pll
->active_mask
, pll
->state
.crtc_mask
);
12764 crtc_mask
= drm_crtc_mask(crtc
);
12766 if (new_state
->active
)
12767 I915_STATE_WARN(!(pll
->active_mask
& crtc_mask
),
12768 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
12769 pipe_name(drm_crtc_index(crtc
)), pll
->active_mask
);
12771 I915_STATE_WARN(pll
->active_mask
& crtc_mask
,
12772 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
12773 pipe_name(drm_crtc_index(crtc
)), pll
->active_mask
);
12775 I915_STATE_WARN(!(pll
->state
.crtc_mask
& crtc_mask
),
12776 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
12777 crtc_mask
, pll
->state
.crtc_mask
);
12779 I915_STATE_WARN(pll
->on
&& memcmp(&pll
->state
.hw_state
,
12781 sizeof(dpll_hw_state
)),
12782 "pll hw state mismatch\n");
12786 verify_shared_dpll_state(struct drm_device
*dev
, struct drm_crtc
*crtc
,
12787 struct drm_crtc_state
*old_crtc_state
,
12788 struct drm_crtc_state
*new_crtc_state
)
12790 struct drm_i915_private
*dev_priv
= to_i915(dev
);
12791 struct intel_crtc_state
*old_state
= to_intel_crtc_state(old_crtc_state
);
12792 struct intel_crtc_state
*new_state
= to_intel_crtc_state(new_crtc_state
);
12794 if (new_state
->shared_dpll
)
12795 verify_single_dpll_state(dev_priv
, new_state
->shared_dpll
, crtc
, new_crtc_state
);
12797 if (old_state
->shared_dpll
&&
12798 old_state
->shared_dpll
!= new_state
->shared_dpll
) {
12799 unsigned int crtc_mask
= drm_crtc_mask(crtc
);
12800 struct intel_shared_dpll
*pll
= old_state
->shared_dpll
;
12802 I915_STATE_WARN(pll
->active_mask
& crtc_mask
,
12803 "pll active mismatch (didn't expect pipe %c in active mask)\n",
12804 pipe_name(drm_crtc_index(crtc
)));
12805 I915_STATE_WARN(pll
->state
.crtc_mask
& crtc_mask
,
12806 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
12807 pipe_name(drm_crtc_index(crtc
)));
12812 intel_modeset_verify_crtc(struct drm_crtc
*crtc
,
12813 struct drm_atomic_state
*state
,
12814 struct drm_crtc_state
*old_state
,
12815 struct drm_crtc_state
*new_state
)
12817 if (!needs_modeset(new_state
) &&
12818 !to_intel_crtc_state(new_state
)->update_pipe
)
12821 verify_wm_state(crtc
, new_state
);
12822 verify_connector_state(crtc
->dev
, state
, crtc
);
12823 verify_crtc_state(crtc
, old_state
, new_state
);
12824 verify_shared_dpll_state(crtc
->dev
, crtc
, old_state
, new_state
);
12828 verify_disabled_dpll_state(struct drm_device
*dev
)
12830 struct drm_i915_private
*dev_priv
= to_i915(dev
);
12833 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++)
12834 verify_single_dpll_state(dev_priv
, &dev_priv
->shared_dplls
[i
], NULL
, NULL
);
12838 intel_modeset_verify_disabled(struct drm_device
*dev
,
12839 struct drm_atomic_state
*state
)
12841 verify_encoder_state(dev
, state
);
12842 verify_connector_state(dev
, state
, NULL
);
12843 verify_disabled_dpll_state(dev
);
12846 static void update_scanline_offset(const struct intel_crtc_state
*crtc_state
)
12848 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
12849 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
12852 * The scanline counter increments at the leading edge of hsync.
12854 * On most platforms it starts counting from vtotal-1 on the
12855 * first active line. That means the scanline counter value is
12856 * always one less than what we would expect. Ie. just after
12857 * start of vblank, which also occurs at start of hsync (on the
12858 * last active line), the scanline counter will read vblank_start-1.
12860 * On gen2 the scanline counter starts counting from 1 instead
12861 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12862 * to keep the value positive), instead of adding one.
12864 * On HSW+ the behaviour of the scanline counter depends on the output
12865 * type. For DP ports it behaves like most other platforms, but on HDMI
12866 * there's an extra 1 line difference. So we need to add two instead of
12867 * one to the value.
12869 * On VLV/CHV DSI the scanline counter would appear to increment
12870 * approx. 1/3 of a scanline before start of vblank. Unfortunately
12871 * that means we can't tell whether we're in vblank or not while
12872 * we're on that particular line. We must still set scanline_offset
12873 * to 1 so that the vblank timestamps come out correct when we query
12874 * the scanline counter from within the vblank interrupt handler.
12875 * However if queried just before the start of vblank we'll get an
12876 * answer that's slightly in the future.
12878 if (IS_GEN(dev_priv
, 2)) {
12879 const struct drm_display_mode
*adjusted_mode
= &crtc_state
->base
.adjusted_mode
;
12882 vtotal
= adjusted_mode
->crtc_vtotal
;
12883 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
12886 crtc
->scanline_offset
= vtotal
- 1;
12887 } else if (HAS_DDI(dev_priv
) &&
12888 intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_HDMI
)) {
12889 crtc
->scanline_offset
= 2;
12891 crtc
->scanline_offset
= 1;
12894 static void intel_modeset_clear_plls(struct drm_atomic_state
*state
)
12896 struct drm_device
*dev
= state
->dev
;
12897 struct drm_i915_private
*dev_priv
= to_i915(dev
);
12898 struct drm_crtc
*crtc
;
12899 struct drm_crtc_state
*old_crtc_state
, *new_crtc_state
;
12902 if (!dev_priv
->display
.crtc_compute_clock
)
12905 for_each_oldnew_crtc_in_state(state
, crtc
, old_crtc_state
, new_crtc_state
, i
) {
12906 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
12907 struct intel_shared_dpll
*old_dpll
=
12908 to_intel_crtc_state(old_crtc_state
)->shared_dpll
;
12910 if (!needs_modeset(new_crtc_state
))
12913 to_intel_crtc_state(new_crtc_state
)->shared_dpll
= NULL
;
12918 intel_release_shared_dpll(old_dpll
, intel_crtc
, state
);
12923 * This implements the workaround described in the "notes" section of the mode
12924 * set sequence documentation. When going from no pipes or single pipe to
12925 * multiple pipes, and planes are enabled after the pipe, we need to wait at
12926 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12928 static int haswell_mode_set_planes_workaround(struct drm_atomic_state
*state
)
12930 struct drm_crtc_state
*crtc_state
;
12931 struct intel_crtc
*intel_crtc
;
12932 struct drm_crtc
*crtc
;
12933 struct intel_crtc_state
*first_crtc_state
= NULL
;
12934 struct intel_crtc_state
*other_crtc_state
= NULL
;
12935 enum pipe first_pipe
= INVALID_PIPE
, enabled_pipe
= INVALID_PIPE
;
12938 /* look at all crtc's that are going to be enabled in during modeset */
12939 for_each_new_crtc_in_state(state
, crtc
, crtc_state
, i
) {
12940 intel_crtc
= to_intel_crtc(crtc
);
12942 if (!crtc_state
->active
|| !needs_modeset(crtc_state
))
12945 if (first_crtc_state
) {
12946 other_crtc_state
= to_intel_crtc_state(crtc_state
);
12949 first_crtc_state
= to_intel_crtc_state(crtc_state
);
12950 first_pipe
= intel_crtc
->pipe
;
12954 /* No workaround needed? */
12955 if (!first_crtc_state
)
12958 /* w/a possibly needed, check how many crtc's are already enabled. */
12959 for_each_intel_crtc(state
->dev
, intel_crtc
) {
12960 struct intel_crtc_state
*pipe_config
;
12962 pipe_config
= intel_atomic_get_crtc_state(state
, intel_crtc
);
12963 if (IS_ERR(pipe_config
))
12964 return PTR_ERR(pipe_config
);
12966 pipe_config
->hsw_workaround_pipe
= INVALID_PIPE
;
12968 if (!pipe_config
->base
.active
||
12969 needs_modeset(&pipe_config
->base
))
12972 /* 2 or more enabled crtcs means no need for w/a */
12973 if (enabled_pipe
!= INVALID_PIPE
)
12976 enabled_pipe
= intel_crtc
->pipe
;
12979 if (enabled_pipe
!= INVALID_PIPE
)
12980 first_crtc_state
->hsw_workaround_pipe
= enabled_pipe
;
12981 else if (other_crtc_state
)
12982 other_crtc_state
->hsw_workaround_pipe
= first_pipe
;
12987 static int intel_lock_all_pipes(struct drm_atomic_state
*state
)
12989 struct drm_crtc
*crtc
;
12991 /* Add all pipes to the state */
12992 for_each_crtc(state
->dev
, crtc
) {
12993 struct drm_crtc_state
*crtc_state
;
12995 crtc_state
= drm_atomic_get_crtc_state(state
, crtc
);
12996 if (IS_ERR(crtc_state
))
12997 return PTR_ERR(crtc_state
);
13003 static int intel_modeset_all_pipes(struct drm_atomic_state
*state
)
13005 struct drm_crtc
*crtc
;
13008 * Add all pipes to the state, and force
13009 * a modeset on all the active ones.
13011 for_each_crtc(state
->dev
, crtc
) {
13012 struct drm_crtc_state
*crtc_state
;
13015 crtc_state
= drm_atomic_get_crtc_state(state
, crtc
);
13016 if (IS_ERR(crtc_state
))
13017 return PTR_ERR(crtc_state
);
13019 if (!crtc_state
->active
|| needs_modeset(crtc_state
))
13022 crtc_state
->mode_changed
= true;
13024 ret
= drm_atomic_add_affected_connectors(state
, crtc
);
13028 ret
= drm_atomic_add_affected_planes(state
, crtc
);
13036 static int intel_modeset_checks(struct drm_atomic_state
*state
)
13038 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
13039 struct drm_i915_private
*dev_priv
= to_i915(state
->dev
);
13040 struct drm_crtc
*crtc
;
13041 struct drm_crtc_state
*old_crtc_state
, *new_crtc_state
;
13044 if (!check_digital_port_conflicts(state
)) {
13045 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13049 /* keep the current setting */
13050 if (!intel_state
->cdclk
.force_min_cdclk_changed
)
13051 intel_state
->cdclk
.force_min_cdclk
=
13052 dev_priv
->cdclk
.force_min_cdclk
;
13054 intel_state
->modeset
= true;
13055 intel_state
->active_crtcs
= dev_priv
->active_crtcs
;
13056 intel_state
->cdclk
.logical
= dev_priv
->cdclk
.logical
;
13057 intel_state
->cdclk
.actual
= dev_priv
->cdclk
.actual
;
13058 intel_state
->cdclk
.pipe
= INVALID_PIPE
;
13060 for_each_oldnew_crtc_in_state(state
, crtc
, old_crtc_state
, new_crtc_state
, i
) {
13061 if (new_crtc_state
->active
)
13062 intel_state
->active_crtcs
|= 1 << i
;
13064 intel_state
->active_crtcs
&= ~(1 << i
);
13066 if (old_crtc_state
->active
!= new_crtc_state
->active
)
13067 intel_state
->active_pipe_changes
|= drm_crtc_mask(crtc
);
13071 * See if the config requires any additional preparation, e.g.
13072 * to adjust global state with pipes off. We need to do this
13073 * here so we can get the modeset_pipe updated config for the new
13074 * mode set on this crtc. For other crtcs we need to use the
13075 * adjusted_mode bits in the crtc directly.
13077 if (dev_priv
->display
.modeset_calc_cdclk
) {
13080 ret
= dev_priv
->display
.modeset_calc_cdclk(state
);
13085 * Writes to dev_priv->cdclk.logical must protected by
13086 * holding all the crtc locks, even if we don't end up
13087 * touching the hardware
13089 if (intel_cdclk_changed(&dev_priv
->cdclk
.logical
,
13090 &intel_state
->cdclk
.logical
)) {
13091 ret
= intel_lock_all_pipes(state
);
13096 if (is_power_of_2(intel_state
->active_crtcs
)) {
13097 struct drm_crtc
*crtc
;
13098 struct drm_crtc_state
*crtc_state
;
13100 pipe
= ilog2(intel_state
->active_crtcs
);
13101 crtc
= &intel_get_crtc_for_pipe(dev_priv
, pipe
)->base
;
13102 crtc_state
= drm_atomic_get_new_crtc_state(state
, crtc
);
13103 if (crtc_state
&& needs_modeset(crtc_state
))
13104 pipe
= INVALID_PIPE
;
13106 pipe
= INVALID_PIPE
;
13109 /* All pipes must be switched off while we change the cdclk. */
13110 if (pipe
!= INVALID_PIPE
&&
13111 intel_cdclk_needs_cd2x_update(dev_priv
,
13112 &dev_priv
->cdclk
.actual
,
13113 &intel_state
->cdclk
.actual
)) {
13114 ret
= intel_lock_all_pipes(state
);
13118 intel_state
->cdclk
.pipe
= pipe
;
13119 } else if (intel_cdclk_needs_modeset(&dev_priv
->cdclk
.actual
,
13120 &intel_state
->cdclk
.actual
)) {
13121 ret
= intel_modeset_all_pipes(state
);
13125 intel_state
->cdclk
.pipe
= INVALID_PIPE
;
13128 DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n",
13129 intel_state
->cdclk
.logical
.cdclk
,
13130 intel_state
->cdclk
.actual
.cdclk
);
13131 DRM_DEBUG_KMS("New voltage level calculated to be logical %u, actual %u\n",
13132 intel_state
->cdclk
.logical
.voltage_level
,
13133 intel_state
->cdclk
.actual
.voltage_level
);
13136 intel_modeset_clear_plls(state
);
13138 if (IS_HASWELL(dev_priv
))
13139 return haswell_mode_set_planes_workaround(state
);
13145 * Handle calculation of various watermark data at the end of the atomic check
13146 * phase. The code here should be run after the per-crtc and per-plane 'check'
13147 * handlers to ensure that all derived state has been updated.
13149 static int calc_watermark_data(struct intel_atomic_state
*state
)
13151 struct drm_device
*dev
= state
->base
.dev
;
13152 struct drm_i915_private
*dev_priv
= to_i915(dev
);
13154 /* Is there platform-specific watermark information to calculate? */
13155 if (dev_priv
->display
.compute_global_watermarks
)
13156 return dev_priv
->display
.compute_global_watermarks(state
);
13162 * intel_atomic_check - validate state object
13164 * @state: state to validate
13166 static int intel_atomic_check(struct drm_device
*dev
,
13167 struct drm_atomic_state
*state
)
13169 struct drm_i915_private
*dev_priv
= to_i915(dev
);
13170 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
13171 struct drm_crtc
*crtc
;
13172 struct drm_crtc_state
*old_crtc_state
, *crtc_state
;
13174 bool any_ms
= intel_state
->cdclk
.force_min_cdclk_changed
;
13176 /* Catch I915_MODE_FLAG_INHERITED */
13177 for_each_oldnew_crtc_in_state(state
, crtc
, old_crtc_state
,
13179 if (crtc_state
->mode
.private_flags
!=
13180 old_crtc_state
->mode
.private_flags
)
13181 crtc_state
->mode_changed
= true;
13184 ret
= drm_atomic_helper_check_modeset(dev
, state
);
13188 for_each_oldnew_crtc_in_state(state
, crtc
, old_crtc_state
, crtc_state
, i
) {
13189 struct intel_crtc_state
*pipe_config
=
13190 to_intel_crtc_state(crtc_state
);
13192 if (!needs_modeset(crtc_state
))
13195 if (!crtc_state
->enable
) {
13200 ret
= intel_modeset_pipe_config(crtc
, pipe_config
);
13201 if (ret
== -EDEADLK
)
13204 intel_dump_pipe_config(to_intel_crtc(crtc
),
13205 pipe_config
, "[failed]");
13209 if (intel_pipe_config_compare(dev_priv
,
13210 to_intel_crtc_state(old_crtc_state
),
13211 pipe_config
, true)) {
13212 crtc_state
->mode_changed
= false;
13213 pipe_config
->update_pipe
= true;
13216 if (needs_modeset(crtc_state
))
13219 intel_dump_pipe_config(to_intel_crtc(crtc
), pipe_config
,
13220 needs_modeset(crtc_state
) ?
13221 "[modeset]" : "[fastset]");
13224 ret
= drm_dp_mst_atomic_check(state
);
13229 ret
= intel_modeset_checks(state
);
13234 intel_state
->cdclk
.logical
= dev_priv
->cdclk
.logical
;
13237 ret
= icl_add_linked_planes(intel_state
);
13241 ret
= drm_atomic_helper_check_planes(dev
, state
);
13245 intel_fbc_choose_crtc(dev_priv
, intel_state
);
13246 return calc_watermark_data(intel_state
);
13249 static int intel_atomic_prepare_commit(struct drm_device
*dev
,
13250 struct drm_atomic_state
*state
)
13252 return drm_atomic_helper_prepare_planes(dev
, state
);
13255 u32
intel_crtc_get_vblank_counter(struct intel_crtc
*crtc
)
13257 struct drm_device
*dev
= crtc
->base
.dev
;
13258 struct drm_vblank_crtc
*vblank
= &dev
->vblank
[drm_crtc_index(&crtc
->base
)];
13260 if (!vblank
->max_vblank_count
)
13261 return (u32
)drm_crtc_accurate_vblank_count(&crtc
->base
);
13263 return dev
->driver
->get_vblank_counter(dev
, crtc
->pipe
);
13266 static void intel_update_crtc(struct drm_crtc
*crtc
,
13267 struct drm_atomic_state
*state
,
13268 struct drm_crtc_state
*old_crtc_state
,
13269 struct drm_crtc_state
*new_crtc_state
)
13271 struct drm_device
*dev
= crtc
->dev
;
13272 struct drm_i915_private
*dev_priv
= to_i915(dev
);
13273 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
13274 struct intel_crtc_state
*pipe_config
= to_intel_crtc_state(new_crtc_state
);
13275 bool modeset
= needs_modeset(new_crtc_state
);
13276 struct intel_plane_state
*new_plane_state
=
13277 intel_atomic_get_new_plane_state(to_intel_atomic_state(state
),
13278 to_intel_plane(crtc
->primary
));
13281 update_scanline_offset(pipe_config
);
13282 dev_priv
->display
.crtc_enable(pipe_config
, state
);
13284 /* vblanks work again, re-enable pipe CRC. */
13285 intel_crtc_enable_pipe_crc(intel_crtc
);
13287 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state
),
13290 if (pipe_config
->update_pipe
)
13291 intel_encoders_update_pipe(crtc
, pipe_config
, state
);
13294 if (pipe_config
->update_pipe
&& !pipe_config
->enable_fbc
)
13295 intel_fbc_disable(intel_crtc
);
13296 else if (new_plane_state
)
13297 intel_fbc_enable(intel_crtc
, pipe_config
, new_plane_state
);
13299 intel_begin_crtc_commit(to_intel_atomic_state(state
), intel_crtc
);
13301 if (INTEL_GEN(dev_priv
) >= 9)
13302 skl_update_planes_on_crtc(to_intel_atomic_state(state
), intel_crtc
);
13304 i9xx_update_planes_on_crtc(to_intel_atomic_state(state
), intel_crtc
);
13306 intel_finish_crtc_commit(to_intel_atomic_state(state
), intel_crtc
);
13309 static void intel_update_crtcs(struct drm_atomic_state
*state
)
13311 struct drm_crtc
*crtc
;
13312 struct drm_crtc_state
*old_crtc_state
, *new_crtc_state
;
13315 for_each_oldnew_crtc_in_state(state
, crtc
, old_crtc_state
, new_crtc_state
, i
) {
13316 if (!new_crtc_state
->active
)
13319 intel_update_crtc(crtc
, state
, old_crtc_state
,
13324 static void skl_update_crtcs(struct drm_atomic_state
*state
)
13326 struct drm_i915_private
*dev_priv
= to_i915(state
->dev
);
13327 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
13328 struct drm_crtc
*crtc
;
13329 struct intel_crtc
*intel_crtc
;
13330 struct drm_crtc_state
*old_crtc_state
, *new_crtc_state
;
13331 struct intel_crtc_state
*cstate
;
13332 unsigned int updated
= 0;
13336 u8 hw_enabled_slices
= dev_priv
->wm
.skl_hw
.ddb
.enabled_slices
;
13337 u8 required_slices
= intel_state
->wm_results
.ddb
.enabled_slices
;
13338 struct skl_ddb_entry entries
[I915_MAX_PIPES
] = {};
13340 for_each_oldnew_crtc_in_state(state
, crtc
, old_crtc_state
, new_crtc_state
, i
)
13341 /* ignore allocations for crtc's that have been turned off. */
13342 if (new_crtc_state
->active
)
13343 entries
[i
] = to_intel_crtc_state(old_crtc_state
)->wm
.skl
.ddb
;
13345 /* If 2nd DBuf slice required, enable it here */
13346 if (INTEL_GEN(dev_priv
) >= 11 && required_slices
> hw_enabled_slices
)
13347 icl_dbuf_slices_update(dev_priv
, required_slices
);
13350 * Whenever the number of active pipes changes, we need to make sure we
13351 * update the pipes in the right order so that their ddb allocations
13352 * never overlap with eachother inbetween CRTC updates. Otherwise we'll
13353 * cause pipe underruns and other bad stuff.
13358 for_each_oldnew_crtc_in_state(state
, crtc
, old_crtc_state
, new_crtc_state
, i
) {
13359 bool vbl_wait
= false;
13360 unsigned int cmask
= drm_crtc_mask(crtc
);
13362 intel_crtc
= to_intel_crtc(crtc
);
13363 cstate
= to_intel_crtc_state(new_crtc_state
);
13364 pipe
= intel_crtc
->pipe
;
13366 if (updated
& cmask
|| !cstate
->base
.active
)
13369 if (skl_ddb_allocation_overlaps(&cstate
->wm
.skl
.ddb
,
13371 INTEL_INFO(dev_priv
)->num_pipes
, i
))
13375 entries
[i
] = cstate
->wm
.skl
.ddb
;
13378 * If this is an already active pipe, it's DDB changed,
13379 * and this isn't the last pipe that needs updating
13380 * then we need to wait for a vblank to pass for the
13381 * new ddb allocation to take effect.
13383 if (!skl_ddb_entry_equal(&cstate
->wm
.skl
.ddb
,
13384 &to_intel_crtc_state(old_crtc_state
)->wm
.skl
.ddb
) &&
13385 !new_crtc_state
->active_changed
&&
13386 intel_state
->wm_results
.dirty_pipes
!= updated
)
13389 intel_update_crtc(crtc
, state
, old_crtc_state
,
13393 intel_wait_for_vblank(dev_priv
, pipe
);
13397 } while (progress
);
13399 /* If 2nd DBuf slice is no more required disable it */
13400 if (INTEL_GEN(dev_priv
) >= 11 && required_slices
< hw_enabled_slices
)
13401 icl_dbuf_slices_update(dev_priv
, required_slices
);
13404 static void intel_atomic_helper_free_state(struct drm_i915_private
*dev_priv
)
13406 struct intel_atomic_state
*state
, *next
;
13407 struct llist_node
*freed
;
13409 freed
= llist_del_all(&dev_priv
->atomic_helper
.free_list
);
13410 llist_for_each_entry_safe(state
, next
, freed
, freed
)
13411 drm_atomic_state_put(&state
->base
);
13414 static void intel_atomic_helper_free_state_worker(struct work_struct
*work
)
13416 struct drm_i915_private
*dev_priv
=
13417 container_of(work
, typeof(*dev_priv
), atomic_helper
.free_work
);
13419 intel_atomic_helper_free_state(dev_priv
);
13422 static void intel_atomic_commit_fence_wait(struct intel_atomic_state
*intel_state
)
13424 struct wait_queue_entry wait_fence
, wait_reset
;
13425 struct drm_i915_private
*dev_priv
= to_i915(intel_state
->base
.dev
);
13427 init_wait_entry(&wait_fence
, 0);
13428 init_wait_entry(&wait_reset
, 0);
13430 prepare_to_wait(&intel_state
->commit_ready
.wait
,
13431 &wait_fence
, TASK_UNINTERRUPTIBLE
);
13432 prepare_to_wait(&dev_priv
->gpu_error
.wait_queue
,
13433 &wait_reset
, TASK_UNINTERRUPTIBLE
);
13436 if (i915_sw_fence_done(&intel_state
->commit_ready
)
13437 || test_bit(I915_RESET_MODESET
, &dev_priv
->gpu_error
.flags
))
13442 finish_wait(&intel_state
->commit_ready
.wait
, &wait_fence
);
13443 finish_wait(&dev_priv
->gpu_error
.wait_queue
, &wait_reset
);
13446 static void intel_atomic_cleanup_work(struct work_struct
*work
)
13448 struct drm_atomic_state
*state
=
13449 container_of(work
, struct drm_atomic_state
, commit_work
);
13450 struct drm_i915_private
*i915
= to_i915(state
->dev
);
13452 drm_atomic_helper_cleanup_planes(&i915
->drm
, state
);
13453 drm_atomic_helper_commit_cleanup_done(state
);
13454 drm_atomic_state_put(state
);
13456 intel_atomic_helper_free_state(i915
);
13459 static void intel_atomic_commit_tail(struct drm_atomic_state
*state
)
13461 struct drm_device
*dev
= state
->dev
;
13462 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
13463 struct drm_i915_private
*dev_priv
= to_i915(dev
);
13464 struct drm_crtc_state
*old_crtc_state
, *new_crtc_state
;
13465 struct intel_crtc_state
*new_intel_crtc_state
, *old_intel_crtc_state
;
13466 struct drm_crtc
*crtc
;
13467 struct intel_crtc
*intel_crtc
;
13468 u64 put_domains
[I915_MAX_PIPES
] = {};
13469 intel_wakeref_t wakeref
= 0;
13472 intel_atomic_commit_fence_wait(intel_state
);
13474 drm_atomic_helper_wait_for_dependencies(state
);
13476 if (intel_state
->modeset
)
13477 wakeref
= intel_display_power_get(dev_priv
, POWER_DOMAIN_MODESET
);
13479 for_each_oldnew_crtc_in_state(state
, crtc
, old_crtc_state
, new_crtc_state
, i
) {
13480 old_intel_crtc_state
= to_intel_crtc_state(old_crtc_state
);
13481 new_intel_crtc_state
= to_intel_crtc_state(new_crtc_state
);
13482 intel_crtc
= to_intel_crtc(crtc
);
13484 if (needs_modeset(new_crtc_state
) ||
13485 to_intel_crtc_state(new_crtc_state
)->update_pipe
) {
13487 put_domains
[intel_crtc
->pipe
] =
13488 modeset_get_crtc_power_domains(crtc
,
13489 new_intel_crtc_state
);
13492 if (!needs_modeset(new_crtc_state
))
13495 intel_pre_plane_update(old_intel_crtc_state
, new_intel_crtc_state
);
13497 if (old_crtc_state
->active
) {
13498 intel_crtc_disable_planes(intel_state
, intel_crtc
);
13501 * We need to disable pipe CRC before disabling the pipe,
13502 * or we race against vblank off.
13504 intel_crtc_disable_pipe_crc(intel_crtc
);
13506 dev_priv
->display
.crtc_disable(old_intel_crtc_state
, state
);
13507 intel_crtc
->active
= false;
13508 intel_fbc_disable(intel_crtc
);
13509 intel_disable_shared_dpll(old_intel_crtc_state
);
13512 * Underruns don't always raise
13513 * interrupts, so check manually.
13515 intel_check_cpu_fifo_underruns(dev_priv
);
13516 intel_check_pch_fifo_underruns(dev_priv
);
13518 /* FIXME unify this for all platforms */
13519 if (!new_crtc_state
->active
&&
13520 !HAS_GMCH(dev_priv
) &&
13521 dev_priv
->display
.initial_watermarks
)
13522 dev_priv
->display
.initial_watermarks(intel_state
,
13523 new_intel_crtc_state
);
13527 /* FIXME: Eventually get rid of our intel_crtc->config pointer */
13528 for_each_new_crtc_in_state(state
, crtc
, new_crtc_state
, i
)
13529 to_intel_crtc(crtc
)->config
= to_intel_crtc_state(new_crtc_state
);
13531 if (intel_state
->modeset
) {
13532 drm_atomic_helper_update_legacy_modeset_state(state
->dev
, state
);
13534 intel_set_cdclk_pre_plane_update(dev_priv
,
13535 &intel_state
->cdclk
.actual
,
13536 &dev_priv
->cdclk
.actual
,
13537 intel_state
->cdclk
.pipe
);
13540 * SKL workaround: bspec recommends we disable the SAGV when we
13541 * have more then one pipe enabled
13543 if (!intel_can_enable_sagv(state
))
13544 intel_disable_sagv(dev_priv
);
13546 intel_modeset_verify_disabled(dev
, state
);
13549 /* Complete the events for pipes that have now been disabled */
13550 for_each_new_crtc_in_state(state
, crtc
, new_crtc_state
, i
) {
13551 bool modeset
= needs_modeset(new_crtc_state
);
13553 /* Complete events for now disable pipes here. */
13554 if (modeset
&& !new_crtc_state
->active
&& new_crtc_state
->event
) {
13555 spin_lock_irq(&dev
->event_lock
);
13556 drm_crtc_send_vblank_event(crtc
, new_crtc_state
->event
);
13557 spin_unlock_irq(&dev
->event_lock
);
13559 new_crtc_state
->event
= NULL
;
13563 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13564 dev_priv
->display
.update_crtcs(state
);
13566 if (intel_state
->modeset
)
13567 intel_set_cdclk_post_plane_update(dev_priv
,
13568 &intel_state
->cdclk
.actual
,
13569 &dev_priv
->cdclk
.actual
,
13570 intel_state
->cdclk
.pipe
);
13572 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
13573 * already, but still need the state for the delayed optimization. To
13575 * - wrap the optimization/post_plane_update stuff into a per-crtc work.
13576 * - schedule that vblank worker _before_ calling hw_done
13577 * - at the start of commit_tail, cancel it _synchrously
13578 * - switch over to the vblank wait helper in the core after that since
13579 * we don't need out special handling any more.
13581 drm_atomic_helper_wait_for_flip_done(dev
, state
);
13583 for_each_new_crtc_in_state(state
, crtc
, new_crtc_state
, i
) {
13584 new_intel_crtc_state
= to_intel_crtc_state(new_crtc_state
);
13586 if (new_crtc_state
->active
&&
13587 !needs_modeset(new_crtc_state
) &&
13588 (new_intel_crtc_state
->base
.color_mgmt_changed
||
13589 new_intel_crtc_state
->update_pipe
))
13590 intel_color_load_luts(new_intel_crtc_state
);
13594 * Now that the vblank has passed, we can go ahead and program the
13595 * optimal watermarks on platforms that need two-step watermark
13598 * TODO: Move this (and other cleanup) to an async worker eventually.
13600 for_each_new_crtc_in_state(state
, crtc
, new_crtc_state
, i
) {
13601 new_intel_crtc_state
= to_intel_crtc_state(new_crtc_state
);
13603 if (dev_priv
->display
.optimize_watermarks
)
13604 dev_priv
->display
.optimize_watermarks(intel_state
,
13605 new_intel_crtc_state
);
13608 for_each_oldnew_crtc_in_state(state
, crtc
, old_crtc_state
, new_crtc_state
, i
) {
13609 intel_post_plane_update(to_intel_crtc_state(old_crtc_state
));
13611 if (put_domains
[i
])
13612 modeset_put_power_domains(dev_priv
, put_domains
[i
]);
13614 intel_modeset_verify_crtc(crtc
, state
, old_crtc_state
, new_crtc_state
);
13617 if (intel_state
->modeset
)
13618 intel_verify_planes(intel_state
);
13620 if (intel_state
->modeset
&& intel_can_enable_sagv(state
))
13621 intel_enable_sagv(dev_priv
);
13623 drm_atomic_helper_commit_hw_done(state
);
13625 if (intel_state
->modeset
) {
13626 /* As one of the primary mmio accessors, KMS has a high
13627 * likelihood of triggering bugs in unclaimed access. After we
13628 * finish modesetting, see if an error has been flagged, and if
13629 * so enable debugging for the next modeset - and hope we catch
13632 intel_uncore_arm_unclaimed_mmio_detection(&dev_priv
->uncore
);
13633 intel_display_power_put(dev_priv
, POWER_DOMAIN_MODESET
, wakeref
);
13637 * Defer the cleanup of the old state to a separate worker to not
13638 * impede the current task (userspace for blocking modesets) that
13639 * are executed inline. For out-of-line asynchronous modesets/flips,
13640 * deferring to a new worker seems overkill, but we would place a
13641 * schedule point (cond_resched()) here anyway to keep latencies
13644 INIT_WORK(&state
->commit_work
, intel_atomic_cleanup_work
);
13645 queue_work(system_highpri_wq
, &state
->commit_work
);
13648 static void intel_atomic_commit_work(struct work_struct
*work
)
13650 struct drm_atomic_state
*state
=
13651 container_of(work
, struct drm_atomic_state
, commit_work
);
13653 intel_atomic_commit_tail(state
);
13656 static int __i915_sw_fence_call
13657 intel_atomic_commit_ready(struct i915_sw_fence
*fence
,
13658 enum i915_sw_fence_notify notify
)
13660 struct intel_atomic_state
*state
=
13661 container_of(fence
, struct intel_atomic_state
, commit_ready
);
13664 case FENCE_COMPLETE
:
13665 /* we do blocking waits in the worker, nothing to do here */
13669 struct intel_atomic_helper
*helper
=
13670 &to_i915(state
->base
.dev
)->atomic_helper
;
13672 if (llist_add(&state
->freed
, &helper
->free_list
))
13673 schedule_work(&helper
->free_work
);
13678 return NOTIFY_DONE
;
13681 static void intel_atomic_track_fbs(struct drm_atomic_state
*state
)
13683 struct drm_plane_state
*old_plane_state
, *new_plane_state
;
13684 struct drm_plane
*plane
;
13687 for_each_oldnew_plane_in_state(state
, plane
, old_plane_state
, new_plane_state
, i
)
13688 i915_gem_track_fb(intel_fb_obj(old_plane_state
->fb
),
13689 intel_fb_obj(new_plane_state
->fb
),
13690 to_intel_plane(plane
)->frontbuffer_bit
);
13694 * intel_atomic_commit - commit validated state object
13696 * @state: the top-level driver state object
13697 * @nonblock: nonblocking commit
13699 * This function commits a top-level state object that has been validated
13700 * with drm_atomic_helper_check().
13703 * Zero for success or -errno.
13705 static int intel_atomic_commit(struct drm_device
*dev
,
13706 struct drm_atomic_state
*state
,
13709 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
13710 struct drm_i915_private
*dev_priv
= to_i915(dev
);
13713 drm_atomic_state_get(state
);
13714 i915_sw_fence_init(&intel_state
->commit_ready
,
13715 intel_atomic_commit_ready
);
13718 * The intel_legacy_cursor_update() fast path takes care
13719 * of avoiding the vblank waits for simple cursor
13720 * movement and flips. For cursor on/off and size changes,
13721 * we want to perform the vblank waits so that watermark
13722 * updates happen during the correct frames. Gen9+ have
13723 * double buffered watermarks and so shouldn't need this.
13725 * Unset state->legacy_cursor_update before the call to
13726 * drm_atomic_helper_setup_commit() because otherwise
13727 * drm_atomic_helper_wait_for_flip_done() is a noop and
13728 * we get FIFO underruns because we didn't wait
13731 * FIXME doing watermarks and fb cleanup from a vblank worker
13732 * (assuming we had any) would solve these problems.
13734 if (INTEL_GEN(dev_priv
) < 9 && state
->legacy_cursor_update
) {
13735 struct intel_crtc_state
*new_crtc_state
;
13736 struct intel_crtc
*crtc
;
13739 for_each_new_intel_crtc_in_state(intel_state
, crtc
, new_crtc_state
, i
)
13740 if (new_crtc_state
->wm
.need_postvbl_update
||
13741 new_crtc_state
->update_wm_post
)
13742 state
->legacy_cursor_update
= false;
13745 ret
= intel_atomic_prepare_commit(dev
, state
);
13747 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret
);
13748 i915_sw_fence_commit(&intel_state
->commit_ready
);
13752 ret
= drm_atomic_helper_setup_commit(state
, nonblock
);
13754 ret
= drm_atomic_helper_swap_state(state
, true);
13757 i915_sw_fence_commit(&intel_state
->commit_ready
);
13759 drm_atomic_helper_cleanup_planes(dev
, state
);
13762 dev_priv
->wm
.distrust_bios_wm
= false;
13763 intel_shared_dpll_swap_state(state
);
13764 intel_atomic_track_fbs(state
);
13766 if (intel_state
->modeset
) {
13767 memcpy(dev_priv
->min_cdclk
, intel_state
->min_cdclk
,
13768 sizeof(intel_state
->min_cdclk
));
13769 memcpy(dev_priv
->min_voltage_level
,
13770 intel_state
->min_voltage_level
,
13771 sizeof(intel_state
->min_voltage_level
));
13772 dev_priv
->active_crtcs
= intel_state
->active_crtcs
;
13773 dev_priv
->cdclk
.force_min_cdclk
=
13774 intel_state
->cdclk
.force_min_cdclk
;
13776 intel_cdclk_swap_state(intel_state
);
13779 drm_atomic_state_get(state
);
13780 INIT_WORK(&state
->commit_work
, intel_atomic_commit_work
);
13782 i915_sw_fence_commit(&intel_state
->commit_ready
);
13783 if (nonblock
&& intel_state
->modeset
) {
13784 queue_work(dev_priv
->modeset_wq
, &state
->commit_work
);
13785 } else if (nonblock
) {
13786 queue_work(system_unbound_wq
, &state
->commit_work
);
13788 if (intel_state
->modeset
)
13789 flush_workqueue(dev_priv
->modeset_wq
);
13790 intel_atomic_commit_tail(state
);
13796 static const struct drm_crtc_funcs intel_crtc_funcs
= {
13797 .gamma_set
= drm_atomic_helper_legacy_gamma_set
,
13798 .set_config
= drm_atomic_helper_set_config
,
13799 .destroy
= intel_crtc_destroy
,
13800 .page_flip
= drm_atomic_helper_page_flip
,
13801 .atomic_duplicate_state
= intel_crtc_duplicate_state
,
13802 .atomic_destroy_state
= intel_crtc_destroy_state
,
13803 .set_crc_source
= intel_crtc_set_crc_source
,
13804 .verify_crc_source
= intel_crtc_verify_crc_source
,
13805 .get_crc_sources
= intel_crtc_get_crc_sources
,
13808 struct wait_rps_boost
{
13809 struct wait_queue_entry wait
;
13811 struct drm_crtc
*crtc
;
13812 struct i915_request
*request
;
13815 static int do_rps_boost(struct wait_queue_entry
*_wait
,
13816 unsigned mode
, int sync
, void *key
)
13818 struct wait_rps_boost
*wait
= container_of(_wait
, typeof(*wait
), wait
);
13819 struct i915_request
*rq
= wait
->request
;
13822 * If we missed the vblank, but the request is already running it
13823 * is reasonable to assume that it will complete before the next
13824 * vblank without our intervention, so leave RPS alone.
13826 if (!i915_request_started(rq
))
13827 gen6_rps_boost(rq
);
13828 i915_request_put(rq
);
13830 drm_crtc_vblank_put(wait
->crtc
);
13832 list_del(&wait
->wait
.entry
);
13837 static void add_rps_boost_after_vblank(struct drm_crtc
*crtc
,
13838 struct dma_fence
*fence
)
13840 struct wait_rps_boost
*wait
;
13842 if (!dma_fence_is_i915(fence
))
13845 if (INTEL_GEN(to_i915(crtc
->dev
)) < 6)
13848 if (drm_crtc_vblank_get(crtc
))
13851 wait
= kmalloc(sizeof(*wait
), GFP_KERNEL
);
13853 drm_crtc_vblank_put(crtc
);
13857 wait
->request
= to_request(dma_fence_get(fence
));
13860 wait
->wait
.func
= do_rps_boost
;
13861 wait
->wait
.flags
= 0;
13863 add_wait_queue(drm_crtc_vblank_waitqueue(crtc
), &wait
->wait
);
13866 static int intel_plane_pin_fb(struct intel_plane_state
*plane_state
)
13868 struct intel_plane
*plane
= to_intel_plane(plane_state
->base
.plane
);
13869 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
13870 struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
13871 struct i915_vma
*vma
;
13873 if (plane
->id
== PLANE_CURSOR
&&
13874 INTEL_INFO(dev_priv
)->display
.cursor_needs_physical
) {
13875 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
13876 const int align
= intel_cursor_alignment(dev_priv
);
13879 err
= i915_gem_object_attach_phys(obj
, align
);
13884 vma
= intel_pin_and_fence_fb_obj(fb
,
13885 &plane_state
->view
,
13886 intel_plane_uses_fence(plane_state
),
13887 &plane_state
->flags
);
13889 return PTR_ERR(vma
);
13891 plane_state
->vma
= vma
;
13896 static void intel_plane_unpin_fb(struct intel_plane_state
*old_plane_state
)
13898 struct i915_vma
*vma
;
13900 vma
= fetch_and_zero(&old_plane_state
->vma
);
13902 intel_unpin_fb_vma(vma
, old_plane_state
->flags
);
13905 static void fb_obj_bump_render_priority(struct drm_i915_gem_object
*obj
)
13907 struct i915_sched_attr attr
= {
13908 .priority
= I915_PRIORITY_DISPLAY
,
13911 i915_gem_object_wait_priority(obj
, 0, &attr
);
13915 * intel_prepare_plane_fb - Prepare fb for usage on plane
13916 * @plane: drm plane to prepare for
13917 * @new_state: the plane state being prepared
13919 * Prepares a framebuffer for usage on a display plane. Generally this
13920 * involves pinning the underlying object and updating the frontbuffer tracking
13921 * bits. Some older platforms need special physical address handling for
13924 * Must be called with struct_mutex held.
13926 * Returns 0 on success, negative error code on failure.
13929 intel_prepare_plane_fb(struct drm_plane
*plane
,
13930 struct drm_plane_state
*new_state
)
13932 struct intel_atomic_state
*intel_state
=
13933 to_intel_atomic_state(new_state
->state
);
13934 struct drm_i915_private
*dev_priv
= to_i915(plane
->dev
);
13935 struct drm_framebuffer
*fb
= new_state
->fb
;
13936 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
13937 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(plane
->state
->fb
);
13941 struct drm_crtc_state
*crtc_state
=
13942 drm_atomic_get_new_crtc_state(new_state
->state
,
13943 plane
->state
->crtc
);
13945 /* Big Hammer, we also need to ensure that any pending
13946 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13947 * current scanout is retired before unpinning the old
13948 * framebuffer. Note that we rely on userspace rendering
13949 * into the buffer attached to the pipe they are waiting
13950 * on. If not, userspace generates a GPU hang with IPEHR
13951 * point to the MI_WAIT_FOR_EVENT.
13953 * This should only fail upon a hung GPU, in which case we
13954 * can safely continue.
13956 if (needs_modeset(crtc_state
)) {
13957 ret
= i915_sw_fence_await_reservation(&intel_state
->commit_ready
,
13958 old_obj
->resv
, NULL
,
13966 if (new_state
->fence
) { /* explicit fencing */
13967 ret
= i915_sw_fence_await_dma_fence(&intel_state
->commit_ready
,
13969 I915_FENCE_TIMEOUT
,
13978 ret
= i915_gem_object_pin_pages(obj
);
13982 ret
= mutex_lock_interruptible(&dev_priv
->drm
.struct_mutex
);
13984 i915_gem_object_unpin_pages(obj
);
13988 ret
= intel_plane_pin_fb(to_intel_plane_state(new_state
));
13990 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
13991 i915_gem_object_unpin_pages(obj
);
13995 fb_obj_bump_render_priority(obj
);
13996 intel_fb_obj_flush(obj
, ORIGIN_DIRTYFB
);
13998 if (!new_state
->fence
) { /* implicit fencing */
13999 struct dma_fence
*fence
;
14001 ret
= i915_sw_fence_await_reservation(&intel_state
->commit_ready
,
14003 false, I915_FENCE_TIMEOUT
,
14008 fence
= reservation_object_get_excl_rcu(obj
->resv
);
14010 add_rps_boost_after_vblank(new_state
->crtc
, fence
);
14011 dma_fence_put(fence
);
14014 add_rps_boost_after_vblank(new_state
->crtc
, new_state
->fence
);
14018 * We declare pageflips to be interactive and so merit a small bias
14019 * towards upclocking to deliver the frame on time. By only changing
14020 * the RPS thresholds to sample more regularly and aim for higher
14021 * clocks we can hopefully deliver low power workloads (like kodi)
14022 * that are not quite steady state without resorting to forcing
14023 * maximum clocks following a vblank miss (see do_rps_boost()).
14025 if (!intel_state
->rps_interactive
) {
14026 intel_rps_mark_interactive(dev_priv
, true);
14027 intel_state
->rps_interactive
= true;
14034 * intel_cleanup_plane_fb - Cleans up an fb after plane use
14035 * @plane: drm plane to clean up for
14036 * @old_state: the state from the previous modeset
14038 * Cleans up a framebuffer that has just been removed from a plane.
14040 * Must be called with struct_mutex held.
14043 intel_cleanup_plane_fb(struct drm_plane
*plane
,
14044 struct drm_plane_state
*old_state
)
14046 struct intel_atomic_state
*intel_state
=
14047 to_intel_atomic_state(old_state
->state
);
14048 struct drm_i915_private
*dev_priv
= to_i915(plane
->dev
);
14050 if (intel_state
->rps_interactive
) {
14051 intel_rps_mark_interactive(dev_priv
, false);
14052 intel_state
->rps_interactive
= false;
14055 /* Should only be called after a successful intel_prepare_plane_fb()! */
14056 mutex_lock(&dev_priv
->drm
.struct_mutex
);
14057 intel_plane_unpin_fb(to_intel_plane_state(old_state
));
14058 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
14062 skl_max_scale(const struct intel_crtc_state
*crtc_state
,
14065 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
14066 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
14067 int max_scale
, mult
;
14068 int crtc_clock
, max_dotclk
, tmpclk1
, tmpclk2
;
14070 if (!crtc_state
->base
.enable
)
14071 return DRM_PLANE_HELPER_NO_SCALING
;
14073 crtc_clock
= crtc_state
->base
.adjusted_mode
.crtc_clock
;
14074 max_dotclk
= to_intel_atomic_state(crtc_state
->base
.state
)->cdclk
.logical
.cdclk
;
14076 if (IS_GEMINILAKE(dev_priv
) || INTEL_GEN(dev_priv
) >= 10)
14079 if (WARN_ON_ONCE(!crtc_clock
|| max_dotclk
< crtc_clock
))
14080 return DRM_PLANE_HELPER_NO_SCALING
;
14083 * skl max scale is lower of:
14084 * close to 3 but not 3, -1 is for that purpose
14088 mult
= is_planar_yuv_format(pixel_format
) ? 2 : 3;
14089 tmpclk1
= (1 << 16) * mult
- 1;
14090 tmpclk2
= (1 << 8) * ((max_dotclk
<< 8) / crtc_clock
);
14091 max_scale
= min(tmpclk1
, tmpclk2
);
14096 static void intel_begin_crtc_commit(struct intel_atomic_state
*state
,
14097 struct intel_crtc
*crtc
)
14099 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
14100 struct intel_crtc_state
*old_crtc_state
=
14101 intel_atomic_get_old_crtc_state(state
, crtc
);
14102 struct intel_crtc_state
*new_crtc_state
=
14103 intel_atomic_get_new_crtc_state(state
, crtc
);
14104 bool modeset
= needs_modeset(&new_crtc_state
->base
);
14106 /* Perform vblank evasion around commit operation */
14107 intel_pipe_update_start(new_crtc_state
);
14112 if (new_crtc_state
->base
.color_mgmt_changed
||
14113 new_crtc_state
->update_pipe
)
14114 intel_color_commit(new_crtc_state
);
14116 if (new_crtc_state
->update_pipe
)
14117 intel_update_pipe_config(old_crtc_state
, new_crtc_state
);
14118 else if (INTEL_GEN(dev_priv
) >= 9)
14119 skl_detach_scalers(new_crtc_state
);
14122 if (dev_priv
->display
.atomic_update_watermarks
)
14123 dev_priv
->display
.atomic_update_watermarks(state
,
14127 void intel_crtc_arm_fifo_underrun(struct intel_crtc
*crtc
,
14128 struct intel_crtc_state
*crtc_state
)
14130 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
14132 if (!IS_GEN(dev_priv
, 2))
14133 intel_set_cpu_fifo_underrun_reporting(dev_priv
, crtc
->pipe
, true);
14135 if (crtc_state
->has_pch_encoder
) {
14136 enum pipe pch_transcoder
=
14137 intel_crtc_pch_transcoder(crtc
);
14139 intel_set_pch_fifo_underrun_reporting(dev_priv
, pch_transcoder
, true);
14143 static void intel_finish_crtc_commit(struct intel_atomic_state
*state
,
14144 struct intel_crtc
*crtc
)
14146 struct intel_crtc_state
*old_crtc_state
=
14147 intel_atomic_get_old_crtc_state(state
, crtc
);
14148 struct intel_crtc_state
*new_crtc_state
=
14149 intel_atomic_get_new_crtc_state(state
, crtc
);
14151 intel_pipe_update_end(new_crtc_state
);
14153 if (new_crtc_state
->update_pipe
&&
14154 !needs_modeset(&new_crtc_state
->base
) &&
14155 old_crtc_state
->base
.mode
.private_flags
& I915_MODE_FLAG_INHERITED
)
14156 intel_crtc_arm_fifo_underrun(crtc
, new_crtc_state
);
14160 * intel_plane_destroy - destroy a plane
14161 * @plane: plane to destroy
14163 * Common destruction function for all types of planes (primary, cursor,
14166 void intel_plane_destroy(struct drm_plane
*plane
)
14168 drm_plane_cleanup(plane
);
14169 kfree(to_intel_plane(plane
));
14172 static bool i8xx_plane_format_mod_supported(struct drm_plane
*_plane
,
14173 u32 format
, u64 modifier
)
14175 switch (modifier
) {
14176 case DRM_FORMAT_MOD_LINEAR
:
14177 case I915_FORMAT_MOD_X_TILED
:
14184 case DRM_FORMAT_C8
:
14185 case DRM_FORMAT_RGB565
:
14186 case DRM_FORMAT_XRGB1555
:
14187 case DRM_FORMAT_XRGB8888
:
14188 return modifier
== DRM_FORMAT_MOD_LINEAR
||
14189 modifier
== I915_FORMAT_MOD_X_TILED
;
14195 static bool i965_plane_format_mod_supported(struct drm_plane
*_plane
,
14196 u32 format
, u64 modifier
)
14198 switch (modifier
) {
14199 case DRM_FORMAT_MOD_LINEAR
:
14200 case I915_FORMAT_MOD_X_TILED
:
14207 case DRM_FORMAT_C8
:
14208 case DRM_FORMAT_RGB565
:
14209 case DRM_FORMAT_XRGB8888
:
14210 case DRM_FORMAT_XBGR8888
:
14211 case DRM_FORMAT_XRGB2101010
:
14212 case DRM_FORMAT_XBGR2101010
:
14213 return modifier
== DRM_FORMAT_MOD_LINEAR
||
14214 modifier
== I915_FORMAT_MOD_X_TILED
;
14220 static bool intel_cursor_format_mod_supported(struct drm_plane
*_plane
,
14221 u32 format
, u64 modifier
)
14223 return modifier
== DRM_FORMAT_MOD_LINEAR
&&
14224 format
== DRM_FORMAT_ARGB8888
;
14227 static const struct drm_plane_funcs i965_plane_funcs
= {
14228 .update_plane
= drm_atomic_helper_update_plane
,
14229 .disable_plane
= drm_atomic_helper_disable_plane
,
14230 .destroy
= intel_plane_destroy
,
14231 .atomic_get_property
= intel_plane_atomic_get_property
,
14232 .atomic_set_property
= intel_plane_atomic_set_property
,
14233 .atomic_duplicate_state
= intel_plane_duplicate_state
,
14234 .atomic_destroy_state
= intel_plane_destroy_state
,
14235 .format_mod_supported
= i965_plane_format_mod_supported
,
14238 static const struct drm_plane_funcs i8xx_plane_funcs
= {
14239 .update_plane
= drm_atomic_helper_update_plane
,
14240 .disable_plane
= drm_atomic_helper_disable_plane
,
14241 .destroy
= intel_plane_destroy
,
14242 .atomic_get_property
= intel_plane_atomic_get_property
,
14243 .atomic_set_property
= intel_plane_atomic_set_property
,
14244 .atomic_duplicate_state
= intel_plane_duplicate_state
,
14245 .atomic_destroy_state
= intel_plane_destroy_state
,
14246 .format_mod_supported
= i8xx_plane_format_mod_supported
,
14250 intel_legacy_cursor_update(struct drm_plane
*plane
,
14251 struct drm_crtc
*crtc
,
14252 struct drm_framebuffer
*fb
,
14253 int crtc_x
, int crtc_y
,
14254 unsigned int crtc_w
, unsigned int crtc_h
,
14255 u32 src_x
, u32 src_y
,
14256 u32 src_w
, u32 src_h
,
14257 struct drm_modeset_acquire_ctx
*ctx
)
14259 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
14261 struct drm_plane_state
*old_plane_state
, *new_plane_state
;
14262 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
14263 struct drm_framebuffer
*old_fb
;
14264 struct intel_crtc_state
*crtc_state
=
14265 to_intel_crtc_state(crtc
->state
);
14266 struct intel_crtc_state
*new_crtc_state
;
14269 * When crtc is inactive or there is a modeset pending,
14270 * wait for it to complete in the slowpath
14272 if (!crtc_state
->base
.active
|| needs_modeset(&crtc_state
->base
) ||
14273 crtc_state
->update_pipe
)
14276 old_plane_state
= plane
->state
;
14278 * Don't do an async update if there is an outstanding commit modifying
14279 * the plane. This prevents our async update's changes from getting
14280 * overridden by a previous synchronous update's state.
14282 if (old_plane_state
->commit
&&
14283 !try_wait_for_completion(&old_plane_state
->commit
->hw_done
))
14287 * If any parameters change that may affect watermarks,
14288 * take the slowpath. Only changing fb or position should be
14291 if (old_plane_state
->crtc
!= crtc
||
14292 old_plane_state
->src_w
!= src_w
||
14293 old_plane_state
->src_h
!= src_h
||
14294 old_plane_state
->crtc_w
!= crtc_w
||
14295 old_plane_state
->crtc_h
!= crtc_h
||
14296 !old_plane_state
->fb
!= !fb
)
14299 new_plane_state
= intel_plane_duplicate_state(plane
);
14300 if (!new_plane_state
)
14303 new_crtc_state
= to_intel_crtc_state(intel_crtc_duplicate_state(crtc
));
14304 if (!new_crtc_state
) {
14309 drm_atomic_set_fb_for_plane(new_plane_state
, fb
);
14311 new_plane_state
->src_x
= src_x
;
14312 new_plane_state
->src_y
= src_y
;
14313 new_plane_state
->src_w
= src_w
;
14314 new_plane_state
->src_h
= src_h
;
14315 new_plane_state
->crtc_x
= crtc_x
;
14316 new_plane_state
->crtc_y
= crtc_y
;
14317 new_plane_state
->crtc_w
= crtc_w
;
14318 new_plane_state
->crtc_h
= crtc_h
;
14320 ret
= intel_plane_atomic_check_with_state(crtc_state
, new_crtc_state
,
14321 to_intel_plane_state(old_plane_state
),
14322 to_intel_plane_state(new_plane_state
));
14326 ret
= mutex_lock_interruptible(&dev_priv
->drm
.struct_mutex
);
14330 ret
= intel_plane_pin_fb(to_intel_plane_state(new_plane_state
));
14334 intel_fb_obj_flush(intel_fb_obj(fb
), ORIGIN_FLIP
);
14336 old_fb
= old_plane_state
->fb
;
14337 i915_gem_track_fb(intel_fb_obj(old_fb
), intel_fb_obj(fb
),
14338 intel_plane
->frontbuffer_bit
);
14340 /* Swap plane state */
14341 plane
->state
= new_plane_state
;
14344 * We cannot swap crtc_state as it may be in use by an atomic commit or
14345 * page flip that's running simultaneously. If we swap crtc_state and
14346 * destroy the old state, we will cause a use-after-free there.
14348 * Only update active_planes, which is needed for our internal
14349 * bookkeeping. Either value will do the right thing when updating
14350 * planes atomically. If the cursor was part of the atomic update then
14351 * we would have taken the slowpath.
14353 crtc_state
->active_planes
= new_crtc_state
->active_planes
;
14355 if (plane
->state
->visible
)
14356 intel_update_plane(intel_plane
, crtc_state
,
14357 to_intel_plane_state(plane
->state
));
14359 intel_disable_plane(intel_plane
, crtc_state
);
14361 intel_plane_unpin_fb(to_intel_plane_state(old_plane_state
));
14364 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
14366 if (new_crtc_state
)
14367 intel_crtc_destroy_state(crtc
, &new_crtc_state
->base
);
14369 intel_plane_destroy_state(plane
, new_plane_state
);
14371 intel_plane_destroy_state(plane
, old_plane_state
);
14375 return drm_atomic_helper_update_plane(plane
, crtc
, fb
,
14376 crtc_x
, crtc_y
, crtc_w
, crtc_h
,
14377 src_x
, src_y
, src_w
, src_h
, ctx
);
14380 static const struct drm_plane_funcs intel_cursor_plane_funcs
= {
14381 .update_plane
= intel_legacy_cursor_update
,
14382 .disable_plane
= drm_atomic_helper_disable_plane
,
14383 .destroy
= intel_plane_destroy
,
14384 .atomic_get_property
= intel_plane_atomic_get_property
,
14385 .atomic_set_property
= intel_plane_atomic_set_property
,
14386 .atomic_duplicate_state
= intel_plane_duplicate_state
,
14387 .atomic_destroy_state
= intel_plane_destroy_state
,
14388 .format_mod_supported
= intel_cursor_format_mod_supported
,
14391 static bool i9xx_plane_has_fbc(struct drm_i915_private
*dev_priv
,
14392 enum i9xx_plane_id i9xx_plane
)
14394 if (!HAS_FBC(dev_priv
))
14397 if (IS_BROADWELL(dev_priv
) || IS_HASWELL(dev_priv
))
14398 return i9xx_plane
== PLANE_A
; /* tied to pipe A */
14399 else if (IS_IVYBRIDGE(dev_priv
))
14400 return i9xx_plane
== PLANE_A
|| i9xx_plane
== PLANE_B
||
14401 i9xx_plane
== PLANE_C
;
14402 else if (INTEL_GEN(dev_priv
) >= 4)
14403 return i9xx_plane
== PLANE_A
|| i9xx_plane
== PLANE_B
;
14405 return i9xx_plane
== PLANE_A
;
14408 static struct intel_plane
*
14409 intel_primary_plane_create(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
14411 struct intel_plane
*plane
;
14412 const struct drm_plane_funcs
*plane_funcs
;
14413 unsigned int supported_rotations
;
14414 unsigned int possible_crtcs
;
14415 const u64
*modifiers
;
14416 const u32
*formats
;
14420 if (INTEL_GEN(dev_priv
) >= 9)
14421 return skl_universal_plane_create(dev_priv
, pipe
,
14424 plane
= intel_plane_alloc();
14428 plane
->pipe
= pipe
;
14430 * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
14431 * port is hooked to pipe B. Hence we want plane A feeding pipe B.
14433 if (HAS_FBC(dev_priv
) && INTEL_GEN(dev_priv
) < 4)
14434 plane
->i9xx_plane
= (enum i9xx_plane_id
) !pipe
;
14436 plane
->i9xx_plane
= (enum i9xx_plane_id
) pipe
;
14437 plane
->id
= PLANE_PRIMARY
;
14438 plane
->frontbuffer_bit
= INTEL_FRONTBUFFER(pipe
, plane
->id
);
14440 plane
->has_fbc
= i9xx_plane_has_fbc(dev_priv
, plane
->i9xx_plane
);
14441 if (plane
->has_fbc
) {
14442 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
14444 fbc
->possible_framebuffer_bits
|= plane
->frontbuffer_bit
;
14447 if (INTEL_GEN(dev_priv
) >= 4) {
14448 formats
= i965_primary_formats
;
14449 num_formats
= ARRAY_SIZE(i965_primary_formats
);
14450 modifiers
= i9xx_format_modifiers
;
14452 plane
->max_stride
= i9xx_plane_max_stride
;
14453 plane
->update_plane
= i9xx_update_plane
;
14454 plane
->disable_plane
= i9xx_disable_plane
;
14455 plane
->get_hw_state
= i9xx_plane_get_hw_state
;
14456 plane
->check_plane
= i9xx_plane_check
;
14458 plane_funcs
= &i965_plane_funcs
;
14460 formats
= i8xx_primary_formats
;
14461 num_formats
= ARRAY_SIZE(i8xx_primary_formats
);
14462 modifiers
= i9xx_format_modifiers
;
14464 plane
->max_stride
= i9xx_plane_max_stride
;
14465 plane
->update_plane
= i9xx_update_plane
;
14466 plane
->disable_plane
= i9xx_disable_plane
;
14467 plane
->get_hw_state
= i9xx_plane_get_hw_state
;
14468 plane
->check_plane
= i9xx_plane_check
;
14470 plane_funcs
= &i8xx_plane_funcs
;
14473 possible_crtcs
= BIT(pipe
);
14475 if (INTEL_GEN(dev_priv
) >= 5 || IS_G4X(dev_priv
))
14476 ret
= drm_universal_plane_init(&dev_priv
->drm
, &plane
->base
,
14477 possible_crtcs
, plane_funcs
,
14478 formats
, num_formats
, modifiers
,
14479 DRM_PLANE_TYPE_PRIMARY
,
14480 "primary %c", pipe_name(pipe
));
14482 ret
= drm_universal_plane_init(&dev_priv
->drm
, &plane
->base
,
14483 possible_crtcs
, plane_funcs
,
14484 formats
, num_formats
, modifiers
,
14485 DRM_PLANE_TYPE_PRIMARY
,
14487 plane_name(plane
->i9xx_plane
));
14491 if (IS_CHERRYVIEW(dev_priv
) && pipe
== PIPE_B
) {
14492 supported_rotations
=
14493 DRM_MODE_ROTATE_0
| DRM_MODE_ROTATE_180
|
14494 DRM_MODE_REFLECT_X
;
14495 } else if (INTEL_GEN(dev_priv
) >= 4) {
14496 supported_rotations
=
14497 DRM_MODE_ROTATE_0
| DRM_MODE_ROTATE_180
;
14499 supported_rotations
= DRM_MODE_ROTATE_0
;
14502 if (INTEL_GEN(dev_priv
) >= 4)
14503 drm_plane_create_rotation_property(&plane
->base
,
14505 supported_rotations
);
14507 drm_plane_helper_add(&plane
->base
, &intel_plane_helper_funcs
);
14512 intel_plane_free(plane
);
14514 return ERR_PTR(ret
);
14517 static struct intel_plane
*
14518 intel_cursor_plane_create(struct drm_i915_private
*dev_priv
,
14521 unsigned int possible_crtcs
;
14522 struct intel_plane
*cursor
;
14525 cursor
= intel_plane_alloc();
14526 if (IS_ERR(cursor
))
14529 cursor
->pipe
= pipe
;
14530 cursor
->i9xx_plane
= (enum i9xx_plane_id
) pipe
;
14531 cursor
->id
= PLANE_CURSOR
;
14532 cursor
->frontbuffer_bit
= INTEL_FRONTBUFFER(pipe
, cursor
->id
);
14534 if (IS_I845G(dev_priv
) || IS_I865G(dev_priv
)) {
14535 cursor
->max_stride
= i845_cursor_max_stride
;
14536 cursor
->update_plane
= i845_update_cursor
;
14537 cursor
->disable_plane
= i845_disable_cursor
;
14538 cursor
->get_hw_state
= i845_cursor_get_hw_state
;
14539 cursor
->check_plane
= i845_check_cursor
;
14541 cursor
->max_stride
= i9xx_cursor_max_stride
;
14542 cursor
->update_plane
= i9xx_update_cursor
;
14543 cursor
->disable_plane
= i9xx_disable_cursor
;
14544 cursor
->get_hw_state
= i9xx_cursor_get_hw_state
;
14545 cursor
->check_plane
= i9xx_check_cursor
;
14548 cursor
->cursor
.base
= ~0;
14549 cursor
->cursor
.cntl
= ~0;
14551 if (IS_I845G(dev_priv
) || IS_I865G(dev_priv
) || HAS_CUR_FBC(dev_priv
))
14552 cursor
->cursor
.size
= ~0;
14554 possible_crtcs
= BIT(pipe
);
14556 ret
= drm_universal_plane_init(&dev_priv
->drm
, &cursor
->base
,
14557 possible_crtcs
, &intel_cursor_plane_funcs
,
14558 intel_cursor_formats
,
14559 ARRAY_SIZE(intel_cursor_formats
),
14560 cursor_format_modifiers
,
14561 DRM_PLANE_TYPE_CURSOR
,
14562 "cursor %c", pipe_name(pipe
));
14566 if (INTEL_GEN(dev_priv
) >= 4)
14567 drm_plane_create_rotation_property(&cursor
->base
,
14569 DRM_MODE_ROTATE_0
|
14570 DRM_MODE_ROTATE_180
);
14572 drm_plane_helper_add(&cursor
->base
, &intel_plane_helper_funcs
);
14577 intel_plane_free(cursor
);
14579 return ERR_PTR(ret
);
14582 static void intel_crtc_init_scalers(struct intel_crtc
*crtc
,
14583 struct intel_crtc_state
*crtc_state
)
14585 struct intel_crtc_scaler_state
*scaler_state
=
14586 &crtc_state
->scaler_state
;
14587 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
14590 crtc
->num_scalers
= RUNTIME_INFO(dev_priv
)->num_scalers
[crtc
->pipe
];
14591 if (!crtc
->num_scalers
)
14594 for (i
= 0; i
< crtc
->num_scalers
; i
++) {
14595 struct intel_scaler
*scaler
= &scaler_state
->scalers
[i
];
14597 scaler
->in_use
= 0;
14601 scaler_state
->scaler_id
= -1;
14604 static int intel_crtc_init(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
14606 struct intel_crtc
*intel_crtc
;
14607 struct intel_crtc_state
*crtc_state
= NULL
;
14608 struct intel_plane
*primary
= NULL
;
14609 struct intel_plane
*cursor
= NULL
;
14612 intel_crtc
= kzalloc(sizeof(*intel_crtc
), GFP_KERNEL
);
14616 crtc_state
= kzalloc(sizeof(*crtc_state
), GFP_KERNEL
);
14621 intel_crtc
->config
= crtc_state
;
14622 intel_crtc
->base
.state
= &crtc_state
->base
;
14623 crtc_state
->base
.crtc
= &intel_crtc
->base
;
14625 primary
= intel_primary_plane_create(dev_priv
, pipe
);
14626 if (IS_ERR(primary
)) {
14627 ret
= PTR_ERR(primary
);
14630 intel_crtc
->plane_ids_mask
|= BIT(primary
->id
);
14632 for_each_sprite(dev_priv
, pipe
, sprite
) {
14633 struct intel_plane
*plane
;
14635 plane
= intel_sprite_plane_create(dev_priv
, pipe
, sprite
);
14636 if (IS_ERR(plane
)) {
14637 ret
= PTR_ERR(plane
);
14640 intel_crtc
->plane_ids_mask
|= BIT(plane
->id
);
14643 cursor
= intel_cursor_plane_create(dev_priv
, pipe
);
14644 if (IS_ERR(cursor
)) {
14645 ret
= PTR_ERR(cursor
);
14648 intel_crtc
->plane_ids_mask
|= BIT(cursor
->id
);
14650 ret
= drm_crtc_init_with_planes(&dev_priv
->drm
, &intel_crtc
->base
,
14651 &primary
->base
, &cursor
->base
,
14653 "pipe %c", pipe_name(pipe
));
14657 intel_crtc
->pipe
= pipe
;
14659 /* initialize shared scalers */
14660 intel_crtc_init_scalers(intel_crtc
, crtc_state
);
14662 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->pipe_to_crtc_mapping
) ||
14663 dev_priv
->pipe_to_crtc_mapping
[pipe
] != NULL
);
14664 dev_priv
->pipe_to_crtc_mapping
[pipe
] = intel_crtc
;
14666 if (INTEL_GEN(dev_priv
) < 9) {
14667 enum i9xx_plane_id i9xx_plane
= primary
->i9xx_plane
;
14669 BUG_ON(i9xx_plane
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
14670 dev_priv
->plane_to_crtc_mapping
[i9xx_plane
] != NULL
);
14671 dev_priv
->plane_to_crtc_mapping
[i9xx_plane
] = intel_crtc
;
14674 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
14676 intel_color_init(intel_crtc
);
14678 WARN_ON(drm_crtc_index(&intel_crtc
->base
) != intel_crtc
->pipe
);
14684 * drm_mode_config_cleanup() will free up any
14685 * crtcs/planes already initialized.
14693 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device
*dev
, void *data
,
14694 struct drm_file
*file
)
14696 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
14697 struct drm_crtc
*drmmode_crtc
;
14698 struct intel_crtc
*crtc
;
14700 drmmode_crtc
= drm_crtc_find(dev
, file
, pipe_from_crtc_id
->crtc_id
);
14704 crtc
= to_intel_crtc(drmmode_crtc
);
14705 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
14710 static int intel_encoder_clones(struct intel_encoder
*encoder
)
14712 struct drm_device
*dev
= encoder
->base
.dev
;
14713 struct intel_encoder
*source_encoder
;
14714 int index_mask
= 0;
14717 for_each_intel_encoder(dev
, source_encoder
) {
14718 if (encoders_cloneable(encoder
, source_encoder
))
14719 index_mask
|= (1 << entry
);
14727 static bool ilk_has_edp_a(struct drm_i915_private
*dev_priv
)
14729 if (!IS_MOBILE(dev_priv
))
14732 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
14735 if (IS_GEN(dev_priv
, 5) && (I915_READ(FUSE_STRAP
) & ILK_eDP_A_DISABLE
))
14741 static bool intel_ddi_crt_present(struct drm_i915_private
*dev_priv
)
14743 if (INTEL_GEN(dev_priv
) >= 9)
14746 if (IS_HSW_ULT(dev_priv
) || IS_BDW_ULT(dev_priv
))
14749 if (HAS_PCH_LPT_H(dev_priv
) &&
14750 I915_READ(SFUSE_STRAP
) & SFUSE_STRAP_CRT_DISABLED
)
14753 /* DDI E can't be used if DDI A requires 4 lanes */
14754 if (I915_READ(DDI_BUF_CTL(PORT_A
)) & DDI_A_4_LANES
)
14757 if (!dev_priv
->vbt
.int_crt_support
)
14763 void intel_pps_unlock_regs_wa(struct drm_i915_private
*dev_priv
)
14768 if (HAS_DDI(dev_priv
))
14771 * This w/a is needed at least on CPT/PPT, but to be sure apply it
14772 * everywhere where registers can be write protected.
14774 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
14779 for (pps_idx
= 0; pps_idx
< pps_num
; pps_idx
++) {
14780 u32 val
= I915_READ(PP_CONTROL(pps_idx
));
14782 val
= (val
& ~PANEL_UNLOCK_MASK
) | PANEL_UNLOCK_REGS
;
14783 I915_WRITE(PP_CONTROL(pps_idx
), val
);
14787 static void intel_pps_init(struct drm_i915_private
*dev_priv
)
14789 if (HAS_PCH_SPLIT(dev_priv
) || IS_GEN9_LP(dev_priv
))
14790 dev_priv
->pps_mmio_base
= PCH_PPS_BASE
;
14791 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
14792 dev_priv
->pps_mmio_base
= VLV_PPS_BASE
;
14794 dev_priv
->pps_mmio_base
= PPS_BASE
;
14796 intel_pps_unlock_regs_wa(dev_priv
);
14799 static void intel_setup_outputs(struct drm_i915_private
*dev_priv
)
14801 struct intel_encoder
*encoder
;
14802 bool dpd_is_edp
= false;
14804 intel_pps_init(dev_priv
);
14806 if (!HAS_DISPLAY(dev_priv
))
14809 if (IS_ELKHARTLAKE(dev_priv
)) {
14810 intel_ddi_init(dev_priv
, PORT_A
);
14811 intel_ddi_init(dev_priv
, PORT_B
);
14812 intel_ddi_init(dev_priv
, PORT_C
);
14813 icl_dsi_init(dev_priv
);
14814 } else if (INTEL_GEN(dev_priv
) >= 11) {
14815 intel_ddi_init(dev_priv
, PORT_A
);
14816 intel_ddi_init(dev_priv
, PORT_B
);
14817 intel_ddi_init(dev_priv
, PORT_C
);
14818 intel_ddi_init(dev_priv
, PORT_D
);
14819 intel_ddi_init(dev_priv
, PORT_E
);
14821 * On some ICL SKUs port F is not present. No strap bits for
14822 * this, so rely on VBT.
14823 * Work around broken VBTs on SKUs known to have no port F.
14825 if (IS_ICL_WITH_PORT_F(dev_priv
) &&
14826 intel_bios_is_port_present(dev_priv
, PORT_F
))
14827 intel_ddi_init(dev_priv
, PORT_F
);
14829 icl_dsi_init(dev_priv
);
14830 } else if (IS_GEN9_LP(dev_priv
)) {
14832 * FIXME: Broxton doesn't support port detection via the
14833 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14834 * detect the ports.
14836 intel_ddi_init(dev_priv
, PORT_A
);
14837 intel_ddi_init(dev_priv
, PORT_B
);
14838 intel_ddi_init(dev_priv
, PORT_C
);
14840 vlv_dsi_init(dev_priv
);
14841 } else if (HAS_DDI(dev_priv
)) {
14844 if (intel_ddi_crt_present(dev_priv
))
14845 intel_crt_init(dev_priv
);
14848 * Haswell uses DDI functions to detect digital outputs.
14849 * On SKL pre-D0 the strap isn't connected, so we assume
14852 found
= I915_READ(DDI_BUF_CTL(PORT_A
)) & DDI_INIT_DISPLAY_DETECTED
;
14853 /* WaIgnoreDDIAStrap: skl */
14854 if (found
|| IS_GEN9_BC(dev_priv
))
14855 intel_ddi_init(dev_priv
, PORT_A
);
14857 /* DDI B, C, D, and F detection is indicated by the SFUSE_STRAP
14859 found
= I915_READ(SFUSE_STRAP
);
14861 if (found
& SFUSE_STRAP_DDIB_DETECTED
)
14862 intel_ddi_init(dev_priv
, PORT_B
);
14863 if (found
& SFUSE_STRAP_DDIC_DETECTED
)
14864 intel_ddi_init(dev_priv
, PORT_C
);
14865 if (found
& SFUSE_STRAP_DDID_DETECTED
)
14866 intel_ddi_init(dev_priv
, PORT_D
);
14867 if (found
& SFUSE_STRAP_DDIF_DETECTED
)
14868 intel_ddi_init(dev_priv
, PORT_F
);
14870 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14872 if (IS_GEN9_BC(dev_priv
) &&
14873 intel_bios_is_port_present(dev_priv
, PORT_E
))
14874 intel_ddi_init(dev_priv
, PORT_E
);
14876 } else if (HAS_PCH_SPLIT(dev_priv
)) {
14880 * intel_edp_init_connector() depends on this completing first,
14881 * to prevent the registration of both eDP and LVDS and the
14882 * incorrect sharing of the PPS.
14884 intel_lvds_init(dev_priv
);
14885 intel_crt_init(dev_priv
);
14887 dpd_is_edp
= intel_dp_is_port_edp(dev_priv
, PORT_D
);
14889 if (ilk_has_edp_a(dev_priv
))
14890 intel_dp_init(dev_priv
, DP_A
, PORT_A
);
14892 if (I915_READ(PCH_HDMIB
) & SDVO_DETECTED
) {
14893 /* PCH SDVOB multiplex with HDMIB */
14894 found
= intel_sdvo_init(dev_priv
, PCH_SDVOB
, PORT_B
);
14896 intel_hdmi_init(dev_priv
, PCH_HDMIB
, PORT_B
);
14897 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
14898 intel_dp_init(dev_priv
, PCH_DP_B
, PORT_B
);
14901 if (I915_READ(PCH_HDMIC
) & SDVO_DETECTED
)
14902 intel_hdmi_init(dev_priv
, PCH_HDMIC
, PORT_C
);
14904 if (!dpd_is_edp
&& I915_READ(PCH_HDMID
) & SDVO_DETECTED
)
14905 intel_hdmi_init(dev_priv
, PCH_HDMID
, PORT_D
);
14907 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
14908 intel_dp_init(dev_priv
, PCH_DP_C
, PORT_C
);
14910 if (I915_READ(PCH_DP_D
) & DP_DETECTED
)
14911 intel_dp_init(dev_priv
, PCH_DP_D
, PORT_D
);
14912 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
14913 bool has_edp
, has_port
;
14915 if (IS_VALLEYVIEW(dev_priv
) && dev_priv
->vbt
.int_crt_support
)
14916 intel_crt_init(dev_priv
);
14919 * The DP_DETECTED bit is the latched state of the DDC
14920 * SDA pin at boot. However since eDP doesn't require DDC
14921 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14922 * eDP ports may have been muxed to an alternate function.
14923 * Thus we can't rely on the DP_DETECTED bit alone to detect
14924 * eDP ports. Consult the VBT as well as DP_DETECTED to
14925 * detect eDP ports.
14927 * Sadly the straps seem to be missing sometimes even for HDMI
14928 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
14929 * and VBT for the presence of the port. Additionally we can't
14930 * trust the port type the VBT declares as we've seen at least
14931 * HDMI ports that the VBT claim are DP or eDP.
14933 has_edp
= intel_dp_is_port_edp(dev_priv
, PORT_B
);
14934 has_port
= intel_bios_is_port_present(dev_priv
, PORT_B
);
14935 if (I915_READ(VLV_DP_B
) & DP_DETECTED
|| has_port
)
14936 has_edp
&= intel_dp_init(dev_priv
, VLV_DP_B
, PORT_B
);
14937 if ((I915_READ(VLV_HDMIB
) & SDVO_DETECTED
|| has_port
) && !has_edp
)
14938 intel_hdmi_init(dev_priv
, VLV_HDMIB
, PORT_B
);
14940 has_edp
= intel_dp_is_port_edp(dev_priv
, PORT_C
);
14941 has_port
= intel_bios_is_port_present(dev_priv
, PORT_C
);
14942 if (I915_READ(VLV_DP_C
) & DP_DETECTED
|| has_port
)
14943 has_edp
&= intel_dp_init(dev_priv
, VLV_DP_C
, PORT_C
);
14944 if ((I915_READ(VLV_HDMIC
) & SDVO_DETECTED
|| has_port
) && !has_edp
)
14945 intel_hdmi_init(dev_priv
, VLV_HDMIC
, PORT_C
);
14947 if (IS_CHERRYVIEW(dev_priv
)) {
14949 * eDP not supported on port D,
14950 * so no need to worry about it
14952 has_port
= intel_bios_is_port_present(dev_priv
, PORT_D
);
14953 if (I915_READ(CHV_DP_D
) & DP_DETECTED
|| has_port
)
14954 intel_dp_init(dev_priv
, CHV_DP_D
, PORT_D
);
14955 if (I915_READ(CHV_HDMID
) & SDVO_DETECTED
|| has_port
)
14956 intel_hdmi_init(dev_priv
, CHV_HDMID
, PORT_D
);
14959 vlv_dsi_init(dev_priv
);
14960 } else if (IS_PINEVIEW(dev_priv
)) {
14961 intel_lvds_init(dev_priv
);
14962 intel_crt_init(dev_priv
);
14963 } else if (IS_GEN_RANGE(dev_priv
, 3, 4)) {
14964 bool found
= false;
14966 if (IS_MOBILE(dev_priv
))
14967 intel_lvds_init(dev_priv
);
14969 intel_crt_init(dev_priv
);
14971 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
14972 DRM_DEBUG_KMS("probing SDVOB\n");
14973 found
= intel_sdvo_init(dev_priv
, GEN3_SDVOB
, PORT_B
);
14974 if (!found
&& IS_G4X(dev_priv
)) {
14975 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14976 intel_hdmi_init(dev_priv
, GEN4_HDMIB
, PORT_B
);
14979 if (!found
&& IS_G4X(dev_priv
))
14980 intel_dp_init(dev_priv
, DP_B
, PORT_B
);
14983 /* Before G4X SDVOC doesn't have its own detect register */
14985 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
14986 DRM_DEBUG_KMS("probing SDVOC\n");
14987 found
= intel_sdvo_init(dev_priv
, GEN3_SDVOC
, PORT_C
);
14990 if (!found
&& (I915_READ(GEN3_SDVOC
) & SDVO_DETECTED
)) {
14992 if (IS_G4X(dev_priv
)) {
14993 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14994 intel_hdmi_init(dev_priv
, GEN4_HDMIC
, PORT_C
);
14996 if (IS_G4X(dev_priv
))
14997 intel_dp_init(dev_priv
, DP_C
, PORT_C
);
15000 if (IS_G4X(dev_priv
) && (I915_READ(DP_D
) & DP_DETECTED
))
15001 intel_dp_init(dev_priv
, DP_D
, PORT_D
);
15003 if (SUPPORTS_TV(dev_priv
))
15004 intel_tv_init(dev_priv
);
15005 } else if (IS_GEN(dev_priv
, 2)) {
15006 if (IS_I85X(dev_priv
))
15007 intel_lvds_init(dev_priv
);
15009 intel_crt_init(dev_priv
);
15010 intel_dvo_init(dev_priv
);
15013 intel_psr_init(dev_priv
);
15015 for_each_intel_encoder(&dev_priv
->drm
, encoder
) {
15016 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
15017 encoder
->base
.possible_clones
=
15018 intel_encoder_clones(encoder
);
15021 intel_init_pch_refclk(dev_priv
);
15023 drm_helper_move_panel_connectors_to_head(&dev_priv
->drm
);
15026 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
15028 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
15029 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
15031 drm_framebuffer_cleanup(fb
);
15033 i915_gem_object_lock(obj
);
15034 WARN_ON(!obj
->framebuffer_references
--);
15035 i915_gem_object_unlock(obj
);
15037 i915_gem_object_put(obj
);
15042 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
15043 struct drm_file
*file
,
15044 unsigned int *handle
)
15046 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
15048 if (obj
->userptr
.mm
) {
15049 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
15053 return drm_gem_handle_create(file
, &obj
->base
, handle
);
15056 static int intel_user_framebuffer_dirty(struct drm_framebuffer
*fb
,
15057 struct drm_file
*file
,
15058 unsigned flags
, unsigned color
,
15059 struct drm_clip_rect
*clips
,
15060 unsigned num_clips
)
15062 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
15064 i915_gem_object_flush_if_display(obj
);
15065 intel_fb_obj_flush(obj
, ORIGIN_DIRTYFB
);
15070 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
15071 .destroy
= intel_user_framebuffer_destroy
,
15072 .create_handle
= intel_user_framebuffer_create_handle
,
15073 .dirty
= intel_user_framebuffer_dirty
,
15077 u32
intel_fb_pitch_limit(struct drm_i915_private
*dev_priv
,
15078 u32 pixel_format
, u64 fb_modifier
)
15080 struct intel_crtc
*crtc
;
15081 struct intel_plane
*plane
;
15084 * We assume the primary plane for pipe A has
15085 * the highest stride limits of them all.
15087 crtc
= intel_get_crtc_for_pipe(dev_priv
, PIPE_A
);
15088 plane
= to_intel_plane(crtc
->base
.primary
);
15090 return plane
->max_stride(plane
, pixel_format
, fb_modifier
,
15091 DRM_MODE_ROTATE_0
);
15094 static int intel_framebuffer_init(struct intel_framebuffer
*intel_fb
,
15095 struct drm_i915_gem_object
*obj
,
15096 struct drm_mode_fb_cmd2
*mode_cmd
)
15098 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
15099 struct drm_framebuffer
*fb
= &intel_fb
->base
;
15101 unsigned int tiling
, stride
;
15105 i915_gem_object_lock(obj
);
15106 obj
->framebuffer_references
++;
15107 tiling
= i915_gem_object_get_tiling(obj
);
15108 stride
= i915_gem_object_get_stride(obj
);
15109 i915_gem_object_unlock(obj
);
15111 if (mode_cmd
->flags
& DRM_MODE_FB_MODIFIERS
) {
15113 * If there's a fence, enforce that
15114 * the fb modifier and tiling mode match.
15116 if (tiling
!= I915_TILING_NONE
&&
15117 tiling
!= intel_fb_modifier_to_tiling(mode_cmd
->modifier
[0])) {
15118 DRM_DEBUG_KMS("tiling_mode doesn't match fb modifier\n");
15122 if (tiling
== I915_TILING_X
) {
15123 mode_cmd
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
15124 } else if (tiling
== I915_TILING_Y
) {
15125 DRM_DEBUG_KMS("No Y tiling for legacy addfb\n");
15130 if (!drm_any_plane_has_format(&dev_priv
->drm
,
15131 mode_cmd
->pixel_format
,
15132 mode_cmd
->modifier
[0])) {
15133 struct drm_format_name_buf format_name
;
15135 DRM_DEBUG_KMS("unsupported pixel format %s / modifier 0x%llx\n",
15136 drm_get_format_name(mode_cmd
->pixel_format
,
15138 mode_cmd
->modifier
[0]);
15143 * gen2/3 display engine uses the fence if present,
15144 * so the tiling mode must match the fb modifier exactly.
15146 if (INTEL_GEN(dev_priv
) < 4 &&
15147 tiling
!= intel_fb_modifier_to_tiling(mode_cmd
->modifier
[0])) {
15148 DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n");
15152 pitch_limit
= intel_fb_pitch_limit(dev_priv
, mode_cmd
->pixel_format
,
15153 mode_cmd
->modifier
[0]);
15154 if (mode_cmd
->pitches
[0] > pitch_limit
) {
15155 DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n",
15156 mode_cmd
->modifier
[0] != DRM_FORMAT_MOD_LINEAR
?
15157 "tiled" : "linear",
15158 mode_cmd
->pitches
[0], pitch_limit
);
15163 * If there's a fence, enforce that
15164 * the fb pitch and fence stride match.
15166 if (tiling
!= I915_TILING_NONE
&& mode_cmd
->pitches
[0] != stride
) {
15167 DRM_DEBUG_KMS("pitch (%d) must match tiling stride (%d)\n",
15168 mode_cmd
->pitches
[0], stride
);
15172 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
15173 if (mode_cmd
->offsets
[0] != 0)
15176 drm_helper_mode_fill_fb_struct(&dev_priv
->drm
, fb
, mode_cmd
);
15178 for (i
= 0; i
< fb
->format
->num_planes
; i
++) {
15179 u32 stride_alignment
;
15181 if (mode_cmd
->handles
[i
] != mode_cmd
->handles
[0]) {
15182 DRM_DEBUG_KMS("bad plane %d handle\n", i
);
15186 stride_alignment
= intel_fb_stride_alignment(fb
, i
);
15189 * Display WA #0531: skl,bxt,kbl,glk
15191 * Render decompression and plane width > 3840
15192 * combined with horizontal panning requires the
15193 * plane stride to be a multiple of 4. We'll just
15194 * require the entire fb to accommodate that to avoid
15195 * potential runtime errors at plane configuration time.
15197 if (IS_GEN(dev_priv
, 9) && i
== 0 && fb
->width
> 3840 &&
15198 is_ccs_modifier(fb
->modifier
))
15199 stride_alignment
*= 4;
15201 if (fb
->pitches
[i
] & (stride_alignment
- 1)) {
15202 DRM_DEBUG_KMS("plane %d pitch (%d) must be at least %u byte aligned\n",
15203 i
, fb
->pitches
[i
], stride_alignment
);
15207 fb
->obj
[i
] = &obj
->base
;
15210 ret
= intel_fill_fb_info(dev_priv
, fb
);
15214 ret
= drm_framebuffer_init(&dev_priv
->drm
, fb
, &intel_fb_funcs
);
15216 DRM_ERROR("framebuffer init failed %d\n", ret
);
15223 i915_gem_object_lock(obj
);
15224 obj
->framebuffer_references
--;
15225 i915_gem_object_unlock(obj
);
15229 static struct drm_framebuffer
*
15230 intel_user_framebuffer_create(struct drm_device
*dev
,
15231 struct drm_file
*filp
,
15232 const struct drm_mode_fb_cmd2
*user_mode_cmd
)
15234 struct drm_framebuffer
*fb
;
15235 struct drm_i915_gem_object
*obj
;
15236 struct drm_mode_fb_cmd2 mode_cmd
= *user_mode_cmd
;
15238 obj
= i915_gem_object_lookup(filp
, mode_cmd
.handles
[0]);
15240 return ERR_PTR(-ENOENT
);
15242 fb
= intel_framebuffer_create(obj
, &mode_cmd
);
15244 i915_gem_object_put(obj
);
15249 static void intel_atomic_state_free(struct drm_atomic_state
*state
)
15251 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
15253 drm_atomic_state_default_release(state
);
15255 i915_sw_fence_fini(&intel_state
->commit_ready
);
15260 static enum drm_mode_status
15261 intel_mode_valid(struct drm_device
*dev
,
15262 const struct drm_display_mode
*mode
)
15264 struct drm_i915_private
*dev_priv
= to_i915(dev
);
15265 int hdisplay_max
, htotal_max
;
15266 int vdisplay_max
, vtotal_max
;
15269 * Can't reject DBLSCAN here because Xorg ddxen can add piles
15270 * of DBLSCAN modes to the output's mode list when they detect
15271 * the scaling mode property on the connector. And they don't
15272 * ask the kernel to validate those modes in any way until
15273 * modeset time at which point the client gets a protocol error.
15274 * So in order to not upset those clients we silently ignore the
15275 * DBLSCAN flag on such connectors. For other connectors we will
15276 * reject modes with the DBLSCAN flag in encoder->compute_config().
15277 * And we always reject DBLSCAN modes in connector->mode_valid()
15278 * as we never want such modes on the connector's mode list.
15281 if (mode
->vscan
> 1)
15282 return MODE_NO_VSCAN
;
15284 if (mode
->flags
& DRM_MODE_FLAG_HSKEW
)
15285 return MODE_H_ILLEGAL
;
15287 if (mode
->flags
& (DRM_MODE_FLAG_CSYNC
|
15288 DRM_MODE_FLAG_NCSYNC
|
15289 DRM_MODE_FLAG_PCSYNC
))
15292 if (mode
->flags
& (DRM_MODE_FLAG_BCAST
|
15293 DRM_MODE_FLAG_PIXMUX
|
15294 DRM_MODE_FLAG_CLKDIV2
))
15297 if (INTEL_GEN(dev_priv
) >= 9 ||
15298 IS_BROADWELL(dev_priv
) || IS_HASWELL(dev_priv
)) {
15299 hdisplay_max
= 8192; /* FDI max 4096 handled elsewhere */
15300 vdisplay_max
= 4096;
15303 } else if (INTEL_GEN(dev_priv
) >= 3) {
15304 hdisplay_max
= 4096;
15305 vdisplay_max
= 4096;
15309 hdisplay_max
= 2048;
15310 vdisplay_max
= 2048;
15315 if (mode
->hdisplay
> hdisplay_max
||
15316 mode
->hsync_start
> htotal_max
||
15317 mode
->hsync_end
> htotal_max
||
15318 mode
->htotal
> htotal_max
)
15319 return MODE_H_ILLEGAL
;
15321 if (mode
->vdisplay
> vdisplay_max
||
15322 mode
->vsync_start
> vtotal_max
||
15323 mode
->vsync_end
> vtotal_max
||
15324 mode
->vtotal
> vtotal_max
)
15325 return MODE_V_ILLEGAL
;
15330 static const struct drm_mode_config_funcs intel_mode_funcs
= {
15331 .fb_create
= intel_user_framebuffer_create
,
15332 .get_format_info
= intel_get_format_info
,
15333 .output_poll_changed
= intel_fbdev_output_poll_changed
,
15334 .mode_valid
= intel_mode_valid
,
15335 .atomic_check
= intel_atomic_check
,
15336 .atomic_commit
= intel_atomic_commit
,
15337 .atomic_state_alloc
= intel_atomic_state_alloc
,
15338 .atomic_state_clear
= intel_atomic_state_clear
,
15339 .atomic_state_free
= intel_atomic_state_free
,
15343 * intel_init_display_hooks - initialize the display modesetting hooks
15344 * @dev_priv: device private
15346 void intel_init_display_hooks(struct drm_i915_private
*dev_priv
)
15348 intel_init_cdclk_hooks(dev_priv
);
15350 if (INTEL_GEN(dev_priv
) >= 9) {
15351 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
15352 dev_priv
->display
.get_initial_plane_config
=
15353 skylake_get_initial_plane_config
;
15354 dev_priv
->display
.crtc_compute_clock
=
15355 haswell_crtc_compute_clock
;
15356 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
15357 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
15358 } else if (HAS_DDI(dev_priv
)) {
15359 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
15360 dev_priv
->display
.get_initial_plane_config
=
15361 i9xx_get_initial_plane_config
;
15362 dev_priv
->display
.crtc_compute_clock
=
15363 haswell_crtc_compute_clock
;
15364 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
15365 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
15366 } else if (HAS_PCH_SPLIT(dev_priv
)) {
15367 dev_priv
->display
.get_pipe_config
= ironlake_get_pipe_config
;
15368 dev_priv
->display
.get_initial_plane_config
=
15369 i9xx_get_initial_plane_config
;
15370 dev_priv
->display
.crtc_compute_clock
=
15371 ironlake_crtc_compute_clock
;
15372 dev_priv
->display
.crtc_enable
= ironlake_crtc_enable
;
15373 dev_priv
->display
.crtc_disable
= ironlake_crtc_disable
;
15374 } else if (IS_CHERRYVIEW(dev_priv
)) {
15375 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
15376 dev_priv
->display
.get_initial_plane_config
=
15377 i9xx_get_initial_plane_config
;
15378 dev_priv
->display
.crtc_compute_clock
= chv_crtc_compute_clock
;
15379 dev_priv
->display
.crtc_enable
= valleyview_crtc_enable
;
15380 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
15381 } else if (IS_VALLEYVIEW(dev_priv
)) {
15382 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
15383 dev_priv
->display
.get_initial_plane_config
=
15384 i9xx_get_initial_plane_config
;
15385 dev_priv
->display
.crtc_compute_clock
= vlv_crtc_compute_clock
;
15386 dev_priv
->display
.crtc_enable
= valleyview_crtc_enable
;
15387 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
15388 } else if (IS_G4X(dev_priv
)) {
15389 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
15390 dev_priv
->display
.get_initial_plane_config
=
15391 i9xx_get_initial_plane_config
;
15392 dev_priv
->display
.crtc_compute_clock
= g4x_crtc_compute_clock
;
15393 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
15394 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
15395 } else if (IS_PINEVIEW(dev_priv
)) {
15396 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
15397 dev_priv
->display
.get_initial_plane_config
=
15398 i9xx_get_initial_plane_config
;
15399 dev_priv
->display
.crtc_compute_clock
= pnv_crtc_compute_clock
;
15400 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
15401 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
15402 } else if (!IS_GEN(dev_priv
, 2)) {
15403 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
15404 dev_priv
->display
.get_initial_plane_config
=
15405 i9xx_get_initial_plane_config
;
15406 dev_priv
->display
.crtc_compute_clock
= i9xx_crtc_compute_clock
;
15407 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
15408 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
15410 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
15411 dev_priv
->display
.get_initial_plane_config
=
15412 i9xx_get_initial_plane_config
;
15413 dev_priv
->display
.crtc_compute_clock
= i8xx_crtc_compute_clock
;
15414 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
15415 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
15418 if (IS_GEN(dev_priv
, 5)) {
15419 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
15420 } else if (IS_GEN(dev_priv
, 6)) {
15421 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
15422 } else if (IS_IVYBRIDGE(dev_priv
)) {
15423 /* FIXME: detect B0+ stepping and use auto training */
15424 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
15425 } else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
15426 dev_priv
->display
.fdi_link_train
= hsw_fdi_link_train
;
15429 if (INTEL_GEN(dev_priv
) >= 9)
15430 dev_priv
->display
.update_crtcs
= skl_update_crtcs
;
15432 dev_priv
->display
.update_crtcs
= intel_update_crtcs
;
15435 /* Disable the VGA plane that we never use */
15436 static void i915_disable_vga(struct drm_i915_private
*dev_priv
)
15438 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
15440 i915_reg_t vga_reg
= i915_vgacntrl_reg(dev_priv
);
15442 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15443 vga_get_uninterruptible(pdev
, VGA_RSRC_LEGACY_IO
);
15444 outb(SR01
, VGA_SR_INDEX
);
15445 sr1
= inb(VGA_SR_DATA
);
15446 outb(sr1
| 1<<5, VGA_SR_DATA
);
15447 vga_put(pdev
, VGA_RSRC_LEGACY_IO
);
15450 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
15451 POSTING_READ(vga_reg
);
15454 void intel_modeset_init_hw(struct drm_device
*dev
)
15456 struct drm_i915_private
*dev_priv
= to_i915(dev
);
15458 intel_update_cdclk(dev_priv
);
15459 intel_dump_cdclk_state(&dev_priv
->cdclk
.hw
, "Current CDCLK");
15460 dev_priv
->cdclk
.logical
= dev_priv
->cdclk
.actual
= dev_priv
->cdclk
.hw
;
15464 * Calculate what we think the watermarks should be for the state we've read
15465 * out of the hardware and then immediately program those watermarks so that
15466 * we ensure the hardware settings match our internal state.
15468 * We can calculate what we think WM's should be by creating a duplicate of the
15469 * current state (which was constructed during hardware readout) and running it
15470 * through the atomic check code to calculate new watermark values in the
15473 static void sanitize_watermarks(struct drm_device
*dev
)
15475 struct drm_i915_private
*dev_priv
= to_i915(dev
);
15476 struct drm_atomic_state
*state
;
15477 struct intel_atomic_state
*intel_state
;
15478 struct drm_crtc
*crtc
;
15479 struct drm_crtc_state
*cstate
;
15480 struct drm_modeset_acquire_ctx ctx
;
15484 /* Only supported on platforms that use atomic watermark design */
15485 if (!dev_priv
->display
.optimize_watermarks
)
15489 * We need to hold connection_mutex before calling duplicate_state so
15490 * that the connector loop is protected.
15492 drm_modeset_acquire_init(&ctx
, 0);
15494 ret
= drm_modeset_lock_all_ctx(dev
, &ctx
);
15495 if (ret
== -EDEADLK
) {
15496 drm_modeset_backoff(&ctx
);
15498 } else if (WARN_ON(ret
)) {
15502 state
= drm_atomic_helper_duplicate_state(dev
, &ctx
);
15503 if (WARN_ON(IS_ERR(state
)))
15506 intel_state
= to_intel_atomic_state(state
);
15509 * Hardware readout is the only time we don't want to calculate
15510 * intermediate watermarks (since we don't trust the current
15513 if (!HAS_GMCH(dev_priv
))
15514 intel_state
->skip_intermediate_wm
= true;
15516 ret
= intel_atomic_check(dev
, state
);
15519 * If we fail here, it means that the hardware appears to be
15520 * programmed in a way that shouldn't be possible, given our
15521 * understanding of watermark requirements. This might mean a
15522 * mistake in the hardware readout code or a mistake in the
15523 * watermark calculations for a given platform. Raise a WARN
15524 * so that this is noticeable.
15526 * If this actually happens, we'll have to just leave the
15527 * BIOS-programmed watermarks untouched and hope for the best.
15529 WARN(true, "Could not determine valid watermarks for inherited state\n");
15533 /* Write calculated watermark values back */
15534 for_each_new_crtc_in_state(state
, crtc
, cstate
, i
) {
15535 struct intel_crtc_state
*cs
= to_intel_crtc_state(cstate
);
15537 cs
->wm
.need_postvbl_update
= true;
15538 dev_priv
->display
.optimize_watermarks(intel_state
, cs
);
15540 to_intel_crtc_state(crtc
->state
)->wm
= cs
->wm
;
15544 drm_atomic_state_put(state
);
15546 drm_modeset_drop_locks(&ctx
);
15547 drm_modeset_acquire_fini(&ctx
);
15550 static void intel_update_fdi_pll_freq(struct drm_i915_private
*dev_priv
)
15552 if (IS_GEN(dev_priv
, 5)) {
15554 I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
;
15556 dev_priv
->fdi_pll_freq
= (fdi_pll_clk
+ 2) * 10000;
15557 } else if (IS_GEN(dev_priv
, 6) || IS_IVYBRIDGE(dev_priv
)) {
15558 dev_priv
->fdi_pll_freq
= 270000;
15563 DRM_DEBUG_DRIVER("FDI PLL freq=%d\n", dev_priv
->fdi_pll_freq
);
15566 static int intel_initial_commit(struct drm_device
*dev
)
15568 struct drm_atomic_state
*state
= NULL
;
15569 struct drm_modeset_acquire_ctx ctx
;
15570 struct drm_crtc
*crtc
;
15571 struct drm_crtc_state
*crtc_state
;
15574 state
= drm_atomic_state_alloc(dev
);
15578 drm_modeset_acquire_init(&ctx
, 0);
15581 state
->acquire_ctx
= &ctx
;
15583 drm_for_each_crtc(crtc
, dev
) {
15584 crtc_state
= drm_atomic_get_crtc_state(state
, crtc
);
15585 if (IS_ERR(crtc_state
)) {
15586 ret
= PTR_ERR(crtc_state
);
15590 if (crtc_state
->active
) {
15591 ret
= drm_atomic_add_affected_planes(state
, crtc
);
15596 * FIXME hack to force a LUT update to avoid the
15597 * plane update forcing the pipe gamma on without
15598 * having a proper LUT loaded. Remove once we
15599 * have readout for pipe gamma enable.
15601 crtc_state
->color_mgmt_changed
= true;
15605 ret
= drm_atomic_commit(state
);
15608 if (ret
== -EDEADLK
) {
15609 drm_atomic_state_clear(state
);
15610 drm_modeset_backoff(&ctx
);
15614 drm_atomic_state_put(state
);
15616 drm_modeset_drop_locks(&ctx
);
15617 drm_modeset_acquire_fini(&ctx
);
15622 int intel_modeset_init(struct drm_device
*dev
)
15624 struct drm_i915_private
*dev_priv
= to_i915(dev
);
15625 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
15627 struct intel_crtc
*crtc
;
15630 dev_priv
->modeset_wq
= alloc_ordered_workqueue("i915_modeset", 0);
15632 drm_mode_config_init(dev
);
15634 dev
->mode_config
.min_width
= 0;
15635 dev
->mode_config
.min_height
= 0;
15637 dev
->mode_config
.preferred_depth
= 24;
15638 dev
->mode_config
.prefer_shadow
= 1;
15640 dev
->mode_config
.allow_fb_modifiers
= true;
15642 dev
->mode_config
.funcs
= &intel_mode_funcs
;
15644 init_llist_head(&dev_priv
->atomic_helper
.free_list
);
15645 INIT_WORK(&dev_priv
->atomic_helper
.free_work
,
15646 intel_atomic_helper_free_state_worker
);
15648 intel_init_quirks(dev_priv
);
15650 intel_fbc_init(dev_priv
);
15652 intel_init_pm(dev_priv
);
15655 * There may be no VBT; and if the BIOS enabled SSC we can
15656 * just keep using it to avoid unnecessary flicker. Whereas if the
15657 * BIOS isn't using it, don't assume it will work even if the VBT
15658 * indicates as much.
15660 if (HAS_PCH_IBX(dev_priv
) || HAS_PCH_CPT(dev_priv
)) {
15661 bool bios_lvds_use_ssc
= !!(I915_READ(PCH_DREF_CONTROL
) &
15664 if (dev_priv
->vbt
.lvds_use_ssc
!= bios_lvds_use_ssc
) {
15665 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15666 bios_lvds_use_ssc
? "en" : "dis",
15667 dev_priv
->vbt
.lvds_use_ssc
? "en" : "dis");
15668 dev_priv
->vbt
.lvds_use_ssc
= bios_lvds_use_ssc
;
15672 /* maximum framebuffer dimensions */
15673 if (IS_GEN(dev_priv
, 2)) {
15674 dev
->mode_config
.max_width
= 2048;
15675 dev
->mode_config
.max_height
= 2048;
15676 } else if (IS_GEN(dev_priv
, 3)) {
15677 dev
->mode_config
.max_width
= 4096;
15678 dev
->mode_config
.max_height
= 4096;
15680 dev
->mode_config
.max_width
= 8192;
15681 dev
->mode_config
.max_height
= 8192;
15684 if (IS_I845G(dev_priv
) || IS_I865G(dev_priv
)) {
15685 dev
->mode_config
.cursor_width
= IS_I845G(dev_priv
) ? 64 : 512;
15686 dev
->mode_config
.cursor_height
= 1023;
15687 } else if (IS_GEN(dev_priv
, 2)) {
15688 dev
->mode_config
.cursor_width
= 64;
15689 dev
->mode_config
.cursor_height
= 64;
15691 dev
->mode_config
.cursor_width
= 256;
15692 dev
->mode_config
.cursor_height
= 256;
15695 dev
->mode_config
.fb_base
= ggtt
->gmadr
.start
;
15697 DRM_DEBUG_KMS("%d display pipe%s available.\n",
15698 INTEL_INFO(dev_priv
)->num_pipes
,
15699 INTEL_INFO(dev_priv
)->num_pipes
> 1 ? "s" : "");
15701 for_each_pipe(dev_priv
, pipe
) {
15702 ret
= intel_crtc_init(dev_priv
, pipe
);
15704 drm_mode_config_cleanup(dev
);
15709 intel_shared_dpll_init(dev
);
15710 intel_update_fdi_pll_freq(dev_priv
);
15712 intel_update_czclk(dev_priv
);
15713 intel_modeset_init_hw(dev
);
15715 intel_hdcp_component_init(dev_priv
);
15717 if (dev_priv
->max_cdclk_freq
== 0)
15718 intel_update_max_cdclk(dev_priv
);
15720 /* Just disable it once at startup */
15721 i915_disable_vga(dev_priv
);
15722 intel_setup_outputs(dev_priv
);
15724 drm_modeset_lock_all(dev
);
15725 intel_modeset_setup_hw_state(dev
, dev
->mode_config
.acquire_ctx
);
15726 drm_modeset_unlock_all(dev
);
15728 for_each_intel_crtc(dev
, crtc
) {
15729 struct intel_initial_plane_config plane_config
= {};
15735 * Note that reserving the BIOS fb up front prevents us
15736 * from stuffing other stolen allocations like the ring
15737 * on top. This prevents some ugliness at boot time, and
15738 * can even allow for smooth boot transitions if the BIOS
15739 * fb is large enough for the active pipe configuration.
15741 dev_priv
->display
.get_initial_plane_config(crtc
,
15745 * If the fb is shared between multiple heads, we'll
15746 * just get the first one.
15748 intel_find_initial_plane_obj(crtc
, &plane_config
);
15752 * Make sure hardware watermarks really match the state we read out.
15753 * Note that we need to do this after reconstructing the BIOS fb's
15754 * since the watermark calculation done here will use pstate->fb.
15756 if (!HAS_GMCH(dev_priv
))
15757 sanitize_watermarks(dev
);
15760 * Force all active planes to recompute their states. So that on
15761 * mode_setcrtc after probe, all the intel_plane_state variables
15762 * are already calculated and there is no assert_plane warnings
15765 ret
= intel_initial_commit(dev
);
15767 DRM_DEBUG_KMS("Initial commit in probe failed.\n");
15772 void i830_enable_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
15774 struct intel_crtc
*crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
15775 /* 640x480@60Hz, ~25175 kHz */
15776 struct dpll clock
= {
15786 WARN_ON(i9xx_calc_dpll_params(48000, &clock
) != 25154);
15788 DRM_DEBUG_KMS("enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
15789 pipe_name(pipe
), clock
.vco
, clock
.dot
);
15791 fp
= i9xx_dpll_compute_fp(&clock
);
15792 dpll
= DPLL_DVO_2X_MODE
|
15793 DPLL_VGA_MODE_DIS
|
15794 ((clock
.p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
) |
15795 PLL_P2_DIVIDE_BY_4
|
15796 PLL_REF_INPUT_DREFCLK
|
15799 I915_WRITE(FP0(pipe
), fp
);
15800 I915_WRITE(FP1(pipe
), fp
);
15802 I915_WRITE(HTOTAL(pipe
), (640 - 1) | ((800 - 1) << 16));
15803 I915_WRITE(HBLANK(pipe
), (640 - 1) | ((800 - 1) << 16));
15804 I915_WRITE(HSYNC(pipe
), (656 - 1) | ((752 - 1) << 16));
15805 I915_WRITE(VTOTAL(pipe
), (480 - 1) | ((525 - 1) << 16));
15806 I915_WRITE(VBLANK(pipe
), (480 - 1) | ((525 - 1) << 16));
15807 I915_WRITE(VSYNC(pipe
), (490 - 1) | ((492 - 1) << 16));
15808 I915_WRITE(PIPESRC(pipe
), ((640 - 1) << 16) | (480 - 1));
15811 * Apparently we need to have VGA mode enabled prior to changing
15812 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
15813 * dividers, even though the register value does change.
15815 I915_WRITE(DPLL(pipe
), dpll
& ~DPLL_VGA_MODE_DIS
);
15816 I915_WRITE(DPLL(pipe
), dpll
);
15818 /* Wait for the clocks to stabilize. */
15819 POSTING_READ(DPLL(pipe
));
15822 /* The pixel multiplier can only be updated once the
15823 * DPLL is enabled and the clocks are stable.
15825 * So write it again.
15827 I915_WRITE(DPLL(pipe
), dpll
);
15829 /* We do this three times for luck */
15830 for (i
= 0; i
< 3 ; i
++) {
15831 I915_WRITE(DPLL(pipe
), dpll
);
15832 POSTING_READ(DPLL(pipe
));
15833 udelay(150); /* wait for warmup */
15836 I915_WRITE(PIPECONF(pipe
), PIPECONF_ENABLE
| PIPECONF_PROGRESSIVE
);
15837 POSTING_READ(PIPECONF(pipe
));
15839 intel_wait_for_pipe_scanline_moving(crtc
);
15842 void i830_disable_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
15844 struct intel_crtc
*crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
15846 DRM_DEBUG_KMS("disabling pipe %c due to force quirk\n",
15849 WARN_ON(I915_READ(DSPCNTR(PLANE_A
)) & DISPLAY_PLANE_ENABLE
);
15850 WARN_ON(I915_READ(DSPCNTR(PLANE_B
)) & DISPLAY_PLANE_ENABLE
);
15851 WARN_ON(I915_READ(DSPCNTR(PLANE_C
)) & DISPLAY_PLANE_ENABLE
);
15852 WARN_ON(I915_READ(CURCNTR(PIPE_A
)) & MCURSOR_MODE
);
15853 WARN_ON(I915_READ(CURCNTR(PIPE_B
)) & MCURSOR_MODE
);
15855 I915_WRITE(PIPECONF(pipe
), 0);
15856 POSTING_READ(PIPECONF(pipe
));
15858 intel_wait_for_pipe_scanline_stopped(crtc
);
15860 I915_WRITE(DPLL(pipe
), DPLL_VGA_MODE_DIS
);
15861 POSTING_READ(DPLL(pipe
));
15865 intel_sanitize_plane_mapping(struct drm_i915_private
*dev_priv
)
15867 struct intel_crtc
*crtc
;
15869 if (INTEL_GEN(dev_priv
) >= 4)
15872 for_each_intel_crtc(&dev_priv
->drm
, crtc
) {
15873 struct intel_plane
*plane
=
15874 to_intel_plane(crtc
->base
.primary
);
15875 struct intel_crtc
*plane_crtc
;
15878 if (!plane
->get_hw_state(plane
, &pipe
))
15881 if (pipe
== crtc
->pipe
)
15884 DRM_DEBUG_KMS("[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n",
15885 plane
->base
.base
.id
, plane
->base
.name
);
15887 plane_crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
15888 intel_plane_disable_noatomic(plane_crtc
, plane
);
15892 static bool intel_crtc_has_encoders(struct intel_crtc
*crtc
)
15894 struct drm_device
*dev
= crtc
->base
.dev
;
15895 struct intel_encoder
*encoder
;
15897 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
)
15903 static struct intel_connector
*intel_encoder_find_connector(struct intel_encoder
*encoder
)
15905 struct drm_device
*dev
= encoder
->base
.dev
;
15906 struct intel_connector
*connector
;
15908 for_each_connector_on_encoder(dev
, &encoder
->base
, connector
)
15914 static bool has_pch_trancoder(struct drm_i915_private
*dev_priv
,
15915 enum pipe pch_transcoder
)
15917 return HAS_PCH_IBX(dev_priv
) || HAS_PCH_CPT(dev_priv
) ||
15918 (HAS_PCH_LPT_H(dev_priv
) && pch_transcoder
== PIPE_A
);
15921 static void intel_sanitize_crtc(struct intel_crtc
*crtc
,
15922 struct drm_modeset_acquire_ctx
*ctx
)
15924 struct drm_device
*dev
= crtc
->base
.dev
;
15925 struct drm_i915_private
*dev_priv
= to_i915(dev
);
15926 struct intel_crtc_state
*crtc_state
= to_intel_crtc_state(crtc
->base
.state
);
15927 enum transcoder cpu_transcoder
= crtc_state
->cpu_transcoder
;
15929 /* Clear any frame start delays used for debugging left by the BIOS */
15930 if (crtc
->active
&& !transcoder_is_dsi(cpu_transcoder
)) {
15931 i915_reg_t reg
= PIPECONF(cpu_transcoder
);
15934 I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
15937 if (crtc_state
->base
.active
) {
15938 struct intel_plane
*plane
;
15940 /* Disable everything but the primary plane */
15941 for_each_intel_plane_on_crtc(dev
, crtc
, plane
) {
15942 const struct intel_plane_state
*plane_state
=
15943 to_intel_plane_state(plane
->base
.state
);
15945 if (plane_state
->base
.visible
&&
15946 plane
->base
.type
!= DRM_PLANE_TYPE_PRIMARY
)
15947 intel_plane_disable_noatomic(crtc
, plane
);
15951 * Disable any background color set by the BIOS, but enable the
15952 * gamma and CSC to match how we program our planes.
15954 if (INTEL_GEN(dev_priv
) >= 9)
15955 I915_WRITE(SKL_BOTTOM_COLOR(crtc
->pipe
),
15956 SKL_BOTTOM_COLOR_GAMMA_ENABLE
|
15957 SKL_BOTTOM_COLOR_CSC_ENABLE
);
15960 /* Adjust the state of the output pipe according to whether we
15961 * have active connectors/encoders. */
15962 if (crtc_state
->base
.active
&& !intel_crtc_has_encoders(crtc
))
15963 intel_crtc_disable_noatomic(&crtc
->base
, ctx
);
15965 if (crtc_state
->base
.active
|| HAS_GMCH(dev_priv
)) {
15967 * We start out with underrun reporting disabled to avoid races.
15968 * For correct bookkeeping mark this on active crtcs.
15970 * Also on gmch platforms we dont have any hardware bits to
15971 * disable the underrun reporting. Which means we need to start
15972 * out with underrun reporting disabled also on inactive pipes,
15973 * since otherwise we'll complain about the garbage we read when
15974 * e.g. coming up after runtime pm.
15976 * No protection against concurrent access is required - at
15977 * worst a fifo underrun happens which also sets this to false.
15979 crtc
->cpu_fifo_underrun_disabled
= true;
15981 * We track the PCH trancoder underrun reporting state
15982 * within the crtc. With crtc for pipe A housing the underrun
15983 * reporting state for PCH transcoder A, crtc for pipe B housing
15984 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
15985 * and marking underrun reporting as disabled for the non-existing
15986 * PCH transcoders B and C would prevent enabling the south
15987 * error interrupt (see cpt_can_enable_serr_int()).
15989 if (has_pch_trancoder(dev_priv
, crtc
->pipe
))
15990 crtc
->pch_fifo_underrun_disabled
= true;
15994 static bool has_bogus_dpll_config(const struct intel_crtc_state
*crtc_state
)
15996 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->base
.crtc
->dev
);
15999 * Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram
16000 * the hardware when a high res displays plugged in. DPLL P
16001 * divider is zero, and the pipe timings are bonkers. We'll
16002 * try to disable everything in that case.
16004 * FIXME would be nice to be able to sanitize this state
16005 * without several WARNs, but for now let's take the easy
16008 return IS_GEN(dev_priv
, 6) &&
16009 crtc_state
->base
.active
&&
16010 crtc_state
->shared_dpll
&&
16011 crtc_state
->port_clock
== 0;
16014 static void intel_sanitize_encoder(struct intel_encoder
*encoder
)
16016 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
16017 struct intel_connector
*connector
;
16018 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
16019 struct intel_crtc_state
*crtc_state
= crtc
?
16020 to_intel_crtc_state(crtc
->base
.state
) : NULL
;
16022 /* We need to check both for a crtc link (meaning that the
16023 * encoder is active and trying to read from a pipe) and the
16024 * pipe itself being active. */
16025 bool has_active_crtc
= crtc_state
&&
16026 crtc_state
->base
.active
;
16028 if (crtc_state
&& has_bogus_dpll_config(crtc_state
)) {
16029 DRM_DEBUG_KMS("BIOS has misprogrammed the hardware. Disabling pipe %c\n",
16030 pipe_name(crtc
->pipe
));
16031 has_active_crtc
= false;
16034 connector
= intel_encoder_find_connector(encoder
);
16035 if (connector
&& !has_active_crtc
) {
16036 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
16037 encoder
->base
.base
.id
,
16038 encoder
->base
.name
);
16040 /* Connector is active, but has no active pipe. This is
16041 * fallout from our resume register restoring. Disable
16042 * the encoder manually again. */
16044 struct drm_encoder
*best_encoder
;
16046 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
16047 encoder
->base
.base
.id
,
16048 encoder
->base
.name
);
16050 /* avoid oopsing in case the hooks consult best_encoder */
16051 best_encoder
= connector
->base
.state
->best_encoder
;
16052 connector
->base
.state
->best_encoder
= &encoder
->base
;
16054 if (encoder
->disable
)
16055 encoder
->disable(encoder
, crtc_state
,
16056 connector
->base
.state
);
16057 if (encoder
->post_disable
)
16058 encoder
->post_disable(encoder
, crtc_state
,
16059 connector
->base
.state
);
16061 connector
->base
.state
->best_encoder
= best_encoder
;
16063 encoder
->base
.crtc
= NULL
;
16065 /* Inconsistent output/port/pipe state happens presumably due to
16066 * a bug in one of the get_hw_state functions. Or someplace else
16067 * in our code, like the register restore mess on resume. Clamp
16068 * things to off as a safer default. */
16070 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
16071 connector
->base
.encoder
= NULL
;
16074 /* notify opregion of the sanitized encoder state */
16075 intel_opregion_notify_encoder(encoder
, connector
&& has_active_crtc
);
16077 if (INTEL_GEN(dev_priv
) >= 11)
16078 icl_sanitize_encoder_pll_mapping(encoder
);
16081 void i915_redisable_vga_power_on(struct drm_i915_private
*dev_priv
)
16083 i915_reg_t vga_reg
= i915_vgacntrl_reg(dev_priv
);
16085 if (!(I915_READ(vga_reg
) & VGA_DISP_DISABLE
)) {
16086 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
16087 i915_disable_vga(dev_priv
);
16091 void i915_redisable_vga(struct drm_i915_private
*dev_priv
)
16093 intel_wakeref_t wakeref
;
16096 * This function can be called both from intel_modeset_setup_hw_state or
16097 * at a very early point in our resume sequence, where the power well
16098 * structures are not yet restored. Since this function is at a very
16099 * paranoid "someone might have enabled VGA while we were not looking"
16100 * level, just check if the power well is enabled instead of trying to
16101 * follow the "don't touch the power well if we don't need it" policy
16102 * the rest of the driver uses.
16104 wakeref
= intel_display_power_get_if_enabled(dev_priv
,
16109 i915_redisable_vga_power_on(dev_priv
);
16111 intel_display_power_put(dev_priv
, POWER_DOMAIN_VGA
, wakeref
);
16114 /* FIXME read out full plane state for all planes */
16115 static void readout_plane_state(struct drm_i915_private
*dev_priv
)
16117 struct intel_plane
*plane
;
16118 struct intel_crtc
*crtc
;
16120 for_each_intel_plane(&dev_priv
->drm
, plane
) {
16121 struct intel_plane_state
*plane_state
=
16122 to_intel_plane_state(plane
->base
.state
);
16123 struct intel_crtc_state
*crtc_state
;
16124 enum pipe pipe
= PIPE_A
;
16127 visible
= plane
->get_hw_state(plane
, &pipe
);
16129 crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
16130 crtc_state
= to_intel_crtc_state(crtc
->base
.state
);
16132 intel_set_plane_visible(crtc_state
, plane_state
, visible
);
16134 DRM_DEBUG_KMS("[PLANE:%d:%s] hw state readout: %s, pipe %c\n",
16135 plane
->base
.base
.id
, plane
->base
.name
,
16136 enableddisabled(visible
), pipe_name(pipe
));
16139 for_each_intel_crtc(&dev_priv
->drm
, crtc
) {
16140 struct intel_crtc_state
*crtc_state
=
16141 to_intel_crtc_state(crtc
->base
.state
);
16143 fixup_active_planes(crtc_state
);
16147 static void intel_modeset_readout_hw_state(struct drm_device
*dev
)
16149 struct drm_i915_private
*dev_priv
= to_i915(dev
);
16151 struct intel_crtc
*crtc
;
16152 struct intel_encoder
*encoder
;
16153 struct intel_connector
*connector
;
16154 struct drm_connector_list_iter conn_iter
;
16157 dev_priv
->active_crtcs
= 0;
16159 for_each_intel_crtc(dev
, crtc
) {
16160 struct intel_crtc_state
*crtc_state
=
16161 to_intel_crtc_state(crtc
->base
.state
);
16163 __drm_atomic_helper_crtc_destroy_state(&crtc_state
->base
);
16164 memset(crtc_state
, 0, sizeof(*crtc_state
));
16165 crtc_state
->base
.crtc
= &crtc
->base
;
16167 crtc_state
->base
.active
= crtc_state
->base
.enable
=
16168 dev_priv
->display
.get_pipe_config(crtc
, crtc_state
);
16170 crtc
->base
.enabled
= crtc_state
->base
.enable
;
16171 crtc
->active
= crtc_state
->base
.active
;
16173 if (crtc_state
->base
.active
)
16174 dev_priv
->active_crtcs
|= 1 << crtc
->pipe
;
16176 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
16177 crtc
->base
.base
.id
, crtc
->base
.name
,
16178 enableddisabled(crtc_state
->base
.active
));
16181 readout_plane_state(dev_priv
);
16183 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
16184 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
16186 pll
->on
= pll
->info
->funcs
->get_hw_state(dev_priv
, pll
,
16187 &pll
->state
.hw_state
);
16188 pll
->state
.crtc_mask
= 0;
16189 for_each_intel_crtc(dev
, crtc
) {
16190 struct intel_crtc_state
*crtc_state
=
16191 to_intel_crtc_state(crtc
->base
.state
);
16193 if (crtc_state
->base
.active
&&
16194 crtc_state
->shared_dpll
== pll
)
16195 pll
->state
.crtc_mask
|= 1 << crtc
->pipe
;
16197 pll
->active_mask
= pll
->state
.crtc_mask
;
16199 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
16200 pll
->info
->name
, pll
->state
.crtc_mask
, pll
->on
);
16203 for_each_intel_encoder(dev
, encoder
) {
16206 if (encoder
->get_hw_state(encoder
, &pipe
)) {
16207 struct intel_crtc_state
*crtc_state
;
16209 crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
16210 crtc_state
= to_intel_crtc_state(crtc
->base
.state
);
16212 encoder
->base
.crtc
= &crtc
->base
;
16213 encoder
->get_config(encoder
, crtc_state
);
16215 encoder
->base
.crtc
= NULL
;
16218 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
16219 encoder
->base
.base
.id
, encoder
->base
.name
,
16220 enableddisabled(encoder
->base
.crtc
),
16224 drm_connector_list_iter_begin(dev
, &conn_iter
);
16225 for_each_intel_connector_iter(connector
, &conn_iter
) {
16226 if (connector
->get_hw_state(connector
)) {
16227 connector
->base
.dpms
= DRM_MODE_DPMS_ON
;
16229 encoder
= connector
->encoder
;
16230 connector
->base
.encoder
= &encoder
->base
;
16232 if (encoder
->base
.crtc
&&
16233 encoder
->base
.crtc
->state
->active
) {
16235 * This has to be done during hardware readout
16236 * because anything calling .crtc_disable may
16237 * rely on the connector_mask being accurate.
16239 encoder
->base
.crtc
->state
->connector_mask
|=
16240 drm_connector_mask(&connector
->base
);
16241 encoder
->base
.crtc
->state
->encoder_mask
|=
16242 drm_encoder_mask(&encoder
->base
);
16246 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
16247 connector
->base
.encoder
= NULL
;
16249 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
16250 connector
->base
.base
.id
, connector
->base
.name
,
16251 enableddisabled(connector
->base
.encoder
));
16253 drm_connector_list_iter_end(&conn_iter
);
16255 for_each_intel_crtc(dev
, crtc
) {
16256 struct intel_crtc_state
*crtc_state
=
16257 to_intel_crtc_state(crtc
->base
.state
);
16260 memset(&crtc
->base
.mode
, 0, sizeof(crtc
->base
.mode
));
16261 if (crtc_state
->base
.active
) {
16262 intel_mode_from_pipe_config(&crtc
->base
.mode
, crtc_state
);
16263 crtc
->base
.mode
.hdisplay
= crtc_state
->pipe_src_w
;
16264 crtc
->base
.mode
.vdisplay
= crtc_state
->pipe_src_h
;
16265 intel_mode_from_pipe_config(&crtc_state
->base
.adjusted_mode
, crtc_state
);
16266 WARN_ON(drm_atomic_set_mode_for_crtc(crtc
->base
.state
, &crtc
->base
.mode
));
16269 * The initial mode needs to be set in order to keep
16270 * the atomic core happy. It wants a valid mode if the
16271 * crtc's enabled, so we do the above call.
16273 * But we don't set all the derived state fully, hence
16274 * set a flag to indicate that a full recalculation is
16275 * needed on the next commit.
16277 crtc_state
->base
.mode
.private_flags
= I915_MODE_FLAG_INHERITED
;
16279 intel_crtc_compute_pixel_rate(crtc_state
);
16281 if (dev_priv
->display
.modeset_calc_cdclk
) {
16282 min_cdclk
= intel_crtc_compute_min_cdclk(crtc_state
);
16283 if (WARN_ON(min_cdclk
< 0))
16287 drm_calc_timestamping_constants(&crtc
->base
,
16288 &crtc_state
->base
.adjusted_mode
);
16289 update_scanline_offset(crtc_state
);
16292 dev_priv
->min_cdclk
[crtc
->pipe
] = min_cdclk
;
16293 dev_priv
->min_voltage_level
[crtc
->pipe
] =
16294 crtc_state
->min_voltage_level
;
16296 intel_pipe_config_sanity_check(dev_priv
, crtc_state
);
16301 get_encoder_power_domains(struct drm_i915_private
*dev_priv
)
16303 struct intel_encoder
*encoder
;
16305 for_each_intel_encoder(&dev_priv
->drm
, encoder
) {
16306 struct intel_crtc_state
*crtc_state
;
16308 if (!encoder
->get_power_domains
)
16312 * MST-primary and inactive encoders don't have a crtc state
16313 * and neither of these require any power domain references.
16315 if (!encoder
->base
.crtc
)
16318 crtc_state
= to_intel_crtc_state(encoder
->base
.crtc
->state
);
16319 encoder
->get_power_domains(encoder
, crtc_state
);
16323 static void intel_early_display_was(struct drm_i915_private
*dev_priv
)
16325 /* Display WA #1185 WaDisableDARBFClkGating:cnl,glk */
16326 if (IS_CANNONLAKE(dev_priv
) || IS_GEMINILAKE(dev_priv
))
16327 I915_WRITE(GEN9_CLKGATE_DIS_0
, I915_READ(GEN9_CLKGATE_DIS_0
) |
16330 if (IS_HASWELL(dev_priv
)) {
16332 * WaRsPkgCStateDisplayPMReq:hsw
16333 * System hang if this isn't done before disabling all planes!
16335 I915_WRITE(CHICKEN_PAR1_1
,
16336 I915_READ(CHICKEN_PAR1_1
) | FORCE_ARB_IDLE_PLANES
);
16340 static void ibx_sanitize_pch_hdmi_port(struct drm_i915_private
*dev_priv
,
16341 enum port port
, i915_reg_t hdmi_reg
)
16343 u32 val
= I915_READ(hdmi_reg
);
16345 if (val
& SDVO_ENABLE
||
16346 (val
& SDVO_PIPE_SEL_MASK
) == SDVO_PIPE_SEL(PIPE_A
))
16349 DRM_DEBUG_KMS("Sanitizing transcoder select for HDMI %c\n",
16352 val
&= ~SDVO_PIPE_SEL_MASK
;
16353 val
|= SDVO_PIPE_SEL(PIPE_A
);
16355 I915_WRITE(hdmi_reg
, val
);
16358 static void ibx_sanitize_pch_dp_port(struct drm_i915_private
*dev_priv
,
16359 enum port port
, i915_reg_t dp_reg
)
16361 u32 val
= I915_READ(dp_reg
);
16363 if (val
& DP_PORT_EN
||
16364 (val
& DP_PIPE_SEL_MASK
) == DP_PIPE_SEL(PIPE_A
))
16367 DRM_DEBUG_KMS("Sanitizing transcoder select for DP %c\n",
16370 val
&= ~DP_PIPE_SEL_MASK
;
16371 val
|= DP_PIPE_SEL(PIPE_A
);
16373 I915_WRITE(dp_reg
, val
);
16376 static void ibx_sanitize_pch_ports(struct drm_i915_private
*dev_priv
)
16379 * The BIOS may select transcoder B on some of the PCH
16380 * ports even it doesn't enable the port. This would trip
16381 * assert_pch_dp_disabled() and assert_pch_hdmi_disabled().
16382 * Sanitize the transcoder select bits to prevent that. We
16383 * assume that the BIOS never actually enabled the port,
16384 * because if it did we'd actually have to toggle the port
16385 * on and back off to make the transcoder A select stick
16386 * (see. intel_dp_link_down(), intel_disable_hdmi(),
16387 * intel_disable_sdvo()).
16389 ibx_sanitize_pch_dp_port(dev_priv
, PORT_B
, PCH_DP_B
);
16390 ibx_sanitize_pch_dp_port(dev_priv
, PORT_C
, PCH_DP_C
);
16391 ibx_sanitize_pch_dp_port(dev_priv
, PORT_D
, PCH_DP_D
);
16393 /* PCH SDVOB multiplex with HDMIB */
16394 ibx_sanitize_pch_hdmi_port(dev_priv
, PORT_B
, PCH_HDMIB
);
16395 ibx_sanitize_pch_hdmi_port(dev_priv
, PORT_C
, PCH_HDMIC
);
16396 ibx_sanitize_pch_hdmi_port(dev_priv
, PORT_D
, PCH_HDMID
);
16399 /* Scan out the current hw modeset state,
16400 * and sanitizes it to the current state
16403 intel_modeset_setup_hw_state(struct drm_device
*dev
,
16404 struct drm_modeset_acquire_ctx
*ctx
)
16406 struct drm_i915_private
*dev_priv
= to_i915(dev
);
16407 struct intel_crtc_state
*crtc_state
;
16408 struct intel_encoder
*encoder
;
16409 struct intel_crtc
*crtc
;
16410 intel_wakeref_t wakeref
;
16413 wakeref
= intel_display_power_get(dev_priv
, POWER_DOMAIN_INIT
);
16415 intel_early_display_was(dev_priv
);
16416 intel_modeset_readout_hw_state(dev
);
16418 /* HW state is read out, now we need to sanitize this mess. */
16419 get_encoder_power_domains(dev_priv
);
16421 if (HAS_PCH_IBX(dev_priv
))
16422 ibx_sanitize_pch_ports(dev_priv
);
16425 * intel_sanitize_plane_mapping() may need to do vblank
16426 * waits, so we need vblank interrupts restored beforehand.
16428 for_each_intel_crtc(&dev_priv
->drm
, crtc
) {
16429 crtc_state
= to_intel_crtc_state(crtc
->base
.state
);
16431 drm_crtc_vblank_reset(&crtc
->base
);
16433 if (crtc_state
->base
.active
)
16434 intel_crtc_vblank_on(crtc_state
);
16437 intel_sanitize_plane_mapping(dev_priv
);
16439 for_each_intel_encoder(dev
, encoder
)
16440 intel_sanitize_encoder(encoder
);
16442 for_each_intel_crtc(&dev_priv
->drm
, crtc
) {
16443 crtc_state
= to_intel_crtc_state(crtc
->base
.state
);
16444 intel_sanitize_crtc(crtc
, ctx
);
16445 intel_dump_pipe_config(crtc
, crtc_state
,
16446 "[setup_hw_state]");
16449 intel_modeset_update_connector_atomic_state(dev
);
16451 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
16452 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
16454 if (!pll
->on
|| pll
->active_mask
)
16457 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n",
16460 pll
->info
->funcs
->disable(dev_priv
, pll
);
16464 if (IS_G4X(dev_priv
)) {
16465 g4x_wm_get_hw_state(dev_priv
);
16466 g4x_wm_sanitize(dev_priv
);
16467 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
16468 vlv_wm_get_hw_state(dev_priv
);
16469 vlv_wm_sanitize(dev_priv
);
16470 } else if (INTEL_GEN(dev_priv
) >= 9) {
16471 skl_wm_get_hw_state(dev_priv
);
16472 } else if (HAS_PCH_SPLIT(dev_priv
)) {
16473 ilk_wm_get_hw_state(dev_priv
);
16476 for_each_intel_crtc(dev
, crtc
) {
16479 crtc_state
= to_intel_crtc_state(crtc
->base
.state
);
16480 put_domains
= modeset_get_crtc_power_domains(&crtc
->base
, crtc_state
);
16481 if (WARN_ON(put_domains
))
16482 modeset_put_power_domains(dev_priv
, put_domains
);
16485 intel_display_power_put(dev_priv
, POWER_DOMAIN_INIT
, wakeref
);
16487 intel_fbc_init_pipe_state(dev_priv
);
16490 void intel_display_resume(struct drm_device
*dev
)
16492 struct drm_i915_private
*dev_priv
= to_i915(dev
);
16493 struct drm_atomic_state
*state
= dev_priv
->modeset_restore_state
;
16494 struct drm_modeset_acquire_ctx ctx
;
16497 dev_priv
->modeset_restore_state
= NULL
;
16499 state
->acquire_ctx
= &ctx
;
16501 drm_modeset_acquire_init(&ctx
, 0);
16504 ret
= drm_modeset_lock_all_ctx(dev
, &ctx
);
16505 if (ret
!= -EDEADLK
)
16508 drm_modeset_backoff(&ctx
);
16512 ret
= __intel_display_resume(dev
, state
, &ctx
);
16514 intel_enable_ipc(dev_priv
);
16515 drm_modeset_drop_locks(&ctx
);
16516 drm_modeset_acquire_fini(&ctx
);
16519 DRM_ERROR("Restoring old state failed with %i\n", ret
);
16521 drm_atomic_state_put(state
);
16524 static void intel_hpd_poll_fini(struct drm_device
*dev
)
16526 struct intel_connector
*connector
;
16527 struct drm_connector_list_iter conn_iter
;
16529 /* Kill all the work that may have been queued by hpd. */
16530 drm_connector_list_iter_begin(dev
, &conn_iter
);
16531 for_each_intel_connector_iter(connector
, &conn_iter
) {
16532 if (connector
->modeset_retry_work
.func
)
16533 cancel_work_sync(&connector
->modeset_retry_work
);
16534 if (connector
->hdcp
.shim
) {
16535 cancel_delayed_work_sync(&connector
->hdcp
.check_work
);
16536 cancel_work_sync(&connector
->hdcp
.prop_work
);
16539 drm_connector_list_iter_end(&conn_iter
);
16542 void intel_modeset_cleanup(struct drm_device
*dev
)
16544 struct drm_i915_private
*dev_priv
= to_i915(dev
);
16546 flush_workqueue(dev_priv
->modeset_wq
);
16548 flush_work(&dev_priv
->atomic_helper
.free_work
);
16549 WARN_ON(!llist_empty(&dev_priv
->atomic_helper
.free_list
));
16552 * Interrupts and polling as the first thing to avoid creating havoc.
16553 * Too much stuff here (turning of connectors, ...) would
16554 * experience fancy races otherwise.
16556 intel_irq_uninstall(dev_priv
);
16559 * Due to the hpd irq storm handling the hotplug work can re-arm the
16560 * poll handlers. Hence disable polling after hpd handling is shut down.
16562 intel_hpd_poll_fini(dev
);
16564 /* poll work can call into fbdev, hence clean that up afterwards */
16565 intel_fbdev_fini(dev_priv
);
16567 intel_unregister_dsm_handler();
16569 intel_fbc_global_disable(dev_priv
);
16571 /* flush any delayed tasks or pending work */
16572 flush_scheduled_work();
16574 intel_hdcp_component_fini(dev_priv
);
16576 drm_mode_config_cleanup(dev
);
16578 intel_overlay_cleanup(dev_priv
);
16580 intel_teardown_gmbus(dev_priv
);
16582 destroy_workqueue(dev_priv
->modeset_wq
);
16584 intel_fbc_cleanup_cfb(dev_priv
);
16588 * set vga decode state - true == enable VGA decode
16590 int intel_modeset_vga_set_state(struct drm_i915_private
*dev_priv
, bool state
)
16592 unsigned reg
= INTEL_GEN(dev_priv
) >= 6 ? SNB_GMCH_CTRL
: INTEL_GMCH_CTRL
;
16595 if (pci_read_config_word(dev_priv
->bridge_dev
, reg
, &gmch_ctrl
)) {
16596 DRM_ERROR("failed to read control word\n");
16600 if (!!(gmch_ctrl
& INTEL_GMCH_VGA_DISABLE
) == !state
)
16604 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
16606 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
16608 if (pci_write_config_word(dev_priv
->bridge_dev
, reg
, gmch_ctrl
)) {
16609 DRM_ERROR("failed to write control word\n");
16616 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
16618 struct intel_display_error_state
{
16620 u32 power_well_driver
;
16622 struct intel_cursor_error_state
{
16627 } cursor
[I915_MAX_PIPES
];
16629 struct intel_pipe_error_state
{
16630 bool power_domain_on
;
16633 } pipe
[I915_MAX_PIPES
];
16635 struct intel_plane_error_state
{
16643 } plane
[I915_MAX_PIPES
];
16645 struct intel_transcoder_error_state
{
16647 bool power_domain_on
;
16648 enum transcoder cpu_transcoder
;
16661 struct intel_display_error_state
*
16662 intel_display_capture_error_state(struct drm_i915_private
*dev_priv
)
16664 struct intel_display_error_state
*error
;
16665 int transcoders
[] = {
16673 BUILD_BUG_ON(ARRAY_SIZE(transcoders
) != ARRAY_SIZE(error
->transcoder
));
16675 if (!HAS_DISPLAY(dev_priv
))
16678 error
= kzalloc(sizeof(*error
), GFP_ATOMIC
);
16682 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
16683 error
->power_well_driver
= I915_READ(HSW_PWR_WELL_CTL2
);
16685 for_each_pipe(dev_priv
, i
) {
16686 error
->pipe
[i
].power_domain_on
=
16687 __intel_display_power_is_enabled(dev_priv
,
16688 POWER_DOMAIN_PIPE(i
));
16689 if (!error
->pipe
[i
].power_domain_on
)
16692 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
16693 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
16694 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
16696 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
16697 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
16698 if (INTEL_GEN(dev_priv
) <= 3) {
16699 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
16700 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
16702 if (INTEL_GEN(dev_priv
) <= 7 && !IS_HASWELL(dev_priv
))
16703 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
16704 if (INTEL_GEN(dev_priv
) >= 4) {
16705 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
16706 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
16709 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
16711 if (HAS_GMCH(dev_priv
))
16712 error
->pipe
[i
].stat
= I915_READ(PIPESTAT(i
));
16715 for (i
= 0; i
< ARRAY_SIZE(error
->transcoder
); i
++) {
16716 enum transcoder cpu_transcoder
= transcoders
[i
];
16718 if (!INTEL_INFO(dev_priv
)->trans_offsets
[cpu_transcoder
])
16721 error
->transcoder
[i
].available
= true;
16722 error
->transcoder
[i
].power_domain_on
=
16723 __intel_display_power_is_enabled(dev_priv
,
16724 POWER_DOMAIN_TRANSCODER(cpu_transcoder
));
16725 if (!error
->transcoder
[i
].power_domain_on
)
16728 error
->transcoder
[i
].cpu_transcoder
= cpu_transcoder
;
16730 error
->transcoder
[i
].conf
= I915_READ(PIPECONF(cpu_transcoder
));
16731 error
->transcoder
[i
].htotal
= I915_READ(HTOTAL(cpu_transcoder
));
16732 error
->transcoder
[i
].hblank
= I915_READ(HBLANK(cpu_transcoder
));
16733 error
->transcoder
[i
].hsync
= I915_READ(HSYNC(cpu_transcoder
));
16734 error
->transcoder
[i
].vtotal
= I915_READ(VTOTAL(cpu_transcoder
));
16735 error
->transcoder
[i
].vblank
= I915_READ(VBLANK(cpu_transcoder
));
16736 error
->transcoder
[i
].vsync
= I915_READ(VSYNC(cpu_transcoder
));
16742 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
16745 intel_display_print_error_state(struct drm_i915_error_state_buf
*m
,
16746 struct intel_display_error_state
*error
)
16748 struct drm_i915_private
*dev_priv
= m
->i915
;
16754 err_printf(m
, "Num Pipes: %d\n", INTEL_INFO(dev_priv
)->num_pipes
);
16755 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
16756 err_printf(m
, "PWR_WELL_CTL2: %08x\n",
16757 error
->power_well_driver
);
16758 for_each_pipe(dev_priv
, i
) {
16759 err_printf(m
, "Pipe [%d]:\n", i
);
16760 err_printf(m
, " Power: %s\n",
16761 onoff(error
->pipe
[i
].power_domain_on
));
16762 err_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
16763 err_printf(m
, " STAT: %08x\n", error
->pipe
[i
].stat
);
16765 err_printf(m
, "Plane [%d]:\n", i
);
16766 err_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
16767 err_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
16768 if (INTEL_GEN(dev_priv
) <= 3) {
16769 err_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
16770 err_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
16772 if (INTEL_GEN(dev_priv
) <= 7 && !IS_HASWELL(dev_priv
))
16773 err_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
16774 if (INTEL_GEN(dev_priv
) >= 4) {
16775 err_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
16776 err_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
16779 err_printf(m
, "Cursor [%d]:\n", i
);
16780 err_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
16781 err_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
16782 err_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);
16785 for (i
= 0; i
< ARRAY_SIZE(error
->transcoder
); i
++) {
16786 if (!error
->transcoder
[i
].available
)
16789 err_printf(m
, "CPU transcoder: %s\n",
16790 transcoder_name(error
->transcoder
[i
].cpu_transcoder
));
16791 err_printf(m
, " Power: %s\n",
16792 onoff(error
->transcoder
[i
].power_domain_on
));
16793 err_printf(m
, " CONF: %08x\n", error
->transcoder
[i
].conf
);
16794 err_printf(m
, " HTOTAL: %08x\n", error
->transcoder
[i
].htotal
);
16795 err_printf(m
, " HBLANK: %08x\n", error
->transcoder
[i
].hblank
);
16796 err_printf(m
, " HSYNC: %08x\n", error
->transcoder
[i
].hsync
);
16797 err_printf(m
, " VTOTAL: %08x\n", error
->transcoder
[i
].vtotal
);
16798 err_printf(m
, " VBLANK: %08x\n", error
->transcoder
[i
].vblank
);
16799 err_printf(m
, " VSYNC: %08x\n", error
->transcoder
[i
].vsync
);