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drm/i915: extract intel_color.h from intel_drv.h
[thirdparty/kernel/stable.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/i2c.h>
28 #include <linux/input.h>
29 #include <linux/intel-iommu.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/reservation.h>
33 #include <linux/slab.h>
34 #include <linux/vgaarb.h>
35
36 #include <drm/drm_atomic.h>
37 #include <drm/drm_atomic_helper.h>
38 #include <drm/drm_atomic_uapi.h>
39 #include <drm/drm_dp_helper.h>
40 #include <drm/drm_edid.h>
41 #include <drm/drm_fourcc.h>
42 #include <drm/drm_plane_helper.h>
43 #include <drm/drm_probe_helper.h>
44 #include <drm/drm_rect.h>
45 #include <drm/i915_drm.h>
46
47 #include "i915_drv.h"
48 #include "i915_gem_clflush.h"
49 #include "i915_reset.h"
50 #include "i915_trace.h"
51 #include "intel_color.h"
52 #include "intel_crt.h"
53 #include "intel_ddi.h"
54 #include "intel_drv.h"
55 #include "intel_dsi.h"
56 #include "intel_fbc.h"
57 #include "intel_frontbuffer.h"
58 #include "intel_psr.h"
59
60 /* Primary plane formats for gen <= 3 */
61 static const u32 i8xx_primary_formats[] = {
62 DRM_FORMAT_C8,
63 DRM_FORMAT_RGB565,
64 DRM_FORMAT_XRGB1555,
65 DRM_FORMAT_XRGB8888,
66 };
67
68 /* Primary plane formats for gen >= 4 */
69 static const u32 i965_primary_formats[] = {
70 DRM_FORMAT_C8,
71 DRM_FORMAT_RGB565,
72 DRM_FORMAT_XRGB8888,
73 DRM_FORMAT_XBGR8888,
74 DRM_FORMAT_XRGB2101010,
75 DRM_FORMAT_XBGR2101010,
76 };
77
78 static const u64 i9xx_format_modifiers[] = {
79 I915_FORMAT_MOD_X_TILED,
80 DRM_FORMAT_MOD_LINEAR,
81 DRM_FORMAT_MOD_INVALID
82 };
83
84 /* Cursor formats */
85 static const u32 intel_cursor_formats[] = {
86 DRM_FORMAT_ARGB8888,
87 };
88
89 static const u64 cursor_format_modifiers[] = {
90 DRM_FORMAT_MOD_LINEAR,
91 DRM_FORMAT_MOD_INVALID
92 };
93
94 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
95 struct intel_crtc_state *pipe_config);
96 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
97 struct intel_crtc_state *pipe_config);
98
99 static int intel_framebuffer_init(struct intel_framebuffer *ifb,
100 struct drm_i915_gem_object *obj,
101 struct drm_mode_fb_cmd2 *mode_cmd);
102 static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state);
103 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
104 static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
105 const struct intel_link_m_n *m_n,
106 const struct intel_link_m_n *m2_n2);
107 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);
108 static void ironlake_set_pipeconf(const struct intel_crtc_state *crtc_state);
109 static void haswell_set_pipeconf(const struct intel_crtc_state *crtc_state);
110 static void haswell_set_pipemisc(const struct intel_crtc_state *crtc_state);
111 static void vlv_prepare_pll(struct intel_crtc *crtc,
112 const struct intel_crtc_state *pipe_config);
113 static void chv_prepare_pll(struct intel_crtc *crtc,
114 const struct intel_crtc_state *pipe_config);
115 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
116 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
117 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
118 struct intel_crtc_state *crtc_state);
119 static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state);
120 static void ironlake_pfit_disable(const struct intel_crtc_state *old_crtc_state);
121 static void ironlake_pfit_enable(const struct intel_crtc_state *crtc_state);
122 static void intel_modeset_setup_hw_state(struct drm_device *dev,
123 struct drm_modeset_acquire_ctx *ctx);
124 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
125
126 struct intel_limit {
127 struct {
128 int min, max;
129 } dot, vco, n, m, m1, m2, p, p1;
130
131 struct {
132 int dot_limit;
133 int p2_slow, p2_fast;
134 } p2;
135 };
136
137 /* returns HPLL frequency in kHz */
138 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
139 {
140 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
141
142 /* Obtain SKU information */
143 mutex_lock(&dev_priv->sb_lock);
144 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
145 CCK_FUSE_HPLL_FREQ_MASK;
146 mutex_unlock(&dev_priv->sb_lock);
147
148 return vco_freq[hpll_freq] * 1000;
149 }
150
151 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
152 const char *name, u32 reg, int ref_freq)
153 {
154 u32 val;
155 int divider;
156
157 mutex_lock(&dev_priv->sb_lock);
158 val = vlv_cck_read(dev_priv, reg);
159 mutex_unlock(&dev_priv->sb_lock);
160
161 divider = val & CCK_FREQUENCY_VALUES;
162
163 WARN((val & CCK_FREQUENCY_STATUS) !=
164 (divider << CCK_FREQUENCY_STATUS_SHIFT),
165 "%s change in progress\n", name);
166
167 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
168 }
169
170 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
171 const char *name, u32 reg)
172 {
173 if (dev_priv->hpll_freq == 0)
174 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
175
176 return vlv_get_cck_clock(dev_priv, name, reg,
177 dev_priv->hpll_freq);
178 }
179
180 static void intel_update_czclk(struct drm_i915_private *dev_priv)
181 {
182 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
183 return;
184
185 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
186 CCK_CZ_CLOCK_CONTROL);
187
188 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
189 }
190
191 static inline u32 /* units of 100MHz */
192 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
193 const struct intel_crtc_state *pipe_config)
194 {
195 if (HAS_DDI(dev_priv))
196 return pipe_config->port_clock; /* SPLL */
197 else
198 return dev_priv->fdi_pll_freq;
199 }
200
201 static const struct intel_limit intel_limits_i8xx_dac = {
202 .dot = { .min = 25000, .max = 350000 },
203 .vco = { .min = 908000, .max = 1512000 },
204 .n = { .min = 2, .max = 16 },
205 .m = { .min = 96, .max = 140 },
206 .m1 = { .min = 18, .max = 26 },
207 .m2 = { .min = 6, .max = 16 },
208 .p = { .min = 4, .max = 128 },
209 .p1 = { .min = 2, .max = 33 },
210 .p2 = { .dot_limit = 165000,
211 .p2_slow = 4, .p2_fast = 2 },
212 };
213
214 static const struct intel_limit intel_limits_i8xx_dvo = {
215 .dot = { .min = 25000, .max = 350000 },
216 .vco = { .min = 908000, .max = 1512000 },
217 .n = { .min = 2, .max = 16 },
218 .m = { .min = 96, .max = 140 },
219 .m1 = { .min = 18, .max = 26 },
220 .m2 = { .min = 6, .max = 16 },
221 .p = { .min = 4, .max = 128 },
222 .p1 = { .min = 2, .max = 33 },
223 .p2 = { .dot_limit = 165000,
224 .p2_slow = 4, .p2_fast = 4 },
225 };
226
227 static const struct intel_limit intel_limits_i8xx_lvds = {
228 .dot = { .min = 25000, .max = 350000 },
229 .vco = { .min = 908000, .max = 1512000 },
230 .n = { .min = 2, .max = 16 },
231 .m = { .min = 96, .max = 140 },
232 .m1 = { .min = 18, .max = 26 },
233 .m2 = { .min = 6, .max = 16 },
234 .p = { .min = 4, .max = 128 },
235 .p1 = { .min = 1, .max = 6 },
236 .p2 = { .dot_limit = 165000,
237 .p2_slow = 14, .p2_fast = 7 },
238 };
239
240 static const struct intel_limit intel_limits_i9xx_sdvo = {
241 .dot = { .min = 20000, .max = 400000 },
242 .vco = { .min = 1400000, .max = 2800000 },
243 .n = { .min = 1, .max = 6 },
244 .m = { .min = 70, .max = 120 },
245 .m1 = { .min = 8, .max = 18 },
246 .m2 = { .min = 3, .max = 7 },
247 .p = { .min = 5, .max = 80 },
248 .p1 = { .min = 1, .max = 8 },
249 .p2 = { .dot_limit = 200000,
250 .p2_slow = 10, .p2_fast = 5 },
251 };
252
253 static const struct intel_limit intel_limits_i9xx_lvds = {
254 .dot = { .min = 20000, .max = 400000 },
255 .vco = { .min = 1400000, .max = 2800000 },
256 .n = { .min = 1, .max = 6 },
257 .m = { .min = 70, .max = 120 },
258 .m1 = { .min = 8, .max = 18 },
259 .m2 = { .min = 3, .max = 7 },
260 .p = { .min = 7, .max = 98 },
261 .p1 = { .min = 1, .max = 8 },
262 .p2 = { .dot_limit = 112000,
263 .p2_slow = 14, .p2_fast = 7 },
264 };
265
266
267 static const struct intel_limit intel_limits_g4x_sdvo = {
268 .dot = { .min = 25000, .max = 270000 },
269 .vco = { .min = 1750000, .max = 3500000},
270 .n = { .min = 1, .max = 4 },
271 .m = { .min = 104, .max = 138 },
272 .m1 = { .min = 17, .max = 23 },
273 .m2 = { .min = 5, .max = 11 },
274 .p = { .min = 10, .max = 30 },
275 .p1 = { .min = 1, .max = 3},
276 .p2 = { .dot_limit = 270000,
277 .p2_slow = 10,
278 .p2_fast = 10
279 },
280 };
281
282 static const struct intel_limit intel_limits_g4x_hdmi = {
283 .dot = { .min = 22000, .max = 400000 },
284 .vco = { .min = 1750000, .max = 3500000},
285 .n = { .min = 1, .max = 4 },
286 .m = { .min = 104, .max = 138 },
287 .m1 = { .min = 16, .max = 23 },
288 .m2 = { .min = 5, .max = 11 },
289 .p = { .min = 5, .max = 80 },
290 .p1 = { .min = 1, .max = 8},
291 .p2 = { .dot_limit = 165000,
292 .p2_slow = 10, .p2_fast = 5 },
293 };
294
295 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
296 .dot = { .min = 20000, .max = 115000 },
297 .vco = { .min = 1750000, .max = 3500000 },
298 .n = { .min = 1, .max = 3 },
299 .m = { .min = 104, .max = 138 },
300 .m1 = { .min = 17, .max = 23 },
301 .m2 = { .min = 5, .max = 11 },
302 .p = { .min = 28, .max = 112 },
303 .p1 = { .min = 2, .max = 8 },
304 .p2 = { .dot_limit = 0,
305 .p2_slow = 14, .p2_fast = 14
306 },
307 };
308
309 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
310 .dot = { .min = 80000, .max = 224000 },
311 .vco = { .min = 1750000, .max = 3500000 },
312 .n = { .min = 1, .max = 3 },
313 .m = { .min = 104, .max = 138 },
314 .m1 = { .min = 17, .max = 23 },
315 .m2 = { .min = 5, .max = 11 },
316 .p = { .min = 14, .max = 42 },
317 .p1 = { .min = 2, .max = 6 },
318 .p2 = { .dot_limit = 0,
319 .p2_slow = 7, .p2_fast = 7
320 },
321 };
322
323 static const struct intel_limit intel_limits_pineview_sdvo = {
324 .dot = { .min = 20000, .max = 400000},
325 .vco = { .min = 1700000, .max = 3500000 },
326 /* Pineview's Ncounter is a ring counter */
327 .n = { .min = 3, .max = 6 },
328 .m = { .min = 2, .max = 256 },
329 /* Pineview only has one combined m divider, which we treat as m2. */
330 .m1 = { .min = 0, .max = 0 },
331 .m2 = { .min = 0, .max = 254 },
332 .p = { .min = 5, .max = 80 },
333 .p1 = { .min = 1, .max = 8 },
334 .p2 = { .dot_limit = 200000,
335 .p2_slow = 10, .p2_fast = 5 },
336 };
337
338 static const struct intel_limit intel_limits_pineview_lvds = {
339 .dot = { .min = 20000, .max = 400000 },
340 .vco = { .min = 1700000, .max = 3500000 },
341 .n = { .min = 3, .max = 6 },
342 .m = { .min = 2, .max = 256 },
343 .m1 = { .min = 0, .max = 0 },
344 .m2 = { .min = 0, .max = 254 },
345 .p = { .min = 7, .max = 112 },
346 .p1 = { .min = 1, .max = 8 },
347 .p2 = { .dot_limit = 112000,
348 .p2_slow = 14, .p2_fast = 14 },
349 };
350
351 /* Ironlake / Sandybridge
352 *
353 * We calculate clock using (register_value + 2) for N/M1/M2, so here
354 * the range value for them is (actual_value - 2).
355 */
356 static const struct intel_limit intel_limits_ironlake_dac = {
357 .dot = { .min = 25000, .max = 350000 },
358 .vco = { .min = 1760000, .max = 3510000 },
359 .n = { .min = 1, .max = 5 },
360 .m = { .min = 79, .max = 127 },
361 .m1 = { .min = 12, .max = 22 },
362 .m2 = { .min = 5, .max = 9 },
363 .p = { .min = 5, .max = 80 },
364 .p1 = { .min = 1, .max = 8 },
365 .p2 = { .dot_limit = 225000,
366 .p2_slow = 10, .p2_fast = 5 },
367 };
368
369 static const struct intel_limit intel_limits_ironlake_single_lvds = {
370 .dot = { .min = 25000, .max = 350000 },
371 .vco = { .min = 1760000, .max = 3510000 },
372 .n = { .min = 1, .max = 3 },
373 .m = { .min = 79, .max = 118 },
374 .m1 = { .min = 12, .max = 22 },
375 .m2 = { .min = 5, .max = 9 },
376 .p = { .min = 28, .max = 112 },
377 .p1 = { .min = 2, .max = 8 },
378 .p2 = { .dot_limit = 225000,
379 .p2_slow = 14, .p2_fast = 14 },
380 };
381
382 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
383 .dot = { .min = 25000, .max = 350000 },
384 .vco = { .min = 1760000, .max = 3510000 },
385 .n = { .min = 1, .max = 3 },
386 .m = { .min = 79, .max = 127 },
387 .m1 = { .min = 12, .max = 22 },
388 .m2 = { .min = 5, .max = 9 },
389 .p = { .min = 14, .max = 56 },
390 .p1 = { .min = 2, .max = 8 },
391 .p2 = { .dot_limit = 225000,
392 .p2_slow = 7, .p2_fast = 7 },
393 };
394
395 /* LVDS 100mhz refclk limits. */
396 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
397 .dot = { .min = 25000, .max = 350000 },
398 .vco = { .min = 1760000, .max = 3510000 },
399 .n = { .min = 1, .max = 2 },
400 .m = { .min = 79, .max = 126 },
401 .m1 = { .min = 12, .max = 22 },
402 .m2 = { .min = 5, .max = 9 },
403 .p = { .min = 28, .max = 112 },
404 .p1 = { .min = 2, .max = 8 },
405 .p2 = { .dot_limit = 225000,
406 .p2_slow = 14, .p2_fast = 14 },
407 };
408
409 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
410 .dot = { .min = 25000, .max = 350000 },
411 .vco = { .min = 1760000, .max = 3510000 },
412 .n = { .min = 1, .max = 3 },
413 .m = { .min = 79, .max = 126 },
414 .m1 = { .min = 12, .max = 22 },
415 .m2 = { .min = 5, .max = 9 },
416 .p = { .min = 14, .max = 42 },
417 .p1 = { .min = 2, .max = 6 },
418 .p2 = { .dot_limit = 225000,
419 .p2_slow = 7, .p2_fast = 7 },
420 };
421
422 static const struct intel_limit intel_limits_vlv = {
423 /*
424 * These are the data rate limits (measured in fast clocks)
425 * since those are the strictest limits we have. The fast
426 * clock and actual rate limits are more relaxed, so checking
427 * them would make no difference.
428 */
429 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
430 .vco = { .min = 4000000, .max = 6000000 },
431 .n = { .min = 1, .max = 7 },
432 .m1 = { .min = 2, .max = 3 },
433 .m2 = { .min = 11, .max = 156 },
434 .p1 = { .min = 2, .max = 3 },
435 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
436 };
437
438 static const struct intel_limit intel_limits_chv = {
439 /*
440 * These are the data rate limits (measured in fast clocks)
441 * since those are the strictest limits we have. The fast
442 * clock and actual rate limits are more relaxed, so checking
443 * them would make no difference.
444 */
445 .dot = { .min = 25000 * 5, .max = 540000 * 5},
446 .vco = { .min = 4800000, .max = 6480000 },
447 .n = { .min = 1, .max = 1 },
448 .m1 = { .min = 2, .max = 2 },
449 .m2 = { .min = 24 << 22, .max = 175 << 22 },
450 .p1 = { .min = 2, .max = 4 },
451 .p2 = { .p2_slow = 1, .p2_fast = 14 },
452 };
453
454 static const struct intel_limit intel_limits_bxt = {
455 /* FIXME: find real dot limits */
456 .dot = { .min = 0, .max = INT_MAX },
457 .vco = { .min = 4800000, .max = 6700000 },
458 .n = { .min = 1, .max = 1 },
459 .m1 = { .min = 2, .max = 2 },
460 /* FIXME: find real m2 limits */
461 .m2 = { .min = 2 << 22, .max = 255 << 22 },
462 .p1 = { .min = 2, .max = 4 },
463 .p2 = { .p2_slow = 1, .p2_fast = 20 },
464 };
465
466 static void
467 skl_wa_clkgate(struct drm_i915_private *dev_priv, int pipe, bool enable)
468 {
469 if (enable)
470 I915_WRITE(CLKGATE_DIS_PSL(pipe),
471 DUPS1_GATING_DIS | DUPS2_GATING_DIS);
472 else
473 I915_WRITE(CLKGATE_DIS_PSL(pipe),
474 I915_READ(CLKGATE_DIS_PSL(pipe)) &
475 ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS));
476 }
477
478 static bool
479 needs_modeset(const struct drm_crtc_state *state)
480 {
481 return drm_atomic_crtc_needs_modeset(state);
482 }
483
484 /*
485 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
486 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
487 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
488 * The helpers' return value is the rate of the clock that is fed to the
489 * display engine's pipe which can be the above fast dot clock rate or a
490 * divided-down version of it.
491 */
492 /* m1 is reserved as 0 in Pineview, n is a ring counter */
493 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
494 {
495 clock->m = clock->m2 + 2;
496 clock->p = clock->p1 * clock->p2;
497 if (WARN_ON(clock->n == 0 || clock->p == 0))
498 return 0;
499 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
500 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
501
502 return clock->dot;
503 }
504
505 static u32 i9xx_dpll_compute_m(struct dpll *dpll)
506 {
507 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
508 }
509
510 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
511 {
512 clock->m = i9xx_dpll_compute_m(clock);
513 clock->p = clock->p1 * clock->p2;
514 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
515 return 0;
516 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
517 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
518
519 return clock->dot;
520 }
521
522 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
523 {
524 clock->m = clock->m1 * clock->m2;
525 clock->p = clock->p1 * clock->p2;
526 if (WARN_ON(clock->n == 0 || clock->p == 0))
527 return 0;
528 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
529 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
530
531 return clock->dot / 5;
532 }
533
534 int chv_calc_dpll_params(int refclk, struct dpll *clock)
535 {
536 clock->m = clock->m1 * clock->m2;
537 clock->p = clock->p1 * clock->p2;
538 if (WARN_ON(clock->n == 0 || clock->p == 0))
539 return 0;
540 clock->vco = DIV_ROUND_CLOSEST_ULL((u64)refclk * clock->m,
541 clock->n << 22);
542 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
543
544 return clock->dot / 5;
545 }
546
547 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
548
549 /*
550 * Returns whether the given set of divisors are valid for a given refclk with
551 * the given connectors.
552 */
553 static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
554 const struct intel_limit *limit,
555 const struct dpll *clock)
556 {
557 if (clock->n < limit->n.min || limit->n.max < clock->n)
558 INTELPllInvalid("n out of range\n");
559 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
560 INTELPllInvalid("p1 out of range\n");
561 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
562 INTELPllInvalid("m2 out of range\n");
563 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
564 INTELPllInvalid("m1 out of range\n");
565
566 if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
567 !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
568 if (clock->m1 <= clock->m2)
569 INTELPllInvalid("m1 <= m2\n");
570
571 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
572 !IS_GEN9_LP(dev_priv)) {
573 if (clock->p < limit->p.min || limit->p.max < clock->p)
574 INTELPllInvalid("p out of range\n");
575 if (clock->m < limit->m.min || limit->m.max < clock->m)
576 INTELPllInvalid("m out of range\n");
577 }
578
579 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
580 INTELPllInvalid("vco out of range\n");
581 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
582 * connector, etc., rather than just a single range.
583 */
584 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
585 INTELPllInvalid("dot out of range\n");
586
587 return true;
588 }
589
590 static int
591 i9xx_select_p2_div(const struct intel_limit *limit,
592 const struct intel_crtc_state *crtc_state,
593 int target)
594 {
595 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
596
597 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
598 /*
599 * For LVDS just rely on its current settings for dual-channel.
600 * We haven't figured out how to reliably set up different
601 * single/dual channel state, if we even can.
602 */
603 if (intel_is_dual_link_lvds(dev_priv))
604 return limit->p2.p2_fast;
605 else
606 return limit->p2.p2_slow;
607 } else {
608 if (target < limit->p2.dot_limit)
609 return limit->p2.p2_slow;
610 else
611 return limit->p2.p2_fast;
612 }
613 }
614
615 /*
616 * Returns a set of divisors for the desired target clock with the given
617 * refclk, or FALSE. The returned values represent the clock equation:
618 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
619 *
620 * Target and reference clocks are specified in kHz.
621 *
622 * If match_clock is provided, then best_clock P divider must match the P
623 * divider from @match_clock used for LVDS downclocking.
624 */
625 static bool
626 i9xx_find_best_dpll(const struct intel_limit *limit,
627 struct intel_crtc_state *crtc_state,
628 int target, int refclk, struct dpll *match_clock,
629 struct dpll *best_clock)
630 {
631 struct drm_device *dev = crtc_state->base.crtc->dev;
632 struct dpll clock;
633 int err = target;
634
635 memset(best_clock, 0, sizeof(*best_clock));
636
637 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
638
639 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
640 clock.m1++) {
641 for (clock.m2 = limit->m2.min;
642 clock.m2 <= limit->m2.max; clock.m2++) {
643 if (clock.m2 >= clock.m1)
644 break;
645 for (clock.n = limit->n.min;
646 clock.n <= limit->n.max; clock.n++) {
647 for (clock.p1 = limit->p1.min;
648 clock.p1 <= limit->p1.max; clock.p1++) {
649 int this_err;
650
651 i9xx_calc_dpll_params(refclk, &clock);
652 if (!intel_PLL_is_valid(to_i915(dev),
653 limit,
654 &clock))
655 continue;
656 if (match_clock &&
657 clock.p != match_clock->p)
658 continue;
659
660 this_err = abs(clock.dot - target);
661 if (this_err < err) {
662 *best_clock = clock;
663 err = this_err;
664 }
665 }
666 }
667 }
668 }
669
670 return (err != target);
671 }
672
673 /*
674 * Returns a set of divisors for the desired target clock with the given
675 * refclk, or FALSE. The returned values represent the clock equation:
676 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
677 *
678 * Target and reference clocks are specified in kHz.
679 *
680 * If match_clock is provided, then best_clock P divider must match the P
681 * divider from @match_clock used for LVDS downclocking.
682 */
683 static bool
684 pnv_find_best_dpll(const struct intel_limit *limit,
685 struct intel_crtc_state *crtc_state,
686 int target, int refclk, struct dpll *match_clock,
687 struct dpll *best_clock)
688 {
689 struct drm_device *dev = crtc_state->base.crtc->dev;
690 struct dpll clock;
691 int err = target;
692
693 memset(best_clock, 0, sizeof(*best_clock));
694
695 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
696
697 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
698 clock.m1++) {
699 for (clock.m2 = limit->m2.min;
700 clock.m2 <= limit->m2.max; clock.m2++) {
701 for (clock.n = limit->n.min;
702 clock.n <= limit->n.max; clock.n++) {
703 for (clock.p1 = limit->p1.min;
704 clock.p1 <= limit->p1.max; clock.p1++) {
705 int this_err;
706
707 pnv_calc_dpll_params(refclk, &clock);
708 if (!intel_PLL_is_valid(to_i915(dev),
709 limit,
710 &clock))
711 continue;
712 if (match_clock &&
713 clock.p != match_clock->p)
714 continue;
715
716 this_err = abs(clock.dot - target);
717 if (this_err < err) {
718 *best_clock = clock;
719 err = this_err;
720 }
721 }
722 }
723 }
724 }
725
726 return (err != target);
727 }
728
729 /*
730 * Returns a set of divisors for the desired target clock with the given
731 * refclk, or FALSE. The returned values represent the clock equation:
732 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
733 *
734 * Target and reference clocks are specified in kHz.
735 *
736 * If match_clock is provided, then best_clock P divider must match the P
737 * divider from @match_clock used for LVDS downclocking.
738 */
739 static bool
740 g4x_find_best_dpll(const struct intel_limit *limit,
741 struct intel_crtc_state *crtc_state,
742 int target, int refclk, struct dpll *match_clock,
743 struct dpll *best_clock)
744 {
745 struct drm_device *dev = crtc_state->base.crtc->dev;
746 struct dpll clock;
747 int max_n;
748 bool found = false;
749 /* approximately equals target * 0.00585 */
750 int err_most = (target >> 8) + (target >> 9);
751
752 memset(best_clock, 0, sizeof(*best_clock));
753
754 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
755
756 max_n = limit->n.max;
757 /* based on hardware requirement, prefer smaller n to precision */
758 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
759 /* based on hardware requirement, prefere larger m1,m2 */
760 for (clock.m1 = limit->m1.max;
761 clock.m1 >= limit->m1.min; clock.m1--) {
762 for (clock.m2 = limit->m2.max;
763 clock.m2 >= limit->m2.min; clock.m2--) {
764 for (clock.p1 = limit->p1.max;
765 clock.p1 >= limit->p1.min; clock.p1--) {
766 int this_err;
767
768 i9xx_calc_dpll_params(refclk, &clock);
769 if (!intel_PLL_is_valid(to_i915(dev),
770 limit,
771 &clock))
772 continue;
773
774 this_err = abs(clock.dot - target);
775 if (this_err < err_most) {
776 *best_clock = clock;
777 err_most = this_err;
778 max_n = clock.n;
779 found = true;
780 }
781 }
782 }
783 }
784 }
785 return found;
786 }
787
788 /*
789 * Check if the calculated PLL configuration is more optimal compared to the
790 * best configuration and error found so far. Return the calculated error.
791 */
792 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
793 const struct dpll *calculated_clock,
794 const struct dpll *best_clock,
795 unsigned int best_error_ppm,
796 unsigned int *error_ppm)
797 {
798 /*
799 * For CHV ignore the error and consider only the P value.
800 * Prefer a bigger P value based on HW requirements.
801 */
802 if (IS_CHERRYVIEW(to_i915(dev))) {
803 *error_ppm = 0;
804
805 return calculated_clock->p > best_clock->p;
806 }
807
808 if (WARN_ON_ONCE(!target_freq))
809 return false;
810
811 *error_ppm = div_u64(1000000ULL *
812 abs(target_freq - calculated_clock->dot),
813 target_freq);
814 /*
815 * Prefer a better P value over a better (smaller) error if the error
816 * is small. Ensure this preference for future configurations too by
817 * setting the error to 0.
818 */
819 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
820 *error_ppm = 0;
821
822 return true;
823 }
824
825 return *error_ppm + 10 < best_error_ppm;
826 }
827
828 /*
829 * Returns a set of divisors for the desired target clock with the given
830 * refclk, or FALSE. The returned values represent the clock equation:
831 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
832 */
833 static bool
834 vlv_find_best_dpll(const struct intel_limit *limit,
835 struct intel_crtc_state *crtc_state,
836 int target, int refclk, struct dpll *match_clock,
837 struct dpll *best_clock)
838 {
839 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
840 struct drm_device *dev = crtc->base.dev;
841 struct dpll clock;
842 unsigned int bestppm = 1000000;
843 /* min update 19.2 MHz */
844 int max_n = min(limit->n.max, refclk / 19200);
845 bool found = false;
846
847 target *= 5; /* fast clock */
848
849 memset(best_clock, 0, sizeof(*best_clock));
850
851 /* based on hardware requirement, prefer smaller n to precision */
852 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
853 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
854 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
855 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
856 clock.p = clock.p1 * clock.p2;
857 /* based on hardware requirement, prefer bigger m1,m2 values */
858 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
859 unsigned int ppm;
860
861 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
862 refclk * clock.m1);
863
864 vlv_calc_dpll_params(refclk, &clock);
865
866 if (!intel_PLL_is_valid(to_i915(dev),
867 limit,
868 &clock))
869 continue;
870
871 if (!vlv_PLL_is_optimal(dev, target,
872 &clock,
873 best_clock,
874 bestppm, &ppm))
875 continue;
876
877 *best_clock = clock;
878 bestppm = ppm;
879 found = true;
880 }
881 }
882 }
883 }
884
885 return found;
886 }
887
888 /*
889 * Returns a set of divisors for the desired target clock with the given
890 * refclk, or FALSE. The returned values represent the clock equation:
891 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
892 */
893 static bool
894 chv_find_best_dpll(const struct intel_limit *limit,
895 struct intel_crtc_state *crtc_state,
896 int target, int refclk, struct dpll *match_clock,
897 struct dpll *best_clock)
898 {
899 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
900 struct drm_device *dev = crtc->base.dev;
901 unsigned int best_error_ppm;
902 struct dpll clock;
903 u64 m2;
904 int found = false;
905
906 memset(best_clock, 0, sizeof(*best_clock));
907 best_error_ppm = 1000000;
908
909 /*
910 * Based on hardware doc, the n always set to 1, and m1 always
911 * set to 2. If requires to support 200Mhz refclk, we need to
912 * revisit this because n may not 1 anymore.
913 */
914 clock.n = 1, clock.m1 = 2;
915 target *= 5; /* fast clock */
916
917 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
918 for (clock.p2 = limit->p2.p2_fast;
919 clock.p2 >= limit->p2.p2_slow;
920 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
921 unsigned int error_ppm;
922
923 clock.p = clock.p1 * clock.p2;
924
925 m2 = DIV_ROUND_CLOSEST_ULL(((u64)target * clock.p *
926 clock.n) << 22, refclk * clock.m1);
927
928 if (m2 > INT_MAX/clock.m1)
929 continue;
930
931 clock.m2 = m2;
932
933 chv_calc_dpll_params(refclk, &clock);
934
935 if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
936 continue;
937
938 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
939 best_error_ppm, &error_ppm))
940 continue;
941
942 *best_clock = clock;
943 best_error_ppm = error_ppm;
944 found = true;
945 }
946 }
947
948 return found;
949 }
950
951 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
952 struct dpll *best_clock)
953 {
954 int refclk = 100000;
955 const struct intel_limit *limit = &intel_limits_bxt;
956
957 return chv_find_best_dpll(limit, crtc_state,
958 crtc_state->port_clock, refclk,
959 NULL, best_clock);
960 }
961
962 bool intel_crtc_active(struct intel_crtc *crtc)
963 {
964 /* Be paranoid as we can arrive here with only partial
965 * state retrieved from the hardware during setup.
966 *
967 * We can ditch the adjusted_mode.crtc_clock check as soon
968 * as Haswell has gained clock readout/fastboot support.
969 *
970 * We can ditch the crtc->primary->state->fb check as soon as we can
971 * properly reconstruct framebuffers.
972 *
973 * FIXME: The intel_crtc->active here should be switched to
974 * crtc->state->active once we have proper CRTC states wired up
975 * for atomic.
976 */
977 return crtc->active && crtc->base.primary->state->fb &&
978 crtc->config->base.adjusted_mode.crtc_clock;
979 }
980
981 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
982 enum pipe pipe)
983 {
984 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
985
986 return crtc->config->cpu_transcoder;
987 }
988
989 static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv,
990 enum pipe pipe)
991 {
992 i915_reg_t reg = PIPEDSL(pipe);
993 u32 line1, line2;
994 u32 line_mask;
995
996 if (IS_GEN(dev_priv, 2))
997 line_mask = DSL_LINEMASK_GEN2;
998 else
999 line_mask = DSL_LINEMASK_GEN3;
1000
1001 line1 = I915_READ(reg) & line_mask;
1002 msleep(5);
1003 line2 = I915_READ(reg) & line_mask;
1004
1005 return line1 != line2;
1006 }
1007
1008 static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state)
1009 {
1010 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1011 enum pipe pipe = crtc->pipe;
1012
1013 /* Wait for the display line to settle/start moving */
1014 if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100))
1015 DRM_ERROR("pipe %c scanline %s wait timed out\n",
1016 pipe_name(pipe), onoff(state));
1017 }
1018
1019 static void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc)
1020 {
1021 wait_for_pipe_scanline_moving(crtc, false);
1022 }
1023
1024 static void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc)
1025 {
1026 wait_for_pipe_scanline_moving(crtc, true);
1027 }
1028
1029 static void
1030 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
1031 {
1032 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
1033 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1034
1035 if (INTEL_GEN(dev_priv) >= 4) {
1036 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
1037 i915_reg_t reg = PIPECONF(cpu_transcoder);
1038
1039 /* Wait for the Pipe State to go off */
1040 if (intel_wait_for_register(&dev_priv->uncore,
1041 reg, I965_PIPECONF_ACTIVE, 0,
1042 100))
1043 WARN(1, "pipe_off wait timed out\n");
1044 } else {
1045 intel_wait_for_pipe_scanline_stopped(crtc);
1046 }
1047 }
1048
1049 /* Only for pre-ILK configs */
1050 void assert_pll(struct drm_i915_private *dev_priv,
1051 enum pipe pipe, bool state)
1052 {
1053 u32 val;
1054 bool cur_state;
1055
1056 val = I915_READ(DPLL(pipe));
1057 cur_state = !!(val & DPLL_VCO_ENABLE);
1058 I915_STATE_WARN(cur_state != state,
1059 "PLL state assertion failure (expected %s, current %s)\n",
1060 onoff(state), onoff(cur_state));
1061 }
1062
1063 /* XXX: the dsi pll is shared between MIPI DSI ports */
1064 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1065 {
1066 u32 val;
1067 bool cur_state;
1068
1069 mutex_lock(&dev_priv->sb_lock);
1070 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1071 mutex_unlock(&dev_priv->sb_lock);
1072
1073 cur_state = val & DSI_PLL_VCO_EN;
1074 I915_STATE_WARN(cur_state != state,
1075 "DSI PLL state assertion failure (expected %s, current %s)\n",
1076 onoff(state), onoff(cur_state));
1077 }
1078
1079 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1080 enum pipe pipe, bool state)
1081 {
1082 bool cur_state;
1083 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1084 pipe);
1085
1086 if (HAS_DDI(dev_priv)) {
1087 /* DDI does not have a specific FDI_TX register */
1088 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1089 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1090 } else {
1091 u32 val = I915_READ(FDI_TX_CTL(pipe));
1092 cur_state = !!(val & FDI_TX_ENABLE);
1093 }
1094 I915_STATE_WARN(cur_state != state,
1095 "FDI TX state assertion failure (expected %s, current %s)\n",
1096 onoff(state), onoff(cur_state));
1097 }
1098 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1099 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1100
1101 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1102 enum pipe pipe, bool state)
1103 {
1104 u32 val;
1105 bool cur_state;
1106
1107 val = I915_READ(FDI_RX_CTL(pipe));
1108 cur_state = !!(val & FDI_RX_ENABLE);
1109 I915_STATE_WARN(cur_state != state,
1110 "FDI RX state assertion failure (expected %s, current %s)\n",
1111 onoff(state), onoff(cur_state));
1112 }
1113 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1114 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1115
1116 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1117 enum pipe pipe)
1118 {
1119 u32 val;
1120
1121 /* ILK FDI PLL is always enabled */
1122 if (IS_GEN(dev_priv, 5))
1123 return;
1124
1125 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1126 if (HAS_DDI(dev_priv))
1127 return;
1128
1129 val = I915_READ(FDI_TX_CTL(pipe));
1130 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1131 }
1132
1133 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1134 enum pipe pipe, bool state)
1135 {
1136 u32 val;
1137 bool cur_state;
1138
1139 val = I915_READ(FDI_RX_CTL(pipe));
1140 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1141 I915_STATE_WARN(cur_state != state,
1142 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1143 onoff(state), onoff(cur_state));
1144 }
1145
1146 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1147 {
1148 i915_reg_t pp_reg;
1149 u32 val;
1150 enum pipe panel_pipe = INVALID_PIPE;
1151 bool locked = true;
1152
1153 if (WARN_ON(HAS_DDI(dev_priv)))
1154 return;
1155
1156 if (HAS_PCH_SPLIT(dev_priv)) {
1157 u32 port_sel;
1158
1159 pp_reg = PP_CONTROL(0);
1160 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1161
1162 switch (port_sel) {
1163 case PANEL_PORT_SELECT_LVDS:
1164 intel_lvds_port_enabled(dev_priv, PCH_LVDS, &panel_pipe);
1165 break;
1166 case PANEL_PORT_SELECT_DPA:
1167 intel_dp_port_enabled(dev_priv, DP_A, PORT_A, &panel_pipe);
1168 break;
1169 case PANEL_PORT_SELECT_DPC:
1170 intel_dp_port_enabled(dev_priv, PCH_DP_C, PORT_C, &panel_pipe);
1171 break;
1172 case PANEL_PORT_SELECT_DPD:
1173 intel_dp_port_enabled(dev_priv, PCH_DP_D, PORT_D, &panel_pipe);
1174 break;
1175 default:
1176 MISSING_CASE(port_sel);
1177 break;
1178 }
1179 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1180 /* presumably write lock depends on pipe, not port select */
1181 pp_reg = PP_CONTROL(pipe);
1182 panel_pipe = pipe;
1183 } else {
1184 u32 port_sel;
1185
1186 pp_reg = PP_CONTROL(0);
1187 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1188
1189 WARN_ON(port_sel != PANEL_PORT_SELECT_LVDS);
1190 intel_lvds_port_enabled(dev_priv, LVDS, &panel_pipe);
1191 }
1192
1193 val = I915_READ(pp_reg);
1194 if (!(val & PANEL_POWER_ON) ||
1195 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1196 locked = false;
1197
1198 I915_STATE_WARN(panel_pipe == pipe && locked,
1199 "panel assertion failure, pipe %c regs locked\n",
1200 pipe_name(pipe));
1201 }
1202
1203 void assert_pipe(struct drm_i915_private *dev_priv,
1204 enum pipe pipe, bool state)
1205 {
1206 bool cur_state;
1207 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1208 pipe);
1209 enum intel_display_power_domain power_domain;
1210 intel_wakeref_t wakeref;
1211
1212 /* we keep both pipes enabled on 830 */
1213 if (IS_I830(dev_priv))
1214 state = true;
1215
1216 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1217 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
1218 if (wakeref) {
1219 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1220 cur_state = !!(val & PIPECONF_ENABLE);
1221
1222 intel_display_power_put(dev_priv, power_domain, wakeref);
1223 } else {
1224 cur_state = false;
1225 }
1226
1227 I915_STATE_WARN(cur_state != state,
1228 "pipe %c assertion failure (expected %s, current %s)\n",
1229 pipe_name(pipe), onoff(state), onoff(cur_state));
1230 }
1231
1232 static void assert_plane(struct intel_plane *plane, bool state)
1233 {
1234 enum pipe pipe;
1235 bool cur_state;
1236
1237 cur_state = plane->get_hw_state(plane, &pipe);
1238
1239 I915_STATE_WARN(cur_state != state,
1240 "%s assertion failure (expected %s, current %s)\n",
1241 plane->base.name, onoff(state), onoff(cur_state));
1242 }
1243
1244 #define assert_plane_enabled(p) assert_plane(p, true)
1245 #define assert_plane_disabled(p) assert_plane(p, false)
1246
1247 static void assert_planes_disabled(struct intel_crtc *crtc)
1248 {
1249 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1250 struct intel_plane *plane;
1251
1252 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)
1253 assert_plane_disabled(plane);
1254 }
1255
1256 static void assert_vblank_disabled(struct drm_crtc *crtc)
1257 {
1258 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1259 drm_crtc_vblank_put(crtc);
1260 }
1261
1262 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1263 enum pipe pipe)
1264 {
1265 u32 val;
1266 bool enabled;
1267
1268 val = I915_READ(PCH_TRANSCONF(pipe));
1269 enabled = !!(val & TRANS_ENABLE);
1270 I915_STATE_WARN(enabled,
1271 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1272 pipe_name(pipe));
1273 }
1274
1275 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1276 enum pipe pipe, enum port port,
1277 i915_reg_t dp_reg)
1278 {
1279 enum pipe port_pipe;
1280 bool state;
1281
1282 state = intel_dp_port_enabled(dev_priv, dp_reg, port, &port_pipe);
1283
1284 I915_STATE_WARN(state && port_pipe == pipe,
1285 "PCH DP %c enabled on transcoder %c, should be disabled\n",
1286 port_name(port), pipe_name(pipe));
1287
1288 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
1289 "IBX PCH DP %c still using transcoder B\n",
1290 port_name(port));
1291 }
1292
1293 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1294 enum pipe pipe, enum port port,
1295 i915_reg_t hdmi_reg)
1296 {
1297 enum pipe port_pipe;
1298 bool state;
1299
1300 state = intel_sdvo_port_enabled(dev_priv, hdmi_reg, &port_pipe);
1301
1302 I915_STATE_WARN(state && port_pipe == pipe,
1303 "PCH HDMI %c enabled on transcoder %c, should be disabled\n",
1304 port_name(port), pipe_name(pipe));
1305
1306 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
1307 "IBX PCH HDMI %c still using transcoder B\n",
1308 port_name(port));
1309 }
1310
1311 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1312 enum pipe pipe)
1313 {
1314 enum pipe port_pipe;
1315
1316 assert_pch_dp_disabled(dev_priv, pipe, PORT_B, PCH_DP_B);
1317 assert_pch_dp_disabled(dev_priv, pipe, PORT_C, PCH_DP_C);
1318 assert_pch_dp_disabled(dev_priv, pipe, PORT_D, PCH_DP_D);
1319
1320 I915_STATE_WARN(intel_crt_port_enabled(dev_priv, PCH_ADPA, &port_pipe) &&
1321 port_pipe == pipe,
1322 "PCH VGA enabled on transcoder %c, should be disabled\n",
1323 pipe_name(pipe));
1324
1325 I915_STATE_WARN(intel_lvds_port_enabled(dev_priv, PCH_LVDS, &port_pipe) &&
1326 port_pipe == pipe,
1327 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1328 pipe_name(pipe));
1329
1330 /* PCH SDVOB multiplex with HDMIB */
1331 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_B, PCH_HDMIB);
1332 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_C, PCH_HDMIC);
1333 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_D, PCH_HDMID);
1334 }
1335
1336 static void _vlv_enable_pll(struct intel_crtc *crtc,
1337 const struct intel_crtc_state *pipe_config)
1338 {
1339 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1340 enum pipe pipe = crtc->pipe;
1341
1342 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1343 POSTING_READ(DPLL(pipe));
1344 udelay(150);
1345
1346 if (intel_wait_for_register(&dev_priv->uncore,
1347 DPLL(pipe),
1348 DPLL_LOCK_VLV,
1349 DPLL_LOCK_VLV,
1350 1))
1351 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1352 }
1353
1354 static void vlv_enable_pll(struct intel_crtc *crtc,
1355 const struct intel_crtc_state *pipe_config)
1356 {
1357 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1358 enum pipe pipe = crtc->pipe;
1359
1360 assert_pipe_disabled(dev_priv, pipe);
1361
1362 /* PLL is protected by panel, make sure we can write it */
1363 assert_panel_unlocked(dev_priv, pipe);
1364
1365 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1366 _vlv_enable_pll(crtc, pipe_config);
1367
1368 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1369 POSTING_READ(DPLL_MD(pipe));
1370 }
1371
1372
1373 static void _chv_enable_pll(struct intel_crtc *crtc,
1374 const struct intel_crtc_state *pipe_config)
1375 {
1376 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1377 enum pipe pipe = crtc->pipe;
1378 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1379 u32 tmp;
1380
1381 mutex_lock(&dev_priv->sb_lock);
1382
1383 /* Enable back the 10bit clock to display controller */
1384 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1385 tmp |= DPIO_DCLKP_EN;
1386 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1387
1388 mutex_unlock(&dev_priv->sb_lock);
1389
1390 /*
1391 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1392 */
1393 udelay(1);
1394
1395 /* Enable PLL */
1396 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1397
1398 /* Check PLL is locked */
1399 if (intel_wait_for_register(&dev_priv->uncore,
1400 DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1401 1))
1402 DRM_ERROR("PLL %d failed to lock\n", pipe);
1403 }
1404
1405 static void chv_enable_pll(struct intel_crtc *crtc,
1406 const struct intel_crtc_state *pipe_config)
1407 {
1408 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1409 enum pipe pipe = crtc->pipe;
1410
1411 assert_pipe_disabled(dev_priv, pipe);
1412
1413 /* PLL is protected by panel, make sure we can write it */
1414 assert_panel_unlocked(dev_priv, pipe);
1415
1416 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1417 _chv_enable_pll(crtc, pipe_config);
1418
1419 if (pipe != PIPE_A) {
1420 /*
1421 * WaPixelRepeatModeFixForC0:chv
1422 *
1423 * DPLLCMD is AWOL. Use chicken bits to propagate
1424 * the value from DPLLBMD to either pipe B or C.
1425 */
1426 I915_WRITE(CBR4_VLV, CBR_DPLLBMD_PIPE(pipe));
1427 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1428 I915_WRITE(CBR4_VLV, 0);
1429 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1430
1431 /*
1432 * DPLLB VGA mode also seems to cause problems.
1433 * We should always have it disabled.
1434 */
1435 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1436 } else {
1437 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1438 POSTING_READ(DPLL_MD(pipe));
1439 }
1440 }
1441
1442 static bool i9xx_has_pps(struct drm_i915_private *dev_priv)
1443 {
1444 if (IS_I830(dev_priv))
1445 return false;
1446
1447 return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
1448 }
1449
1450 static void i9xx_enable_pll(struct intel_crtc *crtc,
1451 const struct intel_crtc_state *crtc_state)
1452 {
1453 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1454 i915_reg_t reg = DPLL(crtc->pipe);
1455 u32 dpll = crtc_state->dpll_hw_state.dpll;
1456 int i;
1457
1458 assert_pipe_disabled(dev_priv, crtc->pipe);
1459
1460 /* PLL is protected by panel, make sure we can write it */
1461 if (i9xx_has_pps(dev_priv))
1462 assert_panel_unlocked(dev_priv, crtc->pipe);
1463
1464 /*
1465 * Apparently we need to have VGA mode enabled prior to changing
1466 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1467 * dividers, even though the register value does change.
1468 */
1469 I915_WRITE(reg, dpll & ~DPLL_VGA_MODE_DIS);
1470 I915_WRITE(reg, dpll);
1471
1472 /* Wait for the clocks to stabilize. */
1473 POSTING_READ(reg);
1474 udelay(150);
1475
1476 if (INTEL_GEN(dev_priv) >= 4) {
1477 I915_WRITE(DPLL_MD(crtc->pipe),
1478 crtc_state->dpll_hw_state.dpll_md);
1479 } else {
1480 /* The pixel multiplier can only be updated once the
1481 * DPLL is enabled and the clocks are stable.
1482 *
1483 * So write it again.
1484 */
1485 I915_WRITE(reg, dpll);
1486 }
1487
1488 /* We do this three times for luck */
1489 for (i = 0; i < 3; i++) {
1490 I915_WRITE(reg, dpll);
1491 POSTING_READ(reg);
1492 udelay(150); /* wait for warmup */
1493 }
1494 }
1495
1496 static void i9xx_disable_pll(const struct intel_crtc_state *crtc_state)
1497 {
1498 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1499 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1500 enum pipe pipe = crtc->pipe;
1501
1502 /* Don't disable pipe or pipe PLLs if needed */
1503 if (IS_I830(dev_priv))
1504 return;
1505
1506 /* Make sure the pipe isn't still relying on us */
1507 assert_pipe_disabled(dev_priv, pipe);
1508
1509 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1510 POSTING_READ(DPLL(pipe));
1511 }
1512
1513 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1514 {
1515 u32 val;
1516
1517 /* Make sure the pipe isn't still relying on us */
1518 assert_pipe_disabled(dev_priv, pipe);
1519
1520 val = DPLL_INTEGRATED_REF_CLK_VLV |
1521 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1522 if (pipe != PIPE_A)
1523 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1524
1525 I915_WRITE(DPLL(pipe), val);
1526 POSTING_READ(DPLL(pipe));
1527 }
1528
1529 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1530 {
1531 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1532 u32 val;
1533
1534 /* Make sure the pipe isn't still relying on us */
1535 assert_pipe_disabled(dev_priv, pipe);
1536
1537 val = DPLL_SSC_REF_CLK_CHV |
1538 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1539 if (pipe != PIPE_A)
1540 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1541
1542 I915_WRITE(DPLL(pipe), val);
1543 POSTING_READ(DPLL(pipe));
1544
1545 mutex_lock(&dev_priv->sb_lock);
1546
1547 /* Disable 10bit clock to display controller */
1548 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1549 val &= ~DPIO_DCLKP_EN;
1550 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1551
1552 mutex_unlock(&dev_priv->sb_lock);
1553 }
1554
1555 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1556 struct intel_digital_port *dport,
1557 unsigned int expected_mask)
1558 {
1559 u32 port_mask;
1560 i915_reg_t dpll_reg;
1561
1562 switch (dport->base.port) {
1563 case PORT_B:
1564 port_mask = DPLL_PORTB_READY_MASK;
1565 dpll_reg = DPLL(0);
1566 break;
1567 case PORT_C:
1568 port_mask = DPLL_PORTC_READY_MASK;
1569 dpll_reg = DPLL(0);
1570 expected_mask <<= 4;
1571 break;
1572 case PORT_D:
1573 port_mask = DPLL_PORTD_READY_MASK;
1574 dpll_reg = DPIO_PHY_STATUS;
1575 break;
1576 default:
1577 BUG();
1578 }
1579
1580 if (intel_wait_for_register(&dev_priv->uncore,
1581 dpll_reg, port_mask, expected_mask,
1582 1000))
1583 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1584 port_name(dport->base.port),
1585 I915_READ(dpll_reg) & port_mask, expected_mask);
1586 }
1587
1588 static void ironlake_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
1589 {
1590 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1591 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1592 enum pipe pipe = crtc->pipe;
1593 i915_reg_t reg;
1594 u32 val, pipeconf_val;
1595
1596 /* Make sure PCH DPLL is enabled */
1597 assert_shared_dpll_enabled(dev_priv, crtc_state->shared_dpll);
1598
1599 /* FDI must be feeding us bits for PCH ports */
1600 assert_fdi_tx_enabled(dev_priv, pipe);
1601 assert_fdi_rx_enabled(dev_priv, pipe);
1602
1603 if (HAS_PCH_CPT(dev_priv)) {
1604 /* Workaround: Set the timing override bit before enabling the
1605 * pch transcoder. */
1606 reg = TRANS_CHICKEN2(pipe);
1607 val = I915_READ(reg);
1608 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1609 I915_WRITE(reg, val);
1610 }
1611
1612 reg = PCH_TRANSCONF(pipe);
1613 val = I915_READ(reg);
1614 pipeconf_val = I915_READ(PIPECONF(pipe));
1615
1616 if (HAS_PCH_IBX(dev_priv)) {
1617 /*
1618 * Make the BPC in transcoder be consistent with
1619 * that in pipeconf reg. For HDMI we must use 8bpc
1620 * here for both 8bpc and 12bpc.
1621 */
1622 val &= ~PIPECONF_BPC_MASK;
1623 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1624 val |= PIPECONF_8BPC;
1625 else
1626 val |= pipeconf_val & PIPECONF_BPC_MASK;
1627 }
1628
1629 val &= ~TRANS_INTERLACE_MASK;
1630 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) {
1631 if (HAS_PCH_IBX(dev_priv) &&
1632 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
1633 val |= TRANS_LEGACY_INTERLACED_ILK;
1634 else
1635 val |= TRANS_INTERLACED;
1636 } else {
1637 val |= TRANS_PROGRESSIVE;
1638 }
1639
1640 I915_WRITE(reg, val | TRANS_ENABLE);
1641 if (intel_wait_for_register(&dev_priv->uncore,
1642 reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1643 100))
1644 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1645 }
1646
1647 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1648 enum transcoder cpu_transcoder)
1649 {
1650 u32 val, pipeconf_val;
1651
1652 /* FDI must be feeding us bits for PCH ports */
1653 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1654 assert_fdi_rx_enabled(dev_priv, PIPE_A);
1655
1656 /* Workaround: set timing override bit. */
1657 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1658 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1659 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1660
1661 val = TRANS_ENABLE;
1662 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1663
1664 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1665 PIPECONF_INTERLACED_ILK)
1666 val |= TRANS_INTERLACED;
1667 else
1668 val |= TRANS_PROGRESSIVE;
1669
1670 I915_WRITE(LPT_TRANSCONF, val);
1671 if (intel_wait_for_register(&dev_priv->uncore,
1672 LPT_TRANSCONF,
1673 TRANS_STATE_ENABLE,
1674 TRANS_STATE_ENABLE,
1675 100))
1676 DRM_ERROR("Failed to enable PCH transcoder\n");
1677 }
1678
1679 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1680 enum pipe pipe)
1681 {
1682 i915_reg_t reg;
1683 u32 val;
1684
1685 /* FDI relies on the transcoder */
1686 assert_fdi_tx_disabled(dev_priv, pipe);
1687 assert_fdi_rx_disabled(dev_priv, pipe);
1688
1689 /* Ports must be off as well */
1690 assert_pch_ports_disabled(dev_priv, pipe);
1691
1692 reg = PCH_TRANSCONF(pipe);
1693 val = I915_READ(reg);
1694 val &= ~TRANS_ENABLE;
1695 I915_WRITE(reg, val);
1696 /* wait for PCH transcoder off, transcoder state */
1697 if (intel_wait_for_register(&dev_priv->uncore,
1698 reg, TRANS_STATE_ENABLE, 0,
1699 50))
1700 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1701
1702 if (HAS_PCH_CPT(dev_priv)) {
1703 /* Workaround: Clear the timing override chicken bit again. */
1704 reg = TRANS_CHICKEN2(pipe);
1705 val = I915_READ(reg);
1706 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1707 I915_WRITE(reg, val);
1708 }
1709 }
1710
1711 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1712 {
1713 u32 val;
1714
1715 val = I915_READ(LPT_TRANSCONF);
1716 val &= ~TRANS_ENABLE;
1717 I915_WRITE(LPT_TRANSCONF, val);
1718 /* wait for PCH transcoder off, transcoder state */
1719 if (intel_wait_for_register(&dev_priv->uncore,
1720 LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1721 50))
1722 DRM_ERROR("Failed to disable PCH transcoder\n");
1723
1724 /* Workaround: clear timing override bit. */
1725 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1726 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1727 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1728 }
1729
1730 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1731 {
1732 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1733
1734 if (HAS_PCH_LPT(dev_priv))
1735 return PIPE_A;
1736 else
1737 return crtc->pipe;
1738 }
1739
1740 static u32 intel_crtc_max_vblank_count(const struct intel_crtc_state *crtc_state)
1741 {
1742 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1743
1744 /*
1745 * On i965gm the hardware frame counter reads
1746 * zero when the TV encoder is enabled :(
1747 */
1748 if (IS_I965GM(dev_priv) &&
1749 (crtc_state->output_types & BIT(INTEL_OUTPUT_TVOUT)))
1750 return 0;
1751
1752 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
1753 return 0xffffffff; /* full 32 bit counter */
1754 else if (INTEL_GEN(dev_priv) >= 3)
1755 return 0xffffff; /* only 24 bits of frame count */
1756 else
1757 return 0; /* Gen2 doesn't have a hardware frame counter */
1758 }
1759
1760 static void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state)
1761 {
1762 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1763
1764 drm_crtc_set_max_vblank_count(&crtc->base,
1765 intel_crtc_max_vblank_count(crtc_state));
1766 drm_crtc_vblank_on(&crtc->base);
1767 }
1768
1769 static void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state)
1770 {
1771 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
1772 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1773 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
1774 enum pipe pipe = crtc->pipe;
1775 i915_reg_t reg;
1776 u32 val;
1777
1778 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1779
1780 assert_planes_disabled(crtc);
1781
1782 /*
1783 * A pipe without a PLL won't actually be able to drive bits from
1784 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1785 * need the check.
1786 */
1787 if (HAS_GMCH(dev_priv)) {
1788 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
1789 assert_dsi_pll_enabled(dev_priv);
1790 else
1791 assert_pll_enabled(dev_priv, pipe);
1792 } else {
1793 if (new_crtc_state->has_pch_encoder) {
1794 /* if driving the PCH, we need FDI enabled */
1795 assert_fdi_rx_pll_enabled(dev_priv,
1796 intel_crtc_pch_transcoder(crtc));
1797 assert_fdi_tx_pll_enabled(dev_priv,
1798 (enum pipe) cpu_transcoder);
1799 }
1800 /* FIXME: assert CPU port conditions for SNB+ */
1801 }
1802
1803 trace_intel_pipe_enable(dev_priv, pipe);
1804
1805 reg = PIPECONF(cpu_transcoder);
1806 val = I915_READ(reg);
1807 if (val & PIPECONF_ENABLE) {
1808 /* we keep both pipes enabled on 830 */
1809 WARN_ON(!IS_I830(dev_priv));
1810 return;
1811 }
1812
1813 I915_WRITE(reg, val | PIPECONF_ENABLE);
1814 POSTING_READ(reg);
1815
1816 /*
1817 * Until the pipe starts PIPEDSL reads will return a stale value,
1818 * which causes an apparent vblank timestamp jump when PIPEDSL
1819 * resets to its proper value. That also messes up the frame count
1820 * when it's derived from the timestamps. So let's wait for the
1821 * pipe to start properly before we call drm_crtc_vblank_on()
1822 */
1823 if (intel_crtc_max_vblank_count(new_crtc_state) == 0)
1824 intel_wait_for_pipe_scanline_moving(crtc);
1825 }
1826
1827 static void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state)
1828 {
1829 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
1830 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1831 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
1832 enum pipe pipe = crtc->pipe;
1833 i915_reg_t reg;
1834 u32 val;
1835
1836 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
1837
1838 /*
1839 * Make sure planes won't keep trying to pump pixels to us,
1840 * or we might hang the display.
1841 */
1842 assert_planes_disabled(crtc);
1843
1844 trace_intel_pipe_disable(dev_priv, pipe);
1845
1846 reg = PIPECONF(cpu_transcoder);
1847 val = I915_READ(reg);
1848 if ((val & PIPECONF_ENABLE) == 0)
1849 return;
1850
1851 /*
1852 * Double wide has implications for planes
1853 * so best keep it disabled when not needed.
1854 */
1855 if (old_crtc_state->double_wide)
1856 val &= ~PIPECONF_DOUBLE_WIDE;
1857
1858 /* Don't disable pipe or pipe PLLs if needed */
1859 if (!IS_I830(dev_priv))
1860 val &= ~PIPECONF_ENABLE;
1861
1862 I915_WRITE(reg, val);
1863 if ((val & PIPECONF_ENABLE) == 0)
1864 intel_wait_for_pipe_off(old_crtc_state);
1865 }
1866
1867 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
1868 {
1869 return IS_GEN(dev_priv, 2) ? 2048 : 4096;
1870 }
1871
1872 static unsigned int
1873 intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
1874 {
1875 struct drm_i915_private *dev_priv = to_i915(fb->dev);
1876 unsigned int cpp = fb->format->cpp[color_plane];
1877
1878 switch (fb->modifier) {
1879 case DRM_FORMAT_MOD_LINEAR:
1880 return cpp;
1881 case I915_FORMAT_MOD_X_TILED:
1882 if (IS_GEN(dev_priv, 2))
1883 return 128;
1884 else
1885 return 512;
1886 case I915_FORMAT_MOD_Y_TILED_CCS:
1887 if (color_plane == 1)
1888 return 128;
1889 /* fall through */
1890 case I915_FORMAT_MOD_Y_TILED:
1891 if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv))
1892 return 128;
1893 else
1894 return 512;
1895 case I915_FORMAT_MOD_Yf_TILED_CCS:
1896 if (color_plane == 1)
1897 return 128;
1898 /* fall through */
1899 case I915_FORMAT_MOD_Yf_TILED:
1900 switch (cpp) {
1901 case 1:
1902 return 64;
1903 case 2:
1904 case 4:
1905 return 128;
1906 case 8:
1907 case 16:
1908 return 256;
1909 default:
1910 MISSING_CASE(cpp);
1911 return cpp;
1912 }
1913 break;
1914 default:
1915 MISSING_CASE(fb->modifier);
1916 return cpp;
1917 }
1918 }
1919
1920 static unsigned int
1921 intel_tile_height(const struct drm_framebuffer *fb, int color_plane)
1922 {
1923 if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
1924 return 1;
1925 else
1926 return intel_tile_size(to_i915(fb->dev)) /
1927 intel_tile_width_bytes(fb, color_plane);
1928 }
1929
1930 /* Return the tile dimensions in pixel units */
1931 static void intel_tile_dims(const struct drm_framebuffer *fb, int color_plane,
1932 unsigned int *tile_width,
1933 unsigned int *tile_height)
1934 {
1935 unsigned int tile_width_bytes = intel_tile_width_bytes(fb, color_plane);
1936 unsigned int cpp = fb->format->cpp[color_plane];
1937
1938 *tile_width = tile_width_bytes / cpp;
1939 *tile_height = intel_tile_size(to_i915(fb->dev)) / tile_width_bytes;
1940 }
1941
1942 unsigned int
1943 intel_fb_align_height(const struct drm_framebuffer *fb,
1944 int color_plane, unsigned int height)
1945 {
1946 unsigned int tile_height = intel_tile_height(fb, color_plane);
1947
1948 return ALIGN(height, tile_height);
1949 }
1950
1951 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
1952 {
1953 unsigned int size = 0;
1954 int i;
1955
1956 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
1957 size += rot_info->plane[i].width * rot_info->plane[i].height;
1958
1959 return size;
1960 }
1961
1962 static void
1963 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
1964 const struct drm_framebuffer *fb,
1965 unsigned int rotation)
1966 {
1967 view->type = I915_GGTT_VIEW_NORMAL;
1968 if (drm_rotation_90_or_270(rotation)) {
1969 view->type = I915_GGTT_VIEW_ROTATED;
1970 view->rotated = to_intel_framebuffer(fb)->rot_info;
1971 }
1972 }
1973
1974 static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_priv)
1975 {
1976 if (IS_I830(dev_priv))
1977 return 16 * 1024;
1978 else if (IS_I85X(dev_priv))
1979 return 256;
1980 else if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
1981 return 32;
1982 else
1983 return 4 * 1024;
1984 }
1985
1986 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
1987 {
1988 if (INTEL_GEN(dev_priv) >= 9)
1989 return 256 * 1024;
1990 else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
1991 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1992 return 128 * 1024;
1993 else if (INTEL_GEN(dev_priv) >= 4)
1994 return 4 * 1024;
1995 else
1996 return 0;
1997 }
1998
1999 static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
2000 int color_plane)
2001 {
2002 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2003
2004 /* AUX_DIST needs only 4K alignment */
2005 if (color_plane == 1)
2006 return 4096;
2007
2008 switch (fb->modifier) {
2009 case DRM_FORMAT_MOD_LINEAR:
2010 return intel_linear_alignment(dev_priv);
2011 case I915_FORMAT_MOD_X_TILED:
2012 if (INTEL_GEN(dev_priv) >= 9)
2013 return 256 * 1024;
2014 return 0;
2015 case I915_FORMAT_MOD_Y_TILED_CCS:
2016 case I915_FORMAT_MOD_Yf_TILED_CCS:
2017 case I915_FORMAT_MOD_Y_TILED:
2018 case I915_FORMAT_MOD_Yf_TILED:
2019 return 1 * 1024 * 1024;
2020 default:
2021 MISSING_CASE(fb->modifier);
2022 return 0;
2023 }
2024 }
2025
2026 static bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
2027 {
2028 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
2029 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
2030
2031 return INTEL_GEN(dev_priv) < 4 || plane->has_fbc;
2032 }
2033
2034 struct i915_vma *
2035 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2036 const struct i915_ggtt_view *view,
2037 bool uses_fence,
2038 unsigned long *out_flags)
2039 {
2040 struct drm_device *dev = fb->dev;
2041 struct drm_i915_private *dev_priv = to_i915(dev);
2042 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2043 intel_wakeref_t wakeref;
2044 struct i915_vma *vma;
2045 unsigned int pinctl;
2046 u32 alignment;
2047
2048 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2049
2050 alignment = intel_surf_alignment(fb, 0);
2051
2052 /* Note that the w/a also requires 64 PTE of padding following the
2053 * bo. We currently fill all unused PTE with the shadow page and so
2054 * we should always have valid PTE following the scanout preventing
2055 * the VT-d warning.
2056 */
2057 if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2058 alignment = 256 * 1024;
2059
2060 /*
2061 * Global gtt pte registers are special registers which actually forward
2062 * writes to a chunk of system memory. Which means that there is no risk
2063 * that the register values disappear as soon as we call
2064 * intel_runtime_pm_put(), so it is correct to wrap only the
2065 * pin/unpin/fence and not more.
2066 */
2067 wakeref = intel_runtime_pm_get(dev_priv);
2068
2069 atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
2070
2071 pinctl = 0;
2072
2073 /* Valleyview is definitely limited to scanning out the first
2074 * 512MiB. Lets presume this behaviour was inherited from the
2075 * g4x display engine and that all earlier gen are similarly
2076 * limited. Testing suggests that it is a little more
2077 * complicated than this. For example, Cherryview appears quite
2078 * happy to scanout from anywhere within its global aperture.
2079 */
2080 if (HAS_GMCH(dev_priv))
2081 pinctl |= PIN_MAPPABLE;
2082
2083 vma = i915_gem_object_pin_to_display_plane(obj,
2084 alignment, view, pinctl);
2085 if (IS_ERR(vma))
2086 goto err;
2087
2088 if (uses_fence && i915_vma_is_map_and_fenceable(vma)) {
2089 int ret;
2090
2091 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2092 * fence, whereas 965+ only requires a fence if using
2093 * framebuffer compression. For simplicity, we always, when
2094 * possible, install a fence as the cost is not that onerous.
2095 *
2096 * If we fail to fence the tiled scanout, then either the
2097 * modeset will reject the change (which is highly unlikely as
2098 * the affected systems, all but one, do not have unmappable
2099 * space) or we will not be able to enable full powersaving
2100 * techniques (also likely not to apply due to various limits
2101 * FBC and the like impose on the size of the buffer, which
2102 * presumably we violated anyway with this unmappable buffer).
2103 * Anyway, it is presumably better to stumble onwards with
2104 * something and try to run the system in a "less than optimal"
2105 * mode that matches the user configuration.
2106 */
2107 ret = i915_vma_pin_fence(vma);
2108 if (ret != 0 && INTEL_GEN(dev_priv) < 4) {
2109 i915_gem_object_unpin_from_display_plane(vma);
2110 vma = ERR_PTR(ret);
2111 goto err;
2112 }
2113
2114 if (ret == 0 && vma->fence)
2115 *out_flags |= PLANE_HAS_FENCE;
2116 }
2117
2118 i915_vma_get(vma);
2119 err:
2120 atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
2121
2122 intel_runtime_pm_put(dev_priv, wakeref);
2123 return vma;
2124 }
2125
2126 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags)
2127 {
2128 lockdep_assert_held(&vma->vm->i915->drm.struct_mutex);
2129
2130 if (flags & PLANE_HAS_FENCE)
2131 i915_vma_unpin_fence(vma);
2132 i915_gem_object_unpin_from_display_plane(vma);
2133 i915_vma_put(vma);
2134 }
2135
2136 static int intel_fb_pitch(const struct drm_framebuffer *fb, int color_plane,
2137 unsigned int rotation)
2138 {
2139 if (drm_rotation_90_or_270(rotation))
2140 return to_intel_framebuffer(fb)->rotated[color_plane].pitch;
2141 else
2142 return fb->pitches[color_plane];
2143 }
2144
2145 /*
2146 * Convert the x/y offsets into a linear offset.
2147 * Only valid with 0/180 degree rotation, which is fine since linear
2148 * offset is only used with linear buffers on pre-hsw and tiled buffers
2149 * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2150 */
2151 u32 intel_fb_xy_to_linear(int x, int y,
2152 const struct intel_plane_state *state,
2153 int color_plane)
2154 {
2155 const struct drm_framebuffer *fb = state->base.fb;
2156 unsigned int cpp = fb->format->cpp[color_plane];
2157 unsigned int pitch = state->color_plane[color_plane].stride;
2158
2159 return y * pitch + x * cpp;
2160 }
2161
2162 /*
2163 * Add the x/y offsets derived from fb->offsets[] to the user
2164 * specified plane src x/y offsets. The resulting x/y offsets
2165 * specify the start of scanout from the beginning of the gtt mapping.
2166 */
2167 void intel_add_fb_offsets(int *x, int *y,
2168 const struct intel_plane_state *state,
2169 int color_plane)
2170
2171 {
2172 const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
2173 unsigned int rotation = state->base.rotation;
2174
2175 if (drm_rotation_90_or_270(rotation)) {
2176 *x += intel_fb->rotated[color_plane].x;
2177 *y += intel_fb->rotated[color_plane].y;
2178 } else {
2179 *x += intel_fb->normal[color_plane].x;
2180 *y += intel_fb->normal[color_plane].y;
2181 }
2182 }
2183
2184 static u32 intel_adjust_tile_offset(int *x, int *y,
2185 unsigned int tile_width,
2186 unsigned int tile_height,
2187 unsigned int tile_size,
2188 unsigned int pitch_tiles,
2189 u32 old_offset,
2190 u32 new_offset)
2191 {
2192 unsigned int pitch_pixels = pitch_tiles * tile_width;
2193 unsigned int tiles;
2194
2195 WARN_ON(old_offset & (tile_size - 1));
2196 WARN_ON(new_offset & (tile_size - 1));
2197 WARN_ON(new_offset > old_offset);
2198
2199 tiles = (old_offset - new_offset) / tile_size;
2200
2201 *y += tiles / pitch_tiles * tile_height;
2202 *x += tiles % pitch_tiles * tile_width;
2203
2204 /* minimize x in case it got needlessly big */
2205 *y += *x / pitch_pixels * tile_height;
2206 *x %= pitch_pixels;
2207
2208 return new_offset;
2209 }
2210
2211 static bool is_surface_linear(u64 modifier, int color_plane)
2212 {
2213 return modifier == DRM_FORMAT_MOD_LINEAR;
2214 }
2215
2216 static u32 intel_adjust_aligned_offset(int *x, int *y,
2217 const struct drm_framebuffer *fb,
2218 int color_plane,
2219 unsigned int rotation,
2220 unsigned int pitch,
2221 u32 old_offset, u32 new_offset)
2222 {
2223 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2224 unsigned int cpp = fb->format->cpp[color_plane];
2225
2226 WARN_ON(new_offset > old_offset);
2227
2228 if (!is_surface_linear(fb->modifier, color_plane)) {
2229 unsigned int tile_size, tile_width, tile_height;
2230 unsigned int pitch_tiles;
2231
2232 tile_size = intel_tile_size(dev_priv);
2233 intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
2234
2235 if (drm_rotation_90_or_270(rotation)) {
2236 pitch_tiles = pitch / tile_height;
2237 swap(tile_width, tile_height);
2238 } else {
2239 pitch_tiles = pitch / (tile_width * cpp);
2240 }
2241
2242 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2243 tile_size, pitch_tiles,
2244 old_offset, new_offset);
2245 } else {
2246 old_offset += *y * pitch + *x * cpp;
2247
2248 *y = (old_offset - new_offset) / pitch;
2249 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2250 }
2251
2252 return new_offset;
2253 }
2254
2255 /*
2256 * Adjust the tile offset by moving the difference into
2257 * the x/y offsets.
2258 */
2259 static u32 intel_plane_adjust_aligned_offset(int *x, int *y,
2260 const struct intel_plane_state *state,
2261 int color_plane,
2262 u32 old_offset, u32 new_offset)
2263 {
2264 return intel_adjust_aligned_offset(x, y, state->base.fb, color_plane,
2265 state->base.rotation,
2266 state->color_plane[color_plane].stride,
2267 old_offset, new_offset);
2268 }
2269
2270 /*
2271 * Computes the aligned offset to the base tile and adjusts
2272 * x, y. bytes per pixel is assumed to be a power-of-two.
2273 *
2274 * In the 90/270 rotated case, x and y are assumed
2275 * to be already rotated to match the rotated GTT view, and
2276 * pitch is the tile_height aligned framebuffer height.
2277 *
2278 * This function is used when computing the derived information
2279 * under intel_framebuffer, so using any of that information
2280 * here is not allowed. Anything under drm_framebuffer can be
2281 * used. This is why the user has to pass in the pitch since it
2282 * is specified in the rotated orientation.
2283 */
2284 static u32 intel_compute_aligned_offset(struct drm_i915_private *dev_priv,
2285 int *x, int *y,
2286 const struct drm_framebuffer *fb,
2287 int color_plane,
2288 unsigned int pitch,
2289 unsigned int rotation,
2290 u32 alignment)
2291 {
2292 unsigned int cpp = fb->format->cpp[color_plane];
2293 u32 offset, offset_aligned;
2294
2295 if (alignment)
2296 alignment--;
2297
2298 if (!is_surface_linear(fb->modifier, color_plane)) {
2299 unsigned int tile_size, tile_width, tile_height;
2300 unsigned int tile_rows, tiles, pitch_tiles;
2301
2302 tile_size = intel_tile_size(dev_priv);
2303 intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
2304
2305 if (drm_rotation_90_or_270(rotation)) {
2306 pitch_tiles = pitch / tile_height;
2307 swap(tile_width, tile_height);
2308 } else {
2309 pitch_tiles = pitch / (tile_width * cpp);
2310 }
2311
2312 tile_rows = *y / tile_height;
2313 *y %= tile_height;
2314
2315 tiles = *x / tile_width;
2316 *x %= tile_width;
2317
2318 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2319 offset_aligned = offset & ~alignment;
2320
2321 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2322 tile_size, pitch_tiles,
2323 offset, offset_aligned);
2324 } else {
2325 offset = *y * pitch + *x * cpp;
2326 offset_aligned = offset & ~alignment;
2327
2328 *y = (offset & alignment) / pitch;
2329 *x = ((offset & alignment) - *y * pitch) / cpp;
2330 }
2331
2332 return offset_aligned;
2333 }
2334
2335 static u32 intel_plane_compute_aligned_offset(int *x, int *y,
2336 const struct intel_plane_state *state,
2337 int color_plane)
2338 {
2339 struct intel_plane *intel_plane = to_intel_plane(state->base.plane);
2340 struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
2341 const struct drm_framebuffer *fb = state->base.fb;
2342 unsigned int rotation = state->base.rotation;
2343 int pitch = state->color_plane[color_plane].stride;
2344 u32 alignment;
2345
2346 if (intel_plane->id == PLANE_CURSOR)
2347 alignment = intel_cursor_alignment(dev_priv);
2348 else
2349 alignment = intel_surf_alignment(fb, color_plane);
2350
2351 return intel_compute_aligned_offset(dev_priv, x, y, fb, color_plane,
2352 pitch, rotation, alignment);
2353 }
2354
2355 /* Convert the fb->offset[] into x/y offsets */
2356 static int intel_fb_offset_to_xy(int *x, int *y,
2357 const struct drm_framebuffer *fb,
2358 int color_plane)
2359 {
2360 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2361 unsigned int height;
2362
2363 if (fb->modifier != DRM_FORMAT_MOD_LINEAR &&
2364 fb->offsets[color_plane] % intel_tile_size(dev_priv)) {
2365 DRM_DEBUG_KMS("Misaligned offset 0x%08x for color plane %d\n",
2366 fb->offsets[color_plane], color_plane);
2367 return -EINVAL;
2368 }
2369
2370 height = drm_framebuffer_plane_height(fb->height, fb, color_plane);
2371 height = ALIGN(height, intel_tile_height(fb, color_plane));
2372
2373 /* Catch potential overflows early */
2374 if (add_overflows_t(u32, mul_u32_u32(height, fb->pitches[color_plane]),
2375 fb->offsets[color_plane])) {
2376 DRM_DEBUG_KMS("Bad offset 0x%08x or pitch %d for color plane %d\n",
2377 fb->offsets[color_plane], fb->pitches[color_plane],
2378 color_plane);
2379 return -ERANGE;
2380 }
2381
2382 *x = 0;
2383 *y = 0;
2384
2385 intel_adjust_aligned_offset(x, y,
2386 fb, color_plane, DRM_MODE_ROTATE_0,
2387 fb->pitches[color_plane],
2388 fb->offsets[color_plane], 0);
2389
2390 return 0;
2391 }
2392
2393 static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
2394 {
2395 switch (fb_modifier) {
2396 case I915_FORMAT_MOD_X_TILED:
2397 return I915_TILING_X;
2398 case I915_FORMAT_MOD_Y_TILED:
2399 case I915_FORMAT_MOD_Y_TILED_CCS:
2400 return I915_TILING_Y;
2401 default:
2402 return I915_TILING_NONE;
2403 }
2404 }
2405
2406 /*
2407 * From the Sky Lake PRM:
2408 * "The Color Control Surface (CCS) contains the compression status of
2409 * the cache-line pairs. The compression state of the cache-line pair
2410 * is specified by 2 bits in the CCS. Each CCS cache-line represents
2411 * an area on the main surface of 16 x16 sets of 128 byte Y-tiled
2412 * cache-line-pairs. CCS is always Y tiled."
2413 *
2414 * Since cache line pairs refers to horizontally adjacent cache lines,
2415 * each cache line in the CCS corresponds to an area of 32x16 cache
2416 * lines on the main surface. Since each pixel is 4 bytes, this gives
2417 * us a ratio of one byte in the CCS for each 8x16 pixels in the
2418 * main surface.
2419 */
2420 static const struct drm_format_info ccs_formats[] = {
2421 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2422 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2423 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2424 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2425 };
2426
2427 static const struct drm_format_info *
2428 lookup_format_info(const struct drm_format_info formats[],
2429 int num_formats, u32 format)
2430 {
2431 int i;
2432
2433 for (i = 0; i < num_formats; i++) {
2434 if (formats[i].format == format)
2435 return &formats[i];
2436 }
2437
2438 return NULL;
2439 }
2440
2441 static const struct drm_format_info *
2442 intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
2443 {
2444 switch (cmd->modifier[0]) {
2445 case I915_FORMAT_MOD_Y_TILED_CCS:
2446 case I915_FORMAT_MOD_Yf_TILED_CCS:
2447 return lookup_format_info(ccs_formats,
2448 ARRAY_SIZE(ccs_formats),
2449 cmd->pixel_format);
2450 default:
2451 return NULL;
2452 }
2453 }
2454
2455 bool is_ccs_modifier(u64 modifier)
2456 {
2457 return modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
2458 modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
2459 }
2460
2461 static int
2462 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2463 struct drm_framebuffer *fb)
2464 {
2465 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2466 struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2467 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2468 u32 gtt_offset_rotated = 0;
2469 unsigned int max_size = 0;
2470 int i, num_planes = fb->format->num_planes;
2471 unsigned int tile_size = intel_tile_size(dev_priv);
2472
2473 for (i = 0; i < num_planes; i++) {
2474 unsigned int width, height;
2475 unsigned int cpp, size;
2476 u32 offset;
2477 int x, y;
2478 int ret;
2479
2480 cpp = fb->format->cpp[i];
2481 width = drm_framebuffer_plane_width(fb->width, fb, i);
2482 height = drm_framebuffer_plane_height(fb->height, fb, i);
2483
2484 ret = intel_fb_offset_to_xy(&x, &y, fb, i);
2485 if (ret) {
2486 DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2487 i, fb->offsets[i]);
2488 return ret;
2489 }
2490
2491 if (is_ccs_modifier(fb->modifier) && i == 1) {
2492 int hsub = fb->format->hsub;
2493 int vsub = fb->format->vsub;
2494 int tile_width, tile_height;
2495 int main_x, main_y;
2496 int ccs_x, ccs_y;
2497
2498 intel_tile_dims(fb, i, &tile_width, &tile_height);
2499 tile_width *= hsub;
2500 tile_height *= vsub;
2501
2502 ccs_x = (x * hsub) % tile_width;
2503 ccs_y = (y * vsub) % tile_height;
2504 main_x = intel_fb->normal[0].x % tile_width;
2505 main_y = intel_fb->normal[0].y % tile_height;
2506
2507 /*
2508 * CCS doesn't have its own x/y offset register, so the intra CCS tile
2509 * x/y offsets must match between CCS and the main surface.
2510 */
2511 if (main_x != ccs_x || main_y != ccs_y) {
2512 DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
2513 main_x, main_y,
2514 ccs_x, ccs_y,
2515 intel_fb->normal[0].x,
2516 intel_fb->normal[0].y,
2517 x, y);
2518 return -EINVAL;
2519 }
2520 }
2521
2522 /*
2523 * The fence (if used) is aligned to the start of the object
2524 * so having the framebuffer wrap around across the edge of the
2525 * fenced region doesn't really work. We have no API to configure
2526 * the fence start offset within the object (nor could we probably
2527 * on gen2/3). So it's just easier if we just require that the
2528 * fb layout agrees with the fence layout. We already check that the
2529 * fb stride matches the fence stride elsewhere.
2530 */
2531 if (i == 0 && i915_gem_object_is_tiled(obj) &&
2532 (x + width) * cpp > fb->pitches[i]) {
2533 DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2534 i, fb->offsets[i]);
2535 return -EINVAL;
2536 }
2537
2538 /*
2539 * First pixel of the framebuffer from
2540 * the start of the normal gtt mapping.
2541 */
2542 intel_fb->normal[i].x = x;
2543 intel_fb->normal[i].y = y;
2544
2545 offset = intel_compute_aligned_offset(dev_priv, &x, &y, fb, i,
2546 fb->pitches[i],
2547 DRM_MODE_ROTATE_0,
2548 tile_size);
2549 offset /= tile_size;
2550
2551 if (!is_surface_linear(fb->modifier, i)) {
2552 unsigned int tile_width, tile_height;
2553 unsigned int pitch_tiles;
2554 struct drm_rect r;
2555
2556 intel_tile_dims(fb, i, &tile_width, &tile_height);
2557
2558 rot_info->plane[i].offset = offset;
2559 rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2560 rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2561 rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2562
2563 intel_fb->rotated[i].pitch =
2564 rot_info->plane[i].height * tile_height;
2565
2566 /* how many tiles does this plane need */
2567 size = rot_info->plane[i].stride * rot_info->plane[i].height;
2568 /*
2569 * If the plane isn't horizontally tile aligned,
2570 * we need one more tile.
2571 */
2572 if (x != 0)
2573 size++;
2574
2575 /* rotate the x/y offsets to match the GTT view */
2576 r.x1 = x;
2577 r.y1 = y;
2578 r.x2 = x + width;
2579 r.y2 = y + height;
2580 drm_rect_rotate(&r,
2581 rot_info->plane[i].width * tile_width,
2582 rot_info->plane[i].height * tile_height,
2583 DRM_MODE_ROTATE_270);
2584 x = r.x1;
2585 y = r.y1;
2586
2587 /* rotate the tile dimensions to match the GTT view */
2588 pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2589 swap(tile_width, tile_height);
2590
2591 /*
2592 * We only keep the x/y offsets, so push all of the
2593 * gtt offset into the x/y offsets.
2594 */
2595 intel_adjust_tile_offset(&x, &y,
2596 tile_width, tile_height,
2597 tile_size, pitch_tiles,
2598 gtt_offset_rotated * tile_size, 0);
2599
2600 gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2601
2602 /*
2603 * First pixel of the framebuffer from
2604 * the start of the rotated gtt mapping.
2605 */
2606 intel_fb->rotated[i].x = x;
2607 intel_fb->rotated[i].y = y;
2608 } else {
2609 size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2610 x * cpp, tile_size);
2611 }
2612
2613 /* how many tiles in total needed in the bo */
2614 max_size = max(max_size, offset + size);
2615 }
2616
2617 if (mul_u32_u32(max_size, tile_size) > obj->base.size) {
2618 DRM_DEBUG_KMS("fb too big for bo (need %llu bytes, have %zu bytes)\n",
2619 mul_u32_u32(max_size, tile_size), obj->base.size);
2620 return -EINVAL;
2621 }
2622
2623 return 0;
2624 }
2625
2626 static int i9xx_format_to_fourcc(int format)
2627 {
2628 switch (format) {
2629 case DISPPLANE_8BPP:
2630 return DRM_FORMAT_C8;
2631 case DISPPLANE_BGRX555:
2632 return DRM_FORMAT_XRGB1555;
2633 case DISPPLANE_BGRX565:
2634 return DRM_FORMAT_RGB565;
2635 default:
2636 case DISPPLANE_BGRX888:
2637 return DRM_FORMAT_XRGB8888;
2638 case DISPPLANE_RGBX888:
2639 return DRM_FORMAT_XBGR8888;
2640 case DISPPLANE_BGRX101010:
2641 return DRM_FORMAT_XRGB2101010;
2642 case DISPPLANE_RGBX101010:
2643 return DRM_FORMAT_XBGR2101010;
2644 }
2645 }
2646
2647 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2648 {
2649 switch (format) {
2650 case PLANE_CTL_FORMAT_RGB_565:
2651 return DRM_FORMAT_RGB565;
2652 case PLANE_CTL_FORMAT_NV12:
2653 return DRM_FORMAT_NV12;
2654 case PLANE_CTL_FORMAT_P010:
2655 return DRM_FORMAT_P010;
2656 case PLANE_CTL_FORMAT_P012:
2657 return DRM_FORMAT_P012;
2658 case PLANE_CTL_FORMAT_P016:
2659 return DRM_FORMAT_P016;
2660 case PLANE_CTL_FORMAT_Y210:
2661 return DRM_FORMAT_Y210;
2662 case PLANE_CTL_FORMAT_Y212:
2663 return DRM_FORMAT_Y212;
2664 case PLANE_CTL_FORMAT_Y216:
2665 return DRM_FORMAT_Y216;
2666 case PLANE_CTL_FORMAT_Y410:
2667 return DRM_FORMAT_XVYU2101010;
2668 case PLANE_CTL_FORMAT_Y412:
2669 return DRM_FORMAT_XVYU12_16161616;
2670 case PLANE_CTL_FORMAT_Y416:
2671 return DRM_FORMAT_XVYU16161616;
2672 default:
2673 case PLANE_CTL_FORMAT_XRGB_8888:
2674 if (rgb_order) {
2675 if (alpha)
2676 return DRM_FORMAT_ABGR8888;
2677 else
2678 return DRM_FORMAT_XBGR8888;
2679 } else {
2680 if (alpha)
2681 return DRM_FORMAT_ARGB8888;
2682 else
2683 return DRM_FORMAT_XRGB8888;
2684 }
2685 case PLANE_CTL_FORMAT_XRGB_2101010:
2686 if (rgb_order)
2687 return DRM_FORMAT_XBGR2101010;
2688 else
2689 return DRM_FORMAT_XRGB2101010;
2690 case PLANE_CTL_FORMAT_XRGB_16161616F:
2691 if (rgb_order) {
2692 if (alpha)
2693 return DRM_FORMAT_ABGR16161616F;
2694 else
2695 return DRM_FORMAT_XBGR16161616F;
2696 } else {
2697 if (alpha)
2698 return DRM_FORMAT_ARGB16161616F;
2699 else
2700 return DRM_FORMAT_XRGB16161616F;
2701 }
2702 }
2703 }
2704
2705 static bool
2706 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2707 struct intel_initial_plane_config *plane_config)
2708 {
2709 struct drm_device *dev = crtc->base.dev;
2710 struct drm_i915_private *dev_priv = to_i915(dev);
2711 struct drm_i915_gem_object *obj = NULL;
2712 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2713 struct drm_framebuffer *fb = &plane_config->fb->base;
2714 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2715 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2716 PAGE_SIZE);
2717
2718 size_aligned -= base_aligned;
2719
2720 if (plane_config->size == 0)
2721 return false;
2722
2723 /* If the FB is too big, just don't use it since fbdev is not very
2724 * important and we should probably use that space with FBC or other
2725 * features. */
2726 if (size_aligned * 2 > dev_priv->stolen_usable_size)
2727 return false;
2728
2729 switch (fb->modifier) {
2730 case DRM_FORMAT_MOD_LINEAR:
2731 case I915_FORMAT_MOD_X_TILED:
2732 case I915_FORMAT_MOD_Y_TILED:
2733 break;
2734 default:
2735 DRM_DEBUG_DRIVER("Unsupported modifier for initial FB: 0x%llx\n",
2736 fb->modifier);
2737 return false;
2738 }
2739
2740 mutex_lock(&dev->struct_mutex);
2741 obj = i915_gem_object_create_stolen_for_preallocated(dev_priv,
2742 base_aligned,
2743 base_aligned,
2744 size_aligned);
2745 mutex_unlock(&dev->struct_mutex);
2746 if (!obj)
2747 return false;
2748
2749 switch (plane_config->tiling) {
2750 case I915_TILING_NONE:
2751 break;
2752 case I915_TILING_X:
2753 case I915_TILING_Y:
2754 obj->tiling_and_stride = fb->pitches[0] | plane_config->tiling;
2755 break;
2756 default:
2757 MISSING_CASE(plane_config->tiling);
2758 return false;
2759 }
2760
2761 mode_cmd.pixel_format = fb->format->format;
2762 mode_cmd.width = fb->width;
2763 mode_cmd.height = fb->height;
2764 mode_cmd.pitches[0] = fb->pitches[0];
2765 mode_cmd.modifier[0] = fb->modifier;
2766 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2767
2768 if (intel_framebuffer_init(to_intel_framebuffer(fb), obj, &mode_cmd)) {
2769 DRM_DEBUG_KMS("intel fb init failed\n");
2770 goto out_unref_obj;
2771 }
2772
2773
2774 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2775 return true;
2776
2777 out_unref_obj:
2778 i915_gem_object_put(obj);
2779 return false;
2780 }
2781
2782 static void
2783 intel_set_plane_visible(struct intel_crtc_state *crtc_state,
2784 struct intel_plane_state *plane_state,
2785 bool visible)
2786 {
2787 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
2788
2789 plane_state->base.visible = visible;
2790
2791 if (visible)
2792 crtc_state->base.plane_mask |= drm_plane_mask(&plane->base);
2793 else
2794 crtc_state->base.plane_mask &= ~drm_plane_mask(&plane->base);
2795 }
2796
2797 static void fixup_active_planes(struct intel_crtc_state *crtc_state)
2798 {
2799 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
2800 struct drm_plane *plane;
2801
2802 /*
2803 * Active_planes aliases if multiple "primary" or cursor planes
2804 * have been used on the same (or wrong) pipe. plane_mask uses
2805 * unique ids, hence we can use that to reconstruct active_planes.
2806 */
2807 crtc_state->active_planes = 0;
2808
2809 drm_for_each_plane_mask(plane, &dev_priv->drm,
2810 crtc_state->base.plane_mask)
2811 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id);
2812 }
2813
2814 static void intel_plane_disable_noatomic(struct intel_crtc *crtc,
2815 struct intel_plane *plane)
2816 {
2817 struct intel_crtc_state *crtc_state =
2818 to_intel_crtc_state(crtc->base.state);
2819 struct intel_plane_state *plane_state =
2820 to_intel_plane_state(plane->base.state);
2821
2822 DRM_DEBUG_KMS("Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n",
2823 plane->base.base.id, plane->base.name,
2824 crtc->base.base.id, crtc->base.name);
2825
2826 intel_set_plane_visible(crtc_state, plane_state, false);
2827 fixup_active_planes(crtc_state);
2828
2829 if (plane->id == PLANE_PRIMARY)
2830 intel_pre_disable_primary_noatomic(&crtc->base);
2831
2832 intel_disable_plane(plane, crtc_state);
2833 }
2834
2835 static void
2836 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2837 struct intel_initial_plane_config *plane_config)
2838 {
2839 struct drm_device *dev = intel_crtc->base.dev;
2840 struct drm_i915_private *dev_priv = to_i915(dev);
2841 struct drm_crtc *c;
2842 struct drm_i915_gem_object *obj;
2843 struct drm_plane *primary = intel_crtc->base.primary;
2844 struct drm_plane_state *plane_state = primary->state;
2845 struct intel_plane *intel_plane = to_intel_plane(primary);
2846 struct intel_plane_state *intel_state =
2847 to_intel_plane_state(plane_state);
2848 struct drm_framebuffer *fb;
2849
2850 if (!plane_config->fb)
2851 return;
2852
2853 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2854 fb = &plane_config->fb->base;
2855 goto valid_fb;
2856 }
2857
2858 kfree(plane_config->fb);
2859
2860 /*
2861 * Failed to alloc the obj, check to see if we should share
2862 * an fb with another CRTC instead
2863 */
2864 for_each_crtc(dev, c) {
2865 struct intel_plane_state *state;
2866
2867 if (c == &intel_crtc->base)
2868 continue;
2869
2870 if (!to_intel_crtc(c)->active)
2871 continue;
2872
2873 state = to_intel_plane_state(c->primary->state);
2874 if (!state->vma)
2875 continue;
2876
2877 if (intel_plane_ggtt_offset(state) == plane_config->base) {
2878 fb = state->base.fb;
2879 drm_framebuffer_get(fb);
2880 goto valid_fb;
2881 }
2882 }
2883
2884 /*
2885 * We've failed to reconstruct the BIOS FB. Current display state
2886 * indicates that the primary plane is visible, but has a NULL FB,
2887 * which will lead to problems later if we don't fix it up. The
2888 * simplest solution is to just disable the primary plane now and
2889 * pretend the BIOS never had it enabled.
2890 */
2891 intel_plane_disable_noatomic(intel_crtc, intel_plane);
2892
2893 return;
2894
2895 valid_fb:
2896 intel_state->base.rotation = plane_config->rotation;
2897 intel_fill_fb_ggtt_view(&intel_state->view, fb,
2898 intel_state->base.rotation);
2899 intel_state->color_plane[0].stride =
2900 intel_fb_pitch(fb, 0, intel_state->base.rotation);
2901
2902 mutex_lock(&dev->struct_mutex);
2903 intel_state->vma =
2904 intel_pin_and_fence_fb_obj(fb,
2905 &intel_state->view,
2906 intel_plane_uses_fence(intel_state),
2907 &intel_state->flags);
2908 mutex_unlock(&dev->struct_mutex);
2909 if (IS_ERR(intel_state->vma)) {
2910 DRM_ERROR("failed to pin boot fb on pipe %d: %li\n",
2911 intel_crtc->pipe, PTR_ERR(intel_state->vma));
2912
2913 intel_state->vma = NULL;
2914 drm_framebuffer_put(fb);
2915 return;
2916 }
2917
2918 obj = intel_fb_obj(fb);
2919 intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
2920
2921 plane_state->src_x = 0;
2922 plane_state->src_y = 0;
2923 plane_state->src_w = fb->width << 16;
2924 plane_state->src_h = fb->height << 16;
2925
2926 plane_state->crtc_x = 0;
2927 plane_state->crtc_y = 0;
2928 plane_state->crtc_w = fb->width;
2929 plane_state->crtc_h = fb->height;
2930
2931 intel_state->base.src = drm_plane_state_src(plane_state);
2932 intel_state->base.dst = drm_plane_state_dest(plane_state);
2933
2934 if (i915_gem_object_is_tiled(obj))
2935 dev_priv->preserve_bios_swizzle = true;
2936
2937 plane_state->fb = fb;
2938 plane_state->crtc = &intel_crtc->base;
2939
2940 atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2941 &obj->frontbuffer_bits);
2942 }
2943
2944 static int skl_max_plane_width(const struct drm_framebuffer *fb,
2945 int color_plane,
2946 unsigned int rotation)
2947 {
2948 int cpp = fb->format->cpp[color_plane];
2949
2950 switch (fb->modifier) {
2951 case DRM_FORMAT_MOD_LINEAR:
2952 case I915_FORMAT_MOD_X_TILED:
2953 switch (cpp) {
2954 case 8:
2955 return 4096;
2956 case 4:
2957 case 2:
2958 case 1:
2959 return 8192;
2960 default:
2961 MISSING_CASE(cpp);
2962 break;
2963 }
2964 break;
2965 case I915_FORMAT_MOD_Y_TILED_CCS:
2966 case I915_FORMAT_MOD_Yf_TILED_CCS:
2967 /* FIXME AUX plane? */
2968 case I915_FORMAT_MOD_Y_TILED:
2969 case I915_FORMAT_MOD_Yf_TILED:
2970 switch (cpp) {
2971 case 8:
2972 return 2048;
2973 case 4:
2974 return 4096;
2975 case 2:
2976 case 1:
2977 return 8192;
2978 default:
2979 MISSING_CASE(cpp);
2980 break;
2981 }
2982 break;
2983 default:
2984 MISSING_CASE(fb->modifier);
2985 }
2986
2987 return 2048;
2988 }
2989
2990 static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
2991 int main_x, int main_y, u32 main_offset)
2992 {
2993 const struct drm_framebuffer *fb = plane_state->base.fb;
2994 int hsub = fb->format->hsub;
2995 int vsub = fb->format->vsub;
2996 int aux_x = plane_state->color_plane[1].x;
2997 int aux_y = plane_state->color_plane[1].y;
2998 u32 aux_offset = plane_state->color_plane[1].offset;
2999 u32 alignment = intel_surf_alignment(fb, 1);
3000
3001 while (aux_offset >= main_offset && aux_y <= main_y) {
3002 int x, y;
3003
3004 if (aux_x == main_x && aux_y == main_y)
3005 break;
3006
3007 if (aux_offset == 0)
3008 break;
3009
3010 x = aux_x / hsub;
3011 y = aux_y / vsub;
3012 aux_offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 1,
3013 aux_offset, aux_offset - alignment);
3014 aux_x = x * hsub + aux_x % hsub;
3015 aux_y = y * vsub + aux_y % vsub;
3016 }
3017
3018 if (aux_x != main_x || aux_y != main_y)
3019 return false;
3020
3021 plane_state->color_plane[1].offset = aux_offset;
3022 plane_state->color_plane[1].x = aux_x;
3023 plane_state->color_plane[1].y = aux_y;
3024
3025 return true;
3026 }
3027
3028 static int skl_check_main_surface(struct intel_plane_state *plane_state)
3029 {
3030 const struct drm_framebuffer *fb = plane_state->base.fb;
3031 unsigned int rotation = plane_state->base.rotation;
3032 int x = plane_state->base.src.x1 >> 16;
3033 int y = plane_state->base.src.y1 >> 16;
3034 int w = drm_rect_width(&plane_state->base.src) >> 16;
3035 int h = drm_rect_height(&plane_state->base.src) >> 16;
3036 int max_width = skl_max_plane_width(fb, 0, rotation);
3037 int max_height = 4096;
3038 u32 alignment, offset, aux_offset = plane_state->color_plane[1].offset;
3039
3040 if (w > max_width || h > max_height) {
3041 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
3042 w, h, max_width, max_height);
3043 return -EINVAL;
3044 }
3045
3046 intel_add_fb_offsets(&x, &y, plane_state, 0);
3047 offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 0);
3048 alignment = intel_surf_alignment(fb, 0);
3049
3050 /*
3051 * AUX surface offset is specified as the distance from the
3052 * main surface offset, and it must be non-negative. Make
3053 * sure that is what we will get.
3054 */
3055 if (offset > aux_offset)
3056 offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3057 offset, aux_offset & ~(alignment - 1));
3058
3059 /*
3060 * When using an X-tiled surface, the plane blows up
3061 * if the x offset + width exceed the stride.
3062 *
3063 * TODO: linear and Y-tiled seem fine, Yf untested,
3064 */
3065 if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
3066 int cpp = fb->format->cpp[0];
3067
3068 while ((x + w) * cpp > plane_state->color_plane[0].stride) {
3069 if (offset == 0) {
3070 DRM_DEBUG_KMS("Unable to find suitable display surface offset due to X-tiling\n");
3071 return -EINVAL;
3072 }
3073
3074 offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3075 offset, offset - alignment);
3076 }
3077 }
3078
3079 /*
3080 * CCS AUX surface doesn't have its own x/y offsets, we must make sure
3081 * they match with the main surface x/y offsets.
3082 */
3083 if (is_ccs_modifier(fb->modifier)) {
3084 while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset)) {
3085 if (offset == 0)
3086 break;
3087
3088 offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3089 offset, offset - alignment);
3090 }
3091
3092 if (x != plane_state->color_plane[1].x || y != plane_state->color_plane[1].y) {
3093 DRM_DEBUG_KMS("Unable to find suitable display surface offset due to CCS\n");
3094 return -EINVAL;
3095 }
3096 }
3097
3098 plane_state->color_plane[0].offset = offset;
3099 plane_state->color_plane[0].x = x;
3100 plane_state->color_plane[0].y = y;
3101
3102 return 0;
3103 }
3104
3105 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
3106 {
3107 const struct drm_framebuffer *fb = plane_state->base.fb;
3108 unsigned int rotation = plane_state->base.rotation;
3109 int max_width = skl_max_plane_width(fb, 1, rotation);
3110 int max_height = 4096;
3111 int x = plane_state->base.src.x1 >> 17;
3112 int y = plane_state->base.src.y1 >> 17;
3113 int w = drm_rect_width(&plane_state->base.src) >> 17;
3114 int h = drm_rect_height(&plane_state->base.src) >> 17;
3115 u32 offset;
3116
3117 intel_add_fb_offsets(&x, &y, plane_state, 1);
3118 offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 1);
3119
3120 /* FIXME not quite sure how/if these apply to the chroma plane */
3121 if (w > max_width || h > max_height) {
3122 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
3123 w, h, max_width, max_height);
3124 return -EINVAL;
3125 }
3126
3127 plane_state->color_plane[1].offset = offset;
3128 plane_state->color_plane[1].x = x;
3129 plane_state->color_plane[1].y = y;
3130
3131 return 0;
3132 }
3133
3134 static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
3135 {
3136 const struct drm_framebuffer *fb = plane_state->base.fb;
3137 int src_x = plane_state->base.src.x1 >> 16;
3138 int src_y = plane_state->base.src.y1 >> 16;
3139 int hsub = fb->format->hsub;
3140 int vsub = fb->format->vsub;
3141 int x = src_x / hsub;
3142 int y = src_y / vsub;
3143 u32 offset;
3144
3145 intel_add_fb_offsets(&x, &y, plane_state, 1);
3146 offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 1);
3147
3148 plane_state->color_plane[1].offset = offset;
3149 plane_state->color_plane[1].x = x * hsub + src_x % hsub;
3150 plane_state->color_plane[1].y = y * vsub + src_y % vsub;
3151
3152 return 0;
3153 }
3154
3155 int skl_check_plane_surface(struct intel_plane_state *plane_state)
3156 {
3157 const struct drm_framebuffer *fb = plane_state->base.fb;
3158 unsigned int rotation = plane_state->base.rotation;
3159 int ret;
3160
3161 intel_fill_fb_ggtt_view(&plane_state->view, fb, rotation);
3162 plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0, rotation);
3163 plane_state->color_plane[1].stride = intel_fb_pitch(fb, 1, rotation);
3164
3165 ret = intel_plane_check_stride(plane_state);
3166 if (ret)
3167 return ret;
3168
3169 if (!plane_state->base.visible)
3170 return 0;
3171
3172 /* Rotate src coordinates to match rotated GTT view */
3173 if (drm_rotation_90_or_270(rotation))
3174 drm_rect_rotate(&plane_state->base.src,
3175 fb->width << 16, fb->height << 16,
3176 DRM_MODE_ROTATE_270);
3177
3178 /*
3179 * Handle the AUX surface first since
3180 * the main surface setup depends on it.
3181 */
3182 if (is_planar_yuv_format(fb->format->format)) {
3183 ret = skl_check_nv12_aux_surface(plane_state);
3184 if (ret)
3185 return ret;
3186 } else if (is_ccs_modifier(fb->modifier)) {
3187 ret = skl_check_ccs_aux_surface(plane_state);
3188 if (ret)
3189 return ret;
3190 } else {
3191 plane_state->color_plane[1].offset = ~0xfff;
3192 plane_state->color_plane[1].x = 0;
3193 plane_state->color_plane[1].y = 0;
3194 }
3195
3196 ret = skl_check_main_surface(plane_state);
3197 if (ret)
3198 return ret;
3199
3200 return 0;
3201 }
3202
3203 unsigned int
3204 i9xx_plane_max_stride(struct intel_plane *plane,
3205 u32 pixel_format, u64 modifier,
3206 unsigned int rotation)
3207 {
3208 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3209
3210 if (!HAS_GMCH(dev_priv)) {
3211 return 32*1024;
3212 } else if (INTEL_GEN(dev_priv) >= 4) {
3213 if (modifier == I915_FORMAT_MOD_X_TILED)
3214 return 16*1024;
3215 else
3216 return 32*1024;
3217 } else if (INTEL_GEN(dev_priv) >= 3) {
3218 if (modifier == I915_FORMAT_MOD_X_TILED)
3219 return 8*1024;
3220 else
3221 return 16*1024;
3222 } else {
3223 if (plane->i9xx_plane == PLANE_C)
3224 return 4*1024;
3225 else
3226 return 8*1024;
3227 }
3228 }
3229
3230 static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
3231 {
3232 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3233 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3234 u32 dspcntr = 0;
3235
3236 if (crtc_state->gamma_enable)
3237 dspcntr |= DISPPLANE_GAMMA_ENABLE;
3238
3239 if (crtc_state->csc_enable)
3240 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
3241
3242 if (INTEL_GEN(dev_priv) < 5)
3243 dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
3244
3245 return dspcntr;
3246 }
3247
3248 static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
3249 const struct intel_plane_state *plane_state)
3250 {
3251 struct drm_i915_private *dev_priv =
3252 to_i915(plane_state->base.plane->dev);
3253 const struct drm_framebuffer *fb = plane_state->base.fb;
3254 unsigned int rotation = plane_state->base.rotation;
3255 u32 dspcntr;
3256
3257 dspcntr = DISPLAY_PLANE_ENABLE;
3258
3259 if (IS_G4X(dev_priv) || IS_GEN(dev_priv, 5) ||
3260 IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
3261 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3262
3263 switch (fb->format->format) {
3264 case DRM_FORMAT_C8:
3265 dspcntr |= DISPPLANE_8BPP;
3266 break;
3267 case DRM_FORMAT_XRGB1555:
3268 dspcntr |= DISPPLANE_BGRX555;
3269 break;
3270 case DRM_FORMAT_RGB565:
3271 dspcntr |= DISPPLANE_BGRX565;
3272 break;
3273 case DRM_FORMAT_XRGB8888:
3274 dspcntr |= DISPPLANE_BGRX888;
3275 break;
3276 case DRM_FORMAT_XBGR8888:
3277 dspcntr |= DISPPLANE_RGBX888;
3278 break;
3279 case DRM_FORMAT_XRGB2101010:
3280 dspcntr |= DISPPLANE_BGRX101010;
3281 break;
3282 case DRM_FORMAT_XBGR2101010:
3283 dspcntr |= DISPPLANE_RGBX101010;
3284 break;
3285 default:
3286 MISSING_CASE(fb->format->format);
3287 return 0;
3288 }
3289
3290 if (INTEL_GEN(dev_priv) >= 4 &&
3291 fb->modifier == I915_FORMAT_MOD_X_TILED)
3292 dspcntr |= DISPPLANE_TILED;
3293
3294 if (rotation & DRM_MODE_ROTATE_180)
3295 dspcntr |= DISPPLANE_ROTATE_180;
3296
3297 if (rotation & DRM_MODE_REFLECT_X)
3298 dspcntr |= DISPPLANE_MIRROR;
3299
3300 return dspcntr;
3301 }
3302
3303 int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
3304 {
3305 struct drm_i915_private *dev_priv =
3306 to_i915(plane_state->base.plane->dev);
3307 const struct drm_framebuffer *fb = plane_state->base.fb;
3308 unsigned int rotation = plane_state->base.rotation;
3309 int src_x = plane_state->base.src.x1 >> 16;
3310 int src_y = plane_state->base.src.y1 >> 16;
3311 u32 offset;
3312 int ret;
3313
3314 intel_fill_fb_ggtt_view(&plane_state->view, fb, rotation);
3315 plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0, rotation);
3316
3317 ret = intel_plane_check_stride(plane_state);
3318 if (ret)
3319 return ret;
3320
3321 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
3322
3323 if (INTEL_GEN(dev_priv) >= 4)
3324 offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
3325 plane_state, 0);
3326 else
3327 offset = 0;
3328
3329 /* HSW/BDW do this automagically in hardware */
3330 if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
3331 int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3332 int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3333
3334 if (rotation & DRM_MODE_ROTATE_180) {
3335 src_x += src_w - 1;
3336 src_y += src_h - 1;
3337 } else if (rotation & DRM_MODE_REFLECT_X) {
3338 src_x += src_w - 1;
3339 }
3340 }
3341
3342 plane_state->color_plane[0].offset = offset;
3343 plane_state->color_plane[0].x = src_x;
3344 plane_state->color_plane[0].y = src_y;
3345
3346 return 0;
3347 }
3348
3349 static int
3350 i9xx_plane_check(struct intel_crtc_state *crtc_state,
3351 struct intel_plane_state *plane_state)
3352 {
3353 int ret;
3354
3355 ret = chv_plane_check_rotation(plane_state);
3356 if (ret)
3357 return ret;
3358
3359 ret = drm_atomic_helper_check_plane_state(&plane_state->base,
3360 &crtc_state->base,
3361 DRM_PLANE_HELPER_NO_SCALING,
3362 DRM_PLANE_HELPER_NO_SCALING,
3363 false, true);
3364 if (ret)
3365 return ret;
3366
3367 if (!plane_state->base.visible)
3368 return 0;
3369
3370 ret = intel_plane_check_src_coordinates(plane_state);
3371 if (ret)
3372 return ret;
3373
3374 ret = i9xx_check_plane_surface(plane_state);
3375 if (ret)
3376 return ret;
3377
3378 plane_state->ctl = i9xx_plane_ctl(crtc_state, plane_state);
3379
3380 return 0;
3381 }
3382
3383 static void i9xx_update_plane(struct intel_plane *plane,
3384 const struct intel_crtc_state *crtc_state,
3385 const struct intel_plane_state *plane_state)
3386 {
3387 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3388 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
3389 u32 linear_offset;
3390 int x = plane_state->color_plane[0].x;
3391 int y = plane_state->color_plane[0].y;
3392 unsigned long irqflags;
3393 u32 dspaddr_offset;
3394 u32 dspcntr;
3395
3396 dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state);
3397
3398 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3399
3400 if (INTEL_GEN(dev_priv) >= 4)
3401 dspaddr_offset = plane_state->color_plane[0].offset;
3402 else
3403 dspaddr_offset = linear_offset;
3404
3405 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3406
3407 I915_WRITE_FW(DSPSTRIDE(i9xx_plane), plane_state->color_plane[0].stride);
3408
3409 if (INTEL_GEN(dev_priv) < 4) {
3410 /* pipesrc and dspsize control the size that is scaled from,
3411 * which should always be the user's requested size.
3412 */
3413 I915_WRITE_FW(DSPPOS(i9xx_plane), 0);
3414 I915_WRITE_FW(DSPSIZE(i9xx_plane),
3415 ((crtc_state->pipe_src_h - 1) << 16) |
3416 (crtc_state->pipe_src_w - 1));
3417 } else if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) {
3418 I915_WRITE_FW(PRIMPOS(i9xx_plane), 0);
3419 I915_WRITE_FW(PRIMSIZE(i9xx_plane),
3420 ((crtc_state->pipe_src_h - 1) << 16) |
3421 (crtc_state->pipe_src_w - 1));
3422 I915_WRITE_FW(PRIMCNSTALPHA(i9xx_plane), 0);
3423 }
3424
3425 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3426 I915_WRITE_FW(DSPOFFSET(i9xx_plane), (y << 16) | x);
3427 } else if (INTEL_GEN(dev_priv) >= 4) {
3428 I915_WRITE_FW(DSPLINOFF(i9xx_plane), linear_offset);
3429 I915_WRITE_FW(DSPTILEOFF(i9xx_plane), (y << 16) | x);
3430 }
3431
3432 /*
3433 * The control register self-arms if the plane was previously
3434 * disabled. Try to make the plane enable atomic by writing
3435 * the control register just before the surface register.
3436 */
3437 I915_WRITE_FW(DSPCNTR(i9xx_plane), dspcntr);
3438 if (INTEL_GEN(dev_priv) >= 4)
3439 I915_WRITE_FW(DSPSURF(i9xx_plane),
3440 intel_plane_ggtt_offset(plane_state) +
3441 dspaddr_offset);
3442 else
3443 I915_WRITE_FW(DSPADDR(i9xx_plane),
3444 intel_plane_ggtt_offset(plane_state) +
3445 dspaddr_offset);
3446
3447 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3448 }
3449
3450 static void i9xx_disable_plane(struct intel_plane *plane,
3451 const struct intel_crtc_state *crtc_state)
3452 {
3453 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3454 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
3455 unsigned long irqflags;
3456 u32 dspcntr;
3457
3458 /*
3459 * DSPCNTR pipe gamma enable on g4x+ and pipe csc
3460 * enable on ilk+ affect the pipe bottom color as
3461 * well, so we must configure them even if the plane
3462 * is disabled.
3463 *
3464 * On pre-g4x there is no way to gamma correct the
3465 * pipe bottom color but we'll keep on doing this
3466 * anyway so that the crtc state readout works correctly.
3467 */
3468 dspcntr = i9xx_plane_ctl_crtc(crtc_state);
3469
3470 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3471
3472 I915_WRITE_FW(DSPCNTR(i9xx_plane), dspcntr);
3473 if (INTEL_GEN(dev_priv) >= 4)
3474 I915_WRITE_FW(DSPSURF(i9xx_plane), 0);
3475 else
3476 I915_WRITE_FW(DSPADDR(i9xx_plane), 0);
3477
3478 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3479 }
3480
3481 static bool i9xx_plane_get_hw_state(struct intel_plane *plane,
3482 enum pipe *pipe)
3483 {
3484 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3485 enum intel_display_power_domain power_domain;
3486 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
3487 intel_wakeref_t wakeref;
3488 bool ret;
3489 u32 val;
3490
3491 /*
3492 * Not 100% correct for planes that can move between pipes,
3493 * but that's only the case for gen2-4 which don't have any
3494 * display power wells.
3495 */
3496 power_domain = POWER_DOMAIN_PIPE(plane->pipe);
3497 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
3498 if (!wakeref)
3499 return false;
3500
3501 val = I915_READ(DSPCNTR(i9xx_plane));
3502
3503 ret = val & DISPLAY_PLANE_ENABLE;
3504
3505 if (INTEL_GEN(dev_priv) >= 5)
3506 *pipe = plane->pipe;
3507 else
3508 *pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
3509 DISPPLANE_SEL_PIPE_SHIFT;
3510
3511 intel_display_power_put(dev_priv, power_domain, wakeref);
3512
3513 return ret;
3514 }
3515
3516 static u32
3517 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
3518 {
3519 if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
3520 return 64;
3521 else
3522 return intel_tile_width_bytes(fb, color_plane);
3523 }
3524
3525 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3526 {
3527 struct drm_device *dev = intel_crtc->base.dev;
3528 struct drm_i915_private *dev_priv = to_i915(dev);
3529
3530 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3531 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3532 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
3533 }
3534
3535 /*
3536 * This function detaches (aka. unbinds) unused scalers in hardware
3537 */
3538 static void skl_detach_scalers(const struct intel_crtc_state *crtc_state)
3539 {
3540 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3541 const struct intel_crtc_scaler_state *scaler_state =
3542 &crtc_state->scaler_state;
3543 int i;
3544
3545 /* loop through and disable scalers that aren't in use */
3546 for (i = 0; i < intel_crtc->num_scalers; i++) {
3547 if (!scaler_state->scalers[i].in_use)
3548 skl_detach_scaler(intel_crtc, i);
3549 }
3550 }
3551
3552 static unsigned int skl_plane_stride_mult(const struct drm_framebuffer *fb,
3553 int color_plane, unsigned int rotation)
3554 {
3555 /*
3556 * The stride is either expressed as a multiple of 64 bytes chunks for
3557 * linear buffers or in number of tiles for tiled buffers.
3558 */
3559 if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
3560 return 64;
3561 else if (drm_rotation_90_or_270(rotation))
3562 return intel_tile_height(fb, color_plane);
3563 else
3564 return intel_tile_width_bytes(fb, color_plane);
3565 }
3566
3567 u32 skl_plane_stride(const struct intel_plane_state *plane_state,
3568 int color_plane)
3569 {
3570 const struct drm_framebuffer *fb = plane_state->base.fb;
3571 unsigned int rotation = plane_state->base.rotation;
3572 u32 stride = plane_state->color_plane[color_plane].stride;
3573
3574 if (color_plane >= fb->format->num_planes)
3575 return 0;
3576
3577 return stride / skl_plane_stride_mult(fb, color_plane, rotation);
3578 }
3579
3580 static u32 skl_plane_ctl_format(u32 pixel_format)
3581 {
3582 switch (pixel_format) {
3583 case DRM_FORMAT_C8:
3584 return PLANE_CTL_FORMAT_INDEXED;
3585 case DRM_FORMAT_RGB565:
3586 return PLANE_CTL_FORMAT_RGB_565;
3587 case DRM_FORMAT_XBGR8888:
3588 case DRM_FORMAT_ABGR8888:
3589 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3590 case DRM_FORMAT_XRGB8888:
3591 case DRM_FORMAT_ARGB8888:
3592 return PLANE_CTL_FORMAT_XRGB_8888;
3593 case DRM_FORMAT_XRGB2101010:
3594 return PLANE_CTL_FORMAT_XRGB_2101010;
3595 case DRM_FORMAT_XBGR2101010:
3596 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3597 case DRM_FORMAT_XBGR16161616F:
3598 case DRM_FORMAT_ABGR16161616F:
3599 return PLANE_CTL_FORMAT_XRGB_16161616F | PLANE_CTL_ORDER_RGBX;
3600 case DRM_FORMAT_XRGB16161616F:
3601 case DRM_FORMAT_ARGB16161616F:
3602 return PLANE_CTL_FORMAT_XRGB_16161616F;
3603 case DRM_FORMAT_YUYV:
3604 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3605 case DRM_FORMAT_YVYU:
3606 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3607 case DRM_FORMAT_UYVY:
3608 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3609 case DRM_FORMAT_VYUY:
3610 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3611 case DRM_FORMAT_NV12:
3612 return PLANE_CTL_FORMAT_NV12;
3613 case DRM_FORMAT_P010:
3614 return PLANE_CTL_FORMAT_P010;
3615 case DRM_FORMAT_P012:
3616 return PLANE_CTL_FORMAT_P012;
3617 case DRM_FORMAT_P016:
3618 return PLANE_CTL_FORMAT_P016;
3619 case DRM_FORMAT_Y210:
3620 return PLANE_CTL_FORMAT_Y210;
3621 case DRM_FORMAT_Y212:
3622 return PLANE_CTL_FORMAT_Y212;
3623 case DRM_FORMAT_Y216:
3624 return PLANE_CTL_FORMAT_Y216;
3625 case DRM_FORMAT_XVYU2101010:
3626 return PLANE_CTL_FORMAT_Y410;
3627 case DRM_FORMAT_XVYU12_16161616:
3628 return PLANE_CTL_FORMAT_Y412;
3629 case DRM_FORMAT_XVYU16161616:
3630 return PLANE_CTL_FORMAT_Y416;
3631 default:
3632 MISSING_CASE(pixel_format);
3633 }
3634
3635 return 0;
3636 }
3637
3638 static u32 skl_plane_ctl_alpha(const struct intel_plane_state *plane_state)
3639 {
3640 if (!plane_state->base.fb->format->has_alpha)
3641 return PLANE_CTL_ALPHA_DISABLE;
3642
3643 switch (plane_state->base.pixel_blend_mode) {
3644 case DRM_MODE_BLEND_PIXEL_NONE:
3645 return PLANE_CTL_ALPHA_DISABLE;
3646 case DRM_MODE_BLEND_PREMULTI:
3647 return PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3648 case DRM_MODE_BLEND_COVERAGE:
3649 return PLANE_CTL_ALPHA_HW_PREMULTIPLY;
3650 default:
3651 MISSING_CASE(plane_state->base.pixel_blend_mode);
3652 return PLANE_CTL_ALPHA_DISABLE;
3653 }
3654 }
3655
3656 static u32 glk_plane_color_ctl_alpha(const struct intel_plane_state *plane_state)
3657 {
3658 if (!plane_state->base.fb->format->has_alpha)
3659 return PLANE_COLOR_ALPHA_DISABLE;
3660
3661 switch (plane_state->base.pixel_blend_mode) {
3662 case DRM_MODE_BLEND_PIXEL_NONE:
3663 return PLANE_COLOR_ALPHA_DISABLE;
3664 case DRM_MODE_BLEND_PREMULTI:
3665 return PLANE_COLOR_ALPHA_SW_PREMULTIPLY;
3666 case DRM_MODE_BLEND_COVERAGE:
3667 return PLANE_COLOR_ALPHA_HW_PREMULTIPLY;
3668 default:
3669 MISSING_CASE(plane_state->base.pixel_blend_mode);
3670 return PLANE_COLOR_ALPHA_DISABLE;
3671 }
3672 }
3673
3674 static u32 skl_plane_ctl_tiling(u64 fb_modifier)
3675 {
3676 switch (fb_modifier) {
3677 case DRM_FORMAT_MOD_LINEAR:
3678 break;
3679 case I915_FORMAT_MOD_X_TILED:
3680 return PLANE_CTL_TILED_X;
3681 case I915_FORMAT_MOD_Y_TILED:
3682 return PLANE_CTL_TILED_Y;
3683 case I915_FORMAT_MOD_Y_TILED_CCS:
3684 return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
3685 case I915_FORMAT_MOD_Yf_TILED:
3686 return PLANE_CTL_TILED_YF;
3687 case I915_FORMAT_MOD_Yf_TILED_CCS:
3688 return PLANE_CTL_TILED_YF | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
3689 default:
3690 MISSING_CASE(fb_modifier);
3691 }
3692
3693 return 0;
3694 }
3695
3696 static u32 skl_plane_ctl_rotate(unsigned int rotate)
3697 {
3698 switch (rotate) {
3699 case DRM_MODE_ROTATE_0:
3700 break;
3701 /*
3702 * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
3703 * while i915 HW rotation is clockwise, thats why this swapping.
3704 */
3705 case DRM_MODE_ROTATE_90:
3706 return PLANE_CTL_ROTATE_270;
3707 case DRM_MODE_ROTATE_180:
3708 return PLANE_CTL_ROTATE_180;
3709 case DRM_MODE_ROTATE_270:
3710 return PLANE_CTL_ROTATE_90;
3711 default:
3712 MISSING_CASE(rotate);
3713 }
3714
3715 return 0;
3716 }
3717
3718 static u32 cnl_plane_ctl_flip(unsigned int reflect)
3719 {
3720 switch (reflect) {
3721 case 0:
3722 break;
3723 case DRM_MODE_REFLECT_X:
3724 return PLANE_CTL_FLIP_HORIZONTAL;
3725 case DRM_MODE_REFLECT_Y:
3726 default:
3727 MISSING_CASE(reflect);
3728 }
3729
3730 return 0;
3731 }
3732
3733 u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
3734 {
3735 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
3736 u32 plane_ctl = 0;
3737
3738 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
3739 return plane_ctl;
3740
3741 if (crtc_state->gamma_enable)
3742 plane_ctl |= PLANE_CTL_PIPE_GAMMA_ENABLE;
3743
3744 if (crtc_state->csc_enable)
3745 plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE;
3746
3747 return plane_ctl;
3748 }
3749
3750 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
3751 const struct intel_plane_state *plane_state)
3752 {
3753 struct drm_i915_private *dev_priv =
3754 to_i915(plane_state->base.plane->dev);
3755 const struct drm_framebuffer *fb = plane_state->base.fb;
3756 unsigned int rotation = plane_state->base.rotation;
3757 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
3758 u32 plane_ctl;
3759
3760 plane_ctl = PLANE_CTL_ENABLE;
3761
3762 if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) {
3763 plane_ctl |= skl_plane_ctl_alpha(plane_state);
3764 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3765
3766 if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
3767 plane_ctl |= PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709;
3768
3769 if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
3770 plane_ctl |= PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE;
3771 }
3772
3773 plane_ctl |= skl_plane_ctl_format(fb->format->format);
3774 plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
3775 plane_ctl |= skl_plane_ctl_rotate(rotation & DRM_MODE_ROTATE_MASK);
3776
3777 if (INTEL_GEN(dev_priv) >= 10)
3778 plane_ctl |= cnl_plane_ctl_flip(rotation &
3779 DRM_MODE_REFLECT_MASK);
3780
3781 if (key->flags & I915_SET_COLORKEY_DESTINATION)
3782 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
3783 else if (key->flags & I915_SET_COLORKEY_SOURCE)
3784 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
3785
3786 return plane_ctl;
3787 }
3788
3789 u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state)
3790 {
3791 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
3792 u32 plane_color_ctl = 0;
3793
3794 if (INTEL_GEN(dev_priv) >= 11)
3795 return plane_color_ctl;
3796
3797 if (crtc_state->gamma_enable)
3798 plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;
3799
3800 if (crtc_state->csc_enable)
3801 plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
3802
3803 return plane_color_ctl;
3804 }
3805
3806 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
3807 const struct intel_plane_state *plane_state)
3808 {
3809 struct drm_i915_private *dev_priv =
3810 to_i915(plane_state->base.plane->dev);
3811 const struct drm_framebuffer *fb = plane_state->base.fb;
3812 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
3813 u32 plane_color_ctl = 0;
3814
3815 plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
3816 plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state);
3817
3818 if (fb->format->is_yuv && !icl_is_hdr_plane(dev_priv, plane->id)) {
3819 if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
3820 plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
3821 else
3822 plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709;
3823
3824 if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
3825 plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
3826 } else if (fb->format->is_yuv) {
3827 plane_color_ctl |= PLANE_COLOR_INPUT_CSC_ENABLE;
3828 }
3829
3830 return plane_color_ctl;
3831 }
3832
3833 static int
3834 __intel_display_resume(struct drm_device *dev,
3835 struct drm_atomic_state *state,
3836 struct drm_modeset_acquire_ctx *ctx)
3837 {
3838 struct drm_crtc_state *crtc_state;
3839 struct drm_crtc *crtc;
3840 int i, ret;
3841
3842 intel_modeset_setup_hw_state(dev, ctx);
3843 i915_redisable_vga(to_i915(dev));
3844
3845 if (!state)
3846 return 0;
3847
3848 /*
3849 * We've duplicated the state, pointers to the old state are invalid.
3850 *
3851 * Don't attempt to use the old state until we commit the duplicated state.
3852 */
3853 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
3854 /*
3855 * Force recalculation even if we restore
3856 * current state. With fast modeset this may not result
3857 * in a modeset when the state is compatible.
3858 */
3859 crtc_state->mode_changed = true;
3860 }
3861
3862 /* ignore any reset values/BIOS leftovers in the WM registers */
3863 if (!HAS_GMCH(to_i915(dev)))
3864 to_intel_atomic_state(state)->skip_intermediate_wm = true;
3865
3866 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
3867
3868 WARN_ON(ret == -EDEADLK);
3869 return ret;
3870 }
3871
3872 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
3873 {
3874 return (INTEL_INFO(dev_priv)->gpu_reset_clobbers_display &&
3875 intel_has_gpu_reset(dev_priv));
3876 }
3877
3878 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3879 {
3880 struct drm_device *dev = &dev_priv->drm;
3881 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3882 struct drm_atomic_state *state;
3883 int ret;
3884
3885 /* reset doesn't touch the display */
3886 if (!i915_modparams.force_reset_modeset_test &&
3887 !gpu_reset_clobbers_display(dev_priv))
3888 return;
3889
3890 /* We have a modeset vs reset deadlock, defensively unbreak it. */
3891 set_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags);
3892 wake_up_all(&dev_priv->gpu_error.wait_queue);
3893
3894 if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) {
3895 DRM_DEBUG_KMS("Modeset potentially stuck, unbreaking through wedging\n");
3896 i915_gem_set_wedged(dev_priv);
3897 }
3898
3899 /*
3900 * Need mode_config.mutex so that we don't
3901 * trample ongoing ->detect() and whatnot.
3902 */
3903 mutex_lock(&dev->mode_config.mutex);
3904 drm_modeset_acquire_init(ctx, 0);
3905 while (1) {
3906 ret = drm_modeset_lock_all_ctx(dev, ctx);
3907 if (ret != -EDEADLK)
3908 break;
3909
3910 drm_modeset_backoff(ctx);
3911 }
3912 /*
3913 * Disabling the crtcs gracefully seems nicer. Also the
3914 * g33 docs say we should at least disable all the planes.
3915 */
3916 state = drm_atomic_helper_duplicate_state(dev, ctx);
3917 if (IS_ERR(state)) {
3918 ret = PTR_ERR(state);
3919 DRM_ERROR("Duplicating state failed with %i\n", ret);
3920 return;
3921 }
3922
3923 ret = drm_atomic_helper_disable_all(dev, ctx);
3924 if (ret) {
3925 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
3926 drm_atomic_state_put(state);
3927 return;
3928 }
3929
3930 dev_priv->modeset_restore_state = state;
3931 state->acquire_ctx = ctx;
3932 }
3933
3934 void intel_finish_reset(struct drm_i915_private *dev_priv)
3935 {
3936 struct drm_device *dev = &dev_priv->drm;
3937 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3938 struct drm_atomic_state *state;
3939 int ret;
3940
3941 /* reset doesn't touch the display */
3942 if (!test_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags))
3943 return;
3944
3945 state = fetch_and_zero(&dev_priv->modeset_restore_state);
3946 if (!state)
3947 goto unlock;
3948
3949 /* reset doesn't touch the display */
3950 if (!gpu_reset_clobbers_display(dev_priv)) {
3951 /* for testing only restore the display */
3952 ret = __intel_display_resume(dev, state, ctx);
3953 if (ret)
3954 DRM_ERROR("Restoring old state failed with %i\n", ret);
3955 } else {
3956 /*
3957 * The display has been reset as well,
3958 * so need a full re-initialization.
3959 */
3960 intel_pps_unlock_regs_wa(dev_priv);
3961 intel_modeset_init_hw(dev);
3962 intel_init_clock_gating(dev_priv);
3963
3964 spin_lock_irq(&dev_priv->irq_lock);
3965 if (dev_priv->display.hpd_irq_setup)
3966 dev_priv->display.hpd_irq_setup(dev_priv);
3967 spin_unlock_irq(&dev_priv->irq_lock);
3968
3969 ret = __intel_display_resume(dev, state, ctx);
3970 if (ret)
3971 DRM_ERROR("Restoring old state failed with %i\n", ret);
3972
3973 intel_hpd_init(dev_priv);
3974 }
3975
3976 drm_atomic_state_put(state);
3977 unlock:
3978 drm_modeset_drop_locks(ctx);
3979 drm_modeset_acquire_fini(ctx);
3980 mutex_unlock(&dev->mode_config.mutex);
3981
3982 clear_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags);
3983 }
3984
3985 static void icl_set_pipe_chicken(struct intel_crtc *crtc)
3986 {
3987 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3988 enum pipe pipe = crtc->pipe;
3989 u32 tmp;
3990
3991 tmp = I915_READ(PIPE_CHICKEN(pipe));
3992
3993 /*
3994 * Display WA #1153: icl
3995 * enable hardware to bypass the alpha math
3996 * and rounding for per-pixel values 00 and 0xff
3997 */
3998 tmp |= PER_PIXEL_ALPHA_BYPASS_EN;
3999 /*
4000 * Display WA # 1605353570: icl
4001 * Set the pixel rounding bit to 1 for allowing
4002 * passthrough of Frame buffer pixels unmodified
4003 * across pipe
4004 */
4005 tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU;
4006 I915_WRITE(PIPE_CHICKEN(pipe), tmp);
4007 }
4008
4009 static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_state,
4010 const struct intel_crtc_state *new_crtc_state)
4011 {
4012 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
4013 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4014
4015 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
4016 crtc->base.mode = new_crtc_state->base.mode;
4017
4018 /*
4019 * Update pipe size and adjust fitter if needed: the reason for this is
4020 * that in compute_mode_changes we check the native mode (not the pfit
4021 * mode) to see if we can flip rather than do a full mode set. In the
4022 * fastboot case, we'll flip, but if we don't update the pipesrc and
4023 * pfit state, we'll end up with a big fb scanned out into the wrong
4024 * sized surface.
4025 */
4026
4027 I915_WRITE(PIPESRC(crtc->pipe),
4028 ((new_crtc_state->pipe_src_w - 1) << 16) |
4029 (new_crtc_state->pipe_src_h - 1));
4030
4031 /* on skylake this is done by detaching scalers */
4032 if (INTEL_GEN(dev_priv) >= 9) {
4033 skl_detach_scalers(new_crtc_state);
4034
4035 if (new_crtc_state->pch_pfit.enabled)
4036 skylake_pfit_enable(new_crtc_state);
4037 } else if (HAS_PCH_SPLIT(dev_priv)) {
4038 if (new_crtc_state->pch_pfit.enabled)
4039 ironlake_pfit_enable(new_crtc_state);
4040 else if (old_crtc_state->pch_pfit.enabled)
4041 ironlake_pfit_disable(old_crtc_state);
4042 }
4043
4044 if (INTEL_GEN(dev_priv) >= 11)
4045 icl_set_pipe_chicken(crtc);
4046 }
4047
4048 static void intel_fdi_normal_train(struct intel_crtc *crtc)
4049 {
4050 struct drm_device *dev = crtc->base.dev;
4051 struct drm_i915_private *dev_priv = to_i915(dev);
4052 int pipe = crtc->pipe;
4053 i915_reg_t reg;
4054 u32 temp;
4055
4056 /* enable normal train */
4057 reg = FDI_TX_CTL(pipe);
4058 temp = I915_READ(reg);
4059 if (IS_IVYBRIDGE(dev_priv)) {
4060 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4061 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
4062 } else {
4063 temp &= ~FDI_LINK_TRAIN_NONE;
4064 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
4065 }
4066 I915_WRITE(reg, temp);
4067
4068 reg = FDI_RX_CTL(pipe);
4069 temp = I915_READ(reg);
4070 if (HAS_PCH_CPT(dev_priv)) {
4071 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4072 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
4073 } else {
4074 temp &= ~FDI_LINK_TRAIN_NONE;
4075 temp |= FDI_LINK_TRAIN_NONE;
4076 }
4077 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
4078
4079 /* wait one idle pattern time */
4080 POSTING_READ(reg);
4081 udelay(1000);
4082
4083 /* IVB wants error correction enabled */
4084 if (IS_IVYBRIDGE(dev_priv))
4085 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
4086 FDI_FE_ERRC_ENABLE);
4087 }
4088
4089 /* The FDI link training functions for ILK/Ibexpeak. */
4090 static void ironlake_fdi_link_train(struct intel_crtc *crtc,
4091 const struct intel_crtc_state *crtc_state)
4092 {
4093 struct drm_device *dev = crtc->base.dev;
4094 struct drm_i915_private *dev_priv = to_i915(dev);
4095 int pipe = crtc->pipe;
4096 i915_reg_t reg;
4097 u32 temp, tries;
4098
4099 /* FDI needs bits from pipe first */
4100 assert_pipe_enabled(dev_priv, pipe);
4101
4102 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4103 for train result */
4104 reg = FDI_RX_IMR(pipe);
4105 temp = I915_READ(reg);
4106 temp &= ~FDI_RX_SYMBOL_LOCK;
4107 temp &= ~FDI_RX_BIT_LOCK;
4108 I915_WRITE(reg, temp);
4109 I915_READ(reg);
4110 udelay(150);
4111
4112 /* enable CPU FDI TX and PCH FDI RX */
4113 reg = FDI_TX_CTL(pipe);
4114 temp = I915_READ(reg);
4115 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4116 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4117 temp &= ~FDI_LINK_TRAIN_NONE;
4118 temp |= FDI_LINK_TRAIN_PATTERN_1;
4119 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4120
4121 reg = FDI_RX_CTL(pipe);
4122 temp = I915_READ(reg);
4123 temp &= ~FDI_LINK_TRAIN_NONE;
4124 temp |= FDI_LINK_TRAIN_PATTERN_1;
4125 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4126
4127 POSTING_READ(reg);
4128 udelay(150);
4129
4130 /* Ironlake workaround, enable clock pointer after FDI enable*/
4131 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4132 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
4133 FDI_RX_PHASE_SYNC_POINTER_EN);
4134
4135 reg = FDI_RX_IIR(pipe);
4136 for (tries = 0; tries < 5; tries++) {
4137 temp = I915_READ(reg);
4138 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4139
4140 if ((temp & FDI_RX_BIT_LOCK)) {
4141 DRM_DEBUG_KMS("FDI train 1 done.\n");
4142 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4143 break;
4144 }
4145 }
4146 if (tries == 5)
4147 DRM_ERROR("FDI train 1 fail!\n");
4148
4149 /* Train 2 */
4150 reg = FDI_TX_CTL(pipe);
4151 temp = I915_READ(reg);
4152 temp &= ~FDI_LINK_TRAIN_NONE;
4153 temp |= FDI_LINK_TRAIN_PATTERN_2;
4154 I915_WRITE(reg, temp);
4155
4156 reg = FDI_RX_CTL(pipe);
4157 temp = I915_READ(reg);
4158 temp &= ~FDI_LINK_TRAIN_NONE;
4159 temp |= FDI_LINK_TRAIN_PATTERN_2;
4160 I915_WRITE(reg, temp);
4161
4162 POSTING_READ(reg);
4163 udelay(150);
4164
4165 reg = FDI_RX_IIR(pipe);
4166 for (tries = 0; tries < 5; tries++) {
4167 temp = I915_READ(reg);
4168 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4169
4170 if (temp & FDI_RX_SYMBOL_LOCK) {
4171 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4172 DRM_DEBUG_KMS("FDI train 2 done.\n");
4173 break;
4174 }
4175 }
4176 if (tries == 5)
4177 DRM_ERROR("FDI train 2 fail!\n");
4178
4179 DRM_DEBUG_KMS("FDI train done\n");
4180
4181 }
4182
4183 static const int snb_b_fdi_train_param[] = {
4184 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
4185 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
4186 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
4187 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
4188 };
4189
4190 /* The FDI link training functions for SNB/Cougarpoint. */
4191 static void gen6_fdi_link_train(struct intel_crtc *crtc,
4192 const struct intel_crtc_state *crtc_state)
4193 {
4194 struct drm_device *dev = crtc->base.dev;
4195 struct drm_i915_private *dev_priv = to_i915(dev);
4196 int pipe = crtc->pipe;
4197 i915_reg_t reg;
4198 u32 temp, i, retry;
4199
4200 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4201 for train result */
4202 reg = FDI_RX_IMR(pipe);
4203 temp = I915_READ(reg);
4204 temp &= ~FDI_RX_SYMBOL_LOCK;
4205 temp &= ~FDI_RX_BIT_LOCK;
4206 I915_WRITE(reg, temp);
4207
4208 POSTING_READ(reg);
4209 udelay(150);
4210
4211 /* enable CPU FDI TX and PCH FDI RX */
4212 reg = FDI_TX_CTL(pipe);
4213 temp = I915_READ(reg);
4214 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4215 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4216 temp &= ~FDI_LINK_TRAIN_NONE;
4217 temp |= FDI_LINK_TRAIN_PATTERN_1;
4218 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4219 /* SNB-B */
4220 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
4221 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4222
4223 I915_WRITE(FDI_RX_MISC(pipe),
4224 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4225
4226 reg = FDI_RX_CTL(pipe);
4227 temp = I915_READ(reg);
4228 if (HAS_PCH_CPT(dev_priv)) {
4229 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4230 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4231 } else {
4232 temp &= ~FDI_LINK_TRAIN_NONE;
4233 temp |= FDI_LINK_TRAIN_PATTERN_1;
4234 }
4235 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4236
4237 POSTING_READ(reg);
4238 udelay(150);
4239
4240 for (i = 0; i < 4; i++) {
4241 reg = FDI_TX_CTL(pipe);
4242 temp = I915_READ(reg);
4243 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4244 temp |= snb_b_fdi_train_param[i];
4245 I915_WRITE(reg, temp);
4246
4247 POSTING_READ(reg);
4248 udelay(500);
4249
4250 for (retry = 0; retry < 5; retry++) {
4251 reg = FDI_RX_IIR(pipe);
4252 temp = I915_READ(reg);
4253 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4254 if (temp & FDI_RX_BIT_LOCK) {
4255 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4256 DRM_DEBUG_KMS("FDI train 1 done.\n");
4257 break;
4258 }
4259 udelay(50);
4260 }
4261 if (retry < 5)
4262 break;
4263 }
4264 if (i == 4)
4265 DRM_ERROR("FDI train 1 fail!\n");
4266
4267 /* Train 2 */
4268 reg = FDI_TX_CTL(pipe);
4269 temp = I915_READ(reg);
4270 temp &= ~FDI_LINK_TRAIN_NONE;
4271 temp |= FDI_LINK_TRAIN_PATTERN_2;
4272 if (IS_GEN(dev_priv, 6)) {
4273 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4274 /* SNB-B */
4275 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
4276 }
4277 I915_WRITE(reg, temp);
4278
4279 reg = FDI_RX_CTL(pipe);
4280 temp = I915_READ(reg);
4281 if (HAS_PCH_CPT(dev_priv)) {
4282 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4283 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4284 } else {
4285 temp &= ~FDI_LINK_TRAIN_NONE;
4286 temp |= FDI_LINK_TRAIN_PATTERN_2;
4287 }
4288 I915_WRITE(reg, temp);
4289
4290 POSTING_READ(reg);
4291 udelay(150);
4292
4293 for (i = 0; i < 4; i++) {
4294 reg = FDI_TX_CTL(pipe);
4295 temp = I915_READ(reg);
4296 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4297 temp |= snb_b_fdi_train_param[i];
4298 I915_WRITE(reg, temp);
4299
4300 POSTING_READ(reg);
4301 udelay(500);
4302
4303 for (retry = 0; retry < 5; retry++) {
4304 reg = FDI_RX_IIR(pipe);
4305 temp = I915_READ(reg);
4306 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4307 if (temp & FDI_RX_SYMBOL_LOCK) {
4308 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4309 DRM_DEBUG_KMS("FDI train 2 done.\n");
4310 break;
4311 }
4312 udelay(50);
4313 }
4314 if (retry < 5)
4315 break;
4316 }
4317 if (i == 4)
4318 DRM_ERROR("FDI train 2 fail!\n");
4319
4320 DRM_DEBUG_KMS("FDI train done.\n");
4321 }
4322
4323 /* Manual link training for Ivy Bridge A0 parts */
4324 static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
4325 const struct intel_crtc_state *crtc_state)
4326 {
4327 struct drm_device *dev = crtc->base.dev;
4328 struct drm_i915_private *dev_priv = to_i915(dev);
4329 int pipe = crtc->pipe;
4330 i915_reg_t reg;
4331 u32 temp, i, j;
4332
4333 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4334 for train result */
4335 reg = FDI_RX_IMR(pipe);
4336 temp = I915_READ(reg);
4337 temp &= ~FDI_RX_SYMBOL_LOCK;
4338 temp &= ~FDI_RX_BIT_LOCK;
4339 I915_WRITE(reg, temp);
4340
4341 POSTING_READ(reg);
4342 udelay(150);
4343
4344 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
4345 I915_READ(FDI_RX_IIR(pipe)));
4346
4347 /* Try each vswing and preemphasis setting twice before moving on */
4348 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
4349 /* disable first in case we need to retry */
4350 reg = FDI_TX_CTL(pipe);
4351 temp = I915_READ(reg);
4352 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
4353 temp &= ~FDI_TX_ENABLE;
4354 I915_WRITE(reg, temp);
4355
4356 reg = FDI_RX_CTL(pipe);
4357 temp = I915_READ(reg);
4358 temp &= ~FDI_LINK_TRAIN_AUTO;
4359 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4360 temp &= ~FDI_RX_ENABLE;
4361 I915_WRITE(reg, temp);
4362
4363 /* enable CPU FDI TX and PCH FDI RX */
4364 reg = FDI_TX_CTL(pipe);
4365 temp = I915_READ(reg);
4366 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4367 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4368 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
4369 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4370 temp |= snb_b_fdi_train_param[j/2];
4371 temp |= FDI_COMPOSITE_SYNC;
4372 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4373
4374 I915_WRITE(FDI_RX_MISC(pipe),
4375 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4376
4377 reg = FDI_RX_CTL(pipe);
4378 temp = I915_READ(reg);
4379 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4380 temp |= FDI_COMPOSITE_SYNC;
4381 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4382
4383 POSTING_READ(reg);
4384 udelay(1); /* should be 0.5us */
4385
4386 for (i = 0; i < 4; i++) {
4387 reg = FDI_RX_IIR(pipe);
4388 temp = I915_READ(reg);
4389 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4390
4391 if (temp & FDI_RX_BIT_LOCK ||
4392 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
4393 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4394 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4395 i);
4396 break;
4397 }
4398 udelay(1); /* should be 0.5us */
4399 }
4400 if (i == 4) {
4401 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4402 continue;
4403 }
4404
4405 /* Train 2 */
4406 reg = FDI_TX_CTL(pipe);
4407 temp = I915_READ(reg);
4408 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4409 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4410 I915_WRITE(reg, temp);
4411
4412 reg = FDI_RX_CTL(pipe);
4413 temp = I915_READ(reg);
4414 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4415 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4416 I915_WRITE(reg, temp);
4417
4418 POSTING_READ(reg);
4419 udelay(2); /* should be 1.5us */
4420
4421 for (i = 0; i < 4; i++) {
4422 reg = FDI_RX_IIR(pipe);
4423 temp = I915_READ(reg);
4424 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4425
4426 if (temp & FDI_RX_SYMBOL_LOCK ||
4427 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4428 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4429 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4430 i);
4431 goto train_done;
4432 }
4433 udelay(2); /* should be 1.5us */
4434 }
4435 if (i == 4)
4436 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
4437 }
4438
4439 train_done:
4440 DRM_DEBUG_KMS("FDI train done.\n");
4441 }
4442
4443 static void ironlake_fdi_pll_enable(const struct intel_crtc_state *crtc_state)
4444 {
4445 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4446 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4447 int pipe = intel_crtc->pipe;
4448 i915_reg_t reg;
4449 u32 temp;
4450
4451 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4452 reg = FDI_RX_CTL(pipe);
4453 temp = I915_READ(reg);
4454 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
4455 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4456 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4457 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4458
4459 POSTING_READ(reg);
4460 udelay(200);
4461
4462 /* Switch from Rawclk to PCDclk */
4463 temp = I915_READ(reg);
4464 I915_WRITE(reg, temp | FDI_PCDCLK);
4465
4466 POSTING_READ(reg);
4467 udelay(200);
4468
4469 /* Enable CPU FDI TX PLL, always on for Ironlake */
4470 reg = FDI_TX_CTL(pipe);
4471 temp = I915_READ(reg);
4472 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
4473 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4474
4475 POSTING_READ(reg);
4476 udelay(100);
4477 }
4478 }
4479
4480 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
4481 {
4482 struct drm_device *dev = intel_crtc->base.dev;
4483 struct drm_i915_private *dev_priv = to_i915(dev);
4484 int pipe = intel_crtc->pipe;
4485 i915_reg_t reg;
4486 u32 temp;
4487
4488 /* Switch from PCDclk to Rawclk */
4489 reg = FDI_RX_CTL(pipe);
4490 temp = I915_READ(reg);
4491 I915_WRITE(reg, temp & ~FDI_PCDCLK);
4492
4493 /* Disable CPU FDI TX PLL */
4494 reg = FDI_TX_CTL(pipe);
4495 temp = I915_READ(reg);
4496 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
4497
4498 POSTING_READ(reg);
4499 udelay(100);
4500
4501 reg = FDI_RX_CTL(pipe);
4502 temp = I915_READ(reg);
4503 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
4504
4505 /* Wait for the clocks to turn off. */
4506 POSTING_READ(reg);
4507 udelay(100);
4508 }
4509
4510 static void ironlake_fdi_disable(struct drm_crtc *crtc)
4511 {
4512 struct drm_device *dev = crtc->dev;
4513 struct drm_i915_private *dev_priv = to_i915(dev);
4514 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4515 int pipe = intel_crtc->pipe;
4516 i915_reg_t reg;
4517 u32 temp;
4518
4519 /* disable CPU FDI tx and PCH FDI rx */
4520 reg = FDI_TX_CTL(pipe);
4521 temp = I915_READ(reg);
4522 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
4523 POSTING_READ(reg);
4524
4525 reg = FDI_RX_CTL(pipe);
4526 temp = I915_READ(reg);
4527 temp &= ~(0x7 << 16);
4528 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4529 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
4530
4531 POSTING_READ(reg);
4532 udelay(100);
4533
4534 /* Ironlake workaround, disable clock pointer after downing FDI */
4535 if (HAS_PCH_IBX(dev_priv))
4536 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4537
4538 /* still set train pattern 1 */
4539 reg = FDI_TX_CTL(pipe);
4540 temp = I915_READ(reg);
4541 temp &= ~FDI_LINK_TRAIN_NONE;
4542 temp |= FDI_LINK_TRAIN_PATTERN_1;
4543 I915_WRITE(reg, temp);
4544
4545 reg = FDI_RX_CTL(pipe);
4546 temp = I915_READ(reg);
4547 if (HAS_PCH_CPT(dev_priv)) {
4548 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4549 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4550 } else {
4551 temp &= ~FDI_LINK_TRAIN_NONE;
4552 temp |= FDI_LINK_TRAIN_PATTERN_1;
4553 }
4554 /* BPC in FDI rx is consistent with that in PIPECONF */
4555 temp &= ~(0x07 << 16);
4556 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4557 I915_WRITE(reg, temp);
4558
4559 POSTING_READ(reg);
4560 udelay(100);
4561 }
4562
4563 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
4564 {
4565 struct drm_crtc *crtc;
4566 bool cleanup_done;
4567
4568 drm_for_each_crtc(crtc, &dev_priv->drm) {
4569 struct drm_crtc_commit *commit;
4570 spin_lock(&crtc->commit_lock);
4571 commit = list_first_entry_or_null(&crtc->commit_list,
4572 struct drm_crtc_commit, commit_entry);
4573 cleanup_done = commit ?
4574 try_wait_for_completion(&commit->cleanup_done) : true;
4575 spin_unlock(&crtc->commit_lock);
4576
4577 if (cleanup_done)
4578 continue;
4579
4580 drm_crtc_wait_one_vblank(crtc);
4581
4582 return true;
4583 }
4584
4585 return false;
4586 }
4587
4588 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
4589 {
4590 u32 temp;
4591
4592 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
4593
4594 mutex_lock(&dev_priv->sb_lock);
4595
4596 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4597 temp |= SBI_SSCCTL_DISABLE;
4598 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4599
4600 mutex_unlock(&dev_priv->sb_lock);
4601 }
4602
4603 /* Program iCLKIP clock to the desired frequency */
4604 static void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
4605 {
4606 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4607 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4608 int clock = crtc_state->base.adjusted_mode.crtc_clock;
4609 u32 divsel, phaseinc, auxdiv, phasedir = 0;
4610 u32 temp;
4611
4612 lpt_disable_iclkip(dev_priv);
4613
4614 /* The iCLK virtual clock root frequency is in MHz,
4615 * but the adjusted_mode->crtc_clock in in KHz. To get the
4616 * divisors, it is necessary to divide one by another, so we
4617 * convert the virtual clock precision to KHz here for higher
4618 * precision.
4619 */
4620 for (auxdiv = 0; auxdiv < 2; auxdiv++) {
4621 u32 iclk_virtual_root_freq = 172800 * 1000;
4622 u32 iclk_pi_range = 64;
4623 u32 desired_divisor;
4624
4625 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4626 clock << auxdiv);
4627 divsel = (desired_divisor / iclk_pi_range) - 2;
4628 phaseinc = desired_divisor % iclk_pi_range;
4629
4630 /*
4631 * Near 20MHz is a corner case which is
4632 * out of range for the 7-bit divisor
4633 */
4634 if (divsel <= 0x7f)
4635 break;
4636 }
4637
4638 /* This should not happen with any sane values */
4639 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4640 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4641 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4642 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4643
4644 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4645 clock,
4646 auxdiv,
4647 divsel,
4648 phasedir,
4649 phaseinc);
4650
4651 mutex_lock(&dev_priv->sb_lock);
4652
4653 /* Program SSCDIVINTPHASE6 */
4654 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4655 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4656 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4657 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4658 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4659 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4660 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4661 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4662
4663 /* Program SSCAUXDIV */
4664 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4665 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4666 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4667 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4668
4669 /* Enable modulator and associated divider */
4670 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4671 temp &= ~SBI_SSCCTL_DISABLE;
4672 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4673
4674 mutex_unlock(&dev_priv->sb_lock);
4675
4676 /* Wait for initialization time */
4677 udelay(24);
4678
4679 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4680 }
4681
4682 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
4683 {
4684 u32 divsel, phaseinc, auxdiv;
4685 u32 iclk_virtual_root_freq = 172800 * 1000;
4686 u32 iclk_pi_range = 64;
4687 u32 desired_divisor;
4688 u32 temp;
4689
4690 if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
4691 return 0;
4692
4693 mutex_lock(&dev_priv->sb_lock);
4694
4695 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4696 if (temp & SBI_SSCCTL_DISABLE) {
4697 mutex_unlock(&dev_priv->sb_lock);
4698 return 0;
4699 }
4700
4701 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4702 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4703 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4704 phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4705 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4706
4707 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4708 auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4709 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4710
4711 mutex_unlock(&dev_priv->sb_lock);
4712
4713 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4714
4715 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4716 desired_divisor << auxdiv);
4717 }
4718
4719 static void ironlake_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_state,
4720 enum pipe pch_transcoder)
4721 {
4722 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4723 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4724 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
4725
4726 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4727 I915_READ(HTOTAL(cpu_transcoder)));
4728 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4729 I915_READ(HBLANK(cpu_transcoder)));
4730 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4731 I915_READ(HSYNC(cpu_transcoder)));
4732
4733 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4734 I915_READ(VTOTAL(cpu_transcoder)));
4735 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4736 I915_READ(VBLANK(cpu_transcoder)));
4737 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4738 I915_READ(VSYNC(cpu_transcoder)));
4739 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4740 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4741 }
4742
4743 static void cpt_set_fdi_bc_bifurcation(struct drm_i915_private *dev_priv, bool enable)
4744 {
4745 u32 temp;
4746
4747 temp = I915_READ(SOUTH_CHICKEN1);
4748 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4749 return;
4750
4751 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4752 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4753
4754 temp &= ~FDI_BC_BIFURCATION_SELECT;
4755 if (enable)
4756 temp |= FDI_BC_BIFURCATION_SELECT;
4757
4758 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4759 I915_WRITE(SOUTH_CHICKEN1, temp);
4760 POSTING_READ(SOUTH_CHICKEN1);
4761 }
4762
4763 static void ivybridge_update_fdi_bc_bifurcation(const struct intel_crtc_state *crtc_state)
4764 {
4765 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4766 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4767
4768 switch (crtc->pipe) {
4769 case PIPE_A:
4770 break;
4771 case PIPE_B:
4772 if (crtc_state->fdi_lanes > 2)
4773 cpt_set_fdi_bc_bifurcation(dev_priv, false);
4774 else
4775 cpt_set_fdi_bc_bifurcation(dev_priv, true);
4776
4777 break;
4778 case PIPE_C:
4779 cpt_set_fdi_bc_bifurcation(dev_priv, true);
4780
4781 break;
4782 default:
4783 BUG();
4784 }
4785 }
4786
4787 /*
4788 * Finds the encoder associated with the given CRTC. This can only be
4789 * used when we know that the CRTC isn't feeding multiple encoders!
4790 */
4791 static struct intel_encoder *
4792 intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
4793 const struct intel_crtc_state *crtc_state)
4794 {
4795 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4796 const struct drm_connector_state *connector_state;
4797 const struct drm_connector *connector;
4798 struct intel_encoder *encoder = NULL;
4799 int num_encoders = 0;
4800 int i;
4801
4802 for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
4803 if (connector_state->crtc != &crtc->base)
4804 continue;
4805
4806 encoder = to_intel_encoder(connector_state->best_encoder);
4807 num_encoders++;
4808 }
4809
4810 WARN(num_encoders != 1, "%d encoders for pipe %c\n",
4811 num_encoders, pipe_name(crtc->pipe));
4812
4813 return encoder;
4814 }
4815
4816 /*
4817 * Enable PCH resources required for PCH ports:
4818 * - PCH PLLs
4819 * - FDI training & RX/TX
4820 * - update transcoder timings
4821 * - DP transcoding bits
4822 * - transcoder
4823 */
4824 static void ironlake_pch_enable(const struct intel_atomic_state *state,
4825 const struct intel_crtc_state *crtc_state)
4826 {
4827 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4828 struct drm_device *dev = crtc->base.dev;
4829 struct drm_i915_private *dev_priv = to_i915(dev);
4830 int pipe = crtc->pipe;
4831 u32 temp;
4832
4833 assert_pch_transcoder_disabled(dev_priv, pipe);
4834
4835 if (IS_IVYBRIDGE(dev_priv))
4836 ivybridge_update_fdi_bc_bifurcation(crtc_state);
4837
4838 /* Write the TU size bits before fdi link training, so that error
4839 * detection works. */
4840 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4841 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4842
4843 /* For PCH output, training FDI link */
4844 dev_priv->display.fdi_link_train(crtc, crtc_state);
4845
4846 /* We need to program the right clock selection before writing the pixel
4847 * mutliplier into the DPLL. */
4848 if (HAS_PCH_CPT(dev_priv)) {
4849 u32 sel;
4850
4851 temp = I915_READ(PCH_DPLL_SEL);
4852 temp |= TRANS_DPLL_ENABLE(pipe);
4853 sel = TRANS_DPLLB_SEL(pipe);
4854 if (crtc_state->shared_dpll ==
4855 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4856 temp |= sel;
4857 else
4858 temp &= ~sel;
4859 I915_WRITE(PCH_DPLL_SEL, temp);
4860 }
4861
4862 /* XXX: pch pll's can be enabled any time before we enable the PCH
4863 * transcoder, and we actually should do this to not upset any PCH
4864 * transcoder that already use the clock when we share it.
4865 *
4866 * Note that enable_shared_dpll tries to do the right thing, but
4867 * get_shared_dpll unconditionally resets the pll - we need that to have
4868 * the right LVDS enable sequence. */
4869 intel_enable_shared_dpll(crtc_state);
4870
4871 /* set transcoder timing, panel must allow it */
4872 assert_panel_unlocked(dev_priv, pipe);
4873 ironlake_pch_transcoder_set_timings(crtc_state, pipe);
4874
4875 intel_fdi_normal_train(crtc);
4876
4877 /* For PCH DP, enable TRANS_DP_CTL */
4878 if (HAS_PCH_CPT(dev_priv) &&
4879 intel_crtc_has_dp_encoder(crtc_state)) {
4880 const struct drm_display_mode *adjusted_mode =
4881 &crtc_state->base.adjusted_mode;
4882 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4883 i915_reg_t reg = TRANS_DP_CTL(pipe);
4884 enum port port;
4885
4886 temp = I915_READ(reg);
4887 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4888 TRANS_DP_SYNC_MASK |
4889 TRANS_DP_BPC_MASK);
4890 temp |= TRANS_DP_OUTPUT_ENABLE;
4891 temp |= bpc << 9; /* same format but at 11:9 */
4892
4893 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4894 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4895 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4896 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4897
4898 port = intel_get_crtc_new_encoder(state, crtc_state)->port;
4899 WARN_ON(port < PORT_B || port > PORT_D);
4900 temp |= TRANS_DP_PORT_SEL(port);
4901
4902 I915_WRITE(reg, temp);
4903 }
4904
4905 ironlake_enable_pch_transcoder(crtc_state);
4906 }
4907
4908 static void lpt_pch_enable(const struct intel_atomic_state *state,
4909 const struct intel_crtc_state *crtc_state)
4910 {
4911 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4912 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4913 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
4914
4915 assert_pch_transcoder_disabled(dev_priv, PIPE_A);
4916
4917 lpt_program_iclkip(crtc_state);
4918
4919 /* Set transcoder timing. */
4920 ironlake_pch_transcoder_set_timings(crtc_state, PIPE_A);
4921
4922 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4923 }
4924
4925 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4926 {
4927 struct drm_i915_private *dev_priv = to_i915(dev);
4928 i915_reg_t dslreg = PIPEDSL(pipe);
4929 u32 temp;
4930
4931 temp = I915_READ(dslreg);
4932 udelay(500);
4933 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4934 if (wait_for(I915_READ(dslreg) != temp, 5))
4935 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4936 }
4937 }
4938
4939 /*
4940 * The hardware phase 0.0 refers to the center of the pixel.
4941 * We want to start from the top/left edge which is phase
4942 * -0.5. That matches how the hardware calculates the scaling
4943 * factors (from top-left of the first pixel to bottom-right
4944 * of the last pixel, as opposed to the pixel centers).
4945 *
4946 * For 4:2:0 subsampled chroma planes we obviously have to
4947 * adjust that so that the chroma sample position lands in
4948 * the right spot.
4949 *
4950 * Note that for packed YCbCr 4:2:2 formats there is no way to
4951 * control chroma siting. The hardware simply replicates the
4952 * chroma samples for both of the luma samples, and thus we don't
4953 * actually get the expected MPEG2 chroma siting convention :(
4954 * The same behaviour is observed on pre-SKL platforms as well.
4955 *
4956 * Theory behind the formula (note that we ignore sub-pixel
4957 * source coordinates):
4958 * s = source sample position
4959 * d = destination sample position
4960 *
4961 * Downscaling 4:1:
4962 * -0.5
4963 * | 0.0
4964 * | | 1.5 (initial phase)
4965 * | | |
4966 * v v v
4967 * | s | s | s | s |
4968 * | d |
4969 *
4970 * Upscaling 1:4:
4971 * -0.5
4972 * | -0.375 (initial phase)
4973 * | | 0.0
4974 * | | |
4975 * v v v
4976 * | s |
4977 * | d | d | d | d |
4978 */
4979 u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_cosited)
4980 {
4981 int phase = -0x8000;
4982 u16 trip = 0;
4983
4984 if (chroma_cosited)
4985 phase += (sub - 1) * 0x8000 / sub;
4986
4987 phase += scale / (2 * sub);
4988
4989 /*
4990 * Hardware initial phase limited to [-0.5:1.5].
4991 * Since the max hardware scale factor is 3.0, we
4992 * should never actually excdeed 1.0 here.
4993 */
4994 WARN_ON(phase < -0x8000 || phase > 0x18000);
4995
4996 if (phase < 0)
4997 phase = 0x10000 + phase;
4998 else
4999 trip = PS_PHASE_TRIP;
5000
5001 return ((phase >> 2) & PS_PHASE_MASK) | trip;
5002 }
5003
5004 static int
5005 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
5006 unsigned int scaler_user, int *scaler_id,
5007 int src_w, int src_h, int dst_w, int dst_h,
5008 const struct drm_format_info *format, bool need_scaler)
5009 {
5010 struct intel_crtc_scaler_state *scaler_state =
5011 &crtc_state->scaler_state;
5012 struct intel_crtc *intel_crtc =
5013 to_intel_crtc(crtc_state->base.crtc);
5014 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
5015 const struct drm_display_mode *adjusted_mode =
5016 &crtc_state->base.adjusted_mode;
5017
5018 /*
5019 * Src coordinates are already rotated by 270 degrees for
5020 * the 90/270 degree plane rotation cases (to match the
5021 * GTT mapping), hence no need to account for rotation here.
5022 */
5023 if (src_w != dst_w || src_h != dst_h)
5024 need_scaler = true;
5025
5026 /*
5027 * Scaling/fitting not supported in IF-ID mode in GEN9+
5028 * TODO: Interlace fetch mode doesn't support YUV420 planar formats.
5029 * Once NV12 is enabled, handle it here while allocating scaler
5030 * for NV12.
5031 */
5032 if (INTEL_GEN(dev_priv) >= 9 && crtc_state->base.enable &&
5033 need_scaler && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5034 DRM_DEBUG_KMS("Pipe/Plane scaling not supported with IF-ID mode\n");
5035 return -EINVAL;
5036 }
5037
5038 /*
5039 * if plane is being disabled or scaler is no more required or force detach
5040 * - free scaler binded to this plane/crtc
5041 * - in order to do this, update crtc->scaler_usage
5042 *
5043 * Here scaler state in crtc_state is set free so that
5044 * scaler can be assigned to other user. Actual register
5045 * update to free the scaler is done in plane/panel-fit programming.
5046 * For this purpose crtc/plane_state->scaler_id isn't reset here.
5047 */
5048 if (force_detach || !need_scaler) {
5049 if (*scaler_id >= 0) {
5050 scaler_state->scaler_users &= ~(1 << scaler_user);
5051 scaler_state->scalers[*scaler_id].in_use = 0;
5052
5053 DRM_DEBUG_KMS("scaler_user index %u.%u: "
5054 "Staged freeing scaler id %d scaler_users = 0x%x\n",
5055 intel_crtc->pipe, scaler_user, *scaler_id,
5056 scaler_state->scaler_users);
5057 *scaler_id = -1;
5058 }
5059 return 0;
5060 }
5061
5062 if (format && is_planar_yuv_format(format->format) &&
5063 (src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) {
5064 DRM_DEBUG_KMS("Planar YUV: src dimensions not met\n");
5065 return -EINVAL;
5066 }
5067
5068 /* range checks */
5069 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
5070 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
5071 (INTEL_GEN(dev_priv) >= 11 &&
5072 (src_w > ICL_MAX_SRC_W || src_h > ICL_MAX_SRC_H ||
5073 dst_w > ICL_MAX_DST_W || dst_h > ICL_MAX_DST_H)) ||
5074 (INTEL_GEN(dev_priv) < 11 &&
5075 (src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
5076 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H))) {
5077 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
5078 "size is out of scaler range\n",
5079 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
5080 return -EINVAL;
5081 }
5082
5083 /* mark this plane as a scaler user in crtc_state */
5084 scaler_state->scaler_users |= (1 << scaler_user);
5085 DRM_DEBUG_KMS("scaler_user index %u.%u: "
5086 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
5087 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
5088 scaler_state->scaler_users);
5089
5090 return 0;
5091 }
5092
5093 /**
5094 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
5095 *
5096 * @state: crtc's scaler state
5097 *
5098 * Return
5099 * 0 - scaler_usage updated successfully
5100 * error - requested scaling cannot be supported or other error condition
5101 */
5102 int skl_update_scaler_crtc(struct intel_crtc_state *state)
5103 {
5104 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
5105 bool need_scaler = false;
5106
5107 if (state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
5108 need_scaler = true;
5109
5110 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
5111 &state->scaler_state.scaler_id,
5112 state->pipe_src_w, state->pipe_src_h,
5113 adjusted_mode->crtc_hdisplay,
5114 adjusted_mode->crtc_vdisplay, NULL, need_scaler);
5115 }
5116
5117 /**
5118 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
5119 * @crtc_state: crtc's scaler state
5120 * @plane_state: atomic plane state to update
5121 *
5122 * Return
5123 * 0 - scaler_usage updated successfully
5124 * error - requested scaling cannot be supported or other error condition
5125 */
5126 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
5127 struct intel_plane_state *plane_state)
5128 {
5129 struct intel_plane *intel_plane =
5130 to_intel_plane(plane_state->base.plane);
5131 struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
5132 struct drm_framebuffer *fb = plane_state->base.fb;
5133 int ret;
5134 bool force_detach = !fb || !plane_state->base.visible;
5135 bool need_scaler = false;
5136
5137 /* Pre-gen11 and SDR planes always need a scaler for planar formats. */
5138 if (!icl_is_hdr_plane(dev_priv, intel_plane->id) &&
5139 fb && is_planar_yuv_format(fb->format->format))
5140 need_scaler = true;
5141
5142 ret = skl_update_scaler(crtc_state, force_detach,
5143 drm_plane_index(&intel_plane->base),
5144 &plane_state->scaler_id,
5145 drm_rect_width(&plane_state->base.src) >> 16,
5146 drm_rect_height(&plane_state->base.src) >> 16,
5147 drm_rect_width(&plane_state->base.dst),
5148 drm_rect_height(&plane_state->base.dst),
5149 fb ? fb->format : NULL, need_scaler);
5150
5151 if (ret || plane_state->scaler_id < 0)
5152 return ret;
5153
5154 /* check colorkey */
5155 if (plane_state->ckey.flags) {
5156 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
5157 intel_plane->base.base.id,
5158 intel_plane->base.name);
5159 return -EINVAL;
5160 }
5161
5162 /* Check src format */
5163 switch (fb->format->format) {
5164 case DRM_FORMAT_RGB565:
5165 case DRM_FORMAT_XBGR8888:
5166 case DRM_FORMAT_XRGB8888:
5167 case DRM_FORMAT_ABGR8888:
5168 case DRM_FORMAT_ARGB8888:
5169 case DRM_FORMAT_XRGB2101010:
5170 case DRM_FORMAT_XBGR2101010:
5171 case DRM_FORMAT_XBGR16161616F:
5172 case DRM_FORMAT_ABGR16161616F:
5173 case DRM_FORMAT_XRGB16161616F:
5174 case DRM_FORMAT_ARGB16161616F:
5175 case DRM_FORMAT_YUYV:
5176 case DRM_FORMAT_YVYU:
5177 case DRM_FORMAT_UYVY:
5178 case DRM_FORMAT_VYUY:
5179 case DRM_FORMAT_NV12:
5180 case DRM_FORMAT_P010:
5181 case DRM_FORMAT_P012:
5182 case DRM_FORMAT_P016:
5183 case DRM_FORMAT_Y210:
5184 case DRM_FORMAT_Y212:
5185 case DRM_FORMAT_Y216:
5186 case DRM_FORMAT_XVYU2101010:
5187 case DRM_FORMAT_XVYU12_16161616:
5188 case DRM_FORMAT_XVYU16161616:
5189 break;
5190 default:
5191 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
5192 intel_plane->base.base.id, intel_plane->base.name,
5193 fb->base.id, fb->format->format);
5194 return -EINVAL;
5195 }
5196
5197 return 0;
5198 }
5199
5200 static void skylake_scaler_disable(struct intel_crtc *crtc)
5201 {
5202 int i;
5203
5204 for (i = 0; i < crtc->num_scalers; i++)
5205 skl_detach_scaler(crtc, i);
5206 }
5207
5208 static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state)
5209 {
5210 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
5211 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5212 enum pipe pipe = crtc->pipe;
5213 const struct intel_crtc_scaler_state *scaler_state =
5214 &crtc_state->scaler_state;
5215
5216 if (crtc_state->pch_pfit.enabled) {
5217 u16 uv_rgb_hphase, uv_rgb_vphase;
5218 int pfit_w, pfit_h, hscale, vscale;
5219 int id;
5220
5221 if (WARN_ON(crtc_state->scaler_state.scaler_id < 0))
5222 return;
5223
5224 pfit_w = (crtc_state->pch_pfit.size >> 16) & 0xFFFF;
5225 pfit_h = crtc_state->pch_pfit.size & 0xFFFF;
5226
5227 hscale = (crtc_state->pipe_src_w << 16) / pfit_w;
5228 vscale = (crtc_state->pipe_src_h << 16) / pfit_h;
5229
5230 uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
5231 uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
5232
5233 id = scaler_state->scaler_id;
5234 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
5235 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
5236 I915_WRITE_FW(SKL_PS_VPHASE(pipe, id),
5237 PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase));
5238 I915_WRITE_FW(SKL_PS_HPHASE(pipe, id),
5239 PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase));
5240 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc_state->pch_pfit.pos);
5241 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc_state->pch_pfit.size);
5242 }
5243 }
5244
5245 static void ironlake_pfit_enable(const struct intel_crtc_state *crtc_state)
5246 {
5247 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
5248 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5249 int pipe = crtc->pipe;
5250
5251 if (crtc_state->pch_pfit.enabled) {
5252 /* Force use of hard-coded filter coefficients
5253 * as some pre-programmed values are broken,
5254 * e.g. x201.
5255 */
5256 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
5257 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
5258 PF_PIPE_SEL_IVB(pipe));
5259 else
5260 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
5261 I915_WRITE(PF_WIN_POS(pipe), crtc_state->pch_pfit.pos);
5262 I915_WRITE(PF_WIN_SZ(pipe), crtc_state->pch_pfit.size);
5263 }
5264 }
5265
5266 void hsw_enable_ips(const struct intel_crtc_state *crtc_state)
5267 {
5268 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
5269 struct drm_device *dev = crtc->base.dev;
5270 struct drm_i915_private *dev_priv = to_i915(dev);
5271
5272 if (!crtc_state->ips_enabled)
5273 return;
5274
5275 /*
5276 * We can only enable IPS after we enable a plane and wait for a vblank
5277 * This function is called from post_plane_update, which is run after
5278 * a vblank wait.
5279 */
5280 WARN_ON(!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)));
5281
5282 if (IS_BROADWELL(dev_priv)) {
5283 mutex_lock(&dev_priv->pcu_lock);
5284 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
5285 IPS_ENABLE | IPS_PCODE_CONTROL));
5286 mutex_unlock(&dev_priv->pcu_lock);
5287 /* Quoting Art Runyan: "its not safe to expect any particular
5288 * value in IPS_CTL bit 31 after enabling IPS through the
5289 * mailbox." Moreover, the mailbox may return a bogus state,
5290 * so we need to just enable it and continue on.
5291 */
5292 } else {
5293 I915_WRITE(IPS_CTL, IPS_ENABLE);
5294 /* The bit only becomes 1 in the next vblank, so this wait here
5295 * is essentially intel_wait_for_vblank. If we don't have this
5296 * and don't wait for vblanks until the end of crtc_enable, then
5297 * the HW state readout code will complain that the expected
5298 * IPS_CTL value is not the one we read. */
5299 if (intel_wait_for_register(&dev_priv->uncore,
5300 IPS_CTL, IPS_ENABLE, IPS_ENABLE,
5301 50))
5302 DRM_ERROR("Timed out waiting for IPS enable\n");
5303 }
5304 }
5305
5306 void hsw_disable_ips(const struct intel_crtc_state *crtc_state)
5307 {
5308 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
5309 struct drm_device *dev = crtc->base.dev;
5310 struct drm_i915_private *dev_priv = to_i915(dev);
5311
5312 if (!crtc_state->ips_enabled)
5313 return;
5314
5315 if (IS_BROADWELL(dev_priv)) {
5316 mutex_lock(&dev_priv->pcu_lock);
5317 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
5318 mutex_unlock(&dev_priv->pcu_lock);
5319 /*
5320 * Wait for PCODE to finish disabling IPS. The BSpec specified
5321 * 42ms timeout value leads to occasional timeouts so use 100ms
5322 * instead.
5323 */
5324 if (intel_wait_for_register(&dev_priv->uncore,
5325 IPS_CTL, IPS_ENABLE, 0,
5326 100))
5327 DRM_ERROR("Timed out waiting for IPS disable\n");
5328 } else {
5329 I915_WRITE(IPS_CTL, 0);
5330 POSTING_READ(IPS_CTL);
5331 }
5332
5333 /* We need to wait for a vblank before we can disable the plane. */
5334 intel_wait_for_vblank(dev_priv, crtc->pipe);
5335 }
5336
5337 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
5338 {
5339 if (intel_crtc->overlay) {
5340 struct drm_device *dev = intel_crtc->base.dev;
5341
5342 mutex_lock(&dev->struct_mutex);
5343 (void) intel_overlay_switch_off(intel_crtc->overlay);
5344 mutex_unlock(&dev->struct_mutex);
5345 }
5346
5347 /* Let userspace switch the overlay on again. In most cases userspace
5348 * has to recompute where to put it anyway.
5349 */
5350 }
5351
5352 /**
5353 * intel_post_enable_primary - Perform operations after enabling primary plane
5354 * @crtc: the CRTC whose primary plane was just enabled
5355 * @new_crtc_state: the enabling state
5356 *
5357 * Performs potentially sleeping operations that must be done after the primary
5358 * plane is enabled, such as updating FBC and IPS. Note that this may be
5359 * called due to an explicit primary plane update, or due to an implicit
5360 * re-enable that is caused when a sprite plane is updated to no longer
5361 * completely hide the primary plane.
5362 */
5363 static void
5364 intel_post_enable_primary(struct drm_crtc *crtc,
5365 const struct intel_crtc_state *new_crtc_state)
5366 {
5367 struct drm_device *dev = crtc->dev;
5368 struct drm_i915_private *dev_priv = to_i915(dev);
5369 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5370 int pipe = intel_crtc->pipe;
5371
5372 /*
5373 * Gen2 reports pipe underruns whenever all planes are disabled.
5374 * So don't enable underrun reporting before at least some planes
5375 * are enabled.
5376 * FIXME: Need to fix the logic to work when we turn off all planes
5377 * but leave the pipe running.
5378 */
5379 if (IS_GEN(dev_priv, 2))
5380 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5381
5382 /* Underruns don't always raise interrupts, so check manually. */
5383 intel_check_cpu_fifo_underruns(dev_priv);
5384 intel_check_pch_fifo_underruns(dev_priv);
5385 }
5386
5387 /* FIXME get rid of this and use pre_plane_update */
5388 static void
5389 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
5390 {
5391 struct drm_device *dev = crtc->dev;
5392 struct drm_i915_private *dev_priv = to_i915(dev);
5393 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5394 int pipe = intel_crtc->pipe;
5395
5396 /*
5397 * Gen2 reports pipe underruns whenever all planes are disabled.
5398 * So disable underrun reporting before all the planes get disabled.
5399 */
5400 if (IS_GEN(dev_priv, 2))
5401 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5402
5403 hsw_disable_ips(to_intel_crtc_state(crtc->state));
5404
5405 /*
5406 * Vblank time updates from the shadow to live plane control register
5407 * are blocked if the memory self-refresh mode is active at that
5408 * moment. So to make sure the plane gets truly disabled, disable
5409 * first the self-refresh mode. The self-refresh enable bit in turn
5410 * will be checked/applied by the HW only at the next frame start
5411 * event which is after the vblank start event, so we need to have a
5412 * wait-for-vblank between disabling the plane and the pipe.
5413 */
5414 if (HAS_GMCH(dev_priv) &&
5415 intel_set_memory_cxsr(dev_priv, false))
5416 intel_wait_for_vblank(dev_priv, pipe);
5417 }
5418
5419 static bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_state,
5420 const struct intel_crtc_state *new_crtc_state)
5421 {
5422 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
5423 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5424
5425 if (!old_crtc_state->ips_enabled)
5426 return false;
5427
5428 if (needs_modeset(&new_crtc_state->base))
5429 return true;
5430
5431 /*
5432 * Workaround : Do not read or write the pipe palette/gamma data while
5433 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
5434 *
5435 * Disable IPS before we program the LUT.
5436 */
5437 if (IS_HASWELL(dev_priv) &&
5438 (new_crtc_state->base.color_mgmt_changed ||
5439 new_crtc_state->update_pipe) &&
5440 new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
5441 return true;
5442
5443 return !new_crtc_state->ips_enabled;
5444 }
5445
5446 static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_state,
5447 const struct intel_crtc_state *new_crtc_state)
5448 {
5449 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
5450 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5451
5452 if (!new_crtc_state->ips_enabled)
5453 return false;
5454
5455 if (needs_modeset(&new_crtc_state->base))
5456 return true;
5457
5458 /*
5459 * Workaround : Do not read or write the pipe palette/gamma data while
5460 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
5461 *
5462 * Re-enable IPS after the LUT has been programmed.
5463 */
5464 if (IS_HASWELL(dev_priv) &&
5465 (new_crtc_state->base.color_mgmt_changed ||
5466 new_crtc_state->update_pipe) &&
5467 new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
5468 return true;
5469
5470 /*
5471 * We can't read out IPS on broadwell, assume the worst and
5472 * forcibly enable IPS on the first fastset.
5473 */
5474 if (new_crtc_state->update_pipe &&
5475 old_crtc_state->base.adjusted_mode.private_flags & I915_MODE_FLAG_INHERITED)
5476 return true;
5477
5478 return !old_crtc_state->ips_enabled;
5479 }
5480
5481 static bool needs_nv12_wa(struct drm_i915_private *dev_priv,
5482 const struct intel_crtc_state *crtc_state)
5483 {
5484 if (!crtc_state->nv12_planes)
5485 return false;
5486
5487 /* WA Display #0827: Gen9:all */
5488 if (IS_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv))
5489 return true;
5490
5491 return false;
5492 }
5493
5494 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
5495 {
5496 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5497 struct drm_device *dev = crtc->base.dev;
5498 struct drm_i915_private *dev_priv = to_i915(dev);
5499 struct drm_atomic_state *old_state = old_crtc_state->base.state;
5500 struct intel_crtc_state *pipe_config =
5501 intel_atomic_get_new_crtc_state(to_intel_atomic_state(old_state),
5502 crtc);
5503 struct drm_plane *primary = crtc->base.primary;
5504 struct drm_plane_state *old_primary_state =
5505 drm_atomic_get_old_plane_state(old_state, primary);
5506
5507 intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
5508
5509 if (pipe_config->update_wm_post && pipe_config->base.active)
5510 intel_update_watermarks(crtc);
5511
5512 if (hsw_post_update_enable_ips(old_crtc_state, pipe_config))
5513 hsw_enable_ips(pipe_config);
5514
5515 if (old_primary_state) {
5516 struct drm_plane_state *new_primary_state =
5517 drm_atomic_get_new_plane_state(old_state, primary);
5518
5519 intel_fbc_post_update(crtc);
5520
5521 if (new_primary_state->visible &&
5522 (needs_modeset(&pipe_config->base) ||
5523 !old_primary_state->visible))
5524 intel_post_enable_primary(&crtc->base, pipe_config);
5525 }
5526
5527 /* Display WA 827 */
5528 if (needs_nv12_wa(dev_priv, old_crtc_state) &&
5529 !needs_nv12_wa(dev_priv, pipe_config)) {
5530 skl_wa_clkgate(dev_priv, crtc->pipe, false);
5531 }
5532 }
5533
5534 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
5535 struct intel_crtc_state *pipe_config)
5536 {
5537 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5538 struct drm_device *dev = crtc->base.dev;
5539 struct drm_i915_private *dev_priv = to_i915(dev);
5540 struct drm_atomic_state *old_state = old_crtc_state->base.state;
5541 struct drm_plane *primary = crtc->base.primary;
5542 struct drm_plane_state *old_primary_state =
5543 drm_atomic_get_old_plane_state(old_state, primary);
5544 bool modeset = needs_modeset(&pipe_config->base);
5545 struct intel_atomic_state *old_intel_state =
5546 to_intel_atomic_state(old_state);
5547
5548 if (hsw_pre_update_disable_ips(old_crtc_state, pipe_config))
5549 hsw_disable_ips(old_crtc_state);
5550
5551 if (old_primary_state) {
5552 struct intel_plane_state *new_primary_state =
5553 intel_atomic_get_new_plane_state(old_intel_state,
5554 to_intel_plane(primary));
5555
5556 intel_fbc_pre_update(crtc, pipe_config, new_primary_state);
5557 /*
5558 * Gen2 reports pipe underruns whenever all planes are disabled.
5559 * So disable underrun reporting before all the planes get disabled.
5560 */
5561 if (IS_GEN(dev_priv, 2) && old_primary_state->visible &&
5562 (modeset || !new_primary_state->base.visible))
5563 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
5564 }
5565
5566 /* Display WA 827 */
5567 if (!needs_nv12_wa(dev_priv, old_crtc_state) &&
5568 needs_nv12_wa(dev_priv, pipe_config)) {
5569 skl_wa_clkgate(dev_priv, crtc->pipe, true);
5570 }
5571
5572 /*
5573 * Vblank time updates from the shadow to live plane control register
5574 * are blocked if the memory self-refresh mode is active at that
5575 * moment. So to make sure the plane gets truly disabled, disable
5576 * first the self-refresh mode. The self-refresh enable bit in turn
5577 * will be checked/applied by the HW only at the next frame start
5578 * event which is after the vblank start event, so we need to have a
5579 * wait-for-vblank between disabling the plane and the pipe.
5580 */
5581 if (HAS_GMCH(dev_priv) && old_crtc_state->base.active &&
5582 pipe_config->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
5583 intel_wait_for_vblank(dev_priv, crtc->pipe);
5584
5585 /*
5586 * IVB workaround: must disable low power watermarks for at least
5587 * one frame before enabling scaling. LP watermarks can be re-enabled
5588 * when scaling is disabled.
5589 *
5590 * WaCxSRDisabledForSpriteScaling:ivb
5591 */
5592 if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev) &&
5593 old_crtc_state->base.active)
5594 intel_wait_for_vblank(dev_priv, crtc->pipe);
5595
5596 /*
5597 * If we're doing a modeset, we're done. No need to do any pre-vblank
5598 * watermark programming here.
5599 */
5600 if (needs_modeset(&pipe_config->base))
5601 return;
5602
5603 /*
5604 * For platforms that support atomic watermarks, program the
5605 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
5606 * will be the intermediate values that are safe for both pre- and
5607 * post- vblank; when vblank happens, the 'active' values will be set
5608 * to the final 'target' values and we'll do this again to get the
5609 * optimal watermarks. For gen9+ platforms, the values we program here
5610 * will be the final target values which will get automatically latched
5611 * at vblank time; no further programming will be necessary.
5612 *
5613 * If a platform hasn't been transitioned to atomic watermarks yet,
5614 * we'll continue to update watermarks the old way, if flags tell
5615 * us to.
5616 */
5617 if (dev_priv->display.initial_watermarks != NULL)
5618 dev_priv->display.initial_watermarks(old_intel_state,
5619 pipe_config);
5620 else if (pipe_config->update_wm_pre)
5621 intel_update_watermarks(crtc);
5622 }
5623
5624 static void intel_crtc_disable_planes(struct intel_atomic_state *state,
5625 struct intel_crtc *crtc)
5626 {
5627 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5628 const struct intel_crtc_state *new_crtc_state =
5629 intel_atomic_get_new_crtc_state(state, crtc);
5630 unsigned int update_mask = new_crtc_state->update_planes;
5631 const struct intel_plane_state *old_plane_state;
5632 struct intel_plane *plane;
5633 unsigned fb_bits = 0;
5634 int i;
5635
5636 intel_crtc_dpms_overlay_disable(crtc);
5637
5638 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
5639 if (crtc->pipe != plane->pipe ||
5640 !(update_mask & BIT(plane->id)))
5641 continue;
5642
5643 intel_disable_plane(plane, new_crtc_state);
5644
5645 if (old_plane_state->base.visible)
5646 fb_bits |= plane->frontbuffer_bit;
5647 }
5648
5649 intel_frontbuffer_flip(dev_priv, fb_bits);
5650 }
5651
5652 static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc,
5653 struct intel_crtc_state *crtc_state,
5654 struct drm_atomic_state *old_state)
5655 {
5656 struct drm_connector_state *conn_state;
5657 struct drm_connector *conn;
5658 int i;
5659
5660 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5661 struct intel_encoder *encoder =
5662 to_intel_encoder(conn_state->best_encoder);
5663
5664 if (conn_state->crtc != crtc)
5665 continue;
5666
5667 if (encoder->pre_pll_enable)
5668 encoder->pre_pll_enable(encoder, crtc_state, conn_state);
5669 }
5670 }
5671
5672 static void intel_encoders_pre_enable(struct drm_crtc *crtc,
5673 struct intel_crtc_state *crtc_state,
5674 struct drm_atomic_state *old_state)
5675 {
5676 struct drm_connector_state *conn_state;
5677 struct drm_connector *conn;
5678 int i;
5679
5680 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5681 struct intel_encoder *encoder =
5682 to_intel_encoder(conn_state->best_encoder);
5683
5684 if (conn_state->crtc != crtc)
5685 continue;
5686
5687 if (encoder->pre_enable)
5688 encoder->pre_enable(encoder, crtc_state, conn_state);
5689 }
5690 }
5691
5692 static void intel_encoders_enable(struct drm_crtc *crtc,
5693 struct intel_crtc_state *crtc_state,
5694 struct drm_atomic_state *old_state)
5695 {
5696 struct drm_connector_state *conn_state;
5697 struct drm_connector *conn;
5698 int i;
5699
5700 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5701 struct intel_encoder *encoder =
5702 to_intel_encoder(conn_state->best_encoder);
5703
5704 if (conn_state->crtc != crtc)
5705 continue;
5706
5707 if (encoder->enable)
5708 encoder->enable(encoder, crtc_state, conn_state);
5709 intel_opregion_notify_encoder(encoder, true);
5710 }
5711 }
5712
5713 static void intel_encoders_disable(struct drm_crtc *crtc,
5714 struct intel_crtc_state *old_crtc_state,
5715 struct drm_atomic_state *old_state)
5716 {
5717 struct drm_connector_state *old_conn_state;
5718 struct drm_connector *conn;
5719 int i;
5720
5721 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5722 struct intel_encoder *encoder =
5723 to_intel_encoder(old_conn_state->best_encoder);
5724
5725 if (old_conn_state->crtc != crtc)
5726 continue;
5727
5728 intel_opregion_notify_encoder(encoder, false);
5729 if (encoder->disable)
5730 encoder->disable(encoder, old_crtc_state, old_conn_state);
5731 }
5732 }
5733
5734 static void intel_encoders_post_disable(struct drm_crtc *crtc,
5735 struct intel_crtc_state *old_crtc_state,
5736 struct drm_atomic_state *old_state)
5737 {
5738 struct drm_connector_state *old_conn_state;
5739 struct drm_connector *conn;
5740 int i;
5741
5742 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5743 struct intel_encoder *encoder =
5744 to_intel_encoder(old_conn_state->best_encoder);
5745
5746 if (old_conn_state->crtc != crtc)
5747 continue;
5748
5749 if (encoder->post_disable)
5750 encoder->post_disable(encoder, old_crtc_state, old_conn_state);
5751 }
5752 }
5753
5754 static void intel_encoders_post_pll_disable(struct drm_crtc *crtc,
5755 struct intel_crtc_state *old_crtc_state,
5756 struct drm_atomic_state *old_state)
5757 {
5758 struct drm_connector_state *old_conn_state;
5759 struct drm_connector *conn;
5760 int i;
5761
5762 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5763 struct intel_encoder *encoder =
5764 to_intel_encoder(old_conn_state->best_encoder);
5765
5766 if (old_conn_state->crtc != crtc)
5767 continue;
5768
5769 if (encoder->post_pll_disable)
5770 encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
5771 }
5772 }
5773
5774 static void intel_encoders_update_pipe(struct drm_crtc *crtc,
5775 struct intel_crtc_state *crtc_state,
5776 struct drm_atomic_state *old_state)
5777 {
5778 struct drm_connector_state *conn_state;
5779 struct drm_connector *conn;
5780 int i;
5781
5782 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5783 struct intel_encoder *encoder =
5784 to_intel_encoder(conn_state->best_encoder);
5785
5786 if (conn_state->crtc != crtc)
5787 continue;
5788
5789 if (encoder->update_pipe)
5790 encoder->update_pipe(encoder, crtc_state, conn_state);
5791 }
5792 }
5793
5794 static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state)
5795 {
5796 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
5797 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
5798
5799 plane->disable_plane(plane, crtc_state);
5800 }
5801
5802 static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
5803 struct drm_atomic_state *old_state)
5804 {
5805 struct drm_crtc *crtc = pipe_config->base.crtc;
5806 struct drm_device *dev = crtc->dev;
5807 struct drm_i915_private *dev_priv = to_i915(dev);
5808 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5809 int pipe = intel_crtc->pipe;
5810 struct intel_atomic_state *old_intel_state =
5811 to_intel_atomic_state(old_state);
5812
5813 if (WARN_ON(intel_crtc->active))
5814 return;
5815
5816 /*
5817 * Sometimes spurious CPU pipe underruns happen during FDI
5818 * training, at least with VGA+HDMI cloning. Suppress them.
5819 *
5820 * On ILK we get an occasional spurious CPU pipe underruns
5821 * between eDP port A enable and vdd enable. Also PCH port
5822 * enable seems to result in the occasional CPU pipe underrun.
5823 *
5824 * Spurious PCH underruns also occur during PCH enabling.
5825 */
5826 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5827 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5828
5829 if (pipe_config->has_pch_encoder)
5830 intel_prepare_shared_dpll(pipe_config);
5831
5832 if (intel_crtc_has_dp_encoder(pipe_config))
5833 intel_dp_set_m_n(pipe_config, M1_N1);
5834
5835 intel_set_pipe_timings(pipe_config);
5836 intel_set_pipe_src_size(pipe_config);
5837
5838 if (pipe_config->has_pch_encoder) {
5839 intel_cpu_transcoder_set_m_n(pipe_config,
5840 &pipe_config->fdi_m_n, NULL);
5841 }
5842
5843 ironlake_set_pipeconf(pipe_config);
5844
5845 intel_crtc->active = true;
5846
5847 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5848
5849 if (pipe_config->has_pch_encoder) {
5850 /* Note: FDI PLL enabling _must_ be done before we enable the
5851 * cpu pipes, hence this is separate from all the other fdi/pch
5852 * enabling. */
5853 ironlake_fdi_pll_enable(pipe_config);
5854 } else {
5855 assert_fdi_tx_disabled(dev_priv, pipe);
5856 assert_fdi_rx_disabled(dev_priv, pipe);
5857 }
5858
5859 ironlake_pfit_enable(pipe_config);
5860
5861 /*
5862 * On ILK+ LUT must be loaded before the pipe is running but with
5863 * clocks enabled
5864 */
5865 intel_color_load_luts(pipe_config);
5866 intel_color_commit(pipe_config);
5867 /* update DSPCNTR to configure gamma for pipe bottom color */
5868 intel_disable_primary_plane(pipe_config);
5869
5870 if (dev_priv->display.initial_watermarks != NULL)
5871 dev_priv->display.initial_watermarks(old_intel_state, pipe_config);
5872 intel_enable_pipe(pipe_config);
5873
5874 if (pipe_config->has_pch_encoder)
5875 ironlake_pch_enable(old_intel_state, pipe_config);
5876
5877 assert_vblank_disabled(crtc);
5878 intel_crtc_vblank_on(pipe_config);
5879
5880 intel_encoders_enable(crtc, pipe_config, old_state);
5881
5882 if (HAS_PCH_CPT(dev_priv))
5883 cpt_verify_modeset(dev, intel_crtc->pipe);
5884
5885 /*
5886 * Must wait for vblank to avoid spurious PCH FIFO underruns.
5887 * And a second vblank wait is needed at least on ILK with
5888 * some interlaced HDMI modes. Let's do the double wait always
5889 * in case there are more corner cases we don't know about.
5890 */
5891 if (pipe_config->has_pch_encoder) {
5892 intel_wait_for_vblank(dev_priv, pipe);
5893 intel_wait_for_vblank(dev_priv, pipe);
5894 }
5895 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5896 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5897 }
5898
5899 /* IPS only exists on ULT machines and is tied to pipe A. */
5900 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
5901 {
5902 return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
5903 }
5904
5905 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv,
5906 enum pipe pipe, bool apply)
5907 {
5908 u32 val = I915_READ(CLKGATE_DIS_PSL(pipe));
5909 u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS;
5910
5911 if (apply)
5912 val |= mask;
5913 else
5914 val &= ~mask;
5915
5916 I915_WRITE(CLKGATE_DIS_PSL(pipe), val);
5917 }
5918
5919 static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
5920 {
5921 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5922 enum pipe pipe = crtc->pipe;
5923 u32 val;
5924
5925 val = MBUS_DBOX_A_CREDIT(2);
5926 val |= MBUS_DBOX_BW_CREDIT(1);
5927 val |= MBUS_DBOX_B_CREDIT(8);
5928
5929 I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val);
5930 }
5931
5932 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
5933 struct drm_atomic_state *old_state)
5934 {
5935 struct drm_crtc *crtc = pipe_config->base.crtc;
5936 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5937 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5938 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
5939 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5940 struct intel_atomic_state *old_intel_state =
5941 to_intel_atomic_state(old_state);
5942 bool psl_clkgate_wa;
5943
5944 if (WARN_ON(intel_crtc->active))
5945 return;
5946
5947 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5948
5949 if (pipe_config->shared_dpll)
5950 intel_enable_shared_dpll(pipe_config);
5951
5952 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5953
5954 if (intel_crtc_has_dp_encoder(pipe_config))
5955 intel_dp_set_m_n(pipe_config, M1_N1);
5956
5957 if (!transcoder_is_dsi(cpu_transcoder))
5958 intel_set_pipe_timings(pipe_config);
5959
5960 intel_set_pipe_src_size(pipe_config);
5961
5962 if (cpu_transcoder != TRANSCODER_EDP &&
5963 !transcoder_is_dsi(cpu_transcoder)) {
5964 I915_WRITE(PIPE_MULT(cpu_transcoder),
5965 pipe_config->pixel_multiplier - 1);
5966 }
5967
5968 if (pipe_config->has_pch_encoder) {
5969 intel_cpu_transcoder_set_m_n(pipe_config,
5970 &pipe_config->fdi_m_n, NULL);
5971 }
5972
5973 if (!transcoder_is_dsi(cpu_transcoder))
5974 haswell_set_pipeconf(pipe_config);
5975
5976 haswell_set_pipemisc(pipe_config);
5977
5978 intel_crtc->active = true;
5979
5980 /* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
5981 psl_clkgate_wa = (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
5982 pipe_config->pch_pfit.enabled;
5983 if (psl_clkgate_wa)
5984 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
5985
5986 if (INTEL_GEN(dev_priv) >= 9)
5987 skylake_pfit_enable(pipe_config);
5988 else
5989 ironlake_pfit_enable(pipe_config);
5990
5991 /*
5992 * On ILK+ LUT must be loaded before the pipe is running but with
5993 * clocks enabled
5994 */
5995 intel_color_load_luts(pipe_config);
5996 intel_color_commit(pipe_config);
5997 /* update DSPCNTR to configure gamma/csc for pipe bottom color */
5998 if (INTEL_GEN(dev_priv) < 9)
5999 intel_disable_primary_plane(pipe_config);
6000
6001 if (INTEL_GEN(dev_priv) >= 11)
6002 icl_set_pipe_chicken(intel_crtc);
6003
6004 intel_ddi_set_pipe_settings(pipe_config);
6005 if (!transcoder_is_dsi(cpu_transcoder))
6006 intel_ddi_enable_transcoder_func(pipe_config);
6007
6008 if (dev_priv->display.initial_watermarks != NULL)
6009 dev_priv->display.initial_watermarks(old_intel_state, pipe_config);
6010
6011 if (INTEL_GEN(dev_priv) >= 11)
6012 icl_pipe_mbus_enable(intel_crtc);
6013
6014 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
6015 if (!transcoder_is_dsi(cpu_transcoder))
6016 intel_enable_pipe(pipe_config);
6017
6018 if (pipe_config->has_pch_encoder)
6019 lpt_pch_enable(old_intel_state, pipe_config);
6020
6021 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST))
6022 intel_ddi_set_vc_payload_alloc(pipe_config, true);
6023
6024 assert_vblank_disabled(crtc);
6025 intel_crtc_vblank_on(pipe_config);
6026
6027 intel_encoders_enable(crtc, pipe_config, old_state);
6028
6029 if (psl_clkgate_wa) {
6030 intel_wait_for_vblank(dev_priv, pipe);
6031 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false);
6032 }
6033
6034 /* If we change the relative order between pipe/planes enabling, we need
6035 * to change the workaround. */
6036 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
6037 if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
6038 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
6039 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
6040 }
6041 }
6042
6043 static void ironlake_pfit_disable(const struct intel_crtc_state *old_crtc_state)
6044 {
6045 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
6046 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6047 enum pipe pipe = crtc->pipe;
6048
6049 /* To avoid upsetting the power well on haswell only disable the pfit if
6050 * it's in use. The hw state code will make sure we get this right. */
6051 if (old_crtc_state->pch_pfit.enabled) {
6052 I915_WRITE(PF_CTL(pipe), 0);
6053 I915_WRITE(PF_WIN_POS(pipe), 0);
6054 I915_WRITE(PF_WIN_SZ(pipe), 0);
6055 }
6056 }
6057
6058 static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
6059 struct drm_atomic_state *old_state)
6060 {
6061 struct drm_crtc *crtc = old_crtc_state->base.crtc;
6062 struct drm_device *dev = crtc->dev;
6063 struct drm_i915_private *dev_priv = to_i915(dev);
6064 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6065 int pipe = intel_crtc->pipe;
6066
6067 /*
6068 * Sometimes spurious CPU pipe underruns happen when the
6069 * pipe is already disabled, but FDI RX/TX is still enabled.
6070 * Happens at least with VGA+HDMI cloning. Suppress them.
6071 */
6072 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6073 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
6074
6075 intel_encoders_disable(crtc, old_crtc_state, old_state);
6076
6077 drm_crtc_vblank_off(crtc);
6078 assert_vblank_disabled(crtc);
6079
6080 intel_disable_pipe(old_crtc_state);
6081
6082 ironlake_pfit_disable(old_crtc_state);
6083
6084 if (old_crtc_state->has_pch_encoder)
6085 ironlake_fdi_disable(crtc);
6086
6087 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
6088
6089 if (old_crtc_state->has_pch_encoder) {
6090 ironlake_disable_pch_transcoder(dev_priv, pipe);
6091
6092 if (HAS_PCH_CPT(dev_priv)) {
6093 i915_reg_t reg;
6094 u32 temp;
6095
6096 /* disable TRANS_DP_CTL */
6097 reg = TRANS_DP_CTL(pipe);
6098 temp = I915_READ(reg);
6099 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
6100 TRANS_DP_PORT_SEL_MASK);
6101 temp |= TRANS_DP_PORT_SEL_NONE;
6102 I915_WRITE(reg, temp);
6103
6104 /* disable DPLL_SEL */
6105 temp = I915_READ(PCH_DPLL_SEL);
6106 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
6107 I915_WRITE(PCH_DPLL_SEL, temp);
6108 }
6109
6110 ironlake_fdi_pll_disable(intel_crtc);
6111 }
6112
6113 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6114 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
6115 }
6116
6117 static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
6118 struct drm_atomic_state *old_state)
6119 {
6120 struct drm_crtc *crtc = old_crtc_state->base.crtc;
6121 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6122 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6123 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
6124
6125 intel_encoders_disable(crtc, old_crtc_state, old_state);
6126
6127 drm_crtc_vblank_off(crtc);
6128 assert_vblank_disabled(crtc);
6129
6130 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
6131 if (!transcoder_is_dsi(cpu_transcoder))
6132 intel_disable_pipe(old_crtc_state);
6133
6134 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST))
6135 intel_ddi_set_vc_payload_alloc(old_crtc_state, false);
6136
6137 if (!transcoder_is_dsi(cpu_transcoder))
6138 intel_ddi_disable_transcoder_func(old_crtc_state);
6139
6140 intel_dsc_disable(old_crtc_state);
6141
6142 if (INTEL_GEN(dev_priv) >= 9)
6143 skylake_scaler_disable(intel_crtc);
6144 else
6145 ironlake_pfit_disable(old_crtc_state);
6146
6147 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
6148
6149 intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
6150 }
6151
6152 static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
6153 {
6154 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
6155 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6156
6157 if (!crtc_state->gmch_pfit.control)
6158 return;
6159
6160 /*
6161 * The panel fitter should only be adjusted whilst the pipe is disabled,
6162 * according to register description and PRM.
6163 */
6164 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
6165 assert_pipe_disabled(dev_priv, crtc->pipe);
6166
6167 I915_WRITE(PFIT_PGM_RATIOS, crtc_state->gmch_pfit.pgm_ratios);
6168 I915_WRITE(PFIT_CONTROL, crtc_state->gmch_pfit.control);
6169
6170 /* Border color in case we don't scale up to the full screen. Black by
6171 * default, change to something else for debugging. */
6172 I915_WRITE(BCLRPAT(crtc->pipe), 0);
6173 }
6174
6175 bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port)
6176 {
6177 if (port == PORT_NONE)
6178 return false;
6179
6180 if (IS_ELKHARTLAKE(dev_priv))
6181 return port <= PORT_C;
6182
6183 if (INTEL_GEN(dev_priv) >= 11)
6184 return port <= PORT_B;
6185
6186 return false;
6187 }
6188
6189 bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port)
6190 {
6191 if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
6192 return port >= PORT_C && port <= PORT_F;
6193
6194 return false;
6195 }
6196
6197 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
6198 {
6199 if (!intel_port_is_tc(dev_priv, port))
6200 return PORT_TC_NONE;
6201
6202 return port - PORT_C;
6203 }
6204
6205 enum intel_display_power_domain intel_port_to_power_domain(enum port port)
6206 {
6207 switch (port) {
6208 case PORT_A:
6209 return POWER_DOMAIN_PORT_DDI_A_LANES;
6210 case PORT_B:
6211 return POWER_DOMAIN_PORT_DDI_B_LANES;
6212 case PORT_C:
6213 return POWER_DOMAIN_PORT_DDI_C_LANES;
6214 case PORT_D:
6215 return POWER_DOMAIN_PORT_DDI_D_LANES;
6216 case PORT_E:
6217 return POWER_DOMAIN_PORT_DDI_E_LANES;
6218 case PORT_F:
6219 return POWER_DOMAIN_PORT_DDI_F_LANES;
6220 default:
6221 MISSING_CASE(port);
6222 return POWER_DOMAIN_PORT_OTHER;
6223 }
6224 }
6225
6226 enum intel_display_power_domain
6227 intel_aux_power_domain(struct intel_digital_port *dig_port)
6228 {
6229 switch (dig_port->aux_ch) {
6230 case AUX_CH_A:
6231 return POWER_DOMAIN_AUX_A;
6232 case AUX_CH_B:
6233 return POWER_DOMAIN_AUX_B;
6234 case AUX_CH_C:
6235 return POWER_DOMAIN_AUX_C;
6236 case AUX_CH_D:
6237 return POWER_DOMAIN_AUX_D;
6238 case AUX_CH_E:
6239 return POWER_DOMAIN_AUX_E;
6240 case AUX_CH_F:
6241 return POWER_DOMAIN_AUX_F;
6242 default:
6243 MISSING_CASE(dig_port->aux_ch);
6244 return POWER_DOMAIN_AUX_A;
6245 }
6246 }
6247
6248 static u64 get_crtc_power_domains(struct drm_crtc *crtc,
6249 struct intel_crtc_state *crtc_state)
6250 {
6251 struct drm_device *dev = crtc->dev;
6252 struct drm_i915_private *dev_priv = to_i915(dev);
6253 struct drm_encoder *encoder;
6254 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6255 enum pipe pipe = intel_crtc->pipe;
6256 u64 mask;
6257 enum transcoder transcoder = crtc_state->cpu_transcoder;
6258
6259 if (!crtc_state->base.active)
6260 return 0;
6261
6262 mask = BIT_ULL(POWER_DOMAIN_PIPE(pipe));
6263 mask |= BIT_ULL(POWER_DOMAIN_TRANSCODER(transcoder));
6264 if (crtc_state->pch_pfit.enabled ||
6265 crtc_state->pch_pfit.force_thru)
6266 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
6267
6268 drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
6269 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6270
6271 mask |= BIT_ULL(intel_encoder->power_domain);
6272 }
6273
6274 if (HAS_DDI(dev_priv) && crtc_state->has_audio)
6275 mask |= BIT_ULL(POWER_DOMAIN_AUDIO);
6276
6277 if (crtc_state->shared_dpll)
6278 mask |= BIT_ULL(POWER_DOMAIN_PLLS);
6279
6280 return mask;
6281 }
6282
6283 static u64
6284 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
6285 struct intel_crtc_state *crtc_state)
6286 {
6287 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6288 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6289 enum intel_display_power_domain domain;
6290 u64 domains, new_domains, old_domains;
6291
6292 old_domains = intel_crtc->enabled_power_domains;
6293 intel_crtc->enabled_power_domains = new_domains =
6294 get_crtc_power_domains(crtc, crtc_state);
6295
6296 domains = new_domains & ~old_domains;
6297
6298 for_each_power_domain(domain, domains)
6299 intel_display_power_get(dev_priv, domain);
6300
6301 return old_domains & ~new_domains;
6302 }
6303
6304 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
6305 u64 domains)
6306 {
6307 enum intel_display_power_domain domain;
6308
6309 for_each_power_domain(domain, domains)
6310 intel_display_power_put_unchecked(dev_priv, domain);
6311 }
6312
6313 static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
6314 struct drm_atomic_state *old_state)
6315 {
6316 struct intel_atomic_state *old_intel_state =
6317 to_intel_atomic_state(old_state);
6318 struct drm_crtc *crtc = pipe_config->base.crtc;
6319 struct drm_device *dev = crtc->dev;
6320 struct drm_i915_private *dev_priv = to_i915(dev);
6321 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6322 int pipe = intel_crtc->pipe;
6323
6324 if (WARN_ON(intel_crtc->active))
6325 return;
6326
6327 if (intel_crtc_has_dp_encoder(pipe_config))
6328 intel_dp_set_m_n(pipe_config, M1_N1);
6329
6330 intel_set_pipe_timings(pipe_config);
6331 intel_set_pipe_src_size(pipe_config);
6332
6333 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
6334 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6335 I915_WRITE(CHV_CANVAS(pipe), 0);
6336 }
6337
6338 i9xx_set_pipeconf(pipe_config);
6339
6340 intel_crtc->active = true;
6341
6342 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6343
6344 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
6345
6346 if (IS_CHERRYVIEW(dev_priv)) {
6347 chv_prepare_pll(intel_crtc, pipe_config);
6348 chv_enable_pll(intel_crtc, pipe_config);
6349 } else {
6350 vlv_prepare_pll(intel_crtc, pipe_config);
6351 vlv_enable_pll(intel_crtc, pipe_config);
6352 }
6353
6354 intel_encoders_pre_enable(crtc, pipe_config, old_state);
6355
6356 i9xx_pfit_enable(pipe_config);
6357
6358 intel_color_load_luts(pipe_config);
6359 intel_color_commit(pipe_config);
6360 /* update DSPCNTR to configure gamma for pipe bottom color */
6361 intel_disable_primary_plane(pipe_config);
6362
6363 dev_priv->display.initial_watermarks(old_intel_state,
6364 pipe_config);
6365 intel_enable_pipe(pipe_config);
6366
6367 assert_vblank_disabled(crtc);
6368 intel_crtc_vblank_on(pipe_config);
6369
6370 intel_encoders_enable(crtc, pipe_config, old_state);
6371 }
6372
6373 static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
6374 {
6375 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
6376 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6377
6378 I915_WRITE(FP0(crtc->pipe), crtc_state->dpll_hw_state.fp0);
6379 I915_WRITE(FP1(crtc->pipe), crtc_state->dpll_hw_state.fp1);
6380 }
6381
6382 static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
6383 struct drm_atomic_state *old_state)
6384 {
6385 struct intel_atomic_state *old_intel_state =
6386 to_intel_atomic_state(old_state);
6387 struct drm_crtc *crtc = pipe_config->base.crtc;
6388 struct drm_device *dev = crtc->dev;
6389 struct drm_i915_private *dev_priv = to_i915(dev);
6390 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6391 enum pipe pipe = intel_crtc->pipe;
6392
6393 if (WARN_ON(intel_crtc->active))
6394 return;
6395
6396 i9xx_set_pll_dividers(pipe_config);
6397
6398 if (intel_crtc_has_dp_encoder(pipe_config))
6399 intel_dp_set_m_n(pipe_config, M1_N1);
6400
6401 intel_set_pipe_timings(pipe_config);
6402 intel_set_pipe_src_size(pipe_config);
6403
6404 i9xx_set_pipeconf(pipe_config);
6405
6406 intel_crtc->active = true;
6407
6408 if (!IS_GEN(dev_priv, 2))
6409 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6410
6411 intel_encoders_pre_enable(crtc, pipe_config, old_state);
6412
6413 i9xx_enable_pll(intel_crtc, pipe_config);
6414
6415 i9xx_pfit_enable(pipe_config);
6416
6417 intel_color_load_luts(pipe_config);
6418 intel_color_commit(pipe_config);
6419 /* update DSPCNTR to configure gamma for pipe bottom color */
6420 intel_disable_primary_plane(pipe_config);
6421
6422 if (dev_priv->display.initial_watermarks != NULL)
6423 dev_priv->display.initial_watermarks(old_intel_state,
6424 pipe_config);
6425 else
6426 intel_update_watermarks(intel_crtc);
6427 intel_enable_pipe(pipe_config);
6428
6429 assert_vblank_disabled(crtc);
6430 intel_crtc_vblank_on(pipe_config);
6431
6432 intel_encoders_enable(crtc, pipe_config, old_state);
6433 }
6434
6435 static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
6436 {
6437 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
6438 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6439
6440 if (!old_crtc_state->gmch_pfit.control)
6441 return;
6442
6443 assert_pipe_disabled(dev_priv, crtc->pipe);
6444
6445 DRM_DEBUG_KMS("disabling pfit, current: 0x%08x\n",
6446 I915_READ(PFIT_CONTROL));
6447 I915_WRITE(PFIT_CONTROL, 0);
6448 }
6449
6450 static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
6451 struct drm_atomic_state *old_state)
6452 {
6453 struct drm_crtc *crtc = old_crtc_state->base.crtc;
6454 struct drm_device *dev = crtc->dev;
6455 struct drm_i915_private *dev_priv = to_i915(dev);
6456 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6457 int pipe = intel_crtc->pipe;
6458
6459 /*
6460 * On gen2 planes are double buffered but the pipe isn't, so we must
6461 * wait for planes to fully turn off before disabling the pipe.
6462 */
6463 if (IS_GEN(dev_priv, 2))
6464 intel_wait_for_vblank(dev_priv, pipe);
6465
6466 intel_encoders_disable(crtc, old_crtc_state, old_state);
6467
6468 drm_crtc_vblank_off(crtc);
6469 assert_vblank_disabled(crtc);
6470
6471 intel_disable_pipe(old_crtc_state);
6472
6473 i9xx_pfit_disable(old_crtc_state);
6474
6475 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
6476
6477 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) {
6478 if (IS_CHERRYVIEW(dev_priv))
6479 chv_disable_pll(dev_priv, pipe);
6480 else if (IS_VALLEYVIEW(dev_priv))
6481 vlv_disable_pll(dev_priv, pipe);
6482 else
6483 i9xx_disable_pll(old_crtc_state);
6484 }
6485
6486 intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
6487
6488 if (!IS_GEN(dev_priv, 2))
6489 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6490
6491 if (!dev_priv->display.initial_watermarks)
6492 intel_update_watermarks(intel_crtc);
6493
6494 /* clock the pipe down to 640x480@60 to potentially save power */
6495 if (IS_I830(dev_priv))
6496 i830_enable_pipe(dev_priv, pipe);
6497 }
6498
6499 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc,
6500 struct drm_modeset_acquire_ctx *ctx)
6501 {
6502 struct intel_encoder *encoder;
6503 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6504 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6505 enum intel_display_power_domain domain;
6506 struct intel_plane *plane;
6507 u64 domains;
6508 struct drm_atomic_state *state;
6509 struct intel_crtc_state *crtc_state;
6510 int ret;
6511
6512 if (!intel_crtc->active)
6513 return;
6514
6515 for_each_intel_plane_on_crtc(&dev_priv->drm, intel_crtc, plane) {
6516 const struct intel_plane_state *plane_state =
6517 to_intel_plane_state(plane->base.state);
6518
6519 if (plane_state->base.visible)
6520 intel_plane_disable_noatomic(intel_crtc, plane);
6521 }
6522
6523 state = drm_atomic_state_alloc(crtc->dev);
6524 if (!state) {
6525 DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory",
6526 crtc->base.id, crtc->name);
6527 return;
6528 }
6529
6530 state->acquire_ctx = ctx;
6531
6532 /* Everything's already locked, -EDEADLK can't happen. */
6533 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
6534 ret = drm_atomic_add_affected_connectors(state, crtc);
6535
6536 WARN_ON(IS_ERR(crtc_state) || ret);
6537
6538 dev_priv->display.crtc_disable(crtc_state, state);
6539
6540 drm_atomic_state_put(state);
6541
6542 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
6543 crtc->base.id, crtc->name);
6544
6545 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
6546 crtc->state->active = false;
6547 intel_crtc->active = false;
6548 crtc->enabled = false;
6549 crtc->state->connector_mask = 0;
6550 crtc->state->encoder_mask = 0;
6551
6552 for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
6553 encoder->base.crtc = NULL;
6554
6555 intel_fbc_disable(intel_crtc);
6556 intel_update_watermarks(intel_crtc);
6557 intel_disable_shared_dpll(to_intel_crtc_state(crtc->state));
6558
6559 domains = intel_crtc->enabled_power_domains;
6560 for_each_power_domain(domain, domains)
6561 intel_display_power_put_unchecked(dev_priv, domain);
6562 intel_crtc->enabled_power_domains = 0;
6563
6564 dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6565 dev_priv->min_cdclk[intel_crtc->pipe] = 0;
6566 dev_priv->min_voltage_level[intel_crtc->pipe] = 0;
6567 }
6568
6569 /*
6570 * turn all crtc's off, but do not adjust state
6571 * This has to be paired with a call to intel_modeset_setup_hw_state.
6572 */
6573 int intel_display_suspend(struct drm_device *dev)
6574 {
6575 struct drm_i915_private *dev_priv = to_i915(dev);
6576 struct drm_atomic_state *state;
6577 int ret;
6578
6579 state = drm_atomic_helper_suspend(dev);
6580 ret = PTR_ERR_OR_ZERO(state);
6581 if (ret)
6582 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6583 else
6584 dev_priv->modeset_restore_state = state;
6585 return ret;
6586 }
6587
6588 void intel_encoder_destroy(struct drm_encoder *encoder)
6589 {
6590 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6591
6592 drm_encoder_cleanup(encoder);
6593 kfree(intel_encoder);
6594 }
6595
6596 /* Cross check the actual hw state with our own modeset state tracking (and it's
6597 * internal consistency). */
6598 static void intel_connector_verify_state(struct drm_crtc_state *crtc_state,
6599 struct drm_connector_state *conn_state)
6600 {
6601 struct intel_connector *connector = to_intel_connector(conn_state->connector);
6602
6603 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6604 connector->base.base.id,
6605 connector->base.name);
6606
6607 if (connector->get_hw_state(connector)) {
6608 struct intel_encoder *encoder = connector->encoder;
6609
6610 I915_STATE_WARN(!crtc_state,
6611 "connector enabled without attached crtc\n");
6612
6613 if (!crtc_state)
6614 return;
6615
6616 I915_STATE_WARN(!crtc_state->active,
6617 "connector is active, but attached crtc isn't\n");
6618
6619 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6620 return;
6621
6622 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6623 "atomic encoder doesn't match attached encoder\n");
6624
6625 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6626 "attached encoder crtc differs from connector crtc\n");
6627 } else {
6628 I915_STATE_WARN(crtc_state && crtc_state->active,
6629 "attached crtc is active, but connector isn't\n");
6630 I915_STATE_WARN(!crtc_state && conn_state->best_encoder,
6631 "best encoder set without crtc!\n");
6632 }
6633 }
6634
6635 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6636 {
6637 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6638 return crtc_state->fdi_lanes;
6639
6640 return 0;
6641 }
6642
6643 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6644 struct intel_crtc_state *pipe_config)
6645 {
6646 struct drm_i915_private *dev_priv = to_i915(dev);
6647 struct drm_atomic_state *state = pipe_config->base.state;
6648 struct intel_crtc *other_crtc;
6649 struct intel_crtc_state *other_crtc_state;
6650
6651 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6652 pipe_name(pipe), pipe_config->fdi_lanes);
6653 if (pipe_config->fdi_lanes > 4) {
6654 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6655 pipe_name(pipe), pipe_config->fdi_lanes);
6656 return -EINVAL;
6657 }
6658
6659 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
6660 if (pipe_config->fdi_lanes > 2) {
6661 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6662 pipe_config->fdi_lanes);
6663 return -EINVAL;
6664 } else {
6665 return 0;
6666 }
6667 }
6668
6669 if (INTEL_INFO(dev_priv)->num_pipes == 2)
6670 return 0;
6671
6672 /* Ivybridge 3 pipe is really complicated */
6673 switch (pipe) {
6674 case PIPE_A:
6675 return 0;
6676 case PIPE_B:
6677 if (pipe_config->fdi_lanes <= 2)
6678 return 0;
6679
6680 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
6681 other_crtc_state =
6682 intel_atomic_get_crtc_state(state, other_crtc);
6683 if (IS_ERR(other_crtc_state))
6684 return PTR_ERR(other_crtc_state);
6685
6686 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6687 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6688 pipe_name(pipe), pipe_config->fdi_lanes);
6689 return -EINVAL;
6690 }
6691 return 0;
6692 case PIPE_C:
6693 if (pipe_config->fdi_lanes > 2) {
6694 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6695 pipe_name(pipe), pipe_config->fdi_lanes);
6696 return -EINVAL;
6697 }
6698
6699 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
6700 other_crtc_state =
6701 intel_atomic_get_crtc_state(state, other_crtc);
6702 if (IS_ERR(other_crtc_state))
6703 return PTR_ERR(other_crtc_state);
6704
6705 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6706 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6707 return -EINVAL;
6708 }
6709 return 0;
6710 default:
6711 BUG();
6712 }
6713 }
6714
6715 #define RETRY 1
6716 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6717 struct intel_crtc_state *pipe_config)
6718 {
6719 struct drm_device *dev = intel_crtc->base.dev;
6720 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6721 int lane, link_bw, fdi_dotclock, ret;
6722 bool needs_recompute = false;
6723
6724 retry:
6725 /* FDI is a binary signal running at ~2.7GHz, encoding
6726 * each output octet as 10 bits. The actual frequency
6727 * is stored as a divider into a 100MHz clock, and the
6728 * mode pixel clock is stored in units of 1KHz.
6729 * Hence the bw of each lane in terms of the mode signal
6730 * is:
6731 */
6732 link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6733
6734 fdi_dotclock = adjusted_mode->crtc_clock;
6735
6736 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6737 pipe_config->pipe_bpp);
6738
6739 pipe_config->fdi_lanes = lane;
6740
6741 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6742 link_bw, &pipe_config->fdi_m_n, false);
6743
6744 ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6745 if (ret == -EDEADLK)
6746 return ret;
6747
6748 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6749 pipe_config->pipe_bpp -= 2*3;
6750 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6751 pipe_config->pipe_bpp);
6752 needs_recompute = true;
6753 pipe_config->bw_constrained = true;
6754
6755 goto retry;
6756 }
6757
6758 if (needs_recompute)
6759 return RETRY;
6760
6761 return ret;
6762 }
6763
6764 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
6765 {
6766 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
6767 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6768
6769 /* IPS only exists on ULT machines and is tied to pipe A. */
6770 if (!hsw_crtc_supports_ips(crtc))
6771 return false;
6772
6773 if (!i915_modparams.enable_ips)
6774 return false;
6775
6776 if (crtc_state->pipe_bpp > 24)
6777 return false;
6778
6779 /*
6780 * We compare against max which means we must take
6781 * the increased cdclk requirement into account when
6782 * calculating the new cdclk.
6783 *
6784 * Should measure whether using a lower cdclk w/o IPS
6785 */
6786 if (IS_BROADWELL(dev_priv) &&
6787 crtc_state->pixel_rate > dev_priv->max_cdclk_freq * 95 / 100)
6788 return false;
6789
6790 return true;
6791 }
6792
6793 static bool hsw_compute_ips_config(struct intel_crtc_state *crtc_state)
6794 {
6795 struct drm_i915_private *dev_priv =
6796 to_i915(crtc_state->base.crtc->dev);
6797 struct intel_atomic_state *intel_state =
6798 to_intel_atomic_state(crtc_state->base.state);
6799
6800 if (!hsw_crtc_state_ips_capable(crtc_state))
6801 return false;
6802
6803 /*
6804 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
6805 * enabled and disabled dynamically based on package C states,
6806 * user space can't make reliable use of the CRCs, so let's just
6807 * completely disable it.
6808 */
6809 if (crtc_state->crc_enabled)
6810 return false;
6811
6812 /* IPS should be fine as long as at least one plane is enabled. */
6813 if (!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)))
6814 return false;
6815
6816 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
6817 if (IS_BROADWELL(dev_priv) &&
6818 crtc_state->pixel_rate > intel_state->cdclk.logical.cdclk * 95 / 100)
6819 return false;
6820
6821 return true;
6822 }
6823
6824 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6825 {
6826 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6827
6828 /* GDG double wide on either pipe, otherwise pipe A only */
6829 return INTEL_GEN(dev_priv) < 4 &&
6830 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6831 }
6832
6833 static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
6834 {
6835 u32 pixel_rate;
6836
6837 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
6838
6839 /*
6840 * We only use IF-ID interlacing. If we ever use
6841 * PF-ID we'll need to adjust the pixel_rate here.
6842 */
6843
6844 if (pipe_config->pch_pfit.enabled) {
6845 u64 pipe_w, pipe_h, pfit_w, pfit_h;
6846 u32 pfit_size = pipe_config->pch_pfit.size;
6847
6848 pipe_w = pipe_config->pipe_src_w;
6849 pipe_h = pipe_config->pipe_src_h;
6850
6851 pfit_w = (pfit_size >> 16) & 0xFFFF;
6852 pfit_h = pfit_size & 0xFFFF;
6853 if (pipe_w < pfit_w)
6854 pipe_w = pfit_w;
6855 if (pipe_h < pfit_h)
6856 pipe_h = pfit_h;
6857
6858 if (WARN_ON(!pfit_w || !pfit_h))
6859 return pixel_rate;
6860
6861 pixel_rate = div_u64((u64)pixel_rate * pipe_w * pipe_h,
6862 pfit_w * pfit_h);
6863 }
6864
6865 return pixel_rate;
6866 }
6867
6868 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
6869 {
6870 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
6871
6872 if (HAS_GMCH(dev_priv))
6873 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
6874 crtc_state->pixel_rate =
6875 crtc_state->base.adjusted_mode.crtc_clock;
6876 else
6877 crtc_state->pixel_rate =
6878 ilk_pipe_pixel_rate(crtc_state);
6879 }
6880
6881 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6882 struct intel_crtc_state *pipe_config)
6883 {
6884 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6885 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6886 int clock_limit = dev_priv->max_dotclk_freq;
6887
6888 if (INTEL_GEN(dev_priv) < 4) {
6889 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6890
6891 /*
6892 * Enable double wide mode when the dot clock
6893 * is > 90% of the (display) core speed.
6894 */
6895 if (intel_crtc_supports_double_wide(crtc) &&
6896 adjusted_mode->crtc_clock > clock_limit) {
6897 clock_limit = dev_priv->max_dotclk_freq;
6898 pipe_config->double_wide = true;
6899 }
6900 }
6901
6902 if (adjusted_mode->crtc_clock > clock_limit) {
6903 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6904 adjusted_mode->crtc_clock, clock_limit,
6905 yesno(pipe_config->double_wide));
6906 return -EINVAL;
6907 }
6908
6909 if ((pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
6910 pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) &&
6911 pipe_config->base.ctm) {
6912 /*
6913 * There is only one pipe CSC unit per pipe, and we need that
6914 * for output conversion from RGB->YCBCR. So if CTM is already
6915 * applied we can't support YCBCR420 output.
6916 */
6917 DRM_DEBUG_KMS("YCBCR420 and CTM together are not possible\n");
6918 return -EINVAL;
6919 }
6920
6921 /*
6922 * Pipe horizontal size must be even in:
6923 * - DVO ganged mode
6924 * - LVDS dual channel mode
6925 * - Double wide pipe
6926 */
6927 if (pipe_config->pipe_src_w & 1) {
6928 if (pipe_config->double_wide) {
6929 DRM_DEBUG_KMS("Odd pipe source width not supported with double wide pipe\n");
6930 return -EINVAL;
6931 }
6932
6933 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6934 intel_is_dual_link_lvds(dev_priv)) {
6935 DRM_DEBUG_KMS("Odd pipe source width not supported with dual link LVDS\n");
6936 return -EINVAL;
6937 }
6938 }
6939
6940 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6941 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6942 */
6943 if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
6944 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6945 return -EINVAL;
6946
6947 intel_crtc_compute_pixel_rate(pipe_config);
6948
6949 if (pipe_config->has_pch_encoder)
6950 return ironlake_fdi_compute_config(crtc, pipe_config);
6951
6952 return 0;
6953 }
6954
6955 static void
6956 intel_reduce_m_n_ratio(u32 *num, u32 *den)
6957 {
6958 while (*num > DATA_LINK_M_N_MASK ||
6959 *den > DATA_LINK_M_N_MASK) {
6960 *num >>= 1;
6961 *den >>= 1;
6962 }
6963 }
6964
6965 static void compute_m_n(unsigned int m, unsigned int n,
6966 u32 *ret_m, u32 *ret_n,
6967 bool constant_n)
6968 {
6969 /*
6970 * Several DP dongles in particular seem to be fussy about
6971 * too large link M/N values. Give N value as 0x8000 that
6972 * should be acceptable by specific devices. 0x8000 is the
6973 * specified fixed N value for asynchronous clock mode,
6974 * which the devices expect also in synchronous clock mode.
6975 */
6976 if (constant_n)
6977 *ret_n = 0x8000;
6978 else
6979 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6980
6981 *ret_m = div_u64((u64)m * *ret_n, n);
6982 intel_reduce_m_n_ratio(ret_m, ret_n);
6983 }
6984
6985 void
6986 intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
6987 int pixel_clock, int link_clock,
6988 struct intel_link_m_n *m_n,
6989 bool constant_n)
6990 {
6991 m_n->tu = 64;
6992
6993 compute_m_n(bits_per_pixel * pixel_clock,
6994 link_clock * nlanes * 8,
6995 &m_n->gmch_m, &m_n->gmch_n,
6996 constant_n);
6997
6998 compute_m_n(pixel_clock, link_clock,
6999 &m_n->link_m, &m_n->link_n,
7000 constant_n);
7001 }
7002
7003 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7004 {
7005 if (i915_modparams.panel_use_ssc >= 0)
7006 return i915_modparams.panel_use_ssc != 0;
7007 return dev_priv->vbt.lvds_use_ssc
7008 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7009 }
7010
7011 static u32 pnv_dpll_compute_fp(struct dpll *dpll)
7012 {
7013 return (1 << dpll->n) << 16 | dpll->m2;
7014 }
7015
7016 static u32 i9xx_dpll_compute_fp(struct dpll *dpll)
7017 {
7018 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7019 }
7020
7021 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7022 struct intel_crtc_state *crtc_state,
7023 struct dpll *reduced_clock)
7024 {
7025 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7026 u32 fp, fp2 = 0;
7027
7028 if (IS_PINEVIEW(dev_priv)) {
7029 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7030 if (reduced_clock)
7031 fp2 = pnv_dpll_compute_fp(reduced_clock);
7032 } else {
7033 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7034 if (reduced_clock)
7035 fp2 = i9xx_dpll_compute_fp(reduced_clock);
7036 }
7037
7038 crtc_state->dpll_hw_state.fp0 = fp;
7039
7040 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7041 reduced_clock) {
7042 crtc_state->dpll_hw_state.fp1 = fp2;
7043 } else {
7044 crtc_state->dpll_hw_state.fp1 = fp;
7045 }
7046 }
7047
7048 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7049 pipe)
7050 {
7051 u32 reg_val;
7052
7053 /*
7054 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7055 * and set it to a reasonable value instead.
7056 */
7057 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7058 reg_val &= 0xffffff00;
7059 reg_val |= 0x00000030;
7060 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7061
7062 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7063 reg_val &= 0x00ffffff;
7064 reg_val |= 0x8c000000;
7065 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7066
7067 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7068 reg_val &= 0xffffff00;
7069 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7070
7071 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7072 reg_val &= 0x00ffffff;
7073 reg_val |= 0xb0000000;
7074 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7075 }
7076
7077 static void intel_pch_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
7078 const struct intel_link_m_n *m_n)
7079 {
7080 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
7081 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7082 enum pipe pipe = crtc->pipe;
7083
7084 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7085 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7086 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7087 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7088 }
7089
7090 static bool transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
7091 enum transcoder transcoder)
7092 {
7093 if (IS_HASWELL(dev_priv))
7094 return transcoder == TRANSCODER_EDP;
7095
7096 /*
7097 * Strictly speaking some registers are available before
7098 * gen7, but we only support DRRS on gen7+
7099 */
7100 return IS_GEN(dev_priv, 7) || IS_CHERRYVIEW(dev_priv);
7101 }
7102
7103 static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
7104 const struct intel_link_m_n *m_n,
7105 const struct intel_link_m_n *m2_n2)
7106 {
7107 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
7108 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7109 enum pipe pipe = crtc->pipe;
7110 enum transcoder transcoder = crtc_state->cpu_transcoder;
7111
7112 if (INTEL_GEN(dev_priv) >= 5) {
7113 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7114 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7115 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7116 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7117 /*
7118 * M2_N2 registers are set only if DRRS is supported
7119 * (to make sure the registers are not unnecessarily accessed).
7120 */
7121 if (m2_n2 && crtc_state->has_drrs &&
7122 transcoder_has_m2_n2(dev_priv, transcoder)) {
7123 I915_WRITE(PIPE_DATA_M2(transcoder),
7124 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7125 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7126 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7127 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7128 }
7129 } else {
7130 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7131 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7132 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7133 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7134 }
7135 }
7136
7137 void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state, enum link_m_n_set m_n)
7138 {
7139 const struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7140
7141 if (m_n == M1_N1) {
7142 dp_m_n = &crtc_state->dp_m_n;
7143 dp_m2_n2 = &crtc_state->dp_m2_n2;
7144 } else if (m_n == M2_N2) {
7145
7146 /*
7147 * M2_N2 registers are not supported. Hence m2_n2 divider value
7148 * needs to be programmed into M1_N1.
7149 */
7150 dp_m_n = &crtc_state->dp_m2_n2;
7151 } else {
7152 DRM_ERROR("Unsupported divider value\n");
7153 return;
7154 }
7155
7156 if (crtc_state->has_pch_encoder)
7157 intel_pch_transcoder_set_m_n(crtc_state, &crtc_state->dp_m_n);
7158 else
7159 intel_cpu_transcoder_set_m_n(crtc_state, dp_m_n, dp_m2_n2);
7160 }
7161
7162 static void vlv_compute_dpll(struct intel_crtc *crtc,
7163 struct intel_crtc_state *pipe_config)
7164 {
7165 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
7166 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7167 if (crtc->pipe != PIPE_A)
7168 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7169
7170 /* DPLL not used with DSI, but still need the rest set up */
7171 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7172 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
7173 DPLL_EXT_BUFFER_ENABLE_VLV;
7174
7175 pipe_config->dpll_hw_state.dpll_md =
7176 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7177 }
7178
7179 static void chv_compute_dpll(struct intel_crtc *crtc,
7180 struct intel_crtc_state *pipe_config)
7181 {
7182 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7183 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7184 if (crtc->pipe != PIPE_A)
7185 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7186
7187 /* DPLL not used with DSI, but still need the rest set up */
7188 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7189 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
7190
7191 pipe_config->dpll_hw_state.dpll_md =
7192 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7193 }
7194
7195 static void vlv_prepare_pll(struct intel_crtc *crtc,
7196 const struct intel_crtc_state *pipe_config)
7197 {
7198 struct drm_device *dev = crtc->base.dev;
7199 struct drm_i915_private *dev_priv = to_i915(dev);
7200 enum pipe pipe = crtc->pipe;
7201 u32 mdiv;
7202 u32 bestn, bestm1, bestm2, bestp1, bestp2;
7203 u32 coreclk, reg_val;
7204
7205 /* Enable Refclk */
7206 I915_WRITE(DPLL(pipe),
7207 pipe_config->dpll_hw_state.dpll &
7208 ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
7209
7210 /* No need to actually set up the DPLL with DSI */
7211 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7212 return;
7213
7214 mutex_lock(&dev_priv->sb_lock);
7215
7216 bestn = pipe_config->dpll.n;
7217 bestm1 = pipe_config->dpll.m1;
7218 bestm2 = pipe_config->dpll.m2;
7219 bestp1 = pipe_config->dpll.p1;
7220 bestp2 = pipe_config->dpll.p2;
7221
7222 /* See eDP HDMI DPIO driver vbios notes doc */
7223
7224 /* PLL B needs special handling */
7225 if (pipe == PIPE_B)
7226 vlv_pllb_recal_opamp(dev_priv, pipe);
7227
7228 /* Set up Tx target for periodic Rcomp update */
7229 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7230
7231 /* Disable target IRef on PLL */
7232 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7233 reg_val &= 0x00ffffff;
7234 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7235
7236 /* Disable fast lock */
7237 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7238
7239 /* Set idtafcrecal before PLL is enabled */
7240 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7241 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7242 mdiv |= ((bestn << DPIO_N_SHIFT));
7243 mdiv |= (1 << DPIO_K_SHIFT);
7244
7245 /*
7246 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7247 * but we don't support that).
7248 * Note: don't use the DAC post divider as it seems unstable.
7249 */
7250 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7251 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7252
7253 mdiv |= DPIO_ENABLE_CALIBRATION;
7254 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7255
7256 /* Set HBR and RBR LPF coefficients */
7257 if (pipe_config->port_clock == 162000 ||
7258 intel_crtc_has_type(pipe_config, INTEL_OUTPUT_ANALOG) ||
7259 intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
7260 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7261 0x009f0003);
7262 else
7263 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7264 0x00d0000f);
7265
7266 if (intel_crtc_has_dp_encoder(pipe_config)) {
7267 /* Use SSC source */
7268 if (pipe == PIPE_A)
7269 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7270 0x0df40000);
7271 else
7272 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7273 0x0df70000);
7274 } else { /* HDMI or VGA */
7275 /* Use bend source */
7276 if (pipe == PIPE_A)
7277 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7278 0x0df70000);
7279 else
7280 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7281 0x0df40000);
7282 }
7283
7284 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7285 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7286 if (intel_crtc_has_dp_encoder(pipe_config))
7287 coreclk |= 0x01000000;
7288 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7289
7290 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7291 mutex_unlock(&dev_priv->sb_lock);
7292 }
7293
7294 static void chv_prepare_pll(struct intel_crtc *crtc,
7295 const struct intel_crtc_state *pipe_config)
7296 {
7297 struct drm_device *dev = crtc->base.dev;
7298 struct drm_i915_private *dev_priv = to_i915(dev);
7299 enum pipe pipe = crtc->pipe;
7300 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7301 u32 loopfilter, tribuf_calcntr;
7302 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7303 u32 dpio_val;
7304 int vco;
7305
7306 /* Enable Refclk and SSC */
7307 I915_WRITE(DPLL(pipe),
7308 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7309
7310 /* No need to actually set up the DPLL with DSI */
7311 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7312 return;
7313
7314 bestn = pipe_config->dpll.n;
7315 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7316 bestm1 = pipe_config->dpll.m1;
7317 bestm2 = pipe_config->dpll.m2 >> 22;
7318 bestp1 = pipe_config->dpll.p1;
7319 bestp2 = pipe_config->dpll.p2;
7320 vco = pipe_config->dpll.vco;
7321 dpio_val = 0;
7322 loopfilter = 0;
7323
7324 mutex_lock(&dev_priv->sb_lock);
7325
7326 /* p1 and p2 divider */
7327 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7328 5 << DPIO_CHV_S1_DIV_SHIFT |
7329 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7330 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7331 1 << DPIO_CHV_K_DIV_SHIFT);
7332
7333 /* Feedback post-divider - m2 */
7334 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7335
7336 /* Feedback refclk divider - n and m1 */
7337 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7338 DPIO_CHV_M1_DIV_BY_2 |
7339 1 << DPIO_CHV_N_DIV_SHIFT);
7340
7341 /* M2 fraction division */
7342 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7343
7344 /* M2 fraction division enable */
7345 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7346 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7347 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7348 if (bestm2_frac)
7349 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7350 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7351
7352 /* Program digital lock detect threshold */
7353 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7354 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7355 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7356 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7357 if (!bestm2_frac)
7358 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7359 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7360
7361 /* Loop filter */
7362 if (vco == 5400000) {
7363 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7364 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7365 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7366 tribuf_calcntr = 0x9;
7367 } else if (vco <= 6200000) {
7368 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7369 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7370 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7371 tribuf_calcntr = 0x9;
7372 } else if (vco <= 6480000) {
7373 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7374 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7375 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7376 tribuf_calcntr = 0x8;
7377 } else {
7378 /* Not supported. Apply the same limits as in the max case */
7379 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7380 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7381 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7382 tribuf_calcntr = 0;
7383 }
7384 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7385
7386 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7387 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7388 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7389 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7390
7391 /* AFC Recal */
7392 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7393 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7394 DPIO_AFC_RECAL);
7395
7396 mutex_unlock(&dev_priv->sb_lock);
7397 }
7398
7399 /**
7400 * vlv_force_pll_on - forcibly enable just the PLL
7401 * @dev_priv: i915 private structure
7402 * @pipe: pipe PLL to enable
7403 * @dpll: PLL configuration
7404 *
7405 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7406 * in cases where we need the PLL enabled even when @pipe is not going to
7407 * be enabled.
7408 */
7409 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
7410 const struct dpll *dpll)
7411 {
7412 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
7413 struct intel_crtc_state *pipe_config;
7414
7415 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7416 if (!pipe_config)
7417 return -ENOMEM;
7418
7419 pipe_config->base.crtc = &crtc->base;
7420 pipe_config->pixel_multiplier = 1;
7421 pipe_config->dpll = *dpll;
7422
7423 if (IS_CHERRYVIEW(dev_priv)) {
7424 chv_compute_dpll(crtc, pipe_config);
7425 chv_prepare_pll(crtc, pipe_config);
7426 chv_enable_pll(crtc, pipe_config);
7427 } else {
7428 vlv_compute_dpll(crtc, pipe_config);
7429 vlv_prepare_pll(crtc, pipe_config);
7430 vlv_enable_pll(crtc, pipe_config);
7431 }
7432
7433 kfree(pipe_config);
7434
7435 return 0;
7436 }
7437
7438 /**
7439 * vlv_force_pll_off - forcibly disable just the PLL
7440 * @dev_priv: i915 private structure
7441 * @pipe: pipe PLL to disable
7442 *
7443 * Disable the PLL for @pipe. To be used in cases where we need
7444 * the PLL enabled even when @pipe is not going to be enabled.
7445 */
7446 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
7447 {
7448 if (IS_CHERRYVIEW(dev_priv))
7449 chv_disable_pll(dev_priv, pipe);
7450 else
7451 vlv_disable_pll(dev_priv, pipe);
7452 }
7453
7454 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7455 struct intel_crtc_state *crtc_state,
7456 struct dpll *reduced_clock)
7457 {
7458 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7459 u32 dpll;
7460 struct dpll *clock = &crtc_state->dpll;
7461
7462 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7463
7464 dpll = DPLL_VGA_MODE_DIS;
7465
7466 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
7467 dpll |= DPLLB_MODE_LVDS;
7468 else
7469 dpll |= DPLLB_MODE_DAC_SERIAL;
7470
7471 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
7472 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
7473 dpll |= (crtc_state->pixel_multiplier - 1)
7474 << SDVO_MULTIPLIER_SHIFT_HIRES;
7475 }
7476
7477 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7478 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
7479 dpll |= DPLL_SDVO_HIGH_SPEED;
7480
7481 if (intel_crtc_has_dp_encoder(crtc_state))
7482 dpll |= DPLL_SDVO_HIGH_SPEED;
7483
7484 /* compute bitmask from p1 value */
7485 if (IS_PINEVIEW(dev_priv))
7486 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7487 else {
7488 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7489 if (IS_G4X(dev_priv) && reduced_clock)
7490 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7491 }
7492 switch (clock->p2) {
7493 case 5:
7494 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7495 break;
7496 case 7:
7497 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7498 break;
7499 case 10:
7500 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7501 break;
7502 case 14:
7503 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7504 break;
7505 }
7506 if (INTEL_GEN(dev_priv) >= 4)
7507 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7508
7509 if (crtc_state->sdvo_tv_clock)
7510 dpll |= PLL_REF_INPUT_TVCLKINBC;
7511 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7512 intel_panel_use_ssc(dev_priv))
7513 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7514 else
7515 dpll |= PLL_REF_INPUT_DREFCLK;
7516
7517 dpll |= DPLL_VCO_ENABLE;
7518 crtc_state->dpll_hw_state.dpll = dpll;
7519
7520 if (INTEL_GEN(dev_priv) >= 4) {
7521 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7522 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7523 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7524 }
7525 }
7526
7527 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7528 struct intel_crtc_state *crtc_state,
7529 struct dpll *reduced_clock)
7530 {
7531 struct drm_device *dev = crtc->base.dev;
7532 struct drm_i915_private *dev_priv = to_i915(dev);
7533 u32 dpll;
7534 struct dpll *clock = &crtc_state->dpll;
7535
7536 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7537
7538 dpll = DPLL_VGA_MODE_DIS;
7539
7540 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7541 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7542 } else {
7543 if (clock->p1 == 2)
7544 dpll |= PLL_P1_DIVIDE_BY_TWO;
7545 else
7546 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7547 if (clock->p2 == 4)
7548 dpll |= PLL_P2_DIVIDE_BY_4;
7549 }
7550
7551 /*
7552 * Bspec:
7553 * "[Almador Errata}: For the correct operation of the muxed DVO pins
7554 * (GDEVSELB/I2Cdata, GIRDBY/I2CClk) and (GFRAMEB/DVI_Data,
7555 * GTRDYB/DVI_Clk): Bit 31 (DPLL VCO Enable) and Bit 30 (2X Clock
7556 * Enable) must be set to “1” in both the DPLL A Control Register
7557 * (06014h-06017h) and DPLL B Control Register (06018h-0601Bh)."
7558 *
7559 * For simplicity We simply keep both bits always enabled in
7560 * both DPLLS. The spec says we should disable the DVO 2X clock
7561 * when not needed, but this seems to work fine in practice.
7562 */
7563 if (IS_I830(dev_priv) ||
7564 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
7565 dpll |= DPLL_DVO_2X_MODE;
7566
7567 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7568 intel_panel_use_ssc(dev_priv))
7569 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7570 else
7571 dpll |= PLL_REF_INPUT_DREFCLK;
7572
7573 dpll |= DPLL_VCO_ENABLE;
7574 crtc_state->dpll_hw_state.dpll = dpll;
7575 }
7576
7577 static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state)
7578 {
7579 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
7580 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7581 enum pipe pipe = crtc->pipe;
7582 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
7583 const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
7584 u32 crtc_vtotal, crtc_vblank_end;
7585 int vsyncshift = 0;
7586
7587 /* We need to be careful not to changed the adjusted mode, for otherwise
7588 * the hw state checker will get angry at the mismatch. */
7589 crtc_vtotal = adjusted_mode->crtc_vtotal;
7590 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7591
7592 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7593 /* the chip adds 2 halflines automatically */
7594 crtc_vtotal -= 1;
7595 crtc_vblank_end -= 1;
7596
7597 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
7598 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7599 else
7600 vsyncshift = adjusted_mode->crtc_hsync_start -
7601 adjusted_mode->crtc_htotal / 2;
7602 if (vsyncshift < 0)
7603 vsyncshift += adjusted_mode->crtc_htotal;
7604 }
7605
7606 if (INTEL_GEN(dev_priv) > 3)
7607 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7608
7609 I915_WRITE(HTOTAL(cpu_transcoder),
7610 (adjusted_mode->crtc_hdisplay - 1) |
7611 ((adjusted_mode->crtc_htotal - 1) << 16));
7612 I915_WRITE(HBLANK(cpu_transcoder),
7613 (adjusted_mode->crtc_hblank_start - 1) |
7614 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7615 I915_WRITE(HSYNC(cpu_transcoder),
7616 (adjusted_mode->crtc_hsync_start - 1) |
7617 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7618
7619 I915_WRITE(VTOTAL(cpu_transcoder),
7620 (adjusted_mode->crtc_vdisplay - 1) |
7621 ((crtc_vtotal - 1) << 16));
7622 I915_WRITE(VBLANK(cpu_transcoder),
7623 (adjusted_mode->crtc_vblank_start - 1) |
7624 ((crtc_vblank_end - 1) << 16));
7625 I915_WRITE(VSYNC(cpu_transcoder),
7626 (adjusted_mode->crtc_vsync_start - 1) |
7627 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7628
7629 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7630 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7631 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7632 * bits. */
7633 if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
7634 (pipe == PIPE_B || pipe == PIPE_C))
7635 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7636
7637 }
7638
7639 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
7640 {
7641 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
7642 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7643 enum pipe pipe = crtc->pipe;
7644
7645 /* pipesrc controls the size that is scaled from, which should
7646 * always be the user's requested size.
7647 */
7648 I915_WRITE(PIPESRC(pipe),
7649 ((crtc_state->pipe_src_w - 1) << 16) |
7650 (crtc_state->pipe_src_h - 1));
7651 }
7652
7653 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7654 struct intel_crtc_state *pipe_config)
7655 {
7656 struct drm_device *dev = crtc->base.dev;
7657 struct drm_i915_private *dev_priv = to_i915(dev);
7658 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7659 u32 tmp;
7660
7661 tmp = I915_READ(HTOTAL(cpu_transcoder));
7662 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7663 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7664 tmp = I915_READ(HBLANK(cpu_transcoder));
7665 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7666 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7667 tmp = I915_READ(HSYNC(cpu_transcoder));
7668 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7669 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7670
7671 tmp = I915_READ(VTOTAL(cpu_transcoder));
7672 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7673 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7674 tmp = I915_READ(VBLANK(cpu_transcoder));
7675 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7676 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7677 tmp = I915_READ(VSYNC(cpu_transcoder));
7678 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7679 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7680
7681 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7682 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7683 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7684 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7685 }
7686 }
7687
7688 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
7689 struct intel_crtc_state *pipe_config)
7690 {
7691 struct drm_device *dev = crtc->base.dev;
7692 struct drm_i915_private *dev_priv = to_i915(dev);
7693 u32 tmp;
7694
7695 tmp = I915_READ(PIPESRC(crtc->pipe));
7696 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7697 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7698
7699 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7700 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7701 }
7702
7703 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7704 struct intel_crtc_state *pipe_config)
7705 {
7706 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7707 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7708 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7709 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7710
7711 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7712 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7713 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7714 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7715
7716 mode->flags = pipe_config->base.adjusted_mode.flags;
7717 mode->type = DRM_MODE_TYPE_DRIVER;
7718
7719 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7720
7721 mode->hsync = drm_mode_hsync(mode);
7722 mode->vrefresh = drm_mode_vrefresh(mode);
7723 drm_mode_set_name(mode);
7724 }
7725
7726 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
7727 {
7728 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
7729 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7730 u32 pipeconf;
7731
7732 pipeconf = 0;
7733
7734 /* we keep both pipes enabled on 830 */
7735 if (IS_I830(dev_priv))
7736 pipeconf |= I915_READ(PIPECONF(crtc->pipe)) & PIPECONF_ENABLE;
7737
7738 if (crtc_state->double_wide)
7739 pipeconf |= PIPECONF_DOUBLE_WIDE;
7740
7741 /* only g4x and later have fancy bpc/dither controls */
7742 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7743 IS_CHERRYVIEW(dev_priv)) {
7744 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7745 if (crtc_state->dither && crtc_state->pipe_bpp != 30)
7746 pipeconf |= PIPECONF_DITHER_EN |
7747 PIPECONF_DITHER_TYPE_SP;
7748
7749 switch (crtc_state->pipe_bpp) {
7750 case 18:
7751 pipeconf |= PIPECONF_6BPC;
7752 break;
7753 case 24:
7754 pipeconf |= PIPECONF_8BPC;
7755 break;
7756 case 30:
7757 pipeconf |= PIPECONF_10BPC;
7758 break;
7759 default:
7760 /* Case prevented by intel_choose_pipe_bpp_dither. */
7761 BUG();
7762 }
7763 }
7764
7765 if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7766 if (INTEL_GEN(dev_priv) < 4 ||
7767 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
7768 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7769 else
7770 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7771 } else {
7772 pipeconf |= PIPECONF_PROGRESSIVE;
7773 }
7774
7775 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7776 crtc_state->limited_color_range)
7777 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7778
7779 pipeconf |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
7780
7781 I915_WRITE(PIPECONF(crtc->pipe), pipeconf);
7782 POSTING_READ(PIPECONF(crtc->pipe));
7783 }
7784
7785 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
7786 struct intel_crtc_state *crtc_state)
7787 {
7788 struct drm_device *dev = crtc->base.dev;
7789 struct drm_i915_private *dev_priv = to_i915(dev);
7790 const struct intel_limit *limit;
7791 int refclk = 48000;
7792
7793 memset(&crtc_state->dpll_hw_state, 0,
7794 sizeof(crtc_state->dpll_hw_state));
7795
7796 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7797 if (intel_panel_use_ssc(dev_priv)) {
7798 refclk = dev_priv->vbt.lvds_ssc_freq;
7799 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7800 }
7801
7802 limit = &intel_limits_i8xx_lvds;
7803 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
7804 limit = &intel_limits_i8xx_dvo;
7805 } else {
7806 limit = &intel_limits_i8xx_dac;
7807 }
7808
7809 if (!crtc_state->clock_set &&
7810 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7811 refclk, NULL, &crtc_state->dpll)) {
7812 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7813 return -EINVAL;
7814 }
7815
7816 i8xx_compute_dpll(crtc, crtc_state, NULL);
7817
7818 return 0;
7819 }
7820
7821 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7822 struct intel_crtc_state *crtc_state)
7823 {
7824 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7825 const struct intel_limit *limit;
7826 int refclk = 96000;
7827
7828 memset(&crtc_state->dpll_hw_state, 0,
7829 sizeof(crtc_state->dpll_hw_state));
7830
7831 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7832 if (intel_panel_use_ssc(dev_priv)) {
7833 refclk = dev_priv->vbt.lvds_ssc_freq;
7834 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7835 }
7836
7837 if (intel_is_dual_link_lvds(dev_priv))
7838 limit = &intel_limits_g4x_dual_channel_lvds;
7839 else
7840 limit = &intel_limits_g4x_single_channel_lvds;
7841 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
7842 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
7843 limit = &intel_limits_g4x_hdmi;
7844 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
7845 limit = &intel_limits_g4x_sdvo;
7846 } else {
7847 /* The option is for other outputs */
7848 limit = &intel_limits_i9xx_sdvo;
7849 }
7850
7851 if (!crtc_state->clock_set &&
7852 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7853 refclk, NULL, &crtc_state->dpll)) {
7854 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7855 return -EINVAL;
7856 }
7857
7858 i9xx_compute_dpll(crtc, crtc_state, NULL);
7859
7860 return 0;
7861 }
7862
7863 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
7864 struct intel_crtc_state *crtc_state)
7865 {
7866 struct drm_device *dev = crtc->base.dev;
7867 struct drm_i915_private *dev_priv = to_i915(dev);
7868 const struct intel_limit *limit;
7869 int refclk = 96000;
7870
7871 memset(&crtc_state->dpll_hw_state, 0,
7872 sizeof(crtc_state->dpll_hw_state));
7873
7874 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7875 if (intel_panel_use_ssc(dev_priv)) {
7876 refclk = dev_priv->vbt.lvds_ssc_freq;
7877 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7878 }
7879
7880 limit = &intel_limits_pineview_lvds;
7881 } else {
7882 limit = &intel_limits_pineview_sdvo;
7883 }
7884
7885 if (!crtc_state->clock_set &&
7886 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7887 refclk, NULL, &crtc_state->dpll)) {
7888 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7889 return -EINVAL;
7890 }
7891
7892 i9xx_compute_dpll(crtc, crtc_state, NULL);
7893
7894 return 0;
7895 }
7896
7897 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7898 struct intel_crtc_state *crtc_state)
7899 {
7900 struct drm_device *dev = crtc->base.dev;
7901 struct drm_i915_private *dev_priv = to_i915(dev);
7902 const struct intel_limit *limit;
7903 int refclk = 96000;
7904
7905 memset(&crtc_state->dpll_hw_state, 0,
7906 sizeof(crtc_state->dpll_hw_state));
7907
7908 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7909 if (intel_panel_use_ssc(dev_priv)) {
7910 refclk = dev_priv->vbt.lvds_ssc_freq;
7911 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7912 }
7913
7914 limit = &intel_limits_i9xx_lvds;
7915 } else {
7916 limit = &intel_limits_i9xx_sdvo;
7917 }
7918
7919 if (!crtc_state->clock_set &&
7920 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7921 refclk, NULL, &crtc_state->dpll)) {
7922 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7923 return -EINVAL;
7924 }
7925
7926 i9xx_compute_dpll(crtc, crtc_state, NULL);
7927
7928 return 0;
7929 }
7930
7931 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
7932 struct intel_crtc_state *crtc_state)
7933 {
7934 int refclk = 100000;
7935 const struct intel_limit *limit = &intel_limits_chv;
7936
7937 memset(&crtc_state->dpll_hw_state, 0,
7938 sizeof(crtc_state->dpll_hw_state));
7939
7940 if (!crtc_state->clock_set &&
7941 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7942 refclk, NULL, &crtc_state->dpll)) {
7943 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7944 return -EINVAL;
7945 }
7946
7947 chv_compute_dpll(crtc, crtc_state);
7948
7949 return 0;
7950 }
7951
7952 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
7953 struct intel_crtc_state *crtc_state)
7954 {
7955 int refclk = 100000;
7956 const struct intel_limit *limit = &intel_limits_vlv;
7957
7958 memset(&crtc_state->dpll_hw_state, 0,
7959 sizeof(crtc_state->dpll_hw_state));
7960
7961 if (!crtc_state->clock_set &&
7962 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7963 refclk, NULL, &crtc_state->dpll)) {
7964 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7965 return -EINVAL;
7966 }
7967
7968 vlv_compute_dpll(crtc, crtc_state);
7969
7970 return 0;
7971 }
7972
7973 static bool i9xx_has_pfit(struct drm_i915_private *dev_priv)
7974 {
7975 if (IS_I830(dev_priv))
7976 return false;
7977
7978 return INTEL_GEN(dev_priv) >= 4 ||
7979 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
7980 }
7981
7982 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7983 struct intel_crtc_state *pipe_config)
7984 {
7985 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7986 u32 tmp;
7987
7988 if (!i9xx_has_pfit(dev_priv))
7989 return;
7990
7991 tmp = I915_READ(PFIT_CONTROL);
7992 if (!(tmp & PFIT_ENABLE))
7993 return;
7994
7995 /* Check whether the pfit is attached to our pipe. */
7996 if (INTEL_GEN(dev_priv) < 4) {
7997 if (crtc->pipe != PIPE_B)
7998 return;
7999 } else {
8000 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8001 return;
8002 }
8003
8004 pipe_config->gmch_pfit.control = tmp;
8005 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8006 }
8007
8008 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8009 struct intel_crtc_state *pipe_config)
8010 {
8011 struct drm_device *dev = crtc->base.dev;
8012 struct drm_i915_private *dev_priv = to_i915(dev);
8013 int pipe = pipe_config->cpu_transcoder;
8014 struct dpll clock;
8015 u32 mdiv;
8016 int refclk = 100000;
8017
8018 /* In case of DSI, DPLL will not be used */
8019 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8020 return;
8021
8022 mutex_lock(&dev_priv->sb_lock);
8023 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8024 mutex_unlock(&dev_priv->sb_lock);
8025
8026 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8027 clock.m2 = mdiv & DPIO_M2DIV_MASK;
8028 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8029 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8030 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8031
8032 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8033 }
8034
8035 static void
8036 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8037 struct intel_initial_plane_config *plane_config)
8038 {
8039 struct drm_device *dev = crtc->base.dev;
8040 struct drm_i915_private *dev_priv = to_i915(dev);
8041 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
8042 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
8043 enum pipe pipe;
8044 u32 val, base, offset;
8045 int fourcc, pixel_format;
8046 unsigned int aligned_height;
8047 struct drm_framebuffer *fb;
8048 struct intel_framebuffer *intel_fb;
8049
8050 if (!plane->get_hw_state(plane, &pipe))
8051 return;
8052
8053 WARN_ON(pipe != crtc->pipe);
8054
8055 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8056 if (!intel_fb) {
8057 DRM_DEBUG_KMS("failed to alloc fb\n");
8058 return;
8059 }
8060
8061 fb = &intel_fb->base;
8062
8063 fb->dev = dev;
8064
8065 val = I915_READ(DSPCNTR(i9xx_plane));
8066
8067 if (INTEL_GEN(dev_priv) >= 4) {
8068 if (val & DISPPLANE_TILED) {
8069 plane_config->tiling = I915_TILING_X;
8070 fb->modifier = I915_FORMAT_MOD_X_TILED;
8071 }
8072
8073 if (val & DISPPLANE_ROTATE_180)
8074 plane_config->rotation = DRM_MODE_ROTATE_180;
8075 }
8076
8077 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B &&
8078 val & DISPPLANE_MIRROR)
8079 plane_config->rotation |= DRM_MODE_REFLECT_X;
8080
8081 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8082 fourcc = i9xx_format_to_fourcc(pixel_format);
8083 fb->format = drm_format_info(fourcc);
8084
8085 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
8086 offset = I915_READ(DSPOFFSET(i9xx_plane));
8087 base = I915_READ(DSPSURF(i9xx_plane)) & 0xfffff000;
8088 } else if (INTEL_GEN(dev_priv) >= 4) {
8089 if (plane_config->tiling)
8090 offset = I915_READ(DSPTILEOFF(i9xx_plane));
8091 else
8092 offset = I915_READ(DSPLINOFF(i9xx_plane));
8093 base = I915_READ(DSPSURF(i9xx_plane)) & 0xfffff000;
8094 } else {
8095 base = I915_READ(DSPADDR(i9xx_plane));
8096 }
8097 plane_config->base = base;
8098
8099 val = I915_READ(PIPESRC(pipe));
8100 fb->width = ((val >> 16) & 0xfff) + 1;
8101 fb->height = ((val >> 0) & 0xfff) + 1;
8102
8103 val = I915_READ(DSPSTRIDE(i9xx_plane));
8104 fb->pitches[0] = val & 0xffffffc0;
8105
8106 aligned_height = intel_fb_align_height(fb, 0, fb->height);
8107
8108 plane_config->size = fb->pitches[0] * aligned_height;
8109
8110 DRM_DEBUG_KMS("%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8111 crtc->base.name, plane->base.name, fb->width, fb->height,
8112 fb->format->cpp[0] * 8, base, fb->pitches[0],
8113 plane_config->size);
8114
8115 plane_config->fb = intel_fb;
8116 }
8117
8118 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8119 struct intel_crtc_state *pipe_config)
8120 {
8121 struct drm_device *dev = crtc->base.dev;
8122 struct drm_i915_private *dev_priv = to_i915(dev);
8123 int pipe = pipe_config->cpu_transcoder;
8124 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8125 struct dpll clock;
8126 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8127 int refclk = 100000;
8128
8129 /* In case of DSI, DPLL will not be used */
8130 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8131 return;
8132
8133 mutex_lock(&dev_priv->sb_lock);
8134 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8135 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8136 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8137 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8138 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8139 mutex_unlock(&dev_priv->sb_lock);
8140
8141 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8142 clock.m2 = (pll_dw0 & 0xff) << 22;
8143 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8144 clock.m2 |= pll_dw2 & 0x3fffff;
8145 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8146 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8147 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8148
8149 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8150 }
8151
8152 static void intel_get_crtc_ycbcr_config(struct intel_crtc *crtc,
8153 struct intel_crtc_state *pipe_config)
8154 {
8155 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8156 enum intel_output_format output = INTEL_OUTPUT_FORMAT_RGB;
8157
8158 pipe_config->lspcon_downsampling = false;
8159
8160 if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) {
8161 u32 tmp = I915_READ(PIPEMISC(crtc->pipe));
8162
8163 if (tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV) {
8164 bool ycbcr420_enabled = tmp & PIPEMISC_YUV420_ENABLE;
8165 bool blend = tmp & PIPEMISC_YUV420_MODE_FULL_BLEND;
8166
8167 if (ycbcr420_enabled) {
8168 /* We support 4:2:0 in full blend mode only */
8169 if (!blend)
8170 output = INTEL_OUTPUT_FORMAT_INVALID;
8171 else if (!(IS_GEMINILAKE(dev_priv) ||
8172 INTEL_GEN(dev_priv) >= 10))
8173 output = INTEL_OUTPUT_FORMAT_INVALID;
8174 else
8175 output = INTEL_OUTPUT_FORMAT_YCBCR420;
8176 } else {
8177 /*
8178 * Currently there is no interface defined to
8179 * check user preference between RGB/YCBCR444
8180 * or YCBCR420. So the only possible case for
8181 * YCBCR444 usage is driving YCBCR420 output
8182 * with LSPCON, when pipe is configured for
8183 * YCBCR444 output and LSPCON takes care of
8184 * downsampling it.
8185 */
8186 pipe_config->lspcon_downsampling = true;
8187 output = INTEL_OUTPUT_FORMAT_YCBCR444;
8188 }
8189 }
8190 }
8191
8192 pipe_config->output_format = output;
8193 }
8194
8195 static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state)
8196 {
8197 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
8198 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
8199 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8200 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
8201 u32 tmp;
8202
8203 tmp = I915_READ(DSPCNTR(i9xx_plane));
8204
8205 if (tmp & DISPPLANE_GAMMA_ENABLE)
8206 crtc_state->gamma_enable = true;
8207
8208 if (!HAS_GMCH(dev_priv) &&
8209 tmp & DISPPLANE_PIPE_CSC_ENABLE)
8210 crtc_state->csc_enable = true;
8211 }
8212
8213 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8214 struct intel_crtc_state *pipe_config)
8215 {
8216 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8217 enum intel_display_power_domain power_domain;
8218 intel_wakeref_t wakeref;
8219 u32 tmp;
8220 bool ret;
8221
8222 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8223 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
8224 if (!wakeref)
8225 return false;
8226
8227 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
8228 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8229 pipe_config->shared_dpll = NULL;
8230
8231 ret = false;
8232
8233 tmp = I915_READ(PIPECONF(crtc->pipe));
8234 if (!(tmp & PIPECONF_ENABLE))
8235 goto out;
8236
8237 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
8238 IS_CHERRYVIEW(dev_priv)) {
8239 switch (tmp & PIPECONF_BPC_MASK) {
8240 case PIPECONF_6BPC:
8241 pipe_config->pipe_bpp = 18;
8242 break;
8243 case PIPECONF_8BPC:
8244 pipe_config->pipe_bpp = 24;
8245 break;
8246 case PIPECONF_10BPC:
8247 pipe_config->pipe_bpp = 30;
8248 break;
8249 default:
8250 break;
8251 }
8252 }
8253
8254 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
8255 (tmp & PIPECONF_COLOR_RANGE_SELECT))
8256 pipe_config->limited_color_range = true;
8257
8258 pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_I9XX) >>
8259 PIPECONF_GAMMA_MODE_SHIFT;
8260
8261 if (IS_CHERRYVIEW(dev_priv))
8262 pipe_config->cgm_mode = I915_READ(CGM_PIPE_MODE(crtc->pipe));
8263
8264 i9xx_get_pipe_color_config(pipe_config);
8265
8266 if (INTEL_GEN(dev_priv) < 4)
8267 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8268
8269 intel_get_pipe_timings(crtc, pipe_config);
8270 intel_get_pipe_src_size(crtc, pipe_config);
8271
8272 i9xx_get_pfit_config(crtc, pipe_config);
8273
8274 if (INTEL_GEN(dev_priv) >= 4) {
8275 /* No way to read it out on pipes B and C */
8276 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
8277 tmp = dev_priv->chv_dpll_md[crtc->pipe];
8278 else
8279 tmp = I915_READ(DPLL_MD(crtc->pipe));
8280 pipe_config->pixel_multiplier =
8281 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8282 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8283 pipe_config->dpll_hw_state.dpll_md = tmp;
8284 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
8285 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
8286 tmp = I915_READ(DPLL(crtc->pipe));
8287 pipe_config->pixel_multiplier =
8288 ((tmp & SDVO_MULTIPLIER_MASK)
8289 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8290 } else {
8291 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8292 * port and will be fixed up in the encoder->get_config
8293 * function. */
8294 pipe_config->pixel_multiplier = 1;
8295 }
8296 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8297 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
8298 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8299 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8300 } else {
8301 /* Mask out read-only status bits. */
8302 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8303 DPLL_PORTC_READY_MASK |
8304 DPLL_PORTB_READY_MASK);
8305 }
8306
8307 if (IS_CHERRYVIEW(dev_priv))
8308 chv_crtc_clock_get(crtc, pipe_config);
8309 else if (IS_VALLEYVIEW(dev_priv))
8310 vlv_crtc_clock_get(crtc, pipe_config);
8311 else
8312 i9xx_crtc_clock_get(crtc, pipe_config);
8313
8314 /*
8315 * Normally the dotclock is filled in by the encoder .get_config()
8316 * but in case the pipe is enabled w/o any ports we need a sane
8317 * default.
8318 */
8319 pipe_config->base.adjusted_mode.crtc_clock =
8320 pipe_config->port_clock / pipe_config->pixel_multiplier;
8321
8322 ret = true;
8323
8324 out:
8325 intel_display_power_put(dev_priv, power_domain, wakeref);
8326
8327 return ret;
8328 }
8329
8330 static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv)
8331 {
8332 struct intel_encoder *encoder;
8333 int i;
8334 u32 val, final;
8335 bool has_lvds = false;
8336 bool has_cpu_edp = false;
8337 bool has_panel = false;
8338 bool has_ck505 = false;
8339 bool can_ssc = false;
8340 bool using_ssc_source = false;
8341
8342 /* We need to take the global config into account */
8343 for_each_intel_encoder(&dev_priv->drm, encoder) {
8344 switch (encoder->type) {
8345 case INTEL_OUTPUT_LVDS:
8346 has_panel = true;
8347 has_lvds = true;
8348 break;
8349 case INTEL_OUTPUT_EDP:
8350 has_panel = true;
8351 if (encoder->port == PORT_A)
8352 has_cpu_edp = true;
8353 break;
8354 default:
8355 break;
8356 }
8357 }
8358
8359 if (HAS_PCH_IBX(dev_priv)) {
8360 has_ck505 = dev_priv->vbt.display_clock_mode;
8361 can_ssc = has_ck505;
8362 } else {
8363 has_ck505 = false;
8364 can_ssc = true;
8365 }
8366
8367 /* Check if any DPLLs are using the SSC source */
8368 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8369 u32 temp = I915_READ(PCH_DPLL(i));
8370
8371 if (!(temp & DPLL_VCO_ENABLE))
8372 continue;
8373
8374 if ((temp & PLL_REF_INPUT_MASK) ==
8375 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
8376 using_ssc_source = true;
8377 break;
8378 }
8379 }
8380
8381 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
8382 has_panel, has_lvds, has_ck505, using_ssc_source);
8383
8384 /* Ironlake: try to setup display ref clock before DPLL
8385 * enabling. This is only under driver's control after
8386 * PCH B stepping, previous chipset stepping should be
8387 * ignoring this setting.
8388 */
8389 val = I915_READ(PCH_DREF_CONTROL);
8390
8391 /* As we must carefully and slowly disable/enable each source in turn,
8392 * compute the final state we want first and check if we need to
8393 * make any changes at all.
8394 */
8395 final = val;
8396 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8397 if (has_ck505)
8398 final |= DREF_NONSPREAD_CK505_ENABLE;
8399 else
8400 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8401
8402 final &= ~DREF_SSC_SOURCE_MASK;
8403 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8404 final &= ~DREF_SSC1_ENABLE;
8405
8406 if (has_panel) {
8407 final |= DREF_SSC_SOURCE_ENABLE;
8408
8409 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8410 final |= DREF_SSC1_ENABLE;
8411
8412 if (has_cpu_edp) {
8413 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8414 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8415 else
8416 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8417 } else
8418 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8419 } else if (using_ssc_source) {
8420 final |= DREF_SSC_SOURCE_ENABLE;
8421 final |= DREF_SSC1_ENABLE;
8422 }
8423
8424 if (final == val)
8425 return;
8426
8427 /* Always enable nonspread source */
8428 val &= ~DREF_NONSPREAD_SOURCE_MASK;
8429
8430 if (has_ck505)
8431 val |= DREF_NONSPREAD_CK505_ENABLE;
8432 else
8433 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8434
8435 if (has_panel) {
8436 val &= ~DREF_SSC_SOURCE_MASK;
8437 val |= DREF_SSC_SOURCE_ENABLE;
8438
8439 /* SSC must be turned on before enabling the CPU output */
8440 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8441 DRM_DEBUG_KMS("Using SSC on panel\n");
8442 val |= DREF_SSC1_ENABLE;
8443 } else
8444 val &= ~DREF_SSC1_ENABLE;
8445
8446 /* Get SSC going before enabling the outputs */
8447 I915_WRITE(PCH_DREF_CONTROL, val);
8448 POSTING_READ(PCH_DREF_CONTROL);
8449 udelay(200);
8450
8451 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8452
8453 /* Enable CPU source on CPU attached eDP */
8454 if (has_cpu_edp) {
8455 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8456 DRM_DEBUG_KMS("Using SSC on eDP\n");
8457 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8458 } else
8459 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8460 } else
8461 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8462
8463 I915_WRITE(PCH_DREF_CONTROL, val);
8464 POSTING_READ(PCH_DREF_CONTROL);
8465 udelay(200);
8466 } else {
8467 DRM_DEBUG_KMS("Disabling CPU source output\n");
8468
8469 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8470
8471 /* Turn off CPU output */
8472 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8473
8474 I915_WRITE(PCH_DREF_CONTROL, val);
8475 POSTING_READ(PCH_DREF_CONTROL);
8476 udelay(200);
8477
8478 if (!using_ssc_source) {
8479 DRM_DEBUG_KMS("Disabling SSC source\n");
8480
8481 /* Turn off the SSC source */
8482 val &= ~DREF_SSC_SOURCE_MASK;
8483 val |= DREF_SSC_SOURCE_DISABLE;
8484
8485 /* Turn off SSC1 */
8486 val &= ~DREF_SSC1_ENABLE;
8487
8488 I915_WRITE(PCH_DREF_CONTROL, val);
8489 POSTING_READ(PCH_DREF_CONTROL);
8490 udelay(200);
8491 }
8492 }
8493
8494 BUG_ON(val != final);
8495 }
8496
8497 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8498 {
8499 u32 tmp;
8500
8501 tmp = I915_READ(SOUTH_CHICKEN2);
8502 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8503 I915_WRITE(SOUTH_CHICKEN2, tmp);
8504
8505 if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
8506 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8507 DRM_ERROR("FDI mPHY reset assert timeout\n");
8508
8509 tmp = I915_READ(SOUTH_CHICKEN2);
8510 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8511 I915_WRITE(SOUTH_CHICKEN2, tmp);
8512
8513 if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
8514 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8515 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8516 }
8517
8518 /* WaMPhyProgramming:hsw */
8519 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8520 {
8521 u32 tmp;
8522
8523 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8524 tmp &= ~(0xFF << 24);
8525 tmp |= (0x12 << 24);
8526 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8527
8528 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8529 tmp |= (1 << 11);
8530 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8531
8532 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8533 tmp |= (1 << 11);
8534 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8535
8536 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8537 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8538 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8539
8540 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8541 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8542 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8543
8544 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8545 tmp &= ~(7 << 13);
8546 tmp |= (5 << 13);
8547 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8548
8549 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8550 tmp &= ~(7 << 13);
8551 tmp |= (5 << 13);
8552 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8553
8554 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8555 tmp &= ~0xFF;
8556 tmp |= 0x1C;
8557 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8558
8559 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8560 tmp &= ~0xFF;
8561 tmp |= 0x1C;
8562 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8563
8564 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8565 tmp &= ~(0xFF << 16);
8566 tmp |= (0x1C << 16);
8567 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8568
8569 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8570 tmp &= ~(0xFF << 16);
8571 tmp |= (0x1C << 16);
8572 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8573
8574 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8575 tmp |= (1 << 27);
8576 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8577
8578 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8579 tmp |= (1 << 27);
8580 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8581
8582 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8583 tmp &= ~(0xF << 28);
8584 tmp |= (4 << 28);
8585 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8586
8587 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8588 tmp &= ~(0xF << 28);
8589 tmp |= (4 << 28);
8590 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8591 }
8592
8593 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8594 * Programming" based on the parameters passed:
8595 * - Sequence to enable CLKOUT_DP
8596 * - Sequence to enable CLKOUT_DP without spread
8597 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8598 */
8599 static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
8600 bool with_spread, bool with_fdi)
8601 {
8602 u32 reg, tmp;
8603
8604 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8605 with_spread = true;
8606 if (WARN(HAS_PCH_LPT_LP(dev_priv) &&
8607 with_fdi, "LP PCH doesn't have FDI\n"))
8608 with_fdi = false;
8609
8610 mutex_lock(&dev_priv->sb_lock);
8611
8612 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8613 tmp &= ~SBI_SSCCTL_DISABLE;
8614 tmp |= SBI_SSCCTL_PATHALT;
8615 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8616
8617 udelay(24);
8618
8619 if (with_spread) {
8620 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8621 tmp &= ~SBI_SSCCTL_PATHALT;
8622 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8623
8624 if (with_fdi) {
8625 lpt_reset_fdi_mphy(dev_priv);
8626 lpt_program_fdi_mphy(dev_priv);
8627 }
8628 }
8629
8630 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
8631 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8632 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8633 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8634
8635 mutex_unlock(&dev_priv->sb_lock);
8636 }
8637
8638 /* Sequence to disable CLKOUT_DP */
8639 static void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
8640 {
8641 u32 reg, tmp;
8642
8643 mutex_lock(&dev_priv->sb_lock);
8644
8645 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
8646 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8647 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8648 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8649
8650 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8651 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8652 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8653 tmp |= SBI_SSCCTL_PATHALT;
8654 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8655 udelay(32);
8656 }
8657 tmp |= SBI_SSCCTL_DISABLE;
8658 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8659 }
8660
8661 mutex_unlock(&dev_priv->sb_lock);
8662 }
8663
8664 #define BEND_IDX(steps) ((50 + (steps)) / 5)
8665
8666 static const u16 sscdivintphase[] = {
8667 [BEND_IDX( 50)] = 0x3B23,
8668 [BEND_IDX( 45)] = 0x3B23,
8669 [BEND_IDX( 40)] = 0x3C23,
8670 [BEND_IDX( 35)] = 0x3C23,
8671 [BEND_IDX( 30)] = 0x3D23,
8672 [BEND_IDX( 25)] = 0x3D23,
8673 [BEND_IDX( 20)] = 0x3E23,
8674 [BEND_IDX( 15)] = 0x3E23,
8675 [BEND_IDX( 10)] = 0x3F23,
8676 [BEND_IDX( 5)] = 0x3F23,
8677 [BEND_IDX( 0)] = 0x0025,
8678 [BEND_IDX( -5)] = 0x0025,
8679 [BEND_IDX(-10)] = 0x0125,
8680 [BEND_IDX(-15)] = 0x0125,
8681 [BEND_IDX(-20)] = 0x0225,
8682 [BEND_IDX(-25)] = 0x0225,
8683 [BEND_IDX(-30)] = 0x0325,
8684 [BEND_IDX(-35)] = 0x0325,
8685 [BEND_IDX(-40)] = 0x0425,
8686 [BEND_IDX(-45)] = 0x0425,
8687 [BEND_IDX(-50)] = 0x0525,
8688 };
8689
8690 /*
8691 * Bend CLKOUT_DP
8692 * steps -50 to 50 inclusive, in steps of 5
8693 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
8694 * change in clock period = -(steps / 10) * 5.787 ps
8695 */
8696 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
8697 {
8698 u32 tmp;
8699 int idx = BEND_IDX(steps);
8700
8701 if (WARN_ON(steps % 5 != 0))
8702 return;
8703
8704 if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
8705 return;
8706
8707 mutex_lock(&dev_priv->sb_lock);
8708
8709 if (steps % 10 != 0)
8710 tmp = 0xAAAAAAAB;
8711 else
8712 tmp = 0x00000000;
8713 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
8714
8715 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
8716 tmp &= 0xffff0000;
8717 tmp |= sscdivintphase[idx];
8718 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
8719
8720 mutex_unlock(&dev_priv->sb_lock);
8721 }
8722
8723 #undef BEND_IDX
8724
8725 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
8726 {
8727 struct intel_encoder *encoder;
8728 bool has_vga = false;
8729
8730 for_each_intel_encoder(&dev_priv->drm, encoder) {
8731 switch (encoder->type) {
8732 case INTEL_OUTPUT_ANALOG:
8733 has_vga = true;
8734 break;
8735 default:
8736 break;
8737 }
8738 }
8739
8740 if (has_vga) {
8741 lpt_bend_clkout_dp(dev_priv, 0);
8742 lpt_enable_clkout_dp(dev_priv, true, true);
8743 } else {
8744 lpt_disable_clkout_dp(dev_priv);
8745 }
8746 }
8747
8748 /*
8749 * Initialize reference clocks when the driver loads
8750 */
8751 void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
8752 {
8753 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
8754 ironlake_init_pch_refclk(dev_priv);
8755 else if (HAS_PCH_LPT(dev_priv))
8756 lpt_init_pch_refclk(dev_priv);
8757 }
8758
8759 static void ironlake_set_pipeconf(const struct intel_crtc_state *crtc_state)
8760 {
8761 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
8762 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8763 enum pipe pipe = crtc->pipe;
8764 u32 val;
8765
8766 val = 0;
8767
8768 switch (crtc_state->pipe_bpp) {
8769 case 18:
8770 val |= PIPECONF_6BPC;
8771 break;
8772 case 24:
8773 val |= PIPECONF_8BPC;
8774 break;
8775 case 30:
8776 val |= PIPECONF_10BPC;
8777 break;
8778 case 36:
8779 val |= PIPECONF_12BPC;
8780 break;
8781 default:
8782 /* Case prevented by intel_choose_pipe_bpp_dither. */
8783 BUG();
8784 }
8785
8786 if (crtc_state->dither)
8787 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8788
8789 if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8790 val |= PIPECONF_INTERLACED_ILK;
8791 else
8792 val |= PIPECONF_PROGRESSIVE;
8793
8794 if (crtc_state->limited_color_range)
8795 val |= PIPECONF_COLOR_RANGE_SELECT;
8796
8797 val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
8798
8799 I915_WRITE(PIPECONF(pipe), val);
8800 POSTING_READ(PIPECONF(pipe));
8801 }
8802
8803 static void haswell_set_pipeconf(const struct intel_crtc_state *crtc_state)
8804 {
8805 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
8806 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8807 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
8808 u32 val = 0;
8809
8810 if (IS_HASWELL(dev_priv) && crtc_state->dither)
8811 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8812
8813 if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8814 val |= PIPECONF_INTERLACED_ILK;
8815 else
8816 val |= PIPECONF_PROGRESSIVE;
8817
8818 I915_WRITE(PIPECONF(cpu_transcoder), val);
8819 POSTING_READ(PIPECONF(cpu_transcoder));
8820 }
8821
8822 static void haswell_set_pipemisc(const struct intel_crtc_state *crtc_state)
8823 {
8824 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
8825 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
8826
8827 if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) {
8828 u32 val = 0;
8829
8830 switch (crtc_state->pipe_bpp) {
8831 case 18:
8832 val |= PIPEMISC_DITHER_6_BPC;
8833 break;
8834 case 24:
8835 val |= PIPEMISC_DITHER_8_BPC;
8836 break;
8837 case 30:
8838 val |= PIPEMISC_DITHER_10_BPC;
8839 break;
8840 case 36:
8841 val |= PIPEMISC_DITHER_12_BPC;
8842 break;
8843 default:
8844 /* Case prevented by pipe_config_set_bpp. */
8845 BUG();
8846 }
8847
8848 if (crtc_state->dither)
8849 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8850
8851 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
8852 crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
8853 val |= PIPEMISC_OUTPUT_COLORSPACE_YUV;
8854
8855 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
8856 val |= PIPEMISC_YUV420_ENABLE |
8857 PIPEMISC_YUV420_MODE_FULL_BLEND;
8858
8859 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
8860 }
8861 }
8862
8863 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8864 {
8865 /*
8866 * Account for spread spectrum to avoid
8867 * oversubscribing the link. Max center spread
8868 * is 2.5%; use 5% for safety's sake.
8869 */
8870 u32 bps = target_clock * bpp * 21 / 20;
8871 return DIV_ROUND_UP(bps, link_bw * 8);
8872 }
8873
8874 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8875 {
8876 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8877 }
8878
8879 static void ironlake_compute_dpll(struct intel_crtc *crtc,
8880 struct intel_crtc_state *crtc_state,
8881 struct dpll *reduced_clock)
8882 {
8883 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8884 u32 dpll, fp, fp2;
8885 int factor;
8886
8887 /* Enable autotuning of the PLL clock (if permissible) */
8888 factor = 21;
8889 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8890 if ((intel_panel_use_ssc(dev_priv) &&
8891 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8892 (HAS_PCH_IBX(dev_priv) &&
8893 intel_is_dual_link_lvds(dev_priv)))
8894 factor = 25;
8895 } else if (crtc_state->sdvo_tv_clock) {
8896 factor = 20;
8897 }
8898
8899 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8900
8901 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8902 fp |= FP_CB_TUNE;
8903
8904 if (reduced_clock) {
8905 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8906
8907 if (reduced_clock->m < factor * reduced_clock->n)
8908 fp2 |= FP_CB_TUNE;
8909 } else {
8910 fp2 = fp;
8911 }
8912
8913 dpll = 0;
8914
8915 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8916 dpll |= DPLLB_MODE_LVDS;
8917 else
8918 dpll |= DPLLB_MODE_DAC_SERIAL;
8919
8920 dpll |= (crtc_state->pixel_multiplier - 1)
8921 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8922
8923 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8924 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8925 dpll |= DPLL_SDVO_HIGH_SPEED;
8926
8927 if (intel_crtc_has_dp_encoder(crtc_state))
8928 dpll |= DPLL_SDVO_HIGH_SPEED;
8929
8930 /*
8931 * The high speed IO clock is only really required for
8932 * SDVO/HDMI/DP, but we also enable it for CRT to make it
8933 * possible to share the DPLL between CRT and HDMI. Enabling
8934 * the clock needlessly does no real harm, except use up a
8935 * bit of power potentially.
8936 *
8937 * We'll limit this to IVB with 3 pipes, since it has only two
8938 * DPLLs and so DPLL sharing is the only way to get three pipes
8939 * driving PCH ports at the same time. On SNB we could do this,
8940 * and potentially avoid enabling the second DPLL, but it's not
8941 * clear if it''s a win or loss power wise. No point in doing
8942 * this on ILK at all since it has a fixed DPLL<->pipe mapping.
8943 */
8944 if (INTEL_INFO(dev_priv)->num_pipes == 3 &&
8945 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
8946 dpll |= DPLL_SDVO_HIGH_SPEED;
8947
8948 /* compute bitmask from p1 value */
8949 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8950 /* also FPA1 */
8951 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8952
8953 switch (crtc_state->dpll.p2) {
8954 case 5:
8955 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8956 break;
8957 case 7:
8958 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8959 break;
8960 case 10:
8961 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8962 break;
8963 case 14:
8964 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8965 break;
8966 }
8967
8968 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8969 intel_panel_use_ssc(dev_priv))
8970 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8971 else
8972 dpll |= PLL_REF_INPUT_DREFCLK;
8973
8974 dpll |= DPLL_VCO_ENABLE;
8975
8976 crtc_state->dpll_hw_state.dpll = dpll;
8977 crtc_state->dpll_hw_state.fp0 = fp;
8978 crtc_state->dpll_hw_state.fp1 = fp2;
8979 }
8980
8981 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8982 struct intel_crtc_state *crtc_state)
8983 {
8984 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8985 const struct intel_limit *limit;
8986 int refclk = 120000;
8987
8988 memset(&crtc_state->dpll_hw_state, 0,
8989 sizeof(crtc_state->dpll_hw_state));
8990
8991 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8992 if (!crtc_state->has_pch_encoder)
8993 return 0;
8994
8995 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8996 if (intel_panel_use_ssc(dev_priv)) {
8997 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8998 dev_priv->vbt.lvds_ssc_freq);
8999 refclk = dev_priv->vbt.lvds_ssc_freq;
9000 }
9001
9002 if (intel_is_dual_link_lvds(dev_priv)) {
9003 if (refclk == 100000)
9004 limit = &intel_limits_ironlake_dual_lvds_100m;
9005 else
9006 limit = &intel_limits_ironlake_dual_lvds;
9007 } else {
9008 if (refclk == 100000)
9009 limit = &intel_limits_ironlake_single_lvds_100m;
9010 else
9011 limit = &intel_limits_ironlake_single_lvds;
9012 }
9013 } else {
9014 limit = &intel_limits_ironlake_dac;
9015 }
9016
9017 if (!crtc_state->clock_set &&
9018 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9019 refclk, NULL, &crtc_state->dpll)) {
9020 DRM_ERROR("Couldn't find PLL settings for mode!\n");
9021 return -EINVAL;
9022 }
9023
9024 ironlake_compute_dpll(crtc, crtc_state, NULL);
9025
9026 if (!intel_get_shared_dpll(crtc_state, NULL)) {
9027 DRM_DEBUG_KMS("failed to find PLL for pipe %c\n",
9028 pipe_name(crtc->pipe));
9029 return -EINVAL;
9030 }
9031
9032 return 0;
9033 }
9034
9035 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
9036 struct intel_link_m_n *m_n)
9037 {
9038 struct drm_device *dev = crtc->base.dev;
9039 struct drm_i915_private *dev_priv = to_i915(dev);
9040 enum pipe pipe = crtc->pipe;
9041
9042 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
9043 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
9044 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
9045 & ~TU_SIZE_MASK;
9046 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
9047 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
9048 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9049 }
9050
9051 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
9052 enum transcoder transcoder,
9053 struct intel_link_m_n *m_n,
9054 struct intel_link_m_n *m2_n2)
9055 {
9056 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9057 enum pipe pipe = crtc->pipe;
9058
9059 if (INTEL_GEN(dev_priv) >= 5) {
9060 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9061 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9062 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9063 & ~TU_SIZE_MASK;
9064 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9065 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9066 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9067
9068 if (m2_n2 && transcoder_has_m2_n2(dev_priv, transcoder)) {
9069 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9070 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9071 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9072 & ~TU_SIZE_MASK;
9073 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9074 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9075 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9076 }
9077 } else {
9078 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9079 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9080 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9081 & ~TU_SIZE_MASK;
9082 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9083 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9084 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9085 }
9086 }
9087
9088 void intel_dp_get_m_n(struct intel_crtc *crtc,
9089 struct intel_crtc_state *pipe_config)
9090 {
9091 if (pipe_config->has_pch_encoder)
9092 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9093 else
9094 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9095 &pipe_config->dp_m_n,
9096 &pipe_config->dp_m2_n2);
9097 }
9098
9099 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9100 struct intel_crtc_state *pipe_config)
9101 {
9102 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9103 &pipe_config->fdi_m_n, NULL);
9104 }
9105
9106 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9107 struct intel_crtc_state *pipe_config)
9108 {
9109 struct drm_device *dev = crtc->base.dev;
9110 struct drm_i915_private *dev_priv = to_i915(dev);
9111 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9112 u32 ps_ctrl = 0;
9113 int id = -1;
9114 int i;
9115
9116 /* find scaler attached to this pipe */
9117 for (i = 0; i < crtc->num_scalers; i++) {
9118 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9119 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9120 id = i;
9121 pipe_config->pch_pfit.enabled = true;
9122 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9123 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9124 scaler_state->scalers[i].in_use = true;
9125 break;
9126 }
9127 }
9128
9129 scaler_state->scaler_id = id;
9130 if (id >= 0) {
9131 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9132 } else {
9133 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9134 }
9135 }
9136
9137 static void
9138 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9139 struct intel_initial_plane_config *plane_config)
9140 {
9141 struct drm_device *dev = crtc->base.dev;
9142 struct drm_i915_private *dev_priv = to_i915(dev);
9143 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
9144 enum plane_id plane_id = plane->id;
9145 enum pipe pipe;
9146 u32 val, base, offset, stride_mult, tiling, alpha;
9147 int fourcc, pixel_format;
9148 unsigned int aligned_height;
9149 struct drm_framebuffer *fb;
9150 struct intel_framebuffer *intel_fb;
9151
9152 if (!plane->get_hw_state(plane, &pipe))
9153 return;
9154
9155 WARN_ON(pipe != crtc->pipe);
9156
9157 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9158 if (!intel_fb) {
9159 DRM_DEBUG_KMS("failed to alloc fb\n");
9160 return;
9161 }
9162
9163 fb = &intel_fb->base;
9164
9165 fb->dev = dev;
9166
9167 val = I915_READ(PLANE_CTL(pipe, plane_id));
9168
9169 if (INTEL_GEN(dev_priv) >= 11)
9170 pixel_format = val & ICL_PLANE_CTL_FORMAT_MASK;
9171 else
9172 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9173
9174 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
9175 alpha = I915_READ(PLANE_COLOR_CTL(pipe, plane_id));
9176 alpha &= PLANE_COLOR_ALPHA_MASK;
9177 } else {
9178 alpha = val & PLANE_CTL_ALPHA_MASK;
9179 }
9180
9181 fourcc = skl_format_to_fourcc(pixel_format,
9182 val & PLANE_CTL_ORDER_RGBX, alpha);
9183 fb->format = drm_format_info(fourcc);
9184
9185 tiling = val & PLANE_CTL_TILED_MASK;
9186 switch (tiling) {
9187 case PLANE_CTL_TILED_LINEAR:
9188 fb->modifier = DRM_FORMAT_MOD_LINEAR;
9189 break;
9190 case PLANE_CTL_TILED_X:
9191 plane_config->tiling = I915_TILING_X;
9192 fb->modifier = I915_FORMAT_MOD_X_TILED;
9193 break;
9194 case PLANE_CTL_TILED_Y:
9195 plane_config->tiling = I915_TILING_Y;
9196 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
9197 fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS;
9198 else
9199 fb->modifier = I915_FORMAT_MOD_Y_TILED;
9200 break;
9201 case PLANE_CTL_TILED_YF:
9202 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
9203 fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
9204 else
9205 fb->modifier = I915_FORMAT_MOD_Yf_TILED;
9206 break;
9207 default:
9208 MISSING_CASE(tiling);
9209 goto error;
9210 }
9211
9212 /*
9213 * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
9214 * while i915 HW rotation is clockwise, thats why this swapping.
9215 */
9216 switch (val & PLANE_CTL_ROTATE_MASK) {
9217 case PLANE_CTL_ROTATE_0:
9218 plane_config->rotation = DRM_MODE_ROTATE_0;
9219 break;
9220 case PLANE_CTL_ROTATE_90:
9221 plane_config->rotation = DRM_MODE_ROTATE_270;
9222 break;
9223 case PLANE_CTL_ROTATE_180:
9224 plane_config->rotation = DRM_MODE_ROTATE_180;
9225 break;
9226 case PLANE_CTL_ROTATE_270:
9227 plane_config->rotation = DRM_MODE_ROTATE_90;
9228 break;
9229 }
9230
9231 if (INTEL_GEN(dev_priv) >= 10 &&
9232 val & PLANE_CTL_FLIP_HORIZONTAL)
9233 plane_config->rotation |= DRM_MODE_REFLECT_X;
9234
9235 base = I915_READ(PLANE_SURF(pipe, plane_id)) & 0xfffff000;
9236 plane_config->base = base;
9237
9238 offset = I915_READ(PLANE_OFFSET(pipe, plane_id));
9239
9240 val = I915_READ(PLANE_SIZE(pipe, plane_id));
9241 fb->height = ((val >> 16) & 0xfff) + 1;
9242 fb->width = ((val >> 0) & 0x1fff) + 1;
9243
9244 val = I915_READ(PLANE_STRIDE(pipe, plane_id));
9245 stride_mult = skl_plane_stride_mult(fb, 0, DRM_MODE_ROTATE_0);
9246 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9247
9248 aligned_height = intel_fb_align_height(fb, 0, fb->height);
9249
9250 plane_config->size = fb->pitches[0] * aligned_height;
9251
9252 DRM_DEBUG_KMS("%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9253 crtc->base.name, plane->base.name, fb->width, fb->height,
9254 fb->format->cpp[0] * 8, base, fb->pitches[0],
9255 plane_config->size);
9256
9257 plane_config->fb = intel_fb;
9258 return;
9259
9260 error:
9261 kfree(intel_fb);
9262 }
9263
9264 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9265 struct intel_crtc_state *pipe_config)
9266 {
9267 struct drm_device *dev = crtc->base.dev;
9268 struct drm_i915_private *dev_priv = to_i915(dev);
9269 u32 tmp;
9270
9271 tmp = I915_READ(PF_CTL(crtc->pipe));
9272
9273 if (tmp & PF_ENABLE) {
9274 pipe_config->pch_pfit.enabled = true;
9275 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9276 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9277
9278 /* We currently do not free assignements of panel fitters on
9279 * ivb/hsw (since we don't use the higher upscaling modes which
9280 * differentiates them) so just WARN about this case for now. */
9281 if (IS_GEN(dev_priv, 7)) {
9282 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9283 PF_PIPE_SEL_IVB(crtc->pipe));
9284 }
9285 }
9286 }
9287
9288 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9289 struct intel_crtc_state *pipe_config)
9290 {
9291 struct drm_device *dev = crtc->base.dev;
9292 struct drm_i915_private *dev_priv = to_i915(dev);
9293 enum intel_display_power_domain power_domain;
9294 intel_wakeref_t wakeref;
9295 u32 tmp;
9296 bool ret;
9297
9298 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9299 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
9300 if (!wakeref)
9301 return false;
9302
9303 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
9304 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9305 pipe_config->shared_dpll = NULL;
9306
9307 ret = false;
9308 tmp = I915_READ(PIPECONF(crtc->pipe));
9309 if (!(tmp & PIPECONF_ENABLE))
9310 goto out;
9311
9312 switch (tmp & PIPECONF_BPC_MASK) {
9313 case PIPECONF_6BPC:
9314 pipe_config->pipe_bpp = 18;
9315 break;
9316 case PIPECONF_8BPC:
9317 pipe_config->pipe_bpp = 24;
9318 break;
9319 case PIPECONF_10BPC:
9320 pipe_config->pipe_bpp = 30;
9321 break;
9322 case PIPECONF_12BPC:
9323 pipe_config->pipe_bpp = 36;
9324 break;
9325 default:
9326 break;
9327 }
9328
9329 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9330 pipe_config->limited_color_range = true;
9331
9332 pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_ILK) >>
9333 PIPECONF_GAMMA_MODE_SHIFT;
9334
9335 pipe_config->csc_mode = I915_READ(PIPE_CSC_MODE(crtc->pipe));
9336
9337 i9xx_get_pipe_color_config(pipe_config);
9338
9339 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9340 struct intel_shared_dpll *pll;
9341 enum intel_dpll_id pll_id;
9342
9343 pipe_config->has_pch_encoder = true;
9344
9345 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9346 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9347 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9348
9349 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9350
9351 if (HAS_PCH_IBX(dev_priv)) {
9352 /*
9353 * The pipe->pch transcoder and pch transcoder->pll
9354 * mapping is fixed.
9355 */
9356 pll_id = (enum intel_dpll_id) crtc->pipe;
9357 } else {
9358 tmp = I915_READ(PCH_DPLL_SEL);
9359 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9360 pll_id = DPLL_ID_PCH_PLL_B;
9361 else
9362 pll_id= DPLL_ID_PCH_PLL_A;
9363 }
9364
9365 pipe_config->shared_dpll =
9366 intel_get_shared_dpll_by_id(dev_priv, pll_id);
9367 pll = pipe_config->shared_dpll;
9368
9369 WARN_ON(!pll->info->funcs->get_hw_state(dev_priv, pll,
9370 &pipe_config->dpll_hw_state));
9371
9372 tmp = pipe_config->dpll_hw_state.dpll;
9373 pipe_config->pixel_multiplier =
9374 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9375 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9376
9377 ironlake_pch_clock_get(crtc, pipe_config);
9378 } else {
9379 pipe_config->pixel_multiplier = 1;
9380 }
9381
9382 intel_get_pipe_timings(crtc, pipe_config);
9383 intel_get_pipe_src_size(crtc, pipe_config);
9384
9385 ironlake_get_pfit_config(crtc, pipe_config);
9386
9387 ret = true;
9388
9389 out:
9390 intel_display_power_put(dev_priv, power_domain, wakeref);
9391
9392 return ret;
9393 }
9394
9395 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9396 {
9397 struct drm_device *dev = &dev_priv->drm;
9398 struct intel_crtc *crtc;
9399
9400 for_each_intel_crtc(dev, crtc)
9401 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9402 pipe_name(crtc->pipe));
9403
9404 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_CTL2),
9405 "Display power well on\n");
9406 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9407 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9408 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9409 I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
9410 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9411 "CPU PWM1 enabled\n");
9412 if (IS_HASWELL(dev_priv))
9413 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9414 "CPU PWM2 enabled\n");
9415 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9416 "PCH PWM1 enabled\n");
9417 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9418 "Utility pin enabled\n");
9419 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9420
9421 /*
9422 * In theory we can still leave IRQs enabled, as long as only the HPD
9423 * interrupts remain enabled. We used to check for that, but since it's
9424 * gen-specific and since we only disable LCPLL after we fully disable
9425 * the interrupts, the check below should be enough.
9426 */
9427 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9428 }
9429
9430 static u32 hsw_read_dcomp(struct drm_i915_private *dev_priv)
9431 {
9432 if (IS_HASWELL(dev_priv))
9433 return I915_READ(D_COMP_HSW);
9434 else
9435 return I915_READ(D_COMP_BDW);
9436 }
9437
9438 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, u32 val)
9439 {
9440 if (IS_HASWELL(dev_priv)) {
9441 mutex_lock(&dev_priv->pcu_lock);
9442 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9443 val))
9444 DRM_DEBUG_KMS("Failed to write to D_COMP\n");
9445 mutex_unlock(&dev_priv->pcu_lock);
9446 } else {
9447 I915_WRITE(D_COMP_BDW, val);
9448 POSTING_READ(D_COMP_BDW);
9449 }
9450 }
9451
9452 /*
9453 * This function implements pieces of two sequences from BSpec:
9454 * - Sequence for display software to disable LCPLL
9455 * - Sequence for display software to allow package C8+
9456 * The steps implemented here are just the steps that actually touch the LCPLL
9457 * register. Callers should take care of disabling all the display engine
9458 * functions, doing the mode unset, fixing interrupts, etc.
9459 */
9460 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9461 bool switch_to_fclk, bool allow_power_down)
9462 {
9463 u32 val;
9464
9465 assert_can_disable_lcpll(dev_priv);
9466
9467 val = I915_READ(LCPLL_CTL);
9468
9469 if (switch_to_fclk) {
9470 val |= LCPLL_CD_SOURCE_FCLK;
9471 I915_WRITE(LCPLL_CTL, val);
9472
9473 if (wait_for_us(I915_READ(LCPLL_CTL) &
9474 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9475 DRM_ERROR("Switching to FCLK failed\n");
9476
9477 val = I915_READ(LCPLL_CTL);
9478 }
9479
9480 val |= LCPLL_PLL_DISABLE;
9481 I915_WRITE(LCPLL_CTL, val);
9482 POSTING_READ(LCPLL_CTL);
9483
9484 if (intel_wait_for_register(&dev_priv->uncore,
9485 LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
9486 DRM_ERROR("LCPLL still locked\n");
9487
9488 val = hsw_read_dcomp(dev_priv);
9489 val |= D_COMP_COMP_DISABLE;
9490 hsw_write_dcomp(dev_priv, val);
9491 ndelay(100);
9492
9493 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9494 1))
9495 DRM_ERROR("D_COMP RCOMP still in progress\n");
9496
9497 if (allow_power_down) {
9498 val = I915_READ(LCPLL_CTL);
9499 val |= LCPLL_POWER_DOWN_ALLOW;
9500 I915_WRITE(LCPLL_CTL, val);
9501 POSTING_READ(LCPLL_CTL);
9502 }
9503 }
9504
9505 /*
9506 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9507 * source.
9508 */
9509 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9510 {
9511 u32 val;
9512
9513 val = I915_READ(LCPLL_CTL);
9514
9515 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9516 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9517 return;
9518
9519 /*
9520 * Make sure we're not on PC8 state before disabling PC8, otherwise
9521 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9522 */
9523 intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
9524
9525 if (val & LCPLL_POWER_DOWN_ALLOW) {
9526 val &= ~LCPLL_POWER_DOWN_ALLOW;
9527 I915_WRITE(LCPLL_CTL, val);
9528 POSTING_READ(LCPLL_CTL);
9529 }
9530
9531 val = hsw_read_dcomp(dev_priv);
9532 val |= D_COMP_COMP_FORCE;
9533 val &= ~D_COMP_COMP_DISABLE;
9534 hsw_write_dcomp(dev_priv, val);
9535
9536 val = I915_READ(LCPLL_CTL);
9537 val &= ~LCPLL_PLL_DISABLE;
9538 I915_WRITE(LCPLL_CTL, val);
9539
9540 if (intel_wait_for_register(&dev_priv->uncore,
9541 LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
9542 5))
9543 DRM_ERROR("LCPLL not locked yet\n");
9544
9545 if (val & LCPLL_CD_SOURCE_FCLK) {
9546 val = I915_READ(LCPLL_CTL);
9547 val &= ~LCPLL_CD_SOURCE_FCLK;
9548 I915_WRITE(LCPLL_CTL, val);
9549
9550 if (wait_for_us((I915_READ(LCPLL_CTL) &
9551 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9552 DRM_ERROR("Switching back to LCPLL failed\n");
9553 }
9554
9555 intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
9556
9557 intel_update_cdclk(dev_priv);
9558 intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
9559 }
9560
9561 /*
9562 * Package states C8 and deeper are really deep PC states that can only be
9563 * reached when all the devices on the system allow it, so even if the graphics
9564 * device allows PC8+, it doesn't mean the system will actually get to these
9565 * states. Our driver only allows PC8+ when going into runtime PM.
9566 *
9567 * The requirements for PC8+ are that all the outputs are disabled, the power
9568 * well is disabled and most interrupts are disabled, and these are also
9569 * requirements for runtime PM. When these conditions are met, we manually do
9570 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9571 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9572 * hang the machine.
9573 *
9574 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9575 * the state of some registers, so when we come back from PC8+ we need to
9576 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9577 * need to take care of the registers kept by RC6. Notice that this happens even
9578 * if we don't put the device in PCI D3 state (which is what currently happens
9579 * because of the runtime PM support).
9580 *
9581 * For more, read "Display Sequences for Package C8" on the hardware
9582 * documentation.
9583 */
9584 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9585 {
9586 u32 val;
9587
9588 DRM_DEBUG_KMS("Enabling package C8+\n");
9589
9590 if (HAS_PCH_LPT_LP(dev_priv)) {
9591 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9592 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9593 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9594 }
9595
9596 lpt_disable_clkout_dp(dev_priv);
9597 hsw_disable_lcpll(dev_priv, true, true);
9598 }
9599
9600 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9601 {
9602 u32 val;
9603
9604 DRM_DEBUG_KMS("Disabling package C8+\n");
9605
9606 hsw_restore_lcpll(dev_priv);
9607 lpt_init_pch_refclk(dev_priv);
9608
9609 if (HAS_PCH_LPT_LP(dev_priv)) {
9610 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9611 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9612 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9613 }
9614 }
9615
9616 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9617 struct intel_crtc_state *crtc_state)
9618 {
9619 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9620 struct intel_atomic_state *state =
9621 to_intel_atomic_state(crtc_state->base.state);
9622
9623 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) ||
9624 INTEL_GEN(dev_priv) >= 11) {
9625 struct intel_encoder *encoder =
9626 intel_get_crtc_new_encoder(state, crtc_state);
9627
9628 if (!intel_get_shared_dpll(crtc_state, encoder)) {
9629 DRM_DEBUG_KMS("failed to find PLL for pipe %c\n",
9630 pipe_name(crtc->pipe));
9631 return -EINVAL;
9632 }
9633 }
9634
9635 return 0;
9636 }
9637
9638 static void cannonlake_get_ddi_pll(struct drm_i915_private *dev_priv,
9639 enum port port,
9640 struct intel_crtc_state *pipe_config)
9641 {
9642 enum intel_dpll_id id;
9643 u32 temp;
9644
9645 temp = I915_READ(DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
9646 id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
9647
9648 if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL2))
9649 return;
9650
9651 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9652 }
9653
9654 static void icelake_get_ddi_pll(struct drm_i915_private *dev_priv,
9655 enum port port,
9656 struct intel_crtc_state *pipe_config)
9657 {
9658 enum intel_dpll_id id;
9659 u32 temp;
9660
9661 /* TODO: TBT pll not implemented. */
9662 if (intel_port_is_combophy(dev_priv, port)) {
9663 temp = I915_READ(DPCLKA_CFGCR0_ICL) &
9664 DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
9665 id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
9666 } else if (intel_port_is_tc(dev_priv, port)) {
9667 id = icl_tc_port_to_pll_id(intel_port_to_tc(dev_priv, port));
9668 } else {
9669 WARN(1, "Invalid port %x\n", port);
9670 return;
9671 }
9672
9673 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9674 }
9675
9676 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9677 enum port port,
9678 struct intel_crtc_state *pipe_config)
9679 {
9680 enum intel_dpll_id id;
9681
9682 switch (port) {
9683 case PORT_A:
9684 id = DPLL_ID_SKL_DPLL0;
9685 break;
9686 case PORT_B:
9687 id = DPLL_ID_SKL_DPLL1;
9688 break;
9689 case PORT_C:
9690 id = DPLL_ID_SKL_DPLL2;
9691 break;
9692 default:
9693 DRM_ERROR("Incorrect port type\n");
9694 return;
9695 }
9696
9697 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9698 }
9699
9700 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9701 enum port port,
9702 struct intel_crtc_state *pipe_config)
9703 {
9704 enum intel_dpll_id id;
9705 u32 temp;
9706
9707 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9708 id = temp >> (port * 3 + 1);
9709
9710 if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))
9711 return;
9712
9713 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9714 }
9715
9716 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9717 enum port port,
9718 struct intel_crtc_state *pipe_config)
9719 {
9720 enum intel_dpll_id id;
9721 u32 ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9722
9723 switch (ddi_pll_sel) {
9724 case PORT_CLK_SEL_WRPLL1:
9725 id = DPLL_ID_WRPLL1;
9726 break;
9727 case PORT_CLK_SEL_WRPLL2:
9728 id = DPLL_ID_WRPLL2;
9729 break;
9730 case PORT_CLK_SEL_SPLL:
9731 id = DPLL_ID_SPLL;
9732 break;
9733 case PORT_CLK_SEL_LCPLL_810:
9734 id = DPLL_ID_LCPLL_810;
9735 break;
9736 case PORT_CLK_SEL_LCPLL_1350:
9737 id = DPLL_ID_LCPLL_1350;
9738 break;
9739 case PORT_CLK_SEL_LCPLL_2700:
9740 id = DPLL_ID_LCPLL_2700;
9741 break;
9742 default:
9743 MISSING_CASE(ddi_pll_sel);
9744 /* fall through */
9745 case PORT_CLK_SEL_NONE:
9746 return;
9747 }
9748
9749 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9750 }
9751
9752 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
9753 struct intel_crtc_state *pipe_config,
9754 u64 *power_domain_mask,
9755 intel_wakeref_t *wakerefs)
9756 {
9757 struct drm_device *dev = crtc->base.dev;
9758 struct drm_i915_private *dev_priv = to_i915(dev);
9759 enum intel_display_power_domain power_domain;
9760 unsigned long panel_transcoder_mask = 0;
9761 unsigned long enabled_panel_transcoders = 0;
9762 enum transcoder panel_transcoder;
9763 intel_wakeref_t wf;
9764 u32 tmp;
9765
9766 if (INTEL_GEN(dev_priv) >= 11)
9767 panel_transcoder_mask |=
9768 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1);
9769
9770 if (HAS_TRANSCODER_EDP(dev_priv))
9771 panel_transcoder_mask |= BIT(TRANSCODER_EDP);
9772
9773 /*
9774 * The pipe->transcoder mapping is fixed with the exception of the eDP
9775 * and DSI transcoders handled below.
9776 */
9777 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9778
9779 /*
9780 * XXX: Do intel_display_power_get_if_enabled before reading this (for
9781 * consistency and less surprising code; it's in always on power).
9782 */
9783 for_each_set_bit(panel_transcoder,
9784 &panel_transcoder_mask,
9785 ARRAY_SIZE(INTEL_INFO(dev_priv)->trans_offsets)) {
9786 enum pipe trans_pipe;
9787
9788 tmp = I915_READ(TRANS_DDI_FUNC_CTL(panel_transcoder));
9789 if (!(tmp & TRANS_DDI_FUNC_ENABLE))
9790 continue;
9791
9792 /*
9793 * Log all enabled ones, only use the first one.
9794 *
9795 * FIXME: This won't work for two separate DSI displays.
9796 */
9797 enabled_panel_transcoders |= BIT(panel_transcoder);
9798 if (enabled_panel_transcoders != BIT(panel_transcoder))
9799 continue;
9800
9801 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9802 default:
9803 WARN(1, "unknown pipe linked to transcoder %s\n",
9804 transcoder_name(panel_transcoder));
9805 /* fall through */
9806 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9807 case TRANS_DDI_EDP_INPUT_A_ON:
9808 trans_pipe = PIPE_A;
9809 break;
9810 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9811 trans_pipe = PIPE_B;
9812 break;
9813 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9814 trans_pipe = PIPE_C;
9815 break;
9816 }
9817
9818 if (trans_pipe == crtc->pipe)
9819 pipe_config->cpu_transcoder = panel_transcoder;
9820 }
9821
9822 /*
9823 * Valid combos: none, eDP, DSI0, DSI1, DSI0+DSI1
9824 */
9825 WARN_ON((enabled_panel_transcoders & BIT(TRANSCODER_EDP)) &&
9826 enabled_panel_transcoders != BIT(TRANSCODER_EDP));
9827
9828 power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
9829 WARN_ON(*power_domain_mask & BIT_ULL(power_domain));
9830
9831 wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
9832 if (!wf)
9833 return false;
9834
9835 wakerefs[power_domain] = wf;
9836 *power_domain_mask |= BIT_ULL(power_domain);
9837
9838 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9839
9840 return tmp & PIPECONF_ENABLE;
9841 }
9842
9843 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
9844 struct intel_crtc_state *pipe_config,
9845 u64 *power_domain_mask,
9846 intel_wakeref_t *wakerefs)
9847 {
9848 struct drm_device *dev = crtc->base.dev;
9849 struct drm_i915_private *dev_priv = to_i915(dev);
9850 enum intel_display_power_domain power_domain;
9851 enum transcoder cpu_transcoder;
9852 intel_wakeref_t wf;
9853 enum port port;
9854 u32 tmp;
9855
9856 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
9857 if (port == PORT_A)
9858 cpu_transcoder = TRANSCODER_DSI_A;
9859 else
9860 cpu_transcoder = TRANSCODER_DSI_C;
9861
9862 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
9863 WARN_ON(*power_domain_mask & BIT_ULL(power_domain));
9864
9865 wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
9866 if (!wf)
9867 continue;
9868
9869 wakerefs[power_domain] = wf;
9870 *power_domain_mask |= BIT_ULL(power_domain);
9871
9872 /*
9873 * The PLL needs to be enabled with a valid divider
9874 * configuration, otherwise accessing DSI registers will hang
9875 * the machine. See BSpec North Display Engine
9876 * registers/MIPI[BXT]. We can break out here early, since we
9877 * need the same DSI PLL to be enabled for both DSI ports.
9878 */
9879 if (!bxt_dsi_pll_is_enabled(dev_priv))
9880 break;
9881
9882 /* XXX: this works for video mode only */
9883 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
9884 if (!(tmp & DPI_ENABLE))
9885 continue;
9886
9887 tmp = I915_READ(MIPI_CTRL(port));
9888 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
9889 continue;
9890
9891 pipe_config->cpu_transcoder = cpu_transcoder;
9892 break;
9893 }
9894
9895 return transcoder_is_dsi(pipe_config->cpu_transcoder);
9896 }
9897
9898 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9899 struct intel_crtc_state *pipe_config)
9900 {
9901 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9902 struct intel_shared_dpll *pll;
9903 enum port port;
9904 u32 tmp;
9905
9906 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9907
9908 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9909
9910 if (INTEL_GEN(dev_priv) >= 11)
9911 icelake_get_ddi_pll(dev_priv, port, pipe_config);
9912 else if (IS_CANNONLAKE(dev_priv))
9913 cannonlake_get_ddi_pll(dev_priv, port, pipe_config);
9914 else if (IS_GEN9_BC(dev_priv))
9915 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9916 else if (IS_GEN9_LP(dev_priv))
9917 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9918 else
9919 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9920
9921 pll = pipe_config->shared_dpll;
9922 if (pll) {
9923 WARN_ON(!pll->info->funcs->get_hw_state(dev_priv, pll,
9924 &pipe_config->dpll_hw_state));
9925 }
9926
9927 /*
9928 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9929 * DDI E. So just check whether this pipe is wired to DDI E and whether
9930 * the PCH transcoder is on.
9931 */
9932 if (INTEL_GEN(dev_priv) < 9 &&
9933 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9934 pipe_config->has_pch_encoder = true;
9935
9936 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9937 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9938 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9939
9940 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9941 }
9942 }
9943
9944 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9945 struct intel_crtc_state *pipe_config)
9946 {
9947 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9948 intel_wakeref_t wakerefs[POWER_DOMAIN_NUM], wf;
9949 enum intel_display_power_domain power_domain;
9950 u64 power_domain_mask;
9951 bool active;
9952
9953 intel_crtc_init_scalers(crtc, pipe_config);
9954
9955 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9956 wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
9957 if (!wf)
9958 return false;
9959
9960 wakerefs[power_domain] = wf;
9961 power_domain_mask = BIT_ULL(power_domain);
9962
9963 pipe_config->shared_dpll = NULL;
9964
9965 active = hsw_get_transcoder_state(crtc, pipe_config,
9966 &power_domain_mask, wakerefs);
9967
9968 if (IS_GEN9_LP(dev_priv) &&
9969 bxt_get_dsi_transcoder_state(crtc, pipe_config,
9970 &power_domain_mask, wakerefs)) {
9971 WARN_ON(active);
9972 active = true;
9973 }
9974
9975 if (!active)
9976 goto out;
9977
9978 if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
9979 INTEL_GEN(dev_priv) >= 11) {
9980 haswell_get_ddi_port_state(crtc, pipe_config);
9981 intel_get_pipe_timings(crtc, pipe_config);
9982 }
9983
9984 intel_get_pipe_src_size(crtc, pipe_config);
9985 intel_get_crtc_ycbcr_config(crtc, pipe_config);
9986
9987 pipe_config->gamma_mode = I915_READ(GAMMA_MODE(crtc->pipe));
9988
9989 pipe_config->csc_mode = I915_READ(PIPE_CSC_MODE(crtc->pipe));
9990
9991 if (INTEL_GEN(dev_priv) >= 9) {
9992 u32 tmp = I915_READ(SKL_BOTTOM_COLOR(crtc->pipe));
9993
9994 if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE)
9995 pipe_config->gamma_enable = true;
9996
9997 if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE)
9998 pipe_config->csc_enable = true;
9999 } else {
10000 i9xx_get_pipe_color_config(pipe_config);
10001 }
10002
10003 power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
10004 WARN_ON(power_domain_mask & BIT_ULL(power_domain));
10005
10006 wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
10007 if (wf) {
10008 wakerefs[power_domain] = wf;
10009 power_domain_mask |= BIT_ULL(power_domain);
10010
10011 if (INTEL_GEN(dev_priv) >= 9)
10012 skylake_get_pfit_config(crtc, pipe_config);
10013 else
10014 ironlake_get_pfit_config(crtc, pipe_config);
10015 }
10016
10017 if (hsw_crtc_supports_ips(crtc)) {
10018 if (IS_HASWELL(dev_priv))
10019 pipe_config->ips_enabled = I915_READ(IPS_CTL) & IPS_ENABLE;
10020 else {
10021 /*
10022 * We cannot readout IPS state on broadwell, set to
10023 * true so we can set it to a defined state on first
10024 * commit.
10025 */
10026 pipe_config->ips_enabled = true;
10027 }
10028 }
10029
10030 if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
10031 !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10032 pipe_config->pixel_multiplier =
10033 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10034 } else {
10035 pipe_config->pixel_multiplier = 1;
10036 }
10037
10038 out:
10039 for_each_power_domain(power_domain, power_domain_mask)
10040 intel_display_power_put(dev_priv,
10041 power_domain, wakerefs[power_domain]);
10042
10043 return active;
10044 }
10045
10046 static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
10047 {
10048 struct drm_i915_private *dev_priv =
10049 to_i915(plane_state->base.plane->dev);
10050 const struct drm_framebuffer *fb = plane_state->base.fb;
10051 const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10052 u32 base;
10053
10054 if (INTEL_INFO(dev_priv)->display.cursor_needs_physical)
10055 base = obj->phys_handle->busaddr;
10056 else
10057 base = intel_plane_ggtt_offset(plane_state);
10058
10059 base += plane_state->color_plane[0].offset;
10060
10061 /* ILK+ do this automagically */
10062 if (HAS_GMCH(dev_priv) &&
10063 plane_state->base.rotation & DRM_MODE_ROTATE_180)
10064 base += (plane_state->base.crtc_h *
10065 plane_state->base.crtc_w - 1) * fb->format->cpp[0];
10066
10067 return base;
10068 }
10069
10070 static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
10071 {
10072 int x = plane_state->base.crtc_x;
10073 int y = plane_state->base.crtc_y;
10074 u32 pos = 0;
10075
10076 if (x < 0) {
10077 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10078 x = -x;
10079 }
10080 pos |= x << CURSOR_X_SHIFT;
10081
10082 if (y < 0) {
10083 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10084 y = -y;
10085 }
10086 pos |= y << CURSOR_Y_SHIFT;
10087
10088 return pos;
10089 }
10090
10091 static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
10092 {
10093 const struct drm_mode_config *config =
10094 &plane_state->base.plane->dev->mode_config;
10095 int width = plane_state->base.crtc_w;
10096 int height = plane_state->base.crtc_h;
10097
10098 return width > 0 && width <= config->cursor_width &&
10099 height > 0 && height <= config->cursor_height;
10100 }
10101
10102 static int intel_cursor_check_surface(struct intel_plane_state *plane_state)
10103 {
10104 const struct drm_framebuffer *fb = plane_state->base.fb;
10105 unsigned int rotation = plane_state->base.rotation;
10106 int src_x, src_y;
10107 u32 offset;
10108 int ret;
10109
10110 intel_fill_fb_ggtt_view(&plane_state->view, fb, rotation);
10111 plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0, rotation);
10112
10113 ret = intel_plane_check_stride(plane_state);
10114 if (ret)
10115 return ret;
10116
10117 src_x = plane_state->base.src_x >> 16;
10118 src_y = plane_state->base.src_y >> 16;
10119
10120 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
10121 offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
10122 plane_state, 0);
10123
10124 if (src_x != 0 || src_y != 0) {
10125 DRM_DEBUG_KMS("Arbitrary cursor panning not supported\n");
10126 return -EINVAL;
10127 }
10128
10129 plane_state->color_plane[0].offset = offset;
10130
10131 return 0;
10132 }
10133
10134 static int intel_check_cursor(struct intel_crtc_state *crtc_state,
10135 struct intel_plane_state *plane_state)
10136 {
10137 const struct drm_framebuffer *fb = plane_state->base.fb;
10138 int ret;
10139
10140 if (fb && fb->modifier != DRM_FORMAT_MOD_LINEAR) {
10141 DRM_DEBUG_KMS("cursor cannot be tiled\n");
10142 return -EINVAL;
10143 }
10144
10145 ret = drm_atomic_helper_check_plane_state(&plane_state->base,
10146 &crtc_state->base,
10147 DRM_PLANE_HELPER_NO_SCALING,
10148 DRM_PLANE_HELPER_NO_SCALING,
10149 true, true);
10150 if (ret)
10151 return ret;
10152
10153 if (!plane_state->base.visible)
10154 return 0;
10155
10156 ret = intel_plane_check_src_coordinates(plane_state);
10157 if (ret)
10158 return ret;
10159
10160 ret = intel_cursor_check_surface(plane_state);
10161 if (ret)
10162 return ret;
10163
10164 return 0;
10165 }
10166
10167 static unsigned int
10168 i845_cursor_max_stride(struct intel_plane *plane,
10169 u32 pixel_format, u64 modifier,
10170 unsigned int rotation)
10171 {
10172 return 2048;
10173 }
10174
10175 static u32 i845_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
10176 {
10177 u32 cntl = 0;
10178
10179 if (crtc_state->gamma_enable)
10180 cntl |= CURSOR_GAMMA_ENABLE;
10181
10182 return cntl;
10183 }
10184
10185 static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
10186 const struct intel_plane_state *plane_state)
10187 {
10188 return CURSOR_ENABLE |
10189 CURSOR_FORMAT_ARGB |
10190 CURSOR_STRIDE(plane_state->color_plane[0].stride);
10191 }
10192
10193 static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
10194 {
10195 int width = plane_state->base.crtc_w;
10196
10197 /*
10198 * 845g/865g are only limited by the width of their cursors,
10199 * the height is arbitrary up to the precision of the register.
10200 */
10201 return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64);
10202 }
10203
10204 static int i845_check_cursor(struct intel_crtc_state *crtc_state,
10205 struct intel_plane_state *plane_state)
10206 {
10207 const struct drm_framebuffer *fb = plane_state->base.fb;
10208 int ret;
10209
10210 ret = intel_check_cursor(crtc_state, plane_state);
10211 if (ret)
10212 return ret;
10213
10214 /* if we want to turn off the cursor ignore width and height */
10215 if (!fb)
10216 return 0;
10217
10218 /* Check for which cursor types we support */
10219 if (!i845_cursor_size_ok(plane_state)) {
10220 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
10221 plane_state->base.crtc_w,
10222 plane_state->base.crtc_h);
10223 return -EINVAL;
10224 }
10225
10226 WARN_ON(plane_state->base.visible &&
10227 plane_state->color_plane[0].stride != fb->pitches[0]);
10228
10229 switch (fb->pitches[0]) {
10230 case 256:
10231 case 512:
10232 case 1024:
10233 case 2048:
10234 break;
10235 default:
10236 DRM_DEBUG_KMS("Invalid cursor stride (%u)\n",
10237 fb->pitches[0]);
10238 return -EINVAL;
10239 }
10240
10241 plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state);
10242
10243 return 0;
10244 }
10245
10246 static void i845_update_cursor(struct intel_plane *plane,
10247 const struct intel_crtc_state *crtc_state,
10248 const struct intel_plane_state *plane_state)
10249 {
10250 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
10251 u32 cntl = 0, base = 0, pos = 0, size = 0;
10252 unsigned long irqflags;
10253
10254 if (plane_state && plane_state->base.visible) {
10255 unsigned int width = plane_state->base.crtc_w;
10256 unsigned int height = plane_state->base.crtc_h;
10257
10258 cntl = plane_state->ctl |
10259 i845_cursor_ctl_crtc(crtc_state);
10260
10261 size = (height << 12) | width;
10262
10263 base = intel_cursor_base(plane_state);
10264 pos = intel_cursor_position(plane_state);
10265 }
10266
10267 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
10268
10269 /* On these chipsets we can only modify the base/size/stride
10270 * whilst the cursor is disabled.
10271 */
10272 if (plane->cursor.base != base ||
10273 plane->cursor.size != size ||
10274 plane->cursor.cntl != cntl) {
10275 I915_WRITE_FW(CURCNTR(PIPE_A), 0);
10276 I915_WRITE_FW(CURBASE(PIPE_A), base);
10277 I915_WRITE_FW(CURSIZE, size);
10278 I915_WRITE_FW(CURPOS(PIPE_A), pos);
10279 I915_WRITE_FW(CURCNTR(PIPE_A), cntl);
10280
10281 plane->cursor.base = base;
10282 plane->cursor.size = size;
10283 plane->cursor.cntl = cntl;
10284 } else {
10285 I915_WRITE_FW(CURPOS(PIPE_A), pos);
10286 }
10287
10288 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
10289 }
10290
10291 static void i845_disable_cursor(struct intel_plane *plane,
10292 const struct intel_crtc_state *crtc_state)
10293 {
10294 i845_update_cursor(plane, crtc_state, NULL);
10295 }
10296
10297 static bool i845_cursor_get_hw_state(struct intel_plane *plane,
10298 enum pipe *pipe)
10299 {
10300 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
10301 enum intel_display_power_domain power_domain;
10302 intel_wakeref_t wakeref;
10303 bool ret;
10304
10305 power_domain = POWER_DOMAIN_PIPE(PIPE_A);
10306 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
10307 if (!wakeref)
10308 return false;
10309
10310 ret = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
10311
10312 *pipe = PIPE_A;
10313
10314 intel_display_power_put(dev_priv, power_domain, wakeref);
10315
10316 return ret;
10317 }
10318
10319 static unsigned int
10320 i9xx_cursor_max_stride(struct intel_plane *plane,
10321 u32 pixel_format, u64 modifier,
10322 unsigned int rotation)
10323 {
10324 return plane->base.dev->mode_config.cursor_width * 4;
10325 }
10326
10327 static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
10328 {
10329 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
10330 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10331 u32 cntl = 0;
10332
10333 if (INTEL_GEN(dev_priv) >= 11)
10334 return cntl;
10335
10336 if (crtc_state->gamma_enable)
10337 cntl = MCURSOR_GAMMA_ENABLE;
10338
10339 if (crtc_state->csc_enable)
10340 cntl |= MCURSOR_PIPE_CSC_ENABLE;
10341
10342 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
10343 cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
10344
10345 return cntl;
10346 }
10347
10348 static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
10349 const struct intel_plane_state *plane_state)
10350 {
10351 struct drm_i915_private *dev_priv =
10352 to_i915(plane_state->base.plane->dev);
10353 u32 cntl = 0;
10354
10355 if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
10356 cntl |= MCURSOR_TRICKLE_FEED_DISABLE;
10357
10358 switch (plane_state->base.crtc_w) {
10359 case 64:
10360 cntl |= MCURSOR_MODE_64_ARGB_AX;
10361 break;
10362 case 128:
10363 cntl |= MCURSOR_MODE_128_ARGB_AX;
10364 break;
10365 case 256:
10366 cntl |= MCURSOR_MODE_256_ARGB_AX;
10367 break;
10368 default:
10369 MISSING_CASE(plane_state->base.crtc_w);
10370 return 0;
10371 }
10372
10373 if (plane_state->base.rotation & DRM_MODE_ROTATE_180)
10374 cntl |= MCURSOR_ROTATE_180;
10375
10376 return cntl;
10377 }
10378
10379 static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
10380 {
10381 struct drm_i915_private *dev_priv =
10382 to_i915(plane_state->base.plane->dev);
10383 int width = plane_state->base.crtc_w;
10384 int height = plane_state->base.crtc_h;
10385
10386 if (!intel_cursor_size_ok(plane_state))
10387 return false;
10388
10389 /* Cursor width is limited to a few power-of-two sizes */
10390 switch (width) {
10391 case 256:
10392 case 128:
10393 case 64:
10394 break;
10395 default:
10396 return false;
10397 }
10398
10399 /*
10400 * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor
10401 * height from 8 lines up to the cursor width, when the
10402 * cursor is not rotated. Everything else requires square
10403 * cursors.
10404 */
10405 if (HAS_CUR_FBC(dev_priv) &&
10406 plane_state->base.rotation & DRM_MODE_ROTATE_0) {
10407 if (height < 8 || height > width)
10408 return false;
10409 } else {
10410 if (height != width)
10411 return false;
10412 }
10413
10414 return true;
10415 }
10416
10417 static int i9xx_check_cursor(struct intel_crtc_state *crtc_state,
10418 struct intel_plane_state *plane_state)
10419 {
10420 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
10421 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
10422 const struct drm_framebuffer *fb = plane_state->base.fb;
10423 enum pipe pipe = plane->pipe;
10424 int ret;
10425
10426 ret = intel_check_cursor(crtc_state, plane_state);
10427 if (ret)
10428 return ret;
10429
10430 /* if we want to turn off the cursor ignore width and height */
10431 if (!fb)
10432 return 0;
10433
10434 /* Check for which cursor types we support */
10435 if (!i9xx_cursor_size_ok(plane_state)) {
10436 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
10437 plane_state->base.crtc_w,
10438 plane_state->base.crtc_h);
10439 return -EINVAL;
10440 }
10441
10442 WARN_ON(plane_state->base.visible &&
10443 plane_state->color_plane[0].stride != fb->pitches[0]);
10444
10445 if (fb->pitches[0] != plane_state->base.crtc_w * fb->format->cpp[0]) {
10446 DRM_DEBUG_KMS("Invalid cursor stride (%u) (cursor width %d)\n",
10447 fb->pitches[0], plane_state->base.crtc_w);
10448 return -EINVAL;
10449 }
10450
10451 /*
10452 * There's something wrong with the cursor on CHV pipe C.
10453 * If it straddles the left edge of the screen then
10454 * moving it away from the edge or disabling it often
10455 * results in a pipe underrun, and often that can lead to
10456 * dead pipe (constant underrun reported, and it scans
10457 * out just a solid color). To recover from that, the
10458 * display power well must be turned off and on again.
10459 * Refuse the put the cursor into that compromised position.
10460 */
10461 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
10462 plane_state->base.visible && plane_state->base.crtc_x < 0) {
10463 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
10464 return -EINVAL;
10465 }
10466
10467 plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state);
10468
10469 return 0;
10470 }
10471
10472 static void i9xx_update_cursor(struct intel_plane *plane,
10473 const struct intel_crtc_state *crtc_state,
10474 const struct intel_plane_state *plane_state)
10475 {
10476 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
10477 enum pipe pipe = plane->pipe;
10478 u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0;
10479 unsigned long irqflags;
10480
10481 if (plane_state && plane_state->base.visible) {
10482 cntl = plane_state->ctl |
10483 i9xx_cursor_ctl_crtc(crtc_state);
10484
10485 if (plane_state->base.crtc_h != plane_state->base.crtc_w)
10486 fbc_ctl = CUR_FBC_CTL_EN | (plane_state->base.crtc_h - 1);
10487
10488 base = intel_cursor_base(plane_state);
10489 pos = intel_cursor_position(plane_state);
10490 }
10491
10492 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
10493
10494 /*
10495 * On some platforms writing CURCNTR first will also
10496 * cause CURPOS to be armed by the CURBASE write.
10497 * Without the CURCNTR write the CURPOS write would
10498 * arm itself. Thus we always update CURCNTR before
10499 * CURPOS.
10500 *
10501 * On other platforms CURPOS always requires the
10502 * CURBASE write to arm the update. Additonally
10503 * a write to any of the cursor register will cancel
10504 * an already armed cursor update. Thus leaving out
10505 * the CURBASE write after CURPOS could lead to a
10506 * cursor that doesn't appear to move, or even change
10507 * shape. Thus we always write CURBASE.
10508 *
10509 * The other registers are armed by by the CURBASE write
10510 * except when the plane is getting enabled at which time
10511 * the CURCNTR write arms the update.
10512 */
10513
10514 if (INTEL_GEN(dev_priv) >= 9)
10515 skl_write_cursor_wm(plane, crtc_state);
10516
10517 if (plane->cursor.base != base ||
10518 plane->cursor.size != fbc_ctl ||
10519 plane->cursor.cntl != cntl) {
10520 if (HAS_CUR_FBC(dev_priv))
10521 I915_WRITE_FW(CUR_FBC_CTL(pipe), fbc_ctl);
10522 I915_WRITE_FW(CURCNTR(pipe), cntl);
10523 I915_WRITE_FW(CURPOS(pipe), pos);
10524 I915_WRITE_FW(CURBASE(pipe), base);
10525
10526 plane->cursor.base = base;
10527 plane->cursor.size = fbc_ctl;
10528 plane->cursor.cntl = cntl;
10529 } else {
10530 I915_WRITE_FW(CURPOS(pipe), pos);
10531 I915_WRITE_FW(CURBASE(pipe), base);
10532 }
10533
10534 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
10535 }
10536
10537 static void i9xx_disable_cursor(struct intel_plane *plane,
10538 const struct intel_crtc_state *crtc_state)
10539 {
10540 i9xx_update_cursor(plane, crtc_state, NULL);
10541 }
10542
10543 static bool i9xx_cursor_get_hw_state(struct intel_plane *plane,
10544 enum pipe *pipe)
10545 {
10546 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
10547 enum intel_display_power_domain power_domain;
10548 intel_wakeref_t wakeref;
10549 bool ret;
10550 u32 val;
10551
10552 /*
10553 * Not 100% correct for planes that can move between pipes,
10554 * but that's only the case for gen2-3 which don't have any
10555 * display power wells.
10556 */
10557 power_domain = POWER_DOMAIN_PIPE(plane->pipe);
10558 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
10559 if (!wakeref)
10560 return false;
10561
10562 val = I915_READ(CURCNTR(plane->pipe));
10563
10564 ret = val & MCURSOR_MODE;
10565
10566 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
10567 *pipe = plane->pipe;
10568 else
10569 *pipe = (val & MCURSOR_PIPE_SELECT_MASK) >>
10570 MCURSOR_PIPE_SELECT_SHIFT;
10571
10572 intel_display_power_put(dev_priv, power_domain, wakeref);
10573
10574 return ret;
10575 }
10576
10577 /* VESA 640x480x72Hz mode to set on the pipe */
10578 static const struct drm_display_mode load_detect_mode = {
10579 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10580 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10581 };
10582
10583 struct drm_framebuffer *
10584 intel_framebuffer_create(struct drm_i915_gem_object *obj,
10585 struct drm_mode_fb_cmd2 *mode_cmd)
10586 {
10587 struct intel_framebuffer *intel_fb;
10588 int ret;
10589
10590 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10591 if (!intel_fb)
10592 return ERR_PTR(-ENOMEM);
10593
10594 ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
10595 if (ret)
10596 goto err;
10597
10598 return &intel_fb->base;
10599
10600 err:
10601 kfree(intel_fb);
10602 return ERR_PTR(ret);
10603 }
10604
10605 static int intel_modeset_disable_planes(struct drm_atomic_state *state,
10606 struct drm_crtc *crtc)
10607 {
10608 struct drm_plane *plane;
10609 struct drm_plane_state *plane_state;
10610 int ret, i;
10611
10612 ret = drm_atomic_add_affected_planes(state, crtc);
10613 if (ret)
10614 return ret;
10615
10616 for_each_new_plane_in_state(state, plane, plane_state, i) {
10617 if (plane_state->crtc != crtc)
10618 continue;
10619
10620 ret = drm_atomic_set_crtc_for_plane(plane_state, NULL);
10621 if (ret)
10622 return ret;
10623
10624 drm_atomic_set_fb_for_plane(plane_state, NULL);
10625 }
10626
10627 return 0;
10628 }
10629
10630 int intel_get_load_detect_pipe(struct drm_connector *connector,
10631 const struct drm_display_mode *mode,
10632 struct intel_load_detect_pipe *old,
10633 struct drm_modeset_acquire_ctx *ctx)
10634 {
10635 struct intel_crtc *intel_crtc;
10636 struct intel_encoder *intel_encoder =
10637 intel_attached_encoder(connector);
10638 struct drm_crtc *possible_crtc;
10639 struct drm_encoder *encoder = &intel_encoder->base;
10640 struct drm_crtc *crtc = NULL;
10641 struct drm_device *dev = encoder->dev;
10642 struct drm_i915_private *dev_priv = to_i915(dev);
10643 struct drm_mode_config *config = &dev->mode_config;
10644 struct drm_atomic_state *state = NULL, *restore_state = NULL;
10645 struct drm_connector_state *connector_state;
10646 struct intel_crtc_state *crtc_state;
10647 int ret, i = -1;
10648
10649 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10650 connector->base.id, connector->name,
10651 encoder->base.id, encoder->name);
10652
10653 old->restore_state = NULL;
10654
10655 WARN_ON(!drm_modeset_is_locked(&config->connection_mutex));
10656
10657 /*
10658 * Algorithm gets a little messy:
10659 *
10660 * - if the connector already has an assigned crtc, use it (but make
10661 * sure it's on first)
10662 *
10663 * - try to find the first unused crtc that can drive this connector,
10664 * and use that if we find one
10665 */
10666
10667 /* See if we already have a CRTC for this connector */
10668 if (connector->state->crtc) {
10669 crtc = connector->state->crtc;
10670
10671 ret = drm_modeset_lock(&crtc->mutex, ctx);
10672 if (ret)
10673 goto fail;
10674
10675 /* Make sure the crtc and connector are running */
10676 goto found;
10677 }
10678
10679 /* Find an unused one (if possible) */
10680 for_each_crtc(dev, possible_crtc) {
10681 i++;
10682 if (!(encoder->possible_crtcs & (1 << i)))
10683 continue;
10684
10685 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
10686 if (ret)
10687 goto fail;
10688
10689 if (possible_crtc->state->enable) {
10690 drm_modeset_unlock(&possible_crtc->mutex);
10691 continue;
10692 }
10693
10694 crtc = possible_crtc;
10695 break;
10696 }
10697
10698 /*
10699 * If we didn't find an unused CRTC, don't use any.
10700 */
10701 if (!crtc) {
10702 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10703 ret = -ENODEV;
10704 goto fail;
10705 }
10706
10707 found:
10708 intel_crtc = to_intel_crtc(crtc);
10709
10710 state = drm_atomic_state_alloc(dev);
10711 restore_state = drm_atomic_state_alloc(dev);
10712 if (!state || !restore_state) {
10713 ret = -ENOMEM;
10714 goto fail;
10715 }
10716
10717 state->acquire_ctx = ctx;
10718 restore_state->acquire_ctx = ctx;
10719
10720 connector_state = drm_atomic_get_connector_state(state, connector);
10721 if (IS_ERR(connector_state)) {
10722 ret = PTR_ERR(connector_state);
10723 goto fail;
10724 }
10725
10726 ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
10727 if (ret)
10728 goto fail;
10729
10730 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10731 if (IS_ERR(crtc_state)) {
10732 ret = PTR_ERR(crtc_state);
10733 goto fail;
10734 }
10735
10736 crtc_state->base.active = crtc_state->base.enable = true;
10737
10738 if (!mode)
10739 mode = &load_detect_mode;
10740
10741 ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
10742 if (ret)
10743 goto fail;
10744
10745 ret = intel_modeset_disable_planes(state, crtc);
10746 if (ret)
10747 goto fail;
10748
10749 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
10750 if (!ret)
10751 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
10752 if (!ret)
10753 ret = drm_atomic_add_affected_planes(restore_state, crtc);
10754 if (ret) {
10755 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
10756 goto fail;
10757 }
10758
10759 ret = drm_atomic_commit(state);
10760 if (ret) {
10761 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10762 goto fail;
10763 }
10764
10765 old->restore_state = restore_state;
10766 drm_atomic_state_put(state);
10767
10768 /* let the connector get through one full cycle before testing */
10769 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
10770 return true;
10771
10772 fail:
10773 if (state) {
10774 drm_atomic_state_put(state);
10775 state = NULL;
10776 }
10777 if (restore_state) {
10778 drm_atomic_state_put(restore_state);
10779 restore_state = NULL;
10780 }
10781
10782 if (ret == -EDEADLK)
10783 return ret;
10784
10785 return false;
10786 }
10787
10788 void intel_release_load_detect_pipe(struct drm_connector *connector,
10789 struct intel_load_detect_pipe *old,
10790 struct drm_modeset_acquire_ctx *ctx)
10791 {
10792 struct intel_encoder *intel_encoder =
10793 intel_attached_encoder(connector);
10794 struct drm_encoder *encoder = &intel_encoder->base;
10795 struct drm_atomic_state *state = old->restore_state;
10796 int ret;
10797
10798 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10799 connector->base.id, connector->name,
10800 encoder->base.id, encoder->name);
10801
10802 if (!state)
10803 return;
10804
10805 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
10806 if (ret)
10807 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
10808 drm_atomic_state_put(state);
10809 }
10810
10811 static int i9xx_pll_refclk(struct drm_device *dev,
10812 const struct intel_crtc_state *pipe_config)
10813 {
10814 struct drm_i915_private *dev_priv = to_i915(dev);
10815 u32 dpll = pipe_config->dpll_hw_state.dpll;
10816
10817 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10818 return dev_priv->vbt.lvds_ssc_freq;
10819 else if (HAS_PCH_SPLIT(dev_priv))
10820 return 120000;
10821 else if (!IS_GEN(dev_priv, 2))
10822 return 96000;
10823 else
10824 return 48000;
10825 }
10826
10827 /* Returns the clock of the currently programmed mode of the given pipe. */
10828 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10829 struct intel_crtc_state *pipe_config)
10830 {
10831 struct drm_device *dev = crtc->base.dev;
10832 struct drm_i915_private *dev_priv = to_i915(dev);
10833 int pipe = pipe_config->cpu_transcoder;
10834 u32 dpll = pipe_config->dpll_hw_state.dpll;
10835 u32 fp;
10836 struct dpll clock;
10837 int port_clock;
10838 int refclk = i9xx_pll_refclk(dev, pipe_config);
10839
10840 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10841 fp = pipe_config->dpll_hw_state.fp0;
10842 else
10843 fp = pipe_config->dpll_hw_state.fp1;
10844
10845 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10846 if (IS_PINEVIEW(dev_priv)) {
10847 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10848 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10849 } else {
10850 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10851 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10852 }
10853
10854 if (!IS_GEN(dev_priv, 2)) {
10855 if (IS_PINEVIEW(dev_priv))
10856 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10857 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10858 else
10859 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10860 DPLL_FPA01_P1_POST_DIV_SHIFT);
10861
10862 switch (dpll & DPLL_MODE_MASK) {
10863 case DPLLB_MODE_DAC_SERIAL:
10864 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10865 5 : 10;
10866 break;
10867 case DPLLB_MODE_LVDS:
10868 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10869 7 : 14;
10870 break;
10871 default:
10872 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10873 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10874 return;
10875 }
10876
10877 if (IS_PINEVIEW(dev_priv))
10878 port_clock = pnv_calc_dpll_params(refclk, &clock);
10879 else
10880 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10881 } else {
10882 u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);
10883 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10884
10885 if (is_lvds) {
10886 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10887 DPLL_FPA01_P1_POST_DIV_SHIFT);
10888
10889 if (lvds & LVDS_CLKB_POWER_UP)
10890 clock.p2 = 7;
10891 else
10892 clock.p2 = 14;
10893 } else {
10894 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10895 clock.p1 = 2;
10896 else {
10897 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10898 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10899 }
10900 if (dpll & PLL_P2_DIVIDE_BY_4)
10901 clock.p2 = 4;
10902 else
10903 clock.p2 = 2;
10904 }
10905
10906 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10907 }
10908
10909 /*
10910 * This value includes pixel_multiplier. We will use
10911 * port_clock to compute adjusted_mode.crtc_clock in the
10912 * encoder's get_config() function.
10913 */
10914 pipe_config->port_clock = port_clock;
10915 }
10916
10917 int intel_dotclock_calculate(int link_freq,
10918 const struct intel_link_m_n *m_n)
10919 {
10920 /*
10921 * The calculation for the data clock is:
10922 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10923 * But we want to avoid losing precison if possible, so:
10924 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10925 *
10926 * and the link clock is simpler:
10927 * link_clock = (m * link_clock) / n
10928 */
10929
10930 if (!m_n->link_n)
10931 return 0;
10932
10933 return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n);
10934 }
10935
10936 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10937 struct intel_crtc_state *pipe_config)
10938 {
10939 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10940
10941 /* read out port_clock from the DPLL */
10942 i9xx_crtc_clock_get(crtc, pipe_config);
10943
10944 /*
10945 * In case there is an active pipe without active ports,
10946 * we may need some idea for the dotclock anyway.
10947 * Calculate one based on the FDI configuration.
10948 */
10949 pipe_config->base.adjusted_mode.crtc_clock =
10950 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
10951 &pipe_config->fdi_m_n);
10952 }
10953
10954 /* Returns the currently programmed mode of the given encoder. */
10955 struct drm_display_mode *
10956 intel_encoder_current_mode(struct intel_encoder *encoder)
10957 {
10958 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
10959 struct intel_crtc_state *crtc_state;
10960 struct drm_display_mode *mode;
10961 struct intel_crtc *crtc;
10962 enum pipe pipe;
10963
10964 if (!encoder->get_hw_state(encoder, &pipe))
10965 return NULL;
10966
10967 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
10968
10969 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10970 if (!mode)
10971 return NULL;
10972
10973 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
10974 if (!crtc_state) {
10975 kfree(mode);
10976 return NULL;
10977 }
10978
10979 crtc_state->base.crtc = &crtc->base;
10980
10981 if (!dev_priv->display.get_pipe_config(crtc, crtc_state)) {
10982 kfree(crtc_state);
10983 kfree(mode);
10984 return NULL;
10985 }
10986
10987 encoder->get_config(encoder, crtc_state);
10988
10989 intel_mode_from_pipe_config(mode, crtc_state);
10990
10991 kfree(crtc_state);
10992
10993 return mode;
10994 }
10995
10996 static void intel_crtc_destroy(struct drm_crtc *crtc)
10997 {
10998 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10999
11000 drm_crtc_cleanup(crtc);
11001 kfree(intel_crtc);
11002 }
11003
11004 /**
11005 * intel_wm_need_update - Check whether watermarks need updating
11006 * @cur: current plane state
11007 * @new: new plane state
11008 *
11009 * Check current plane state versus the new one to determine whether
11010 * watermarks need to be recalculated.
11011 *
11012 * Returns true or false.
11013 */
11014 static bool intel_wm_need_update(struct intel_plane_state *cur,
11015 struct intel_plane_state *new)
11016 {
11017 /* Update watermarks on tiling or size changes. */
11018 if (new->base.visible != cur->base.visible)
11019 return true;
11020
11021 if (!cur->base.fb || !new->base.fb)
11022 return false;
11023
11024 if (cur->base.fb->modifier != new->base.fb->modifier ||
11025 cur->base.rotation != new->base.rotation ||
11026 drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) ||
11027 drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) ||
11028 drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) ||
11029 drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst))
11030 return true;
11031
11032 return false;
11033 }
11034
11035 static bool needs_scaling(const struct intel_plane_state *state)
11036 {
11037 int src_w = drm_rect_width(&state->base.src) >> 16;
11038 int src_h = drm_rect_height(&state->base.src) >> 16;
11039 int dst_w = drm_rect_width(&state->base.dst);
11040 int dst_h = drm_rect_height(&state->base.dst);
11041
11042 return (src_w != dst_w || src_h != dst_h);
11043 }
11044
11045 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
11046 struct drm_crtc_state *crtc_state,
11047 const struct intel_plane_state *old_plane_state,
11048 struct drm_plane_state *plane_state)
11049 {
11050 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
11051 struct drm_crtc *crtc = crtc_state->crtc;
11052 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11053 struct intel_plane *plane = to_intel_plane(plane_state->plane);
11054 struct drm_device *dev = crtc->dev;
11055 struct drm_i915_private *dev_priv = to_i915(dev);
11056 bool mode_changed = needs_modeset(crtc_state);
11057 bool was_crtc_enabled = old_crtc_state->base.active;
11058 bool is_crtc_enabled = crtc_state->active;
11059 bool turn_off, turn_on, visible, was_visible;
11060 struct drm_framebuffer *fb = plane_state->fb;
11061 int ret;
11062
11063 if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
11064 ret = skl_update_scaler_plane(
11065 to_intel_crtc_state(crtc_state),
11066 to_intel_plane_state(plane_state));
11067 if (ret)
11068 return ret;
11069 }
11070
11071 was_visible = old_plane_state->base.visible;
11072 visible = plane_state->visible;
11073
11074 if (!was_crtc_enabled && WARN_ON(was_visible))
11075 was_visible = false;
11076
11077 /*
11078 * Visibility is calculated as if the crtc was on, but
11079 * after scaler setup everything depends on it being off
11080 * when the crtc isn't active.
11081 *
11082 * FIXME this is wrong for watermarks. Watermarks should also
11083 * be computed as if the pipe would be active. Perhaps move
11084 * per-plane wm computation to the .check_plane() hook, and
11085 * only combine the results from all planes in the current place?
11086 */
11087 if (!is_crtc_enabled) {
11088 plane_state->visible = visible = false;
11089 to_intel_crtc_state(crtc_state)->active_planes &= ~BIT(plane->id);
11090 }
11091
11092 if (!was_visible && !visible)
11093 return 0;
11094
11095 if (fb != old_plane_state->base.fb)
11096 pipe_config->fb_changed = true;
11097
11098 turn_off = was_visible && (!visible || mode_changed);
11099 turn_on = visible && (!was_visible || mode_changed);
11100
11101 DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
11102 intel_crtc->base.base.id, intel_crtc->base.name,
11103 plane->base.base.id, plane->base.name,
11104 fb ? fb->base.id : -1);
11105
11106 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
11107 plane->base.base.id, plane->base.name,
11108 was_visible, visible,
11109 turn_off, turn_on, mode_changed);
11110
11111 if (turn_on) {
11112 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
11113 pipe_config->update_wm_pre = true;
11114
11115 /* must disable cxsr around plane enable/disable */
11116 if (plane->id != PLANE_CURSOR)
11117 pipe_config->disable_cxsr = true;
11118 } else if (turn_off) {
11119 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
11120 pipe_config->update_wm_post = true;
11121
11122 /* must disable cxsr around plane enable/disable */
11123 if (plane->id != PLANE_CURSOR)
11124 pipe_config->disable_cxsr = true;
11125 } else if (intel_wm_need_update(to_intel_plane_state(plane->base.state),
11126 to_intel_plane_state(plane_state))) {
11127 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
11128 /* FIXME bollocks */
11129 pipe_config->update_wm_pre = true;
11130 pipe_config->update_wm_post = true;
11131 }
11132 }
11133
11134 if (visible || was_visible)
11135 pipe_config->fb_bits |= plane->frontbuffer_bit;
11136
11137 /*
11138 * ILK/SNB DVSACNTR/Sprite Enable
11139 * IVB SPR_CTL/Sprite Enable
11140 * "When in Self Refresh Big FIFO mode, a write to enable the
11141 * plane will be internally buffered and delayed while Big FIFO
11142 * mode is exiting."
11143 *
11144 * Which means that enabling the sprite can take an extra frame
11145 * when we start in big FIFO mode (LP1+). Thus we need to drop
11146 * down to LP0 and wait for vblank in order to make sure the
11147 * sprite gets enabled on the next vblank after the register write.
11148 * Doing otherwise would risk enabling the sprite one frame after
11149 * we've already signalled flip completion. We can resume LP1+
11150 * once the sprite has been enabled.
11151 *
11152 *
11153 * WaCxSRDisabledForSpriteScaling:ivb
11154 * IVB SPR_SCALE/Scaling Enable
11155 * "Low Power watermarks must be disabled for at least one
11156 * frame before enabling sprite scaling, and kept disabled
11157 * until sprite scaling is disabled."
11158 *
11159 * ILK/SNB DVSASCALE/Scaling Enable
11160 * "When in Self Refresh Big FIFO mode, scaling enable will be
11161 * masked off while Big FIFO mode is exiting."
11162 *
11163 * Despite the w/a only being listed for IVB we assume that
11164 * the ILK/SNB note has similar ramifications, hence we apply
11165 * the w/a on all three platforms.
11166 *
11167 * With experimental results seems this is needed also for primary
11168 * plane, not only sprite plane.
11169 */
11170 if (plane->id != PLANE_CURSOR &&
11171 (IS_GEN_RANGE(dev_priv, 5, 6) ||
11172 IS_IVYBRIDGE(dev_priv)) &&
11173 (turn_on || (!needs_scaling(old_plane_state) &&
11174 needs_scaling(to_intel_plane_state(plane_state)))))
11175 pipe_config->disable_lp_wm = true;
11176
11177 return 0;
11178 }
11179
11180 static bool encoders_cloneable(const struct intel_encoder *a,
11181 const struct intel_encoder *b)
11182 {
11183 /* masks could be asymmetric, so check both ways */
11184 return a == b || (a->cloneable & (1 << b->type) &&
11185 b->cloneable & (1 << a->type));
11186 }
11187
11188 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11189 struct intel_crtc *crtc,
11190 struct intel_encoder *encoder)
11191 {
11192 struct intel_encoder *source_encoder;
11193 struct drm_connector *connector;
11194 struct drm_connector_state *connector_state;
11195 int i;
11196
11197 for_each_new_connector_in_state(state, connector, connector_state, i) {
11198 if (connector_state->crtc != &crtc->base)
11199 continue;
11200
11201 source_encoder =
11202 to_intel_encoder(connector_state->best_encoder);
11203 if (!encoders_cloneable(encoder, source_encoder))
11204 return false;
11205 }
11206
11207 return true;
11208 }
11209
11210 static int icl_add_linked_planes(struct intel_atomic_state *state)
11211 {
11212 struct intel_plane *plane, *linked;
11213 struct intel_plane_state *plane_state, *linked_plane_state;
11214 int i;
11215
11216 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
11217 linked = plane_state->linked_plane;
11218
11219 if (!linked)
11220 continue;
11221
11222 linked_plane_state = intel_atomic_get_plane_state(state, linked);
11223 if (IS_ERR(linked_plane_state))
11224 return PTR_ERR(linked_plane_state);
11225
11226 WARN_ON(linked_plane_state->linked_plane != plane);
11227 WARN_ON(linked_plane_state->slave == plane_state->slave);
11228 }
11229
11230 return 0;
11231 }
11232
11233 static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
11234 {
11235 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
11236 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11237 struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->base.state);
11238 struct intel_plane *plane, *linked;
11239 struct intel_plane_state *plane_state;
11240 int i;
11241
11242 if (INTEL_GEN(dev_priv) < 11)
11243 return 0;
11244
11245 /*
11246 * Destroy all old plane links and make the slave plane invisible
11247 * in the crtc_state->active_planes mask.
11248 */
11249 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
11250 if (plane->pipe != crtc->pipe || !plane_state->linked_plane)
11251 continue;
11252
11253 plane_state->linked_plane = NULL;
11254 if (plane_state->slave && !plane_state->base.visible) {
11255 crtc_state->active_planes &= ~BIT(plane->id);
11256 crtc_state->update_planes |= BIT(plane->id);
11257 }
11258
11259 plane_state->slave = false;
11260 }
11261
11262 if (!crtc_state->nv12_planes)
11263 return 0;
11264
11265 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
11266 struct intel_plane_state *linked_state = NULL;
11267
11268 if (plane->pipe != crtc->pipe ||
11269 !(crtc_state->nv12_planes & BIT(plane->id)))
11270 continue;
11271
11272 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) {
11273 if (!icl_is_nv12_y_plane(linked->id))
11274 continue;
11275
11276 if (crtc_state->active_planes & BIT(linked->id))
11277 continue;
11278
11279 linked_state = intel_atomic_get_plane_state(state, linked);
11280 if (IS_ERR(linked_state))
11281 return PTR_ERR(linked_state);
11282
11283 break;
11284 }
11285
11286 if (!linked_state) {
11287 DRM_DEBUG_KMS("Need %d free Y planes for planar YUV\n",
11288 hweight8(crtc_state->nv12_planes));
11289
11290 return -EINVAL;
11291 }
11292
11293 plane_state->linked_plane = linked;
11294
11295 linked_state->slave = true;
11296 linked_state->linked_plane = plane;
11297 crtc_state->active_planes |= BIT(linked->id);
11298 crtc_state->update_planes |= BIT(linked->id);
11299 DRM_DEBUG_KMS("Using %s as Y plane for %s\n", linked->base.name, plane->base.name);
11300 }
11301
11302 return 0;
11303 }
11304
11305 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11306 struct drm_crtc_state *crtc_state)
11307 {
11308 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
11309 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11310 struct intel_crtc_state *pipe_config =
11311 to_intel_crtc_state(crtc_state);
11312 int ret;
11313 bool mode_changed = needs_modeset(crtc_state);
11314
11315 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv) &&
11316 mode_changed && !crtc_state->active)
11317 pipe_config->update_wm_post = true;
11318
11319 if (mode_changed && crtc_state->enable &&
11320 dev_priv->display.crtc_compute_clock &&
11321 !WARN_ON(pipe_config->shared_dpll)) {
11322 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11323 pipe_config);
11324 if (ret)
11325 return ret;
11326 }
11327
11328 if (mode_changed || pipe_config->update_pipe ||
11329 crtc_state->color_mgmt_changed) {
11330 ret = intel_color_check(pipe_config);
11331 if (ret)
11332 return ret;
11333 }
11334
11335 ret = 0;
11336 if (dev_priv->display.compute_pipe_wm) {
11337 ret = dev_priv->display.compute_pipe_wm(pipe_config);
11338 if (ret) {
11339 DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
11340 return ret;
11341 }
11342 }
11343
11344 if (dev_priv->display.compute_intermediate_wm) {
11345 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
11346 return 0;
11347
11348 /*
11349 * Calculate 'intermediate' watermarks that satisfy both the
11350 * old state and the new state. We can program these
11351 * immediately.
11352 */
11353 ret = dev_priv->display.compute_intermediate_wm(pipe_config);
11354 if (ret) {
11355 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
11356 return ret;
11357 }
11358 }
11359
11360 if (INTEL_GEN(dev_priv) >= 9) {
11361 if (mode_changed || pipe_config->update_pipe)
11362 ret = skl_update_scaler_crtc(pipe_config);
11363
11364 if (!ret)
11365 ret = icl_check_nv12_planes(pipe_config);
11366 if (!ret)
11367 ret = skl_check_pipe_max_pixel_rate(intel_crtc,
11368 pipe_config);
11369 if (!ret)
11370 ret = intel_atomic_setup_scalers(dev_priv, intel_crtc,
11371 pipe_config);
11372 }
11373
11374 if (HAS_IPS(dev_priv))
11375 pipe_config->ips_enabled = hsw_compute_ips_config(pipe_config);
11376
11377 return ret;
11378 }
11379
11380 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11381 .atomic_check = intel_crtc_atomic_check,
11382 };
11383
11384 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11385 {
11386 struct intel_connector *connector;
11387 struct drm_connector_list_iter conn_iter;
11388
11389 drm_connector_list_iter_begin(dev, &conn_iter);
11390 for_each_intel_connector_iter(connector, &conn_iter) {
11391 if (connector->base.state->crtc)
11392 drm_connector_put(&connector->base);
11393
11394 if (connector->base.encoder) {
11395 connector->base.state->best_encoder =
11396 connector->base.encoder;
11397 connector->base.state->crtc =
11398 connector->base.encoder->crtc;
11399
11400 drm_connector_get(&connector->base);
11401 } else {
11402 connector->base.state->best_encoder = NULL;
11403 connector->base.state->crtc = NULL;
11404 }
11405 }
11406 drm_connector_list_iter_end(&conn_iter);
11407 }
11408
11409 static int
11410 compute_sink_pipe_bpp(const struct drm_connector_state *conn_state,
11411 struct intel_crtc_state *pipe_config)
11412 {
11413 struct drm_connector *connector = conn_state->connector;
11414 const struct drm_display_info *info = &connector->display_info;
11415 int bpp;
11416
11417 switch (conn_state->max_bpc) {
11418 case 6 ... 7:
11419 bpp = 6 * 3;
11420 break;
11421 case 8 ... 9:
11422 bpp = 8 * 3;
11423 break;
11424 case 10 ... 11:
11425 bpp = 10 * 3;
11426 break;
11427 case 12:
11428 bpp = 12 * 3;
11429 break;
11430 default:
11431 return -EINVAL;
11432 }
11433
11434 if (bpp < pipe_config->pipe_bpp) {
11435 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Limiting display bpp to %d instead of "
11436 "EDID bpp %d, requested bpp %d, max platform bpp %d\n",
11437 connector->base.id, connector->name,
11438 bpp, 3 * info->bpc, 3 * conn_state->max_requested_bpc,
11439 pipe_config->pipe_bpp);
11440
11441 pipe_config->pipe_bpp = bpp;
11442 }
11443
11444 return 0;
11445 }
11446
11447 static int
11448 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11449 struct intel_crtc_state *pipe_config)
11450 {
11451 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11452 struct drm_atomic_state *state = pipe_config->base.state;
11453 struct drm_connector *connector;
11454 struct drm_connector_state *connector_state;
11455 int bpp, i;
11456
11457 if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
11458 IS_CHERRYVIEW(dev_priv)))
11459 bpp = 10*3;
11460 else if (INTEL_GEN(dev_priv) >= 5)
11461 bpp = 12*3;
11462 else
11463 bpp = 8*3;
11464
11465 pipe_config->pipe_bpp = bpp;
11466
11467 /* Clamp display bpp to connector max bpp */
11468 for_each_new_connector_in_state(state, connector, connector_state, i) {
11469 int ret;
11470
11471 if (connector_state->crtc != &crtc->base)
11472 continue;
11473
11474 ret = compute_sink_pipe_bpp(connector_state, pipe_config);
11475 if (ret)
11476 return ret;
11477 }
11478
11479 return 0;
11480 }
11481
11482 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11483 {
11484 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11485 "type: 0x%x flags: 0x%x\n",
11486 mode->crtc_clock,
11487 mode->crtc_hdisplay, mode->crtc_hsync_start,
11488 mode->crtc_hsync_end, mode->crtc_htotal,
11489 mode->crtc_vdisplay, mode->crtc_vsync_start,
11490 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11491 }
11492
11493 static inline void
11494 intel_dump_m_n_config(struct intel_crtc_state *pipe_config, char *id,
11495 unsigned int lane_count, struct intel_link_m_n *m_n)
11496 {
11497 DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11498 id, lane_count,
11499 m_n->gmch_m, m_n->gmch_n,
11500 m_n->link_m, m_n->link_n, m_n->tu);
11501 }
11502
11503 static void
11504 intel_dump_infoframe(struct drm_i915_private *dev_priv,
11505 const union hdmi_infoframe *frame)
11506 {
11507 if ((drm_debug & DRM_UT_KMS) == 0)
11508 return;
11509
11510 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame);
11511 }
11512
11513 #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
11514
11515 static const char * const output_type_str[] = {
11516 OUTPUT_TYPE(UNUSED),
11517 OUTPUT_TYPE(ANALOG),
11518 OUTPUT_TYPE(DVO),
11519 OUTPUT_TYPE(SDVO),
11520 OUTPUT_TYPE(LVDS),
11521 OUTPUT_TYPE(TVOUT),
11522 OUTPUT_TYPE(HDMI),
11523 OUTPUT_TYPE(DP),
11524 OUTPUT_TYPE(EDP),
11525 OUTPUT_TYPE(DSI),
11526 OUTPUT_TYPE(DDI),
11527 OUTPUT_TYPE(DP_MST),
11528 };
11529
11530 #undef OUTPUT_TYPE
11531
11532 static void snprintf_output_types(char *buf, size_t len,
11533 unsigned int output_types)
11534 {
11535 char *str = buf;
11536 int i;
11537
11538 str[0] = '\0';
11539
11540 for (i = 0; i < ARRAY_SIZE(output_type_str); i++) {
11541 int r;
11542
11543 if ((output_types & BIT(i)) == 0)
11544 continue;
11545
11546 r = snprintf(str, len, "%s%s",
11547 str != buf ? "," : "", output_type_str[i]);
11548 if (r >= len)
11549 break;
11550 str += r;
11551 len -= r;
11552
11553 output_types &= ~BIT(i);
11554 }
11555
11556 WARN_ON_ONCE(output_types != 0);
11557 }
11558
11559 static const char * const output_format_str[] = {
11560 [INTEL_OUTPUT_FORMAT_INVALID] = "Invalid",
11561 [INTEL_OUTPUT_FORMAT_RGB] = "RGB",
11562 [INTEL_OUTPUT_FORMAT_YCBCR420] = "YCBCR4:2:0",
11563 [INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4",
11564 };
11565
11566 static const char *output_formats(enum intel_output_format format)
11567 {
11568 if (format >= ARRAY_SIZE(output_format_str))
11569 format = INTEL_OUTPUT_FORMAT_INVALID;
11570 return output_format_str[format];
11571 }
11572
11573 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11574 struct intel_crtc_state *pipe_config,
11575 const char *context)
11576 {
11577 struct drm_device *dev = crtc->base.dev;
11578 struct drm_i915_private *dev_priv = to_i915(dev);
11579 struct drm_plane *plane;
11580 struct intel_plane *intel_plane;
11581 struct intel_plane_state *state;
11582 struct drm_framebuffer *fb;
11583 char buf[64];
11584
11585 DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n",
11586 crtc->base.base.id, crtc->base.name, context);
11587
11588 snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
11589 DRM_DEBUG_KMS("output_types: %s (0x%x)\n",
11590 buf, pipe_config->output_types);
11591
11592 DRM_DEBUG_KMS("output format: %s\n",
11593 output_formats(pipe_config->output_format));
11594
11595 DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
11596 transcoder_name(pipe_config->cpu_transcoder),
11597 pipe_config->pipe_bpp, pipe_config->dither);
11598
11599 if (pipe_config->has_pch_encoder)
11600 intel_dump_m_n_config(pipe_config, "fdi",
11601 pipe_config->fdi_lanes,
11602 &pipe_config->fdi_m_n);
11603
11604 if (intel_crtc_has_dp_encoder(pipe_config)) {
11605 intel_dump_m_n_config(pipe_config, "dp m_n",
11606 pipe_config->lane_count, &pipe_config->dp_m_n);
11607 if (pipe_config->has_drrs)
11608 intel_dump_m_n_config(pipe_config, "dp m2_n2",
11609 pipe_config->lane_count,
11610 &pipe_config->dp_m2_n2);
11611 }
11612
11613 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11614 pipe_config->has_audio, pipe_config->has_infoframe);
11615
11616 DRM_DEBUG_KMS("infoframes enabled: 0x%x\n",
11617 pipe_config->infoframes.enable);
11618
11619 if (pipe_config->infoframes.enable &
11620 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL))
11621 DRM_DEBUG_KMS("GCP: 0x%x\n", pipe_config->infoframes.gcp);
11622 if (pipe_config->infoframes.enable &
11623 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI))
11624 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.avi);
11625 if (pipe_config->infoframes.enable &
11626 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD))
11627 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.spd);
11628 if (pipe_config->infoframes.enable &
11629 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR))
11630 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi);
11631
11632 DRM_DEBUG_KMS("requested mode:\n");
11633 drm_mode_debug_printmodeline(&pipe_config->base.mode);
11634 DRM_DEBUG_KMS("adjusted mode:\n");
11635 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11636 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
11637 DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
11638 pipe_config->port_clock,
11639 pipe_config->pipe_src_w, pipe_config->pipe_src_h,
11640 pipe_config->pixel_rate);
11641
11642 if (INTEL_GEN(dev_priv) >= 9)
11643 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11644 crtc->num_scalers,
11645 pipe_config->scaler_state.scaler_users,
11646 pipe_config->scaler_state.scaler_id);
11647
11648 if (HAS_GMCH(dev_priv))
11649 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11650 pipe_config->gmch_pfit.control,
11651 pipe_config->gmch_pfit.pgm_ratios,
11652 pipe_config->gmch_pfit.lvds_border_bits);
11653 else
11654 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11655 pipe_config->pch_pfit.pos,
11656 pipe_config->pch_pfit.size,
11657 enableddisabled(pipe_config->pch_pfit.enabled));
11658
11659 DRM_DEBUG_KMS("ips: %i, double wide: %i\n",
11660 pipe_config->ips_enabled, pipe_config->double_wide);
11661
11662 intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
11663
11664 DRM_DEBUG_KMS("planes on this crtc\n");
11665 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11666 struct drm_format_name_buf format_name;
11667 intel_plane = to_intel_plane(plane);
11668 if (intel_plane->pipe != crtc->pipe)
11669 continue;
11670
11671 state = to_intel_plane_state(plane->state);
11672 fb = state->base.fb;
11673 if (!fb) {
11674 DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
11675 plane->base.id, plane->name, state->scaler_id);
11676 continue;
11677 }
11678
11679 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n",
11680 plane->base.id, plane->name,
11681 fb->base.id, fb->width, fb->height,
11682 drm_get_format_name(fb->format->format, &format_name));
11683 if (INTEL_GEN(dev_priv) >= 9)
11684 DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
11685 state->scaler_id,
11686 state->base.src.x1 >> 16,
11687 state->base.src.y1 >> 16,
11688 drm_rect_width(&state->base.src) >> 16,
11689 drm_rect_height(&state->base.src) >> 16,
11690 state->base.dst.x1, state->base.dst.y1,
11691 drm_rect_width(&state->base.dst),
11692 drm_rect_height(&state->base.dst));
11693 }
11694 }
11695
11696 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
11697 {
11698 struct drm_device *dev = state->dev;
11699 struct drm_connector *connector;
11700 struct drm_connector_list_iter conn_iter;
11701 unsigned int used_ports = 0;
11702 unsigned int used_mst_ports = 0;
11703 bool ret = true;
11704
11705 /*
11706 * Walk the connector list instead of the encoder
11707 * list to detect the problem on ddi platforms
11708 * where there's just one encoder per digital port.
11709 */
11710 drm_connector_list_iter_begin(dev, &conn_iter);
11711 drm_for_each_connector_iter(connector, &conn_iter) {
11712 struct drm_connector_state *connector_state;
11713 struct intel_encoder *encoder;
11714
11715 connector_state = drm_atomic_get_new_connector_state(state, connector);
11716 if (!connector_state)
11717 connector_state = connector->state;
11718
11719 if (!connector_state->best_encoder)
11720 continue;
11721
11722 encoder = to_intel_encoder(connector_state->best_encoder);
11723
11724 WARN_ON(!connector_state->crtc);
11725
11726 switch (encoder->type) {
11727 unsigned int port_mask;
11728 case INTEL_OUTPUT_DDI:
11729 if (WARN_ON(!HAS_DDI(to_i915(dev))))
11730 break;
11731 /* else: fall through */
11732 case INTEL_OUTPUT_DP:
11733 case INTEL_OUTPUT_HDMI:
11734 case INTEL_OUTPUT_EDP:
11735 port_mask = 1 << encoder->port;
11736
11737 /* the same port mustn't appear more than once */
11738 if (used_ports & port_mask)
11739 ret = false;
11740
11741 used_ports |= port_mask;
11742 break;
11743 case INTEL_OUTPUT_DP_MST:
11744 used_mst_ports |=
11745 1 << encoder->port;
11746 break;
11747 default:
11748 break;
11749 }
11750 }
11751 drm_connector_list_iter_end(&conn_iter);
11752
11753 /* can't mix MST and SST/HDMI on the same port */
11754 if (used_ports & used_mst_ports)
11755 return false;
11756
11757 return ret;
11758 }
11759
11760 static int
11761 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
11762 {
11763 struct drm_i915_private *dev_priv =
11764 to_i915(crtc_state->base.crtc->dev);
11765 struct intel_crtc_state *saved_state;
11766
11767 saved_state = kzalloc(sizeof(*saved_state), GFP_KERNEL);
11768 if (!saved_state)
11769 return -ENOMEM;
11770
11771 /* FIXME: before the switch to atomic started, a new pipe_config was
11772 * kzalloc'd. Code that depends on any field being zero should be
11773 * fixed, so that the crtc_state can be safely duplicated. For now,
11774 * only fields that are know to not cause problems are preserved. */
11775
11776 saved_state->scaler_state = crtc_state->scaler_state;
11777 saved_state->shared_dpll = crtc_state->shared_dpll;
11778 saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
11779 saved_state->pch_pfit.force_thru = crtc_state->pch_pfit.force_thru;
11780 saved_state->crc_enabled = crtc_state->crc_enabled;
11781 if (IS_G4X(dev_priv) ||
11782 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11783 saved_state->wm = crtc_state->wm;
11784
11785 /* Keep base drm_crtc_state intact, only clear our extended struct */
11786 BUILD_BUG_ON(offsetof(struct intel_crtc_state, base));
11787 memcpy(&crtc_state->base + 1, &saved_state->base + 1,
11788 sizeof(*crtc_state) - sizeof(crtc_state->base));
11789
11790 kfree(saved_state);
11791 return 0;
11792 }
11793
11794 static int
11795 intel_modeset_pipe_config(struct drm_crtc *crtc,
11796 struct intel_crtc_state *pipe_config)
11797 {
11798 struct drm_atomic_state *state = pipe_config->base.state;
11799 struct intel_encoder *encoder;
11800 struct drm_connector *connector;
11801 struct drm_connector_state *connector_state;
11802 int base_bpp, ret;
11803 int i;
11804 bool retry = true;
11805
11806 ret = clear_intel_crtc_state(pipe_config);
11807 if (ret)
11808 return ret;
11809
11810 pipe_config->cpu_transcoder =
11811 (enum transcoder) to_intel_crtc(crtc)->pipe;
11812
11813 /*
11814 * Sanitize sync polarity flags based on requested ones. If neither
11815 * positive or negative polarity is requested, treat this as meaning
11816 * negative polarity.
11817 */
11818 if (!(pipe_config->base.adjusted_mode.flags &
11819 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
11820 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
11821
11822 if (!(pipe_config->base.adjusted_mode.flags &
11823 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
11824 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
11825
11826 ret = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
11827 pipe_config);
11828 if (ret)
11829 return ret;
11830
11831 base_bpp = pipe_config->pipe_bpp;
11832
11833 /*
11834 * Determine the real pipe dimensions. Note that stereo modes can
11835 * increase the actual pipe size due to the frame doubling and
11836 * insertion of additional space for blanks between the frame. This
11837 * is stored in the crtc timings. We use the requested mode to do this
11838 * computation to clearly distinguish it from the adjusted mode, which
11839 * can be changed by the connectors in the below retry loop.
11840 */
11841 drm_mode_get_hv_timing(&pipe_config->base.mode,
11842 &pipe_config->pipe_src_w,
11843 &pipe_config->pipe_src_h);
11844
11845 for_each_new_connector_in_state(state, connector, connector_state, i) {
11846 if (connector_state->crtc != crtc)
11847 continue;
11848
11849 encoder = to_intel_encoder(connector_state->best_encoder);
11850
11851 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
11852 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11853 return -EINVAL;
11854 }
11855
11856 /*
11857 * Determine output_types before calling the .compute_config()
11858 * hooks so that the hooks can use this information safely.
11859 */
11860 if (encoder->compute_output_type)
11861 pipe_config->output_types |=
11862 BIT(encoder->compute_output_type(encoder, pipe_config,
11863 connector_state));
11864 else
11865 pipe_config->output_types |= BIT(encoder->type);
11866 }
11867
11868 encoder_retry:
11869 /* Ensure the port clock defaults are reset when retrying. */
11870 pipe_config->port_clock = 0;
11871 pipe_config->pixel_multiplier = 1;
11872
11873 /* Fill in default crtc timings, allow encoders to overwrite them. */
11874 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
11875 CRTC_STEREO_DOUBLE);
11876
11877 /* Pass our mode to the connectors and the CRTC to give them a chance to
11878 * adjust it according to limitations or connector properties, and also
11879 * a chance to reject the mode entirely.
11880 */
11881 for_each_new_connector_in_state(state, connector, connector_state, i) {
11882 if (connector_state->crtc != crtc)
11883 continue;
11884
11885 encoder = to_intel_encoder(connector_state->best_encoder);
11886 ret = encoder->compute_config(encoder, pipe_config,
11887 connector_state);
11888 if (ret < 0) {
11889 if (ret != -EDEADLK)
11890 DRM_DEBUG_KMS("Encoder config failure: %d\n",
11891 ret);
11892 return ret;
11893 }
11894 }
11895
11896 /* Set default port clock if not overwritten by the encoder. Needs to be
11897 * done afterwards in case the encoder adjusts the mode. */
11898 if (!pipe_config->port_clock)
11899 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
11900 * pipe_config->pixel_multiplier;
11901
11902 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
11903 if (ret == -EDEADLK)
11904 return ret;
11905 if (ret < 0) {
11906 DRM_DEBUG_KMS("CRTC fixup failed\n");
11907 return ret;
11908 }
11909
11910 if (ret == RETRY) {
11911 if (WARN(!retry, "loop in pipe configuration computation\n"))
11912 return -EINVAL;
11913
11914 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
11915 retry = false;
11916 goto encoder_retry;
11917 }
11918
11919 /* Dithering seems to not pass-through bits correctly when it should, so
11920 * only enable it on 6bpc panels and when its not a compliance
11921 * test requesting 6bpc video pattern.
11922 */
11923 pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
11924 !pipe_config->dither_force_disable;
11925 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
11926 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
11927
11928 return 0;
11929 }
11930
11931 static bool intel_fuzzy_clock_check(int clock1, int clock2)
11932 {
11933 int diff;
11934
11935 if (clock1 == clock2)
11936 return true;
11937
11938 if (!clock1 || !clock2)
11939 return false;
11940
11941 diff = abs(clock1 - clock2);
11942
11943 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11944 return true;
11945
11946 return false;
11947 }
11948
11949 static bool
11950 intel_compare_m_n(unsigned int m, unsigned int n,
11951 unsigned int m2, unsigned int n2,
11952 bool exact)
11953 {
11954 if (m == m2 && n == n2)
11955 return true;
11956
11957 if (exact || !m || !n || !m2 || !n2)
11958 return false;
11959
11960 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
11961
11962 if (n > n2) {
11963 while (n > n2) {
11964 m2 <<= 1;
11965 n2 <<= 1;
11966 }
11967 } else if (n < n2) {
11968 while (n < n2) {
11969 m <<= 1;
11970 n <<= 1;
11971 }
11972 }
11973
11974 if (n != n2)
11975 return false;
11976
11977 return intel_fuzzy_clock_check(m, m2);
11978 }
11979
11980 static bool
11981 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
11982 struct intel_link_m_n *m2_n2,
11983 bool adjust)
11984 {
11985 if (m_n->tu == m2_n2->tu &&
11986 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
11987 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
11988 intel_compare_m_n(m_n->link_m, m_n->link_n,
11989 m2_n2->link_m, m2_n2->link_n, !adjust)) {
11990 if (adjust)
11991 *m2_n2 = *m_n;
11992
11993 return true;
11994 }
11995
11996 return false;
11997 }
11998
11999 static bool
12000 intel_compare_infoframe(const union hdmi_infoframe *a,
12001 const union hdmi_infoframe *b)
12002 {
12003 return memcmp(a, b, sizeof(*a)) == 0;
12004 }
12005
12006 static void
12007 pipe_config_infoframe_err(struct drm_i915_private *dev_priv,
12008 bool adjust, const char *name,
12009 const union hdmi_infoframe *a,
12010 const union hdmi_infoframe *b)
12011 {
12012 if (adjust) {
12013 if ((drm_debug & DRM_UT_KMS) == 0)
12014 return;
12015
12016 drm_dbg(DRM_UT_KMS, "mismatch in %s infoframe", name);
12017 drm_dbg(DRM_UT_KMS, "expected:");
12018 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a);
12019 drm_dbg(DRM_UT_KMS, "found");
12020 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b);
12021 } else {
12022 drm_err("mismatch in %s infoframe", name);
12023 drm_err("expected:");
12024 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a);
12025 drm_err("found");
12026 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b);
12027 }
12028 }
12029
12030 static void __printf(3, 4)
12031 pipe_config_err(bool adjust, const char *name, const char *format, ...)
12032 {
12033 struct va_format vaf;
12034 va_list args;
12035
12036 va_start(args, format);
12037 vaf.fmt = format;
12038 vaf.va = &args;
12039
12040 if (adjust)
12041 drm_dbg(DRM_UT_KMS, "mismatch in %s %pV", name, &vaf);
12042 else
12043 drm_err("mismatch in %s %pV", name, &vaf);
12044
12045 va_end(args);
12046 }
12047
12048 static bool fastboot_enabled(struct drm_i915_private *dev_priv)
12049 {
12050 if (i915_modparams.fastboot != -1)
12051 return i915_modparams.fastboot;
12052
12053 /* Enable fastboot by default on Skylake and newer */
12054 if (INTEL_GEN(dev_priv) >= 9)
12055 return true;
12056
12057 /* Enable fastboot by default on VLV and CHV */
12058 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
12059 return true;
12060
12061 /* Disabled by default on all others */
12062 return false;
12063 }
12064
12065 static bool
12066 intel_pipe_config_compare(struct drm_i915_private *dev_priv,
12067 struct intel_crtc_state *current_config,
12068 struct intel_crtc_state *pipe_config,
12069 bool adjust)
12070 {
12071 bool ret = true;
12072 bool fixup_inherited = adjust &&
12073 (current_config->base.mode.private_flags & I915_MODE_FLAG_INHERITED) &&
12074 !(pipe_config->base.mode.private_flags & I915_MODE_FLAG_INHERITED);
12075
12076 if (fixup_inherited && !fastboot_enabled(dev_priv)) {
12077 DRM_DEBUG_KMS("initial modeset and fastboot not set\n");
12078 ret = false;
12079 }
12080
12081 #define PIPE_CONF_CHECK_X(name) do { \
12082 if (current_config->name != pipe_config->name) { \
12083 pipe_config_err(adjust, __stringify(name), \
12084 "(expected 0x%08x, found 0x%08x)\n", \
12085 current_config->name, \
12086 pipe_config->name); \
12087 ret = false; \
12088 } \
12089 } while (0)
12090
12091 #define PIPE_CONF_CHECK_I(name) do { \
12092 if (current_config->name != pipe_config->name) { \
12093 pipe_config_err(adjust, __stringify(name), \
12094 "(expected %i, found %i)\n", \
12095 current_config->name, \
12096 pipe_config->name); \
12097 ret = false; \
12098 } \
12099 } while (0)
12100
12101 #define PIPE_CONF_CHECK_BOOL(name) do { \
12102 if (current_config->name != pipe_config->name) { \
12103 pipe_config_err(adjust, __stringify(name), \
12104 "(expected %s, found %s)\n", \
12105 yesno(current_config->name), \
12106 yesno(pipe_config->name)); \
12107 ret = false; \
12108 } \
12109 } while (0)
12110
12111 /*
12112 * Checks state where we only read out the enabling, but not the entire
12113 * state itself (like full infoframes or ELD for audio). These states
12114 * require a full modeset on bootup to fix up.
12115 */
12116 #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \
12117 if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \
12118 PIPE_CONF_CHECK_BOOL(name); \
12119 } else { \
12120 pipe_config_err(adjust, __stringify(name), \
12121 "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)\n", \
12122 yesno(current_config->name), \
12123 yesno(pipe_config->name)); \
12124 ret = false; \
12125 } \
12126 } while (0)
12127
12128 #define PIPE_CONF_CHECK_P(name) do { \
12129 if (current_config->name != pipe_config->name) { \
12130 pipe_config_err(adjust, __stringify(name), \
12131 "(expected %p, found %p)\n", \
12132 current_config->name, \
12133 pipe_config->name); \
12134 ret = false; \
12135 } \
12136 } while (0)
12137
12138 #define PIPE_CONF_CHECK_M_N(name) do { \
12139 if (!intel_compare_link_m_n(&current_config->name, \
12140 &pipe_config->name,\
12141 adjust)) { \
12142 pipe_config_err(adjust, __stringify(name), \
12143 "(expected tu %i gmch %i/%i link %i/%i, " \
12144 "found tu %i, gmch %i/%i link %i/%i)\n", \
12145 current_config->name.tu, \
12146 current_config->name.gmch_m, \
12147 current_config->name.gmch_n, \
12148 current_config->name.link_m, \
12149 current_config->name.link_n, \
12150 pipe_config->name.tu, \
12151 pipe_config->name.gmch_m, \
12152 pipe_config->name.gmch_n, \
12153 pipe_config->name.link_m, \
12154 pipe_config->name.link_n); \
12155 ret = false; \
12156 } \
12157 } while (0)
12158
12159 /* This is required for BDW+ where there is only one set of registers for
12160 * switching between high and low RR.
12161 * This macro can be used whenever a comparison has to be made between one
12162 * hw state and multiple sw state variables.
12163 */
12164 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) do { \
12165 if (!intel_compare_link_m_n(&current_config->name, \
12166 &pipe_config->name, adjust) && \
12167 !intel_compare_link_m_n(&current_config->alt_name, \
12168 &pipe_config->name, adjust)) { \
12169 pipe_config_err(adjust, __stringify(name), \
12170 "(expected tu %i gmch %i/%i link %i/%i, " \
12171 "or tu %i gmch %i/%i link %i/%i, " \
12172 "found tu %i, gmch %i/%i link %i/%i)\n", \
12173 current_config->name.tu, \
12174 current_config->name.gmch_m, \
12175 current_config->name.gmch_n, \
12176 current_config->name.link_m, \
12177 current_config->name.link_n, \
12178 current_config->alt_name.tu, \
12179 current_config->alt_name.gmch_m, \
12180 current_config->alt_name.gmch_n, \
12181 current_config->alt_name.link_m, \
12182 current_config->alt_name.link_n, \
12183 pipe_config->name.tu, \
12184 pipe_config->name.gmch_m, \
12185 pipe_config->name.gmch_n, \
12186 pipe_config->name.link_m, \
12187 pipe_config->name.link_n); \
12188 ret = false; \
12189 } \
12190 } while (0)
12191
12192 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \
12193 if ((current_config->name ^ pipe_config->name) & (mask)) { \
12194 pipe_config_err(adjust, __stringify(name), \
12195 "(%x) (expected %i, found %i)\n", \
12196 (mask), \
12197 current_config->name & (mask), \
12198 pipe_config->name & (mask)); \
12199 ret = false; \
12200 } \
12201 } while (0)
12202
12203 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) do { \
12204 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12205 pipe_config_err(adjust, __stringify(name), \
12206 "(expected %i, found %i)\n", \
12207 current_config->name, \
12208 pipe_config->name); \
12209 ret = false; \
12210 } \
12211 } while (0)
12212
12213 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \
12214 if (!intel_compare_infoframe(&current_config->infoframes.name, \
12215 &pipe_config->infoframes.name)) { \
12216 pipe_config_infoframe_err(dev_priv, adjust, __stringify(name), \
12217 &current_config->infoframes.name, \
12218 &pipe_config->infoframes.name); \
12219 ret = false; \
12220 } \
12221 } while (0)
12222
12223 #define PIPE_CONF_QUIRK(quirk) \
12224 ((current_config->quirks | pipe_config->quirks) & (quirk))
12225
12226 PIPE_CONF_CHECK_I(cpu_transcoder);
12227
12228 PIPE_CONF_CHECK_BOOL(has_pch_encoder);
12229 PIPE_CONF_CHECK_I(fdi_lanes);
12230 PIPE_CONF_CHECK_M_N(fdi_m_n);
12231
12232 PIPE_CONF_CHECK_I(lane_count);
12233 PIPE_CONF_CHECK_X(lane_lat_optim_mask);
12234
12235 if (INTEL_GEN(dev_priv) < 8) {
12236 PIPE_CONF_CHECK_M_N(dp_m_n);
12237
12238 if (current_config->has_drrs)
12239 PIPE_CONF_CHECK_M_N(dp_m2_n2);
12240 } else
12241 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12242
12243 PIPE_CONF_CHECK_X(output_types);
12244
12245 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12246 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12247 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12248 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12249 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12250 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12251
12252 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12253 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12254 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12255 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12256 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12257 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12258
12259 PIPE_CONF_CHECK_I(pixel_multiplier);
12260 PIPE_CONF_CHECK_I(output_format);
12261 PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
12262 if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
12263 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
12264 PIPE_CONF_CHECK_BOOL(limited_color_range);
12265
12266 PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
12267 PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
12268 PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_infoframe);
12269
12270 PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
12271
12272 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12273 DRM_MODE_FLAG_INTERLACE);
12274
12275 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12276 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12277 DRM_MODE_FLAG_PHSYNC);
12278 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12279 DRM_MODE_FLAG_NHSYNC);
12280 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12281 DRM_MODE_FLAG_PVSYNC);
12282 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12283 DRM_MODE_FLAG_NVSYNC);
12284 }
12285
12286 PIPE_CONF_CHECK_X(gmch_pfit.control);
12287 /* pfit ratios are autocomputed by the hw on gen4+ */
12288 if (INTEL_GEN(dev_priv) < 4)
12289 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
12290 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12291
12292 if (!adjust) {
12293 PIPE_CONF_CHECK_I(pipe_src_w);
12294 PIPE_CONF_CHECK_I(pipe_src_h);
12295
12296 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled);
12297 if (current_config->pch_pfit.enabled) {
12298 PIPE_CONF_CHECK_X(pch_pfit.pos);
12299 PIPE_CONF_CHECK_X(pch_pfit.size);
12300 }
12301
12302 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12303 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
12304
12305 PIPE_CONF_CHECK_X(gamma_mode);
12306 if (IS_CHERRYVIEW(dev_priv))
12307 PIPE_CONF_CHECK_X(cgm_mode);
12308 else
12309 PIPE_CONF_CHECK_X(csc_mode);
12310 PIPE_CONF_CHECK_BOOL(gamma_enable);
12311 PIPE_CONF_CHECK_BOOL(csc_enable);
12312 }
12313
12314 PIPE_CONF_CHECK_BOOL(double_wide);
12315
12316 PIPE_CONF_CHECK_P(shared_dpll);
12317 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12318 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12319 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12320 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12321 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12322 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
12323 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12324 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12325 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12326 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
12327 PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
12328 PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
12329 PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
12330 PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
12331 PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
12332 PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
12333 PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
12334 PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
12335 PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
12336 PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
12337 PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
12338 PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl);
12339 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1);
12340 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl);
12341 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0);
12342 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1);
12343 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf);
12344 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock);
12345 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc);
12346 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias);
12347 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
12348
12349 PIPE_CONF_CHECK_X(dsi_pll.ctrl);
12350 PIPE_CONF_CHECK_X(dsi_pll.div);
12351
12352 if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
12353 PIPE_CONF_CHECK_I(pipe_bpp);
12354
12355 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12356 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12357
12358 PIPE_CONF_CHECK_I(min_voltage_level);
12359
12360 PIPE_CONF_CHECK_X(infoframes.enable);
12361 PIPE_CONF_CHECK_X(infoframes.gcp);
12362 PIPE_CONF_CHECK_INFOFRAME(avi);
12363 PIPE_CONF_CHECK_INFOFRAME(spd);
12364 PIPE_CONF_CHECK_INFOFRAME(hdmi);
12365
12366 #undef PIPE_CONF_CHECK_X
12367 #undef PIPE_CONF_CHECK_I
12368 #undef PIPE_CONF_CHECK_BOOL
12369 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE
12370 #undef PIPE_CONF_CHECK_P
12371 #undef PIPE_CONF_CHECK_FLAGS
12372 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12373 #undef PIPE_CONF_QUIRK
12374
12375 return ret;
12376 }
12377
12378 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
12379 const struct intel_crtc_state *pipe_config)
12380 {
12381 if (pipe_config->has_pch_encoder) {
12382 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
12383 &pipe_config->fdi_m_n);
12384 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
12385
12386 /*
12387 * FDI already provided one idea for the dotclock.
12388 * Yell if the encoder disagrees.
12389 */
12390 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
12391 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12392 fdi_dotclock, dotclock);
12393 }
12394 }
12395
12396 static void verify_wm_state(struct drm_crtc *crtc,
12397 struct drm_crtc_state *new_state)
12398 {
12399 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
12400 struct skl_hw_state {
12401 struct skl_ddb_entry ddb_y[I915_MAX_PLANES];
12402 struct skl_ddb_entry ddb_uv[I915_MAX_PLANES];
12403 struct skl_ddb_allocation ddb;
12404 struct skl_pipe_wm wm;
12405 } *hw;
12406 struct skl_ddb_allocation *sw_ddb;
12407 struct skl_pipe_wm *sw_wm;
12408 struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
12409 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12410 const enum pipe pipe = intel_crtc->pipe;
12411 int plane, level, max_level = ilk_wm_max_level(dev_priv);
12412
12413 if (INTEL_GEN(dev_priv) < 9 || !new_state->active)
12414 return;
12415
12416 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
12417 if (!hw)
12418 return;
12419
12420 skl_pipe_wm_get_hw_state(intel_crtc, &hw->wm);
12421 sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal;
12422
12423 skl_pipe_ddb_get_hw_state(intel_crtc, hw->ddb_y, hw->ddb_uv);
12424
12425 skl_ddb_get_hw_state(dev_priv, &hw->ddb);
12426 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12427
12428 if (INTEL_GEN(dev_priv) >= 11 &&
12429 hw->ddb.enabled_slices != sw_ddb->enabled_slices)
12430 DRM_ERROR("mismatch in DBUF Slices (expected %u, got %u)\n",
12431 sw_ddb->enabled_slices,
12432 hw->ddb.enabled_slices);
12433
12434 /* planes */
12435 for_each_universal_plane(dev_priv, pipe, plane) {
12436 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
12437
12438 hw_plane_wm = &hw->wm.planes[plane];
12439 sw_plane_wm = &sw_wm->planes[plane];
12440
12441 /* Watermarks */
12442 for (level = 0; level <= max_level; level++) {
12443 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
12444 &sw_plane_wm->wm[level]))
12445 continue;
12446
12447 DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
12448 pipe_name(pipe), plane + 1, level,
12449 sw_plane_wm->wm[level].plane_en,
12450 sw_plane_wm->wm[level].plane_res_b,
12451 sw_plane_wm->wm[level].plane_res_l,
12452 hw_plane_wm->wm[level].plane_en,
12453 hw_plane_wm->wm[level].plane_res_b,
12454 hw_plane_wm->wm[level].plane_res_l);
12455 }
12456
12457 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
12458 &sw_plane_wm->trans_wm)) {
12459 DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
12460 pipe_name(pipe), plane + 1,
12461 sw_plane_wm->trans_wm.plane_en,
12462 sw_plane_wm->trans_wm.plane_res_b,
12463 sw_plane_wm->trans_wm.plane_res_l,
12464 hw_plane_wm->trans_wm.plane_en,
12465 hw_plane_wm->trans_wm.plane_res_b,
12466 hw_plane_wm->trans_wm.plane_res_l);
12467 }
12468
12469 /* DDB */
12470 hw_ddb_entry = &hw->ddb_y[plane];
12471 sw_ddb_entry = &to_intel_crtc_state(new_state)->wm.skl.plane_ddb_y[plane];
12472
12473 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
12474 DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
12475 pipe_name(pipe), plane + 1,
12476 sw_ddb_entry->start, sw_ddb_entry->end,
12477 hw_ddb_entry->start, hw_ddb_entry->end);
12478 }
12479 }
12480
12481 /*
12482 * cursor
12483 * If the cursor plane isn't active, we may not have updated it's ddb
12484 * allocation. In that case since the ddb allocation will be updated
12485 * once the plane becomes visible, we can skip this check
12486 */
12487 if (1) {
12488 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
12489
12490 hw_plane_wm = &hw->wm.planes[PLANE_CURSOR];
12491 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
12492
12493 /* Watermarks */
12494 for (level = 0; level <= max_level; level++) {
12495 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
12496 &sw_plane_wm->wm[level]))
12497 continue;
12498
12499 DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
12500 pipe_name(pipe), level,
12501 sw_plane_wm->wm[level].plane_en,
12502 sw_plane_wm->wm[level].plane_res_b,
12503 sw_plane_wm->wm[level].plane_res_l,
12504 hw_plane_wm->wm[level].plane_en,
12505 hw_plane_wm->wm[level].plane_res_b,
12506 hw_plane_wm->wm[level].plane_res_l);
12507 }
12508
12509 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
12510 &sw_plane_wm->trans_wm)) {
12511 DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
12512 pipe_name(pipe),
12513 sw_plane_wm->trans_wm.plane_en,
12514 sw_plane_wm->trans_wm.plane_res_b,
12515 sw_plane_wm->trans_wm.plane_res_l,
12516 hw_plane_wm->trans_wm.plane_en,
12517 hw_plane_wm->trans_wm.plane_res_b,
12518 hw_plane_wm->trans_wm.plane_res_l);
12519 }
12520
12521 /* DDB */
12522 hw_ddb_entry = &hw->ddb_y[PLANE_CURSOR];
12523 sw_ddb_entry = &to_intel_crtc_state(new_state)->wm.skl.plane_ddb_y[PLANE_CURSOR];
12524
12525 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
12526 DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
12527 pipe_name(pipe),
12528 sw_ddb_entry->start, sw_ddb_entry->end,
12529 hw_ddb_entry->start, hw_ddb_entry->end);
12530 }
12531 }
12532
12533 kfree(hw);
12534 }
12535
12536 static void
12537 verify_connector_state(struct drm_device *dev,
12538 struct drm_atomic_state *state,
12539 struct drm_crtc *crtc)
12540 {
12541 struct drm_connector *connector;
12542 struct drm_connector_state *new_conn_state;
12543 int i;
12544
12545 for_each_new_connector_in_state(state, connector, new_conn_state, i) {
12546 struct drm_encoder *encoder = connector->encoder;
12547 struct drm_crtc_state *crtc_state = NULL;
12548
12549 if (new_conn_state->crtc != crtc)
12550 continue;
12551
12552 if (crtc)
12553 crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
12554
12555 intel_connector_verify_state(crtc_state, new_conn_state);
12556
12557 I915_STATE_WARN(new_conn_state->best_encoder != encoder,
12558 "connector's atomic encoder doesn't match legacy encoder\n");
12559 }
12560 }
12561
12562 static void
12563 verify_encoder_state(struct drm_device *dev, struct drm_atomic_state *state)
12564 {
12565 struct intel_encoder *encoder;
12566 struct drm_connector *connector;
12567 struct drm_connector_state *old_conn_state, *new_conn_state;
12568 int i;
12569
12570 for_each_intel_encoder(dev, encoder) {
12571 bool enabled = false, found = false;
12572 enum pipe pipe;
12573
12574 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12575 encoder->base.base.id,
12576 encoder->base.name);
12577
12578 for_each_oldnew_connector_in_state(state, connector, old_conn_state,
12579 new_conn_state, i) {
12580 if (old_conn_state->best_encoder == &encoder->base)
12581 found = true;
12582
12583 if (new_conn_state->best_encoder != &encoder->base)
12584 continue;
12585 found = enabled = true;
12586
12587 I915_STATE_WARN(new_conn_state->crtc !=
12588 encoder->base.crtc,
12589 "connector's crtc doesn't match encoder crtc\n");
12590 }
12591
12592 if (!found)
12593 continue;
12594
12595 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12596 "encoder's enabled state mismatch "
12597 "(expected %i, found %i)\n",
12598 !!encoder->base.crtc, enabled);
12599
12600 if (!encoder->base.crtc) {
12601 bool active;
12602
12603 active = encoder->get_hw_state(encoder, &pipe);
12604 I915_STATE_WARN(active,
12605 "encoder detached but still enabled on pipe %c.\n",
12606 pipe_name(pipe));
12607 }
12608 }
12609 }
12610
12611 static void
12612 verify_crtc_state(struct drm_crtc *crtc,
12613 struct drm_crtc_state *old_crtc_state,
12614 struct drm_crtc_state *new_crtc_state)
12615 {
12616 struct drm_device *dev = crtc->dev;
12617 struct drm_i915_private *dev_priv = to_i915(dev);
12618 struct intel_encoder *encoder;
12619 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12620 struct intel_crtc_state *pipe_config, *sw_config;
12621 struct drm_atomic_state *old_state;
12622 bool active;
12623
12624 old_state = old_crtc_state->state;
12625 __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
12626 pipe_config = to_intel_crtc_state(old_crtc_state);
12627 memset(pipe_config, 0, sizeof(*pipe_config));
12628 pipe_config->base.crtc = crtc;
12629 pipe_config->base.state = old_state;
12630
12631 DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
12632
12633 active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
12634
12635 /* we keep both pipes enabled on 830 */
12636 if (IS_I830(dev_priv))
12637 active = new_crtc_state->active;
12638
12639 I915_STATE_WARN(new_crtc_state->active != active,
12640 "crtc active state doesn't match with hw state "
12641 "(expected %i, found %i)\n", new_crtc_state->active, active);
12642
12643 I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
12644 "transitional active state does not match atomic hw state "
12645 "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
12646
12647 for_each_encoder_on_crtc(dev, crtc, encoder) {
12648 enum pipe pipe;
12649
12650 active = encoder->get_hw_state(encoder, &pipe);
12651 I915_STATE_WARN(active != new_crtc_state->active,
12652 "[ENCODER:%i] active %i with crtc active %i\n",
12653 encoder->base.base.id, active, new_crtc_state->active);
12654
12655 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12656 "Encoder connected to wrong pipe %c\n",
12657 pipe_name(pipe));
12658
12659 if (active)
12660 encoder->get_config(encoder, pipe_config);
12661 }
12662
12663 intel_crtc_compute_pixel_rate(pipe_config);
12664
12665 if (!new_crtc_state->active)
12666 return;
12667
12668 intel_pipe_config_sanity_check(dev_priv, pipe_config);
12669
12670 sw_config = to_intel_crtc_state(new_crtc_state);
12671 if (!intel_pipe_config_compare(dev_priv, sw_config,
12672 pipe_config, false)) {
12673 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12674 intel_dump_pipe_config(intel_crtc, pipe_config,
12675 "[hw state]");
12676 intel_dump_pipe_config(intel_crtc, sw_config,
12677 "[sw state]");
12678 }
12679 }
12680
12681 static void
12682 intel_verify_planes(struct intel_atomic_state *state)
12683 {
12684 struct intel_plane *plane;
12685 const struct intel_plane_state *plane_state;
12686 int i;
12687
12688 for_each_new_intel_plane_in_state(state, plane,
12689 plane_state, i)
12690 assert_plane(plane, plane_state->slave ||
12691 plane_state->base.visible);
12692 }
12693
12694 static void
12695 verify_single_dpll_state(struct drm_i915_private *dev_priv,
12696 struct intel_shared_dpll *pll,
12697 struct drm_crtc *crtc,
12698 struct drm_crtc_state *new_state)
12699 {
12700 struct intel_dpll_hw_state dpll_hw_state;
12701 unsigned int crtc_mask;
12702 bool active;
12703
12704 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12705
12706 DRM_DEBUG_KMS("%s\n", pll->info->name);
12707
12708 active = pll->info->funcs->get_hw_state(dev_priv, pll, &dpll_hw_state);
12709
12710 if (!(pll->info->flags & INTEL_DPLL_ALWAYS_ON)) {
12711 I915_STATE_WARN(!pll->on && pll->active_mask,
12712 "pll in active use but not on in sw tracking\n");
12713 I915_STATE_WARN(pll->on && !pll->active_mask,
12714 "pll is on but not used by any active crtc\n");
12715 I915_STATE_WARN(pll->on != active,
12716 "pll on state mismatch (expected %i, found %i)\n",
12717 pll->on, active);
12718 }
12719
12720 if (!crtc) {
12721 I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask,
12722 "more active pll users than references: %x vs %x\n",
12723 pll->active_mask, pll->state.crtc_mask);
12724
12725 return;
12726 }
12727
12728 crtc_mask = drm_crtc_mask(crtc);
12729
12730 if (new_state->active)
12731 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
12732 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
12733 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
12734 else
12735 I915_STATE_WARN(pll->active_mask & crtc_mask,
12736 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
12737 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
12738
12739 I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
12740 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
12741 crtc_mask, pll->state.crtc_mask);
12742
12743 I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
12744 &dpll_hw_state,
12745 sizeof(dpll_hw_state)),
12746 "pll hw state mismatch\n");
12747 }
12748
12749 static void
12750 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
12751 struct drm_crtc_state *old_crtc_state,
12752 struct drm_crtc_state *new_crtc_state)
12753 {
12754 struct drm_i915_private *dev_priv = to_i915(dev);
12755 struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
12756 struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
12757
12758 if (new_state->shared_dpll)
12759 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
12760
12761 if (old_state->shared_dpll &&
12762 old_state->shared_dpll != new_state->shared_dpll) {
12763 unsigned int crtc_mask = drm_crtc_mask(crtc);
12764 struct intel_shared_dpll *pll = old_state->shared_dpll;
12765
12766 I915_STATE_WARN(pll->active_mask & crtc_mask,
12767 "pll active mismatch (didn't expect pipe %c in active mask)\n",
12768 pipe_name(drm_crtc_index(crtc)));
12769 I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
12770 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
12771 pipe_name(drm_crtc_index(crtc)));
12772 }
12773 }
12774
12775 static void
12776 intel_modeset_verify_crtc(struct drm_crtc *crtc,
12777 struct drm_atomic_state *state,
12778 struct drm_crtc_state *old_state,
12779 struct drm_crtc_state *new_state)
12780 {
12781 if (!needs_modeset(new_state) &&
12782 !to_intel_crtc_state(new_state)->update_pipe)
12783 return;
12784
12785 verify_wm_state(crtc, new_state);
12786 verify_connector_state(crtc->dev, state, crtc);
12787 verify_crtc_state(crtc, old_state, new_state);
12788 verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
12789 }
12790
12791 static void
12792 verify_disabled_dpll_state(struct drm_device *dev)
12793 {
12794 struct drm_i915_private *dev_priv = to_i915(dev);
12795 int i;
12796
12797 for (i = 0; i < dev_priv->num_shared_dpll; i++)
12798 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
12799 }
12800
12801 static void
12802 intel_modeset_verify_disabled(struct drm_device *dev,
12803 struct drm_atomic_state *state)
12804 {
12805 verify_encoder_state(dev, state);
12806 verify_connector_state(dev, state, NULL);
12807 verify_disabled_dpll_state(dev);
12808 }
12809
12810 static void update_scanline_offset(const struct intel_crtc_state *crtc_state)
12811 {
12812 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
12813 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12814
12815 /*
12816 * The scanline counter increments at the leading edge of hsync.
12817 *
12818 * On most platforms it starts counting from vtotal-1 on the
12819 * first active line. That means the scanline counter value is
12820 * always one less than what we would expect. Ie. just after
12821 * start of vblank, which also occurs at start of hsync (on the
12822 * last active line), the scanline counter will read vblank_start-1.
12823 *
12824 * On gen2 the scanline counter starts counting from 1 instead
12825 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12826 * to keep the value positive), instead of adding one.
12827 *
12828 * On HSW+ the behaviour of the scanline counter depends on the output
12829 * type. For DP ports it behaves like most other platforms, but on HDMI
12830 * there's an extra 1 line difference. So we need to add two instead of
12831 * one to the value.
12832 *
12833 * On VLV/CHV DSI the scanline counter would appear to increment
12834 * approx. 1/3 of a scanline before start of vblank. Unfortunately
12835 * that means we can't tell whether we're in vblank or not while
12836 * we're on that particular line. We must still set scanline_offset
12837 * to 1 so that the vblank timestamps come out correct when we query
12838 * the scanline counter from within the vblank interrupt handler.
12839 * However if queried just before the start of vblank we'll get an
12840 * answer that's slightly in the future.
12841 */
12842 if (IS_GEN(dev_priv, 2)) {
12843 const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
12844 int vtotal;
12845
12846 vtotal = adjusted_mode->crtc_vtotal;
12847 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
12848 vtotal /= 2;
12849
12850 crtc->scanline_offset = vtotal - 1;
12851 } else if (HAS_DDI(dev_priv) &&
12852 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
12853 crtc->scanline_offset = 2;
12854 } else
12855 crtc->scanline_offset = 1;
12856 }
12857
12858 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
12859 {
12860 struct drm_device *dev = state->dev;
12861 struct drm_i915_private *dev_priv = to_i915(dev);
12862 struct drm_crtc *crtc;
12863 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12864 int i;
12865
12866 if (!dev_priv->display.crtc_compute_clock)
12867 return;
12868
12869 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12870 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12871 struct intel_shared_dpll *old_dpll =
12872 to_intel_crtc_state(old_crtc_state)->shared_dpll;
12873
12874 if (!needs_modeset(new_crtc_state))
12875 continue;
12876
12877 to_intel_crtc_state(new_crtc_state)->shared_dpll = NULL;
12878
12879 if (!old_dpll)
12880 continue;
12881
12882 intel_release_shared_dpll(old_dpll, intel_crtc, state);
12883 }
12884 }
12885
12886 /*
12887 * This implements the workaround described in the "notes" section of the mode
12888 * set sequence documentation. When going from no pipes or single pipe to
12889 * multiple pipes, and planes are enabled after the pipe, we need to wait at
12890 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12891 */
12892 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12893 {
12894 struct drm_crtc_state *crtc_state;
12895 struct intel_crtc *intel_crtc;
12896 struct drm_crtc *crtc;
12897 struct intel_crtc_state *first_crtc_state = NULL;
12898 struct intel_crtc_state *other_crtc_state = NULL;
12899 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12900 int i;
12901
12902 /* look at all crtc's that are going to be enabled in during modeset */
12903 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
12904 intel_crtc = to_intel_crtc(crtc);
12905
12906 if (!crtc_state->active || !needs_modeset(crtc_state))
12907 continue;
12908
12909 if (first_crtc_state) {
12910 other_crtc_state = to_intel_crtc_state(crtc_state);
12911 break;
12912 } else {
12913 first_crtc_state = to_intel_crtc_state(crtc_state);
12914 first_pipe = intel_crtc->pipe;
12915 }
12916 }
12917
12918 /* No workaround needed? */
12919 if (!first_crtc_state)
12920 return 0;
12921
12922 /* w/a possibly needed, check how many crtc's are already enabled. */
12923 for_each_intel_crtc(state->dev, intel_crtc) {
12924 struct intel_crtc_state *pipe_config;
12925
12926 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12927 if (IS_ERR(pipe_config))
12928 return PTR_ERR(pipe_config);
12929
12930 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12931
12932 if (!pipe_config->base.active ||
12933 needs_modeset(&pipe_config->base))
12934 continue;
12935
12936 /* 2 or more enabled crtcs means no need for w/a */
12937 if (enabled_pipe != INVALID_PIPE)
12938 return 0;
12939
12940 enabled_pipe = intel_crtc->pipe;
12941 }
12942
12943 if (enabled_pipe != INVALID_PIPE)
12944 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12945 else if (other_crtc_state)
12946 other_crtc_state->hsw_workaround_pipe = first_pipe;
12947
12948 return 0;
12949 }
12950
12951 static int intel_lock_all_pipes(struct drm_atomic_state *state)
12952 {
12953 struct drm_crtc *crtc;
12954
12955 /* Add all pipes to the state */
12956 for_each_crtc(state->dev, crtc) {
12957 struct drm_crtc_state *crtc_state;
12958
12959 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12960 if (IS_ERR(crtc_state))
12961 return PTR_ERR(crtc_state);
12962 }
12963
12964 return 0;
12965 }
12966
12967 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12968 {
12969 struct drm_crtc *crtc;
12970
12971 /*
12972 * Add all pipes to the state, and force
12973 * a modeset on all the active ones.
12974 */
12975 for_each_crtc(state->dev, crtc) {
12976 struct drm_crtc_state *crtc_state;
12977 int ret;
12978
12979 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12980 if (IS_ERR(crtc_state))
12981 return PTR_ERR(crtc_state);
12982
12983 if (!crtc_state->active || needs_modeset(crtc_state))
12984 continue;
12985
12986 crtc_state->mode_changed = true;
12987
12988 ret = drm_atomic_add_affected_connectors(state, crtc);
12989 if (ret)
12990 return ret;
12991
12992 ret = drm_atomic_add_affected_planes(state, crtc);
12993 if (ret)
12994 return ret;
12995 }
12996
12997 return 0;
12998 }
12999
13000 static int intel_modeset_checks(struct drm_atomic_state *state)
13001 {
13002 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13003 struct drm_i915_private *dev_priv = to_i915(state->dev);
13004 struct drm_crtc *crtc;
13005 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
13006 int ret = 0, i;
13007
13008 if (!check_digital_port_conflicts(state)) {
13009 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13010 return -EINVAL;
13011 }
13012
13013 /* keep the current setting */
13014 if (!intel_state->cdclk.force_min_cdclk_changed)
13015 intel_state->cdclk.force_min_cdclk =
13016 dev_priv->cdclk.force_min_cdclk;
13017
13018 intel_state->modeset = true;
13019 intel_state->active_crtcs = dev_priv->active_crtcs;
13020 intel_state->cdclk.logical = dev_priv->cdclk.logical;
13021 intel_state->cdclk.actual = dev_priv->cdclk.actual;
13022 intel_state->cdclk.pipe = INVALID_PIPE;
13023
13024 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
13025 if (new_crtc_state->active)
13026 intel_state->active_crtcs |= 1 << i;
13027 else
13028 intel_state->active_crtcs &= ~(1 << i);
13029
13030 if (old_crtc_state->active != new_crtc_state->active)
13031 intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
13032 }
13033
13034 /*
13035 * See if the config requires any additional preparation, e.g.
13036 * to adjust global state with pipes off. We need to do this
13037 * here so we can get the modeset_pipe updated config for the new
13038 * mode set on this crtc. For other crtcs we need to use the
13039 * adjusted_mode bits in the crtc directly.
13040 */
13041 if (dev_priv->display.modeset_calc_cdclk) {
13042 enum pipe pipe;
13043
13044 ret = dev_priv->display.modeset_calc_cdclk(state);
13045 if (ret < 0)
13046 return ret;
13047
13048 /*
13049 * Writes to dev_priv->cdclk.logical must protected by
13050 * holding all the crtc locks, even if we don't end up
13051 * touching the hardware
13052 */
13053 if (intel_cdclk_changed(&dev_priv->cdclk.logical,
13054 &intel_state->cdclk.logical)) {
13055 ret = intel_lock_all_pipes(state);
13056 if (ret < 0)
13057 return ret;
13058 }
13059
13060 if (is_power_of_2(intel_state->active_crtcs)) {
13061 struct drm_crtc *crtc;
13062 struct drm_crtc_state *crtc_state;
13063
13064 pipe = ilog2(intel_state->active_crtcs);
13065 crtc = &intel_get_crtc_for_pipe(dev_priv, pipe)->base;
13066 crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
13067 if (crtc_state && needs_modeset(crtc_state))
13068 pipe = INVALID_PIPE;
13069 } else {
13070 pipe = INVALID_PIPE;
13071 }
13072
13073 /* All pipes must be switched off while we change the cdclk. */
13074 if (pipe != INVALID_PIPE &&
13075 intel_cdclk_needs_cd2x_update(dev_priv,
13076 &dev_priv->cdclk.actual,
13077 &intel_state->cdclk.actual)) {
13078 ret = intel_lock_all_pipes(state);
13079 if (ret < 0)
13080 return ret;
13081
13082 intel_state->cdclk.pipe = pipe;
13083 } else if (intel_cdclk_needs_modeset(&dev_priv->cdclk.actual,
13084 &intel_state->cdclk.actual)) {
13085 ret = intel_modeset_all_pipes(state);
13086 if (ret < 0)
13087 return ret;
13088
13089 intel_state->cdclk.pipe = INVALID_PIPE;
13090 }
13091
13092 DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n",
13093 intel_state->cdclk.logical.cdclk,
13094 intel_state->cdclk.actual.cdclk);
13095 DRM_DEBUG_KMS("New voltage level calculated to be logical %u, actual %u\n",
13096 intel_state->cdclk.logical.voltage_level,
13097 intel_state->cdclk.actual.voltage_level);
13098 }
13099
13100 intel_modeset_clear_plls(state);
13101
13102 if (IS_HASWELL(dev_priv))
13103 return haswell_mode_set_planes_workaround(state);
13104
13105 return 0;
13106 }
13107
13108 /*
13109 * Handle calculation of various watermark data at the end of the atomic check
13110 * phase. The code here should be run after the per-crtc and per-plane 'check'
13111 * handlers to ensure that all derived state has been updated.
13112 */
13113 static int calc_watermark_data(struct intel_atomic_state *state)
13114 {
13115 struct drm_device *dev = state->base.dev;
13116 struct drm_i915_private *dev_priv = to_i915(dev);
13117
13118 /* Is there platform-specific watermark information to calculate? */
13119 if (dev_priv->display.compute_global_watermarks)
13120 return dev_priv->display.compute_global_watermarks(state);
13121
13122 return 0;
13123 }
13124
13125 /**
13126 * intel_atomic_check - validate state object
13127 * @dev: drm device
13128 * @state: state to validate
13129 */
13130 static int intel_atomic_check(struct drm_device *dev,
13131 struct drm_atomic_state *state)
13132 {
13133 struct drm_i915_private *dev_priv = to_i915(dev);
13134 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13135 struct drm_crtc *crtc;
13136 struct drm_crtc_state *old_crtc_state, *crtc_state;
13137 int ret, i;
13138 bool any_ms = intel_state->cdclk.force_min_cdclk_changed;
13139
13140 /* Catch I915_MODE_FLAG_INHERITED */
13141 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
13142 crtc_state, i) {
13143 if (crtc_state->mode.private_flags !=
13144 old_crtc_state->mode.private_flags)
13145 crtc_state->mode_changed = true;
13146 }
13147
13148 ret = drm_atomic_helper_check_modeset(dev, state);
13149 if (ret)
13150 return ret;
13151
13152 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, crtc_state, i) {
13153 struct intel_crtc_state *pipe_config =
13154 to_intel_crtc_state(crtc_state);
13155
13156 if (!needs_modeset(crtc_state))
13157 continue;
13158
13159 if (!crtc_state->enable) {
13160 any_ms = true;
13161 continue;
13162 }
13163
13164 ret = intel_modeset_pipe_config(crtc, pipe_config);
13165 if (ret == -EDEADLK)
13166 return ret;
13167 if (ret) {
13168 intel_dump_pipe_config(to_intel_crtc(crtc),
13169 pipe_config, "[failed]");
13170 return ret;
13171 }
13172
13173 if (intel_pipe_config_compare(dev_priv,
13174 to_intel_crtc_state(old_crtc_state),
13175 pipe_config, true)) {
13176 crtc_state->mode_changed = false;
13177 pipe_config->update_pipe = true;
13178 }
13179
13180 if (needs_modeset(crtc_state))
13181 any_ms = true;
13182
13183 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13184 needs_modeset(crtc_state) ?
13185 "[modeset]" : "[fastset]");
13186 }
13187
13188 ret = drm_dp_mst_atomic_check(state);
13189 if (ret)
13190 return ret;
13191
13192 if (any_ms) {
13193 ret = intel_modeset_checks(state);
13194
13195 if (ret)
13196 return ret;
13197 } else {
13198 intel_state->cdclk.logical = dev_priv->cdclk.logical;
13199 }
13200
13201 ret = icl_add_linked_planes(intel_state);
13202 if (ret)
13203 return ret;
13204
13205 ret = drm_atomic_helper_check_planes(dev, state);
13206 if (ret)
13207 return ret;
13208
13209 intel_fbc_choose_crtc(dev_priv, intel_state);
13210 return calc_watermark_data(intel_state);
13211 }
13212
13213 static int intel_atomic_prepare_commit(struct drm_device *dev,
13214 struct drm_atomic_state *state)
13215 {
13216 return drm_atomic_helper_prepare_planes(dev, state);
13217 }
13218
13219 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
13220 {
13221 struct drm_device *dev = crtc->base.dev;
13222 struct drm_vblank_crtc *vblank = &dev->vblank[drm_crtc_index(&crtc->base)];
13223
13224 if (!vblank->max_vblank_count)
13225 return (u32)drm_crtc_accurate_vblank_count(&crtc->base);
13226
13227 return dev->driver->get_vblank_counter(dev, crtc->pipe);
13228 }
13229
13230 static void intel_update_crtc(struct drm_crtc *crtc,
13231 struct drm_atomic_state *state,
13232 struct drm_crtc_state *old_crtc_state,
13233 struct drm_crtc_state *new_crtc_state)
13234 {
13235 struct drm_device *dev = crtc->dev;
13236 struct drm_i915_private *dev_priv = to_i915(dev);
13237 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13238 struct intel_crtc_state *pipe_config = to_intel_crtc_state(new_crtc_state);
13239 bool modeset = needs_modeset(new_crtc_state);
13240 struct intel_plane_state *new_plane_state =
13241 intel_atomic_get_new_plane_state(to_intel_atomic_state(state),
13242 to_intel_plane(crtc->primary));
13243
13244 if (modeset) {
13245 update_scanline_offset(pipe_config);
13246 dev_priv->display.crtc_enable(pipe_config, state);
13247
13248 /* vblanks work again, re-enable pipe CRC. */
13249 intel_crtc_enable_pipe_crc(intel_crtc);
13250 } else {
13251 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
13252 pipe_config);
13253
13254 if (pipe_config->update_pipe)
13255 intel_encoders_update_pipe(crtc, pipe_config, state);
13256 }
13257
13258 if (pipe_config->update_pipe && !pipe_config->enable_fbc)
13259 intel_fbc_disable(intel_crtc);
13260 else if (new_plane_state)
13261 intel_fbc_enable(intel_crtc, pipe_config, new_plane_state);
13262
13263 intel_begin_crtc_commit(crtc, old_crtc_state);
13264
13265 if (INTEL_GEN(dev_priv) >= 9)
13266 skl_update_planes_on_crtc(to_intel_atomic_state(state), intel_crtc);
13267 else
13268 i9xx_update_planes_on_crtc(to_intel_atomic_state(state), intel_crtc);
13269
13270 intel_finish_crtc_commit(crtc, old_crtc_state);
13271 }
13272
13273 static void intel_update_crtcs(struct drm_atomic_state *state)
13274 {
13275 struct drm_crtc *crtc;
13276 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
13277 int i;
13278
13279 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
13280 if (!new_crtc_state->active)
13281 continue;
13282
13283 intel_update_crtc(crtc, state, old_crtc_state,
13284 new_crtc_state);
13285 }
13286 }
13287
13288 static void skl_update_crtcs(struct drm_atomic_state *state)
13289 {
13290 struct drm_i915_private *dev_priv = to_i915(state->dev);
13291 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13292 struct drm_crtc *crtc;
13293 struct intel_crtc *intel_crtc;
13294 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
13295 struct intel_crtc_state *cstate;
13296 unsigned int updated = 0;
13297 bool progress;
13298 enum pipe pipe;
13299 int i;
13300 u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices;
13301 u8 required_slices = intel_state->wm_results.ddb.enabled_slices;
13302 struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
13303
13304 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)
13305 /* ignore allocations for crtc's that have been turned off. */
13306 if (new_crtc_state->active)
13307 entries[i] = to_intel_crtc_state(old_crtc_state)->wm.skl.ddb;
13308
13309 /* If 2nd DBuf slice required, enable it here */
13310 if (INTEL_GEN(dev_priv) >= 11 && required_slices > hw_enabled_slices)
13311 icl_dbuf_slices_update(dev_priv, required_slices);
13312
13313 /*
13314 * Whenever the number of active pipes changes, we need to make sure we
13315 * update the pipes in the right order so that their ddb allocations
13316 * never overlap with eachother inbetween CRTC updates. Otherwise we'll
13317 * cause pipe underruns and other bad stuff.
13318 */
13319 do {
13320 progress = false;
13321
13322 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
13323 bool vbl_wait = false;
13324 unsigned int cmask = drm_crtc_mask(crtc);
13325
13326 intel_crtc = to_intel_crtc(crtc);
13327 cstate = to_intel_crtc_state(new_crtc_state);
13328 pipe = intel_crtc->pipe;
13329
13330 if (updated & cmask || !cstate->base.active)
13331 continue;
13332
13333 if (skl_ddb_allocation_overlaps(&cstate->wm.skl.ddb,
13334 entries,
13335 INTEL_INFO(dev_priv)->num_pipes, i))
13336 continue;
13337
13338 updated |= cmask;
13339 entries[i] = cstate->wm.skl.ddb;
13340
13341 /*
13342 * If this is an already active pipe, it's DDB changed,
13343 * and this isn't the last pipe that needs updating
13344 * then we need to wait for a vblank to pass for the
13345 * new ddb allocation to take effect.
13346 */
13347 if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb,
13348 &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) &&
13349 !new_crtc_state->active_changed &&
13350 intel_state->wm_results.dirty_pipes != updated)
13351 vbl_wait = true;
13352
13353 intel_update_crtc(crtc, state, old_crtc_state,
13354 new_crtc_state);
13355
13356 if (vbl_wait)
13357 intel_wait_for_vblank(dev_priv, pipe);
13358
13359 progress = true;
13360 }
13361 } while (progress);
13362
13363 /* If 2nd DBuf slice is no more required disable it */
13364 if (INTEL_GEN(dev_priv) >= 11 && required_slices < hw_enabled_slices)
13365 icl_dbuf_slices_update(dev_priv, required_slices);
13366 }
13367
13368 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
13369 {
13370 struct intel_atomic_state *state, *next;
13371 struct llist_node *freed;
13372
13373 freed = llist_del_all(&dev_priv->atomic_helper.free_list);
13374 llist_for_each_entry_safe(state, next, freed, freed)
13375 drm_atomic_state_put(&state->base);
13376 }
13377
13378 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
13379 {
13380 struct drm_i915_private *dev_priv =
13381 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
13382
13383 intel_atomic_helper_free_state(dev_priv);
13384 }
13385
13386 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state)
13387 {
13388 struct wait_queue_entry wait_fence, wait_reset;
13389 struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev);
13390
13391 init_wait_entry(&wait_fence, 0);
13392 init_wait_entry(&wait_reset, 0);
13393 for (;;) {
13394 prepare_to_wait(&intel_state->commit_ready.wait,
13395 &wait_fence, TASK_UNINTERRUPTIBLE);
13396 prepare_to_wait(&dev_priv->gpu_error.wait_queue,
13397 &wait_reset, TASK_UNINTERRUPTIBLE);
13398
13399
13400 if (i915_sw_fence_done(&intel_state->commit_ready)
13401 || test_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags))
13402 break;
13403
13404 schedule();
13405 }
13406 finish_wait(&intel_state->commit_ready.wait, &wait_fence);
13407 finish_wait(&dev_priv->gpu_error.wait_queue, &wait_reset);
13408 }
13409
13410 static void intel_atomic_cleanup_work(struct work_struct *work)
13411 {
13412 struct drm_atomic_state *state =
13413 container_of(work, struct drm_atomic_state, commit_work);
13414 struct drm_i915_private *i915 = to_i915(state->dev);
13415
13416 drm_atomic_helper_cleanup_planes(&i915->drm, state);
13417 drm_atomic_helper_commit_cleanup_done(state);
13418 drm_atomic_state_put(state);
13419
13420 intel_atomic_helper_free_state(i915);
13421 }
13422
13423 static void intel_atomic_commit_tail(struct drm_atomic_state *state)
13424 {
13425 struct drm_device *dev = state->dev;
13426 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13427 struct drm_i915_private *dev_priv = to_i915(dev);
13428 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
13429 struct intel_crtc_state *new_intel_crtc_state, *old_intel_crtc_state;
13430 struct drm_crtc *crtc;
13431 struct intel_crtc *intel_crtc;
13432 u64 put_domains[I915_MAX_PIPES] = {};
13433 intel_wakeref_t wakeref = 0;
13434 int i;
13435
13436 intel_atomic_commit_fence_wait(intel_state);
13437
13438 drm_atomic_helper_wait_for_dependencies(state);
13439
13440 if (intel_state->modeset)
13441 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
13442
13443 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
13444 old_intel_crtc_state = to_intel_crtc_state(old_crtc_state);
13445 new_intel_crtc_state = to_intel_crtc_state(new_crtc_state);
13446 intel_crtc = to_intel_crtc(crtc);
13447
13448 if (needs_modeset(new_crtc_state) ||
13449 to_intel_crtc_state(new_crtc_state)->update_pipe) {
13450
13451 put_domains[intel_crtc->pipe] =
13452 modeset_get_crtc_power_domains(crtc,
13453 new_intel_crtc_state);
13454 }
13455
13456 if (!needs_modeset(new_crtc_state))
13457 continue;
13458
13459 intel_pre_plane_update(old_intel_crtc_state, new_intel_crtc_state);
13460
13461 if (old_crtc_state->active) {
13462 intel_crtc_disable_planes(intel_state, intel_crtc);
13463
13464 /*
13465 * We need to disable pipe CRC before disabling the pipe,
13466 * or we race against vblank off.
13467 */
13468 intel_crtc_disable_pipe_crc(intel_crtc);
13469
13470 dev_priv->display.crtc_disable(old_intel_crtc_state, state);
13471 intel_crtc->active = false;
13472 intel_fbc_disable(intel_crtc);
13473 intel_disable_shared_dpll(old_intel_crtc_state);
13474
13475 /*
13476 * Underruns don't always raise
13477 * interrupts, so check manually.
13478 */
13479 intel_check_cpu_fifo_underruns(dev_priv);
13480 intel_check_pch_fifo_underruns(dev_priv);
13481
13482 /* FIXME unify this for all platforms */
13483 if (!new_crtc_state->active &&
13484 !HAS_GMCH(dev_priv) &&
13485 dev_priv->display.initial_watermarks)
13486 dev_priv->display.initial_watermarks(intel_state,
13487 new_intel_crtc_state);
13488 }
13489 }
13490
13491 /* FIXME: Eventually get rid of our intel_crtc->config pointer */
13492 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i)
13493 to_intel_crtc(crtc)->config = to_intel_crtc_state(new_crtc_state);
13494
13495 if (intel_state->modeset) {
13496 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13497
13498 intel_set_cdclk_pre_plane_update(dev_priv,
13499 &intel_state->cdclk.actual,
13500 &dev_priv->cdclk.actual,
13501 intel_state->cdclk.pipe);
13502
13503 /*
13504 * SKL workaround: bspec recommends we disable the SAGV when we
13505 * have more then one pipe enabled
13506 */
13507 if (!intel_can_enable_sagv(state))
13508 intel_disable_sagv(dev_priv);
13509
13510 intel_modeset_verify_disabled(dev, state);
13511 }
13512
13513 /* Complete the events for pipes that have now been disabled */
13514 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
13515 bool modeset = needs_modeset(new_crtc_state);
13516
13517 /* Complete events for now disable pipes here. */
13518 if (modeset && !new_crtc_state->active && new_crtc_state->event) {
13519 spin_lock_irq(&dev->event_lock);
13520 drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
13521 spin_unlock_irq(&dev->event_lock);
13522
13523 new_crtc_state->event = NULL;
13524 }
13525 }
13526
13527 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13528 dev_priv->display.update_crtcs(state);
13529
13530 if (intel_state->modeset)
13531 intel_set_cdclk_post_plane_update(dev_priv,
13532 &intel_state->cdclk.actual,
13533 &dev_priv->cdclk.actual,
13534 intel_state->cdclk.pipe);
13535
13536 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
13537 * already, but still need the state for the delayed optimization. To
13538 * fix this:
13539 * - wrap the optimization/post_plane_update stuff into a per-crtc work.
13540 * - schedule that vblank worker _before_ calling hw_done
13541 * - at the start of commit_tail, cancel it _synchrously
13542 * - switch over to the vblank wait helper in the core after that since
13543 * we don't need out special handling any more.
13544 */
13545 drm_atomic_helper_wait_for_flip_done(dev, state);
13546
13547 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
13548 new_intel_crtc_state = to_intel_crtc_state(new_crtc_state);
13549
13550 if (new_crtc_state->active &&
13551 !needs_modeset(new_crtc_state) &&
13552 (new_intel_crtc_state->base.color_mgmt_changed ||
13553 new_intel_crtc_state->update_pipe))
13554 intel_color_load_luts(new_intel_crtc_state);
13555 }
13556
13557 /*
13558 * Now that the vblank has passed, we can go ahead and program the
13559 * optimal watermarks on platforms that need two-step watermark
13560 * programming.
13561 *
13562 * TODO: Move this (and other cleanup) to an async worker eventually.
13563 */
13564 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
13565 new_intel_crtc_state = to_intel_crtc_state(new_crtc_state);
13566
13567 if (dev_priv->display.optimize_watermarks)
13568 dev_priv->display.optimize_watermarks(intel_state,
13569 new_intel_crtc_state);
13570 }
13571
13572 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
13573 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
13574
13575 if (put_domains[i])
13576 modeset_put_power_domains(dev_priv, put_domains[i]);
13577
13578 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
13579 }
13580
13581 if (intel_state->modeset)
13582 intel_verify_planes(intel_state);
13583
13584 if (intel_state->modeset && intel_can_enable_sagv(state))
13585 intel_enable_sagv(dev_priv);
13586
13587 drm_atomic_helper_commit_hw_done(state);
13588
13589 if (intel_state->modeset) {
13590 /* As one of the primary mmio accessors, KMS has a high
13591 * likelihood of triggering bugs in unclaimed access. After we
13592 * finish modesetting, see if an error has been flagged, and if
13593 * so enable debugging for the next modeset - and hope we catch
13594 * the culprit.
13595 */
13596 intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
13597 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref);
13598 }
13599
13600 /*
13601 * Defer the cleanup of the old state to a separate worker to not
13602 * impede the current task (userspace for blocking modesets) that
13603 * are executed inline. For out-of-line asynchronous modesets/flips,
13604 * deferring to a new worker seems overkill, but we would place a
13605 * schedule point (cond_resched()) here anyway to keep latencies
13606 * down.
13607 */
13608 INIT_WORK(&state->commit_work, intel_atomic_cleanup_work);
13609 queue_work(system_highpri_wq, &state->commit_work);
13610 }
13611
13612 static void intel_atomic_commit_work(struct work_struct *work)
13613 {
13614 struct drm_atomic_state *state =
13615 container_of(work, struct drm_atomic_state, commit_work);
13616
13617 intel_atomic_commit_tail(state);
13618 }
13619
13620 static int __i915_sw_fence_call
13621 intel_atomic_commit_ready(struct i915_sw_fence *fence,
13622 enum i915_sw_fence_notify notify)
13623 {
13624 struct intel_atomic_state *state =
13625 container_of(fence, struct intel_atomic_state, commit_ready);
13626
13627 switch (notify) {
13628 case FENCE_COMPLETE:
13629 /* we do blocking waits in the worker, nothing to do here */
13630 break;
13631 case FENCE_FREE:
13632 {
13633 struct intel_atomic_helper *helper =
13634 &to_i915(state->base.dev)->atomic_helper;
13635
13636 if (llist_add(&state->freed, &helper->free_list))
13637 schedule_work(&helper->free_work);
13638 break;
13639 }
13640 }
13641
13642 return NOTIFY_DONE;
13643 }
13644
13645 static void intel_atomic_track_fbs(struct drm_atomic_state *state)
13646 {
13647 struct drm_plane_state *old_plane_state, *new_plane_state;
13648 struct drm_plane *plane;
13649 int i;
13650
13651 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i)
13652 i915_gem_track_fb(intel_fb_obj(old_plane_state->fb),
13653 intel_fb_obj(new_plane_state->fb),
13654 to_intel_plane(plane)->frontbuffer_bit);
13655 }
13656
13657 /**
13658 * intel_atomic_commit - commit validated state object
13659 * @dev: DRM device
13660 * @state: the top-level driver state object
13661 * @nonblock: nonblocking commit
13662 *
13663 * This function commits a top-level state object that has been validated
13664 * with drm_atomic_helper_check().
13665 *
13666 * RETURNS
13667 * Zero for success or -errno.
13668 */
13669 static int intel_atomic_commit(struct drm_device *dev,
13670 struct drm_atomic_state *state,
13671 bool nonblock)
13672 {
13673 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13674 struct drm_i915_private *dev_priv = to_i915(dev);
13675 int ret = 0;
13676
13677 drm_atomic_state_get(state);
13678 i915_sw_fence_init(&intel_state->commit_ready,
13679 intel_atomic_commit_ready);
13680
13681 /*
13682 * The intel_legacy_cursor_update() fast path takes care
13683 * of avoiding the vblank waits for simple cursor
13684 * movement and flips. For cursor on/off and size changes,
13685 * we want to perform the vblank waits so that watermark
13686 * updates happen during the correct frames. Gen9+ have
13687 * double buffered watermarks and so shouldn't need this.
13688 *
13689 * Unset state->legacy_cursor_update before the call to
13690 * drm_atomic_helper_setup_commit() because otherwise
13691 * drm_atomic_helper_wait_for_flip_done() is a noop and
13692 * we get FIFO underruns because we didn't wait
13693 * for vblank.
13694 *
13695 * FIXME doing watermarks and fb cleanup from a vblank worker
13696 * (assuming we had any) would solve these problems.
13697 */
13698 if (INTEL_GEN(dev_priv) < 9 && state->legacy_cursor_update) {
13699 struct intel_crtc_state *new_crtc_state;
13700 struct intel_crtc *crtc;
13701 int i;
13702
13703 for_each_new_intel_crtc_in_state(intel_state, crtc, new_crtc_state, i)
13704 if (new_crtc_state->wm.need_postvbl_update ||
13705 new_crtc_state->update_wm_post)
13706 state->legacy_cursor_update = false;
13707 }
13708
13709 ret = intel_atomic_prepare_commit(dev, state);
13710 if (ret) {
13711 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13712 i915_sw_fence_commit(&intel_state->commit_ready);
13713 return ret;
13714 }
13715
13716 ret = drm_atomic_helper_setup_commit(state, nonblock);
13717 if (!ret)
13718 ret = drm_atomic_helper_swap_state(state, true);
13719
13720 if (ret) {
13721 i915_sw_fence_commit(&intel_state->commit_ready);
13722
13723 drm_atomic_helper_cleanup_planes(dev, state);
13724 return ret;
13725 }
13726 dev_priv->wm.distrust_bios_wm = false;
13727 intel_shared_dpll_swap_state(state);
13728 intel_atomic_track_fbs(state);
13729
13730 if (intel_state->modeset) {
13731 memcpy(dev_priv->min_cdclk, intel_state->min_cdclk,
13732 sizeof(intel_state->min_cdclk));
13733 memcpy(dev_priv->min_voltage_level,
13734 intel_state->min_voltage_level,
13735 sizeof(intel_state->min_voltage_level));
13736 dev_priv->active_crtcs = intel_state->active_crtcs;
13737 dev_priv->cdclk.force_min_cdclk =
13738 intel_state->cdclk.force_min_cdclk;
13739
13740 intel_cdclk_swap_state(intel_state);
13741 }
13742
13743 drm_atomic_state_get(state);
13744 INIT_WORK(&state->commit_work, intel_atomic_commit_work);
13745
13746 i915_sw_fence_commit(&intel_state->commit_ready);
13747 if (nonblock && intel_state->modeset) {
13748 queue_work(dev_priv->modeset_wq, &state->commit_work);
13749 } else if (nonblock) {
13750 queue_work(system_unbound_wq, &state->commit_work);
13751 } else {
13752 if (intel_state->modeset)
13753 flush_workqueue(dev_priv->modeset_wq);
13754 intel_atomic_commit_tail(state);
13755 }
13756
13757 return 0;
13758 }
13759
13760 static const struct drm_crtc_funcs intel_crtc_funcs = {
13761 .gamma_set = drm_atomic_helper_legacy_gamma_set,
13762 .set_config = drm_atomic_helper_set_config,
13763 .destroy = intel_crtc_destroy,
13764 .page_flip = drm_atomic_helper_page_flip,
13765 .atomic_duplicate_state = intel_crtc_duplicate_state,
13766 .atomic_destroy_state = intel_crtc_destroy_state,
13767 .set_crc_source = intel_crtc_set_crc_source,
13768 .verify_crc_source = intel_crtc_verify_crc_source,
13769 .get_crc_sources = intel_crtc_get_crc_sources,
13770 };
13771
13772 struct wait_rps_boost {
13773 struct wait_queue_entry wait;
13774
13775 struct drm_crtc *crtc;
13776 struct i915_request *request;
13777 };
13778
13779 static int do_rps_boost(struct wait_queue_entry *_wait,
13780 unsigned mode, int sync, void *key)
13781 {
13782 struct wait_rps_boost *wait = container_of(_wait, typeof(*wait), wait);
13783 struct i915_request *rq = wait->request;
13784
13785 /*
13786 * If we missed the vblank, but the request is already running it
13787 * is reasonable to assume that it will complete before the next
13788 * vblank without our intervention, so leave RPS alone.
13789 */
13790 if (!i915_request_started(rq))
13791 gen6_rps_boost(rq);
13792 i915_request_put(rq);
13793
13794 drm_crtc_vblank_put(wait->crtc);
13795
13796 list_del(&wait->wait.entry);
13797 kfree(wait);
13798 return 1;
13799 }
13800
13801 static void add_rps_boost_after_vblank(struct drm_crtc *crtc,
13802 struct dma_fence *fence)
13803 {
13804 struct wait_rps_boost *wait;
13805
13806 if (!dma_fence_is_i915(fence))
13807 return;
13808
13809 if (INTEL_GEN(to_i915(crtc->dev)) < 6)
13810 return;
13811
13812 if (drm_crtc_vblank_get(crtc))
13813 return;
13814
13815 wait = kmalloc(sizeof(*wait), GFP_KERNEL);
13816 if (!wait) {
13817 drm_crtc_vblank_put(crtc);
13818 return;
13819 }
13820
13821 wait->request = to_request(dma_fence_get(fence));
13822 wait->crtc = crtc;
13823
13824 wait->wait.func = do_rps_boost;
13825 wait->wait.flags = 0;
13826
13827 add_wait_queue(drm_crtc_vblank_waitqueue(crtc), &wait->wait);
13828 }
13829
13830 static int intel_plane_pin_fb(struct intel_plane_state *plane_state)
13831 {
13832 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
13833 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
13834 struct drm_framebuffer *fb = plane_state->base.fb;
13835 struct i915_vma *vma;
13836
13837 if (plane->id == PLANE_CURSOR &&
13838 INTEL_INFO(dev_priv)->display.cursor_needs_physical) {
13839 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13840 const int align = intel_cursor_alignment(dev_priv);
13841 int err;
13842
13843 err = i915_gem_object_attach_phys(obj, align);
13844 if (err)
13845 return err;
13846 }
13847
13848 vma = intel_pin_and_fence_fb_obj(fb,
13849 &plane_state->view,
13850 intel_plane_uses_fence(plane_state),
13851 &plane_state->flags);
13852 if (IS_ERR(vma))
13853 return PTR_ERR(vma);
13854
13855 plane_state->vma = vma;
13856
13857 return 0;
13858 }
13859
13860 static void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state)
13861 {
13862 struct i915_vma *vma;
13863
13864 vma = fetch_and_zero(&old_plane_state->vma);
13865 if (vma)
13866 intel_unpin_fb_vma(vma, old_plane_state->flags);
13867 }
13868
13869 static void fb_obj_bump_render_priority(struct drm_i915_gem_object *obj)
13870 {
13871 struct i915_sched_attr attr = {
13872 .priority = I915_PRIORITY_DISPLAY,
13873 };
13874
13875 i915_gem_object_wait_priority(obj, 0, &attr);
13876 }
13877
13878 /**
13879 * intel_prepare_plane_fb - Prepare fb for usage on plane
13880 * @plane: drm plane to prepare for
13881 * @new_state: the plane state being prepared
13882 *
13883 * Prepares a framebuffer for usage on a display plane. Generally this
13884 * involves pinning the underlying object and updating the frontbuffer tracking
13885 * bits. Some older platforms need special physical address handling for
13886 * cursor planes.
13887 *
13888 * Must be called with struct_mutex held.
13889 *
13890 * Returns 0 on success, negative error code on failure.
13891 */
13892 int
13893 intel_prepare_plane_fb(struct drm_plane *plane,
13894 struct drm_plane_state *new_state)
13895 {
13896 struct intel_atomic_state *intel_state =
13897 to_intel_atomic_state(new_state->state);
13898 struct drm_i915_private *dev_priv = to_i915(plane->dev);
13899 struct drm_framebuffer *fb = new_state->fb;
13900 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13901 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13902 int ret;
13903
13904 if (old_obj) {
13905 struct drm_crtc_state *crtc_state =
13906 drm_atomic_get_new_crtc_state(new_state->state,
13907 plane->state->crtc);
13908
13909 /* Big Hammer, we also need to ensure that any pending
13910 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13911 * current scanout is retired before unpinning the old
13912 * framebuffer. Note that we rely on userspace rendering
13913 * into the buffer attached to the pipe they are waiting
13914 * on. If not, userspace generates a GPU hang with IPEHR
13915 * point to the MI_WAIT_FOR_EVENT.
13916 *
13917 * This should only fail upon a hung GPU, in which case we
13918 * can safely continue.
13919 */
13920 if (needs_modeset(crtc_state)) {
13921 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
13922 old_obj->resv, NULL,
13923 false, 0,
13924 GFP_KERNEL);
13925 if (ret < 0)
13926 return ret;
13927 }
13928 }
13929
13930 if (new_state->fence) { /* explicit fencing */
13931 ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready,
13932 new_state->fence,
13933 I915_FENCE_TIMEOUT,
13934 GFP_KERNEL);
13935 if (ret < 0)
13936 return ret;
13937 }
13938
13939 if (!obj)
13940 return 0;
13941
13942 ret = i915_gem_object_pin_pages(obj);
13943 if (ret)
13944 return ret;
13945
13946 ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
13947 if (ret) {
13948 i915_gem_object_unpin_pages(obj);
13949 return ret;
13950 }
13951
13952 ret = intel_plane_pin_fb(to_intel_plane_state(new_state));
13953
13954 mutex_unlock(&dev_priv->drm.struct_mutex);
13955 i915_gem_object_unpin_pages(obj);
13956 if (ret)
13957 return ret;
13958
13959 fb_obj_bump_render_priority(obj);
13960 intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
13961
13962 if (!new_state->fence) { /* implicit fencing */
13963 struct dma_fence *fence;
13964
13965 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
13966 obj->resv, NULL,
13967 false, I915_FENCE_TIMEOUT,
13968 GFP_KERNEL);
13969 if (ret < 0)
13970 return ret;
13971
13972 fence = reservation_object_get_excl_rcu(obj->resv);
13973 if (fence) {
13974 add_rps_boost_after_vblank(new_state->crtc, fence);
13975 dma_fence_put(fence);
13976 }
13977 } else {
13978 add_rps_boost_after_vblank(new_state->crtc, new_state->fence);
13979 }
13980
13981 /*
13982 * We declare pageflips to be interactive and so merit a small bias
13983 * towards upclocking to deliver the frame on time. By only changing
13984 * the RPS thresholds to sample more regularly and aim for higher
13985 * clocks we can hopefully deliver low power workloads (like kodi)
13986 * that are not quite steady state without resorting to forcing
13987 * maximum clocks following a vblank miss (see do_rps_boost()).
13988 */
13989 if (!intel_state->rps_interactive) {
13990 intel_rps_mark_interactive(dev_priv, true);
13991 intel_state->rps_interactive = true;
13992 }
13993
13994 return 0;
13995 }
13996
13997 /**
13998 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13999 * @plane: drm plane to clean up for
14000 * @old_state: the state from the previous modeset
14001 *
14002 * Cleans up a framebuffer that has just been removed from a plane.
14003 *
14004 * Must be called with struct_mutex held.
14005 */
14006 void
14007 intel_cleanup_plane_fb(struct drm_plane *plane,
14008 struct drm_plane_state *old_state)
14009 {
14010 struct intel_atomic_state *intel_state =
14011 to_intel_atomic_state(old_state->state);
14012 struct drm_i915_private *dev_priv = to_i915(plane->dev);
14013
14014 if (intel_state->rps_interactive) {
14015 intel_rps_mark_interactive(dev_priv, false);
14016 intel_state->rps_interactive = false;
14017 }
14018
14019 /* Should only be called after a successful intel_prepare_plane_fb()! */
14020 mutex_lock(&dev_priv->drm.struct_mutex);
14021 intel_plane_unpin_fb(to_intel_plane_state(old_state));
14022 mutex_unlock(&dev_priv->drm.struct_mutex);
14023 }
14024
14025 int
14026 skl_max_scale(const struct intel_crtc_state *crtc_state,
14027 u32 pixel_format)
14028 {
14029 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
14030 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14031 int max_scale, mult;
14032 int crtc_clock, max_dotclk, tmpclk1, tmpclk2;
14033
14034 if (!crtc_state->base.enable)
14035 return DRM_PLANE_HELPER_NO_SCALING;
14036
14037 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
14038 max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk;
14039
14040 if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10)
14041 max_dotclk *= 2;
14042
14043 if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock))
14044 return DRM_PLANE_HELPER_NO_SCALING;
14045
14046 /*
14047 * skl max scale is lower of:
14048 * close to 3 but not 3, -1 is for that purpose
14049 * or
14050 * cdclk/crtc_clock
14051 */
14052 mult = is_planar_yuv_format(pixel_format) ? 2 : 3;
14053 tmpclk1 = (1 << 16) * mult - 1;
14054 tmpclk2 = (1 << 8) * ((max_dotclk << 8) / crtc_clock);
14055 max_scale = min(tmpclk1, tmpclk2);
14056
14057 return max_scale;
14058 }
14059
14060 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
14061 struct drm_crtc_state *old_crtc_state)
14062 {
14063 struct drm_device *dev = crtc->dev;
14064 struct drm_i915_private *dev_priv = to_i915(dev);
14065 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14066 struct intel_crtc_state *old_intel_cstate =
14067 to_intel_crtc_state(old_crtc_state);
14068 struct intel_atomic_state *old_intel_state =
14069 to_intel_atomic_state(old_crtc_state->state);
14070 struct intel_crtc_state *intel_cstate =
14071 intel_atomic_get_new_crtc_state(old_intel_state, intel_crtc);
14072 bool modeset = needs_modeset(&intel_cstate->base);
14073
14074 /* Perform vblank evasion around commit operation */
14075 intel_pipe_update_start(intel_cstate);
14076
14077 if (modeset)
14078 goto out;
14079
14080 if (intel_cstate->base.color_mgmt_changed ||
14081 intel_cstate->update_pipe)
14082 intel_color_commit(intel_cstate);
14083
14084 if (intel_cstate->update_pipe)
14085 intel_update_pipe_config(old_intel_cstate, intel_cstate);
14086 else if (INTEL_GEN(dev_priv) >= 9)
14087 skl_detach_scalers(intel_cstate);
14088
14089 out:
14090 if (dev_priv->display.atomic_update_watermarks)
14091 dev_priv->display.atomic_update_watermarks(old_intel_state,
14092 intel_cstate);
14093 }
14094
14095 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
14096 struct intel_crtc_state *crtc_state)
14097 {
14098 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14099
14100 if (!IS_GEN(dev_priv, 2))
14101 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
14102
14103 if (crtc_state->has_pch_encoder) {
14104 enum pipe pch_transcoder =
14105 intel_crtc_pch_transcoder(crtc);
14106
14107 intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true);
14108 }
14109 }
14110
14111 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
14112 struct drm_crtc_state *old_crtc_state)
14113 {
14114 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14115 struct intel_atomic_state *old_intel_state =
14116 to_intel_atomic_state(old_crtc_state->state);
14117 struct intel_crtc_state *new_crtc_state =
14118 intel_atomic_get_new_crtc_state(old_intel_state, intel_crtc);
14119
14120 intel_pipe_update_end(new_crtc_state);
14121
14122 if (new_crtc_state->update_pipe &&
14123 !needs_modeset(&new_crtc_state->base) &&
14124 old_crtc_state->mode.private_flags & I915_MODE_FLAG_INHERITED)
14125 intel_crtc_arm_fifo_underrun(intel_crtc, new_crtc_state);
14126 }
14127
14128 /**
14129 * intel_plane_destroy - destroy a plane
14130 * @plane: plane to destroy
14131 *
14132 * Common destruction function for all types of planes (primary, cursor,
14133 * sprite).
14134 */
14135 void intel_plane_destroy(struct drm_plane *plane)
14136 {
14137 drm_plane_cleanup(plane);
14138 kfree(to_intel_plane(plane));
14139 }
14140
14141 static bool i8xx_plane_format_mod_supported(struct drm_plane *_plane,
14142 u32 format, u64 modifier)
14143 {
14144 switch (modifier) {
14145 case DRM_FORMAT_MOD_LINEAR:
14146 case I915_FORMAT_MOD_X_TILED:
14147 break;
14148 default:
14149 return false;
14150 }
14151
14152 switch (format) {
14153 case DRM_FORMAT_C8:
14154 case DRM_FORMAT_RGB565:
14155 case DRM_FORMAT_XRGB1555:
14156 case DRM_FORMAT_XRGB8888:
14157 return modifier == DRM_FORMAT_MOD_LINEAR ||
14158 modifier == I915_FORMAT_MOD_X_TILED;
14159 default:
14160 return false;
14161 }
14162 }
14163
14164 static bool i965_plane_format_mod_supported(struct drm_plane *_plane,
14165 u32 format, u64 modifier)
14166 {
14167 switch (modifier) {
14168 case DRM_FORMAT_MOD_LINEAR:
14169 case I915_FORMAT_MOD_X_TILED:
14170 break;
14171 default:
14172 return false;
14173 }
14174
14175 switch (format) {
14176 case DRM_FORMAT_C8:
14177 case DRM_FORMAT_RGB565:
14178 case DRM_FORMAT_XRGB8888:
14179 case DRM_FORMAT_XBGR8888:
14180 case DRM_FORMAT_XRGB2101010:
14181 case DRM_FORMAT_XBGR2101010:
14182 return modifier == DRM_FORMAT_MOD_LINEAR ||
14183 modifier == I915_FORMAT_MOD_X_TILED;
14184 default:
14185 return false;
14186 }
14187 }
14188
14189 static bool intel_cursor_format_mod_supported(struct drm_plane *_plane,
14190 u32 format, u64 modifier)
14191 {
14192 return modifier == DRM_FORMAT_MOD_LINEAR &&
14193 format == DRM_FORMAT_ARGB8888;
14194 }
14195
14196 static const struct drm_plane_funcs i965_plane_funcs = {
14197 .update_plane = drm_atomic_helper_update_plane,
14198 .disable_plane = drm_atomic_helper_disable_plane,
14199 .destroy = intel_plane_destroy,
14200 .atomic_get_property = intel_plane_atomic_get_property,
14201 .atomic_set_property = intel_plane_atomic_set_property,
14202 .atomic_duplicate_state = intel_plane_duplicate_state,
14203 .atomic_destroy_state = intel_plane_destroy_state,
14204 .format_mod_supported = i965_plane_format_mod_supported,
14205 };
14206
14207 static const struct drm_plane_funcs i8xx_plane_funcs = {
14208 .update_plane = drm_atomic_helper_update_plane,
14209 .disable_plane = drm_atomic_helper_disable_plane,
14210 .destroy = intel_plane_destroy,
14211 .atomic_get_property = intel_plane_atomic_get_property,
14212 .atomic_set_property = intel_plane_atomic_set_property,
14213 .atomic_duplicate_state = intel_plane_duplicate_state,
14214 .atomic_destroy_state = intel_plane_destroy_state,
14215 .format_mod_supported = i8xx_plane_format_mod_supported,
14216 };
14217
14218 static int
14219 intel_legacy_cursor_update(struct drm_plane *plane,
14220 struct drm_crtc *crtc,
14221 struct drm_framebuffer *fb,
14222 int crtc_x, int crtc_y,
14223 unsigned int crtc_w, unsigned int crtc_h,
14224 u32 src_x, u32 src_y,
14225 u32 src_w, u32 src_h,
14226 struct drm_modeset_acquire_ctx *ctx)
14227 {
14228 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
14229 int ret;
14230 struct drm_plane_state *old_plane_state, *new_plane_state;
14231 struct intel_plane *intel_plane = to_intel_plane(plane);
14232 struct drm_framebuffer *old_fb;
14233 struct intel_crtc_state *crtc_state =
14234 to_intel_crtc_state(crtc->state);
14235 struct intel_crtc_state *new_crtc_state;
14236
14237 /*
14238 * When crtc is inactive or there is a modeset pending,
14239 * wait for it to complete in the slowpath
14240 */
14241 if (!crtc_state->base.active || needs_modeset(&crtc_state->base) ||
14242 crtc_state->update_pipe)
14243 goto slow;
14244
14245 old_plane_state = plane->state;
14246 /*
14247 * Don't do an async update if there is an outstanding commit modifying
14248 * the plane. This prevents our async update's changes from getting
14249 * overridden by a previous synchronous update's state.
14250 */
14251 if (old_plane_state->commit &&
14252 !try_wait_for_completion(&old_plane_state->commit->hw_done))
14253 goto slow;
14254
14255 /*
14256 * If any parameters change that may affect watermarks,
14257 * take the slowpath. Only changing fb or position should be
14258 * in the fastpath.
14259 */
14260 if (old_plane_state->crtc != crtc ||
14261 old_plane_state->src_w != src_w ||
14262 old_plane_state->src_h != src_h ||
14263 old_plane_state->crtc_w != crtc_w ||
14264 old_plane_state->crtc_h != crtc_h ||
14265 !old_plane_state->fb != !fb)
14266 goto slow;
14267
14268 new_plane_state = intel_plane_duplicate_state(plane);
14269 if (!new_plane_state)
14270 return -ENOMEM;
14271
14272 new_crtc_state = to_intel_crtc_state(intel_crtc_duplicate_state(crtc));
14273 if (!new_crtc_state) {
14274 ret = -ENOMEM;
14275 goto out_free;
14276 }
14277
14278 drm_atomic_set_fb_for_plane(new_plane_state, fb);
14279
14280 new_plane_state->src_x = src_x;
14281 new_plane_state->src_y = src_y;
14282 new_plane_state->src_w = src_w;
14283 new_plane_state->src_h = src_h;
14284 new_plane_state->crtc_x = crtc_x;
14285 new_plane_state->crtc_y = crtc_y;
14286 new_plane_state->crtc_w = crtc_w;
14287 new_plane_state->crtc_h = crtc_h;
14288
14289 ret = intel_plane_atomic_check_with_state(crtc_state, new_crtc_state,
14290 to_intel_plane_state(old_plane_state),
14291 to_intel_plane_state(new_plane_state));
14292 if (ret)
14293 goto out_free;
14294
14295 ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
14296 if (ret)
14297 goto out_free;
14298
14299 ret = intel_plane_pin_fb(to_intel_plane_state(new_plane_state));
14300 if (ret)
14301 goto out_unlock;
14302
14303 intel_fb_obj_flush(intel_fb_obj(fb), ORIGIN_FLIP);
14304
14305 old_fb = old_plane_state->fb;
14306 i915_gem_track_fb(intel_fb_obj(old_fb), intel_fb_obj(fb),
14307 intel_plane->frontbuffer_bit);
14308
14309 /* Swap plane state */
14310 plane->state = new_plane_state;
14311
14312 /*
14313 * We cannot swap crtc_state as it may be in use by an atomic commit or
14314 * page flip that's running simultaneously. If we swap crtc_state and
14315 * destroy the old state, we will cause a use-after-free there.
14316 *
14317 * Only update active_planes, which is needed for our internal
14318 * bookkeeping. Either value will do the right thing when updating
14319 * planes atomically. If the cursor was part of the atomic update then
14320 * we would have taken the slowpath.
14321 */
14322 crtc_state->active_planes = new_crtc_state->active_planes;
14323
14324 if (plane->state->visible)
14325 intel_update_plane(intel_plane, crtc_state,
14326 to_intel_plane_state(plane->state));
14327 else
14328 intel_disable_plane(intel_plane, crtc_state);
14329
14330 intel_plane_unpin_fb(to_intel_plane_state(old_plane_state));
14331
14332 out_unlock:
14333 mutex_unlock(&dev_priv->drm.struct_mutex);
14334 out_free:
14335 if (new_crtc_state)
14336 intel_crtc_destroy_state(crtc, &new_crtc_state->base);
14337 if (ret)
14338 intel_plane_destroy_state(plane, new_plane_state);
14339 else
14340 intel_plane_destroy_state(plane, old_plane_state);
14341 return ret;
14342
14343 slow:
14344 return drm_atomic_helper_update_plane(plane, crtc, fb,
14345 crtc_x, crtc_y, crtc_w, crtc_h,
14346 src_x, src_y, src_w, src_h, ctx);
14347 }
14348
14349 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
14350 .update_plane = intel_legacy_cursor_update,
14351 .disable_plane = drm_atomic_helper_disable_plane,
14352 .destroy = intel_plane_destroy,
14353 .atomic_get_property = intel_plane_atomic_get_property,
14354 .atomic_set_property = intel_plane_atomic_set_property,
14355 .atomic_duplicate_state = intel_plane_duplicate_state,
14356 .atomic_destroy_state = intel_plane_destroy_state,
14357 .format_mod_supported = intel_cursor_format_mod_supported,
14358 };
14359
14360 static bool i9xx_plane_has_fbc(struct drm_i915_private *dev_priv,
14361 enum i9xx_plane_id i9xx_plane)
14362 {
14363 if (!HAS_FBC(dev_priv))
14364 return false;
14365
14366 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
14367 return i9xx_plane == PLANE_A; /* tied to pipe A */
14368 else if (IS_IVYBRIDGE(dev_priv))
14369 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B ||
14370 i9xx_plane == PLANE_C;
14371 else if (INTEL_GEN(dev_priv) >= 4)
14372 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B;
14373 else
14374 return i9xx_plane == PLANE_A;
14375 }
14376
14377 static struct intel_plane *
14378 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
14379 {
14380 struct intel_plane *plane;
14381 const struct drm_plane_funcs *plane_funcs;
14382 unsigned int supported_rotations;
14383 unsigned int possible_crtcs;
14384 const u64 *modifiers;
14385 const u32 *formats;
14386 int num_formats;
14387 int ret;
14388
14389 if (INTEL_GEN(dev_priv) >= 9)
14390 return skl_universal_plane_create(dev_priv, pipe,
14391 PLANE_PRIMARY);
14392
14393 plane = intel_plane_alloc();
14394 if (IS_ERR(plane))
14395 return plane;
14396
14397 plane->pipe = pipe;
14398 /*
14399 * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
14400 * port is hooked to pipe B. Hence we want plane A feeding pipe B.
14401 */
14402 if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
14403 plane->i9xx_plane = (enum i9xx_plane_id) !pipe;
14404 else
14405 plane->i9xx_plane = (enum i9xx_plane_id) pipe;
14406 plane->id = PLANE_PRIMARY;
14407 plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane->id);
14408
14409 plane->has_fbc = i9xx_plane_has_fbc(dev_priv, plane->i9xx_plane);
14410 if (plane->has_fbc) {
14411 struct intel_fbc *fbc = &dev_priv->fbc;
14412
14413 fbc->possible_framebuffer_bits |= plane->frontbuffer_bit;
14414 }
14415
14416 if (INTEL_GEN(dev_priv) >= 4) {
14417 formats = i965_primary_formats;
14418 num_formats = ARRAY_SIZE(i965_primary_formats);
14419 modifiers = i9xx_format_modifiers;
14420
14421 plane->max_stride = i9xx_plane_max_stride;
14422 plane->update_plane = i9xx_update_plane;
14423 plane->disable_plane = i9xx_disable_plane;
14424 plane->get_hw_state = i9xx_plane_get_hw_state;
14425 plane->check_plane = i9xx_plane_check;
14426
14427 plane_funcs = &i965_plane_funcs;
14428 } else {
14429 formats = i8xx_primary_formats;
14430 num_formats = ARRAY_SIZE(i8xx_primary_formats);
14431 modifiers = i9xx_format_modifiers;
14432
14433 plane->max_stride = i9xx_plane_max_stride;
14434 plane->update_plane = i9xx_update_plane;
14435 plane->disable_plane = i9xx_disable_plane;
14436 plane->get_hw_state = i9xx_plane_get_hw_state;
14437 plane->check_plane = i9xx_plane_check;
14438
14439 plane_funcs = &i8xx_plane_funcs;
14440 }
14441
14442 possible_crtcs = BIT(pipe);
14443
14444 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
14445 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
14446 possible_crtcs, plane_funcs,
14447 formats, num_formats, modifiers,
14448 DRM_PLANE_TYPE_PRIMARY,
14449 "primary %c", pipe_name(pipe));
14450 else
14451 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
14452 possible_crtcs, plane_funcs,
14453 formats, num_formats, modifiers,
14454 DRM_PLANE_TYPE_PRIMARY,
14455 "plane %c",
14456 plane_name(plane->i9xx_plane));
14457 if (ret)
14458 goto fail;
14459
14460 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
14461 supported_rotations =
14462 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
14463 DRM_MODE_REFLECT_X;
14464 } else if (INTEL_GEN(dev_priv) >= 4) {
14465 supported_rotations =
14466 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
14467 } else {
14468 supported_rotations = DRM_MODE_ROTATE_0;
14469 }
14470
14471 if (INTEL_GEN(dev_priv) >= 4)
14472 drm_plane_create_rotation_property(&plane->base,
14473 DRM_MODE_ROTATE_0,
14474 supported_rotations);
14475
14476 drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs);
14477
14478 return plane;
14479
14480 fail:
14481 intel_plane_free(plane);
14482
14483 return ERR_PTR(ret);
14484 }
14485
14486 static struct intel_plane *
14487 intel_cursor_plane_create(struct drm_i915_private *dev_priv,
14488 enum pipe pipe)
14489 {
14490 unsigned int possible_crtcs;
14491 struct intel_plane *cursor;
14492 int ret;
14493
14494 cursor = intel_plane_alloc();
14495 if (IS_ERR(cursor))
14496 return cursor;
14497
14498 cursor->pipe = pipe;
14499 cursor->i9xx_plane = (enum i9xx_plane_id) pipe;
14500 cursor->id = PLANE_CURSOR;
14501 cursor->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, cursor->id);
14502
14503 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
14504 cursor->max_stride = i845_cursor_max_stride;
14505 cursor->update_plane = i845_update_cursor;
14506 cursor->disable_plane = i845_disable_cursor;
14507 cursor->get_hw_state = i845_cursor_get_hw_state;
14508 cursor->check_plane = i845_check_cursor;
14509 } else {
14510 cursor->max_stride = i9xx_cursor_max_stride;
14511 cursor->update_plane = i9xx_update_cursor;
14512 cursor->disable_plane = i9xx_disable_cursor;
14513 cursor->get_hw_state = i9xx_cursor_get_hw_state;
14514 cursor->check_plane = i9xx_check_cursor;
14515 }
14516
14517 cursor->cursor.base = ~0;
14518 cursor->cursor.cntl = ~0;
14519
14520 if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
14521 cursor->cursor.size = ~0;
14522
14523 possible_crtcs = BIT(pipe);
14524
14525 ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
14526 possible_crtcs, &intel_cursor_plane_funcs,
14527 intel_cursor_formats,
14528 ARRAY_SIZE(intel_cursor_formats),
14529 cursor_format_modifiers,
14530 DRM_PLANE_TYPE_CURSOR,
14531 "cursor %c", pipe_name(pipe));
14532 if (ret)
14533 goto fail;
14534
14535 if (INTEL_GEN(dev_priv) >= 4)
14536 drm_plane_create_rotation_property(&cursor->base,
14537 DRM_MODE_ROTATE_0,
14538 DRM_MODE_ROTATE_0 |
14539 DRM_MODE_ROTATE_180);
14540
14541 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14542
14543 return cursor;
14544
14545 fail:
14546 intel_plane_free(cursor);
14547
14548 return ERR_PTR(ret);
14549 }
14550
14551 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
14552 struct intel_crtc_state *crtc_state)
14553 {
14554 struct intel_crtc_scaler_state *scaler_state =
14555 &crtc_state->scaler_state;
14556 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14557 int i;
14558
14559 crtc->num_scalers = RUNTIME_INFO(dev_priv)->num_scalers[crtc->pipe];
14560 if (!crtc->num_scalers)
14561 return;
14562
14563 for (i = 0; i < crtc->num_scalers; i++) {
14564 struct intel_scaler *scaler = &scaler_state->scalers[i];
14565
14566 scaler->in_use = 0;
14567 scaler->mode = 0;
14568 }
14569
14570 scaler_state->scaler_id = -1;
14571 }
14572
14573 static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
14574 {
14575 struct intel_crtc *intel_crtc;
14576 struct intel_crtc_state *crtc_state = NULL;
14577 struct intel_plane *primary = NULL;
14578 struct intel_plane *cursor = NULL;
14579 int sprite, ret;
14580
14581 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
14582 if (!intel_crtc)
14583 return -ENOMEM;
14584
14585 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14586 if (!crtc_state) {
14587 ret = -ENOMEM;
14588 goto fail;
14589 }
14590 intel_crtc->config = crtc_state;
14591 intel_crtc->base.state = &crtc_state->base;
14592 crtc_state->base.crtc = &intel_crtc->base;
14593
14594 primary = intel_primary_plane_create(dev_priv, pipe);
14595 if (IS_ERR(primary)) {
14596 ret = PTR_ERR(primary);
14597 goto fail;
14598 }
14599 intel_crtc->plane_ids_mask |= BIT(primary->id);
14600
14601 for_each_sprite(dev_priv, pipe, sprite) {
14602 struct intel_plane *plane;
14603
14604 plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
14605 if (IS_ERR(plane)) {
14606 ret = PTR_ERR(plane);
14607 goto fail;
14608 }
14609 intel_crtc->plane_ids_mask |= BIT(plane->id);
14610 }
14611
14612 cursor = intel_cursor_plane_create(dev_priv, pipe);
14613 if (IS_ERR(cursor)) {
14614 ret = PTR_ERR(cursor);
14615 goto fail;
14616 }
14617 intel_crtc->plane_ids_mask |= BIT(cursor->id);
14618
14619 ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base,
14620 &primary->base, &cursor->base,
14621 &intel_crtc_funcs,
14622 "pipe %c", pipe_name(pipe));
14623 if (ret)
14624 goto fail;
14625
14626 intel_crtc->pipe = pipe;
14627
14628 /* initialize shared scalers */
14629 intel_crtc_init_scalers(intel_crtc, crtc_state);
14630
14631 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->pipe_to_crtc_mapping) ||
14632 dev_priv->pipe_to_crtc_mapping[pipe] != NULL);
14633 dev_priv->pipe_to_crtc_mapping[pipe] = intel_crtc;
14634
14635 if (INTEL_GEN(dev_priv) < 9) {
14636 enum i9xx_plane_id i9xx_plane = primary->i9xx_plane;
14637
14638 BUG_ON(i9xx_plane >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14639 dev_priv->plane_to_crtc_mapping[i9xx_plane] != NULL);
14640 dev_priv->plane_to_crtc_mapping[i9xx_plane] = intel_crtc;
14641 }
14642
14643 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14644
14645 intel_color_init(intel_crtc);
14646
14647 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14648
14649 return 0;
14650
14651 fail:
14652 /*
14653 * drm_mode_config_cleanup() will free up any
14654 * crtcs/planes already initialized.
14655 */
14656 kfree(crtc_state);
14657 kfree(intel_crtc);
14658
14659 return ret;
14660 }
14661
14662 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
14663 struct drm_file *file)
14664 {
14665 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14666 struct drm_crtc *drmmode_crtc;
14667 struct intel_crtc *crtc;
14668
14669 drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id);
14670 if (!drmmode_crtc)
14671 return -ENOENT;
14672
14673 crtc = to_intel_crtc(drmmode_crtc);
14674 pipe_from_crtc_id->pipe = crtc->pipe;
14675
14676 return 0;
14677 }
14678
14679 static int intel_encoder_clones(struct intel_encoder *encoder)
14680 {
14681 struct drm_device *dev = encoder->base.dev;
14682 struct intel_encoder *source_encoder;
14683 int index_mask = 0;
14684 int entry = 0;
14685
14686 for_each_intel_encoder(dev, source_encoder) {
14687 if (encoders_cloneable(encoder, source_encoder))
14688 index_mask |= (1 << entry);
14689
14690 entry++;
14691 }
14692
14693 return index_mask;
14694 }
14695
14696 static bool ilk_has_edp_a(struct drm_i915_private *dev_priv)
14697 {
14698 if (!IS_MOBILE(dev_priv))
14699 return false;
14700
14701 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14702 return false;
14703
14704 if (IS_GEN(dev_priv, 5) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14705 return false;
14706
14707 return true;
14708 }
14709
14710 static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv)
14711 {
14712 if (INTEL_GEN(dev_priv) >= 9)
14713 return false;
14714
14715 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
14716 return false;
14717
14718 if (HAS_PCH_LPT_H(dev_priv) &&
14719 I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
14720 return false;
14721
14722 /* DDI E can't be used if DDI A requires 4 lanes */
14723 if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
14724 return false;
14725
14726 if (!dev_priv->vbt.int_crt_support)
14727 return false;
14728
14729 return true;
14730 }
14731
14732 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
14733 {
14734 int pps_num;
14735 int pps_idx;
14736
14737 if (HAS_DDI(dev_priv))
14738 return;
14739 /*
14740 * This w/a is needed at least on CPT/PPT, but to be sure apply it
14741 * everywhere where registers can be write protected.
14742 */
14743 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14744 pps_num = 2;
14745 else
14746 pps_num = 1;
14747
14748 for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
14749 u32 val = I915_READ(PP_CONTROL(pps_idx));
14750
14751 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
14752 I915_WRITE(PP_CONTROL(pps_idx), val);
14753 }
14754 }
14755
14756 static void intel_pps_init(struct drm_i915_private *dev_priv)
14757 {
14758 if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
14759 dev_priv->pps_mmio_base = PCH_PPS_BASE;
14760 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14761 dev_priv->pps_mmio_base = VLV_PPS_BASE;
14762 else
14763 dev_priv->pps_mmio_base = PPS_BASE;
14764
14765 intel_pps_unlock_regs_wa(dev_priv);
14766 }
14767
14768 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
14769 {
14770 struct intel_encoder *encoder;
14771 bool dpd_is_edp = false;
14772
14773 intel_pps_init(dev_priv);
14774
14775 if (!HAS_DISPLAY(dev_priv))
14776 return;
14777
14778 if (IS_ELKHARTLAKE(dev_priv)) {
14779 intel_ddi_init(dev_priv, PORT_A);
14780 intel_ddi_init(dev_priv, PORT_B);
14781 intel_ddi_init(dev_priv, PORT_C);
14782 icl_dsi_init(dev_priv);
14783 } else if (INTEL_GEN(dev_priv) >= 11) {
14784 intel_ddi_init(dev_priv, PORT_A);
14785 intel_ddi_init(dev_priv, PORT_B);
14786 intel_ddi_init(dev_priv, PORT_C);
14787 intel_ddi_init(dev_priv, PORT_D);
14788 intel_ddi_init(dev_priv, PORT_E);
14789 /*
14790 * On some ICL SKUs port F is not present. No strap bits for
14791 * this, so rely on VBT.
14792 * Work around broken VBTs on SKUs known to have no port F.
14793 */
14794 if (IS_ICL_WITH_PORT_F(dev_priv) &&
14795 intel_bios_is_port_present(dev_priv, PORT_F))
14796 intel_ddi_init(dev_priv, PORT_F);
14797
14798 icl_dsi_init(dev_priv);
14799 } else if (IS_GEN9_LP(dev_priv)) {
14800 /*
14801 * FIXME: Broxton doesn't support port detection via the
14802 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14803 * detect the ports.
14804 */
14805 intel_ddi_init(dev_priv, PORT_A);
14806 intel_ddi_init(dev_priv, PORT_B);
14807 intel_ddi_init(dev_priv, PORT_C);
14808
14809 vlv_dsi_init(dev_priv);
14810 } else if (HAS_DDI(dev_priv)) {
14811 int found;
14812
14813 if (intel_ddi_crt_present(dev_priv))
14814 intel_crt_init(dev_priv);
14815
14816 /*
14817 * Haswell uses DDI functions to detect digital outputs.
14818 * On SKL pre-D0 the strap isn't connected, so we assume
14819 * it's there.
14820 */
14821 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14822 /* WaIgnoreDDIAStrap: skl */
14823 if (found || IS_GEN9_BC(dev_priv))
14824 intel_ddi_init(dev_priv, PORT_A);
14825
14826 /* DDI B, C, D, and F detection is indicated by the SFUSE_STRAP
14827 * register */
14828 found = I915_READ(SFUSE_STRAP);
14829
14830 if (found & SFUSE_STRAP_DDIB_DETECTED)
14831 intel_ddi_init(dev_priv, PORT_B);
14832 if (found & SFUSE_STRAP_DDIC_DETECTED)
14833 intel_ddi_init(dev_priv, PORT_C);
14834 if (found & SFUSE_STRAP_DDID_DETECTED)
14835 intel_ddi_init(dev_priv, PORT_D);
14836 if (found & SFUSE_STRAP_DDIF_DETECTED)
14837 intel_ddi_init(dev_priv, PORT_F);
14838 /*
14839 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14840 */
14841 if (IS_GEN9_BC(dev_priv) &&
14842 intel_bios_is_port_present(dev_priv, PORT_E))
14843 intel_ddi_init(dev_priv, PORT_E);
14844
14845 } else if (HAS_PCH_SPLIT(dev_priv)) {
14846 int found;
14847
14848 /*
14849 * intel_edp_init_connector() depends on this completing first,
14850 * to prevent the registration of both eDP and LVDS and the
14851 * incorrect sharing of the PPS.
14852 */
14853 intel_lvds_init(dev_priv);
14854 intel_crt_init(dev_priv);
14855
14856 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
14857
14858 if (ilk_has_edp_a(dev_priv))
14859 intel_dp_init(dev_priv, DP_A, PORT_A);
14860
14861 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14862 /* PCH SDVOB multiplex with HDMIB */
14863 found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
14864 if (!found)
14865 intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
14866 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14867 intel_dp_init(dev_priv, PCH_DP_B, PORT_B);
14868 }
14869
14870 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14871 intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
14872
14873 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14874 intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
14875
14876 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14877 intel_dp_init(dev_priv, PCH_DP_C, PORT_C);
14878
14879 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14880 intel_dp_init(dev_priv, PCH_DP_D, PORT_D);
14881 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
14882 bool has_edp, has_port;
14883
14884 if (IS_VALLEYVIEW(dev_priv) && dev_priv->vbt.int_crt_support)
14885 intel_crt_init(dev_priv);
14886
14887 /*
14888 * The DP_DETECTED bit is the latched state of the DDC
14889 * SDA pin at boot. However since eDP doesn't require DDC
14890 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14891 * eDP ports may have been muxed to an alternate function.
14892 * Thus we can't rely on the DP_DETECTED bit alone to detect
14893 * eDP ports. Consult the VBT as well as DP_DETECTED to
14894 * detect eDP ports.
14895 *
14896 * Sadly the straps seem to be missing sometimes even for HDMI
14897 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
14898 * and VBT for the presence of the port. Additionally we can't
14899 * trust the port type the VBT declares as we've seen at least
14900 * HDMI ports that the VBT claim are DP or eDP.
14901 */
14902 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B);
14903 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
14904 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
14905 has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
14906 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
14907 intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
14908
14909 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C);
14910 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
14911 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
14912 has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
14913 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
14914 intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
14915
14916 if (IS_CHERRYVIEW(dev_priv)) {
14917 /*
14918 * eDP not supported on port D,
14919 * so no need to worry about it
14920 */
14921 has_port = intel_bios_is_port_present(dev_priv, PORT_D);
14922 if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
14923 intel_dp_init(dev_priv, CHV_DP_D, PORT_D);
14924 if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
14925 intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
14926 }
14927
14928 vlv_dsi_init(dev_priv);
14929 } else if (IS_PINEVIEW(dev_priv)) {
14930 intel_lvds_init(dev_priv);
14931 intel_crt_init(dev_priv);
14932 } else if (IS_GEN_RANGE(dev_priv, 3, 4)) {
14933 bool found = false;
14934
14935 if (IS_MOBILE(dev_priv))
14936 intel_lvds_init(dev_priv);
14937
14938 intel_crt_init(dev_priv);
14939
14940 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14941 DRM_DEBUG_KMS("probing SDVOB\n");
14942 found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
14943 if (!found && IS_G4X(dev_priv)) {
14944 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14945 intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
14946 }
14947
14948 if (!found && IS_G4X(dev_priv))
14949 intel_dp_init(dev_priv, DP_B, PORT_B);
14950 }
14951
14952 /* Before G4X SDVOC doesn't have its own detect register */
14953
14954 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14955 DRM_DEBUG_KMS("probing SDVOC\n");
14956 found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
14957 }
14958
14959 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14960
14961 if (IS_G4X(dev_priv)) {
14962 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14963 intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
14964 }
14965 if (IS_G4X(dev_priv))
14966 intel_dp_init(dev_priv, DP_C, PORT_C);
14967 }
14968
14969 if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
14970 intel_dp_init(dev_priv, DP_D, PORT_D);
14971
14972 if (SUPPORTS_TV(dev_priv))
14973 intel_tv_init(dev_priv);
14974 } else if (IS_GEN(dev_priv, 2)) {
14975 if (IS_I85X(dev_priv))
14976 intel_lvds_init(dev_priv);
14977
14978 intel_crt_init(dev_priv);
14979 intel_dvo_init(dev_priv);
14980 }
14981
14982 intel_psr_init(dev_priv);
14983
14984 for_each_intel_encoder(&dev_priv->drm, encoder) {
14985 encoder->base.possible_crtcs = encoder->crtc_mask;
14986 encoder->base.possible_clones =
14987 intel_encoder_clones(encoder);
14988 }
14989
14990 intel_init_pch_refclk(dev_priv);
14991
14992 drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
14993 }
14994
14995 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14996 {
14997 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14998 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14999
15000 drm_framebuffer_cleanup(fb);
15001
15002 i915_gem_object_lock(obj);
15003 WARN_ON(!obj->framebuffer_references--);
15004 i915_gem_object_unlock(obj);
15005
15006 i915_gem_object_put(obj);
15007
15008 kfree(intel_fb);
15009 }
15010
15011 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
15012 struct drm_file *file,
15013 unsigned int *handle)
15014 {
15015 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
15016
15017 if (obj->userptr.mm) {
15018 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
15019 return -EINVAL;
15020 }
15021
15022 return drm_gem_handle_create(file, &obj->base, handle);
15023 }
15024
15025 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
15026 struct drm_file *file,
15027 unsigned flags, unsigned color,
15028 struct drm_clip_rect *clips,
15029 unsigned num_clips)
15030 {
15031 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
15032
15033 i915_gem_object_flush_if_display(obj);
15034 intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
15035
15036 return 0;
15037 }
15038
15039 static const struct drm_framebuffer_funcs intel_fb_funcs = {
15040 .destroy = intel_user_framebuffer_destroy,
15041 .create_handle = intel_user_framebuffer_create_handle,
15042 .dirty = intel_user_framebuffer_dirty,
15043 };
15044
15045 static
15046 u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv,
15047 u32 pixel_format, u64 fb_modifier)
15048 {
15049 struct intel_crtc *crtc;
15050 struct intel_plane *plane;
15051
15052 /*
15053 * We assume the primary plane for pipe A has
15054 * the highest stride limits of them all.
15055 */
15056 crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A);
15057 plane = to_intel_plane(crtc->base.primary);
15058
15059 return plane->max_stride(plane, pixel_format, fb_modifier,
15060 DRM_MODE_ROTATE_0);
15061 }
15062
15063 static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
15064 struct drm_i915_gem_object *obj,
15065 struct drm_mode_fb_cmd2 *mode_cmd)
15066 {
15067 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
15068 struct drm_framebuffer *fb = &intel_fb->base;
15069 u32 pitch_limit;
15070 unsigned int tiling, stride;
15071 int ret = -EINVAL;
15072 int i;
15073
15074 i915_gem_object_lock(obj);
15075 obj->framebuffer_references++;
15076 tiling = i915_gem_object_get_tiling(obj);
15077 stride = i915_gem_object_get_stride(obj);
15078 i915_gem_object_unlock(obj);
15079
15080 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
15081 /*
15082 * If there's a fence, enforce that
15083 * the fb modifier and tiling mode match.
15084 */
15085 if (tiling != I915_TILING_NONE &&
15086 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
15087 DRM_DEBUG_KMS("tiling_mode doesn't match fb modifier\n");
15088 goto err;
15089 }
15090 } else {
15091 if (tiling == I915_TILING_X) {
15092 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
15093 } else if (tiling == I915_TILING_Y) {
15094 DRM_DEBUG_KMS("No Y tiling for legacy addfb\n");
15095 goto err;
15096 }
15097 }
15098
15099 if (!drm_any_plane_has_format(&dev_priv->drm,
15100 mode_cmd->pixel_format,
15101 mode_cmd->modifier[0])) {
15102 struct drm_format_name_buf format_name;
15103
15104 DRM_DEBUG_KMS("unsupported pixel format %s / modifier 0x%llx\n",
15105 drm_get_format_name(mode_cmd->pixel_format,
15106 &format_name),
15107 mode_cmd->modifier[0]);
15108 goto err;
15109 }
15110
15111 /*
15112 * gen2/3 display engine uses the fence if present,
15113 * so the tiling mode must match the fb modifier exactly.
15114 */
15115 if (INTEL_GEN(dev_priv) < 4 &&
15116 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
15117 DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n");
15118 goto err;
15119 }
15120
15121 pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->pixel_format,
15122 mode_cmd->modifier[0]);
15123 if (mode_cmd->pitches[0] > pitch_limit) {
15124 DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n",
15125 mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
15126 "tiled" : "linear",
15127 mode_cmd->pitches[0], pitch_limit);
15128 goto err;
15129 }
15130
15131 /*
15132 * If there's a fence, enforce that
15133 * the fb pitch and fence stride match.
15134 */
15135 if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
15136 DRM_DEBUG_KMS("pitch (%d) must match tiling stride (%d)\n",
15137 mode_cmd->pitches[0], stride);
15138 goto err;
15139 }
15140
15141 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
15142 if (mode_cmd->offsets[0] != 0)
15143 goto err;
15144
15145 drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);
15146
15147 for (i = 0; i < fb->format->num_planes; i++) {
15148 u32 stride_alignment;
15149
15150 if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
15151 DRM_DEBUG_KMS("bad plane %d handle\n", i);
15152 goto err;
15153 }
15154
15155 stride_alignment = intel_fb_stride_alignment(fb, i);
15156
15157 /*
15158 * Display WA #0531: skl,bxt,kbl,glk
15159 *
15160 * Render decompression and plane width > 3840
15161 * combined with horizontal panning requires the
15162 * plane stride to be a multiple of 4. We'll just
15163 * require the entire fb to accommodate that to avoid
15164 * potential runtime errors at plane configuration time.
15165 */
15166 if (IS_GEN(dev_priv, 9) && i == 0 && fb->width > 3840 &&
15167 is_ccs_modifier(fb->modifier))
15168 stride_alignment *= 4;
15169
15170 if (fb->pitches[i] & (stride_alignment - 1)) {
15171 DRM_DEBUG_KMS("plane %d pitch (%d) must be at least %u byte aligned\n",
15172 i, fb->pitches[i], stride_alignment);
15173 goto err;
15174 }
15175
15176 fb->obj[i] = &obj->base;
15177 }
15178
15179 ret = intel_fill_fb_info(dev_priv, fb);
15180 if (ret)
15181 goto err;
15182
15183 ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs);
15184 if (ret) {
15185 DRM_ERROR("framebuffer init failed %d\n", ret);
15186 goto err;
15187 }
15188
15189 return 0;
15190
15191 err:
15192 i915_gem_object_lock(obj);
15193 obj->framebuffer_references--;
15194 i915_gem_object_unlock(obj);
15195 return ret;
15196 }
15197
15198 static struct drm_framebuffer *
15199 intel_user_framebuffer_create(struct drm_device *dev,
15200 struct drm_file *filp,
15201 const struct drm_mode_fb_cmd2 *user_mode_cmd)
15202 {
15203 struct drm_framebuffer *fb;
15204 struct drm_i915_gem_object *obj;
15205 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
15206
15207 obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
15208 if (!obj)
15209 return ERR_PTR(-ENOENT);
15210
15211 fb = intel_framebuffer_create(obj, &mode_cmd);
15212 if (IS_ERR(fb))
15213 i915_gem_object_put(obj);
15214
15215 return fb;
15216 }
15217
15218 static void intel_atomic_state_free(struct drm_atomic_state *state)
15219 {
15220 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
15221
15222 drm_atomic_state_default_release(state);
15223
15224 i915_sw_fence_fini(&intel_state->commit_ready);
15225
15226 kfree(state);
15227 }
15228
15229 static enum drm_mode_status
15230 intel_mode_valid(struct drm_device *dev,
15231 const struct drm_display_mode *mode)
15232 {
15233 struct drm_i915_private *dev_priv = to_i915(dev);
15234 int hdisplay_max, htotal_max;
15235 int vdisplay_max, vtotal_max;
15236
15237 /*
15238 * Can't reject DBLSCAN here because Xorg ddxen can add piles
15239 * of DBLSCAN modes to the output's mode list when they detect
15240 * the scaling mode property on the connector. And they don't
15241 * ask the kernel to validate those modes in any way until
15242 * modeset time at which point the client gets a protocol error.
15243 * So in order to not upset those clients we silently ignore the
15244 * DBLSCAN flag on such connectors. For other connectors we will
15245 * reject modes with the DBLSCAN flag in encoder->compute_config().
15246 * And we always reject DBLSCAN modes in connector->mode_valid()
15247 * as we never want such modes on the connector's mode list.
15248 */
15249
15250 if (mode->vscan > 1)
15251 return MODE_NO_VSCAN;
15252
15253 if (mode->flags & DRM_MODE_FLAG_HSKEW)
15254 return MODE_H_ILLEGAL;
15255
15256 if (mode->flags & (DRM_MODE_FLAG_CSYNC |
15257 DRM_MODE_FLAG_NCSYNC |
15258 DRM_MODE_FLAG_PCSYNC))
15259 return MODE_HSYNC;
15260
15261 if (mode->flags & (DRM_MODE_FLAG_BCAST |
15262 DRM_MODE_FLAG_PIXMUX |
15263 DRM_MODE_FLAG_CLKDIV2))
15264 return MODE_BAD;
15265
15266 if (INTEL_GEN(dev_priv) >= 9 ||
15267 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
15268 hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */
15269 vdisplay_max = 4096;
15270 htotal_max = 8192;
15271 vtotal_max = 8192;
15272 } else if (INTEL_GEN(dev_priv) >= 3) {
15273 hdisplay_max = 4096;
15274 vdisplay_max = 4096;
15275 htotal_max = 8192;
15276 vtotal_max = 8192;
15277 } else {
15278 hdisplay_max = 2048;
15279 vdisplay_max = 2048;
15280 htotal_max = 4096;
15281 vtotal_max = 4096;
15282 }
15283
15284 if (mode->hdisplay > hdisplay_max ||
15285 mode->hsync_start > htotal_max ||
15286 mode->hsync_end > htotal_max ||
15287 mode->htotal > htotal_max)
15288 return MODE_H_ILLEGAL;
15289
15290 if (mode->vdisplay > vdisplay_max ||
15291 mode->vsync_start > vtotal_max ||
15292 mode->vsync_end > vtotal_max ||
15293 mode->vtotal > vtotal_max)
15294 return MODE_V_ILLEGAL;
15295
15296 return MODE_OK;
15297 }
15298
15299 static const struct drm_mode_config_funcs intel_mode_funcs = {
15300 .fb_create = intel_user_framebuffer_create,
15301 .get_format_info = intel_get_format_info,
15302 .output_poll_changed = intel_fbdev_output_poll_changed,
15303 .mode_valid = intel_mode_valid,
15304 .atomic_check = intel_atomic_check,
15305 .atomic_commit = intel_atomic_commit,
15306 .atomic_state_alloc = intel_atomic_state_alloc,
15307 .atomic_state_clear = intel_atomic_state_clear,
15308 .atomic_state_free = intel_atomic_state_free,
15309 };
15310
15311 /**
15312 * intel_init_display_hooks - initialize the display modesetting hooks
15313 * @dev_priv: device private
15314 */
15315 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
15316 {
15317 intel_init_cdclk_hooks(dev_priv);
15318
15319 if (INTEL_GEN(dev_priv) >= 9) {
15320 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
15321 dev_priv->display.get_initial_plane_config =
15322 skylake_get_initial_plane_config;
15323 dev_priv->display.crtc_compute_clock =
15324 haswell_crtc_compute_clock;
15325 dev_priv->display.crtc_enable = haswell_crtc_enable;
15326 dev_priv->display.crtc_disable = haswell_crtc_disable;
15327 } else if (HAS_DDI(dev_priv)) {
15328 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
15329 dev_priv->display.get_initial_plane_config =
15330 i9xx_get_initial_plane_config;
15331 dev_priv->display.crtc_compute_clock =
15332 haswell_crtc_compute_clock;
15333 dev_priv->display.crtc_enable = haswell_crtc_enable;
15334 dev_priv->display.crtc_disable = haswell_crtc_disable;
15335 } else if (HAS_PCH_SPLIT(dev_priv)) {
15336 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
15337 dev_priv->display.get_initial_plane_config =
15338 i9xx_get_initial_plane_config;
15339 dev_priv->display.crtc_compute_clock =
15340 ironlake_crtc_compute_clock;
15341 dev_priv->display.crtc_enable = ironlake_crtc_enable;
15342 dev_priv->display.crtc_disable = ironlake_crtc_disable;
15343 } else if (IS_CHERRYVIEW(dev_priv)) {
15344 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15345 dev_priv->display.get_initial_plane_config =
15346 i9xx_get_initial_plane_config;
15347 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
15348 dev_priv->display.crtc_enable = valleyview_crtc_enable;
15349 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15350 } else if (IS_VALLEYVIEW(dev_priv)) {
15351 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15352 dev_priv->display.get_initial_plane_config =
15353 i9xx_get_initial_plane_config;
15354 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
15355 dev_priv->display.crtc_enable = valleyview_crtc_enable;
15356 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15357 } else if (IS_G4X(dev_priv)) {
15358 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15359 dev_priv->display.get_initial_plane_config =
15360 i9xx_get_initial_plane_config;
15361 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
15362 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15363 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15364 } else if (IS_PINEVIEW(dev_priv)) {
15365 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15366 dev_priv->display.get_initial_plane_config =
15367 i9xx_get_initial_plane_config;
15368 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
15369 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15370 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15371 } else if (!IS_GEN(dev_priv, 2)) {
15372 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15373 dev_priv->display.get_initial_plane_config =
15374 i9xx_get_initial_plane_config;
15375 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
15376 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15377 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15378 } else {
15379 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15380 dev_priv->display.get_initial_plane_config =
15381 i9xx_get_initial_plane_config;
15382 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
15383 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15384 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15385 }
15386
15387 if (IS_GEN(dev_priv, 5)) {
15388 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
15389 } else if (IS_GEN(dev_priv, 6)) {
15390 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
15391 } else if (IS_IVYBRIDGE(dev_priv)) {
15392 /* FIXME: detect B0+ stepping and use auto training */
15393 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
15394 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
15395 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
15396 }
15397
15398 if (INTEL_GEN(dev_priv) >= 9)
15399 dev_priv->display.update_crtcs = skl_update_crtcs;
15400 else
15401 dev_priv->display.update_crtcs = intel_update_crtcs;
15402 }
15403
15404 /* Disable the VGA plane that we never use */
15405 static void i915_disable_vga(struct drm_i915_private *dev_priv)
15406 {
15407 struct pci_dev *pdev = dev_priv->drm.pdev;
15408 u8 sr1;
15409 i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
15410
15411 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15412 vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
15413 outb(SR01, VGA_SR_INDEX);
15414 sr1 = inb(VGA_SR_DATA);
15415 outb(sr1 | 1<<5, VGA_SR_DATA);
15416 vga_put(pdev, VGA_RSRC_LEGACY_IO);
15417 udelay(300);
15418
15419 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
15420 POSTING_READ(vga_reg);
15421 }
15422
15423 void intel_modeset_init_hw(struct drm_device *dev)
15424 {
15425 struct drm_i915_private *dev_priv = to_i915(dev);
15426
15427 intel_update_cdclk(dev_priv);
15428 intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
15429 dev_priv->cdclk.logical = dev_priv->cdclk.actual = dev_priv->cdclk.hw;
15430 }
15431
15432 /*
15433 * Calculate what we think the watermarks should be for the state we've read
15434 * out of the hardware and then immediately program those watermarks so that
15435 * we ensure the hardware settings match our internal state.
15436 *
15437 * We can calculate what we think WM's should be by creating a duplicate of the
15438 * current state (which was constructed during hardware readout) and running it
15439 * through the atomic check code to calculate new watermark values in the
15440 * state object.
15441 */
15442 static void sanitize_watermarks(struct drm_device *dev)
15443 {
15444 struct drm_i915_private *dev_priv = to_i915(dev);
15445 struct drm_atomic_state *state;
15446 struct intel_atomic_state *intel_state;
15447 struct drm_crtc *crtc;
15448 struct drm_crtc_state *cstate;
15449 struct drm_modeset_acquire_ctx ctx;
15450 int ret;
15451 int i;
15452
15453 /* Only supported on platforms that use atomic watermark design */
15454 if (!dev_priv->display.optimize_watermarks)
15455 return;
15456
15457 /*
15458 * We need to hold connection_mutex before calling duplicate_state so
15459 * that the connector loop is protected.
15460 */
15461 drm_modeset_acquire_init(&ctx, 0);
15462 retry:
15463 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15464 if (ret == -EDEADLK) {
15465 drm_modeset_backoff(&ctx);
15466 goto retry;
15467 } else if (WARN_ON(ret)) {
15468 goto fail;
15469 }
15470
15471 state = drm_atomic_helper_duplicate_state(dev, &ctx);
15472 if (WARN_ON(IS_ERR(state)))
15473 goto fail;
15474
15475 intel_state = to_intel_atomic_state(state);
15476
15477 /*
15478 * Hardware readout is the only time we don't want to calculate
15479 * intermediate watermarks (since we don't trust the current
15480 * watermarks).
15481 */
15482 if (!HAS_GMCH(dev_priv))
15483 intel_state->skip_intermediate_wm = true;
15484
15485 ret = intel_atomic_check(dev, state);
15486 if (ret) {
15487 /*
15488 * If we fail here, it means that the hardware appears to be
15489 * programmed in a way that shouldn't be possible, given our
15490 * understanding of watermark requirements. This might mean a
15491 * mistake in the hardware readout code or a mistake in the
15492 * watermark calculations for a given platform. Raise a WARN
15493 * so that this is noticeable.
15494 *
15495 * If this actually happens, we'll have to just leave the
15496 * BIOS-programmed watermarks untouched and hope for the best.
15497 */
15498 WARN(true, "Could not determine valid watermarks for inherited state\n");
15499 goto put_state;
15500 }
15501
15502 /* Write calculated watermark values back */
15503 for_each_new_crtc_in_state(state, crtc, cstate, i) {
15504 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
15505
15506 cs->wm.need_postvbl_update = true;
15507 dev_priv->display.optimize_watermarks(intel_state, cs);
15508
15509 to_intel_crtc_state(crtc->state)->wm = cs->wm;
15510 }
15511
15512 put_state:
15513 drm_atomic_state_put(state);
15514 fail:
15515 drm_modeset_drop_locks(&ctx);
15516 drm_modeset_acquire_fini(&ctx);
15517 }
15518
15519 static void intel_update_fdi_pll_freq(struct drm_i915_private *dev_priv)
15520 {
15521 if (IS_GEN(dev_priv, 5)) {
15522 u32 fdi_pll_clk =
15523 I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK;
15524
15525 dev_priv->fdi_pll_freq = (fdi_pll_clk + 2) * 10000;
15526 } else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv)) {
15527 dev_priv->fdi_pll_freq = 270000;
15528 } else {
15529 return;
15530 }
15531
15532 DRM_DEBUG_DRIVER("FDI PLL freq=%d\n", dev_priv->fdi_pll_freq);
15533 }
15534
15535 static int intel_initial_commit(struct drm_device *dev)
15536 {
15537 struct drm_atomic_state *state = NULL;
15538 struct drm_modeset_acquire_ctx ctx;
15539 struct drm_crtc *crtc;
15540 struct drm_crtc_state *crtc_state;
15541 int ret = 0;
15542
15543 state = drm_atomic_state_alloc(dev);
15544 if (!state)
15545 return -ENOMEM;
15546
15547 drm_modeset_acquire_init(&ctx, 0);
15548
15549 retry:
15550 state->acquire_ctx = &ctx;
15551
15552 drm_for_each_crtc(crtc, dev) {
15553 crtc_state = drm_atomic_get_crtc_state(state, crtc);
15554 if (IS_ERR(crtc_state)) {
15555 ret = PTR_ERR(crtc_state);
15556 goto out;
15557 }
15558
15559 if (crtc_state->active) {
15560 ret = drm_atomic_add_affected_planes(state, crtc);
15561 if (ret)
15562 goto out;
15563
15564 /*
15565 * FIXME hack to force a LUT update to avoid the
15566 * plane update forcing the pipe gamma on without
15567 * having a proper LUT loaded. Remove once we
15568 * have readout for pipe gamma enable.
15569 */
15570 crtc_state->color_mgmt_changed = true;
15571 }
15572 }
15573
15574 ret = drm_atomic_commit(state);
15575
15576 out:
15577 if (ret == -EDEADLK) {
15578 drm_atomic_state_clear(state);
15579 drm_modeset_backoff(&ctx);
15580 goto retry;
15581 }
15582
15583 drm_atomic_state_put(state);
15584
15585 drm_modeset_drop_locks(&ctx);
15586 drm_modeset_acquire_fini(&ctx);
15587
15588 return ret;
15589 }
15590
15591 int intel_modeset_init(struct drm_device *dev)
15592 {
15593 struct drm_i915_private *dev_priv = to_i915(dev);
15594 struct i915_ggtt *ggtt = &dev_priv->ggtt;
15595 enum pipe pipe;
15596 struct intel_crtc *crtc;
15597 int ret;
15598
15599 dev_priv->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0);
15600
15601 drm_mode_config_init(dev);
15602
15603 dev->mode_config.min_width = 0;
15604 dev->mode_config.min_height = 0;
15605
15606 dev->mode_config.preferred_depth = 24;
15607 dev->mode_config.prefer_shadow = 1;
15608
15609 dev->mode_config.allow_fb_modifiers = true;
15610
15611 dev->mode_config.funcs = &intel_mode_funcs;
15612
15613 init_llist_head(&dev_priv->atomic_helper.free_list);
15614 INIT_WORK(&dev_priv->atomic_helper.free_work,
15615 intel_atomic_helper_free_state_worker);
15616
15617 intel_init_quirks(dev_priv);
15618
15619 intel_fbc_init(dev_priv);
15620
15621 intel_init_pm(dev_priv);
15622
15623 /*
15624 * There may be no VBT; and if the BIOS enabled SSC we can
15625 * just keep using it to avoid unnecessary flicker. Whereas if the
15626 * BIOS isn't using it, don't assume it will work even if the VBT
15627 * indicates as much.
15628 */
15629 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
15630 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15631 DREF_SSC1_ENABLE);
15632
15633 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
15634 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15635 bios_lvds_use_ssc ? "en" : "dis",
15636 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
15637 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
15638 }
15639 }
15640
15641 /* maximum framebuffer dimensions */
15642 if (IS_GEN(dev_priv, 2)) {
15643 dev->mode_config.max_width = 2048;
15644 dev->mode_config.max_height = 2048;
15645 } else if (IS_GEN(dev_priv, 3)) {
15646 dev->mode_config.max_width = 4096;
15647 dev->mode_config.max_height = 4096;
15648 } else {
15649 dev->mode_config.max_width = 8192;
15650 dev->mode_config.max_height = 8192;
15651 }
15652
15653 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
15654 dev->mode_config.cursor_width = IS_I845G(dev_priv) ? 64 : 512;
15655 dev->mode_config.cursor_height = 1023;
15656 } else if (IS_GEN(dev_priv, 2)) {
15657 dev->mode_config.cursor_width = 64;
15658 dev->mode_config.cursor_height = 64;
15659 } else {
15660 dev->mode_config.cursor_width = 256;
15661 dev->mode_config.cursor_height = 256;
15662 }
15663
15664 dev->mode_config.fb_base = ggtt->gmadr.start;
15665
15666 DRM_DEBUG_KMS("%d display pipe%s available.\n",
15667 INTEL_INFO(dev_priv)->num_pipes,
15668 INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : "");
15669
15670 for_each_pipe(dev_priv, pipe) {
15671 ret = intel_crtc_init(dev_priv, pipe);
15672 if (ret) {
15673 drm_mode_config_cleanup(dev);
15674 return ret;
15675 }
15676 }
15677
15678 intel_shared_dpll_init(dev);
15679 intel_update_fdi_pll_freq(dev_priv);
15680
15681 intel_update_czclk(dev_priv);
15682 intel_modeset_init_hw(dev);
15683
15684 intel_hdcp_component_init(dev_priv);
15685
15686 if (dev_priv->max_cdclk_freq == 0)
15687 intel_update_max_cdclk(dev_priv);
15688
15689 /* Just disable it once at startup */
15690 i915_disable_vga(dev_priv);
15691 intel_setup_outputs(dev_priv);
15692
15693 drm_modeset_lock_all(dev);
15694 intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx);
15695 drm_modeset_unlock_all(dev);
15696
15697 for_each_intel_crtc(dev, crtc) {
15698 struct intel_initial_plane_config plane_config = {};
15699
15700 if (!crtc->active)
15701 continue;
15702
15703 /*
15704 * Note that reserving the BIOS fb up front prevents us
15705 * from stuffing other stolen allocations like the ring
15706 * on top. This prevents some ugliness at boot time, and
15707 * can even allow for smooth boot transitions if the BIOS
15708 * fb is large enough for the active pipe configuration.
15709 */
15710 dev_priv->display.get_initial_plane_config(crtc,
15711 &plane_config);
15712
15713 /*
15714 * If the fb is shared between multiple heads, we'll
15715 * just get the first one.
15716 */
15717 intel_find_initial_plane_obj(crtc, &plane_config);
15718 }
15719
15720 /*
15721 * Make sure hardware watermarks really match the state we read out.
15722 * Note that we need to do this after reconstructing the BIOS fb's
15723 * since the watermark calculation done here will use pstate->fb.
15724 */
15725 if (!HAS_GMCH(dev_priv))
15726 sanitize_watermarks(dev);
15727
15728 /*
15729 * Force all active planes to recompute their states. So that on
15730 * mode_setcrtc after probe, all the intel_plane_state variables
15731 * are already calculated and there is no assert_plane warnings
15732 * during bootup.
15733 */
15734 ret = intel_initial_commit(dev);
15735 if (ret)
15736 DRM_DEBUG_KMS("Initial commit in probe failed.\n");
15737
15738 return 0;
15739 }
15740
15741 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
15742 {
15743 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15744 /* 640x480@60Hz, ~25175 kHz */
15745 struct dpll clock = {
15746 .m1 = 18,
15747 .m2 = 7,
15748 .p1 = 13,
15749 .p2 = 4,
15750 .n = 2,
15751 };
15752 u32 dpll, fp;
15753 int i;
15754
15755 WARN_ON(i9xx_calc_dpll_params(48000, &clock) != 25154);
15756
15757 DRM_DEBUG_KMS("enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
15758 pipe_name(pipe), clock.vco, clock.dot);
15759
15760 fp = i9xx_dpll_compute_fp(&clock);
15761 dpll = DPLL_DVO_2X_MODE |
15762 DPLL_VGA_MODE_DIS |
15763 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
15764 PLL_P2_DIVIDE_BY_4 |
15765 PLL_REF_INPUT_DREFCLK |
15766 DPLL_VCO_ENABLE;
15767
15768 I915_WRITE(FP0(pipe), fp);
15769 I915_WRITE(FP1(pipe), fp);
15770
15771 I915_WRITE(HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16));
15772 I915_WRITE(HBLANK(pipe), (640 - 1) | ((800 - 1) << 16));
15773 I915_WRITE(HSYNC(pipe), (656 - 1) | ((752 - 1) << 16));
15774 I915_WRITE(VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16));
15775 I915_WRITE(VBLANK(pipe), (480 - 1) | ((525 - 1) << 16));
15776 I915_WRITE(VSYNC(pipe), (490 - 1) | ((492 - 1) << 16));
15777 I915_WRITE(PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1));
15778
15779 /*
15780 * Apparently we need to have VGA mode enabled prior to changing
15781 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
15782 * dividers, even though the register value does change.
15783 */
15784 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
15785 I915_WRITE(DPLL(pipe), dpll);
15786
15787 /* Wait for the clocks to stabilize. */
15788 POSTING_READ(DPLL(pipe));
15789 udelay(150);
15790
15791 /* The pixel multiplier can only be updated once the
15792 * DPLL is enabled and the clocks are stable.
15793 *
15794 * So write it again.
15795 */
15796 I915_WRITE(DPLL(pipe), dpll);
15797
15798 /* We do this three times for luck */
15799 for (i = 0; i < 3 ; i++) {
15800 I915_WRITE(DPLL(pipe), dpll);
15801 POSTING_READ(DPLL(pipe));
15802 udelay(150); /* wait for warmup */
15803 }
15804
15805 I915_WRITE(PIPECONF(pipe), PIPECONF_ENABLE | PIPECONF_PROGRESSIVE);
15806 POSTING_READ(PIPECONF(pipe));
15807
15808 intel_wait_for_pipe_scanline_moving(crtc);
15809 }
15810
15811 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
15812 {
15813 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15814
15815 DRM_DEBUG_KMS("disabling pipe %c due to force quirk\n",
15816 pipe_name(pipe));
15817
15818 WARN_ON(I915_READ(DSPCNTR(PLANE_A)) & DISPLAY_PLANE_ENABLE);
15819 WARN_ON(I915_READ(DSPCNTR(PLANE_B)) & DISPLAY_PLANE_ENABLE);
15820 WARN_ON(I915_READ(DSPCNTR(PLANE_C)) & DISPLAY_PLANE_ENABLE);
15821 WARN_ON(I915_READ(CURCNTR(PIPE_A)) & MCURSOR_MODE);
15822 WARN_ON(I915_READ(CURCNTR(PIPE_B)) & MCURSOR_MODE);
15823
15824 I915_WRITE(PIPECONF(pipe), 0);
15825 POSTING_READ(PIPECONF(pipe));
15826
15827 intel_wait_for_pipe_scanline_stopped(crtc);
15828
15829 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
15830 POSTING_READ(DPLL(pipe));
15831 }
15832
15833 static void
15834 intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv)
15835 {
15836 struct intel_crtc *crtc;
15837
15838 if (INTEL_GEN(dev_priv) >= 4)
15839 return;
15840
15841 for_each_intel_crtc(&dev_priv->drm, crtc) {
15842 struct intel_plane *plane =
15843 to_intel_plane(crtc->base.primary);
15844 struct intel_crtc *plane_crtc;
15845 enum pipe pipe;
15846
15847 if (!plane->get_hw_state(plane, &pipe))
15848 continue;
15849
15850 if (pipe == crtc->pipe)
15851 continue;
15852
15853 DRM_DEBUG_KMS("[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n",
15854 plane->base.base.id, plane->base.name);
15855
15856 plane_crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15857 intel_plane_disable_noatomic(plane_crtc, plane);
15858 }
15859 }
15860
15861 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15862 {
15863 struct drm_device *dev = crtc->base.dev;
15864 struct intel_encoder *encoder;
15865
15866 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15867 return true;
15868
15869 return false;
15870 }
15871
15872 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
15873 {
15874 struct drm_device *dev = encoder->base.dev;
15875 struct intel_connector *connector;
15876
15877 for_each_connector_on_encoder(dev, &encoder->base, connector)
15878 return connector;
15879
15880 return NULL;
15881 }
15882
15883 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
15884 enum pipe pch_transcoder)
15885 {
15886 return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
15887 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == PIPE_A);
15888 }
15889
15890 static void intel_sanitize_crtc(struct intel_crtc *crtc,
15891 struct drm_modeset_acquire_ctx *ctx)
15892 {
15893 struct drm_device *dev = crtc->base.dev;
15894 struct drm_i915_private *dev_priv = to_i915(dev);
15895 struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
15896 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
15897
15898 /* Clear any frame start delays used for debugging left by the BIOS */
15899 if (crtc->active && !transcoder_is_dsi(cpu_transcoder)) {
15900 i915_reg_t reg = PIPECONF(cpu_transcoder);
15901
15902 I915_WRITE(reg,
15903 I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15904 }
15905
15906 if (crtc_state->base.active) {
15907 struct intel_plane *plane;
15908
15909 /* Disable everything but the primary plane */
15910 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15911 const struct intel_plane_state *plane_state =
15912 to_intel_plane_state(plane->base.state);
15913
15914 if (plane_state->base.visible &&
15915 plane->base.type != DRM_PLANE_TYPE_PRIMARY)
15916 intel_plane_disable_noatomic(crtc, plane);
15917 }
15918
15919 /*
15920 * Disable any background color set by the BIOS, but enable the
15921 * gamma and CSC to match how we program our planes.
15922 */
15923 if (INTEL_GEN(dev_priv) >= 9)
15924 I915_WRITE(SKL_BOTTOM_COLOR(crtc->pipe),
15925 SKL_BOTTOM_COLOR_GAMMA_ENABLE |
15926 SKL_BOTTOM_COLOR_CSC_ENABLE);
15927 }
15928
15929 /* Adjust the state of the output pipe according to whether we
15930 * have active connectors/encoders. */
15931 if (crtc_state->base.active && !intel_crtc_has_encoders(crtc))
15932 intel_crtc_disable_noatomic(&crtc->base, ctx);
15933
15934 if (crtc_state->base.active || HAS_GMCH(dev_priv)) {
15935 /*
15936 * We start out with underrun reporting disabled to avoid races.
15937 * For correct bookkeeping mark this on active crtcs.
15938 *
15939 * Also on gmch platforms we dont have any hardware bits to
15940 * disable the underrun reporting. Which means we need to start
15941 * out with underrun reporting disabled also on inactive pipes,
15942 * since otherwise we'll complain about the garbage we read when
15943 * e.g. coming up after runtime pm.
15944 *
15945 * No protection against concurrent access is required - at
15946 * worst a fifo underrun happens which also sets this to false.
15947 */
15948 crtc->cpu_fifo_underrun_disabled = true;
15949 /*
15950 * We track the PCH trancoder underrun reporting state
15951 * within the crtc. With crtc for pipe A housing the underrun
15952 * reporting state for PCH transcoder A, crtc for pipe B housing
15953 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
15954 * and marking underrun reporting as disabled for the non-existing
15955 * PCH transcoders B and C would prevent enabling the south
15956 * error interrupt (see cpt_can_enable_serr_int()).
15957 */
15958 if (has_pch_trancoder(dev_priv, crtc->pipe))
15959 crtc->pch_fifo_underrun_disabled = true;
15960 }
15961 }
15962
15963 static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state)
15964 {
15965 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
15966
15967 /*
15968 * Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram
15969 * the hardware when a high res displays plugged in. DPLL P
15970 * divider is zero, and the pipe timings are bonkers. We'll
15971 * try to disable everything in that case.
15972 *
15973 * FIXME would be nice to be able to sanitize this state
15974 * without several WARNs, but for now let's take the easy
15975 * road.
15976 */
15977 return IS_GEN(dev_priv, 6) &&
15978 crtc_state->base.active &&
15979 crtc_state->shared_dpll &&
15980 crtc_state->port_clock == 0;
15981 }
15982
15983 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15984 {
15985 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
15986 struct intel_connector *connector;
15987 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
15988 struct intel_crtc_state *crtc_state = crtc ?
15989 to_intel_crtc_state(crtc->base.state) : NULL;
15990
15991 /* We need to check both for a crtc link (meaning that the
15992 * encoder is active and trying to read from a pipe) and the
15993 * pipe itself being active. */
15994 bool has_active_crtc = crtc_state &&
15995 crtc_state->base.active;
15996
15997 if (crtc_state && has_bogus_dpll_config(crtc_state)) {
15998 DRM_DEBUG_KMS("BIOS has misprogrammed the hardware. Disabling pipe %c\n",
15999 pipe_name(crtc->pipe));
16000 has_active_crtc = false;
16001 }
16002
16003 connector = intel_encoder_find_connector(encoder);
16004 if (connector && !has_active_crtc) {
16005 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
16006 encoder->base.base.id,
16007 encoder->base.name);
16008
16009 /* Connector is active, but has no active pipe. This is
16010 * fallout from our resume register restoring. Disable
16011 * the encoder manually again. */
16012 if (crtc_state) {
16013 struct drm_encoder *best_encoder;
16014
16015 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
16016 encoder->base.base.id,
16017 encoder->base.name);
16018
16019 /* avoid oopsing in case the hooks consult best_encoder */
16020 best_encoder = connector->base.state->best_encoder;
16021 connector->base.state->best_encoder = &encoder->base;
16022
16023 if (encoder->disable)
16024 encoder->disable(encoder, crtc_state,
16025 connector->base.state);
16026 if (encoder->post_disable)
16027 encoder->post_disable(encoder, crtc_state,
16028 connector->base.state);
16029
16030 connector->base.state->best_encoder = best_encoder;
16031 }
16032 encoder->base.crtc = NULL;
16033
16034 /* Inconsistent output/port/pipe state happens presumably due to
16035 * a bug in one of the get_hw_state functions. Or someplace else
16036 * in our code, like the register restore mess on resume. Clamp
16037 * things to off as a safer default. */
16038
16039 connector->base.dpms = DRM_MODE_DPMS_OFF;
16040 connector->base.encoder = NULL;
16041 }
16042
16043 /* notify opregion of the sanitized encoder state */
16044 intel_opregion_notify_encoder(encoder, connector && has_active_crtc);
16045
16046 if (INTEL_GEN(dev_priv) >= 11)
16047 icl_sanitize_encoder_pll_mapping(encoder);
16048 }
16049
16050 void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv)
16051 {
16052 i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
16053
16054 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
16055 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
16056 i915_disable_vga(dev_priv);
16057 }
16058 }
16059
16060 void i915_redisable_vga(struct drm_i915_private *dev_priv)
16061 {
16062 intel_wakeref_t wakeref;
16063
16064 /*
16065 * This function can be called both from intel_modeset_setup_hw_state or
16066 * at a very early point in our resume sequence, where the power well
16067 * structures are not yet restored. Since this function is at a very
16068 * paranoid "someone might have enabled VGA while we were not looking"
16069 * level, just check if the power well is enabled instead of trying to
16070 * follow the "don't touch the power well if we don't need it" policy
16071 * the rest of the driver uses.
16072 */
16073 wakeref = intel_display_power_get_if_enabled(dev_priv,
16074 POWER_DOMAIN_VGA);
16075 if (!wakeref)
16076 return;
16077
16078 i915_redisable_vga_power_on(dev_priv);
16079
16080 intel_display_power_put(dev_priv, POWER_DOMAIN_VGA, wakeref);
16081 }
16082
16083 /* FIXME read out full plane state for all planes */
16084 static void readout_plane_state(struct drm_i915_private *dev_priv)
16085 {
16086 struct intel_plane *plane;
16087 struct intel_crtc *crtc;
16088
16089 for_each_intel_plane(&dev_priv->drm, plane) {
16090 struct intel_plane_state *plane_state =
16091 to_intel_plane_state(plane->base.state);
16092 struct intel_crtc_state *crtc_state;
16093 enum pipe pipe = PIPE_A;
16094 bool visible;
16095
16096 visible = plane->get_hw_state(plane, &pipe);
16097
16098 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
16099 crtc_state = to_intel_crtc_state(crtc->base.state);
16100
16101 intel_set_plane_visible(crtc_state, plane_state, visible);
16102
16103 DRM_DEBUG_KMS("[PLANE:%d:%s] hw state readout: %s, pipe %c\n",
16104 plane->base.base.id, plane->base.name,
16105 enableddisabled(visible), pipe_name(pipe));
16106 }
16107
16108 for_each_intel_crtc(&dev_priv->drm, crtc) {
16109 struct intel_crtc_state *crtc_state =
16110 to_intel_crtc_state(crtc->base.state);
16111
16112 fixup_active_planes(crtc_state);
16113 }
16114 }
16115
16116 static void intel_modeset_readout_hw_state(struct drm_device *dev)
16117 {
16118 struct drm_i915_private *dev_priv = to_i915(dev);
16119 enum pipe pipe;
16120 struct intel_crtc *crtc;
16121 struct intel_encoder *encoder;
16122 struct intel_connector *connector;
16123 struct drm_connector_list_iter conn_iter;
16124 int i;
16125
16126 dev_priv->active_crtcs = 0;
16127
16128 for_each_intel_crtc(dev, crtc) {
16129 struct intel_crtc_state *crtc_state =
16130 to_intel_crtc_state(crtc->base.state);
16131
16132 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
16133 memset(crtc_state, 0, sizeof(*crtc_state));
16134 crtc_state->base.crtc = &crtc->base;
16135
16136 crtc_state->base.active = crtc_state->base.enable =
16137 dev_priv->display.get_pipe_config(crtc, crtc_state);
16138
16139 crtc->base.enabled = crtc_state->base.enable;
16140 crtc->active = crtc_state->base.active;
16141
16142 if (crtc_state->base.active)
16143 dev_priv->active_crtcs |= 1 << crtc->pipe;
16144
16145 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
16146 crtc->base.base.id, crtc->base.name,
16147 enableddisabled(crtc_state->base.active));
16148 }
16149
16150 readout_plane_state(dev_priv);
16151
16152 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
16153 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
16154
16155 pll->on = pll->info->funcs->get_hw_state(dev_priv, pll,
16156 &pll->state.hw_state);
16157 pll->state.crtc_mask = 0;
16158 for_each_intel_crtc(dev, crtc) {
16159 struct intel_crtc_state *crtc_state =
16160 to_intel_crtc_state(crtc->base.state);
16161
16162 if (crtc_state->base.active &&
16163 crtc_state->shared_dpll == pll)
16164 pll->state.crtc_mask |= 1 << crtc->pipe;
16165 }
16166 pll->active_mask = pll->state.crtc_mask;
16167
16168 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
16169 pll->info->name, pll->state.crtc_mask, pll->on);
16170 }
16171
16172 for_each_intel_encoder(dev, encoder) {
16173 pipe = 0;
16174
16175 if (encoder->get_hw_state(encoder, &pipe)) {
16176 struct intel_crtc_state *crtc_state;
16177
16178 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
16179 crtc_state = to_intel_crtc_state(crtc->base.state);
16180
16181 encoder->base.crtc = &crtc->base;
16182 encoder->get_config(encoder, crtc_state);
16183 } else {
16184 encoder->base.crtc = NULL;
16185 }
16186
16187 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
16188 encoder->base.base.id, encoder->base.name,
16189 enableddisabled(encoder->base.crtc),
16190 pipe_name(pipe));
16191 }
16192
16193 drm_connector_list_iter_begin(dev, &conn_iter);
16194 for_each_intel_connector_iter(connector, &conn_iter) {
16195 if (connector->get_hw_state(connector)) {
16196 connector->base.dpms = DRM_MODE_DPMS_ON;
16197
16198 encoder = connector->encoder;
16199 connector->base.encoder = &encoder->base;
16200
16201 if (encoder->base.crtc &&
16202 encoder->base.crtc->state->active) {
16203 /*
16204 * This has to be done during hardware readout
16205 * because anything calling .crtc_disable may
16206 * rely on the connector_mask being accurate.
16207 */
16208 encoder->base.crtc->state->connector_mask |=
16209 drm_connector_mask(&connector->base);
16210 encoder->base.crtc->state->encoder_mask |=
16211 drm_encoder_mask(&encoder->base);
16212 }
16213
16214 } else {
16215 connector->base.dpms = DRM_MODE_DPMS_OFF;
16216 connector->base.encoder = NULL;
16217 }
16218 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
16219 connector->base.base.id, connector->base.name,
16220 enableddisabled(connector->base.encoder));
16221 }
16222 drm_connector_list_iter_end(&conn_iter);
16223
16224 for_each_intel_crtc(dev, crtc) {
16225 struct intel_crtc_state *crtc_state =
16226 to_intel_crtc_state(crtc->base.state);
16227 int min_cdclk = 0;
16228
16229 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
16230 if (crtc_state->base.active) {
16231 intel_mode_from_pipe_config(&crtc->base.mode, crtc_state);
16232 crtc->base.mode.hdisplay = crtc_state->pipe_src_w;
16233 crtc->base.mode.vdisplay = crtc_state->pipe_src_h;
16234 intel_mode_from_pipe_config(&crtc_state->base.adjusted_mode, crtc_state);
16235 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
16236
16237 /*
16238 * The initial mode needs to be set in order to keep
16239 * the atomic core happy. It wants a valid mode if the
16240 * crtc's enabled, so we do the above call.
16241 *
16242 * But we don't set all the derived state fully, hence
16243 * set a flag to indicate that a full recalculation is
16244 * needed on the next commit.
16245 */
16246 crtc_state->base.mode.private_flags = I915_MODE_FLAG_INHERITED;
16247
16248 intel_crtc_compute_pixel_rate(crtc_state);
16249
16250 if (dev_priv->display.modeset_calc_cdclk) {
16251 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
16252 if (WARN_ON(min_cdclk < 0))
16253 min_cdclk = 0;
16254 }
16255
16256 drm_calc_timestamping_constants(&crtc->base,
16257 &crtc_state->base.adjusted_mode);
16258 update_scanline_offset(crtc_state);
16259 }
16260
16261 dev_priv->min_cdclk[crtc->pipe] = min_cdclk;
16262 dev_priv->min_voltage_level[crtc->pipe] =
16263 crtc_state->min_voltage_level;
16264
16265 intel_pipe_config_sanity_check(dev_priv, crtc_state);
16266 }
16267 }
16268
16269 static void
16270 get_encoder_power_domains(struct drm_i915_private *dev_priv)
16271 {
16272 struct intel_encoder *encoder;
16273
16274 for_each_intel_encoder(&dev_priv->drm, encoder) {
16275 u64 get_domains;
16276 enum intel_display_power_domain domain;
16277 struct intel_crtc_state *crtc_state;
16278
16279 if (!encoder->get_power_domains)
16280 continue;
16281
16282 /*
16283 * MST-primary and inactive encoders don't have a crtc state
16284 * and neither of these require any power domain references.
16285 */
16286 if (!encoder->base.crtc)
16287 continue;
16288
16289 crtc_state = to_intel_crtc_state(encoder->base.crtc->state);
16290 get_domains = encoder->get_power_domains(encoder, crtc_state);
16291 for_each_power_domain(domain, get_domains)
16292 intel_display_power_get(dev_priv, domain);
16293 }
16294 }
16295
16296 static void intel_early_display_was(struct drm_i915_private *dev_priv)
16297 {
16298 /* Display WA #1185 WaDisableDARBFClkGating:cnl,glk */
16299 if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
16300 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
16301 DARBF_GATING_DIS);
16302
16303 if (IS_HASWELL(dev_priv)) {
16304 /*
16305 * WaRsPkgCStateDisplayPMReq:hsw
16306 * System hang if this isn't done before disabling all planes!
16307 */
16308 I915_WRITE(CHICKEN_PAR1_1,
16309 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
16310 }
16311 }
16312
16313 static void ibx_sanitize_pch_hdmi_port(struct drm_i915_private *dev_priv,
16314 enum port port, i915_reg_t hdmi_reg)
16315 {
16316 u32 val = I915_READ(hdmi_reg);
16317
16318 if (val & SDVO_ENABLE ||
16319 (val & SDVO_PIPE_SEL_MASK) == SDVO_PIPE_SEL(PIPE_A))
16320 return;
16321
16322 DRM_DEBUG_KMS("Sanitizing transcoder select for HDMI %c\n",
16323 port_name(port));
16324
16325 val &= ~SDVO_PIPE_SEL_MASK;
16326 val |= SDVO_PIPE_SEL(PIPE_A);
16327
16328 I915_WRITE(hdmi_reg, val);
16329 }
16330
16331 static void ibx_sanitize_pch_dp_port(struct drm_i915_private *dev_priv,
16332 enum port port, i915_reg_t dp_reg)
16333 {
16334 u32 val = I915_READ(dp_reg);
16335
16336 if (val & DP_PORT_EN ||
16337 (val & DP_PIPE_SEL_MASK) == DP_PIPE_SEL(PIPE_A))
16338 return;
16339
16340 DRM_DEBUG_KMS("Sanitizing transcoder select for DP %c\n",
16341 port_name(port));
16342
16343 val &= ~DP_PIPE_SEL_MASK;
16344 val |= DP_PIPE_SEL(PIPE_A);
16345
16346 I915_WRITE(dp_reg, val);
16347 }
16348
16349 static void ibx_sanitize_pch_ports(struct drm_i915_private *dev_priv)
16350 {
16351 /*
16352 * The BIOS may select transcoder B on some of the PCH
16353 * ports even it doesn't enable the port. This would trip
16354 * assert_pch_dp_disabled() and assert_pch_hdmi_disabled().
16355 * Sanitize the transcoder select bits to prevent that. We
16356 * assume that the BIOS never actually enabled the port,
16357 * because if it did we'd actually have to toggle the port
16358 * on and back off to make the transcoder A select stick
16359 * (see. intel_dp_link_down(), intel_disable_hdmi(),
16360 * intel_disable_sdvo()).
16361 */
16362 ibx_sanitize_pch_dp_port(dev_priv, PORT_B, PCH_DP_B);
16363 ibx_sanitize_pch_dp_port(dev_priv, PORT_C, PCH_DP_C);
16364 ibx_sanitize_pch_dp_port(dev_priv, PORT_D, PCH_DP_D);
16365
16366 /* PCH SDVOB multiplex with HDMIB */
16367 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_B, PCH_HDMIB);
16368 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_C, PCH_HDMIC);
16369 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_D, PCH_HDMID);
16370 }
16371
16372 /* Scan out the current hw modeset state,
16373 * and sanitizes it to the current state
16374 */
16375 static void
16376 intel_modeset_setup_hw_state(struct drm_device *dev,
16377 struct drm_modeset_acquire_ctx *ctx)
16378 {
16379 struct drm_i915_private *dev_priv = to_i915(dev);
16380 struct intel_crtc_state *crtc_state;
16381 struct intel_encoder *encoder;
16382 struct intel_crtc *crtc;
16383 intel_wakeref_t wakeref;
16384 int i;
16385
16386 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
16387
16388 intel_early_display_was(dev_priv);
16389 intel_modeset_readout_hw_state(dev);
16390
16391 /* HW state is read out, now we need to sanitize this mess. */
16392 get_encoder_power_domains(dev_priv);
16393
16394 if (HAS_PCH_IBX(dev_priv))
16395 ibx_sanitize_pch_ports(dev_priv);
16396
16397 /*
16398 * intel_sanitize_plane_mapping() may need to do vblank
16399 * waits, so we need vblank interrupts restored beforehand.
16400 */
16401 for_each_intel_crtc(&dev_priv->drm, crtc) {
16402 crtc_state = to_intel_crtc_state(crtc->base.state);
16403
16404 drm_crtc_vblank_reset(&crtc->base);
16405
16406 if (crtc_state->base.active)
16407 intel_crtc_vblank_on(crtc_state);
16408 }
16409
16410 intel_sanitize_plane_mapping(dev_priv);
16411
16412 for_each_intel_encoder(dev, encoder)
16413 intel_sanitize_encoder(encoder);
16414
16415 for_each_intel_crtc(&dev_priv->drm, crtc) {
16416 crtc_state = to_intel_crtc_state(crtc->base.state);
16417 intel_sanitize_crtc(crtc, ctx);
16418 intel_dump_pipe_config(crtc, crtc_state,
16419 "[setup_hw_state]");
16420 }
16421
16422 intel_modeset_update_connector_atomic_state(dev);
16423
16424 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
16425 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
16426
16427 if (!pll->on || pll->active_mask)
16428 continue;
16429
16430 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n",
16431 pll->info->name);
16432
16433 pll->info->funcs->disable(dev_priv, pll);
16434 pll->on = false;
16435 }
16436
16437 if (IS_G4X(dev_priv)) {
16438 g4x_wm_get_hw_state(dev_priv);
16439 g4x_wm_sanitize(dev_priv);
16440 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
16441 vlv_wm_get_hw_state(dev_priv);
16442 vlv_wm_sanitize(dev_priv);
16443 } else if (INTEL_GEN(dev_priv) >= 9) {
16444 skl_wm_get_hw_state(dev_priv);
16445 } else if (HAS_PCH_SPLIT(dev_priv)) {
16446 ilk_wm_get_hw_state(dev_priv);
16447 }
16448
16449 for_each_intel_crtc(dev, crtc) {
16450 u64 put_domains;
16451
16452 crtc_state = to_intel_crtc_state(crtc->base.state);
16453 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc_state);
16454 if (WARN_ON(put_domains))
16455 modeset_put_power_domains(dev_priv, put_domains);
16456 }
16457
16458 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref);
16459
16460 intel_fbc_init_pipe_state(dev_priv);
16461 }
16462
16463 void intel_display_resume(struct drm_device *dev)
16464 {
16465 struct drm_i915_private *dev_priv = to_i915(dev);
16466 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
16467 struct drm_modeset_acquire_ctx ctx;
16468 int ret;
16469
16470 dev_priv->modeset_restore_state = NULL;
16471 if (state)
16472 state->acquire_ctx = &ctx;
16473
16474 drm_modeset_acquire_init(&ctx, 0);
16475
16476 while (1) {
16477 ret = drm_modeset_lock_all_ctx(dev, &ctx);
16478 if (ret != -EDEADLK)
16479 break;
16480
16481 drm_modeset_backoff(&ctx);
16482 }
16483
16484 if (!ret)
16485 ret = __intel_display_resume(dev, state, &ctx);
16486
16487 intel_enable_ipc(dev_priv);
16488 drm_modeset_drop_locks(&ctx);
16489 drm_modeset_acquire_fini(&ctx);
16490
16491 if (ret)
16492 DRM_ERROR("Restoring old state failed with %i\n", ret);
16493 if (state)
16494 drm_atomic_state_put(state);
16495 }
16496
16497 static void intel_hpd_poll_fini(struct drm_device *dev)
16498 {
16499 struct intel_connector *connector;
16500 struct drm_connector_list_iter conn_iter;
16501
16502 /* Kill all the work that may have been queued by hpd. */
16503 drm_connector_list_iter_begin(dev, &conn_iter);
16504 for_each_intel_connector_iter(connector, &conn_iter) {
16505 if (connector->modeset_retry_work.func)
16506 cancel_work_sync(&connector->modeset_retry_work);
16507 if (connector->hdcp.shim) {
16508 cancel_delayed_work_sync(&connector->hdcp.check_work);
16509 cancel_work_sync(&connector->hdcp.prop_work);
16510 }
16511 }
16512 drm_connector_list_iter_end(&conn_iter);
16513 }
16514
16515 void intel_modeset_cleanup(struct drm_device *dev)
16516 {
16517 struct drm_i915_private *dev_priv = to_i915(dev);
16518
16519 flush_workqueue(dev_priv->modeset_wq);
16520
16521 flush_work(&dev_priv->atomic_helper.free_work);
16522 WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list));
16523
16524 /*
16525 * Interrupts and polling as the first thing to avoid creating havoc.
16526 * Too much stuff here (turning of connectors, ...) would
16527 * experience fancy races otherwise.
16528 */
16529 intel_irq_uninstall(dev_priv);
16530
16531 /*
16532 * Due to the hpd irq storm handling the hotplug work can re-arm the
16533 * poll handlers. Hence disable polling after hpd handling is shut down.
16534 */
16535 intel_hpd_poll_fini(dev);
16536
16537 /* poll work can call into fbdev, hence clean that up afterwards */
16538 intel_fbdev_fini(dev_priv);
16539
16540 intel_unregister_dsm_handler();
16541
16542 intel_fbc_global_disable(dev_priv);
16543
16544 /* flush any delayed tasks or pending work */
16545 flush_scheduled_work();
16546
16547 intel_hdcp_component_fini(dev_priv);
16548
16549 drm_mode_config_cleanup(dev);
16550
16551 intel_overlay_cleanup(dev_priv);
16552
16553 intel_teardown_gmbus(dev_priv);
16554
16555 destroy_workqueue(dev_priv->modeset_wq);
16556
16557 intel_fbc_cleanup_cfb(dev_priv);
16558 }
16559
16560 /*
16561 * set vga decode state - true == enable VGA decode
16562 */
16563 int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state)
16564 {
16565 unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
16566 u16 gmch_ctrl;
16567
16568 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
16569 DRM_ERROR("failed to read control word\n");
16570 return -EIO;
16571 }
16572
16573 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
16574 return 0;
16575
16576 if (state)
16577 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
16578 else
16579 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
16580
16581 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
16582 DRM_ERROR("failed to write control word\n");
16583 return -EIO;
16584 }
16585
16586 return 0;
16587 }
16588
16589 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
16590
16591 struct intel_display_error_state {
16592
16593 u32 power_well_driver;
16594
16595 struct intel_cursor_error_state {
16596 u32 control;
16597 u32 position;
16598 u32 base;
16599 u32 size;
16600 } cursor[I915_MAX_PIPES];
16601
16602 struct intel_pipe_error_state {
16603 bool power_domain_on;
16604 u32 source;
16605 u32 stat;
16606 } pipe[I915_MAX_PIPES];
16607
16608 struct intel_plane_error_state {
16609 u32 control;
16610 u32 stride;
16611 u32 size;
16612 u32 pos;
16613 u32 addr;
16614 u32 surface;
16615 u32 tile_offset;
16616 } plane[I915_MAX_PIPES];
16617
16618 struct intel_transcoder_error_state {
16619 bool available;
16620 bool power_domain_on;
16621 enum transcoder cpu_transcoder;
16622
16623 u32 conf;
16624
16625 u32 htotal;
16626 u32 hblank;
16627 u32 hsync;
16628 u32 vtotal;
16629 u32 vblank;
16630 u32 vsync;
16631 } transcoder[4];
16632 };
16633
16634 struct intel_display_error_state *
16635 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
16636 {
16637 struct intel_display_error_state *error;
16638 int transcoders[] = {
16639 TRANSCODER_A,
16640 TRANSCODER_B,
16641 TRANSCODER_C,
16642 TRANSCODER_EDP,
16643 };
16644 int i;
16645
16646 BUILD_BUG_ON(ARRAY_SIZE(transcoders) != ARRAY_SIZE(error->transcoder));
16647
16648 if (!HAS_DISPLAY(dev_priv))
16649 return NULL;
16650
16651 error = kzalloc(sizeof(*error), GFP_ATOMIC);
16652 if (error == NULL)
16653 return NULL;
16654
16655 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
16656 error->power_well_driver = I915_READ(HSW_PWR_WELL_CTL2);
16657
16658 for_each_pipe(dev_priv, i) {
16659 error->pipe[i].power_domain_on =
16660 __intel_display_power_is_enabled(dev_priv,
16661 POWER_DOMAIN_PIPE(i));
16662 if (!error->pipe[i].power_domain_on)
16663 continue;
16664
16665 error->cursor[i].control = I915_READ(CURCNTR(i));
16666 error->cursor[i].position = I915_READ(CURPOS(i));
16667 error->cursor[i].base = I915_READ(CURBASE(i));
16668
16669 error->plane[i].control = I915_READ(DSPCNTR(i));
16670 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
16671 if (INTEL_GEN(dev_priv) <= 3) {
16672 error->plane[i].size = I915_READ(DSPSIZE(i));
16673 error->plane[i].pos = I915_READ(DSPPOS(i));
16674 }
16675 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
16676 error->plane[i].addr = I915_READ(DSPADDR(i));
16677 if (INTEL_GEN(dev_priv) >= 4) {
16678 error->plane[i].surface = I915_READ(DSPSURF(i));
16679 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
16680 }
16681
16682 error->pipe[i].source = I915_READ(PIPESRC(i));
16683
16684 if (HAS_GMCH(dev_priv))
16685 error->pipe[i].stat = I915_READ(PIPESTAT(i));
16686 }
16687
16688 for (i = 0; i < ARRAY_SIZE(error->transcoder); i++) {
16689 enum transcoder cpu_transcoder = transcoders[i];
16690
16691 if (!INTEL_INFO(dev_priv)->trans_offsets[cpu_transcoder])
16692 continue;
16693
16694 error->transcoder[i].available = true;
16695 error->transcoder[i].power_domain_on =
16696 __intel_display_power_is_enabled(dev_priv,
16697 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
16698 if (!error->transcoder[i].power_domain_on)
16699 continue;
16700
16701 error->transcoder[i].cpu_transcoder = cpu_transcoder;
16702
16703 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
16704 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
16705 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
16706 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
16707 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
16708 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
16709 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
16710 }
16711
16712 return error;
16713 }
16714
16715 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
16716
16717 void
16718 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
16719 struct intel_display_error_state *error)
16720 {
16721 struct drm_i915_private *dev_priv = m->i915;
16722 int i;
16723
16724 if (!error)
16725 return;
16726
16727 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes);
16728 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
16729 err_printf(m, "PWR_WELL_CTL2: %08x\n",
16730 error->power_well_driver);
16731 for_each_pipe(dev_priv, i) {
16732 err_printf(m, "Pipe [%d]:\n", i);
16733 err_printf(m, " Power: %s\n",
16734 onoff(error->pipe[i].power_domain_on));
16735 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
16736 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
16737
16738 err_printf(m, "Plane [%d]:\n", i);
16739 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
16740 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
16741 if (INTEL_GEN(dev_priv) <= 3) {
16742 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
16743 err_printf(m, " POS: %08x\n", error->plane[i].pos);
16744 }
16745 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
16746 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
16747 if (INTEL_GEN(dev_priv) >= 4) {
16748 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
16749 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
16750 }
16751
16752 err_printf(m, "Cursor [%d]:\n", i);
16753 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
16754 err_printf(m, " POS: %08x\n", error->cursor[i].position);
16755 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
16756 }
16757
16758 for (i = 0; i < ARRAY_SIZE(error->transcoder); i++) {
16759 if (!error->transcoder[i].available)
16760 continue;
16761
16762 err_printf(m, "CPU transcoder: %s\n",
16763 transcoder_name(error->transcoder[i].cpu_transcoder));
16764 err_printf(m, " Power: %s\n",
16765 onoff(error->transcoder[i].power_domain_on));
16766 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
16767 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
16768 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
16769 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
16770 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
16771 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
16772 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
16773 }
16774 }
16775
16776 #endif
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git