2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_edid.h>
35 #include "intel_drv.h"
36 #include <drm/i915_drm.h>
39 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
43 * @intel_dp: DP struct
45 * If a CPU or PCH DP output is attached to an eDP panel, this function
46 * will return true, and false otherwise.
48 static bool is_edp(struct intel_dp
*intel_dp
)
50 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
52 return intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
;
56 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
57 * @intel_dp: DP struct
59 * Returns true if the given DP struct corresponds to a PCH DP port attached
60 * to an eDP panel, false otherwise. Helpful for determining whether we
61 * may need FDI resources for a given DP output or not.
63 static bool is_pch_edp(struct intel_dp
*intel_dp
)
65 return intel_dp
->is_pch_edp
;
69 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
70 * @intel_dp: DP struct
72 * Returns true if the given DP struct corresponds to a CPU eDP port.
74 static bool is_cpu_edp(struct intel_dp
*intel_dp
)
76 return is_edp(intel_dp
) && !is_pch_edp(intel_dp
);
79 static struct drm_device
*intel_dp_to_dev(struct intel_dp
*intel_dp
)
81 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
83 return intel_dig_port
->base
.base
.dev
;
86 static struct intel_dp
*intel_attached_dp(struct drm_connector
*connector
)
88 return enc_to_intel_dp(&intel_attached_encoder(connector
)->base
);
92 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
93 * @encoder: DRM encoder
95 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
98 bool intel_encoder_is_pch_edp(struct drm_encoder
*encoder
)
100 struct intel_dp
*intel_dp
;
105 intel_dp
= enc_to_intel_dp(encoder
);
107 return is_pch_edp(intel_dp
);
110 static void intel_dp_link_down(struct intel_dp
*intel_dp
);
113 intel_dp_max_link_bw(struct intel_dp
*intel_dp
)
115 int max_link_bw
= intel_dp
->dpcd
[DP_MAX_LINK_RATE
];
117 switch (max_link_bw
) {
118 case DP_LINK_BW_1_62
:
122 max_link_bw
= DP_LINK_BW_1_62
;
129 * The units on the numbers in the next two are... bizarre. Examples will
130 * make it clearer; this one parallels an example in the eDP spec.
132 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
134 * 270000 * 1 * 8 / 10 == 216000
136 * The actual data capacity of that configuration is 2.16Gbit/s, so the
137 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
138 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
139 * 119000. At 18bpp that's 2142000 kilobits per second.
141 * Thus the strange-looking division by 10 in intel_dp_link_required, to
142 * get the result in decakilobits instead of kilobits.
146 intel_dp_link_required(int pixel_clock
, int bpp
)
148 return (pixel_clock
* bpp
+ 9) / 10;
152 intel_dp_max_data_rate(int max_link_clock
, int max_lanes
)
154 return (max_link_clock
* max_lanes
* 8) / 10;
158 intel_dp_mode_valid(struct drm_connector
*connector
,
159 struct drm_display_mode
*mode
)
161 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
162 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
163 struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
164 int target_clock
= mode
->clock
;
165 int max_rate
, mode_rate
, max_lanes
, max_link_clock
;
167 if (is_edp(intel_dp
) && fixed_mode
) {
168 if (mode
->hdisplay
> fixed_mode
->hdisplay
)
171 if (mode
->vdisplay
> fixed_mode
->vdisplay
)
174 target_clock
= fixed_mode
->clock
;
177 max_link_clock
= drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp
));
178 max_lanes
= drm_dp_max_lane_count(intel_dp
->dpcd
);
180 max_rate
= intel_dp_max_data_rate(max_link_clock
, max_lanes
);
181 mode_rate
= intel_dp_link_required(target_clock
, 18);
183 if (mode_rate
> max_rate
)
184 return MODE_CLOCK_HIGH
;
186 if (mode
->clock
< 10000)
187 return MODE_CLOCK_LOW
;
189 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
190 return MODE_H_ILLEGAL
;
196 pack_aux(uint8_t *src
, int src_bytes
)
203 for (i
= 0; i
< src_bytes
; i
++)
204 v
|= ((uint32_t) src
[i
]) << ((3-i
) * 8);
209 unpack_aux(uint32_t src
, uint8_t *dst
, int dst_bytes
)
214 for (i
= 0; i
< dst_bytes
; i
++)
215 dst
[i
] = src
>> ((3-i
) * 8);
218 /* hrawclock is 1/4 the FSB frequency */
220 intel_hrawclk(struct drm_device
*dev
)
222 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
225 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
226 if (IS_VALLEYVIEW(dev
))
229 clkcfg
= I915_READ(CLKCFG
);
230 switch (clkcfg
& CLKCFG_FSB_MASK
) {
239 case CLKCFG_FSB_1067
:
241 case CLKCFG_FSB_1333
:
243 /* these two are just a guess; one of them might be right */
244 case CLKCFG_FSB_1600
:
245 case CLKCFG_FSB_1600_ALT
:
252 static bool ironlake_edp_have_panel_power(struct intel_dp
*intel_dp
)
254 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
255 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
258 pp_stat_reg
= IS_VALLEYVIEW(dev
) ? PIPEA_PP_STATUS
: PCH_PP_STATUS
;
259 return (I915_READ(pp_stat_reg
) & PP_ON
) != 0;
262 static bool ironlake_edp_have_panel_vdd(struct intel_dp
*intel_dp
)
264 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
265 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
268 pp_ctrl_reg
= IS_VALLEYVIEW(dev
) ? PIPEA_PP_CONTROL
: PCH_PP_CONTROL
;
269 return (I915_READ(pp_ctrl_reg
) & EDP_FORCE_VDD
) != 0;
273 intel_dp_check_edp(struct intel_dp
*intel_dp
)
275 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
276 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
277 u32 pp_stat_reg
, pp_ctrl_reg
;
279 if (!is_edp(intel_dp
))
282 pp_stat_reg
= IS_VALLEYVIEW(dev
) ? PIPEA_PP_STATUS
: PCH_PP_STATUS
;
283 pp_ctrl_reg
= IS_VALLEYVIEW(dev
) ? PIPEA_PP_CONTROL
: PCH_PP_CONTROL
;
285 if (!ironlake_edp_have_panel_power(intel_dp
) && !ironlake_edp_have_panel_vdd(intel_dp
)) {
286 WARN(1, "eDP powered off while attempting aux channel communication.\n");
287 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
288 I915_READ(pp_stat_reg
),
289 I915_READ(pp_ctrl_reg
));
294 intel_dp_aux_wait_done(struct intel_dp
*intel_dp
, bool has_aux_irq
)
296 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
297 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
298 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
299 uint32_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
303 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
305 done
= wait_event_timeout(dev_priv
->gmbus_wait_queue
, C
,
306 msecs_to_jiffies(10));
308 done
= wait_for_atomic(C
, 10) == 0;
310 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
318 intel_dp_aux_ch(struct intel_dp
*intel_dp
,
319 uint8_t *send
, int send_bytes
,
320 uint8_t *recv
, int recv_size
)
322 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
323 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
324 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
325 uint32_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
326 uint32_t ch_data
= ch_ctl
+ 4;
327 int i
, ret
, recv_bytes
;
329 uint32_t aux_clock_divider
;
331 bool has_aux_irq
= INTEL_INFO(dev
)->gen
>= 5 && !IS_VALLEYVIEW(dev
);
333 /* dp aux is extremely sensitive to irq latency, hence request the
334 * lowest possible wakeup latency and so prevent the cpu from going into
337 pm_qos_update_request(&dev_priv
->pm_qos
, 0);
339 intel_dp_check_edp(intel_dp
);
340 /* The clock divider is based off the hrawclk,
341 * and would like to run at 2MHz. So, take the
342 * hrawclk value and divide by 2 and use that
344 * Note that PCH attached eDP panels should use a 125MHz input
347 if (is_cpu_edp(intel_dp
)) {
349 aux_clock_divider
= intel_ddi_get_cdclk_freq(dev_priv
) >> 1;
350 else if (IS_VALLEYVIEW(dev
))
351 aux_clock_divider
= 100;
352 else if (IS_GEN6(dev
) || IS_GEN7(dev
))
353 aux_clock_divider
= 200; /* SNB & IVB eDP input clock at 400Mhz */
355 aux_clock_divider
= 225; /* eDP input clock at 450Mhz */
356 } else if (dev_priv
->pch_id
== INTEL_PCH_LPT_DEVICE_ID_TYPE
) {
357 /* Workaround for non-ULT HSW */
358 aux_clock_divider
= 74;
359 } else if (HAS_PCH_SPLIT(dev
)) {
360 aux_clock_divider
= DIV_ROUND_UP(intel_pch_rawclk(dev
), 2);
362 aux_clock_divider
= intel_hrawclk(dev
) / 2;
370 /* Try to wait for any previous AUX channel activity */
371 for (try = 0; try < 3; try++) {
372 status
= I915_READ_NOTRACE(ch_ctl
);
373 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
379 WARN(1, "dp_aux_ch not started status 0x%08x\n",
385 /* Must try at least 3 times according to DP spec */
386 for (try = 0; try < 5; try++) {
387 /* Load the send data into the aux channel data registers */
388 for (i
= 0; i
< send_bytes
; i
+= 4)
389 I915_WRITE(ch_data
+ i
,
390 pack_aux(send
+ i
, send_bytes
- i
));
392 /* Send the command and wait for it to complete */
394 DP_AUX_CH_CTL_SEND_BUSY
|
395 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
396 DP_AUX_CH_CTL_TIME_OUT_400us
|
397 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
398 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
399 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
) |
401 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
402 DP_AUX_CH_CTL_RECEIVE_ERROR
);
404 status
= intel_dp_aux_wait_done(intel_dp
, has_aux_irq
);
406 /* Clear done status and any errors */
410 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
411 DP_AUX_CH_CTL_RECEIVE_ERROR
);
413 if (status
& (DP_AUX_CH_CTL_TIME_OUT_ERROR
|
414 DP_AUX_CH_CTL_RECEIVE_ERROR
))
416 if (status
& DP_AUX_CH_CTL_DONE
)
420 if ((status
& DP_AUX_CH_CTL_DONE
) == 0) {
421 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status
);
426 /* Check for timeout or receive error.
427 * Timeouts occur when the sink is not connected
429 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
430 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status
);
435 /* Timeouts occur when the device isn't connected, so they're
436 * "normal" -- don't fill the kernel log with these */
437 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) {
438 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status
);
443 /* Unload any bytes sent back from the other side */
444 recv_bytes
= ((status
& DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
) >>
445 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
446 if (recv_bytes
> recv_size
)
447 recv_bytes
= recv_size
;
449 for (i
= 0; i
< recv_bytes
; i
+= 4)
450 unpack_aux(I915_READ(ch_data
+ i
),
451 recv
+ i
, recv_bytes
- i
);
455 pm_qos_update_request(&dev_priv
->pm_qos
, PM_QOS_DEFAULT_VALUE
);
460 /* Write data to the aux channel in native mode */
462 intel_dp_aux_native_write(struct intel_dp
*intel_dp
,
463 uint16_t address
, uint8_t *send
, int send_bytes
)
470 intel_dp_check_edp(intel_dp
);
473 msg
[0] = AUX_NATIVE_WRITE
<< 4;
474 msg
[1] = address
>> 8;
475 msg
[2] = address
& 0xff;
476 msg
[3] = send_bytes
- 1;
477 memcpy(&msg
[4], send
, send_bytes
);
478 msg_bytes
= send_bytes
+ 4;
480 ret
= intel_dp_aux_ch(intel_dp
, msg
, msg_bytes
, &ack
, 1);
483 if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_ACK
)
485 else if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_DEFER
)
493 /* Write a single byte to the aux channel in native mode */
495 intel_dp_aux_native_write_1(struct intel_dp
*intel_dp
,
496 uint16_t address
, uint8_t byte
)
498 return intel_dp_aux_native_write(intel_dp
, address
, &byte
, 1);
501 /* read bytes from a native aux channel */
503 intel_dp_aux_native_read(struct intel_dp
*intel_dp
,
504 uint16_t address
, uint8_t *recv
, int recv_bytes
)
513 intel_dp_check_edp(intel_dp
);
514 msg
[0] = AUX_NATIVE_READ
<< 4;
515 msg
[1] = address
>> 8;
516 msg
[2] = address
& 0xff;
517 msg
[3] = recv_bytes
- 1;
520 reply_bytes
= recv_bytes
+ 1;
523 ret
= intel_dp_aux_ch(intel_dp
, msg
, msg_bytes
,
530 if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_ACK
) {
531 memcpy(recv
, reply
+ 1, ret
- 1);
534 else if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_DEFER
)
542 intel_dp_i2c_aux_ch(struct i2c_adapter
*adapter
, int mode
,
543 uint8_t write_byte
, uint8_t *read_byte
)
545 struct i2c_algo_dp_aux_data
*algo_data
= adapter
->algo_data
;
546 struct intel_dp
*intel_dp
= container_of(adapter
,
549 uint16_t address
= algo_data
->address
;
557 intel_dp_check_edp(intel_dp
);
558 /* Set up the command byte */
559 if (mode
& MODE_I2C_READ
)
560 msg
[0] = AUX_I2C_READ
<< 4;
562 msg
[0] = AUX_I2C_WRITE
<< 4;
564 if (!(mode
& MODE_I2C_STOP
))
565 msg
[0] |= AUX_I2C_MOT
<< 4;
567 msg
[1] = address
>> 8;
588 for (retry
= 0; retry
< 5; retry
++) {
589 ret
= intel_dp_aux_ch(intel_dp
,
593 DRM_DEBUG_KMS("aux_ch failed %d\n", ret
);
597 switch (reply
[0] & AUX_NATIVE_REPLY_MASK
) {
598 case AUX_NATIVE_REPLY_ACK
:
599 /* I2C-over-AUX Reply field is only valid
600 * when paired with AUX ACK.
603 case AUX_NATIVE_REPLY_NACK
:
604 DRM_DEBUG_KMS("aux_ch native nack\n");
606 case AUX_NATIVE_REPLY_DEFER
:
610 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
615 switch (reply
[0] & AUX_I2C_REPLY_MASK
) {
616 case AUX_I2C_REPLY_ACK
:
617 if (mode
== MODE_I2C_READ
) {
618 *read_byte
= reply
[1];
620 return reply_bytes
- 1;
621 case AUX_I2C_REPLY_NACK
:
622 DRM_DEBUG_KMS("aux_i2c nack\n");
624 case AUX_I2C_REPLY_DEFER
:
625 DRM_DEBUG_KMS("aux_i2c defer\n");
629 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply
[0]);
634 DRM_ERROR("too many retries, giving up\n");
639 intel_dp_i2c_init(struct intel_dp
*intel_dp
,
640 struct intel_connector
*intel_connector
, const char *name
)
644 DRM_DEBUG_KMS("i2c_init %s\n", name
);
645 intel_dp
->algo
.running
= false;
646 intel_dp
->algo
.address
= 0;
647 intel_dp
->algo
.aux_ch
= intel_dp_i2c_aux_ch
;
649 memset(&intel_dp
->adapter
, '\0', sizeof(intel_dp
->adapter
));
650 intel_dp
->adapter
.owner
= THIS_MODULE
;
651 intel_dp
->adapter
.class = I2C_CLASS_DDC
;
652 strncpy(intel_dp
->adapter
.name
, name
, sizeof(intel_dp
->adapter
.name
) - 1);
653 intel_dp
->adapter
.name
[sizeof(intel_dp
->adapter
.name
) - 1] = '\0';
654 intel_dp
->adapter
.algo_data
= &intel_dp
->algo
;
655 intel_dp
->adapter
.dev
.parent
= &intel_connector
->base
.kdev
;
657 ironlake_edp_panel_vdd_on(intel_dp
);
658 ret
= i2c_dp_aux_add_bus(&intel_dp
->adapter
);
659 ironlake_edp_panel_vdd_off(intel_dp
, false);
664 intel_dp_compute_config(struct intel_encoder
*encoder
,
665 struct intel_crtc_config
*pipe_config
)
667 struct drm_device
*dev
= encoder
->base
.dev
;
668 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
669 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
670 struct drm_display_mode
*mode
= &pipe_config
->requested_mode
;
671 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
672 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
673 int lane_count
, clock
;
674 int max_lane_count
= drm_dp_max_lane_count(intel_dp
->dpcd
);
675 int max_clock
= intel_dp_max_link_bw(intel_dp
) == DP_LINK_BW_2_7
? 1 : 0;
677 static int bws
[2] = { DP_LINK_BW_1_62
, DP_LINK_BW_2_7
};
678 int target_clock
, link_avail
, link_clock
;
680 if (HAS_PCH_SPLIT(dev
) && !HAS_DDI(dev
) && !is_cpu_edp(intel_dp
))
681 pipe_config
->has_pch_encoder
= true;
683 pipe_config
->has_dp_encoder
= true;
685 if (is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
686 intel_fixed_panel_mode(intel_connector
->panel
.fixed_mode
,
688 intel_pch_panel_fitting(dev
,
689 intel_connector
->panel
.fitting_mode
,
690 mode
, adjusted_mode
);
692 /* We need to take the panel's fixed mode into account. */
693 target_clock
= adjusted_mode
->clock
;
695 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
698 DRM_DEBUG_KMS("DP link computation with max lane count %i "
699 "max bw %02x pixel clock %iKHz\n",
700 max_lane_count
, bws
[max_clock
], adjusted_mode
->clock
);
702 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
704 bpp
= min_t(int, 8*3, pipe_config
->pipe_bpp
);
705 for (; bpp
>= 6*3; bpp
-= 2*3) {
706 mode_rate
= intel_dp_link_required(target_clock
, bpp
);
708 for (clock
= 0; clock
<= max_clock
; clock
++) {
709 for (lane_count
= 1; lane_count
<= max_lane_count
; lane_count
<<= 1) {
710 link_clock
= drm_dp_bw_code_to_link_rate(bws
[clock
]);
711 link_avail
= intel_dp_max_data_rate(link_clock
,
714 if (mode_rate
<= link_avail
) {
724 if (intel_dp
->color_range_auto
) {
727 * CEA-861-E - 5.1 Default Encoding Parameters
728 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
730 if (bpp
!= 18 && drm_match_cea_mode(adjusted_mode
) > 1)
731 intel_dp
->color_range
= DP_COLOR_RANGE_16_235
;
733 intel_dp
->color_range
= 0;
736 if (intel_dp
->color_range
)
737 pipe_config
->limited_color_range
= true;
739 intel_dp
->link_bw
= bws
[clock
];
740 intel_dp
->lane_count
= lane_count
;
741 adjusted_mode
->clock
= drm_dp_bw_code_to_link_rate(intel_dp
->link_bw
);
742 pipe_config
->pixel_target_clock
= target_clock
;
744 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
745 intel_dp
->link_bw
, intel_dp
->lane_count
,
746 adjusted_mode
->clock
, bpp
);
747 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
748 mode_rate
, link_avail
);
750 intel_link_compute_m_n(bpp
, lane_count
,
751 target_clock
, adjusted_mode
->clock
,
752 &pipe_config
->dp_m_n
);
755 * XXX: We have a strange regression where using the vbt edp bpp value
756 * for the link bw computation results in black screens, the panel only
757 * works when we do the computation at the usual 24bpp (but still
758 * requires us to use 18bpp). Until that's fully debugged, stay
759 * bug-for-bug compatible with the old code.
761 if (is_edp(intel_dp
) && dev_priv
->edp
.bpp
) {
762 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n",
763 bpp
, dev_priv
->edp
.bpp
);
764 bpp
= min_t(int, bpp
, dev_priv
->edp
.bpp
);
766 pipe_config
->pipe_bpp
= bpp
;
771 void intel_dp_init_link_config(struct intel_dp
*intel_dp
)
773 memset(intel_dp
->link_configuration
, 0, DP_LINK_CONFIGURATION_SIZE
);
774 intel_dp
->link_configuration
[0] = intel_dp
->link_bw
;
775 intel_dp
->link_configuration
[1] = intel_dp
->lane_count
;
776 intel_dp
->link_configuration
[8] = DP_SET_ANSI_8B10B
;
778 * Check for DPCD version > 1.1 and enhanced framing support
780 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
781 (intel_dp
->dpcd
[DP_MAX_LANE_COUNT
] & DP_ENHANCED_FRAME_CAP
)) {
782 intel_dp
->link_configuration
[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN
;
786 static void ironlake_set_pll_edp(struct drm_crtc
*crtc
, int clock
)
788 struct drm_device
*dev
= crtc
->dev
;
789 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
792 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock
);
793 dpa_ctl
= I915_READ(DP_A
);
794 dpa_ctl
&= ~DP_PLL_FREQ_MASK
;
796 if (clock
< 200000) {
797 /* For a long time we've carried around a ILK-DevA w/a for the
798 * 160MHz clock. If we're really unlucky, it's still required.
800 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
801 dpa_ctl
|= DP_PLL_FREQ_160MHZ
;
803 dpa_ctl
|= DP_PLL_FREQ_270MHZ
;
806 I915_WRITE(DP_A
, dpa_ctl
);
813 intel_dp_mode_set(struct drm_encoder
*encoder
, struct drm_display_mode
*mode
,
814 struct drm_display_mode
*adjusted_mode
)
816 struct drm_device
*dev
= encoder
->dev
;
817 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
818 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
819 struct drm_crtc
*crtc
= encoder
->crtc
;
820 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
823 * There are four kinds of DP registers:
830 * IBX PCH and CPU are the same for almost everything,
831 * except that the CPU DP PLL is configured in this
834 * CPT PCH is quite different, having many bits moved
835 * to the TRANS_DP_CTL register instead. That
836 * configuration happens (oddly) in ironlake_pch_enable
839 /* Preserve the BIOS-computed detected bit. This is
840 * supposed to be read-only.
842 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
844 /* Handle DP bits in common between all three register formats */
845 intel_dp
->DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
847 switch (intel_dp
->lane_count
) {
849 intel_dp
->DP
|= DP_PORT_WIDTH_1
;
852 intel_dp
->DP
|= DP_PORT_WIDTH_2
;
855 intel_dp
->DP
|= DP_PORT_WIDTH_4
;
858 if (intel_dp
->has_audio
) {
859 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
860 pipe_name(intel_crtc
->pipe
));
861 intel_dp
->DP
|= DP_AUDIO_OUTPUT_ENABLE
;
862 intel_write_eld(encoder
, adjusted_mode
);
865 intel_dp_init_link_config(intel_dp
);
867 /* Split out the IBX/CPU vs CPT settings */
869 if (is_cpu_edp(intel_dp
) && IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) {
870 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
871 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
872 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
873 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
874 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
876 if (intel_dp
->link_configuration
[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN
)
877 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
879 intel_dp
->DP
|= intel_crtc
->pipe
<< 29;
881 /* don't miss out required setting for eDP */
882 if (adjusted_mode
->clock
< 200000)
883 intel_dp
->DP
|= DP_PLL_FREQ_160MHZ
;
885 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
886 } else if (!HAS_PCH_CPT(dev
) || is_cpu_edp(intel_dp
)) {
887 if (!HAS_PCH_SPLIT(dev
) && !IS_VALLEYVIEW(dev
))
888 intel_dp
->DP
|= intel_dp
->color_range
;
890 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
891 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
892 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
893 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
894 intel_dp
->DP
|= DP_LINK_TRAIN_OFF
;
896 if (intel_dp
->link_configuration
[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN
)
897 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
899 if (intel_crtc
->pipe
== 1)
900 intel_dp
->DP
|= DP_PIPEB_SELECT
;
902 if (is_cpu_edp(intel_dp
) && !IS_VALLEYVIEW(dev
)) {
903 /* don't miss out required setting for eDP */
904 if (adjusted_mode
->clock
< 200000)
905 intel_dp
->DP
|= DP_PLL_FREQ_160MHZ
;
907 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
910 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
913 if (is_cpu_edp(intel_dp
) && !IS_VALLEYVIEW(dev
))
914 ironlake_set_pll_edp(crtc
, adjusted_mode
->clock
);
917 #define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
918 #define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
920 #define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
921 #define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
923 #define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
924 #define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
926 static void ironlake_wait_panel_status(struct intel_dp
*intel_dp
,
930 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
931 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
932 u32 pp_stat_reg
, pp_ctrl_reg
;
934 pp_stat_reg
= IS_VALLEYVIEW(dev
) ? PIPEA_PP_STATUS
: PCH_PP_STATUS
;
935 pp_ctrl_reg
= IS_VALLEYVIEW(dev
) ? PIPEA_PP_CONTROL
: PCH_PP_CONTROL
;
937 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
939 I915_READ(pp_stat_reg
),
940 I915_READ(pp_ctrl_reg
));
942 if (_wait_for((I915_READ(pp_stat_reg
) & mask
) == value
, 5000, 10)) {
943 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
944 I915_READ(pp_stat_reg
),
945 I915_READ(pp_ctrl_reg
));
949 static void ironlake_wait_panel_on(struct intel_dp
*intel_dp
)
951 DRM_DEBUG_KMS("Wait for panel power on\n");
952 ironlake_wait_panel_status(intel_dp
, IDLE_ON_MASK
, IDLE_ON_VALUE
);
955 static void ironlake_wait_panel_off(struct intel_dp
*intel_dp
)
957 DRM_DEBUG_KMS("Wait for panel power off time\n");
958 ironlake_wait_panel_status(intel_dp
, IDLE_OFF_MASK
, IDLE_OFF_VALUE
);
961 static void ironlake_wait_panel_power_cycle(struct intel_dp
*intel_dp
)
963 DRM_DEBUG_KMS("Wait for panel power cycle\n");
964 ironlake_wait_panel_status(intel_dp
, IDLE_CYCLE_MASK
, IDLE_CYCLE_VALUE
);
968 /* Read the current pp_control value, unlocking the register if it
972 static u32
ironlake_get_pp_control(struct intel_dp
*intel_dp
)
974 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
975 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
979 pp_ctrl_reg
= IS_VALLEYVIEW(dev
) ? PIPEA_PP_CONTROL
: PCH_PP_CONTROL
;
980 control
= I915_READ(pp_ctrl_reg
);
982 control
&= ~PANEL_UNLOCK_MASK
;
983 control
|= PANEL_UNLOCK_REGS
;
987 void ironlake_edp_panel_vdd_on(struct intel_dp
*intel_dp
)
989 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
990 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
992 u32 pp_stat_reg
, pp_ctrl_reg
;
994 if (!is_edp(intel_dp
))
996 DRM_DEBUG_KMS("Turn eDP VDD on\n");
998 WARN(intel_dp
->want_panel_vdd
,
999 "eDP VDD already requested on\n");
1001 intel_dp
->want_panel_vdd
= true;
1003 if (ironlake_edp_have_panel_vdd(intel_dp
)) {
1004 DRM_DEBUG_KMS("eDP VDD already on\n");
1008 if (!ironlake_edp_have_panel_power(intel_dp
))
1009 ironlake_wait_panel_power_cycle(intel_dp
);
1011 pp
= ironlake_get_pp_control(intel_dp
);
1012 pp
|= EDP_FORCE_VDD
;
1014 pp_stat_reg
= IS_VALLEYVIEW(dev
) ? PIPEA_PP_STATUS
: PCH_PP_STATUS
;
1015 pp_ctrl_reg
= IS_VALLEYVIEW(dev
) ? PIPEA_PP_CONTROL
: PCH_PP_CONTROL
;
1017 I915_WRITE(pp_ctrl_reg
, pp
);
1018 POSTING_READ(pp_ctrl_reg
);
1019 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1020 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1022 * If the panel wasn't on, delay before accessing aux channel
1024 if (!ironlake_edp_have_panel_power(intel_dp
)) {
1025 DRM_DEBUG_KMS("eDP was not running\n");
1026 msleep(intel_dp
->panel_power_up_delay
);
1030 static void ironlake_panel_vdd_off_sync(struct intel_dp
*intel_dp
)
1032 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1033 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1035 u32 pp_stat_reg
, pp_ctrl_reg
;
1037 WARN_ON(!mutex_is_locked(&dev
->mode_config
.mutex
));
1039 if (!intel_dp
->want_panel_vdd
&& ironlake_edp_have_panel_vdd(intel_dp
)) {
1040 pp
= ironlake_get_pp_control(intel_dp
);
1041 pp
&= ~EDP_FORCE_VDD
;
1043 pp_stat_reg
= IS_VALLEYVIEW(dev
) ? PIPEA_PP_STATUS
: PCH_PP_STATUS
;
1044 pp_ctrl_reg
= IS_VALLEYVIEW(dev
) ? PIPEA_PP_CONTROL
: PCH_PP_CONTROL
;
1046 I915_WRITE(pp_ctrl_reg
, pp
);
1047 POSTING_READ(pp_ctrl_reg
);
1049 /* Make sure sequencer is idle before allowing subsequent activity */
1050 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1051 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1052 msleep(intel_dp
->panel_power_down_delay
);
1056 static void ironlake_panel_vdd_work(struct work_struct
*__work
)
1058 struct intel_dp
*intel_dp
= container_of(to_delayed_work(__work
),
1059 struct intel_dp
, panel_vdd_work
);
1060 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1062 mutex_lock(&dev
->mode_config
.mutex
);
1063 ironlake_panel_vdd_off_sync(intel_dp
);
1064 mutex_unlock(&dev
->mode_config
.mutex
);
1067 void ironlake_edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
)
1069 if (!is_edp(intel_dp
))
1072 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp
->want_panel_vdd
);
1073 WARN(!intel_dp
->want_panel_vdd
, "eDP VDD not forced on");
1075 intel_dp
->want_panel_vdd
= false;
1078 ironlake_panel_vdd_off_sync(intel_dp
);
1081 * Queue the timer to fire a long
1082 * time from now (relative to the power down delay)
1083 * to keep the panel power up across a sequence of operations
1085 schedule_delayed_work(&intel_dp
->panel_vdd_work
,
1086 msecs_to_jiffies(intel_dp
->panel_power_cycle_delay
* 5));
1090 void ironlake_edp_panel_on(struct intel_dp
*intel_dp
)
1092 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1093 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1097 if (!is_edp(intel_dp
))
1100 DRM_DEBUG_KMS("Turn eDP power on\n");
1102 if (ironlake_edp_have_panel_power(intel_dp
)) {
1103 DRM_DEBUG_KMS("eDP power already on\n");
1107 ironlake_wait_panel_power_cycle(intel_dp
);
1109 pp
= ironlake_get_pp_control(intel_dp
);
1111 /* ILK workaround: disable reset around power sequence */
1112 pp
&= ~PANEL_POWER_RESET
;
1113 I915_WRITE(PCH_PP_CONTROL
, pp
);
1114 POSTING_READ(PCH_PP_CONTROL
);
1117 pp
|= POWER_TARGET_ON
;
1119 pp
|= PANEL_POWER_RESET
;
1121 pp_ctrl_reg
= IS_VALLEYVIEW(dev
) ? PIPEA_PP_CONTROL
: PCH_PP_CONTROL
;
1123 I915_WRITE(pp_ctrl_reg
, pp
);
1124 POSTING_READ(pp_ctrl_reg
);
1126 ironlake_wait_panel_on(intel_dp
);
1129 pp
|= PANEL_POWER_RESET
; /* restore panel reset bit */
1130 I915_WRITE(PCH_PP_CONTROL
, pp
);
1131 POSTING_READ(PCH_PP_CONTROL
);
1135 void ironlake_edp_panel_off(struct intel_dp
*intel_dp
)
1137 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1138 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1142 if (!is_edp(intel_dp
))
1145 DRM_DEBUG_KMS("Turn eDP power off\n");
1147 WARN(!intel_dp
->want_panel_vdd
, "Need VDD to turn off panel\n");
1149 pp
= ironlake_get_pp_control(intel_dp
);
1150 /* We need to switch off panel power _and_ force vdd, for otherwise some
1151 * panels get very unhappy and cease to work. */
1152 pp
&= ~(POWER_TARGET_ON
| EDP_FORCE_VDD
| PANEL_POWER_RESET
| EDP_BLC_ENABLE
);
1154 pp_ctrl_reg
= IS_VALLEYVIEW(dev
) ? PIPEA_PP_CONTROL
: PCH_PP_CONTROL
;
1156 I915_WRITE(pp_ctrl_reg
, pp
);
1157 POSTING_READ(pp_ctrl_reg
);
1159 intel_dp
->want_panel_vdd
= false;
1161 ironlake_wait_panel_off(intel_dp
);
1164 void ironlake_edp_backlight_on(struct intel_dp
*intel_dp
)
1166 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1167 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
1168 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1169 int pipe
= to_intel_crtc(intel_dig_port
->base
.base
.crtc
)->pipe
;
1173 if (!is_edp(intel_dp
))
1176 DRM_DEBUG_KMS("\n");
1178 * If we enable the backlight right away following a panel power
1179 * on, we may see slight flicker as the panel syncs with the eDP
1180 * link. So delay a bit to make sure the image is solid before
1181 * allowing it to appear.
1183 msleep(intel_dp
->backlight_on_delay
);
1184 pp
= ironlake_get_pp_control(intel_dp
);
1185 pp
|= EDP_BLC_ENABLE
;
1187 pp_ctrl_reg
= IS_VALLEYVIEW(dev
) ? PIPEA_PP_CONTROL
: PCH_PP_CONTROL
;
1189 I915_WRITE(pp_ctrl_reg
, pp
);
1190 POSTING_READ(pp_ctrl_reg
);
1192 intel_panel_enable_backlight(dev
, pipe
);
1195 void ironlake_edp_backlight_off(struct intel_dp
*intel_dp
)
1197 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1198 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1202 if (!is_edp(intel_dp
))
1205 intel_panel_disable_backlight(dev
);
1207 DRM_DEBUG_KMS("\n");
1208 pp
= ironlake_get_pp_control(intel_dp
);
1209 pp
&= ~EDP_BLC_ENABLE
;
1211 pp_ctrl_reg
= IS_VALLEYVIEW(dev
) ? PIPEA_PP_CONTROL
: PCH_PP_CONTROL
;
1213 I915_WRITE(pp_ctrl_reg
, pp
);
1214 POSTING_READ(pp_ctrl_reg
);
1215 msleep(intel_dp
->backlight_off_delay
);
1218 static void ironlake_edp_pll_on(struct intel_dp
*intel_dp
)
1220 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1221 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
1222 struct drm_device
*dev
= crtc
->dev
;
1223 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1226 assert_pipe_disabled(dev_priv
,
1227 to_intel_crtc(crtc
)->pipe
);
1229 DRM_DEBUG_KMS("\n");
1230 dpa_ctl
= I915_READ(DP_A
);
1231 WARN(dpa_ctl
& DP_PLL_ENABLE
, "dp pll on, should be off\n");
1232 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
1234 /* We don't adjust intel_dp->DP while tearing down the link, to
1235 * facilitate link retraining (e.g. after hotplug). Hence clear all
1236 * enable bits here to ensure that we don't enable too much. */
1237 intel_dp
->DP
&= ~(DP_PORT_EN
| DP_AUDIO_OUTPUT_ENABLE
);
1238 intel_dp
->DP
|= DP_PLL_ENABLE
;
1239 I915_WRITE(DP_A
, intel_dp
->DP
);
1244 static void ironlake_edp_pll_off(struct intel_dp
*intel_dp
)
1246 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1247 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
1248 struct drm_device
*dev
= crtc
->dev
;
1249 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1252 assert_pipe_disabled(dev_priv
,
1253 to_intel_crtc(crtc
)->pipe
);
1255 dpa_ctl
= I915_READ(DP_A
);
1256 WARN((dpa_ctl
& DP_PLL_ENABLE
) == 0,
1257 "dp pll off, should be on\n");
1258 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
1260 /* We can't rely on the value tracked for the DP register in
1261 * intel_dp->DP because link_down must not change that (otherwise link
1262 * re-training will fail. */
1263 dpa_ctl
&= ~DP_PLL_ENABLE
;
1264 I915_WRITE(DP_A
, dpa_ctl
);
1269 /* If the sink supports it, try to set the power state appropriately */
1270 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
)
1274 /* Should have a valid DPCD by this point */
1275 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x11)
1278 if (mode
!= DRM_MODE_DPMS_ON
) {
1279 ret
= intel_dp_aux_native_write_1(intel_dp
, DP_SET_POWER
,
1282 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1285 * When turning on, we need to retry for 1ms to give the sink
1288 for (i
= 0; i
< 3; i
++) {
1289 ret
= intel_dp_aux_native_write_1(intel_dp
,
1299 static bool intel_dp_get_hw_state(struct intel_encoder
*encoder
,
1302 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1303 struct drm_device
*dev
= encoder
->base
.dev
;
1304 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1305 u32 tmp
= I915_READ(intel_dp
->output_reg
);
1307 if (!(tmp
& DP_PORT_EN
))
1310 if (is_cpu_edp(intel_dp
) && IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) {
1311 *pipe
= PORT_TO_PIPE_CPT(tmp
);
1312 } else if (!HAS_PCH_CPT(dev
) || is_cpu_edp(intel_dp
)) {
1313 *pipe
= PORT_TO_PIPE(tmp
);
1319 switch (intel_dp
->output_reg
) {
1321 trans_sel
= TRANS_DP_PORT_SEL_B
;
1324 trans_sel
= TRANS_DP_PORT_SEL_C
;
1327 trans_sel
= TRANS_DP_PORT_SEL_D
;
1334 trans_dp
= I915_READ(TRANS_DP_CTL(i
));
1335 if ((trans_dp
& TRANS_DP_PORT_SEL_MASK
) == trans_sel
) {
1341 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1342 intel_dp
->output_reg
);
1348 static void intel_disable_dp(struct intel_encoder
*encoder
)
1350 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1352 /* Make sure the panel is off before trying to change the mode. But also
1353 * ensure that we have vdd while we switch off the panel. */
1354 ironlake_edp_panel_vdd_on(intel_dp
);
1355 ironlake_edp_backlight_off(intel_dp
);
1356 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
1357 ironlake_edp_panel_off(intel_dp
);
1359 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1360 if (!is_cpu_edp(intel_dp
))
1361 intel_dp_link_down(intel_dp
);
1364 static void intel_post_disable_dp(struct intel_encoder
*encoder
)
1366 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1367 struct drm_device
*dev
= encoder
->base
.dev
;
1369 if (is_cpu_edp(intel_dp
)) {
1370 intel_dp_link_down(intel_dp
);
1371 if (!IS_VALLEYVIEW(dev
))
1372 ironlake_edp_pll_off(intel_dp
);
1376 static void intel_enable_dp(struct intel_encoder
*encoder
)
1378 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1379 struct drm_device
*dev
= encoder
->base
.dev
;
1380 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1381 uint32_t dp_reg
= I915_READ(intel_dp
->output_reg
);
1383 if (WARN_ON(dp_reg
& DP_PORT_EN
))
1386 ironlake_edp_panel_vdd_on(intel_dp
);
1387 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
1388 intel_dp_start_link_train(intel_dp
);
1389 ironlake_edp_panel_on(intel_dp
);
1390 ironlake_edp_panel_vdd_off(intel_dp
, true);
1391 intel_dp_complete_link_train(intel_dp
);
1392 ironlake_edp_backlight_on(intel_dp
);
1395 static void intel_pre_enable_dp(struct intel_encoder
*encoder
)
1397 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1398 struct drm_device
*dev
= encoder
->base
.dev
;
1400 if (is_cpu_edp(intel_dp
) && !IS_VALLEYVIEW(dev
))
1401 ironlake_edp_pll_on(intel_dp
);
1405 * Native read with retry for link status and receiver capability reads for
1406 * cases where the sink may still be asleep.
1409 intel_dp_aux_native_read_retry(struct intel_dp
*intel_dp
, uint16_t address
,
1410 uint8_t *recv
, int recv_bytes
)
1415 * Sinks are *supposed* to come up within 1ms from an off state,
1416 * but we're also supposed to retry 3 times per the spec.
1418 for (i
= 0; i
< 3; i
++) {
1419 ret
= intel_dp_aux_native_read(intel_dp
, address
, recv
,
1421 if (ret
== recv_bytes
)
1430 * Fetch AUX CH registers 0x202 - 0x207 which contain
1431 * link status information
1434 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
1436 return intel_dp_aux_native_read_retry(intel_dp
,
1439 DP_LINK_STATUS_SIZE
);
1443 static char *voltage_names
[] = {
1444 "0.4V", "0.6V", "0.8V", "1.2V"
1446 static char *pre_emph_names
[] = {
1447 "0dB", "3.5dB", "6dB", "9.5dB"
1449 static char *link_train_names
[] = {
1450 "pattern 1", "pattern 2", "idle", "off"
1455 * These are source-specific values; current Intel hardware supports
1456 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1460 intel_dp_voltage_max(struct intel_dp
*intel_dp
)
1462 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1464 if (IS_GEN7(dev
) && is_cpu_edp(intel_dp
))
1465 return DP_TRAIN_VOLTAGE_SWING_800
;
1466 else if (HAS_PCH_CPT(dev
) && !is_cpu_edp(intel_dp
))
1467 return DP_TRAIN_VOLTAGE_SWING_1200
;
1469 return DP_TRAIN_VOLTAGE_SWING_800
;
1473 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, uint8_t voltage_swing
)
1475 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1478 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1479 case DP_TRAIN_VOLTAGE_SWING_400
:
1480 return DP_TRAIN_PRE_EMPHASIS_9_5
;
1481 case DP_TRAIN_VOLTAGE_SWING_600
:
1482 return DP_TRAIN_PRE_EMPHASIS_6
;
1483 case DP_TRAIN_VOLTAGE_SWING_800
:
1484 return DP_TRAIN_PRE_EMPHASIS_3_5
;
1485 case DP_TRAIN_VOLTAGE_SWING_1200
:
1487 return DP_TRAIN_PRE_EMPHASIS_0
;
1489 } else if (IS_GEN7(dev
) && is_cpu_edp(intel_dp
) && !IS_VALLEYVIEW(dev
)) {
1490 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1491 case DP_TRAIN_VOLTAGE_SWING_400
:
1492 return DP_TRAIN_PRE_EMPHASIS_6
;
1493 case DP_TRAIN_VOLTAGE_SWING_600
:
1494 case DP_TRAIN_VOLTAGE_SWING_800
:
1495 return DP_TRAIN_PRE_EMPHASIS_3_5
;
1497 return DP_TRAIN_PRE_EMPHASIS_0
;
1500 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1501 case DP_TRAIN_VOLTAGE_SWING_400
:
1502 return DP_TRAIN_PRE_EMPHASIS_6
;
1503 case DP_TRAIN_VOLTAGE_SWING_600
:
1504 return DP_TRAIN_PRE_EMPHASIS_6
;
1505 case DP_TRAIN_VOLTAGE_SWING_800
:
1506 return DP_TRAIN_PRE_EMPHASIS_3_5
;
1507 case DP_TRAIN_VOLTAGE_SWING_1200
:
1509 return DP_TRAIN_PRE_EMPHASIS_0
;
1515 intel_get_adjust_train(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
1520 uint8_t voltage_max
;
1521 uint8_t preemph_max
;
1523 for (lane
= 0; lane
< intel_dp
->lane_count
; lane
++) {
1524 uint8_t this_v
= drm_dp_get_adjust_request_voltage(link_status
, lane
);
1525 uint8_t this_p
= drm_dp_get_adjust_request_pre_emphasis(link_status
, lane
);
1533 voltage_max
= intel_dp_voltage_max(intel_dp
);
1534 if (v
>= voltage_max
)
1535 v
= voltage_max
| DP_TRAIN_MAX_SWING_REACHED
;
1537 preemph_max
= intel_dp_pre_emphasis_max(intel_dp
, v
);
1538 if (p
>= preemph_max
)
1539 p
= preemph_max
| DP_TRAIN_MAX_PRE_EMPHASIS_REACHED
;
1541 for (lane
= 0; lane
< 4; lane
++)
1542 intel_dp
->train_set
[lane
] = v
| p
;
1546 intel_gen4_signal_levels(uint8_t train_set
)
1548 uint32_t signal_levels
= 0;
1550 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1551 case DP_TRAIN_VOLTAGE_SWING_400
:
1553 signal_levels
|= DP_VOLTAGE_0_4
;
1555 case DP_TRAIN_VOLTAGE_SWING_600
:
1556 signal_levels
|= DP_VOLTAGE_0_6
;
1558 case DP_TRAIN_VOLTAGE_SWING_800
:
1559 signal_levels
|= DP_VOLTAGE_0_8
;
1561 case DP_TRAIN_VOLTAGE_SWING_1200
:
1562 signal_levels
|= DP_VOLTAGE_1_2
;
1565 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
1566 case DP_TRAIN_PRE_EMPHASIS_0
:
1568 signal_levels
|= DP_PRE_EMPHASIS_0
;
1570 case DP_TRAIN_PRE_EMPHASIS_3_5
:
1571 signal_levels
|= DP_PRE_EMPHASIS_3_5
;
1573 case DP_TRAIN_PRE_EMPHASIS_6
:
1574 signal_levels
|= DP_PRE_EMPHASIS_6
;
1576 case DP_TRAIN_PRE_EMPHASIS_9_5
:
1577 signal_levels
|= DP_PRE_EMPHASIS_9_5
;
1580 return signal_levels
;
1583 /* Gen6's DP voltage swing and pre-emphasis control */
1585 intel_gen6_edp_signal_levels(uint8_t train_set
)
1587 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
1588 DP_TRAIN_PRE_EMPHASIS_MASK
);
1589 switch (signal_levels
) {
1590 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
1591 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
1592 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
1593 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1594 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B
;
1595 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
1596 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_6
:
1597 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B
;
1598 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1599 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1600 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B
;
1601 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
1602 case DP_TRAIN_VOLTAGE_SWING_1200
| DP_TRAIN_PRE_EMPHASIS_0
:
1603 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B
;
1605 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1606 "0x%x\n", signal_levels
);
1607 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
1611 /* Gen7's DP voltage swing and pre-emphasis control */
1613 intel_gen7_edp_signal_levels(uint8_t train_set
)
1615 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
1616 DP_TRAIN_PRE_EMPHASIS_MASK
);
1617 switch (signal_levels
) {
1618 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
1619 return EDP_LINK_TRAIN_400MV_0DB_IVB
;
1620 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1621 return EDP_LINK_TRAIN_400MV_3_5DB_IVB
;
1622 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
1623 return EDP_LINK_TRAIN_400MV_6DB_IVB
;
1625 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
1626 return EDP_LINK_TRAIN_600MV_0DB_IVB
;
1627 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1628 return EDP_LINK_TRAIN_600MV_3_5DB_IVB
;
1630 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
1631 return EDP_LINK_TRAIN_800MV_0DB_IVB
;
1632 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1633 return EDP_LINK_TRAIN_800MV_3_5DB_IVB
;
1636 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1637 "0x%x\n", signal_levels
);
1638 return EDP_LINK_TRAIN_500MV_0DB_IVB
;
1642 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
1644 intel_hsw_signal_levels(uint8_t train_set
)
1646 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
1647 DP_TRAIN_PRE_EMPHASIS_MASK
);
1648 switch (signal_levels
) {
1649 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
1650 return DDI_BUF_EMP_400MV_0DB_HSW
;
1651 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1652 return DDI_BUF_EMP_400MV_3_5DB_HSW
;
1653 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
1654 return DDI_BUF_EMP_400MV_6DB_HSW
;
1655 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_9_5
:
1656 return DDI_BUF_EMP_400MV_9_5DB_HSW
;
1658 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
1659 return DDI_BUF_EMP_600MV_0DB_HSW
;
1660 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1661 return DDI_BUF_EMP_600MV_3_5DB_HSW
;
1662 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_6
:
1663 return DDI_BUF_EMP_600MV_6DB_HSW
;
1665 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
1666 return DDI_BUF_EMP_800MV_0DB_HSW
;
1667 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1668 return DDI_BUF_EMP_800MV_3_5DB_HSW
;
1670 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1671 "0x%x\n", signal_levels
);
1672 return DDI_BUF_EMP_400MV_0DB_HSW
;
1676 /* Properly updates "DP" with the correct signal levels. */
1678 intel_dp_set_signal_levels(struct intel_dp
*intel_dp
, uint32_t *DP
)
1680 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1681 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
1682 uint32_t signal_levels
, mask
;
1683 uint8_t train_set
= intel_dp
->train_set
[0];
1686 signal_levels
= intel_hsw_signal_levels(train_set
);
1687 mask
= DDI_BUF_EMP_MASK
;
1688 } else if (IS_GEN7(dev
) && is_cpu_edp(intel_dp
) && !IS_VALLEYVIEW(dev
)) {
1689 signal_levels
= intel_gen7_edp_signal_levels(train_set
);
1690 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
;
1691 } else if (IS_GEN6(dev
) && is_cpu_edp(intel_dp
)) {
1692 signal_levels
= intel_gen6_edp_signal_levels(train_set
);
1693 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
;
1695 signal_levels
= intel_gen4_signal_levels(train_set
);
1696 mask
= DP_VOLTAGE_MASK
| DP_PRE_EMPHASIS_MASK
;
1699 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels
);
1701 *DP
= (*DP
& ~mask
) | signal_levels
;
1705 intel_dp_set_link_train(struct intel_dp
*intel_dp
,
1706 uint32_t dp_reg_value
,
1707 uint8_t dp_train_pat
)
1709 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1710 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
1711 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1712 enum port port
= intel_dig_port
->port
;
1717 temp
= I915_READ(DP_TP_CTL(port
));
1719 if (dp_train_pat
& DP_LINK_SCRAMBLING_DISABLE
)
1720 temp
|= DP_TP_CTL_SCRAMBLE_DISABLE
;
1722 temp
&= ~DP_TP_CTL_SCRAMBLE_DISABLE
;
1724 temp
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
1725 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
1726 case DP_TRAINING_PATTERN_DISABLE
:
1728 if (port
!= PORT_A
) {
1729 temp
|= DP_TP_CTL_LINK_TRAIN_IDLE
;
1730 I915_WRITE(DP_TP_CTL(port
), temp
);
1732 if (wait_for((I915_READ(DP_TP_STATUS(port
)) &
1733 DP_TP_STATUS_IDLE_DONE
), 1))
1734 DRM_ERROR("Timed out waiting for DP idle patterns\n");
1736 temp
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
1739 temp
|= DP_TP_CTL_LINK_TRAIN_NORMAL
;
1742 case DP_TRAINING_PATTERN_1
:
1743 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
1745 case DP_TRAINING_PATTERN_2
:
1746 temp
|= DP_TP_CTL_LINK_TRAIN_PAT2
;
1748 case DP_TRAINING_PATTERN_3
:
1749 temp
|= DP_TP_CTL_LINK_TRAIN_PAT3
;
1752 I915_WRITE(DP_TP_CTL(port
), temp
);
1754 } else if (HAS_PCH_CPT(dev
) &&
1755 (IS_GEN7(dev
) || !is_cpu_edp(intel_dp
))) {
1756 dp_reg_value
&= ~DP_LINK_TRAIN_MASK_CPT
;
1758 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
1759 case DP_TRAINING_PATTERN_DISABLE
:
1760 dp_reg_value
|= DP_LINK_TRAIN_OFF_CPT
;
1762 case DP_TRAINING_PATTERN_1
:
1763 dp_reg_value
|= DP_LINK_TRAIN_PAT_1_CPT
;
1765 case DP_TRAINING_PATTERN_2
:
1766 dp_reg_value
|= DP_LINK_TRAIN_PAT_2_CPT
;
1768 case DP_TRAINING_PATTERN_3
:
1769 DRM_ERROR("DP training pattern 3 not supported\n");
1770 dp_reg_value
|= DP_LINK_TRAIN_PAT_2_CPT
;
1775 dp_reg_value
&= ~DP_LINK_TRAIN_MASK
;
1777 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
1778 case DP_TRAINING_PATTERN_DISABLE
:
1779 dp_reg_value
|= DP_LINK_TRAIN_OFF
;
1781 case DP_TRAINING_PATTERN_1
:
1782 dp_reg_value
|= DP_LINK_TRAIN_PAT_1
;
1784 case DP_TRAINING_PATTERN_2
:
1785 dp_reg_value
|= DP_LINK_TRAIN_PAT_2
;
1787 case DP_TRAINING_PATTERN_3
:
1788 DRM_ERROR("DP training pattern 3 not supported\n");
1789 dp_reg_value
|= DP_LINK_TRAIN_PAT_2
;
1794 I915_WRITE(intel_dp
->output_reg
, dp_reg_value
);
1795 POSTING_READ(intel_dp
->output_reg
);
1797 intel_dp_aux_native_write_1(intel_dp
,
1798 DP_TRAINING_PATTERN_SET
,
1801 if ((dp_train_pat
& DP_TRAINING_PATTERN_MASK
) !=
1802 DP_TRAINING_PATTERN_DISABLE
) {
1803 ret
= intel_dp_aux_native_write(intel_dp
,
1804 DP_TRAINING_LANE0_SET
,
1805 intel_dp
->train_set
,
1806 intel_dp
->lane_count
);
1807 if (ret
!= intel_dp
->lane_count
)
1814 /* Enable corresponding port and start training pattern 1 */
1816 intel_dp_start_link_train(struct intel_dp
*intel_dp
)
1818 struct drm_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
.base
;
1819 struct drm_device
*dev
= encoder
->dev
;
1822 bool clock_recovery
= false;
1823 int voltage_tries
, loop_tries
;
1824 uint32_t DP
= intel_dp
->DP
;
1827 intel_ddi_prepare_link_retrain(encoder
);
1829 /* Write the link configuration data */
1830 intel_dp_aux_native_write(intel_dp
, DP_LINK_BW_SET
,
1831 intel_dp
->link_configuration
,
1832 DP_LINK_CONFIGURATION_SIZE
);
1836 memset(intel_dp
->train_set
, 0, 4);
1840 clock_recovery
= false;
1842 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1843 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
1845 intel_dp_set_signal_levels(intel_dp
, &DP
);
1847 /* Set training pattern 1 */
1848 if (!intel_dp_set_link_train(intel_dp
, DP
,
1849 DP_TRAINING_PATTERN_1
|
1850 DP_LINK_SCRAMBLING_DISABLE
))
1853 drm_dp_link_train_clock_recovery_delay(intel_dp
->dpcd
);
1854 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
1855 DRM_ERROR("failed to get link status\n");
1859 if (drm_dp_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
1860 DRM_DEBUG_KMS("clock recovery OK\n");
1861 clock_recovery
= true;
1865 /* Check to see if we've tried the max voltage */
1866 for (i
= 0; i
< intel_dp
->lane_count
; i
++)
1867 if ((intel_dp
->train_set
[i
] & DP_TRAIN_MAX_SWING_REACHED
) == 0)
1869 if (i
== intel_dp
->lane_count
) {
1871 if (loop_tries
== 5) {
1872 DRM_DEBUG_KMS("too many full retries, give up\n");
1875 memset(intel_dp
->train_set
, 0, 4);
1880 /* Check to see if we've tried the same voltage 5 times */
1881 if ((intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
) == voltage
) {
1883 if (voltage_tries
== 5) {
1884 DRM_DEBUG_KMS("too many voltage retries, give up\n");
1889 voltage
= intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
;
1891 /* Compute new intel_dp->train_set as requested by target */
1892 intel_get_adjust_train(intel_dp
, link_status
);
1899 intel_dp_complete_link_train(struct intel_dp
*intel_dp
)
1901 bool channel_eq
= false;
1902 int tries
, cr_tries
;
1903 uint32_t DP
= intel_dp
->DP
;
1905 /* channel equalization */
1910 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
1913 DRM_ERROR("failed to train DP, aborting\n");
1914 intel_dp_link_down(intel_dp
);
1918 intel_dp_set_signal_levels(intel_dp
, &DP
);
1920 /* channel eq pattern */
1921 if (!intel_dp_set_link_train(intel_dp
, DP
,
1922 DP_TRAINING_PATTERN_2
|
1923 DP_LINK_SCRAMBLING_DISABLE
))
1926 drm_dp_link_train_channel_eq_delay(intel_dp
->dpcd
);
1927 if (!intel_dp_get_link_status(intel_dp
, link_status
))
1930 /* Make sure clock is still ok */
1931 if (!drm_dp_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
1932 intel_dp_start_link_train(intel_dp
);
1937 if (drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
1942 /* Try 5 times, then try clock recovery if that fails */
1944 intel_dp_link_down(intel_dp
);
1945 intel_dp_start_link_train(intel_dp
);
1951 /* Compute new intel_dp->train_set as requested by target */
1952 intel_get_adjust_train(intel_dp
, link_status
);
1957 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
1959 intel_dp_set_link_train(intel_dp
, DP
, DP_TRAINING_PATTERN_DISABLE
);
1963 intel_dp_link_down(struct intel_dp
*intel_dp
)
1965 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1966 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
1967 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1968 struct intel_crtc
*intel_crtc
=
1969 to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
1970 uint32_t DP
= intel_dp
->DP
;
1973 * DDI code has a strict mode set sequence and we should try to respect
1974 * it, otherwise we might hang the machine in many different ways. So we
1975 * really should be disabling the port only on a complete crtc_disable
1976 * sequence. This function is just called under two conditions on DDI
1978 * - Link train failed while doing crtc_enable, and on this case we
1979 * really should respect the mode set sequence and wait for a
1981 * - Someone turned the monitor off and intel_dp_check_link_status
1982 * called us. We don't need to disable the whole port on this case, so
1983 * when someone turns the monitor on again,
1984 * intel_ddi_prepare_link_retrain will take care of redoing the link
1990 if (WARN_ON((I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
) == 0))
1993 DRM_DEBUG_KMS("\n");
1995 if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || !is_cpu_edp(intel_dp
))) {
1996 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
1997 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE_CPT
);
1999 DP
&= ~DP_LINK_TRAIN_MASK
;
2000 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE
);
2002 POSTING_READ(intel_dp
->output_reg
);
2004 /* We don't really know why we're doing this */
2005 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2007 if (HAS_PCH_IBX(dev
) &&
2008 I915_READ(intel_dp
->output_reg
) & DP_PIPEB_SELECT
) {
2009 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
2011 /* Hardware workaround: leaving our transcoder select
2012 * set to transcoder B while it's off will prevent the
2013 * corresponding HDMI output on transcoder A.
2015 * Combine this with another hardware workaround:
2016 * transcoder select bit can only be cleared while the
2019 DP
&= ~DP_PIPEB_SELECT
;
2020 I915_WRITE(intel_dp
->output_reg
, DP
);
2022 /* Changes to enable or select take place the vblank
2023 * after being written.
2025 if (WARN_ON(crtc
== NULL
)) {
2026 /* We should never try to disable a port without a crtc
2027 * attached. For paranoia keep the code around for a
2029 POSTING_READ(intel_dp
->output_reg
);
2032 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2035 DP
&= ~DP_AUDIO_OUTPUT_ENABLE
;
2036 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
2037 POSTING_READ(intel_dp
->output_reg
);
2038 msleep(intel_dp
->panel_power_down_delay
);
2042 intel_dp_get_dpcd(struct intel_dp
*intel_dp
)
2044 char dpcd_hex_dump
[sizeof(intel_dp
->dpcd
) * 3];
2046 if (intel_dp_aux_native_read_retry(intel_dp
, 0x000, intel_dp
->dpcd
,
2047 sizeof(intel_dp
->dpcd
)) == 0)
2048 return false; /* aux transfer failed */
2050 hex_dump_to_buffer(intel_dp
->dpcd
, sizeof(intel_dp
->dpcd
),
2051 32, 1, dpcd_hex_dump
, sizeof(dpcd_hex_dump
), false);
2052 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump
);
2054 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0)
2055 return false; /* DPCD not present */
2057 if (!(intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
2058 DP_DWN_STRM_PORT_PRESENT
))
2059 return true; /* native DP sink */
2061 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0x10)
2062 return true; /* no per-port downstream info */
2064 if (intel_dp_aux_native_read_retry(intel_dp
, DP_DOWNSTREAM_PORT_0
,
2065 intel_dp
->downstream_ports
,
2066 DP_MAX_DOWNSTREAM_PORTS
) == 0)
2067 return false; /* downstream port status fetch failed */
2073 intel_dp_probe_oui(struct intel_dp
*intel_dp
)
2077 if (!(intel_dp
->dpcd
[DP_DOWN_STREAM_PORT_COUNT
] & DP_OUI_SUPPORT
))
2080 ironlake_edp_panel_vdd_on(intel_dp
);
2082 if (intel_dp_aux_native_read_retry(intel_dp
, DP_SINK_OUI
, buf
, 3))
2083 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2084 buf
[0], buf
[1], buf
[2]);
2086 if (intel_dp_aux_native_read_retry(intel_dp
, DP_BRANCH_OUI
, buf
, 3))
2087 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2088 buf
[0], buf
[1], buf
[2]);
2090 ironlake_edp_panel_vdd_off(intel_dp
, false);
2094 intel_dp_get_sink_irq(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
2098 ret
= intel_dp_aux_native_read_retry(intel_dp
,
2099 DP_DEVICE_SERVICE_IRQ_VECTOR
,
2100 sink_irq_vector
, 1);
2108 intel_dp_handle_test_request(struct intel_dp
*intel_dp
)
2110 /* NAK by default */
2111 intel_dp_aux_native_write_1(intel_dp
, DP_TEST_RESPONSE
, DP_TEST_NAK
);
2115 * According to DP spec
2118 * 2. Configure link according to Receiver Capabilities
2119 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2120 * 4. Check link status on receipt of hot-plug interrupt
2124 intel_dp_check_link_status(struct intel_dp
*intel_dp
)
2126 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
2128 u8 link_status
[DP_LINK_STATUS_SIZE
];
2130 if (!intel_encoder
->connectors_active
)
2133 if (WARN_ON(!intel_encoder
->base
.crtc
))
2136 /* Try to read receiver status if the link appears to be up */
2137 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
2138 intel_dp_link_down(intel_dp
);
2142 /* Now read the DPCD to see if it's actually running */
2143 if (!intel_dp_get_dpcd(intel_dp
)) {
2144 intel_dp_link_down(intel_dp
);
2148 /* Try to read the source of the interrupt */
2149 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
2150 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
)) {
2151 /* Clear interrupt source */
2152 intel_dp_aux_native_write_1(intel_dp
,
2153 DP_DEVICE_SERVICE_IRQ_VECTOR
,
2156 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
2157 intel_dp_handle_test_request(intel_dp
);
2158 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
2159 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2162 if (!drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
2163 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2164 drm_get_encoder_name(&intel_encoder
->base
));
2165 intel_dp_start_link_train(intel_dp
);
2166 intel_dp_complete_link_train(intel_dp
);
2170 /* XXX this is probably wrong for multiple downstream ports */
2171 static enum drm_connector_status
2172 intel_dp_detect_dpcd(struct intel_dp
*intel_dp
)
2174 uint8_t *dpcd
= intel_dp
->dpcd
;
2178 if (!intel_dp_get_dpcd(intel_dp
))
2179 return connector_status_disconnected
;
2181 /* if there's no downstream port, we're done */
2182 if (!(dpcd
[DP_DOWNSTREAMPORT_PRESENT
] & DP_DWN_STRM_PORT_PRESENT
))
2183 return connector_status_connected
;
2185 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2186 hpd
= !!(intel_dp
->downstream_ports
[0] & DP_DS_PORT_HPD
);
2189 if (!intel_dp_aux_native_read_retry(intel_dp
, DP_SINK_COUNT
,
2191 return connector_status_unknown
;
2192 return DP_GET_SINK_COUNT(reg
) ? connector_status_connected
2193 : connector_status_disconnected
;
2196 /* If no HPD, poke DDC gently */
2197 if (drm_probe_ddc(&intel_dp
->adapter
))
2198 return connector_status_connected
;
2200 /* Well we tried, say unknown for unreliable port types */
2201 type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
2202 if (type
== DP_DS_PORT_TYPE_VGA
|| type
== DP_DS_PORT_TYPE_NON_EDID
)
2203 return connector_status_unknown
;
2205 /* Anything else is out of spec, warn and ignore */
2206 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2207 return connector_status_disconnected
;
2210 static enum drm_connector_status
2211 ironlake_dp_detect(struct intel_dp
*intel_dp
)
2213 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2214 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2215 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2216 enum drm_connector_status status
;
2218 /* Can't disconnect eDP, but you can close the lid... */
2219 if (is_edp(intel_dp
)) {
2220 status
= intel_panel_detect(dev
);
2221 if (status
== connector_status_unknown
)
2222 status
= connector_status_connected
;
2226 if (!ibx_digital_port_connected(dev_priv
, intel_dig_port
))
2227 return connector_status_disconnected
;
2229 return intel_dp_detect_dpcd(intel_dp
);
2232 static enum drm_connector_status
2233 g4x_dp_detect(struct intel_dp
*intel_dp
)
2235 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2236 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2237 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2240 /* Can't disconnect eDP, but you can close the lid... */
2241 if (is_edp(intel_dp
)) {
2242 enum drm_connector_status status
;
2244 status
= intel_panel_detect(dev
);
2245 if (status
== connector_status_unknown
)
2246 status
= connector_status_connected
;
2250 switch (intel_dig_port
->port
) {
2252 bit
= PORTB_HOTPLUG_LIVE_STATUS
;
2255 bit
= PORTC_HOTPLUG_LIVE_STATUS
;
2258 bit
= PORTD_HOTPLUG_LIVE_STATUS
;
2261 return connector_status_unknown
;
2264 if ((I915_READ(PORT_HOTPLUG_STAT
) & bit
) == 0)
2265 return connector_status_disconnected
;
2267 return intel_dp_detect_dpcd(intel_dp
);
2270 static struct edid
*
2271 intel_dp_get_edid(struct drm_connector
*connector
, struct i2c_adapter
*adapter
)
2273 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
2275 /* use cached edid if we have one */
2276 if (intel_connector
->edid
) {
2281 if (IS_ERR(intel_connector
->edid
))
2284 size
= (intel_connector
->edid
->extensions
+ 1) * EDID_LENGTH
;
2285 edid
= kmalloc(size
, GFP_KERNEL
);
2289 memcpy(edid
, intel_connector
->edid
, size
);
2293 return drm_get_edid(connector
, adapter
);
2297 intel_dp_get_edid_modes(struct drm_connector
*connector
, struct i2c_adapter
*adapter
)
2299 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
2301 /* use cached edid if we have one */
2302 if (intel_connector
->edid
) {
2304 if (IS_ERR(intel_connector
->edid
))
2307 return intel_connector_update_modes(connector
,
2308 intel_connector
->edid
);
2311 return intel_ddc_get_modes(connector
, adapter
);
2314 static enum drm_connector_status
2315 intel_dp_detect(struct drm_connector
*connector
, bool force
)
2317 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2318 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2319 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
2320 struct drm_device
*dev
= connector
->dev
;
2321 enum drm_connector_status status
;
2322 struct edid
*edid
= NULL
;
2324 intel_dp
->has_audio
= false;
2326 if (HAS_PCH_SPLIT(dev
))
2327 status
= ironlake_dp_detect(intel_dp
);
2329 status
= g4x_dp_detect(intel_dp
);
2331 if (status
!= connector_status_connected
)
2334 intel_dp_probe_oui(intel_dp
);
2336 if (intel_dp
->force_audio
!= HDMI_AUDIO_AUTO
) {
2337 intel_dp
->has_audio
= (intel_dp
->force_audio
== HDMI_AUDIO_ON
);
2339 edid
= intel_dp_get_edid(connector
, &intel_dp
->adapter
);
2341 intel_dp
->has_audio
= drm_detect_monitor_audio(edid
);
2346 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
2347 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
2348 return connector_status_connected
;
2351 static int intel_dp_get_modes(struct drm_connector
*connector
)
2353 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2354 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
2355 struct drm_device
*dev
= connector
->dev
;
2358 /* We should parse the EDID data and find out if it has an audio sink
2361 ret
= intel_dp_get_edid_modes(connector
, &intel_dp
->adapter
);
2365 /* if eDP has no EDID, fall back to fixed mode */
2366 if (is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
2367 struct drm_display_mode
*mode
;
2368 mode
= drm_mode_duplicate(dev
,
2369 intel_connector
->panel
.fixed_mode
);
2371 drm_mode_probed_add(connector
, mode
);
2379 intel_dp_detect_audio(struct drm_connector
*connector
)
2381 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2383 bool has_audio
= false;
2385 edid
= intel_dp_get_edid(connector
, &intel_dp
->adapter
);
2387 has_audio
= drm_detect_monitor_audio(edid
);
2395 intel_dp_set_property(struct drm_connector
*connector
,
2396 struct drm_property
*property
,
2399 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
2400 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
2401 struct intel_encoder
*intel_encoder
= intel_attached_encoder(connector
);
2402 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
2405 ret
= drm_object_property_set_value(&connector
->base
, property
, val
);
2409 if (property
== dev_priv
->force_audio_property
) {
2413 if (i
== intel_dp
->force_audio
)
2416 intel_dp
->force_audio
= i
;
2418 if (i
== HDMI_AUDIO_AUTO
)
2419 has_audio
= intel_dp_detect_audio(connector
);
2421 has_audio
= (i
== HDMI_AUDIO_ON
);
2423 if (has_audio
== intel_dp
->has_audio
)
2426 intel_dp
->has_audio
= has_audio
;
2430 if (property
== dev_priv
->broadcast_rgb_property
) {
2431 bool old_auto
= intel_dp
->color_range_auto
;
2432 uint32_t old_range
= intel_dp
->color_range
;
2435 case INTEL_BROADCAST_RGB_AUTO
:
2436 intel_dp
->color_range_auto
= true;
2438 case INTEL_BROADCAST_RGB_FULL
:
2439 intel_dp
->color_range_auto
= false;
2440 intel_dp
->color_range
= 0;
2442 case INTEL_BROADCAST_RGB_LIMITED
:
2443 intel_dp
->color_range_auto
= false;
2444 intel_dp
->color_range
= DP_COLOR_RANGE_16_235
;
2450 if (old_auto
== intel_dp
->color_range_auto
&&
2451 old_range
== intel_dp
->color_range
)
2457 if (is_edp(intel_dp
) &&
2458 property
== connector
->dev
->mode_config
.scaling_mode_property
) {
2459 if (val
== DRM_MODE_SCALE_NONE
) {
2460 DRM_DEBUG_KMS("no scaling not supported\n");
2464 if (intel_connector
->panel
.fitting_mode
== val
) {
2465 /* the eDP scaling property is not changed */
2468 intel_connector
->panel
.fitting_mode
= val
;
2476 if (intel_encoder
->base
.crtc
)
2477 intel_crtc_restore_mode(intel_encoder
->base
.crtc
);
2483 intel_dp_destroy(struct drm_connector
*connector
)
2485 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2486 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
2488 if (!IS_ERR_OR_NULL(intel_connector
->edid
))
2489 kfree(intel_connector
->edid
);
2491 if (is_edp(intel_dp
))
2492 intel_panel_fini(&intel_connector
->panel
);
2494 drm_sysfs_connector_remove(connector
);
2495 drm_connector_cleanup(connector
);
2499 void intel_dp_encoder_destroy(struct drm_encoder
*encoder
)
2501 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
2502 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
2503 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2505 i2c_del_adapter(&intel_dp
->adapter
);
2506 drm_encoder_cleanup(encoder
);
2507 if (is_edp(intel_dp
)) {
2508 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
2509 mutex_lock(&dev
->mode_config
.mutex
);
2510 ironlake_panel_vdd_off_sync(intel_dp
);
2511 mutex_unlock(&dev
->mode_config
.mutex
);
2513 kfree(intel_dig_port
);
2516 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs
= {
2517 .mode_set
= intel_dp_mode_set
,
2520 static const struct drm_connector_funcs intel_dp_connector_funcs
= {
2521 .dpms
= intel_connector_dpms
,
2522 .detect
= intel_dp_detect
,
2523 .fill_modes
= drm_helper_probe_single_connector_modes
,
2524 .set_property
= intel_dp_set_property
,
2525 .destroy
= intel_dp_destroy
,
2528 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs
= {
2529 .get_modes
= intel_dp_get_modes
,
2530 .mode_valid
= intel_dp_mode_valid
,
2531 .best_encoder
= intel_best_encoder
,
2534 static const struct drm_encoder_funcs intel_dp_enc_funcs
= {
2535 .destroy
= intel_dp_encoder_destroy
,
2539 intel_dp_hot_plug(struct intel_encoder
*intel_encoder
)
2541 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
2543 intel_dp_check_link_status(intel_dp
);
2546 /* Return which DP Port should be selected for Transcoder DP control */
2548 intel_trans_dp_port_sel(struct drm_crtc
*crtc
)
2550 struct drm_device
*dev
= crtc
->dev
;
2551 struct intel_encoder
*intel_encoder
;
2552 struct intel_dp
*intel_dp
;
2554 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
2555 intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
2557 if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
||
2558 intel_encoder
->type
== INTEL_OUTPUT_EDP
)
2559 return intel_dp
->output_reg
;
2565 /* check the VBT to see whether the eDP is on DP-D port */
2566 bool intel_dpd_is_edp(struct drm_device
*dev
)
2568 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2569 struct child_device_config
*p_child
;
2572 if (!dev_priv
->child_dev_num
)
2575 for (i
= 0; i
< dev_priv
->child_dev_num
; i
++) {
2576 p_child
= dev_priv
->child_dev
+ i
;
2578 if (p_child
->dvo_port
== PORT_IDPD
&&
2579 p_child
->device_type
== DEVICE_TYPE_eDP
)
2586 intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
)
2588 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
2590 intel_attach_force_audio_property(connector
);
2591 intel_attach_broadcast_rgb_property(connector
);
2592 intel_dp
->color_range_auto
= true;
2594 if (is_edp(intel_dp
)) {
2595 drm_mode_create_scaling_mode_property(connector
->dev
);
2596 drm_object_attach_property(
2598 connector
->dev
->mode_config
.scaling_mode_property
,
2599 DRM_MODE_SCALE_ASPECT
);
2600 intel_connector
->panel
.fitting_mode
= DRM_MODE_SCALE_ASPECT
;
2605 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
2606 struct intel_dp
*intel_dp
,
2607 struct edp_power_seq
*out
)
2609 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2610 struct edp_power_seq cur
, vbt
, spec
, final
;
2611 u32 pp_on
, pp_off
, pp_div
, pp
;
2612 int pp_control_reg
, pp_on_reg
, pp_off_reg
, pp_div_reg
;
2614 if (HAS_PCH_SPLIT(dev
)) {
2615 pp_control_reg
= PCH_PP_CONTROL
;
2616 pp_on_reg
= PCH_PP_ON_DELAYS
;
2617 pp_off_reg
= PCH_PP_OFF_DELAYS
;
2618 pp_div_reg
= PCH_PP_DIVISOR
;
2620 pp_control_reg
= PIPEA_PP_CONTROL
;
2621 pp_on_reg
= PIPEA_PP_ON_DELAYS
;
2622 pp_off_reg
= PIPEA_PP_OFF_DELAYS
;
2623 pp_div_reg
= PIPEA_PP_DIVISOR
;
2626 /* Workaround: Need to write PP_CONTROL with the unlock key as
2627 * the very first thing. */
2628 pp
= ironlake_get_pp_control(intel_dp
);
2629 I915_WRITE(pp_control_reg
, pp
);
2631 pp_on
= I915_READ(pp_on_reg
);
2632 pp_off
= I915_READ(pp_off_reg
);
2633 pp_div
= I915_READ(pp_div_reg
);
2635 /* Pull timing values out of registers */
2636 cur
.t1_t3
= (pp_on
& PANEL_POWER_UP_DELAY_MASK
) >>
2637 PANEL_POWER_UP_DELAY_SHIFT
;
2639 cur
.t8
= (pp_on
& PANEL_LIGHT_ON_DELAY_MASK
) >>
2640 PANEL_LIGHT_ON_DELAY_SHIFT
;
2642 cur
.t9
= (pp_off
& PANEL_LIGHT_OFF_DELAY_MASK
) >>
2643 PANEL_LIGHT_OFF_DELAY_SHIFT
;
2645 cur
.t10
= (pp_off
& PANEL_POWER_DOWN_DELAY_MASK
) >>
2646 PANEL_POWER_DOWN_DELAY_SHIFT
;
2648 cur
.t11_t12
= ((pp_div
& PANEL_POWER_CYCLE_DELAY_MASK
) >>
2649 PANEL_POWER_CYCLE_DELAY_SHIFT
) * 1000;
2651 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2652 cur
.t1_t3
, cur
.t8
, cur
.t9
, cur
.t10
, cur
.t11_t12
);
2654 vbt
= dev_priv
->edp
.pps
;
2656 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
2657 * our hw here, which are all in 100usec. */
2658 spec
.t1_t3
= 210 * 10;
2659 spec
.t8
= 50 * 10; /* no limit for t8, use t7 instead */
2660 spec
.t9
= 50 * 10; /* no limit for t9, make it symmetric with t8 */
2661 spec
.t10
= 500 * 10;
2662 /* This one is special and actually in units of 100ms, but zero
2663 * based in the hw (so we need to add 100 ms). But the sw vbt
2664 * table multiplies it with 1000 to make it in units of 100usec,
2666 spec
.t11_t12
= (510 + 100) * 10;
2668 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2669 vbt
.t1_t3
, vbt
.t8
, vbt
.t9
, vbt
.t10
, vbt
.t11_t12
);
2671 /* Use the max of the register settings and vbt. If both are
2672 * unset, fall back to the spec limits. */
2673 #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
2675 max(cur.field, vbt.field))
2676 assign_final(t1_t3
);
2680 assign_final(t11_t12
);
2683 #define get_delay(field) (DIV_ROUND_UP(final.field, 10))
2684 intel_dp
->panel_power_up_delay
= get_delay(t1_t3
);
2685 intel_dp
->backlight_on_delay
= get_delay(t8
);
2686 intel_dp
->backlight_off_delay
= get_delay(t9
);
2687 intel_dp
->panel_power_down_delay
= get_delay(t10
);
2688 intel_dp
->panel_power_cycle_delay
= get_delay(t11_t12
);
2691 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2692 intel_dp
->panel_power_up_delay
, intel_dp
->panel_power_down_delay
,
2693 intel_dp
->panel_power_cycle_delay
);
2695 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2696 intel_dp
->backlight_on_delay
, intel_dp
->backlight_off_delay
);
2703 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
2704 struct intel_dp
*intel_dp
,
2705 struct edp_power_seq
*seq
)
2707 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2708 u32 pp_on
, pp_off
, pp_div
, port_sel
= 0;
2709 int div
= HAS_PCH_SPLIT(dev
) ? intel_pch_rawclk(dev
) : intel_hrawclk(dev
);
2710 int pp_on_reg
, pp_off_reg
, pp_div_reg
;
2712 if (HAS_PCH_SPLIT(dev
)) {
2713 pp_on_reg
= PCH_PP_ON_DELAYS
;
2714 pp_off_reg
= PCH_PP_OFF_DELAYS
;
2715 pp_div_reg
= PCH_PP_DIVISOR
;
2717 pp_on_reg
= PIPEA_PP_ON_DELAYS
;
2718 pp_off_reg
= PIPEA_PP_OFF_DELAYS
;
2719 pp_div_reg
= PIPEA_PP_DIVISOR
;
2722 if (IS_VALLEYVIEW(dev
))
2723 port_sel
= I915_READ(pp_on_reg
) & 0xc0000000;
2725 /* And finally store the new values in the power sequencer. */
2726 pp_on
= (seq
->t1_t3
<< PANEL_POWER_UP_DELAY_SHIFT
) |
2727 (seq
->t8
<< PANEL_LIGHT_ON_DELAY_SHIFT
);
2728 pp_off
= (seq
->t9
<< PANEL_LIGHT_OFF_DELAY_SHIFT
) |
2729 (seq
->t10
<< PANEL_POWER_DOWN_DELAY_SHIFT
);
2730 /* Compute the divisor for the pp clock, simply match the Bspec
2732 pp_div
= ((100 * div
)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT
;
2733 pp_div
|= (DIV_ROUND_UP(seq
->t11_t12
, 1000)
2734 << PANEL_POWER_CYCLE_DELAY_SHIFT
);
2736 /* Haswell doesn't have any port selection bits for the panel
2737 * power sequencer any more. */
2738 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)) {
2739 if (is_cpu_edp(intel_dp
))
2740 port_sel
= PANEL_POWER_PORT_DP_A
;
2742 port_sel
= PANEL_POWER_PORT_DP_D
;
2747 I915_WRITE(pp_on_reg
, pp_on
);
2748 I915_WRITE(pp_off_reg
, pp_off
);
2749 I915_WRITE(pp_div_reg
, pp_div
);
2751 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
2752 I915_READ(pp_on_reg
),
2753 I915_READ(pp_off_reg
),
2754 I915_READ(pp_div_reg
));
2758 intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
2759 struct intel_connector
*intel_connector
)
2761 struct drm_connector
*connector
= &intel_connector
->base
;
2762 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
2763 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
2764 struct drm_device
*dev
= intel_encoder
->base
.dev
;
2765 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2766 struct drm_display_mode
*fixed_mode
= NULL
;
2767 struct edp_power_seq power_seq
= { 0 };
2768 enum port port
= intel_dig_port
->port
;
2769 const char *name
= NULL
;
2772 /* Preserve the current hw state. */
2773 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
2774 intel_dp
->attached_connector
= intel_connector
;
2776 if (HAS_PCH_SPLIT(dev
) && port
== PORT_D
)
2777 if (intel_dpd_is_edp(dev
))
2778 intel_dp
->is_pch_edp
= true;
2781 * FIXME : We need to initialize built-in panels before external panels.
2782 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
2784 if (IS_VALLEYVIEW(dev
) && port
== PORT_C
) {
2785 type
= DRM_MODE_CONNECTOR_eDP
;
2786 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
2787 } else if (port
== PORT_A
|| is_pch_edp(intel_dp
)) {
2788 type
= DRM_MODE_CONNECTOR_eDP
;
2789 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
2791 /* The intel_encoder->type value may be INTEL_OUTPUT_UNKNOWN for
2792 * DDI or INTEL_OUTPUT_DISPLAYPORT for the older gens, so don't
2795 type
= DRM_MODE_CONNECTOR_DisplayPort
;
2798 drm_connector_init(dev
, connector
, &intel_dp_connector_funcs
, type
);
2799 drm_connector_helper_add(connector
, &intel_dp_connector_helper_funcs
);
2801 connector
->interlace_allowed
= true;
2802 connector
->doublescan_allowed
= 0;
2804 INIT_DELAYED_WORK(&intel_dp
->panel_vdd_work
,
2805 ironlake_panel_vdd_work
);
2807 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
2808 drm_sysfs_connector_add(connector
);
2811 intel_connector
->get_hw_state
= intel_ddi_connector_get_hw_state
;
2813 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
2815 intel_dp
->aux_ch_ctl_reg
= intel_dp
->output_reg
+ 0x10;
2817 switch (intel_dig_port
->port
) {
2819 intel_dp
->aux_ch_ctl_reg
= DPA_AUX_CH_CTL
;
2822 intel_dp
->aux_ch_ctl_reg
= PCH_DPB_AUX_CH_CTL
;
2825 intel_dp
->aux_ch_ctl_reg
= PCH_DPC_AUX_CH_CTL
;
2828 intel_dp
->aux_ch_ctl_reg
= PCH_DPD_AUX_CH_CTL
;
2835 /* Set up the DDC bus. */
2838 intel_encoder
->hpd_pin
= HPD_PORT_A
;
2842 intel_encoder
->hpd_pin
= HPD_PORT_B
;
2846 intel_encoder
->hpd_pin
= HPD_PORT_C
;
2850 intel_encoder
->hpd_pin
= HPD_PORT_D
;
2857 if (is_edp(intel_dp
))
2858 intel_dp_init_panel_power_sequencer(dev
, intel_dp
, &power_seq
);
2860 intel_dp_i2c_init(intel_dp
, intel_connector
, name
);
2862 /* Cache DPCD and EDID for edp. */
2863 if (is_edp(intel_dp
)) {
2865 struct drm_display_mode
*scan
;
2868 ironlake_edp_panel_vdd_on(intel_dp
);
2869 ret
= intel_dp_get_dpcd(intel_dp
);
2870 ironlake_edp_panel_vdd_off(intel_dp
, false);
2873 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11)
2874 dev_priv
->no_aux_handshake
=
2875 intel_dp
->dpcd
[DP_MAX_DOWNSPREAD
] &
2876 DP_NO_AUX_HANDSHAKE_LINK_TRAINING
;
2878 /* if this fails, presume the device is a ghost */
2879 DRM_INFO("failed to retrieve link info, disabling eDP\n");
2880 intel_dp_encoder_destroy(&intel_encoder
->base
);
2881 intel_dp_destroy(connector
);
2885 /* We now know it's not a ghost, init power sequence regs. */
2886 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
,
2889 ironlake_edp_panel_vdd_on(intel_dp
);
2890 edid
= drm_get_edid(connector
, &intel_dp
->adapter
);
2892 if (drm_add_edid_modes(connector
, edid
)) {
2893 drm_mode_connector_update_edid_property(connector
, edid
);
2894 drm_edid_to_eld(connector
, edid
);
2897 edid
= ERR_PTR(-EINVAL
);
2900 edid
= ERR_PTR(-ENOENT
);
2902 intel_connector
->edid
= edid
;
2904 /* prefer fixed mode from EDID if available */
2905 list_for_each_entry(scan
, &connector
->probed_modes
, head
) {
2906 if ((scan
->type
& DRM_MODE_TYPE_PREFERRED
)) {
2907 fixed_mode
= drm_mode_duplicate(dev
, scan
);
2912 /* fallback to VBT if available for eDP */
2913 if (!fixed_mode
&& dev_priv
->lfp_lvds_vbt_mode
) {
2914 fixed_mode
= drm_mode_duplicate(dev
, dev_priv
->lfp_lvds_vbt_mode
);
2916 fixed_mode
->type
|= DRM_MODE_TYPE_PREFERRED
;
2919 ironlake_edp_panel_vdd_off(intel_dp
, false);
2922 if (is_edp(intel_dp
)) {
2923 intel_panel_init(&intel_connector
->panel
, fixed_mode
);
2924 intel_panel_setup_backlight(connector
);
2927 intel_dp_add_properties(intel_dp
, connector
);
2929 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2930 * 0xd. Failure to do so will result in spurious interrupts being
2931 * generated on the port when a cable is not attached.
2933 if (IS_G4X(dev
) && !IS_GM45(dev
)) {
2934 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
2935 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);
2940 intel_dp_init(struct drm_device
*dev
, int output_reg
, enum port port
)
2942 struct intel_digital_port
*intel_dig_port
;
2943 struct intel_encoder
*intel_encoder
;
2944 struct drm_encoder
*encoder
;
2945 struct intel_connector
*intel_connector
;
2947 intel_dig_port
= kzalloc(sizeof(struct intel_digital_port
), GFP_KERNEL
);
2948 if (!intel_dig_port
)
2951 intel_connector
= kzalloc(sizeof(struct intel_connector
), GFP_KERNEL
);
2952 if (!intel_connector
) {
2953 kfree(intel_dig_port
);
2957 intel_encoder
= &intel_dig_port
->base
;
2958 encoder
= &intel_encoder
->base
;
2960 drm_encoder_init(dev
, &intel_encoder
->base
, &intel_dp_enc_funcs
,
2961 DRM_MODE_ENCODER_TMDS
);
2962 drm_encoder_helper_add(&intel_encoder
->base
, &intel_dp_helper_funcs
);
2964 intel_encoder
->compute_config
= intel_dp_compute_config
;
2965 intel_encoder
->enable
= intel_enable_dp
;
2966 intel_encoder
->pre_enable
= intel_pre_enable_dp
;
2967 intel_encoder
->disable
= intel_disable_dp
;
2968 intel_encoder
->post_disable
= intel_post_disable_dp
;
2969 intel_encoder
->get_hw_state
= intel_dp_get_hw_state
;
2971 intel_dig_port
->port
= port
;
2972 intel_dig_port
->dp
.output_reg
= output_reg
;
2974 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
2975 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
2976 intel_encoder
->cloneable
= false;
2977 intel_encoder
->hot_plug
= intel_dp_hot_plug
;
2979 intel_dp_init_connector(intel_dig_port
, intel_connector
);