2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
28 #include <linux/async.h>
29 #include <linux/i2c.h>
30 #include <linux/hdmi.h>
31 #include <linux/sched/clock.h>
32 #include <linux/stackdepot.h>
33 #include <drm/i915_drm.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_encoder.h>
37 #include <drm/drm_fb_helper.h>
38 #include <drm/drm_dp_dual_mode_helper.h>
39 #include <drm/drm_dp_mst_helper.h>
40 #include <drm/drm_probe_helper.h>
41 #include <drm/drm_rect.h>
42 #include <drm/drm_vblank.h>
43 #include <drm/drm_atomic.h>
44 #include <drm/i915_mei_hdcp_interface.h>
45 #include <media/cec-notifier.h>
50 * __wait_for - magic wait macro
52 * Macro to help avoid open coding check/wait/timeout patterns. Note that it's
53 * important that we check the condition again after having timed out, since the
54 * timeout could be due to preemption or similar and we've never had a chance to
55 * check the condition before the timeout.
57 #define __wait_for(OP, COND, US, Wmin, Wmax) ({ \
58 const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll * (US)); \
59 long wait__ = (Wmin); /* recommended min for usleep is 10 us */ \
63 const bool expired__ = ktime_after(ktime_get_raw(), end__); \
65 /* Guarantee COND check prior to timeout */ \
75 usleep_range(wait__, wait__ * 2); \
76 if (wait__ < (Wmax)) \
82 #define _wait_for(COND, US, Wmin, Wmax) __wait_for(, (COND), (US), (Wmin), \
84 #define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 10, 1000)
86 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
87 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
88 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
90 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
93 #define _wait_for_atomic(COND, US, ATOMIC) \
95 int cpu, ret, timeout = (US) * 1000; \
97 _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
100 cpu = smp_processor_id(); \
102 base = local_clock(); \
104 u64 now = local_clock(); \
107 /* Guarantee COND check prior to timeout */ \
113 if (now - base >= timeout) { \
120 if (unlikely(cpu != smp_processor_id())) { \
121 timeout -= now - base; \
122 cpu = smp_processor_id(); \
123 base = local_clock(); \
130 #define wait_for_us(COND, US) \
133 BUILD_BUG_ON(!__builtin_constant_p(US)); \
135 ret__ = _wait_for((COND), (US), 10, 10); \
137 ret__ = _wait_for_atomic((COND), (US), 0); \
141 #define wait_for_atomic_us(COND, US) \
143 BUILD_BUG_ON(!__builtin_constant_p(US)); \
144 BUILD_BUG_ON((US) > 50000); \
145 _wait_for_atomic((COND), (US), 1); \
148 #define wait_for_atomic(COND, MS) wait_for_atomic_us((COND), (MS) * 1000)
150 #define KHz(x) (1000 * (x))
151 #define MHz(x) KHz(1000 * (x))
153 #define KBps(x) (1000 * (x))
154 #define MBps(x) KBps(1000 * (x))
155 #define GBps(x) ((u64)1000 * MBps((x)))
158 * Display related stuff
161 /* store information about an Ixxx DVO */
162 /* The i830->i865 use multiple DVOs with multiple i2cs */
163 /* the i915, i945 have a single sDVO i2c bus - which is different */
164 #define MAX_OUTPUTS 6
165 /* maximum connectors per crtcs in the mode set */
167 #define INTEL_I2C_BUS_DVO 1
168 #define INTEL_I2C_BUS_SDVO 2
170 /* these are outputs from the chip - integrated only
171 external chips are via DVO or SDVO output */
172 enum intel_output_type
{
173 INTEL_OUTPUT_UNUSED
= 0,
174 INTEL_OUTPUT_ANALOG
= 1,
175 INTEL_OUTPUT_DVO
= 2,
176 INTEL_OUTPUT_SDVO
= 3,
177 INTEL_OUTPUT_LVDS
= 4,
178 INTEL_OUTPUT_TVOUT
= 5,
179 INTEL_OUTPUT_HDMI
= 6,
181 INTEL_OUTPUT_EDP
= 8,
182 INTEL_OUTPUT_DSI
= 9,
183 INTEL_OUTPUT_DDI
= 10,
184 INTEL_OUTPUT_DP_MST
= 11,
187 #define INTEL_DVO_CHIP_NONE 0
188 #define INTEL_DVO_CHIP_LVDS 1
189 #define INTEL_DVO_CHIP_TMDS 2
190 #define INTEL_DVO_CHIP_TVOUT 4
192 #define INTEL_DSI_VIDEO_MODE 0
193 #define INTEL_DSI_COMMAND_MODE 1
195 struct intel_framebuffer
{
196 struct drm_framebuffer base
;
197 struct intel_rotation_info rot_info
;
199 /* for each plane in the normal GTT view */
203 /* for each plane in the rotated GTT view */
206 unsigned int pitch
; /* pixels */
211 struct drm_fb_helper helper
;
212 struct intel_framebuffer
*fb
;
213 struct i915_vma
*vma
;
214 unsigned long vma_flags
;
215 async_cookie_t cookie
;
218 /* Whether or not fbdev hpd processing is temporarily suspended */
219 bool hpd_suspended
: 1;
220 /* Set when a hotplug was received while HPD processing was
223 bool hpd_waiting
: 1;
225 /* Protects hpd_suspended */
226 struct mutex hpd_lock
;
229 struct intel_encoder
{
230 struct drm_encoder base
;
232 enum intel_output_type type
;
234 unsigned int cloneable
;
235 bool (*hotplug
)(struct intel_encoder
*encoder
,
236 struct intel_connector
*connector
);
237 enum intel_output_type (*compute_output_type
)(struct intel_encoder
*,
238 struct intel_crtc_state
*,
239 struct drm_connector_state
*);
240 int (*compute_config
)(struct intel_encoder
*,
241 struct intel_crtc_state
*,
242 struct drm_connector_state
*);
243 void (*pre_pll_enable
)(struct intel_encoder
*,
244 const struct intel_crtc_state
*,
245 const struct drm_connector_state
*);
246 void (*pre_enable
)(struct intel_encoder
*,
247 const struct intel_crtc_state
*,
248 const struct drm_connector_state
*);
249 void (*enable
)(struct intel_encoder
*,
250 const struct intel_crtc_state
*,
251 const struct drm_connector_state
*);
252 void (*disable
)(struct intel_encoder
*,
253 const struct intel_crtc_state
*,
254 const struct drm_connector_state
*);
255 void (*post_disable
)(struct intel_encoder
*,
256 const struct intel_crtc_state
*,
257 const struct drm_connector_state
*);
258 void (*post_pll_disable
)(struct intel_encoder
*,
259 const struct intel_crtc_state
*,
260 const struct drm_connector_state
*);
261 void (*update_pipe
)(struct intel_encoder
*,
262 const struct intel_crtc_state
*,
263 const struct drm_connector_state
*);
264 /* Read out the current hw state of this connector, returning true if
265 * the encoder is active. If the encoder is enabled it also set the pipe
266 * it is connected to in the pipe parameter. */
267 bool (*get_hw_state
)(struct intel_encoder
*, enum pipe
*pipe
);
268 /* Reconstructs the equivalent mode flags for the current hardware
269 * state. This must be called _after_ display->get_pipe_config has
270 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
271 * be set correctly before calling this function. */
272 void (*get_config
)(struct intel_encoder
*,
273 struct intel_crtc_state
*pipe_config
);
274 /* Returns a mask of power domains that need to be referenced as part
275 * of the hardware state readout code. */
276 u64 (*get_power_domains
)(struct intel_encoder
*encoder
,
277 struct intel_crtc_state
*crtc_state
);
279 * Called during system suspend after all pending requests for the
280 * encoder are flushed (for example for DP AUX transactions) and
281 * device interrupts are disabled.
283 void (*suspend
)(struct intel_encoder
*);
285 enum hpd_pin hpd_pin
;
286 enum intel_display_power_domain power_domain
;
287 /* for communication with audio component; protected by av_mutex */
288 const struct drm_connector
*audio_connector
;
292 struct drm_display_mode
*fixed_mode
;
293 struct drm_display_mode
*downclock_mode
;
302 bool combination_mode
; /* gen 2/4 only */
304 bool alternate_pwm_increment
; /* lpt+ */
307 bool util_pin_active_low
; /* bxt+ */
308 u8 controller
; /* bxt+ only */
309 struct pwm_device
*pwm
;
311 struct backlight_device
*device
;
313 /* Connector and platform specific backlight functions */
314 int (*setup
)(struct intel_connector
*connector
, enum pipe pipe
);
315 u32 (*get
)(struct intel_connector
*connector
);
316 void (*set
)(const struct drm_connector_state
*conn_state
, u32 level
);
317 void (*disable
)(const struct drm_connector_state
*conn_state
);
318 void (*enable
)(const struct intel_crtc_state
*crtc_state
,
319 const struct drm_connector_state
*conn_state
);
320 u32 (*hz_to_pwm
)(struct intel_connector
*connector
, u32 hz
);
321 void (*power
)(struct intel_connector
*, bool enable
);
325 struct intel_digital_port
;
327 enum check_link_response
{
328 HDCP_LINK_PROTECTED
= 0,
329 HDCP_TOPOLOGY_CHANGE
,
330 HDCP_LINK_INTEGRITY_FAILURE
,
335 * This structure serves as a translation layer between the generic HDCP code
336 * and the bus-specific code. What that means is that HDCP over HDMI differs
337 * from HDCP over DP, so to account for these differences, we need to
338 * communicate with the receiver through this shim.
340 * For completeness, the 2 buses differ in the following ways:
342 * HDCP registers on the receiver are set via DP AUX for DP, and
343 * they are set via DDC for HDMI.
344 * - Receiver register offsets
345 * The offsets of the registers are different for DP vs. HDMI
346 * - Receiver register masks/offsets
347 * For instance, the ready bit for the KSV fifo is in a different
348 * place on DP vs HDMI
349 * - Receiver register names
350 * Seriously. In the DP spec, the 16-bit register containing
351 * downstream information is called BINFO, on HDMI it's called
352 * BSTATUS. To confuse matters further, DP has a BSTATUS register
353 * with a completely different definition.
355 * On HDMI, the ksv fifo is read all at once, whereas on DP it must
356 * be read 3 keys at a time
358 * Since Aksv is hidden in hardware, there's different procedures
359 * to send it over DP AUX vs DDC
361 struct intel_hdcp_shim
{
362 /* Outputs the transmitter's An and Aksv values to the receiver. */
363 int (*write_an_aksv
)(struct intel_digital_port
*intel_dig_port
, u8
*an
);
365 /* Reads the receiver's key selection vector */
366 int (*read_bksv
)(struct intel_digital_port
*intel_dig_port
, u8
*bksv
);
369 * Reads BINFO from DP receivers and BSTATUS from HDMI receivers. The
370 * definitions are the same in the respective specs, but the names are
371 * different. Call it BSTATUS since that's the name the HDMI spec
372 * uses and it was there first.
374 int (*read_bstatus
)(struct intel_digital_port
*intel_dig_port
,
377 /* Determines whether a repeater is present downstream */
378 int (*repeater_present
)(struct intel_digital_port
*intel_dig_port
,
379 bool *repeater_present
);
381 /* Reads the receiver's Ri' value */
382 int (*read_ri_prime
)(struct intel_digital_port
*intel_dig_port
, u8
*ri
);
384 /* Determines if the receiver's KSV FIFO is ready for consumption */
385 int (*read_ksv_ready
)(struct intel_digital_port
*intel_dig_port
,
388 /* Reads the ksv fifo for num_downstream devices */
389 int (*read_ksv_fifo
)(struct intel_digital_port
*intel_dig_port
,
390 int num_downstream
, u8
*ksv_fifo
);
392 /* Reads a 32-bit part of V' from the receiver */
393 int (*read_v_prime_part
)(struct intel_digital_port
*intel_dig_port
,
396 /* Enables HDCP signalling on the port */
397 int (*toggle_signalling
)(struct intel_digital_port
*intel_dig_port
,
400 /* Ensures the link is still protected */
401 bool (*check_link
)(struct intel_digital_port
*intel_dig_port
);
403 /* Detects panel's hdcp capability. This is optional for HDMI. */
404 int (*hdcp_capable
)(struct intel_digital_port
*intel_dig_port
,
407 /* HDCP adaptation(DP/HDMI) required on the port */
408 enum hdcp_wired_protocol protocol
;
410 /* Detects whether sink is HDCP2.2 capable */
411 int (*hdcp_2_2_capable
)(struct intel_digital_port
*intel_dig_port
,
414 /* Write HDCP2.2 messages */
415 int (*write_2_2_msg
)(struct intel_digital_port
*intel_dig_port
,
416 void *buf
, size_t size
);
418 /* Read HDCP2.2 messages */
419 int (*read_2_2_msg
)(struct intel_digital_port
*intel_dig_port
,
420 u8 msg_id
, void *buf
, size_t size
);
423 * Implementation of DP HDCP2.2 Errata for the communication of stream
424 * type to Receivers. In DP HDCP2.2 Stream type is one of the input to
425 * the HDCP2.2 Cipher for En/De-Cryption. Not applicable for HDMI.
427 int (*config_stream_type
)(struct intel_digital_port
*intel_dig_port
,
428 bool is_repeater
, u8 type
);
430 /* HDCP2.2 Link Integrity Check */
431 int (*check_2_2_link
)(struct intel_digital_port
*intel_dig_port
);
435 const struct intel_hdcp_shim
*shim
;
436 /* Mutex for hdcp state of the connector */
439 struct delayed_work check_work
;
440 struct work_struct prop_work
;
442 /* HDCP1.4 Encryption status */
445 /* HDCP2.2 related definitions */
446 /* Flag indicates whether this connector supports HDCP2.2 or not. */
447 bool hdcp2_supported
;
449 /* HDCP2.2 Encryption status */
450 bool hdcp2_encrypted
;
453 * Content Stream Type defined by content owner. TYPE0(0x0) content can
454 * flow in the link protected by HDCP2.2 or HDCP1.4, where as TYPE1(0x1)
455 * content can flow only through a link protected by HDCP2.2.
458 struct hdcp_port_data port_data
;
464 * Count of ReceiverID_List received. Initialized to 0 at AKE_INIT.
465 * Incremented after processing the RepeaterAuth_Send_ReceiverID_List.
466 * When it rolls over re-auth has to be triggered.
471 * Count of RepeaterAuth_Stream_Manage msg propagated.
472 * Initialized to 0 on AKE_INIT. Incremented after every successful
473 * transmission of RepeaterAuth_Stream_Manage message. When it rolls
474 * over re-Auth has to be triggered.
479 * Work queue to signal the CP_IRQ. Used for the waiters to read the
480 * available information from HDCP DP sink.
482 wait_queue_head_t cp_irq_queue
;
483 atomic_t cp_irq_count
;
484 int cp_irq_count_cached
;
487 struct intel_connector
{
488 struct drm_connector base
;
490 * The fixed encoder this connector is connected to.
492 struct intel_encoder
*encoder
;
494 /* ACPI device id for ACPI and driver cooperation */
497 /* Reads out the current hw, returning true if the connector is enabled
498 * and active (i.e. dpms ON state). */
499 bool (*get_hw_state
)(struct intel_connector
*);
501 /* Panel info for eDP and LVDS */
502 struct intel_panel panel
;
504 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
506 struct edid
*detect_edid
;
508 /* since POLL and HPD connectors may use the same HPD line keep the native
509 state of connector->polled in case hotplug storm detection changes it */
512 void *port
; /* store this opaque as its illegal to dereference it */
514 struct intel_dp
*mst_port
;
516 /* Work struct to schedule a uevent on link train failure */
517 struct work_struct modeset_retry_work
;
519 struct intel_hdcp hdcp
;
522 struct intel_digital_connector_state
{
523 struct drm_connector_state base
;
525 enum hdmi_force_audio force_audio
;
529 #define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base)
543 struct intel_atomic_state
{
544 struct drm_atomic_state base
;
548 * Logical state of cdclk (used for all scaling, watermark,
549 * etc. calculations and checks). This is computed as if all
550 * enabled crtcs were active.
552 struct intel_cdclk_state logical
;
555 * Actual state of cdclk, can be different from the logical
556 * state only when all crtc's are DPMS off.
558 struct intel_cdclk_state actual
;
561 bool force_min_cdclk_changed
;
562 /* pipe to which cd2x update is synchronized */
566 bool dpll_set
, modeset
;
569 * Does this transaction change the pipes that are active? This mask
570 * tracks which CRTC's have changed their active state at the end of
571 * the transaction (not counting the temporary disable during modesets).
572 * This mask should only be non-zero when intel_state->modeset is true,
573 * but the converse is not necessarily true; simply changing a mode may
574 * not flip the final active status of any CRTC's
576 unsigned int active_pipe_changes
;
578 unsigned int active_crtcs
;
579 /* minimum acceptable cdclk for each pipe */
580 int min_cdclk
[I915_MAX_PIPES
];
581 /* minimum acceptable voltage level for each pipe */
582 u8 min_voltage_level
[I915_MAX_PIPES
];
584 struct intel_shared_dpll_state shared_dpll
[I915_NUM_PLLS
];
587 * Current watermarks can't be trusted during hardware readout, so
588 * don't bother calculating intermediate watermarks.
590 bool skip_intermediate_wm
;
592 bool rps_interactive
;
595 struct skl_ddb_values wm_results
;
597 struct i915_sw_fence commit_ready
;
599 struct llist_node freed
;
602 struct intel_plane_state
{
603 struct drm_plane_state base
;
604 struct i915_ggtt_view view
;
605 struct i915_vma
*vma
;
607 #define PLANE_HAS_FENCE BIT(0)
613 * bytes for 0/180 degree rotation
614 * pixels for 90/270 degree rotation
620 /* plane control register */
623 /* plane color control register */
628 * = -1 : not using a scaler
629 * >= 0 : using a scalers
631 * plane requiring a scaler:
632 * - During check_plane, its bit is set in
633 * crtc_state->scaler_state.scaler_users by calling helper function
634 * update_scaler_plane.
635 * - scaler_id indicates the scaler it got assigned.
637 * plane doesn't require a scaler:
638 * - this can happen when scaling is no more required or plane simply
640 * - During check_plane, corresponding bit is reset in
641 * crtc_state->scaler_state.scaler_users by calling helper function
642 * update_scaler_plane.
649 * ICL planar formats require 2 planes that are updated as pairs.
650 * This member is used to make sure the other plane is also updated
651 * when required, and for update_slave() to find the correct
652 * plane_state to pass as argument.
654 struct intel_plane
*linked_plane
;
658 * If set don't update use the linked plane's state for updating
659 * this plane during atomic commit with the update_slave() callback.
661 * It's also used by the watermark code to ignore wm calculations on
662 * this plane. They're calculated by the linked plane's wm code.
666 struct drm_intel_sprite_colorkey ckey
;
669 struct intel_initial_plane_config
{
670 struct intel_framebuffer
*fb
;
677 #define SKL_MIN_SRC_W 8
678 #define SKL_MAX_SRC_W 4096
679 #define SKL_MIN_SRC_H 8
680 #define SKL_MAX_SRC_H 4096
681 #define SKL_MIN_DST_W 8
682 #define SKL_MAX_DST_W 4096
683 #define SKL_MIN_DST_H 8
684 #define SKL_MAX_DST_H 4096
685 #define ICL_MAX_SRC_W 5120
686 #define ICL_MAX_SRC_H 4096
687 #define ICL_MAX_DST_W 5120
688 #define ICL_MAX_DST_H 4096
689 #define SKL_MIN_YUV_420_SRC_W 16
690 #define SKL_MIN_YUV_420_SRC_H 16
692 struct intel_scaler
{
697 struct intel_crtc_scaler_state
{
698 #define SKL_NUM_SCALERS 2
699 struct intel_scaler scalers
[SKL_NUM_SCALERS
];
702 * scaler_users: keeps track of users requesting scalers on this crtc.
704 * If a bit is set, a user is using a scaler.
705 * Here user can be a plane or crtc as defined below:
706 * bits 0-30 - plane (bit position is index from drm_plane_index)
709 * Instead of creating a new index to cover planes and crtc, using
710 * existing drm_plane_index for planes which is well less than 31
711 * planes and bit 31 for crtc. This should be fine to cover all
714 * intel_atomic_setup_scalers will setup available scalers to users
715 * requesting scalers. It will gracefully fail if request exceeds
718 #define SKL_CRTC_INDEX 31
719 unsigned scaler_users
;
721 /* scaler used by crtc for panel fitting purpose */
725 /* drm_mode->private_flags */
726 #define I915_MODE_FLAG_INHERITED (1<<0)
727 /* Flag to get scanline using frame time stamps */
728 #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1)
729 /* Flag to use the scanline counter instead of the pixel counter */
730 #define I915_MODE_FLAG_USE_SCANLINE_COUNTER (1<<2)
732 struct intel_pipe_wm
{
733 struct intel_wm_level wm
[5];
737 bool sprites_enabled
;
741 struct skl_plane_wm
{
742 struct skl_wm_level wm
[8];
743 struct skl_wm_level uv_wm
[8];
744 struct skl_wm_level trans_wm
;
749 struct skl_plane_wm planes
[I915_MAX_PLANES
];
756 VLV_WM_LEVEL_DDR_DVFS
,
760 struct vlv_wm_state
{
761 struct g4x_pipe_wm wm
[NUM_VLV_WM_LEVELS
];
762 struct g4x_sr_wm sr
[NUM_VLV_WM_LEVELS
];
767 struct vlv_fifo_state
{
768 u16 plane
[I915_MAX_PLANES
];
778 struct g4x_wm_state
{
779 struct g4x_pipe_wm wm
;
781 struct g4x_sr_wm hpll
;
787 struct intel_crtc_wm_state
{
791 * Intermediate watermarks; these can be
792 * programmed immediately since they satisfy
793 * both the current configuration we're
794 * switching away from and the new
795 * configuration we're switching to.
797 struct intel_pipe_wm intermediate
;
800 * Optimal watermarks, programmed post-vblank
801 * when this state is committed.
803 struct intel_pipe_wm optimal
;
807 /* gen9+ only needs 1-step wm programming */
808 struct skl_pipe_wm optimal
;
809 struct skl_ddb_entry ddb
;
810 struct skl_ddb_entry plane_ddb_y
[I915_MAX_PLANES
];
811 struct skl_ddb_entry plane_ddb_uv
[I915_MAX_PLANES
];
815 /* "raw" watermarks (not inverted) */
816 struct g4x_pipe_wm raw
[NUM_VLV_WM_LEVELS
];
817 /* intermediate watermarks (inverted) */
818 struct vlv_wm_state intermediate
;
819 /* optimal watermarks (inverted) */
820 struct vlv_wm_state optimal
;
821 /* display FIFO split */
822 struct vlv_fifo_state fifo_state
;
826 /* "raw" watermarks */
827 struct g4x_pipe_wm raw
[NUM_G4X_WM_LEVELS
];
828 /* intermediate watermarks */
829 struct g4x_wm_state intermediate
;
830 /* optimal watermarks */
831 struct g4x_wm_state optimal
;
836 * Platforms with two-step watermark programming will need to
837 * update watermark programming post-vblank to switch from the
838 * safe intermediate watermarks to the optimal final
841 bool need_postvbl_update
;
844 enum intel_output_format
{
845 INTEL_OUTPUT_FORMAT_INVALID
,
846 INTEL_OUTPUT_FORMAT_RGB
,
847 INTEL_OUTPUT_FORMAT_YCBCR420
,
848 INTEL_OUTPUT_FORMAT_YCBCR444
,
851 struct intel_crtc_state
{
852 struct drm_crtc_state base
;
855 * quirks - bitfield with hw state readout quirks
857 * For various reasons the hw state readout code might not be able to
858 * completely faithfully read out the current state. These cases are
859 * tracked with quirk flags so that fastboot and state checker can act
862 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
863 unsigned long quirks
;
865 unsigned fb_bits
; /* framebuffers to flip */
866 bool update_pipe
; /* can a fast modeset be performed? */
868 bool update_wm_pre
, update_wm_post
; /* watermarks are updated */
869 bool fb_changed
; /* fb on any of the planes is changed */
870 bool fifo_changed
; /* FIFO split is changed */
872 /* Pipe source size (ie. panel fitter input size)
873 * All planes will be positioned inside this space,
874 * and get clipped at the edges. */
875 int pipe_src_w
, pipe_src_h
;
878 * Pipe pixel rate, adjusted for
879 * panel fitter/pipe scaler downscaling.
881 unsigned int pixel_rate
;
883 /* Whether to set up the PCH/FDI. Note that we never allow sharing
884 * between pch encoders and cpu encoders. */
885 bool has_pch_encoder
;
887 /* Are we sending infoframes on the attached port */
890 /* CPU Transcoder for the pipe. Currently this can only differ from the
891 * pipe on Haswell and later (where we have a special eDP transcoder)
892 * and Broxton (where we have special DSI transcoders). */
893 enum transcoder cpu_transcoder
;
896 * Use reduced/limited/broadcast rbg range, compressing from the full
897 * range fed into the crtcs.
899 bool limited_color_range
;
901 /* Bitmask of encoder types (enum intel_output_type)
902 * driven by the pipe.
904 unsigned int output_types
;
906 /* Whether we should send NULL infoframes. Required for audio. */
909 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
910 * has_dp_encoder is set. */
914 * Enable dithering, used when the selected pipe bpp doesn't match the
920 * Dither gets enabled for 18bpp which causes CRC mismatch errors for
921 * compliance video pattern tests.
922 * Disable dither only if it is a compliance test request for
925 bool dither_force_disable
;
927 /* Controls for the clock computation, to override various stages. */
930 /* SDVO TV has a bunch of special case. To make multifunction encoders
931 * work correctly, we need to track this at runtime.*/
935 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
936 * required. This is set in the 2nd loop of calling encoder's
937 * ->compute_config if the first pick doesn't work out.
941 /* Settings for the intel dpll used on pretty much everything but
945 /* Selected dpll when shared or NULL. */
946 struct intel_shared_dpll
*shared_dpll
;
948 /* Actual register state of the dpll, for shared dpll cross-checking. */
949 struct intel_dpll_hw_state dpll_hw_state
;
951 /* DSI PLL registers */
957 struct intel_link_m_n dp_m_n
;
959 /* m2_n2 for eDP downclock */
960 struct intel_link_m_n dp_m2_n2
;
967 * Frequence the dpll for the port should run at. Differs from the
968 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
969 * already multiplied by pixel_multiplier.
973 /* Used by SDVO (and if we ever fix it, HDMI). */
974 unsigned pixel_multiplier
;
979 * Used by platforms having DP/HDMI PHY with programmable lane
980 * latency optimization.
982 u8 lane_lat_optim_mask
;
984 /* minimum acceptable voltage level */
985 u8 min_voltage_level
;
987 /* Panel fitter controls for gen2-gen4 + VLV */
991 u32 lvds_border_bits
;
994 /* Panel fitter placement and size for Ironlake+ */
1002 /* FDI configuration, only valid if has_pch_encoder is set. */
1004 struct intel_link_m_n fdi_m_n
;
1016 struct intel_crtc_scaler_state scaler_state
;
1018 /* w/a for waiting 2 vblanks during crtc enable */
1019 enum pipe hsw_workaround_pipe
;
1021 /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
1024 struct intel_crtc_wm_state wm
;
1026 /* Gamma mode programmed on the pipe */
1030 /* CSC mode programmed on the pipe */
1037 /* bitmask of visible planes (enum plane_id) */
1042 /* bitmask of planes that will be updated during the commit */
1048 union hdmi_infoframe avi
;
1049 union hdmi_infoframe spd
;
1050 union hdmi_infoframe hdmi
;
1053 /* HDMI scrambling status */
1054 bool hdmi_scrambling
;
1056 /* HDMI High TMDS char rate ratio */
1057 bool hdmi_high_tmds_clock_ratio
;
1059 /* Output format RGB/YCBCR etc */
1060 enum intel_output_format output_format
;
1062 /* Output down scaling is done in LSPCON device */
1063 bool lspcon_downsampling
;
1065 /* enable pipe gamma? */
1068 /* enable pipe csc? */
1071 /* Display Stream compression state */
1073 bool compression_enable
;
1078 struct drm_dsc_config dp_dsc_cfg
;
1080 /* Forward Error correction State */
1085 struct drm_crtc base
;
1088 * Whether the crtc and the connected output pipeline is active. Implies
1089 * that crtc->enabled is set, i.e. the current mode configuration has
1090 * some outputs connected to this crtc.
1094 unsigned long long enabled_power_domains
;
1095 struct intel_overlay
*overlay
;
1097 struct intel_crtc_state
*config
;
1099 /* Access to these should be protected by dev_priv->irq_lock. */
1100 bool cpu_fifo_underrun_disabled
;
1101 bool pch_fifo_underrun_disabled
;
1103 /* per-pipe watermark state */
1105 /* watermarks currently being used */
1107 struct intel_pipe_wm ilk
;
1108 struct vlv_wm_state vlv
;
1109 struct g4x_wm_state g4x
;
1113 int scanline_offset
;
1116 unsigned start_vbl_count
;
1117 ktime_t start_vbl_time
;
1118 int min_vbl
, max_vbl
;
1122 /* scalers available on this crtc */
1126 struct intel_plane
{
1127 struct drm_plane base
;
1128 enum i9xx_plane_id i9xx_plane
;
1133 u32 frontbuffer_bit
;
1136 u32 base
, cntl
, size
;
1140 * NOTE: Do not place new plane state fields here (e.g., when adding
1141 * new plane properties). New runtime state should now be placed in
1142 * the intel_plane_state structure and accessed via plane_state.
1145 unsigned int (*max_stride
)(struct intel_plane
*plane
,
1146 u32 pixel_format
, u64 modifier
,
1147 unsigned int rotation
);
1148 void (*update_plane
)(struct intel_plane
*plane
,
1149 const struct intel_crtc_state
*crtc_state
,
1150 const struct intel_plane_state
*plane_state
);
1151 void (*update_slave
)(struct intel_plane
*plane
,
1152 const struct intel_crtc_state
*crtc_state
,
1153 const struct intel_plane_state
*plane_state
);
1154 void (*disable_plane
)(struct intel_plane
*plane
,
1155 const struct intel_crtc_state
*crtc_state
);
1156 bool (*get_hw_state
)(struct intel_plane
*plane
, enum pipe
*pipe
);
1157 int (*check_plane
)(struct intel_crtc_state
*crtc_state
,
1158 struct intel_plane_state
*plane_state
);
1161 struct intel_watermark_params
{
1169 struct cxsr_latency
{
1170 bool is_desktop
: 1;
1175 u16 display_hpll_disable
;
1177 u16 cursor_hpll_disable
;
1180 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
1181 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
1182 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
1183 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
1184 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
1185 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
1186 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
1187 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
1188 #define intel_fb_obj(x) ((x) ? to_intel_bo((x)->obj[0]) : NULL)
1191 i915_reg_t hdmi_reg
;
1194 enum drm_dp_dual_mode_type type
;
1199 struct intel_connector
*attached_connector
;
1200 struct cec_notifier
*cec_notifier
;
1203 struct intel_dp_mst_encoder
;
1204 #define DP_MAX_DOWNSTREAM_PORTS 0x10
1207 * enum link_m_n_set:
1208 * When platform provides two set of M_N registers for dp, we can
1209 * program them and switch between them incase of DRRS.
1210 * But When only one such register is provided, we have to program the
1211 * required divider value on that registers itself based on the DRRS state.
1213 * M1_N1 : Program dp_m_n on M1_N1 registers
1214 * dp_m2_n2 on M2_N2 registers (If supported)
1216 * M2_N2 : Program dp_m2_n2 on M1_N1 registers
1217 * M2_N2 registers are not supported
1221 /* Sets the m1_n1 and m2_n2 */
1226 struct intel_dp_compliance_data
{
1229 u16 hdisplay
, vdisplay
;
1233 struct intel_dp_compliance
{
1234 unsigned long test_type
;
1235 struct intel_dp_compliance_data test_data
;
1242 i915_reg_t output_reg
;
1250 bool reset_link_params
;
1251 u8 dpcd
[DP_RECEIVER_CAP_SIZE
];
1252 u8 psr_dpcd
[EDP_PSR_RECEIVER_CAP_SIZE
];
1253 u8 downstream_ports
[DP_MAX_DOWNSTREAM_PORTS
];
1254 u8 edp_dpcd
[EDP_DISPLAY_CTL_CAP_SIZE
];
1255 u8 dsc_dpcd
[DP_DSC_RECEIVER_CAP_SIZE
];
1258 int num_source_rates
;
1259 const int *source_rates
;
1260 /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
1262 int sink_rates
[DP_MAX_SUPPORTED_RATES
];
1263 bool use_rate_select
;
1264 /* intersection of source and sink rates */
1265 int num_common_rates
;
1266 int common_rates
[DP_MAX_SUPPORTED_RATES
];
1267 /* Max lane count for the current link */
1268 int max_link_lane_count
;
1269 /* Max rate for the current link */
1271 /* sink or branch descriptor */
1272 struct drm_dp_desc desc
;
1273 struct drm_dp_aux aux
;
1275 int panel_power_up_delay
;
1276 int panel_power_down_delay
;
1277 int panel_power_cycle_delay
;
1278 int backlight_on_delay
;
1279 int backlight_off_delay
;
1280 struct delayed_work panel_vdd_work
;
1281 bool want_panel_vdd
;
1282 unsigned long last_power_on
;
1283 unsigned long last_backlight_off
;
1284 ktime_t panel_power_off_time
;
1286 struct notifier_block edp_notifier
;
1289 * Pipe whose power sequencer is currently locked into
1290 * this port. Only relevant on VLV/CHV.
1294 * Pipe currently driving the port. Used for preventing
1295 * the use of the PPS for any pipe currentrly driving
1296 * external DP as that will mess things up on VLV.
1298 enum pipe active_pipe
;
1300 * Set if the sequencer may be reset due to a power transition,
1301 * requiring a reinitialization. Only relevant on BXT.
1304 struct edp_power_seq pps_delays
;
1306 bool can_mst
; /* this port supports mst */
1308 int active_mst_links
;
1309 /* connector directly attached - won't be use for modeset in mst world */
1310 struct intel_connector
*attached_connector
;
1312 /* mst connector list */
1313 struct intel_dp_mst_encoder
*mst_encoders
[I915_MAX_PIPES
];
1314 struct drm_dp_mst_topology_mgr mst_mgr
;
1316 u32 (*get_aux_clock_divider
)(struct intel_dp
*dp
, int index
);
1318 * This function returns the value we have to program the AUX_CTL
1319 * register with to kick off an AUX transaction.
1321 u32 (*get_aux_send_ctl
)(struct intel_dp
*dp
, int send_bytes
,
1322 u32 aux_clock_divider
);
1324 i915_reg_t (*aux_ch_ctl_reg
)(struct intel_dp
*dp
);
1325 i915_reg_t (*aux_ch_data_reg
)(struct intel_dp
*dp
, int index
);
1327 /* This is called before a link training is starterd */
1328 void (*prepare_link_retrain
)(struct intel_dp
*intel_dp
);
1330 /* Displayport compliance testing */
1331 struct intel_dp_compliance compliance
;
1333 /* Display stream compression testing */
1337 enum lspcon_vendor
{
1339 LSPCON_VENDOR_PARADE
1342 struct intel_lspcon
{
1344 enum drm_lspcon_mode mode
;
1345 enum lspcon_vendor vendor
;
1348 struct intel_digital_port
{
1349 struct intel_encoder base
;
1350 u32 saved_port_bits
;
1352 struct intel_hdmi hdmi
;
1353 struct intel_lspcon lspcon
;
1354 enum irqreturn (*hpd_pulse
)(struct intel_digital_port
*, bool);
1355 bool release_cl2_override
;
1357 /* Used for DP and ICL+ TypeC/DP and TypeC/HDMI ports. */
1359 enum intel_display_power_domain ddi_io_power_domain
;
1360 bool tc_legacy_port
:1;
1361 enum tc_port_type tc_type
;
1363 void (*write_infoframe
)(struct intel_encoder
*encoder
,
1364 const struct intel_crtc_state
*crtc_state
,
1366 const void *frame
, ssize_t len
);
1367 void (*read_infoframe
)(struct intel_encoder
*encoder
,
1368 const struct intel_crtc_state
*crtc_state
,
1370 void *frame
, ssize_t len
);
1371 void (*set_infoframes
)(struct intel_encoder
*encoder
,
1373 const struct intel_crtc_state
*crtc_state
,
1374 const struct drm_connector_state
*conn_state
);
1375 u32 (*infoframes_enabled
)(struct intel_encoder
*encoder
,
1376 const struct intel_crtc_state
*pipe_config
);
1379 struct intel_dp_mst_encoder
{
1380 struct intel_encoder base
;
1382 struct intel_digital_port
*primary
;
1383 struct intel_connector
*connector
;
1386 static inline enum dpio_channel
1387 vlv_dport_to_channel(struct intel_digital_port
*dport
)
1389 switch (dport
->base
.port
) {
1400 static inline enum dpio_phy
1401 vlv_dport_to_phy(struct intel_digital_port
*dport
)
1403 switch (dport
->base
.port
) {
1414 static inline enum dpio_channel
1415 vlv_pipe_to_channel(enum pipe pipe
)
1428 static inline struct intel_crtc
*
1429 intel_get_crtc_for_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1431 return dev_priv
->pipe_to_crtc_mapping
[pipe
];
1434 static inline struct intel_crtc
*
1435 intel_get_crtc_for_plane(struct drm_i915_private
*dev_priv
, enum i9xx_plane_id plane
)
1437 return dev_priv
->plane_to_crtc_mapping
[plane
];
1440 struct intel_load_detect_pipe
{
1441 struct drm_atomic_state
*restore_state
;
1444 static inline struct intel_encoder
*
1445 intel_attached_encoder(struct drm_connector
*connector
)
1447 return to_intel_connector(connector
)->encoder
;
1450 static inline bool intel_encoder_is_dig_port(struct intel_encoder
*encoder
)
1452 switch (encoder
->type
) {
1453 case INTEL_OUTPUT_DDI
:
1454 case INTEL_OUTPUT_DP
:
1455 case INTEL_OUTPUT_EDP
:
1456 case INTEL_OUTPUT_HDMI
:
1463 static inline struct intel_digital_port
*
1464 enc_to_dig_port(struct drm_encoder
*encoder
)
1466 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
1468 if (intel_encoder_is_dig_port(intel_encoder
))
1469 return container_of(encoder
, struct intel_digital_port
,
1475 static inline struct intel_digital_port
*
1476 conn_to_dig_port(struct intel_connector
*connector
)
1478 return enc_to_dig_port(&intel_attached_encoder(&connector
->base
)->base
);
1481 static inline struct intel_dp_mst_encoder
*
1482 enc_to_mst(struct drm_encoder
*encoder
)
1484 return container_of(encoder
, struct intel_dp_mst_encoder
, base
.base
);
1487 static inline struct intel_dp
*enc_to_intel_dp(struct drm_encoder
*encoder
)
1489 return &enc_to_dig_port(encoder
)->dp
;
1492 static inline bool intel_encoder_is_dp(struct intel_encoder
*encoder
)
1494 switch (encoder
->type
) {
1495 case INTEL_OUTPUT_DP
:
1496 case INTEL_OUTPUT_EDP
:
1498 case INTEL_OUTPUT_DDI
:
1499 /* Skip pure HDMI/DVI DDI encoders */
1500 return i915_mmio_reg_valid(enc_to_intel_dp(&encoder
->base
)->output_reg
);
1506 static inline struct intel_lspcon
*
1507 enc_to_intel_lspcon(struct drm_encoder
*encoder
)
1509 return &enc_to_dig_port(encoder
)->lspcon
;
1512 static inline struct intel_digital_port
*
1513 dp_to_dig_port(struct intel_dp
*intel_dp
)
1515 return container_of(intel_dp
, struct intel_digital_port
, dp
);
1518 static inline struct intel_lspcon
*
1519 dp_to_lspcon(struct intel_dp
*intel_dp
)
1521 return &dp_to_dig_port(intel_dp
)->lspcon
;
1524 static inline struct drm_i915_private
*
1525 dp_to_i915(struct intel_dp
*intel_dp
)
1527 return to_i915(dp_to_dig_port(intel_dp
)->base
.base
.dev
);
1530 static inline struct intel_digital_port
*
1531 hdmi_to_dig_port(struct intel_hdmi
*intel_hdmi
)
1533 return container_of(intel_hdmi
, struct intel_digital_port
, hdmi
);
1536 static inline struct intel_plane_state
*
1537 intel_atomic_get_plane_state(struct intel_atomic_state
*state
,
1538 struct intel_plane
*plane
)
1540 struct drm_plane_state
*ret
=
1541 drm_atomic_get_plane_state(&state
->base
, &plane
->base
);
1544 return ERR_CAST(ret
);
1546 return to_intel_plane_state(ret
);
1549 static inline struct intel_plane_state
*
1550 intel_atomic_get_old_plane_state(struct intel_atomic_state
*state
,
1551 struct intel_plane
*plane
)
1553 return to_intel_plane_state(drm_atomic_get_old_plane_state(&state
->base
,
1557 static inline struct intel_plane_state
*
1558 intel_atomic_get_new_plane_state(struct intel_atomic_state
*state
,
1559 struct intel_plane
*plane
)
1561 return to_intel_plane_state(drm_atomic_get_new_plane_state(&state
->base
,
1565 static inline struct intel_crtc_state
*
1566 intel_atomic_get_old_crtc_state(struct intel_atomic_state
*state
,
1567 struct intel_crtc
*crtc
)
1569 return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state
->base
,
1573 static inline struct intel_crtc_state
*
1574 intel_atomic_get_new_crtc_state(struct intel_atomic_state
*state
,
1575 struct intel_crtc
*crtc
)
1577 return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state
->base
,
1581 /* intel_fifo_underrun.c */
1582 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private
*dev_priv
,
1583 enum pipe pipe
, bool enable
);
1584 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private
*dev_priv
,
1585 enum pipe pch_transcoder
,
1587 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private
*dev_priv
,
1589 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private
*dev_priv
,
1590 enum pipe pch_transcoder
);
1591 void intel_check_cpu_fifo_underruns(struct drm_i915_private
*dev_priv
);
1592 void intel_check_pch_fifo_underruns(struct drm_i915_private
*dev_priv
);
1595 void gen5_enable_gt_irq(struct drm_i915_private
*dev_priv
, u32 mask
);
1596 void gen5_disable_gt_irq(struct drm_i915_private
*dev_priv
, u32 mask
);
1597 void gen6_mask_pm_irq(struct drm_i915_private
*dev_priv
, u32 mask
);
1598 void gen6_unmask_pm_irq(struct drm_i915_private
*dev_priv
, u32 mask
);
1599 void gen11_reset_rps_interrupts(struct drm_i915_private
*dev_priv
);
1600 void gen6_reset_rps_interrupts(struct drm_i915_private
*dev_priv
);
1601 void gen6_enable_rps_interrupts(struct drm_i915_private
*dev_priv
);
1602 void gen6_disable_rps_interrupts(struct drm_i915_private
*dev_priv
);
1604 static inline u32
gen6_sanitize_rps_pm_mask(const struct drm_i915_private
*i915
,
1607 return mask
& ~i915
->gt_pm
.rps
.pm_intrmsk_mbz
;
1610 void intel_runtime_pm_disable_interrupts(struct drm_i915_private
*dev_priv
);
1611 void intel_runtime_pm_enable_interrupts(struct drm_i915_private
*dev_priv
);
1612 static inline bool intel_irqs_enabled(struct drm_i915_private
*dev_priv
)
1615 * We only use drm_irq_uninstall() at unload and VT switch, so
1616 * this is the only thing we need to check.
1618 return dev_priv
->runtime_pm
.irqs_enabled
;
1621 int intel_get_crtc_scanline(struct intel_crtc
*crtc
);
1622 void gen8_irq_power_well_post_enable(struct drm_i915_private
*dev_priv
,
1624 void gen8_irq_power_well_pre_disable(struct drm_i915_private
*dev_priv
,
1626 void gen9_reset_guc_interrupts(struct drm_i915_private
*dev_priv
);
1627 void gen9_enable_guc_interrupts(struct drm_i915_private
*dev_priv
);
1628 void gen9_disable_guc_interrupts(struct drm_i915_private
*dev_priv
);
1631 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state
*crtc_state
);
1632 void skl_init_cdclk(struct drm_i915_private
*dev_priv
);
1633 void skl_uninit_cdclk(struct drm_i915_private
*dev_priv
);
1634 void cnl_init_cdclk(struct drm_i915_private
*dev_priv
);
1635 void cnl_uninit_cdclk(struct drm_i915_private
*dev_priv
);
1636 void bxt_init_cdclk(struct drm_i915_private
*dev_priv
);
1637 void bxt_uninit_cdclk(struct drm_i915_private
*dev_priv
);
1638 void icl_init_cdclk(struct drm_i915_private
*dev_priv
);
1639 void icl_uninit_cdclk(struct drm_i915_private
*dev_priv
);
1640 void intel_init_cdclk_hooks(struct drm_i915_private
*dev_priv
);
1641 void intel_update_max_cdclk(struct drm_i915_private
*dev_priv
);
1642 void intel_update_cdclk(struct drm_i915_private
*dev_priv
);
1643 void intel_update_rawclk(struct drm_i915_private
*dev_priv
);
1644 bool intel_cdclk_needs_cd2x_update(struct drm_i915_private
*dev_priv
,
1645 const struct intel_cdclk_state
*a
,
1646 const struct intel_cdclk_state
*b
);
1647 bool intel_cdclk_needs_modeset(const struct intel_cdclk_state
*a
,
1648 const struct intel_cdclk_state
*b
);
1649 bool intel_cdclk_changed(const struct intel_cdclk_state
*a
,
1650 const struct intel_cdclk_state
*b
);
1651 void intel_cdclk_swap_state(struct intel_atomic_state
*state
);
1653 intel_set_cdclk_pre_plane_update(struct drm_i915_private
*dev_priv
,
1654 const struct intel_cdclk_state
*old_state
,
1655 const struct intel_cdclk_state
*new_state
,
1658 intel_set_cdclk_post_plane_update(struct drm_i915_private
*dev_priv
,
1659 const struct intel_cdclk_state
*old_state
,
1660 const struct intel_cdclk_state
*new_state
,
1662 void intel_dump_cdclk_state(const struct intel_cdclk_state
*cdclk_state
,
1663 const char *context
);
1665 /* intel_display.c */
1666 void i830_enable_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
);
1667 void i830_disable_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
);
1668 enum pipe
intel_crtc_pch_transcoder(struct intel_crtc
*crtc
);
1669 int vlv_get_hpll_vco(struct drm_i915_private
*dev_priv
);
1670 int vlv_get_cck_clock(struct drm_i915_private
*dev_priv
,
1671 const char *name
, u32 reg
, int ref_freq
);
1672 int vlv_get_cck_clock_hpll(struct drm_i915_private
*dev_priv
,
1673 const char *name
, u32 reg
);
1674 void lpt_disable_pch_transcoder(struct drm_i915_private
*dev_priv
);
1675 void lpt_disable_iclkip(struct drm_i915_private
*dev_priv
);
1676 void intel_init_display_hooks(struct drm_i915_private
*dev_priv
);
1677 unsigned int intel_fb_xy_to_linear(int x
, int y
,
1678 const struct intel_plane_state
*state
,
1680 unsigned int intel_fb_align_height(const struct drm_framebuffer
*fb
,
1681 int color_plane
, unsigned int height
);
1682 void intel_add_fb_offsets(int *x
, int *y
,
1683 const struct intel_plane_state
*state
, int plane
);
1684 unsigned int intel_rotation_info_size(const struct intel_rotation_info
*rot_info
);
1685 bool intel_has_pending_fb_unpin(struct drm_i915_private
*dev_priv
);
1686 void intel_mark_busy(struct drm_i915_private
*dev_priv
);
1687 void intel_mark_idle(struct drm_i915_private
*dev_priv
);
1688 int intel_display_suspend(struct drm_device
*dev
);
1689 void intel_pps_unlock_regs_wa(struct drm_i915_private
*dev_priv
);
1690 void intel_encoder_destroy(struct drm_encoder
*encoder
);
1691 struct drm_display_mode
*
1692 intel_encoder_current_mode(struct intel_encoder
*encoder
);
1693 bool intel_port_is_combophy(struct drm_i915_private
*dev_priv
, enum port port
);
1694 bool intel_port_is_tc(struct drm_i915_private
*dev_priv
, enum port port
);
1695 enum tc_port
intel_port_to_tc(struct drm_i915_private
*dev_priv
,
1697 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device
*dev
, void *data
,
1698 struct drm_file
*file_priv
);
1699 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
1702 intel_crtc_has_type(const struct intel_crtc_state
*crtc_state
,
1703 enum intel_output_type type
)
1705 return crtc_state
->output_types
& (1 << type
);
1708 intel_crtc_has_dp_encoder(const struct intel_crtc_state
*crtc_state
)
1710 return crtc_state
->output_types
&
1711 ((1 << INTEL_OUTPUT_DP
) |
1712 (1 << INTEL_OUTPUT_DP_MST
) |
1713 (1 << INTEL_OUTPUT_EDP
));
1716 intel_wait_for_vblank(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1718 drm_wait_one_vblank(&dev_priv
->drm
, pipe
);
1721 intel_wait_for_vblank_if_active(struct drm_i915_private
*dev_priv
, int pipe
)
1723 const struct intel_crtc
*crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
1726 intel_wait_for_vblank(dev_priv
, pipe
);
1729 u32
intel_crtc_get_vblank_counter(struct intel_crtc
*crtc
);
1731 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
);
1732 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
,
1733 struct intel_digital_port
*dport
,
1734 unsigned int expected_mask
);
1735 int intel_get_load_detect_pipe(struct drm_connector
*connector
,
1736 const struct drm_display_mode
*mode
,
1737 struct intel_load_detect_pipe
*old
,
1738 struct drm_modeset_acquire_ctx
*ctx
);
1739 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
1740 struct intel_load_detect_pipe
*old
,
1741 struct drm_modeset_acquire_ctx
*ctx
);
1743 intel_pin_and_fence_fb_obj(struct drm_framebuffer
*fb
,
1744 const struct i915_ggtt_view
*view
,
1746 unsigned long *out_flags
);
1747 void intel_unpin_fb_vma(struct i915_vma
*vma
, unsigned long flags
);
1748 struct drm_framebuffer
*
1749 intel_framebuffer_create(struct drm_i915_gem_object
*obj
,
1750 struct drm_mode_fb_cmd2
*mode_cmd
);
1751 int intel_prepare_plane_fb(struct drm_plane
*plane
,
1752 struct drm_plane_state
*new_state
);
1753 void intel_cleanup_plane_fb(struct drm_plane
*plane
,
1754 struct drm_plane_state
*old_state
);
1755 int intel_plane_atomic_get_property(struct drm_plane
*plane
,
1756 const struct drm_plane_state
*state
,
1757 struct drm_property
*property
,
1759 int intel_plane_atomic_set_property(struct drm_plane
*plane
,
1760 struct drm_plane_state
*state
,
1761 struct drm_property
*property
,
1763 int intel_plane_atomic_calc_changes(const struct intel_crtc_state
*old_crtc_state
,
1764 struct drm_crtc_state
*crtc_state
,
1765 const struct intel_plane_state
*old_plane_state
,
1766 struct drm_plane_state
*plane_state
);
1768 void assert_pch_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1771 int vlv_force_pll_on(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
1772 const struct dpll
*dpll
);
1773 void vlv_force_pll_off(struct drm_i915_private
*dev_priv
, enum pipe pipe
);
1774 int lpt_get_iclkip(struct drm_i915_private
*dev_priv
);
1776 /* modesetting asserts */
1777 void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1779 void assert_pll(struct drm_i915_private
*dev_priv
,
1780 enum pipe pipe
, bool state
);
1781 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1782 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1783 void assert_dsi_pll(struct drm_i915_private
*dev_priv
, bool state
);
1784 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1785 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1786 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
1787 enum pipe pipe
, bool state
);
1788 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1789 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1790 void assert_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
, bool state
);
1791 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1792 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1793 void intel_prepare_reset(struct drm_i915_private
*dev_priv
);
1794 void intel_finish_reset(struct drm_i915_private
*dev_priv
);
1795 void hsw_enable_pc8(struct drm_i915_private
*dev_priv
);
1796 void hsw_disable_pc8(struct drm_i915_private
*dev_priv
);
1797 void gen9_sanitize_dc_state(struct drm_i915_private
*dev_priv
);
1798 void bxt_enable_dc9(struct drm_i915_private
*dev_priv
);
1799 void bxt_disable_dc9(struct drm_i915_private
*dev_priv
);
1800 void gen9_enable_dc5(struct drm_i915_private
*dev_priv
);
1801 unsigned int skl_cdclk_get_vco(unsigned int freq
);
1802 void skl_enable_dc6(struct drm_i915_private
*dev_priv
);
1803 void intel_dp_get_m_n(struct intel_crtc
*crtc
,
1804 struct intel_crtc_state
*pipe_config
);
1805 void intel_dp_set_m_n(const struct intel_crtc_state
*crtc_state
,
1806 enum link_m_n_set m_n
);
1807 int intel_dotclock_calculate(int link_freq
, const struct intel_link_m_n
*m_n
);
1808 bool bxt_find_best_dpll(struct intel_crtc_state
*crtc_state
,
1809 struct dpll
*best_clock
);
1810 int chv_calc_dpll_params(int refclk
, struct dpll
*pll_clock
);
1812 bool intel_crtc_active(struct intel_crtc
*crtc
);
1813 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state
*crtc_state
);
1814 void hsw_enable_ips(const struct intel_crtc_state
*crtc_state
);
1815 void hsw_disable_ips(const struct intel_crtc_state
*crtc_state
);
1816 enum intel_display_power_domain
intel_port_to_power_domain(enum port port
);
1817 enum intel_display_power_domain
1818 intel_aux_power_domain(struct intel_digital_port
*dig_port
);
1819 void intel_mode_from_pipe_config(struct drm_display_mode
*mode
,
1820 struct intel_crtc_state
*pipe_config
);
1821 void intel_crtc_arm_fifo_underrun(struct intel_crtc
*crtc
,
1822 struct intel_crtc_state
*crtc_state
);
1824 u16
skl_scaler_calc_phase(int sub
, int scale
, bool chroma_center
);
1825 int skl_update_scaler_crtc(struct intel_crtc_state
*crtc_state
);
1826 int skl_max_scale(const struct intel_crtc_state
*crtc_state
,
1829 static inline u32
intel_plane_ggtt_offset(const struct intel_plane_state
*state
)
1831 return i915_ggtt_offset(state
->vma
);
1834 u32
glk_plane_color_ctl(const struct intel_crtc_state
*crtc_state
,
1835 const struct intel_plane_state
*plane_state
);
1836 u32
glk_plane_color_ctl_crtc(const struct intel_crtc_state
*crtc_state
);
1837 u32
skl_plane_ctl(const struct intel_crtc_state
*crtc_state
,
1838 const struct intel_plane_state
*plane_state
);
1839 u32
skl_plane_ctl_crtc(const struct intel_crtc_state
*crtc_state
);
1840 u32
skl_plane_stride(const struct intel_plane_state
*plane_state
,
1842 int skl_check_plane_surface(struct intel_plane_state
*plane_state
);
1843 int i9xx_check_plane_surface(struct intel_plane_state
*plane_state
);
1844 int skl_format_to_fourcc(int format
, bool rgb_order
, bool alpha
);
1845 unsigned int i9xx_plane_max_stride(struct intel_plane
*plane
,
1846 u32 pixel_format
, u64 modifier
,
1847 unsigned int rotation
);
1850 void intel_csr_ucode_init(struct drm_i915_private
*);
1851 void intel_csr_load_program(struct drm_i915_private
*);
1852 void intel_csr_ucode_fini(struct drm_i915_private
*);
1853 void intel_csr_ucode_suspend(struct drm_i915_private
*);
1854 void intel_csr_ucode_resume(struct drm_i915_private
*);
1857 struct link_config_limits
{
1858 int min_clock
, max_clock
;
1859 int min_lane_count
, max_lane_count
;
1860 int min_bpp
, max_bpp
;
1862 void intel_dp_adjust_compliance_config(struct intel_dp
*intel_dp
,
1863 struct intel_crtc_state
*pipe_config
,
1864 struct link_config_limits
*limits
);
1865 bool intel_dp_limited_color_range(const struct intel_crtc_state
*crtc_state
,
1866 const struct drm_connector_state
*conn_state
);
1867 bool intel_dp_port_enabled(struct drm_i915_private
*dev_priv
,
1868 i915_reg_t dp_reg
, enum port port
,
1870 bool intel_dp_init(struct drm_i915_private
*dev_priv
, i915_reg_t output_reg
,
1872 bool intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
1873 struct intel_connector
*intel_connector
);
1874 void intel_dp_set_link_params(struct intel_dp
*intel_dp
,
1875 int link_rate
, u8 lane_count
,
1877 int intel_dp_get_link_train_fallback_values(struct intel_dp
*intel_dp
,
1878 int link_rate
, u8 lane_count
);
1879 void intel_dp_start_link_train(struct intel_dp
*intel_dp
);
1880 void intel_dp_stop_link_train(struct intel_dp
*intel_dp
);
1881 int intel_dp_retrain_link(struct intel_encoder
*encoder
,
1882 struct drm_modeset_acquire_ctx
*ctx
);
1883 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
);
1884 void intel_dp_sink_set_decompression_state(struct intel_dp
*intel_dp
,
1885 const struct intel_crtc_state
*crtc_state
,
1887 void intel_dp_encoder_reset(struct drm_encoder
*encoder
);
1888 void intel_dp_encoder_suspend(struct intel_encoder
*intel_encoder
);
1889 void intel_dp_encoder_flush_work(struct drm_encoder
*encoder
);
1890 int intel_dp_compute_config(struct intel_encoder
*encoder
,
1891 struct intel_crtc_state
*pipe_config
,
1892 struct drm_connector_state
*conn_state
);
1893 bool intel_dp_is_edp(struct intel_dp
*intel_dp
);
1894 bool intel_dp_is_port_edp(struct drm_i915_private
*dev_priv
, enum port port
);
1895 enum irqreturn
intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port
,
1897 void intel_edp_backlight_on(const struct intel_crtc_state
*crtc_state
,
1898 const struct drm_connector_state
*conn_state
);
1899 void intel_edp_backlight_off(const struct drm_connector_state
*conn_state
);
1900 void intel_edp_panel_vdd_on(struct intel_dp
*intel_dp
);
1901 void intel_edp_panel_on(struct intel_dp
*intel_dp
);
1902 void intel_edp_panel_off(struct intel_dp
*intel_dp
);
1903 void intel_dp_mst_suspend(struct drm_i915_private
*dev_priv
);
1904 void intel_dp_mst_resume(struct drm_i915_private
*dev_priv
);
1905 int intel_dp_max_link_rate(struct intel_dp
*intel_dp
);
1906 int intel_dp_max_lane_count(struct intel_dp
*intel_dp
);
1907 int intel_dp_rate_select(struct intel_dp
*intel_dp
, int rate
);
1908 void intel_dp_hot_plug(struct intel_encoder
*intel_encoder
);
1909 void intel_power_sequencer_reset(struct drm_i915_private
*dev_priv
);
1910 u32
intel_dp_pack_aux(const u8
*src
, int src_bytes
);
1911 void intel_plane_destroy(struct drm_plane
*plane
);
1912 void intel_edp_drrs_enable(struct intel_dp
*intel_dp
,
1913 const struct intel_crtc_state
*crtc_state
);
1914 void intel_edp_drrs_disable(struct intel_dp
*intel_dp
,
1915 const struct intel_crtc_state
*crtc_state
);
1916 void intel_edp_drrs_invalidate(struct drm_i915_private
*dev_priv
,
1917 unsigned int frontbuffer_bits
);
1918 void intel_edp_drrs_flush(struct drm_i915_private
*dev_priv
,
1919 unsigned int frontbuffer_bits
);
1922 intel_dp_program_link_training_pattern(struct intel_dp
*intel_dp
,
1925 intel_dp_set_signal_levels(struct intel_dp
*intel_dp
);
1926 void intel_dp_set_idle_link_train(struct intel_dp
*intel_dp
);
1928 intel_dp_voltage_max(struct intel_dp
*intel_dp
);
1930 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, u8 voltage_swing
);
1931 void intel_dp_compute_rate(struct intel_dp
*intel_dp
, int port_clock
,
1932 u8
*link_bw
, u8
*rate_select
);
1933 bool intel_dp_source_supports_hbr2(struct intel_dp
*intel_dp
);
1934 bool intel_dp_source_supports_hbr3(struct intel_dp
*intel_dp
);
1936 intel_dp_get_link_status(struct intel_dp
*intel_dp
, u8 link_status
[DP_LINK_STATUS_SIZE
]);
1937 u16
intel_dp_dsc_get_output_bpp(int link_clock
, u8 lane_count
,
1938 int mode_clock
, int mode_hdisplay
);
1939 u8
intel_dp_dsc_get_slice_count(struct intel_dp
*intel_dp
, int mode_clock
,
1943 int intel_dp_compute_dsc_params(struct intel_dp
*intel_dp
,
1944 struct intel_crtc_state
*pipe_config
);
1945 enum intel_display_power_domain
1946 intel_dsc_power_domain(const struct intel_crtc_state
*crtc_state
);
1948 static inline unsigned int intel_dp_unused_lane_mask(int lane_count
)
1950 return ~((1 << lane_count
) - 1) & 0xf;
1953 bool intel_dp_read_dpcd(struct intel_dp
*intel_dp
);
1954 int intel_dp_link_required(int pixel_clock
, int bpp
);
1955 int intel_dp_max_data_rate(int max_link_clock
, int max_lanes
);
1956 bool intel_digital_port_connected(struct intel_encoder
*encoder
);
1957 void icl_tc_phy_disconnect(struct drm_i915_private
*dev_priv
,
1958 struct intel_digital_port
*dig_port
);
1960 /* intel_dp_aux_backlight.c */
1961 int intel_dp_aux_init_backlight_funcs(struct intel_connector
*intel_connector
);
1963 /* intel_dp_mst.c */
1964 int intel_dp_mst_encoder_init(struct intel_digital_port
*intel_dig_port
, int conn_id
);
1965 void intel_dp_mst_encoder_cleanup(struct intel_digital_port
*intel_dig_port
);
1967 void vlv_dsi_init(struct drm_i915_private
*dev_priv
);
1970 void icl_dsi_init(struct drm_i915_private
*dev_priv
);
1972 /* intel_dsi_dcs_backlight.c */
1973 int intel_dsi_dcs_init_backlight_funcs(struct intel_connector
*intel_connector
);
1976 void intel_dvo_init(struct drm_i915_private
*dev_priv
);
1977 /* intel_hotplug.c */
1978 void intel_hpd_poll_init(struct drm_i915_private
*dev_priv
);
1979 bool intel_encoder_hotplug(struct intel_encoder
*encoder
,
1980 struct intel_connector
*connector
);
1982 /* legacy fbdev emulation in intel_fbdev.c */
1983 #ifdef CONFIG_DRM_FBDEV_EMULATION
1984 extern int intel_fbdev_init(struct drm_device
*dev
);
1985 extern void intel_fbdev_initial_config_async(struct drm_device
*dev
);
1986 extern void intel_fbdev_unregister(struct drm_i915_private
*dev_priv
);
1987 extern void intel_fbdev_fini(struct drm_i915_private
*dev_priv
);
1988 extern void intel_fbdev_set_suspend(struct drm_device
*dev
, int state
, bool synchronous
);
1989 extern void intel_fbdev_output_poll_changed(struct drm_device
*dev
);
1990 extern void intel_fbdev_restore_mode(struct drm_device
*dev
);
1992 static inline int intel_fbdev_init(struct drm_device
*dev
)
1997 static inline void intel_fbdev_initial_config_async(struct drm_device
*dev
)
2001 static inline void intel_fbdev_unregister(struct drm_i915_private
*dev_priv
)
2005 static inline void intel_fbdev_fini(struct drm_i915_private
*dev_priv
)
2009 static inline void intel_fbdev_set_suspend(struct drm_device
*dev
, int state
, bool synchronous
)
2013 static inline void intel_fbdev_output_poll_changed(struct drm_device
*dev
)
2017 static inline void intel_fbdev_restore_mode(struct drm_device
*dev
)
2023 void intel_fbc_choose_crtc(struct drm_i915_private
*dev_priv
,
2024 struct intel_atomic_state
*state
);
2025 bool intel_fbc_is_active(struct drm_i915_private
*dev_priv
);
2026 void intel_fbc_pre_update(struct intel_crtc
*crtc
,
2027 struct intel_crtc_state
*crtc_state
,
2028 struct intel_plane_state
*plane_state
);
2029 void intel_fbc_post_update(struct intel_crtc
*crtc
);
2030 void intel_fbc_init(struct drm_i915_private
*dev_priv
);
2031 void intel_fbc_init_pipe_state(struct drm_i915_private
*dev_priv
);
2032 void intel_fbc_enable(struct intel_crtc
*crtc
,
2033 struct intel_crtc_state
*crtc_state
,
2034 struct intel_plane_state
*plane_state
);
2035 void intel_fbc_disable(struct intel_crtc
*crtc
);
2036 void intel_fbc_global_disable(struct drm_i915_private
*dev_priv
);
2037 void intel_fbc_invalidate(struct drm_i915_private
*dev_priv
,
2038 unsigned int frontbuffer_bits
,
2039 enum fb_op_origin origin
);
2040 void intel_fbc_flush(struct drm_i915_private
*dev_priv
,
2041 unsigned int frontbuffer_bits
, enum fb_op_origin origin
);
2042 void intel_fbc_cleanup_cfb(struct drm_i915_private
*dev_priv
);
2043 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private
*dev_priv
);
2044 int intel_fbc_reset_underrun(struct drm_i915_private
*dev_priv
);
2047 void intel_hdmi_init(struct drm_i915_private
*dev_priv
, i915_reg_t hdmi_reg
,
2049 void intel_hdmi_init_connector(struct intel_digital_port
*intel_dig_port
,
2050 struct intel_connector
*intel_connector
);
2051 struct intel_hdmi
*enc_to_intel_hdmi(struct drm_encoder
*encoder
);
2052 int intel_hdmi_compute_config(struct intel_encoder
*encoder
,
2053 struct intel_crtc_state
*pipe_config
,
2054 struct drm_connector_state
*conn_state
);
2055 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder
*encoder
,
2056 struct drm_connector
*connector
,
2057 bool high_tmds_clock_ratio
,
2059 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi
*hdmi
, bool enable
);
2060 void intel_infoframe_init(struct intel_digital_port
*intel_dig_port
);
2061 u32
intel_hdmi_infoframes_enabled(struct intel_encoder
*encoder
,
2062 const struct intel_crtc_state
*crtc_state
);
2063 u32
intel_hdmi_infoframe_enable(unsigned int type
);
2064 void intel_hdmi_read_gcp_infoframe(struct intel_encoder
*encoder
,
2065 struct intel_crtc_state
*crtc_state
);
2066 void intel_read_infoframe(struct intel_encoder
*encoder
,
2067 const struct intel_crtc_state
*crtc_state
,
2068 enum hdmi_infoframe_type type
,
2069 union hdmi_infoframe
*frame
);
2072 bool intel_lvds_port_enabled(struct drm_i915_private
*dev_priv
,
2073 i915_reg_t lvds_reg
, enum pipe
*pipe
);
2074 void intel_lvds_init(struct drm_i915_private
*dev_priv
);
2075 struct intel_encoder
*intel_get_lvds_encoder(struct drm_i915_private
*dev_priv
);
2076 bool intel_is_dual_link_lvds(struct drm_i915_private
*dev_priv
);
2078 /* intel_overlay.c */
2079 void intel_overlay_setup(struct drm_i915_private
*dev_priv
);
2080 void intel_overlay_cleanup(struct drm_i915_private
*dev_priv
);
2081 int intel_overlay_switch_off(struct intel_overlay
*overlay
);
2082 int intel_overlay_put_image_ioctl(struct drm_device
*dev
, void *data
,
2083 struct drm_file
*file_priv
);
2084 int intel_overlay_attrs_ioctl(struct drm_device
*dev
, void *data
,
2085 struct drm_file
*file_priv
);
2086 void intel_overlay_reset(struct drm_i915_private
*dev_priv
);
2090 int intel_panel_init(struct intel_panel
*panel
,
2091 struct drm_display_mode
*fixed_mode
,
2092 struct drm_display_mode
*downclock_mode
);
2093 void intel_panel_fini(struct intel_panel
*panel
);
2094 void intel_fixed_panel_mode(const struct drm_display_mode
*fixed_mode
,
2095 struct drm_display_mode
*adjusted_mode
);
2096 void intel_pch_panel_fitting(struct intel_crtc
*crtc
,
2097 struct intel_crtc_state
*pipe_config
,
2099 void intel_gmch_panel_fitting(struct intel_crtc
*crtc
,
2100 struct intel_crtc_state
*pipe_config
,
2102 void intel_panel_set_backlight_acpi(const struct drm_connector_state
*conn_state
,
2103 u32 level
, u32 max
);
2104 int intel_panel_setup_backlight(struct drm_connector
*connector
,
2106 void intel_panel_enable_backlight(const struct intel_crtc_state
*crtc_state
,
2107 const struct drm_connector_state
*conn_state
);
2108 void intel_panel_update_backlight(struct intel_encoder
*encoder
,
2109 const struct intel_crtc_state
*crtc_state
,
2110 const struct drm_connector_state
*conn_state
);
2111 void intel_panel_disable_backlight(const struct drm_connector_state
*old_conn_state
);
2112 struct drm_display_mode
*
2113 intel_panel_edid_downclock_mode(struct intel_connector
*connector
,
2114 const struct drm_display_mode
*fixed_mode
);
2115 struct drm_display_mode
*
2116 intel_panel_edid_fixed_mode(struct intel_connector
*connector
);
2117 struct drm_display_mode
*
2118 intel_panel_vbt_fixed_mode(struct intel_connector
*connector
);
2120 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
2121 int intel_backlight_device_register(struct intel_connector
*connector
);
2122 void intel_backlight_device_unregister(struct intel_connector
*connector
);
2123 #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
2124 static inline int intel_backlight_device_register(struct intel_connector
*connector
)
2128 static inline void intel_backlight_device_unregister(struct intel_connector
*connector
)
2131 #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
2134 void intel_hdcp_atomic_check(struct drm_connector
*connector
,
2135 struct drm_connector_state
*old_state
,
2136 struct drm_connector_state
*new_state
);
2137 int intel_hdcp_init(struct intel_connector
*connector
,
2138 const struct intel_hdcp_shim
*hdcp_shim
);
2139 int intel_hdcp_enable(struct intel_connector
*connector
);
2140 int intel_hdcp_disable(struct intel_connector
*connector
);
2141 bool is_hdcp_supported(struct drm_i915_private
*dev_priv
, enum port port
);
2142 bool intel_hdcp_capable(struct intel_connector
*connector
);
2143 void intel_hdcp_component_init(struct drm_i915_private
*dev_priv
);
2144 void intel_hdcp_component_fini(struct drm_i915_private
*dev_priv
);
2145 void intel_hdcp_cleanup(struct intel_connector
*connector
);
2146 void intel_hdcp_handle_cp_irq(struct intel_connector
*connector
);
2149 #define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv->psr.sink_support)
2150 void intel_psr_init_dpcd(struct intel_dp
*intel_dp
);
2151 void intel_psr_enable(struct intel_dp
*intel_dp
,
2152 const struct intel_crtc_state
*crtc_state
);
2153 void intel_psr_disable(struct intel_dp
*intel_dp
,
2154 const struct intel_crtc_state
*old_crtc_state
);
2155 void intel_psr_update(struct intel_dp
*intel_dp
,
2156 const struct intel_crtc_state
*crtc_state
);
2157 int intel_psr_debug_set(struct drm_i915_private
*dev_priv
, u64 value
);
2158 void intel_psr_invalidate(struct drm_i915_private
*dev_priv
,
2159 unsigned frontbuffer_bits
,
2160 enum fb_op_origin origin
);
2161 void intel_psr_flush(struct drm_i915_private
*dev_priv
,
2162 unsigned frontbuffer_bits
,
2163 enum fb_op_origin origin
);
2164 void intel_psr_init(struct drm_i915_private
*dev_priv
);
2165 void intel_psr_compute_config(struct intel_dp
*intel_dp
,
2166 struct intel_crtc_state
*crtc_state
);
2167 void intel_psr_irq_control(struct drm_i915_private
*dev_priv
, u32 debug
);
2168 void intel_psr_irq_handler(struct drm_i915_private
*dev_priv
, u32 psr_iir
);
2169 void intel_psr_short_pulse(struct intel_dp
*intel_dp
);
2170 int intel_psr_wait_for_idle(const struct intel_crtc_state
*new_crtc_state
,
2172 bool intel_psr_enabled(struct intel_dp
*intel_dp
);
2174 /* intel_quirks.c */
2175 void intel_init_quirks(struct drm_i915_private
*dev_priv
);
2177 /* intel_runtime_pm.c */
2178 void intel_runtime_pm_init_early(struct drm_i915_private
*dev_priv
);
2179 int intel_power_domains_init(struct drm_i915_private
*);
2180 void intel_power_domains_cleanup(struct drm_i915_private
*dev_priv
);
2181 void intel_power_domains_init_hw(struct drm_i915_private
*dev_priv
, bool resume
);
2182 void intel_power_domains_fini_hw(struct drm_i915_private
*dev_priv
);
2183 void icl_display_core_init(struct drm_i915_private
*dev_priv
, bool resume
);
2184 void icl_display_core_uninit(struct drm_i915_private
*dev_priv
);
2185 void intel_power_domains_enable(struct drm_i915_private
*dev_priv
);
2186 void intel_power_domains_disable(struct drm_i915_private
*dev_priv
);
2188 enum i915_drm_suspend_mode
{
2189 I915_DRM_SUSPEND_IDLE
,
2190 I915_DRM_SUSPEND_MEM
,
2191 I915_DRM_SUSPEND_HIBERNATE
,
2194 void intel_power_domains_suspend(struct drm_i915_private
*dev_priv
,
2195 enum i915_drm_suspend_mode
);
2196 void intel_power_domains_resume(struct drm_i915_private
*dev_priv
);
2197 void bxt_display_core_init(struct drm_i915_private
*dev_priv
, bool resume
);
2198 void bxt_display_core_uninit(struct drm_i915_private
*dev_priv
);
2199 void intel_runtime_pm_enable(struct drm_i915_private
*dev_priv
);
2200 void intel_runtime_pm_disable(struct drm_i915_private
*dev_priv
);
2201 void intel_runtime_pm_cleanup(struct drm_i915_private
*dev_priv
);
2203 intel_display_power_domain_str(enum intel_display_power_domain domain
);
2205 bool intel_display_power_is_enabled(struct drm_i915_private
*dev_priv
,
2206 enum intel_display_power_domain domain
);
2207 bool __intel_display_power_is_enabled(struct drm_i915_private
*dev_priv
,
2208 enum intel_display_power_domain domain
);
2209 intel_wakeref_t
intel_display_power_get(struct drm_i915_private
*dev_priv
,
2210 enum intel_display_power_domain domain
);
2212 intel_display_power_get_if_enabled(struct drm_i915_private
*dev_priv
,
2213 enum intel_display_power_domain domain
);
2214 void intel_display_power_put_unchecked(struct drm_i915_private
*dev_priv
,
2215 enum intel_display_power_domain domain
);
2216 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
2217 void intel_display_power_put(struct drm_i915_private
*dev_priv
,
2218 enum intel_display_power_domain domain
,
2219 intel_wakeref_t wakeref
);
2221 #define intel_display_power_put(i915, domain, wakeref) \
2222 intel_display_power_put_unchecked(i915, domain)
2224 void icl_dbuf_slices_update(struct drm_i915_private
*dev_priv
,
2228 assert_rpm_device_not_suspended(struct i915_runtime_pm
*rpm
)
2230 WARN_ONCE(rpm
->suspended
,
2231 "Device suspended during HW access\n");
2235 __assert_rpm_wakelock_held(struct i915_runtime_pm
*rpm
)
2237 assert_rpm_device_not_suspended(rpm
);
2238 WARN_ONCE(!atomic_read(&rpm
->wakeref_count
),
2239 "RPM wakelock ref not held during HW access");
2243 assert_rpm_wakelock_held(struct drm_i915_private
*i915
)
2245 __assert_rpm_wakelock_held(&i915
->runtime_pm
);
2249 * disable_rpm_wakeref_asserts - disable the RPM assert checks
2250 * @i915: i915 device instance
2252 * This function disable asserts that check if we hold an RPM wakelock
2253 * reference, while keeping the device-not-suspended checks still enabled.
2254 * It's meant to be used only in special circumstances where our rule about
2255 * the wakelock refcount wrt. the device power state doesn't hold. According
2256 * to this rule at any point where we access the HW or want to keep the HW in
2257 * an active state we must hold an RPM wakelock reference acquired via one of
2258 * the intel_runtime_pm_get() helpers. Currently there are a few special spots
2259 * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
2260 * forcewake release timer, and the GPU RPS and hangcheck works. All other
2261 * users should avoid using this function.
2263 * Any calls to this function must have a symmetric call to
2264 * enable_rpm_wakeref_asserts().
2267 disable_rpm_wakeref_asserts(struct drm_i915_private
*i915
)
2269 atomic_inc(&i915
->runtime_pm
.wakeref_count
);
2273 * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
2274 * @i915: i915 device instance
2276 * This function re-enables the RPM assert checks after disabling them with
2277 * disable_rpm_wakeref_asserts. It's meant to be used only in special
2278 * circumstances otherwise its use should be avoided.
2280 * Any calls to this function must have a symmetric call to
2281 * disable_rpm_wakeref_asserts().
2284 enable_rpm_wakeref_asserts(struct drm_i915_private
*i915
)
2286 atomic_dec(&i915
->runtime_pm
.wakeref_count
);
2289 intel_wakeref_t
intel_runtime_pm_get(struct drm_i915_private
*i915
);
2290 intel_wakeref_t
intel_runtime_pm_get_if_in_use(struct drm_i915_private
*i915
);
2291 intel_wakeref_t
intel_runtime_pm_get_noresume(struct drm_i915_private
*i915
);
2293 #define with_intel_runtime_pm(i915, wf) \
2294 for ((wf) = intel_runtime_pm_get(i915); (wf); \
2295 intel_runtime_pm_put((i915), (wf)), (wf) = 0)
2297 #define with_intel_runtime_pm_if_in_use(i915, wf) \
2298 for ((wf) = intel_runtime_pm_get_if_in_use(i915); (wf); \
2299 intel_runtime_pm_put((i915), (wf)), (wf) = 0)
2301 void intel_runtime_pm_put_unchecked(struct drm_i915_private
*i915
);
2302 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
2303 void intel_runtime_pm_put(struct drm_i915_private
*i915
, intel_wakeref_t wref
);
2305 #define intel_runtime_pm_put(i915, wref) intel_runtime_pm_put_unchecked(i915)
2308 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
2309 void print_intel_runtime_pm_wakeref(struct drm_i915_private
*i915
,
2310 struct drm_printer
*p
);
2312 static inline void print_intel_runtime_pm_wakeref(struct drm_i915_private
*i915
,
2313 struct drm_printer
*p
)
2318 void chv_phy_powergate_lanes(struct intel_encoder
*encoder
,
2319 bool override
, unsigned int mask
);
2320 bool chv_phy_powergate_ch(struct drm_i915_private
*dev_priv
, enum dpio_phy phy
,
2321 enum dpio_channel ch
, bool override
);
2325 void intel_init_clock_gating(struct drm_i915_private
*dev_priv
);
2326 void intel_suspend_hw(struct drm_i915_private
*dev_priv
);
2327 int ilk_wm_max_level(const struct drm_i915_private
*dev_priv
);
2328 void intel_update_watermarks(struct intel_crtc
*crtc
);
2329 void intel_init_pm(struct drm_i915_private
*dev_priv
);
2330 void intel_init_clock_gating_hooks(struct drm_i915_private
*dev_priv
);
2331 void intel_pm_setup(struct drm_i915_private
*dev_priv
);
2332 void intel_gpu_ips_init(struct drm_i915_private
*dev_priv
);
2333 void intel_gpu_ips_teardown(void);
2334 void intel_init_gt_powersave(struct drm_i915_private
*dev_priv
);
2335 void intel_cleanup_gt_powersave(struct drm_i915_private
*dev_priv
);
2336 void intel_sanitize_gt_powersave(struct drm_i915_private
*dev_priv
);
2337 void intel_enable_gt_powersave(struct drm_i915_private
*dev_priv
);
2338 void intel_disable_gt_powersave(struct drm_i915_private
*dev_priv
);
2339 void gen6_rps_busy(struct drm_i915_private
*dev_priv
);
2340 void gen6_rps_reset_ei(struct drm_i915_private
*dev_priv
);
2341 void gen6_rps_idle(struct drm_i915_private
*dev_priv
);
2342 void gen6_rps_boost(struct i915_request
*rq
);
2343 void g4x_wm_get_hw_state(struct drm_i915_private
*dev_priv
);
2344 void vlv_wm_get_hw_state(struct drm_i915_private
*dev_priv
);
2345 void ilk_wm_get_hw_state(struct drm_i915_private
*dev_priv
);
2346 void skl_wm_get_hw_state(struct drm_i915_private
*dev_priv
);
2347 void skl_pipe_ddb_get_hw_state(struct intel_crtc
*crtc
,
2348 struct skl_ddb_entry
*ddb_y
,
2349 struct skl_ddb_entry
*ddb_uv
);
2350 void skl_ddb_get_hw_state(struct drm_i915_private
*dev_priv
,
2351 struct skl_ddb_allocation
*ddb
/* out */);
2352 void skl_pipe_wm_get_hw_state(struct intel_crtc
*crtc
,
2353 struct skl_pipe_wm
*out
);
2354 void g4x_wm_sanitize(struct drm_i915_private
*dev_priv
);
2355 void vlv_wm_sanitize(struct drm_i915_private
*dev_priv
);
2356 bool intel_can_enable_sagv(struct drm_atomic_state
*state
);
2357 int intel_enable_sagv(struct drm_i915_private
*dev_priv
);
2358 int intel_disable_sagv(struct drm_i915_private
*dev_priv
);
2359 bool skl_wm_level_equals(const struct skl_wm_level
*l1
,
2360 const struct skl_wm_level
*l2
);
2361 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry
*ddb
,
2362 const struct skl_ddb_entry entries
[],
2363 int num_entries
, int ignore_idx
);
2364 void skl_write_plane_wm(struct intel_plane
*plane
,
2365 const struct intel_crtc_state
*crtc_state
);
2366 void skl_write_cursor_wm(struct intel_plane
*plane
,
2367 const struct intel_crtc_state
*crtc_state
);
2368 bool ilk_disable_lp_wm(struct drm_device
*dev
);
2369 int skl_check_pipe_max_pixel_rate(struct intel_crtc
*intel_crtc
,
2370 struct intel_crtc_state
*cstate
);
2371 void intel_init_ipc(struct drm_i915_private
*dev_priv
);
2372 void intel_enable_ipc(struct drm_i915_private
*dev_priv
);
2375 bool intel_sdvo_port_enabled(struct drm_i915_private
*dev_priv
,
2376 i915_reg_t sdvo_reg
, enum pipe
*pipe
);
2377 bool intel_sdvo_init(struct drm_i915_private
*dev_priv
,
2378 i915_reg_t reg
, enum port port
);
2381 /* intel_sprite.c */
2382 bool is_planar_yuv_format(u32 pixelformat
);
2383 int intel_usecs_to_scanlines(const struct drm_display_mode
*adjusted_mode
,
2385 struct intel_plane
*intel_sprite_plane_create(struct drm_i915_private
*dev_priv
,
2386 enum pipe pipe
, int plane
);
2387 int intel_sprite_set_colorkey_ioctl(struct drm_device
*dev
, void *data
,
2388 struct drm_file
*file_priv
);
2389 void intel_pipe_update_start(const struct intel_crtc_state
*new_crtc_state
);
2390 void intel_pipe_update_end(struct intel_crtc_state
*new_crtc_state
);
2391 int intel_plane_check_stride(const struct intel_plane_state
*plane_state
);
2392 int intel_plane_check_src_coordinates(struct intel_plane_state
*plane_state
);
2393 int chv_plane_check_rotation(const struct intel_plane_state
*plane_state
);
2394 struct intel_plane
*
2395 skl_universal_plane_create(struct drm_i915_private
*dev_priv
,
2396 enum pipe pipe
, enum plane_id plane_id
);
2398 static inline bool icl_is_nv12_y_plane(enum plane_id id
)
2400 /* Don't need to do a gen check, these planes are only available on gen11 */
2401 if (id
== PLANE_SPRITE4
|| id
== PLANE_SPRITE5
)
2407 static inline bool icl_is_hdr_plane(struct drm_i915_private
*dev_priv
,
2408 enum plane_id plane_id
)
2410 if (INTEL_GEN(dev_priv
) < 11)
2413 return plane_id
< PLANE_SPRITE2
;
2417 void intel_tv_init(struct drm_i915_private
*dev_priv
);
2419 /* intel_atomic.c */
2420 int intel_digital_connector_atomic_get_property(struct drm_connector
*connector
,
2421 const struct drm_connector_state
*state
,
2422 struct drm_property
*property
,
2424 int intel_digital_connector_atomic_set_property(struct drm_connector
*connector
,
2425 struct drm_connector_state
*state
,
2426 struct drm_property
*property
,
2428 int intel_digital_connector_atomic_check(struct drm_connector
*conn
,
2429 struct drm_connector_state
*new_state
);
2430 struct drm_connector_state
*
2431 intel_digital_connector_duplicate_state(struct drm_connector
*connector
);
2433 struct drm_crtc_state
*intel_crtc_duplicate_state(struct drm_crtc
*crtc
);
2434 void intel_crtc_destroy_state(struct drm_crtc
*crtc
,
2435 struct drm_crtc_state
*state
);
2436 struct drm_atomic_state
*intel_atomic_state_alloc(struct drm_device
*dev
);
2437 void intel_atomic_state_clear(struct drm_atomic_state
*);
2439 static inline struct intel_crtc_state
*
2440 intel_atomic_get_crtc_state(struct drm_atomic_state
*state
,
2441 struct intel_crtc
*crtc
)
2443 struct drm_crtc_state
*crtc_state
;
2444 crtc_state
= drm_atomic_get_crtc_state(state
, &crtc
->base
);
2445 if (IS_ERR(crtc_state
))
2446 return ERR_CAST(crtc_state
);
2448 return to_intel_crtc_state(crtc_state
);
2451 int intel_atomic_setup_scalers(struct drm_i915_private
*dev_priv
,
2452 struct intel_crtc
*intel_crtc
,
2453 struct intel_crtc_state
*crtc_state
);
2455 /* intel_atomic_plane.c */
2456 void intel_update_plane(struct intel_plane
*plane
,
2457 const struct intel_crtc_state
*crtc_state
,
2458 const struct intel_plane_state
*plane_state
);
2459 void intel_update_slave(struct intel_plane
*plane
,
2460 const struct intel_crtc_state
*crtc_state
,
2461 const struct intel_plane_state
*plane_state
);
2462 void intel_disable_plane(struct intel_plane
*plane
,
2463 const struct intel_crtc_state
*crtc_state
);
2464 struct intel_plane
*intel_plane_alloc(void);
2465 void intel_plane_free(struct intel_plane
*plane
);
2466 struct drm_plane_state
*intel_plane_duplicate_state(struct drm_plane
*plane
);
2467 void intel_plane_destroy_state(struct drm_plane
*plane
,
2468 struct drm_plane_state
*state
);
2469 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs
;
2470 void skl_update_planes_on_crtc(struct intel_atomic_state
*state
,
2471 struct intel_crtc
*crtc
);
2472 void i9xx_update_planes_on_crtc(struct intel_atomic_state
*state
,
2473 struct intel_crtc
*crtc
);
2474 int intel_plane_atomic_check_with_state(const struct intel_crtc_state
*old_crtc_state
,
2475 struct intel_crtc_state
*crtc_state
,
2476 const struct intel_plane_state
*old_plane_state
,
2477 struct intel_plane_state
*intel_state
);
2480 void intel_color_init(struct intel_crtc
*crtc
);
2481 int intel_color_check(struct intel_crtc_state
*crtc_state
);
2482 void intel_color_commit(const struct intel_crtc_state
*crtc_state
);
2483 void intel_color_load_luts(const struct intel_crtc_state
*crtc_state
);
2485 /* intel_lspcon.c */
2486 bool lspcon_init(struct intel_digital_port
*intel_dig_port
);
2487 void lspcon_resume(struct intel_lspcon
*lspcon
);
2488 void lspcon_wait_pcon_mode(struct intel_lspcon
*lspcon
);
2489 void lspcon_write_infoframe(struct intel_encoder
*encoder
,
2490 const struct intel_crtc_state
*crtc_state
,
2492 const void *buf
, ssize_t len
);
2493 void lspcon_read_infoframe(struct intel_encoder
*encoder
,
2494 const struct intel_crtc_state
*crtc_state
,
2496 void *frame
, ssize_t len
);
2497 void lspcon_set_infoframes(struct intel_encoder
*encoder
,
2499 const struct intel_crtc_state
*crtc_state
,
2500 const struct drm_connector_state
*conn_state
);
2501 u32
lspcon_infoframes_enabled(struct intel_encoder
*encoder
,
2502 const struct intel_crtc_state
*pipe_config
);
2503 void lspcon_ycbcr420_config(struct drm_connector
*connector
,
2504 struct intel_crtc_state
*crtc_state
);
2506 /* intel_pipe_crc.c */
2507 #ifdef CONFIG_DEBUG_FS
2508 int intel_crtc_set_crc_source(struct drm_crtc
*crtc
, const char *source_name
);
2509 int intel_crtc_verify_crc_source(struct drm_crtc
*crtc
,
2510 const char *source_name
, size_t *values_cnt
);
2511 const char *const *intel_crtc_get_crc_sources(struct drm_crtc
*crtc
,
2513 void intel_crtc_disable_pipe_crc(struct intel_crtc
*crtc
);
2514 void intel_crtc_enable_pipe_crc(struct intel_crtc
*crtc
);
2516 #define intel_crtc_set_crc_source NULL
2517 #define intel_crtc_verify_crc_source NULL
2518 #define intel_crtc_get_crc_sources NULL
2519 static inline void intel_crtc_disable_pipe_crc(struct intel_crtc
*crtc
)
2523 static inline void intel_crtc_enable_pipe_crc(struct intel_crtc
*crtc
)
2527 #endif /* __INTEL_DRV_H__ */