2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
23 * Author: Shobhit Kumar <shobhit.kumar@intel.com>
27 #include <drm/drm_crtc.h>
28 #include <drm/drm_edid.h>
29 #include <drm/i915_drm.h>
30 #include <linux/gpio/consumer.h>
31 #include <linux/mfd/intel_soc_pmic.h>
32 #include <linux/slab.h>
33 #include <video/mipi_display.h>
34 #include <asm/intel-mid.h>
35 #include <asm/unaligned.h>
37 #include "intel_drv.h"
38 #include "intel_dsi.h"
40 #define MIPI_TRANSFER_MODE_SHIFT 0
41 #define MIPI_VIRTUAL_CHANNEL_SHIFT 1
42 #define MIPI_PORT_SHIFT 3
44 #define PREPARE_CNT_MAX 0x3F
45 #define EXIT_ZERO_CNT_MAX 0x3F
46 #define CLK_ZERO_CNT_MAX 0xFF
47 #define TRAIL_CNT_MAX 0x1F
49 #define NS_KHZ_RATIO 1000000
51 /* base offsets for gpio pads */
52 #define VLV_GPIO_NC_0_HV_DDI0_HPD 0x4130
53 #define VLV_GPIO_NC_1_HV_DDI0_DDC_SDA 0x4120
54 #define VLV_GPIO_NC_2_HV_DDI0_DDC_SCL 0x4110
55 #define VLV_GPIO_NC_3_PANEL0_VDDEN 0x4140
56 #define VLV_GPIO_NC_4_PANEL0_BKLTEN 0x4150
57 #define VLV_GPIO_NC_5_PANEL0_BKLTCTL 0x4160
58 #define VLV_GPIO_NC_6_HV_DDI1_HPD 0x4180
59 #define VLV_GPIO_NC_7_HV_DDI1_DDC_SDA 0x4190
60 #define VLV_GPIO_NC_8_HV_DDI1_DDC_SCL 0x4170
61 #define VLV_GPIO_NC_9_PANEL1_VDDEN 0x4100
62 #define VLV_GPIO_NC_10_PANEL1_BKLTEN 0x40E0
63 #define VLV_GPIO_NC_11_PANEL1_BKLTCTL 0x40F0
65 #define VLV_GPIO_PCONF0(base_offset) (base_offset)
66 #define VLV_GPIO_PAD_VAL(base_offset) ((base_offset) + 8)
73 static struct gpio_map vlv_gpio_table
[] = {
74 { VLV_GPIO_NC_0_HV_DDI0_HPD
},
75 { VLV_GPIO_NC_1_HV_DDI0_DDC_SDA
},
76 { VLV_GPIO_NC_2_HV_DDI0_DDC_SCL
},
77 { VLV_GPIO_NC_3_PANEL0_VDDEN
},
78 { VLV_GPIO_NC_4_PANEL0_BKLTEN
},
79 { VLV_GPIO_NC_5_PANEL0_BKLTCTL
},
80 { VLV_GPIO_NC_6_HV_DDI1_HPD
},
81 { VLV_GPIO_NC_7_HV_DDI1_DDC_SDA
},
82 { VLV_GPIO_NC_8_HV_DDI1_DDC_SCL
},
83 { VLV_GPIO_NC_9_PANEL1_VDDEN
},
84 { VLV_GPIO_NC_10_PANEL1_BKLTEN
},
85 { VLV_GPIO_NC_11_PANEL1_BKLTCTL
},
88 #define CHV_GPIO_IDX_START_N 0
89 #define CHV_GPIO_IDX_START_E 73
90 #define CHV_GPIO_IDX_START_SW 100
91 #define CHV_GPIO_IDX_START_SE 198
93 #define CHV_VBT_MAX_PINS_PER_FMLY 15
95 #define CHV_GPIO_PAD_CFG0(f, i) (0x4400 + (f) * 0x400 + (i) * 8)
96 #define CHV_GPIO_GPIOEN (1 << 15)
97 #define CHV_GPIO_GPIOCFG_GPIO (0 << 8)
98 #define CHV_GPIO_GPIOCFG_GPO (1 << 8)
99 #define CHV_GPIO_GPIOCFG_GPI (2 << 8)
100 #define CHV_GPIO_GPIOCFG_HIZ (3 << 8)
101 #define CHV_GPIO_GPIOTXSTATE(state) ((!!(state)) << 1)
103 #define CHV_GPIO_PAD_CFG1(f, i) (0x4400 + (f) * 0x400 + (i) * 8 + 4)
104 #define CHV_GPIO_CFGLOCK (1 << 31)
106 /* ICL DSI Display GPIO Pins */
107 #define ICL_GPIO_DDSP_HPD_A 0
108 #define ICL_GPIO_L_VDDEN_1 1
109 #define ICL_GPIO_L_BKLTEN_1 2
110 #define ICL_GPIO_DDPA_CTRLCLK_1 3
111 #define ICL_GPIO_DDPA_CTRLDATA_1 4
112 #define ICL_GPIO_DDSP_HPD_B 5
113 #define ICL_GPIO_L_VDDEN_2 6
114 #define ICL_GPIO_L_BKLTEN_2 7
115 #define ICL_GPIO_DDPA_CTRLCLK_2 8
116 #define ICL_GPIO_DDPA_CTRLDATA_2 9
118 static inline enum port
intel_dsi_seq_port_to_port(u8 port
)
120 return port
? PORT_C
: PORT_A
;
123 static const u8
*mipi_exec_send_packet(struct intel_dsi
*intel_dsi
,
126 struct drm_i915_private
*dev_priv
= to_i915(intel_dsi
->base
.base
.dev
);
127 struct mipi_dsi_device
*dsi_device
;
128 u8 type
, flags
, seq_port
;
137 len
= *((u16
*) data
);
140 seq_port
= (flags
>> MIPI_PORT_SHIFT
) & 3;
142 /* For DSI single link on Port A & C, the seq_port value which is
143 * parsed from Sequence Block#53 of VBT has been set to 0
144 * Now, read/write of packets for the DSI single link on Port A and
145 * Port C will based on the DVO port from VBT block 2.
147 if (intel_dsi
->ports
== (1 << PORT_C
))
150 port
= intel_dsi_seq_port_to_port(seq_port
);
152 dsi_device
= intel_dsi
->dsi_hosts
[port
]->device
;
154 DRM_DEBUG_KMS("no dsi device for port %c\n", port_name(port
));
158 if ((flags
>> MIPI_TRANSFER_MODE_SHIFT
) & 1)
159 dsi_device
->mode_flags
&= ~MIPI_DSI_MODE_LPM
;
161 dsi_device
->mode_flags
|= MIPI_DSI_MODE_LPM
;
163 dsi_device
->channel
= (flags
>> MIPI_VIRTUAL_CHANNEL_SHIFT
) & 3;
166 case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM
:
167 mipi_dsi_generic_write(dsi_device
, NULL
, 0);
169 case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM
:
170 mipi_dsi_generic_write(dsi_device
, data
, 1);
172 case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM
:
173 mipi_dsi_generic_write(dsi_device
, data
, 2);
175 case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM
:
176 case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM
:
177 case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM
:
178 DRM_DEBUG_DRIVER("Generic Read not yet implemented or used\n");
180 case MIPI_DSI_GENERIC_LONG_WRITE
:
181 mipi_dsi_generic_write(dsi_device
, data
, len
);
183 case MIPI_DSI_DCS_SHORT_WRITE
:
184 mipi_dsi_dcs_write_buffer(dsi_device
, data
, 1);
186 case MIPI_DSI_DCS_SHORT_WRITE_PARAM
:
187 mipi_dsi_dcs_write_buffer(dsi_device
, data
, 2);
189 case MIPI_DSI_DCS_READ
:
190 DRM_DEBUG_DRIVER("DCS Read not yet implemented or used\n");
192 case MIPI_DSI_DCS_LONG_WRITE
:
193 mipi_dsi_dcs_write_buffer(dsi_device
, data
, len
);
197 if (!IS_ICELAKE(dev_priv
))
198 vlv_dsi_wait_for_fifo_empty(intel_dsi
, port
);
206 static const u8
*mipi_exec_delay(struct intel_dsi
*intel_dsi
, const u8
*data
)
208 u32 delay
= *((const u32
*) data
);
212 usleep_range(delay
, delay
+ 10);
218 static void vlv_exec_gpio(struct drm_i915_private
*dev_priv
,
219 u8 gpio_source
, u8 gpio_index
, bool value
)
221 struct gpio_map
*map
;
226 if (gpio_index
>= ARRAY_SIZE(vlv_gpio_table
)) {
227 DRM_DEBUG_KMS("unknown gpio index %u\n", gpio_index
);
231 map
= &vlv_gpio_table
[gpio_index
];
233 if (dev_priv
->vbt
.dsi
.seq_version
>= 3) {
234 /* XXX: this assumes vlv_gpio_table only has NC GPIOs. */
235 port
= IOSF_PORT_GPIO_NC
;
237 if (gpio_source
== 0) {
238 port
= IOSF_PORT_GPIO_NC
;
239 } else if (gpio_source
== 1) {
240 DRM_DEBUG_KMS("SC gpio not supported\n");
243 DRM_DEBUG_KMS("unknown gpio source %u\n", gpio_source
);
248 pconf0
= VLV_GPIO_PCONF0(map
->base_offset
);
249 padval
= VLV_GPIO_PAD_VAL(map
->base_offset
);
251 mutex_lock(&dev_priv
->sb_lock
);
253 /* FIXME: remove constant below */
254 vlv_iosf_sb_write(dev_priv
, port
, pconf0
, 0x2000CC00);
259 vlv_iosf_sb_write(dev_priv
, port
, padval
, tmp
);
260 mutex_unlock(&dev_priv
->sb_lock
);
263 static void chv_exec_gpio(struct drm_i915_private
*dev_priv
,
264 u8 gpio_source
, u8 gpio_index
, bool value
)
270 if (dev_priv
->vbt
.dsi
.seq_version
>= 3) {
271 if (gpio_index
>= CHV_GPIO_IDX_START_SE
) {
272 /* XXX: it's unclear whether 255->57 is part of SE. */
273 gpio_index
-= CHV_GPIO_IDX_START_SE
;
274 port
= CHV_IOSF_PORT_GPIO_SE
;
275 } else if (gpio_index
>= CHV_GPIO_IDX_START_SW
) {
276 gpio_index
-= CHV_GPIO_IDX_START_SW
;
277 port
= CHV_IOSF_PORT_GPIO_SW
;
278 } else if (gpio_index
>= CHV_GPIO_IDX_START_E
) {
279 gpio_index
-= CHV_GPIO_IDX_START_E
;
280 port
= CHV_IOSF_PORT_GPIO_E
;
282 port
= CHV_IOSF_PORT_GPIO_N
;
285 /* XXX: The spec is unclear about CHV GPIO on seq v2 */
286 if (gpio_source
!= 0) {
287 DRM_DEBUG_KMS("unknown gpio source %u\n", gpio_source
);
291 if (gpio_index
>= CHV_GPIO_IDX_START_E
) {
292 DRM_DEBUG_KMS("invalid gpio index %u for GPIO N\n",
297 port
= CHV_IOSF_PORT_GPIO_N
;
300 family_num
= gpio_index
/ CHV_VBT_MAX_PINS_PER_FMLY
;
301 gpio_index
= gpio_index
% CHV_VBT_MAX_PINS_PER_FMLY
;
303 cfg0
= CHV_GPIO_PAD_CFG0(family_num
, gpio_index
);
304 cfg1
= CHV_GPIO_PAD_CFG1(family_num
, gpio_index
);
306 mutex_lock(&dev_priv
->sb_lock
);
307 vlv_iosf_sb_write(dev_priv
, port
, cfg1
, 0);
308 vlv_iosf_sb_write(dev_priv
, port
, cfg0
,
309 CHV_GPIO_GPIOEN
| CHV_GPIO_GPIOCFG_GPO
|
310 CHV_GPIO_GPIOTXSTATE(value
));
311 mutex_unlock(&dev_priv
->sb_lock
);
314 static void bxt_exec_gpio(struct drm_i915_private
*dev_priv
,
315 u8 gpio_source
, u8 gpio_index
, bool value
)
317 /* XXX: this table is a quick ugly hack. */
318 static struct gpio_desc
*bxt_gpio_table
[U8_MAX
+ 1];
319 struct gpio_desc
*gpio_desc
= bxt_gpio_table
[gpio_index
];
322 gpio_desc
= devm_gpiod_get_index(dev_priv
->drm
.dev
,
324 value
? GPIOD_OUT_LOW
:
327 if (IS_ERR_OR_NULL(gpio_desc
)) {
328 DRM_ERROR("GPIO index %u request failed (%ld)\n",
329 gpio_index
, PTR_ERR(gpio_desc
));
333 bxt_gpio_table
[gpio_index
] = gpio_desc
;
336 gpiod_set_value(gpio_desc
, value
);
339 static void icl_exec_gpio(struct drm_i915_private
*dev_priv
,
340 u8 gpio_source
, u8 gpio_index
, bool value
)
342 DRM_DEBUG_KMS("Skipping ICL GPIO element execution\n");
345 static const u8
*mipi_exec_gpio(struct intel_dsi
*intel_dsi
, const u8
*data
)
347 struct drm_device
*dev
= intel_dsi
->base
.base
.dev
;
348 struct drm_i915_private
*dev_priv
= to_i915(dev
);
349 u8 gpio_source
, gpio_index
= 0, gpio_number
;
354 if (dev_priv
->vbt
.dsi
.seq_version
>= 3)
355 gpio_index
= *data
++;
357 gpio_number
= *data
++;
359 /* gpio source in sequence v2 only */
360 if (dev_priv
->vbt
.dsi
.seq_version
== 2)
361 gpio_source
= (*data
>> 1) & 3;
368 if (IS_ICELAKE(dev_priv
))
369 icl_exec_gpio(dev_priv
, gpio_source
, gpio_index
, value
);
370 else if (IS_VALLEYVIEW(dev_priv
))
371 vlv_exec_gpio(dev_priv
, gpio_source
, gpio_number
, value
);
372 else if (IS_CHERRYVIEW(dev_priv
))
373 chv_exec_gpio(dev_priv
, gpio_source
, gpio_number
, value
);
375 bxt_exec_gpio(dev_priv
, gpio_source
, gpio_index
, value
);
380 static const u8
*mipi_exec_i2c(struct intel_dsi
*intel_dsi
, const u8
*data
)
382 DRM_DEBUG_KMS("Skipping I2C element execution\n");
384 return data
+ *(data
+ 6) + 7;
387 static const u8
*mipi_exec_spi(struct intel_dsi
*intel_dsi
, const u8
*data
)
389 DRM_DEBUG_KMS("Skipping SPI element execution\n");
391 return data
+ *(data
+ 5) + 6;
394 static const u8
*mipi_exec_pmic(struct intel_dsi
*intel_dsi
, const u8
*data
)
396 #ifdef CONFIG_PMIC_OPREGION
397 u32 value
, mask
, reg_address
;
401 /* byte 0 aka PMIC Flag is reserved */
402 i2c_address
= get_unaligned_le16(data
+ 1);
403 reg_address
= get_unaligned_le32(data
+ 3);
404 value
= get_unaligned_le32(data
+ 7);
405 mask
= get_unaligned_le32(data
+ 11);
407 ret
= intel_soc_pmic_exec_mipi_pmic_seq_element(i2c_address
,
411 DRM_ERROR("%s failed, error: %d\n", __func__
, ret
);
413 DRM_ERROR("Your hardware requires CONFIG_PMIC_OPREGION and it is not set\n");
419 typedef const u8
* (*fn_mipi_elem_exec
)(struct intel_dsi
*intel_dsi
,
421 static const fn_mipi_elem_exec exec_elem
[] = {
422 [MIPI_SEQ_ELEM_SEND_PKT
] = mipi_exec_send_packet
,
423 [MIPI_SEQ_ELEM_DELAY
] = mipi_exec_delay
,
424 [MIPI_SEQ_ELEM_GPIO
] = mipi_exec_gpio
,
425 [MIPI_SEQ_ELEM_I2C
] = mipi_exec_i2c
,
426 [MIPI_SEQ_ELEM_SPI
] = mipi_exec_spi
,
427 [MIPI_SEQ_ELEM_PMIC
] = mipi_exec_pmic
,
431 * MIPI Sequence from VBT #53 parsing logic
432 * We have already separated each seqence during bios parsing
433 * Following is generic execution function for any sequence
436 static const char * const seq_name
[] = {
437 [MIPI_SEQ_DEASSERT_RESET
] = "MIPI_SEQ_DEASSERT_RESET",
438 [MIPI_SEQ_INIT_OTP
] = "MIPI_SEQ_INIT_OTP",
439 [MIPI_SEQ_DISPLAY_ON
] = "MIPI_SEQ_DISPLAY_ON",
440 [MIPI_SEQ_DISPLAY_OFF
] = "MIPI_SEQ_DISPLAY_OFF",
441 [MIPI_SEQ_ASSERT_RESET
] = "MIPI_SEQ_ASSERT_RESET",
442 [MIPI_SEQ_BACKLIGHT_ON
] = "MIPI_SEQ_BACKLIGHT_ON",
443 [MIPI_SEQ_BACKLIGHT_OFF
] = "MIPI_SEQ_BACKLIGHT_OFF",
444 [MIPI_SEQ_TEAR_ON
] = "MIPI_SEQ_TEAR_ON",
445 [MIPI_SEQ_TEAR_OFF
] = "MIPI_SEQ_TEAR_OFF",
446 [MIPI_SEQ_POWER_ON
] = "MIPI_SEQ_POWER_ON",
447 [MIPI_SEQ_POWER_OFF
] = "MIPI_SEQ_POWER_OFF",
450 static const char *sequence_name(enum mipi_seq seq_id
)
452 if (seq_id
< ARRAY_SIZE(seq_name
) && seq_name
[seq_id
])
453 return seq_name
[seq_id
];
458 void intel_dsi_vbt_exec_sequence(struct intel_dsi
*intel_dsi
,
459 enum mipi_seq seq_id
)
461 struct drm_i915_private
*dev_priv
= to_i915(intel_dsi
->base
.base
.dev
);
463 fn_mipi_elem_exec mipi_elem_exec
;
465 if (WARN_ON(seq_id
>= ARRAY_SIZE(dev_priv
->vbt
.dsi
.sequence
)))
468 data
= dev_priv
->vbt
.dsi
.sequence
[seq_id
];
472 WARN_ON(*data
!= seq_id
);
474 DRM_DEBUG_KMS("Starting MIPI sequence %d - %s\n",
475 seq_id
, sequence_name(seq_id
));
477 /* Skip Sequence Byte. */
480 /* Skip Size of Sequence. */
481 if (dev_priv
->vbt
.dsi
.seq_version
>= 3)
485 u8 operation_byte
= *data
++;
486 u8 operation_size
= 0;
488 if (operation_byte
== MIPI_SEQ_ELEM_END
)
491 if (operation_byte
< ARRAY_SIZE(exec_elem
))
492 mipi_elem_exec
= exec_elem
[operation_byte
];
494 mipi_elem_exec
= NULL
;
496 /* Size of Operation. */
497 if (dev_priv
->vbt
.dsi
.seq_version
>= 3)
498 operation_size
= *data
++;
500 if (mipi_elem_exec
) {
501 const u8
*next
= data
+ operation_size
;
503 data
= mipi_elem_exec(intel_dsi
, data
);
505 /* Consistency check if we have size. */
506 if (operation_size
&& data
!= next
) {
507 DRM_ERROR("Inconsistent operation size\n");
510 } else if (operation_size
) {
511 /* We have size, skip. */
512 DRM_DEBUG_KMS("Unsupported MIPI operation byte %u\n",
514 data
+= operation_size
;
516 /* No size, can't skip without parsing. */
517 DRM_ERROR("Unsupported MIPI operation byte %u\n",
524 void intel_dsi_msleep(struct intel_dsi
*intel_dsi
, int msec
)
526 struct drm_i915_private
*dev_priv
= to_i915(intel_dsi
->base
.base
.dev
);
528 /* For v3 VBTs in vid-mode the delays are part of the VBT sequences */
529 if (is_vid_mode(intel_dsi
) && dev_priv
->vbt
.dsi
.seq_version
>= 3)
535 int intel_dsi_vbt_get_modes(struct intel_dsi
*intel_dsi
)
537 struct intel_connector
*connector
= intel_dsi
->attached_connector
;
538 struct drm_device
*dev
= intel_dsi
->base
.base
.dev
;
539 struct drm_i915_private
*dev_priv
= to_i915(dev
);
540 struct drm_display_mode
*mode
;
542 mode
= drm_mode_duplicate(dev
, dev_priv
->vbt
.lfp_lvds_vbt_mode
);
546 mode
->type
|= DRM_MODE_TYPE_PREFERRED
;
548 drm_mode_probed_add(&connector
->base
, mode
);
553 #define ICL_PREPARE_CNT_MAX 0x7
554 #define ICL_CLK_ZERO_CNT_MAX 0xf
555 #define ICL_TRAIL_CNT_MAX 0x7
556 #define ICL_TCLK_PRE_CNT_MAX 0x3
557 #define ICL_TCLK_POST_CNT_MAX 0x7
558 #define ICL_HS_ZERO_CNT_MAX 0xf
559 #define ICL_EXIT_ZERO_CNT_MAX 0x7
561 static void icl_dphy_param_init(struct intel_dsi
*intel_dsi
)
563 struct drm_device
*dev
= intel_dsi
->base
.base
.dev
;
564 struct drm_i915_private
*dev_priv
= to_i915(dev
);
565 struct mipi_config
*mipi_config
= dev_priv
->vbt
.dsi
.config
;
567 u32 prepare_cnt
, exit_zero_cnt
, clk_zero_cnt
, trail_cnt
;
568 u32 ths_prepare_ns
, tclk_trail_ns
;
570 u32 tclk_pre_cnt
, tclk_post_cnt
;
572 tlpx_ns
= intel_dsi_tlpx_ns(intel_dsi
);
574 tclk_trail_ns
= max(mipi_config
->tclk_trail
, mipi_config
->ths_trail
);
575 ths_prepare_ns
= max(mipi_config
->ths_prepare
,
576 mipi_config
->tclk_prepare
);
579 * prepare cnt in escape clocks
580 * this field represents a hexadecimal value with a precision
581 * of 1.2 – i.e. the most significant bit is the integer
582 * and the least significant 2 bits are fraction bits.
583 * so, the field can represent a range of 0.25 to 1.75
585 prepare_cnt
= DIV_ROUND_UP(ths_prepare_ns
* 4, tlpx_ns
);
586 if (prepare_cnt
> ICL_PREPARE_CNT_MAX
) {
587 DRM_DEBUG_KMS("prepare_cnt out of range (%d)\n", prepare_cnt
);
588 prepare_cnt
= ICL_PREPARE_CNT_MAX
;
591 /* clk zero count in escape clocks */
592 clk_zero_cnt
= DIV_ROUND_UP(mipi_config
->tclk_prepare_clkzero
-
593 ths_prepare_ns
, tlpx_ns
);
594 if (clk_zero_cnt
> ICL_CLK_ZERO_CNT_MAX
) {
595 DRM_DEBUG_KMS("clk_zero_cnt out of range (%d)\n", clk_zero_cnt
);
596 clk_zero_cnt
= ICL_CLK_ZERO_CNT_MAX
;
599 /* trail cnt in escape clocks*/
600 trail_cnt
= DIV_ROUND_UP(tclk_trail_ns
, tlpx_ns
);
601 if (trail_cnt
> ICL_TRAIL_CNT_MAX
) {
602 DRM_DEBUG_KMS("trail_cnt out of range (%d)\n", trail_cnt
);
603 trail_cnt
= ICL_TRAIL_CNT_MAX
;
606 /* tclk pre count in escape clocks */
607 tclk_pre_cnt
= DIV_ROUND_UP(mipi_config
->tclk_pre
, tlpx_ns
);
608 if (tclk_pre_cnt
> ICL_TCLK_PRE_CNT_MAX
) {
609 DRM_DEBUG_KMS("tclk_pre_cnt out of range (%d)\n", tclk_pre_cnt
);
610 tclk_pre_cnt
= ICL_TCLK_PRE_CNT_MAX
;
613 /* tclk post count in escape clocks */
614 tclk_post_cnt
= DIV_ROUND_UP(mipi_config
->tclk_post
, tlpx_ns
);
615 if (tclk_post_cnt
> ICL_TCLK_POST_CNT_MAX
) {
616 DRM_DEBUG_KMS("tclk_post_cnt out of range (%d)\n", tclk_post_cnt
);
617 tclk_post_cnt
= ICL_TCLK_POST_CNT_MAX
;
620 /* hs zero cnt in escape clocks */
621 hs_zero_cnt
= DIV_ROUND_UP(mipi_config
->ths_prepare_hszero
-
622 ths_prepare_ns
, tlpx_ns
);
623 if (hs_zero_cnt
> ICL_HS_ZERO_CNT_MAX
) {
624 DRM_DEBUG_KMS("hs_zero_cnt out of range (%d)\n", hs_zero_cnt
);
625 hs_zero_cnt
= ICL_HS_ZERO_CNT_MAX
;
628 /* hs exit zero cnt in escape clocks */
629 exit_zero_cnt
= DIV_ROUND_UP(mipi_config
->ths_exit
, tlpx_ns
);
630 if (exit_zero_cnt
> ICL_EXIT_ZERO_CNT_MAX
) {
631 DRM_DEBUG_KMS("exit_zero_cnt out of range (%d)\n", exit_zero_cnt
);
632 exit_zero_cnt
= ICL_EXIT_ZERO_CNT_MAX
;
635 /* clock lane dphy timings */
636 intel_dsi
->dphy_reg
= (CLK_PREPARE_OVERRIDE
|
637 CLK_PREPARE(prepare_cnt
) |
639 CLK_ZERO(clk_zero_cnt
) |
641 CLK_PRE(tclk_pre_cnt
) |
643 CLK_POST(tclk_post_cnt
) |
645 CLK_TRAIL(trail_cnt
));
647 /* data lanes dphy timings */
648 intel_dsi
->dphy_data_lane_reg
= (HS_PREPARE_OVERRIDE
|
649 HS_PREPARE(prepare_cnt
) |
651 HS_ZERO(hs_zero_cnt
) |
653 HS_TRAIL(trail_cnt
) |
655 HS_EXIT(exit_zero_cnt
));
658 static void vlv_dphy_param_init(struct intel_dsi
*intel_dsi
)
660 struct drm_device
*dev
= intel_dsi
->base
.base
.dev
;
661 struct drm_i915_private
*dev_priv
= to_i915(dev
);
662 struct mipi_config
*mipi_config
= dev_priv
->vbt
.dsi
.config
;
663 u32 tlpx_ns
, extra_byte_count
, tlpx_ui
;
665 u32 prepare_cnt
, exit_zero_cnt
, clk_zero_cnt
, trail_cnt
;
666 u32 ths_prepare_ns
, tclk_trail_ns
;
667 u32 tclk_prepare_clkzero
, ths_prepare_hszero
;
668 u32 lp_to_hs_switch
, hs_to_lp_switch
;
671 tlpx_ns
= intel_dsi_tlpx_ns(intel_dsi
);
673 switch (intel_dsi
->lane_count
) {
676 extra_byte_count
= 2;
679 extra_byte_count
= 4;
683 extra_byte_count
= 3;
688 ui_num
= NS_KHZ_RATIO
;
689 ui_den
= intel_dsi_bitrate(intel_dsi
);
691 tclk_prepare_clkzero
= mipi_config
->tclk_prepare_clkzero
;
692 ths_prepare_hszero
= mipi_config
->ths_prepare_hszero
;
696 * LP byte clock = TLPX/ (8UI)
698 intel_dsi
->lp_byte_clk
= DIV_ROUND_UP(tlpx_ns
* ui_den
, 8 * ui_num
);
700 /* DDR clock period = 2 * UI
701 * UI(sec) = 1/(bitrate * 10^3) (bitrate is in KHZ)
702 * UI(nsec) = 10^6 / bitrate
703 * DDR clock period (nsec) = 2 * UI = (2 * 10^6)/ bitrate
704 * DDR clock count = ns_value / DDR clock period
706 * For GEMINILAKE dphy_param_reg will be programmed in terms of
707 * HS byte clock count for other platform in HS ddr clock count
709 mul
= IS_GEMINILAKE(dev_priv
) ? 8 : 2;
710 ths_prepare_ns
= max(mipi_config
->ths_prepare
,
711 mipi_config
->tclk_prepare
);
714 prepare_cnt
= DIV_ROUND_UP(ths_prepare_ns
* ui_den
, ui_num
* mul
);
716 if (prepare_cnt
> PREPARE_CNT_MAX
) {
717 DRM_DEBUG_KMS("prepare count too high %u\n", prepare_cnt
);
718 prepare_cnt
= PREPARE_CNT_MAX
;
721 /* exit zero count */
722 exit_zero_cnt
= DIV_ROUND_UP(
723 (ths_prepare_hszero
- ths_prepare_ns
) * ui_den
,
728 * Exit zero is unified val ths_zero and ths_exit
729 * minimum value for ths_exit = 110ns
730 * min (exit_zero_cnt * 2) = 110/UI
731 * exit_zero_cnt = 55/UI
733 if (exit_zero_cnt
< (55 * ui_den
/ ui_num
) && (55 * ui_den
) % ui_num
)
736 if (exit_zero_cnt
> EXIT_ZERO_CNT_MAX
) {
737 DRM_DEBUG_KMS("exit zero count too high %u\n", exit_zero_cnt
);
738 exit_zero_cnt
= EXIT_ZERO_CNT_MAX
;
742 clk_zero_cnt
= DIV_ROUND_UP(
743 (tclk_prepare_clkzero
- ths_prepare_ns
)
744 * ui_den
, ui_num
* mul
);
746 if (clk_zero_cnt
> CLK_ZERO_CNT_MAX
) {
747 DRM_DEBUG_KMS("clock zero count too high %u\n", clk_zero_cnt
);
748 clk_zero_cnt
= CLK_ZERO_CNT_MAX
;
752 tclk_trail_ns
= max(mipi_config
->tclk_trail
, mipi_config
->ths_trail
);
753 trail_cnt
= DIV_ROUND_UP(tclk_trail_ns
* ui_den
, ui_num
* mul
);
755 if (trail_cnt
> TRAIL_CNT_MAX
) {
756 DRM_DEBUG_KMS("trail count too high %u\n", trail_cnt
);
757 trail_cnt
= TRAIL_CNT_MAX
;
761 intel_dsi
->dphy_reg
= exit_zero_cnt
<< 24 | trail_cnt
<< 16 |
762 clk_zero_cnt
<< 8 | prepare_cnt
;
765 * LP to HS switch count = 4TLPX + PREP_COUNT * mul + EXIT_ZERO_COUNT *
766 * mul + 10UI + Extra Byte Count
768 * HS to LP switch count = THS-TRAIL + 2TLPX + Extra Byte Count
769 * Extra Byte Count is calculated according to number of lanes.
770 * High Low Switch Count is the Max of LP to HS and
771 * HS to LP switch count
774 tlpx_ui
= DIV_ROUND_UP(tlpx_ns
* ui_den
, ui_num
);
778 * The comment above does not match with the code */
779 lp_to_hs_switch
= DIV_ROUND_UP(4 * tlpx_ui
+ prepare_cnt
* mul
+
780 exit_zero_cnt
* mul
+ 10, 8);
782 hs_to_lp_switch
= DIV_ROUND_UP(mipi_config
->ths_trail
+ 2 * tlpx_ui
, 8);
784 intel_dsi
->hs_to_lp_count
= max(lp_to_hs_switch
, hs_to_lp_switch
);
785 intel_dsi
->hs_to_lp_count
+= extra_byte_count
;
788 /* LP -> HS for clock lanes
789 * LP clk sync + LP11 + LP01 + tclk_prepare + tclk_zero +
791 * 2TPLX + 1TLPX + 1 TPLX(in ns) + prepare_cnt * 2 + clk_zero_cnt *
792 * 2(in UI) + extra byte count
793 * In byteclks = (4TLPX + prepare_cnt * 2 + clk_zero_cnt *2 (in UI)) /
794 * 8 + extra byte count
796 intel_dsi
->clk_lp_to_hs_count
=
798 4 * tlpx_ui
+ prepare_cnt
* 2 +
802 intel_dsi
->clk_lp_to_hs_count
+= extra_byte_count
;
804 /* HS->LP for Clock Lanes
805 * Low Power clock synchronisations + 1Tx byteclk + tclk_trail +
807 * 2TLPX + 8UI + (trail_count*2)(in UI) + Extra byte count
808 * In byteclks = (2*TLpx(in UI) + trail_count*2 +8)(in UI)/8 +
811 intel_dsi
->clk_hs_to_lp_count
=
812 DIV_ROUND_UP(2 * tlpx_ui
+ trail_cnt
* 2 + 8,
814 intel_dsi
->clk_hs_to_lp_count
+= extra_byte_count
;
817 bool intel_dsi_vbt_init(struct intel_dsi
*intel_dsi
, u16 panel_id
)
819 struct drm_device
*dev
= intel_dsi
->base
.base
.dev
;
820 struct drm_i915_private
*dev_priv
= to_i915(dev
);
821 struct mipi_config
*mipi_config
= dev_priv
->vbt
.dsi
.config
;
822 struct mipi_pps_data
*pps
= dev_priv
->vbt
.dsi
.pps
;
823 struct drm_display_mode
*mode
= dev_priv
->vbt
.lfp_lvds_vbt_mode
;
824 u16 burst_mode_ratio
;
829 intel_dsi
->eotp_pkt
= mipi_config
->eot_pkt_disabled
? 0 : 1;
830 intel_dsi
->clock_stop
= mipi_config
->enable_clk_stop
? 1 : 0;
831 intel_dsi
->lane_count
= mipi_config
->lane_cnt
+ 1;
832 intel_dsi
->pixel_format
=
833 pixel_format_from_register_bits(
834 mipi_config
->videomode_color_format
<< 7);
836 intel_dsi
->dual_link
= mipi_config
->dual_link
;
837 intel_dsi
->pixel_overlap
= mipi_config
->pixel_overlap
;
838 intel_dsi
->operation_mode
= mipi_config
->is_cmd_mode
;
839 intel_dsi
->video_mode_format
= mipi_config
->video_transfer_mode
;
840 intel_dsi
->escape_clk_div
= mipi_config
->byte_clk_sel
;
841 intel_dsi
->lp_rx_timeout
= mipi_config
->lp_rx_timeout
;
842 intel_dsi
->hs_tx_timeout
= mipi_config
->hs_tx_timeout
;
843 intel_dsi
->turn_arnd_val
= mipi_config
->turn_around_timeout
;
844 intel_dsi
->rst_timer_val
= mipi_config
->device_reset_timer
;
845 intel_dsi
->init_count
= mipi_config
->master_init_timer
;
846 intel_dsi
->bw_timer
= mipi_config
->dbi_bw_timer
;
847 intel_dsi
->video_frmt_cfg_bits
=
848 mipi_config
->bta_enabled
? DISABLE_VIDEO_BTA
: 0;
849 intel_dsi
->bgr_enabled
= mipi_config
->rgb_flip
;
851 /* Starting point, adjusted depending on dual link and burst mode */
852 intel_dsi
->pclk
= mode
->clock
;
854 /* In dual link mode each port needs half of pixel clock */
855 if (intel_dsi
->dual_link
) {
856 intel_dsi
->pclk
/= 2;
858 /* we can enable pixel_overlap if needed by panel. In this
859 * case we need to increase the pixelclock for extra pixels
861 if (intel_dsi
->dual_link
== DSI_DUAL_LINK_FRONT_BACK
) {
862 intel_dsi
->pclk
+= DIV_ROUND_UP(mode
->vtotal
* intel_dsi
->pixel_overlap
* 60, 1000);
867 * Target ddr frequency from VBT / non burst ddr freq
868 * multiply by 100 to preserve remainder
870 if (intel_dsi
->video_mode_format
== VIDEO_MODE_BURST
) {
871 if (mipi_config
->target_burst_mode_freq
) {
872 u32 bitrate
= intel_dsi_bitrate(intel_dsi
);
874 if (mipi_config
->target_burst_mode_freq
< bitrate
) {
875 DRM_ERROR("Burst mode freq is less than computed\n");
879 burst_mode_ratio
= DIV_ROUND_UP(
880 mipi_config
->target_burst_mode_freq
* 100,
883 intel_dsi
->pclk
= DIV_ROUND_UP(intel_dsi
->pclk
* burst_mode_ratio
, 100);
885 DRM_ERROR("Burst mode target is not set\n");
889 burst_mode_ratio
= 100;
891 intel_dsi
->burst_mode_ratio
= burst_mode_ratio
;
893 if (IS_ICELAKE(dev_priv
))
894 icl_dphy_param_init(intel_dsi
);
896 vlv_dphy_param_init(intel_dsi
);
898 DRM_DEBUG_KMS("Pclk %d\n", intel_dsi
->pclk
);
899 DRM_DEBUG_KMS("Pixel overlap %d\n", intel_dsi
->pixel_overlap
);
900 DRM_DEBUG_KMS("Lane count %d\n", intel_dsi
->lane_count
);
901 DRM_DEBUG_KMS("DPHY param reg 0x%x\n", intel_dsi
->dphy_reg
);
902 DRM_DEBUG_KMS("Video mode format %s\n",
903 intel_dsi
->video_mode_format
== VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE
?
904 "non-burst with sync pulse" :
905 intel_dsi
->video_mode_format
== VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS
?
906 "non-burst with sync events" :
907 intel_dsi
->video_mode_format
== VIDEO_MODE_BURST
?
908 "burst" : "<unknown>");
909 DRM_DEBUG_KMS("Burst mode ratio %d\n", intel_dsi
->burst_mode_ratio
);
910 DRM_DEBUG_KMS("Reset timer %d\n", intel_dsi
->rst_timer_val
);
911 DRM_DEBUG_KMS("Eot %s\n", enableddisabled(intel_dsi
->eotp_pkt
));
912 DRM_DEBUG_KMS("Clockstop %s\n", enableddisabled(!intel_dsi
->clock_stop
));
913 DRM_DEBUG_KMS("Mode %s\n", intel_dsi
->operation_mode
? "command" : "video");
914 if (intel_dsi
->dual_link
== DSI_DUAL_LINK_FRONT_BACK
)
915 DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_FRONT_BACK\n");
916 else if (intel_dsi
->dual_link
== DSI_DUAL_LINK_PIXEL_ALT
)
917 DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_PIXEL_ALT\n");
919 DRM_DEBUG_KMS("Dual link: NONE\n");
920 DRM_DEBUG_KMS("Pixel Format %d\n", intel_dsi
->pixel_format
);
921 DRM_DEBUG_KMS("TLPX %d\n", intel_dsi
->escape_clk_div
);
922 DRM_DEBUG_KMS("LP RX Timeout 0x%x\n", intel_dsi
->lp_rx_timeout
);
923 DRM_DEBUG_KMS("Turnaround Timeout 0x%x\n", intel_dsi
->turn_arnd_val
);
924 DRM_DEBUG_KMS("Init Count 0x%x\n", intel_dsi
->init_count
);
925 DRM_DEBUG_KMS("HS to LP Count 0x%x\n", intel_dsi
->hs_to_lp_count
);
926 DRM_DEBUG_KMS("LP Byte Clock %d\n", intel_dsi
->lp_byte_clk
);
927 DRM_DEBUG_KMS("DBI BW Timer 0x%x\n", intel_dsi
->bw_timer
);
928 DRM_DEBUG_KMS("LP to HS Clock Count 0x%x\n", intel_dsi
->clk_lp_to_hs_count
);
929 DRM_DEBUG_KMS("HS to LP Clock Count 0x%x\n", intel_dsi
->clk_hs_to_lp_count
);
930 DRM_DEBUG_KMS("BTA %s\n",
931 enableddisabled(!(intel_dsi
->video_frmt_cfg_bits
& DISABLE_VIDEO_BTA
)));
933 /* delays in VBT are in unit of 100us, so need to convert
935 * Delay (100us) * 100 /1000 = Delay / 10 (ms) */
936 intel_dsi
->backlight_off_delay
= pps
->bl_disable_delay
/ 10;
937 intel_dsi
->backlight_on_delay
= pps
->bl_enable_delay
/ 10;
938 intel_dsi
->panel_on_delay
= pps
->panel_on_delay
/ 10;
939 intel_dsi
->panel_off_delay
= pps
->panel_off_delay
/ 10;
940 intel_dsi
->panel_pwr_cycle_delay
= pps
->panel_power_cycle_delay
/ 10;
942 /* a regular driver would get the device in probe */
943 for_each_dsi_port(port
, intel_dsi
->ports
) {
944 mipi_dsi_attach(intel_dsi
->dsi_hosts
[port
]->device
);