2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
23 * Author: Shobhit Kumar <shobhit.kumar@intel.com>
27 #include <linux/gpio/consumer.h>
28 #include <linux/mfd/intel_soc_pmic.h>
29 #include <linux/slab.h>
31 #include <asm/intel-mid.h>
32 #include <asm/unaligned.h>
34 #include <drm/drm_crtc.h>
35 #include <drm/drm_edid.h>
36 #include <drm/i915_drm.h>
38 #include <video/mipi_display.h>
41 #include "intel_drv.h"
42 #include "intel_dsi.h"
43 #include "intel_sideband.h"
45 #define MIPI_TRANSFER_MODE_SHIFT 0
46 #define MIPI_VIRTUAL_CHANNEL_SHIFT 1
47 #define MIPI_PORT_SHIFT 3
49 #define PREPARE_CNT_MAX 0x3F
50 #define EXIT_ZERO_CNT_MAX 0x3F
51 #define CLK_ZERO_CNT_MAX 0xFF
52 #define TRAIL_CNT_MAX 0x1F
54 #define NS_KHZ_RATIO 1000000
56 /* base offsets for gpio pads */
57 #define VLV_GPIO_NC_0_HV_DDI0_HPD 0x4130
58 #define VLV_GPIO_NC_1_HV_DDI0_DDC_SDA 0x4120
59 #define VLV_GPIO_NC_2_HV_DDI0_DDC_SCL 0x4110
60 #define VLV_GPIO_NC_3_PANEL0_VDDEN 0x4140
61 #define VLV_GPIO_NC_4_PANEL0_BKLTEN 0x4150
62 #define VLV_GPIO_NC_5_PANEL0_BKLTCTL 0x4160
63 #define VLV_GPIO_NC_6_HV_DDI1_HPD 0x4180
64 #define VLV_GPIO_NC_7_HV_DDI1_DDC_SDA 0x4190
65 #define VLV_GPIO_NC_8_HV_DDI1_DDC_SCL 0x4170
66 #define VLV_GPIO_NC_9_PANEL1_VDDEN 0x4100
67 #define VLV_GPIO_NC_10_PANEL1_BKLTEN 0x40E0
68 #define VLV_GPIO_NC_11_PANEL1_BKLTCTL 0x40F0
70 #define VLV_GPIO_PCONF0(base_offset) (base_offset)
71 #define VLV_GPIO_PAD_VAL(base_offset) ((base_offset) + 8)
78 static struct gpio_map vlv_gpio_table
[] = {
79 { VLV_GPIO_NC_0_HV_DDI0_HPD
},
80 { VLV_GPIO_NC_1_HV_DDI0_DDC_SDA
},
81 { VLV_GPIO_NC_2_HV_DDI0_DDC_SCL
},
82 { VLV_GPIO_NC_3_PANEL0_VDDEN
},
83 { VLV_GPIO_NC_4_PANEL0_BKLTEN
},
84 { VLV_GPIO_NC_5_PANEL0_BKLTCTL
},
85 { VLV_GPIO_NC_6_HV_DDI1_HPD
},
86 { VLV_GPIO_NC_7_HV_DDI1_DDC_SDA
},
87 { VLV_GPIO_NC_8_HV_DDI1_DDC_SCL
},
88 { VLV_GPIO_NC_9_PANEL1_VDDEN
},
89 { VLV_GPIO_NC_10_PANEL1_BKLTEN
},
90 { VLV_GPIO_NC_11_PANEL1_BKLTCTL
},
93 #define CHV_GPIO_IDX_START_N 0
94 #define CHV_GPIO_IDX_START_E 73
95 #define CHV_GPIO_IDX_START_SW 100
96 #define CHV_GPIO_IDX_START_SE 198
98 #define CHV_VBT_MAX_PINS_PER_FMLY 15
100 #define CHV_GPIO_PAD_CFG0(f, i) (0x4400 + (f) * 0x400 + (i) * 8)
101 #define CHV_GPIO_GPIOEN (1 << 15)
102 #define CHV_GPIO_GPIOCFG_GPIO (0 << 8)
103 #define CHV_GPIO_GPIOCFG_GPO (1 << 8)
104 #define CHV_GPIO_GPIOCFG_GPI (2 << 8)
105 #define CHV_GPIO_GPIOCFG_HIZ (3 << 8)
106 #define CHV_GPIO_GPIOTXSTATE(state) ((!!(state)) << 1)
108 #define CHV_GPIO_PAD_CFG1(f, i) (0x4400 + (f) * 0x400 + (i) * 8 + 4)
109 #define CHV_GPIO_CFGLOCK (1 << 31)
111 /* ICL DSI Display GPIO Pins */
112 #define ICL_GPIO_DDSP_HPD_A 0
113 #define ICL_GPIO_L_VDDEN_1 1
114 #define ICL_GPIO_L_BKLTEN_1 2
115 #define ICL_GPIO_DDPA_CTRLCLK_1 3
116 #define ICL_GPIO_DDPA_CTRLDATA_1 4
117 #define ICL_GPIO_DDSP_HPD_B 5
118 #define ICL_GPIO_L_VDDEN_2 6
119 #define ICL_GPIO_L_BKLTEN_2 7
120 #define ICL_GPIO_DDPA_CTRLCLK_2 8
121 #define ICL_GPIO_DDPA_CTRLDATA_2 9
123 static inline enum port
intel_dsi_seq_port_to_port(u8 port
)
125 return port
? PORT_C
: PORT_A
;
128 static const u8
*mipi_exec_send_packet(struct intel_dsi
*intel_dsi
,
131 struct drm_i915_private
*dev_priv
= to_i915(intel_dsi
->base
.base
.dev
);
132 struct mipi_dsi_device
*dsi_device
;
133 u8 type
, flags
, seq_port
;
142 len
= *((u16
*) data
);
145 seq_port
= (flags
>> MIPI_PORT_SHIFT
) & 3;
147 /* For DSI single link on Port A & C, the seq_port value which is
148 * parsed from Sequence Block#53 of VBT has been set to 0
149 * Now, read/write of packets for the DSI single link on Port A and
150 * Port C will based on the DVO port from VBT block 2.
152 if (intel_dsi
->ports
== (1 << PORT_C
))
155 port
= intel_dsi_seq_port_to_port(seq_port
);
157 dsi_device
= intel_dsi
->dsi_hosts
[port
]->device
;
159 DRM_DEBUG_KMS("no dsi device for port %c\n", port_name(port
));
163 if ((flags
>> MIPI_TRANSFER_MODE_SHIFT
) & 1)
164 dsi_device
->mode_flags
&= ~MIPI_DSI_MODE_LPM
;
166 dsi_device
->mode_flags
|= MIPI_DSI_MODE_LPM
;
168 dsi_device
->channel
= (flags
>> MIPI_VIRTUAL_CHANNEL_SHIFT
) & 3;
171 case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM
:
172 mipi_dsi_generic_write(dsi_device
, NULL
, 0);
174 case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM
:
175 mipi_dsi_generic_write(dsi_device
, data
, 1);
177 case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM
:
178 mipi_dsi_generic_write(dsi_device
, data
, 2);
180 case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM
:
181 case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM
:
182 case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM
:
183 DRM_DEBUG_DRIVER("Generic Read not yet implemented or used\n");
185 case MIPI_DSI_GENERIC_LONG_WRITE
:
186 mipi_dsi_generic_write(dsi_device
, data
, len
);
188 case MIPI_DSI_DCS_SHORT_WRITE
:
189 mipi_dsi_dcs_write_buffer(dsi_device
, data
, 1);
191 case MIPI_DSI_DCS_SHORT_WRITE_PARAM
:
192 mipi_dsi_dcs_write_buffer(dsi_device
, data
, 2);
194 case MIPI_DSI_DCS_READ
:
195 DRM_DEBUG_DRIVER("DCS Read not yet implemented or used\n");
197 case MIPI_DSI_DCS_LONG_WRITE
:
198 mipi_dsi_dcs_write_buffer(dsi_device
, data
, len
);
202 if (INTEL_GEN(dev_priv
) < 11)
203 vlv_dsi_wait_for_fifo_empty(intel_dsi
, port
);
211 static const u8
*mipi_exec_delay(struct intel_dsi
*intel_dsi
, const u8
*data
)
213 u32 delay
= *((const u32
*) data
);
217 usleep_range(delay
, delay
+ 10);
223 static void vlv_exec_gpio(struct drm_i915_private
*dev_priv
,
224 u8 gpio_source
, u8 gpio_index
, bool value
)
226 struct gpio_map
*map
;
231 if (gpio_index
>= ARRAY_SIZE(vlv_gpio_table
)) {
232 DRM_DEBUG_KMS("unknown gpio index %u\n", gpio_index
);
236 map
= &vlv_gpio_table
[gpio_index
];
238 if (dev_priv
->vbt
.dsi
.seq_version
>= 3) {
239 /* XXX: this assumes vlv_gpio_table only has NC GPIOs. */
240 port
= IOSF_PORT_GPIO_NC
;
242 if (gpio_source
== 0) {
243 port
= IOSF_PORT_GPIO_NC
;
244 } else if (gpio_source
== 1) {
245 DRM_DEBUG_KMS("SC gpio not supported\n");
248 DRM_DEBUG_KMS("unknown gpio source %u\n", gpio_source
);
253 pconf0
= VLV_GPIO_PCONF0(map
->base_offset
);
254 padval
= VLV_GPIO_PAD_VAL(map
->base_offset
);
256 vlv_iosf_sb_get(dev_priv
, BIT(VLV_IOSF_SB_GPIO
));
258 /* FIXME: remove constant below */
259 vlv_iosf_sb_write(dev_priv
, port
, pconf0
, 0x2000CC00);
264 vlv_iosf_sb_write(dev_priv
, port
, padval
, tmp
);
265 vlv_iosf_sb_put(dev_priv
, BIT(VLV_IOSF_SB_GPIO
));
268 static void chv_exec_gpio(struct drm_i915_private
*dev_priv
,
269 u8 gpio_source
, u8 gpio_index
, bool value
)
275 if (dev_priv
->vbt
.dsi
.seq_version
>= 3) {
276 if (gpio_index
>= CHV_GPIO_IDX_START_SE
) {
277 /* XXX: it's unclear whether 255->57 is part of SE. */
278 gpio_index
-= CHV_GPIO_IDX_START_SE
;
279 port
= CHV_IOSF_PORT_GPIO_SE
;
280 } else if (gpio_index
>= CHV_GPIO_IDX_START_SW
) {
281 gpio_index
-= CHV_GPIO_IDX_START_SW
;
282 port
= CHV_IOSF_PORT_GPIO_SW
;
283 } else if (gpio_index
>= CHV_GPIO_IDX_START_E
) {
284 gpio_index
-= CHV_GPIO_IDX_START_E
;
285 port
= CHV_IOSF_PORT_GPIO_E
;
287 port
= CHV_IOSF_PORT_GPIO_N
;
290 /* XXX: The spec is unclear about CHV GPIO on seq v2 */
291 if (gpio_source
!= 0) {
292 DRM_DEBUG_KMS("unknown gpio source %u\n", gpio_source
);
296 if (gpio_index
>= CHV_GPIO_IDX_START_E
) {
297 DRM_DEBUG_KMS("invalid gpio index %u for GPIO N\n",
302 port
= CHV_IOSF_PORT_GPIO_N
;
305 family_num
= gpio_index
/ CHV_VBT_MAX_PINS_PER_FMLY
;
306 gpio_index
= gpio_index
% CHV_VBT_MAX_PINS_PER_FMLY
;
308 cfg0
= CHV_GPIO_PAD_CFG0(family_num
, gpio_index
);
309 cfg1
= CHV_GPIO_PAD_CFG1(family_num
, gpio_index
);
311 vlv_iosf_sb_get(dev_priv
, BIT(VLV_IOSF_SB_GPIO
));
312 vlv_iosf_sb_write(dev_priv
, port
, cfg1
, 0);
313 vlv_iosf_sb_write(dev_priv
, port
, cfg0
,
314 CHV_GPIO_GPIOEN
| CHV_GPIO_GPIOCFG_GPO
|
315 CHV_GPIO_GPIOTXSTATE(value
));
316 vlv_iosf_sb_put(dev_priv
, BIT(VLV_IOSF_SB_GPIO
));
319 static void bxt_exec_gpio(struct drm_i915_private
*dev_priv
,
320 u8 gpio_source
, u8 gpio_index
, bool value
)
322 /* XXX: this table is a quick ugly hack. */
323 static struct gpio_desc
*bxt_gpio_table
[U8_MAX
+ 1];
324 struct gpio_desc
*gpio_desc
= bxt_gpio_table
[gpio_index
];
327 gpio_desc
= devm_gpiod_get_index(dev_priv
->drm
.dev
,
329 value
? GPIOD_OUT_LOW
:
332 if (IS_ERR_OR_NULL(gpio_desc
)) {
333 DRM_ERROR("GPIO index %u request failed (%ld)\n",
334 gpio_index
, PTR_ERR(gpio_desc
));
338 bxt_gpio_table
[gpio_index
] = gpio_desc
;
341 gpiod_set_value(gpio_desc
, value
);
344 static void icl_exec_gpio(struct drm_i915_private
*dev_priv
,
345 u8 gpio_source
, u8 gpio_index
, bool value
)
347 DRM_DEBUG_KMS("Skipping ICL GPIO element execution\n");
350 static const u8
*mipi_exec_gpio(struct intel_dsi
*intel_dsi
, const u8
*data
)
352 struct drm_device
*dev
= intel_dsi
->base
.base
.dev
;
353 struct drm_i915_private
*dev_priv
= to_i915(dev
);
354 u8 gpio_source
, gpio_index
= 0, gpio_number
;
359 if (dev_priv
->vbt
.dsi
.seq_version
>= 3)
360 gpio_index
= *data
++;
362 gpio_number
= *data
++;
364 /* gpio source in sequence v2 only */
365 if (dev_priv
->vbt
.dsi
.seq_version
== 2)
366 gpio_source
= (*data
>> 1) & 3;
373 if (INTEL_GEN(dev_priv
) >= 11)
374 icl_exec_gpio(dev_priv
, gpio_source
, gpio_index
, value
);
375 else if (IS_VALLEYVIEW(dev_priv
))
376 vlv_exec_gpio(dev_priv
, gpio_source
, gpio_number
, value
);
377 else if (IS_CHERRYVIEW(dev_priv
))
378 chv_exec_gpio(dev_priv
, gpio_source
, gpio_number
, value
);
380 bxt_exec_gpio(dev_priv
, gpio_source
, gpio_index
, value
);
385 static const u8
*mipi_exec_i2c(struct intel_dsi
*intel_dsi
, const u8
*data
)
387 DRM_DEBUG_KMS("Skipping I2C element execution\n");
389 return data
+ *(data
+ 6) + 7;
392 static const u8
*mipi_exec_spi(struct intel_dsi
*intel_dsi
, const u8
*data
)
394 DRM_DEBUG_KMS("Skipping SPI element execution\n");
396 return data
+ *(data
+ 5) + 6;
399 static const u8
*mipi_exec_pmic(struct intel_dsi
*intel_dsi
, const u8
*data
)
401 #ifdef CONFIG_PMIC_OPREGION
402 u32 value
, mask
, reg_address
;
406 /* byte 0 aka PMIC Flag is reserved */
407 i2c_address
= get_unaligned_le16(data
+ 1);
408 reg_address
= get_unaligned_le32(data
+ 3);
409 value
= get_unaligned_le32(data
+ 7);
410 mask
= get_unaligned_le32(data
+ 11);
412 ret
= intel_soc_pmic_exec_mipi_pmic_seq_element(i2c_address
,
416 DRM_ERROR("%s failed, error: %d\n", __func__
, ret
);
418 DRM_ERROR("Your hardware requires CONFIG_PMIC_OPREGION and it is not set\n");
424 typedef const u8
* (*fn_mipi_elem_exec
)(struct intel_dsi
*intel_dsi
,
426 static const fn_mipi_elem_exec exec_elem
[] = {
427 [MIPI_SEQ_ELEM_SEND_PKT
] = mipi_exec_send_packet
,
428 [MIPI_SEQ_ELEM_DELAY
] = mipi_exec_delay
,
429 [MIPI_SEQ_ELEM_GPIO
] = mipi_exec_gpio
,
430 [MIPI_SEQ_ELEM_I2C
] = mipi_exec_i2c
,
431 [MIPI_SEQ_ELEM_SPI
] = mipi_exec_spi
,
432 [MIPI_SEQ_ELEM_PMIC
] = mipi_exec_pmic
,
436 * MIPI Sequence from VBT #53 parsing logic
437 * We have already separated each seqence during bios parsing
438 * Following is generic execution function for any sequence
441 static const char * const seq_name
[] = {
442 [MIPI_SEQ_DEASSERT_RESET
] = "MIPI_SEQ_DEASSERT_RESET",
443 [MIPI_SEQ_INIT_OTP
] = "MIPI_SEQ_INIT_OTP",
444 [MIPI_SEQ_DISPLAY_ON
] = "MIPI_SEQ_DISPLAY_ON",
445 [MIPI_SEQ_DISPLAY_OFF
] = "MIPI_SEQ_DISPLAY_OFF",
446 [MIPI_SEQ_ASSERT_RESET
] = "MIPI_SEQ_ASSERT_RESET",
447 [MIPI_SEQ_BACKLIGHT_ON
] = "MIPI_SEQ_BACKLIGHT_ON",
448 [MIPI_SEQ_BACKLIGHT_OFF
] = "MIPI_SEQ_BACKLIGHT_OFF",
449 [MIPI_SEQ_TEAR_ON
] = "MIPI_SEQ_TEAR_ON",
450 [MIPI_SEQ_TEAR_OFF
] = "MIPI_SEQ_TEAR_OFF",
451 [MIPI_SEQ_POWER_ON
] = "MIPI_SEQ_POWER_ON",
452 [MIPI_SEQ_POWER_OFF
] = "MIPI_SEQ_POWER_OFF",
455 static const char *sequence_name(enum mipi_seq seq_id
)
457 if (seq_id
< ARRAY_SIZE(seq_name
) && seq_name
[seq_id
])
458 return seq_name
[seq_id
];
463 void intel_dsi_vbt_exec_sequence(struct intel_dsi
*intel_dsi
,
464 enum mipi_seq seq_id
)
466 struct drm_i915_private
*dev_priv
= to_i915(intel_dsi
->base
.base
.dev
);
468 fn_mipi_elem_exec mipi_elem_exec
;
470 if (WARN_ON(seq_id
>= ARRAY_SIZE(dev_priv
->vbt
.dsi
.sequence
)))
473 data
= dev_priv
->vbt
.dsi
.sequence
[seq_id
];
477 WARN_ON(*data
!= seq_id
);
479 DRM_DEBUG_KMS("Starting MIPI sequence %d - %s\n",
480 seq_id
, sequence_name(seq_id
));
482 /* Skip Sequence Byte. */
485 /* Skip Size of Sequence. */
486 if (dev_priv
->vbt
.dsi
.seq_version
>= 3)
490 u8 operation_byte
= *data
++;
491 u8 operation_size
= 0;
493 if (operation_byte
== MIPI_SEQ_ELEM_END
)
496 if (operation_byte
< ARRAY_SIZE(exec_elem
))
497 mipi_elem_exec
= exec_elem
[operation_byte
];
499 mipi_elem_exec
= NULL
;
501 /* Size of Operation. */
502 if (dev_priv
->vbt
.dsi
.seq_version
>= 3)
503 operation_size
= *data
++;
505 if (mipi_elem_exec
) {
506 const u8
*next
= data
+ operation_size
;
508 data
= mipi_elem_exec(intel_dsi
, data
);
510 /* Consistency check if we have size. */
511 if (operation_size
&& data
!= next
) {
512 DRM_ERROR("Inconsistent operation size\n");
515 } else if (operation_size
) {
516 /* We have size, skip. */
517 DRM_DEBUG_KMS("Unsupported MIPI operation byte %u\n",
519 data
+= operation_size
;
521 /* No size, can't skip without parsing. */
522 DRM_ERROR("Unsupported MIPI operation byte %u\n",
529 void intel_dsi_msleep(struct intel_dsi
*intel_dsi
, int msec
)
531 struct drm_i915_private
*dev_priv
= to_i915(intel_dsi
->base
.base
.dev
);
533 /* For v3 VBTs in vid-mode the delays are part of the VBT sequences */
534 if (is_vid_mode(intel_dsi
) && dev_priv
->vbt
.dsi
.seq_version
>= 3)
540 #define ICL_PREPARE_CNT_MAX 0x7
541 #define ICL_CLK_ZERO_CNT_MAX 0xf
542 #define ICL_TRAIL_CNT_MAX 0x7
543 #define ICL_TCLK_PRE_CNT_MAX 0x3
544 #define ICL_TCLK_POST_CNT_MAX 0x7
545 #define ICL_HS_ZERO_CNT_MAX 0xf
546 #define ICL_EXIT_ZERO_CNT_MAX 0x7
548 static void icl_dphy_param_init(struct intel_dsi
*intel_dsi
)
550 struct drm_device
*dev
= intel_dsi
->base
.base
.dev
;
551 struct drm_i915_private
*dev_priv
= to_i915(dev
);
552 struct mipi_config
*mipi_config
= dev_priv
->vbt
.dsi
.config
;
554 u32 prepare_cnt
, exit_zero_cnt
, clk_zero_cnt
, trail_cnt
;
555 u32 ths_prepare_ns
, tclk_trail_ns
;
557 u32 tclk_pre_cnt
, tclk_post_cnt
;
559 tlpx_ns
= intel_dsi_tlpx_ns(intel_dsi
);
561 tclk_trail_ns
= max(mipi_config
->tclk_trail
, mipi_config
->ths_trail
);
562 ths_prepare_ns
= max(mipi_config
->ths_prepare
,
563 mipi_config
->tclk_prepare
);
566 * prepare cnt in escape clocks
567 * this field represents a hexadecimal value with a precision
568 * of 1.2 – i.e. the most significant bit is the integer
569 * and the least significant 2 bits are fraction bits.
570 * so, the field can represent a range of 0.25 to 1.75
572 prepare_cnt
= DIV_ROUND_UP(ths_prepare_ns
* 4, tlpx_ns
);
573 if (prepare_cnt
> ICL_PREPARE_CNT_MAX
) {
574 DRM_DEBUG_KMS("prepare_cnt out of range (%d)\n", prepare_cnt
);
575 prepare_cnt
= ICL_PREPARE_CNT_MAX
;
578 /* clk zero count in escape clocks */
579 clk_zero_cnt
= DIV_ROUND_UP(mipi_config
->tclk_prepare_clkzero
-
580 ths_prepare_ns
, tlpx_ns
);
581 if (clk_zero_cnt
> ICL_CLK_ZERO_CNT_MAX
) {
582 DRM_DEBUG_KMS("clk_zero_cnt out of range (%d)\n", clk_zero_cnt
);
583 clk_zero_cnt
= ICL_CLK_ZERO_CNT_MAX
;
586 /* trail cnt in escape clocks*/
587 trail_cnt
= DIV_ROUND_UP(tclk_trail_ns
, tlpx_ns
);
588 if (trail_cnt
> ICL_TRAIL_CNT_MAX
) {
589 DRM_DEBUG_KMS("trail_cnt out of range (%d)\n", trail_cnt
);
590 trail_cnt
= ICL_TRAIL_CNT_MAX
;
593 /* tclk pre count in escape clocks */
594 tclk_pre_cnt
= DIV_ROUND_UP(mipi_config
->tclk_pre
, tlpx_ns
);
595 if (tclk_pre_cnt
> ICL_TCLK_PRE_CNT_MAX
) {
596 DRM_DEBUG_KMS("tclk_pre_cnt out of range (%d)\n", tclk_pre_cnt
);
597 tclk_pre_cnt
= ICL_TCLK_PRE_CNT_MAX
;
600 /* tclk post count in escape clocks */
601 tclk_post_cnt
= DIV_ROUND_UP(mipi_config
->tclk_post
, tlpx_ns
);
602 if (tclk_post_cnt
> ICL_TCLK_POST_CNT_MAX
) {
603 DRM_DEBUG_KMS("tclk_post_cnt out of range (%d)\n", tclk_post_cnt
);
604 tclk_post_cnt
= ICL_TCLK_POST_CNT_MAX
;
607 /* hs zero cnt in escape clocks */
608 hs_zero_cnt
= DIV_ROUND_UP(mipi_config
->ths_prepare_hszero
-
609 ths_prepare_ns
, tlpx_ns
);
610 if (hs_zero_cnt
> ICL_HS_ZERO_CNT_MAX
) {
611 DRM_DEBUG_KMS("hs_zero_cnt out of range (%d)\n", hs_zero_cnt
);
612 hs_zero_cnt
= ICL_HS_ZERO_CNT_MAX
;
615 /* hs exit zero cnt in escape clocks */
616 exit_zero_cnt
= DIV_ROUND_UP(mipi_config
->ths_exit
, tlpx_ns
);
617 if (exit_zero_cnt
> ICL_EXIT_ZERO_CNT_MAX
) {
618 DRM_DEBUG_KMS("exit_zero_cnt out of range (%d)\n", exit_zero_cnt
);
619 exit_zero_cnt
= ICL_EXIT_ZERO_CNT_MAX
;
622 /* clock lane dphy timings */
623 intel_dsi
->dphy_reg
= (CLK_PREPARE_OVERRIDE
|
624 CLK_PREPARE(prepare_cnt
) |
626 CLK_ZERO(clk_zero_cnt
) |
628 CLK_PRE(tclk_pre_cnt
) |
630 CLK_POST(tclk_post_cnt
) |
632 CLK_TRAIL(trail_cnt
));
634 /* data lanes dphy timings */
635 intel_dsi
->dphy_data_lane_reg
= (HS_PREPARE_OVERRIDE
|
636 HS_PREPARE(prepare_cnt
) |
638 HS_ZERO(hs_zero_cnt
) |
640 HS_TRAIL(trail_cnt
) |
642 HS_EXIT(exit_zero_cnt
));
645 static void vlv_dphy_param_init(struct intel_dsi
*intel_dsi
)
647 struct drm_device
*dev
= intel_dsi
->base
.base
.dev
;
648 struct drm_i915_private
*dev_priv
= to_i915(dev
);
649 struct mipi_config
*mipi_config
= dev_priv
->vbt
.dsi
.config
;
650 u32 tlpx_ns
, extra_byte_count
, tlpx_ui
;
652 u32 prepare_cnt
, exit_zero_cnt
, clk_zero_cnt
, trail_cnt
;
653 u32 ths_prepare_ns
, tclk_trail_ns
;
654 u32 tclk_prepare_clkzero
, ths_prepare_hszero
;
655 u32 lp_to_hs_switch
, hs_to_lp_switch
;
658 tlpx_ns
= intel_dsi_tlpx_ns(intel_dsi
);
660 switch (intel_dsi
->lane_count
) {
663 extra_byte_count
= 2;
666 extra_byte_count
= 4;
670 extra_byte_count
= 3;
675 ui_num
= NS_KHZ_RATIO
;
676 ui_den
= intel_dsi_bitrate(intel_dsi
);
678 tclk_prepare_clkzero
= mipi_config
->tclk_prepare_clkzero
;
679 ths_prepare_hszero
= mipi_config
->ths_prepare_hszero
;
683 * LP byte clock = TLPX/ (8UI)
685 intel_dsi
->lp_byte_clk
= DIV_ROUND_UP(tlpx_ns
* ui_den
, 8 * ui_num
);
687 /* DDR clock period = 2 * UI
688 * UI(sec) = 1/(bitrate * 10^3) (bitrate is in KHZ)
689 * UI(nsec) = 10^6 / bitrate
690 * DDR clock period (nsec) = 2 * UI = (2 * 10^6)/ bitrate
691 * DDR clock count = ns_value / DDR clock period
693 * For GEMINILAKE dphy_param_reg will be programmed in terms of
694 * HS byte clock count for other platform in HS ddr clock count
696 mul
= IS_GEMINILAKE(dev_priv
) ? 8 : 2;
697 ths_prepare_ns
= max(mipi_config
->ths_prepare
,
698 mipi_config
->tclk_prepare
);
701 prepare_cnt
= DIV_ROUND_UP(ths_prepare_ns
* ui_den
, ui_num
* mul
);
703 if (prepare_cnt
> PREPARE_CNT_MAX
) {
704 DRM_DEBUG_KMS("prepare count too high %u\n", prepare_cnt
);
705 prepare_cnt
= PREPARE_CNT_MAX
;
708 /* exit zero count */
709 exit_zero_cnt
= DIV_ROUND_UP(
710 (ths_prepare_hszero
- ths_prepare_ns
) * ui_den
,
715 * Exit zero is unified val ths_zero and ths_exit
716 * minimum value for ths_exit = 110ns
717 * min (exit_zero_cnt * 2) = 110/UI
718 * exit_zero_cnt = 55/UI
720 if (exit_zero_cnt
< (55 * ui_den
/ ui_num
) && (55 * ui_den
) % ui_num
)
723 if (exit_zero_cnt
> EXIT_ZERO_CNT_MAX
) {
724 DRM_DEBUG_KMS("exit zero count too high %u\n", exit_zero_cnt
);
725 exit_zero_cnt
= EXIT_ZERO_CNT_MAX
;
729 clk_zero_cnt
= DIV_ROUND_UP(
730 (tclk_prepare_clkzero
- ths_prepare_ns
)
731 * ui_den
, ui_num
* mul
);
733 if (clk_zero_cnt
> CLK_ZERO_CNT_MAX
) {
734 DRM_DEBUG_KMS("clock zero count too high %u\n", clk_zero_cnt
);
735 clk_zero_cnt
= CLK_ZERO_CNT_MAX
;
739 tclk_trail_ns
= max(mipi_config
->tclk_trail
, mipi_config
->ths_trail
);
740 trail_cnt
= DIV_ROUND_UP(tclk_trail_ns
* ui_den
, ui_num
* mul
);
742 if (trail_cnt
> TRAIL_CNT_MAX
) {
743 DRM_DEBUG_KMS("trail count too high %u\n", trail_cnt
);
744 trail_cnt
= TRAIL_CNT_MAX
;
748 intel_dsi
->dphy_reg
= exit_zero_cnt
<< 24 | trail_cnt
<< 16 |
749 clk_zero_cnt
<< 8 | prepare_cnt
;
752 * LP to HS switch count = 4TLPX + PREP_COUNT * mul + EXIT_ZERO_COUNT *
753 * mul + 10UI + Extra Byte Count
755 * HS to LP switch count = THS-TRAIL + 2TLPX + Extra Byte Count
756 * Extra Byte Count is calculated according to number of lanes.
757 * High Low Switch Count is the Max of LP to HS and
758 * HS to LP switch count
761 tlpx_ui
= DIV_ROUND_UP(tlpx_ns
* ui_den
, ui_num
);
765 * The comment above does not match with the code */
766 lp_to_hs_switch
= DIV_ROUND_UP(4 * tlpx_ui
+ prepare_cnt
* mul
+
767 exit_zero_cnt
* mul
+ 10, 8);
769 hs_to_lp_switch
= DIV_ROUND_UP(mipi_config
->ths_trail
+ 2 * tlpx_ui
, 8);
771 intel_dsi
->hs_to_lp_count
= max(lp_to_hs_switch
, hs_to_lp_switch
);
772 intel_dsi
->hs_to_lp_count
+= extra_byte_count
;
775 /* LP -> HS for clock lanes
776 * LP clk sync + LP11 + LP01 + tclk_prepare + tclk_zero +
778 * 2TPLX + 1TLPX + 1 TPLX(in ns) + prepare_cnt * 2 + clk_zero_cnt *
779 * 2(in UI) + extra byte count
780 * In byteclks = (4TLPX + prepare_cnt * 2 + clk_zero_cnt *2 (in UI)) /
781 * 8 + extra byte count
783 intel_dsi
->clk_lp_to_hs_count
=
785 4 * tlpx_ui
+ prepare_cnt
* 2 +
789 intel_dsi
->clk_lp_to_hs_count
+= extra_byte_count
;
791 /* HS->LP for Clock Lanes
792 * Low Power clock synchronisations + 1Tx byteclk + tclk_trail +
794 * 2TLPX + 8UI + (trail_count*2)(in UI) + Extra byte count
795 * In byteclks = (2*TLpx(in UI) + trail_count*2 +8)(in UI)/8 +
798 intel_dsi
->clk_hs_to_lp_count
=
799 DIV_ROUND_UP(2 * tlpx_ui
+ trail_cnt
* 2 + 8,
801 intel_dsi
->clk_hs_to_lp_count
+= extra_byte_count
;
804 bool intel_dsi_vbt_init(struct intel_dsi
*intel_dsi
, u16 panel_id
)
806 struct drm_device
*dev
= intel_dsi
->base
.base
.dev
;
807 struct drm_i915_private
*dev_priv
= to_i915(dev
);
808 struct mipi_config
*mipi_config
= dev_priv
->vbt
.dsi
.config
;
809 struct mipi_pps_data
*pps
= dev_priv
->vbt
.dsi
.pps
;
810 struct drm_display_mode
*mode
= dev_priv
->vbt
.lfp_lvds_vbt_mode
;
811 u16 burst_mode_ratio
;
816 intel_dsi
->eotp_pkt
= mipi_config
->eot_pkt_disabled
? 0 : 1;
817 intel_dsi
->clock_stop
= mipi_config
->enable_clk_stop
? 1 : 0;
818 intel_dsi
->lane_count
= mipi_config
->lane_cnt
+ 1;
819 intel_dsi
->pixel_format
=
820 pixel_format_from_register_bits(
821 mipi_config
->videomode_color_format
<< 7);
823 intel_dsi
->dual_link
= mipi_config
->dual_link
;
824 intel_dsi
->pixel_overlap
= mipi_config
->pixel_overlap
;
825 intel_dsi
->operation_mode
= mipi_config
->is_cmd_mode
;
826 intel_dsi
->video_mode_format
= mipi_config
->video_transfer_mode
;
827 intel_dsi
->escape_clk_div
= mipi_config
->byte_clk_sel
;
828 intel_dsi
->lp_rx_timeout
= mipi_config
->lp_rx_timeout
;
829 intel_dsi
->hs_tx_timeout
= mipi_config
->hs_tx_timeout
;
830 intel_dsi
->turn_arnd_val
= mipi_config
->turn_around_timeout
;
831 intel_dsi
->rst_timer_val
= mipi_config
->device_reset_timer
;
832 intel_dsi
->init_count
= mipi_config
->master_init_timer
;
833 intel_dsi
->bw_timer
= mipi_config
->dbi_bw_timer
;
834 intel_dsi
->video_frmt_cfg_bits
=
835 mipi_config
->bta_enabled
? DISABLE_VIDEO_BTA
: 0;
836 intel_dsi
->bgr_enabled
= mipi_config
->rgb_flip
;
838 /* Starting point, adjusted depending on dual link and burst mode */
839 intel_dsi
->pclk
= mode
->clock
;
841 /* In dual link mode each port needs half of pixel clock */
842 if (intel_dsi
->dual_link
) {
843 intel_dsi
->pclk
/= 2;
845 /* we can enable pixel_overlap if needed by panel. In this
846 * case we need to increase the pixelclock for extra pixels
848 if (intel_dsi
->dual_link
== DSI_DUAL_LINK_FRONT_BACK
) {
849 intel_dsi
->pclk
+= DIV_ROUND_UP(mode
->vtotal
* intel_dsi
->pixel_overlap
* 60, 1000);
854 * Target ddr frequency from VBT / non burst ddr freq
855 * multiply by 100 to preserve remainder
857 if (intel_dsi
->video_mode_format
== VIDEO_MODE_BURST
) {
858 if (mipi_config
->target_burst_mode_freq
) {
859 u32 bitrate
= intel_dsi_bitrate(intel_dsi
);
861 if (mipi_config
->target_burst_mode_freq
< bitrate
) {
862 DRM_ERROR("Burst mode freq is less than computed\n");
866 burst_mode_ratio
= DIV_ROUND_UP(
867 mipi_config
->target_burst_mode_freq
* 100,
870 intel_dsi
->pclk
= DIV_ROUND_UP(intel_dsi
->pclk
* burst_mode_ratio
, 100);
872 DRM_ERROR("Burst mode target is not set\n");
876 burst_mode_ratio
= 100;
878 intel_dsi
->burst_mode_ratio
= burst_mode_ratio
;
880 if (INTEL_GEN(dev_priv
) >= 11)
881 icl_dphy_param_init(intel_dsi
);
883 vlv_dphy_param_init(intel_dsi
);
885 DRM_DEBUG_KMS("Pclk %d\n", intel_dsi
->pclk
);
886 DRM_DEBUG_KMS("Pixel overlap %d\n", intel_dsi
->pixel_overlap
);
887 DRM_DEBUG_KMS("Lane count %d\n", intel_dsi
->lane_count
);
888 DRM_DEBUG_KMS("DPHY param reg 0x%x\n", intel_dsi
->dphy_reg
);
889 DRM_DEBUG_KMS("Video mode format %s\n",
890 intel_dsi
->video_mode_format
== VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE
?
891 "non-burst with sync pulse" :
892 intel_dsi
->video_mode_format
== VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS
?
893 "non-burst with sync events" :
894 intel_dsi
->video_mode_format
== VIDEO_MODE_BURST
?
895 "burst" : "<unknown>");
896 DRM_DEBUG_KMS("Burst mode ratio %d\n", intel_dsi
->burst_mode_ratio
);
897 DRM_DEBUG_KMS("Reset timer %d\n", intel_dsi
->rst_timer_val
);
898 DRM_DEBUG_KMS("Eot %s\n", enableddisabled(intel_dsi
->eotp_pkt
));
899 DRM_DEBUG_KMS("Clockstop %s\n", enableddisabled(!intel_dsi
->clock_stop
));
900 DRM_DEBUG_KMS("Mode %s\n", intel_dsi
->operation_mode
? "command" : "video");
901 if (intel_dsi
->dual_link
== DSI_DUAL_LINK_FRONT_BACK
)
902 DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_FRONT_BACK\n");
903 else if (intel_dsi
->dual_link
== DSI_DUAL_LINK_PIXEL_ALT
)
904 DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_PIXEL_ALT\n");
906 DRM_DEBUG_KMS("Dual link: NONE\n");
907 DRM_DEBUG_KMS("Pixel Format %d\n", intel_dsi
->pixel_format
);
908 DRM_DEBUG_KMS("TLPX %d\n", intel_dsi
->escape_clk_div
);
909 DRM_DEBUG_KMS("LP RX Timeout 0x%x\n", intel_dsi
->lp_rx_timeout
);
910 DRM_DEBUG_KMS("Turnaround Timeout 0x%x\n", intel_dsi
->turn_arnd_val
);
911 DRM_DEBUG_KMS("Init Count 0x%x\n", intel_dsi
->init_count
);
912 DRM_DEBUG_KMS("HS to LP Count 0x%x\n", intel_dsi
->hs_to_lp_count
);
913 DRM_DEBUG_KMS("LP Byte Clock %d\n", intel_dsi
->lp_byte_clk
);
914 DRM_DEBUG_KMS("DBI BW Timer 0x%x\n", intel_dsi
->bw_timer
);
915 DRM_DEBUG_KMS("LP to HS Clock Count 0x%x\n", intel_dsi
->clk_lp_to_hs_count
);
916 DRM_DEBUG_KMS("HS to LP Clock Count 0x%x\n", intel_dsi
->clk_hs_to_lp_count
);
917 DRM_DEBUG_KMS("BTA %s\n",
918 enableddisabled(!(intel_dsi
->video_frmt_cfg_bits
& DISABLE_VIDEO_BTA
)));
920 /* delays in VBT are in unit of 100us, so need to convert
922 * Delay (100us) * 100 /1000 = Delay / 10 (ms) */
923 intel_dsi
->backlight_off_delay
= pps
->bl_disable_delay
/ 10;
924 intel_dsi
->backlight_on_delay
= pps
->bl_enable_delay
/ 10;
925 intel_dsi
->panel_on_delay
= pps
->panel_on_delay
/ 10;
926 intel_dsi
->panel_off_delay
= pps
->panel_off_delay
/ 10;
927 intel_dsi
->panel_pwr_cycle_delay
= pps
->panel_power_cycle_delay
/ 10;
929 /* a regular driver would get the device in probe */
930 for_each_dsi_port(port
, intel_dsi
->ports
) {
931 mipi_dsi_attach(intel_dsi
->dsi_hosts
[port
]->device
);