2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
25 * DOC: Frame Buffer Compression (FBC)
27 * FBC tries to save memory bandwidth (and so power consumption) by
28 * compressing the amount of memory used by the display. It is total
29 * transparent to user space and completely handled in the kernel.
31 * The benefits of FBC are mostly visible with solid backgrounds and
32 * variation-less patterns. It comes from keeping the memory footprint small
33 * and having fewer memory pages opened and accessed for refreshing the display.
35 * i915 is responsible to reserve stolen memory for FBC and configure its
36 * offset on proper registers. The hardware takes care of all
37 * compress/decompress. However there are many known cases where we have to
38 * forcibly disable it to allow proper screen updates.
41 #include <drm/drm_fourcc.h>
43 #include "intel_drv.h"
46 static inline bool fbc_supported(struct drm_i915_private
*dev_priv
)
48 return HAS_FBC(dev_priv
);
51 static inline bool no_fbc_on_multiple_pipes(struct drm_i915_private
*dev_priv
)
53 return INTEL_GEN(dev_priv
) <= 3;
57 * In some platforms where the CRTC's x:0/y:0 coordinates doesn't match the
58 * frontbuffer's x:0/y:0 coordinates we lie to the hardware about the plane's
59 * origin so the x and y offsets can actually fit the registers. As a
60 * consequence, the fence doesn't really start exactly at the display plane
61 * address we program because it starts at the real start of the buffer, so we
62 * have to take this into consideration here.
64 static unsigned int get_crtc_fence_y_offset(struct intel_fbc
*fbc
)
66 return fbc
->state_cache
.plane
.y
- fbc
->state_cache
.plane
.adjusted_y
;
70 * For SKL+, the plane source size used by the hardware is based on the value we
71 * write to the PLANE_SIZE register. For BDW-, the hardware looks at the value
72 * we wrote to PIPESRC.
74 static void intel_fbc_get_plane_source_size(struct intel_fbc_state_cache
*cache
,
75 int *width
, int *height
)
78 *width
= cache
->plane
.src_w
;
80 *height
= cache
->plane
.src_h
;
83 static int intel_fbc_calculate_cfb_size(struct drm_i915_private
*dev_priv
,
84 struct intel_fbc_state_cache
*cache
)
88 intel_fbc_get_plane_source_size(cache
, NULL
, &lines
);
89 if (IS_GEN(dev_priv
, 7))
90 lines
= min(lines
, 2048);
91 else if (INTEL_GEN(dev_priv
) >= 8)
92 lines
= min(lines
, 2560);
94 /* Hardware needs the full buffer stride, not just the active area. */
95 return lines
* cache
->fb
.stride
;
98 static void i8xx_fbc_deactivate(struct drm_i915_private
*dev_priv
)
102 /* Disable compression */
103 fbc_ctl
= I915_READ(FBC_CONTROL
);
104 if ((fbc_ctl
& FBC_CTL_EN
) == 0)
107 fbc_ctl
&= ~FBC_CTL_EN
;
108 I915_WRITE(FBC_CONTROL
, fbc_ctl
);
110 /* Wait for compressing bit to clear */
111 if (intel_wait_for_register(dev_priv
,
112 FBC_STATUS
, FBC_STAT_COMPRESSING
, 0,
114 DRM_DEBUG_KMS("FBC idle timed out\n");
119 static void i8xx_fbc_activate(struct drm_i915_private
*dev_priv
)
121 struct intel_fbc_reg_params
*params
= &dev_priv
->fbc
.params
;
126 /* Note: fbc.threshold == 1 for i8xx */
127 cfb_pitch
= params
->cfb_size
/ FBC_LL_SIZE
;
128 if (params
->fb
.stride
< cfb_pitch
)
129 cfb_pitch
= params
->fb
.stride
;
131 /* FBC_CTL wants 32B or 64B units */
132 if (IS_GEN(dev_priv
, 2))
133 cfb_pitch
= (cfb_pitch
/ 32) - 1;
135 cfb_pitch
= (cfb_pitch
/ 64) - 1;
138 for (i
= 0; i
< (FBC_LL_SIZE
/ 32) + 1; i
++)
139 I915_WRITE(FBC_TAG(i
), 0);
141 if (IS_GEN(dev_priv
, 4)) {
145 fbc_ctl2
= FBC_CTL_FENCE_DBL
| FBC_CTL_IDLE_IMM
| FBC_CTL_CPU_FENCE
;
146 fbc_ctl2
|= FBC_CTL_PLANE(params
->crtc
.i9xx_plane
);
147 I915_WRITE(FBC_CONTROL2
, fbc_ctl2
);
148 I915_WRITE(FBC_FENCE_OFF
, params
->crtc
.fence_y_offset
);
152 fbc_ctl
= I915_READ(FBC_CONTROL
);
153 fbc_ctl
&= 0x3fff << FBC_CTL_INTERVAL_SHIFT
;
154 fbc_ctl
|= FBC_CTL_EN
| FBC_CTL_PERIODIC
;
155 if (IS_I945GM(dev_priv
))
156 fbc_ctl
|= FBC_CTL_C3_IDLE
; /* 945 needs special SR handling */
157 fbc_ctl
|= (cfb_pitch
& 0xff) << FBC_CTL_STRIDE_SHIFT
;
158 fbc_ctl
|= params
->vma
->fence
->id
;
159 I915_WRITE(FBC_CONTROL
, fbc_ctl
);
162 static bool i8xx_fbc_is_active(struct drm_i915_private
*dev_priv
)
164 return I915_READ(FBC_CONTROL
) & FBC_CTL_EN
;
167 static void g4x_fbc_activate(struct drm_i915_private
*dev_priv
)
169 struct intel_fbc_reg_params
*params
= &dev_priv
->fbc
.params
;
172 dpfc_ctl
= DPFC_CTL_PLANE(params
->crtc
.i9xx_plane
) | DPFC_SR_EN
;
173 if (params
->fb
.format
->cpp
[0] == 2)
174 dpfc_ctl
|= DPFC_CTL_LIMIT_2X
;
176 dpfc_ctl
|= DPFC_CTL_LIMIT_1X
;
178 if (params
->flags
& PLANE_HAS_FENCE
) {
179 dpfc_ctl
|= DPFC_CTL_FENCE_EN
| params
->vma
->fence
->id
;
180 I915_WRITE(DPFC_FENCE_YOFF
, params
->crtc
.fence_y_offset
);
182 I915_WRITE(DPFC_FENCE_YOFF
, 0);
186 I915_WRITE(DPFC_CONTROL
, dpfc_ctl
| DPFC_CTL_EN
);
189 static void g4x_fbc_deactivate(struct drm_i915_private
*dev_priv
)
193 /* Disable compression */
194 dpfc_ctl
= I915_READ(DPFC_CONTROL
);
195 if (dpfc_ctl
& DPFC_CTL_EN
) {
196 dpfc_ctl
&= ~DPFC_CTL_EN
;
197 I915_WRITE(DPFC_CONTROL
, dpfc_ctl
);
201 static bool g4x_fbc_is_active(struct drm_i915_private
*dev_priv
)
203 return I915_READ(DPFC_CONTROL
) & DPFC_CTL_EN
;
206 /* This function forces a CFB recompression through the nuke operation. */
207 static void intel_fbc_recompress(struct drm_i915_private
*dev_priv
)
209 I915_WRITE(MSG_FBC_REND_STATE
, FBC_REND_NUKE
);
210 POSTING_READ(MSG_FBC_REND_STATE
);
213 static void ilk_fbc_activate(struct drm_i915_private
*dev_priv
)
215 struct intel_fbc_reg_params
*params
= &dev_priv
->fbc
.params
;
217 int threshold
= dev_priv
->fbc
.threshold
;
219 dpfc_ctl
= DPFC_CTL_PLANE(params
->crtc
.i9xx_plane
);
220 if (params
->fb
.format
->cpp
[0] == 2)
226 dpfc_ctl
|= DPFC_CTL_LIMIT_4X
;
229 dpfc_ctl
|= DPFC_CTL_LIMIT_2X
;
232 dpfc_ctl
|= DPFC_CTL_LIMIT_1X
;
236 if (params
->flags
& PLANE_HAS_FENCE
) {
237 dpfc_ctl
|= DPFC_CTL_FENCE_EN
;
238 if (IS_GEN(dev_priv
, 5))
239 dpfc_ctl
|= params
->vma
->fence
->id
;
240 if (IS_GEN(dev_priv
, 6)) {
241 I915_WRITE(SNB_DPFC_CTL_SA
,
242 SNB_CPU_FENCE_ENABLE
|
243 params
->vma
->fence
->id
);
244 I915_WRITE(DPFC_CPU_FENCE_OFFSET
,
245 params
->crtc
.fence_y_offset
);
248 if (IS_GEN(dev_priv
, 6)) {
249 I915_WRITE(SNB_DPFC_CTL_SA
, 0);
250 I915_WRITE(DPFC_CPU_FENCE_OFFSET
, 0);
254 I915_WRITE(ILK_DPFC_FENCE_YOFF
, params
->crtc
.fence_y_offset
);
255 I915_WRITE(ILK_FBC_RT_BASE
,
256 i915_ggtt_offset(params
->vma
) | ILK_FBC_RT_VALID
);
258 I915_WRITE(ILK_DPFC_CONTROL
, dpfc_ctl
| DPFC_CTL_EN
);
260 intel_fbc_recompress(dev_priv
);
263 static void ilk_fbc_deactivate(struct drm_i915_private
*dev_priv
)
267 /* Disable compression */
268 dpfc_ctl
= I915_READ(ILK_DPFC_CONTROL
);
269 if (dpfc_ctl
& DPFC_CTL_EN
) {
270 dpfc_ctl
&= ~DPFC_CTL_EN
;
271 I915_WRITE(ILK_DPFC_CONTROL
, dpfc_ctl
);
275 static bool ilk_fbc_is_active(struct drm_i915_private
*dev_priv
)
277 return I915_READ(ILK_DPFC_CONTROL
) & DPFC_CTL_EN
;
280 static void gen7_fbc_activate(struct drm_i915_private
*dev_priv
)
282 struct intel_fbc_reg_params
*params
= &dev_priv
->fbc
.params
;
284 int threshold
= dev_priv
->fbc
.threshold
;
286 /* Display WA #0529: skl, kbl, bxt. */
287 if (IS_GEN(dev_priv
, 9) && !IS_GEMINILAKE(dev_priv
)) {
288 u32 val
= I915_READ(CHICKEN_MISC_4
);
290 val
&= ~(FBC_STRIDE_OVERRIDE
| FBC_STRIDE_MASK
);
292 if (i915_gem_object_get_tiling(params
->vma
->obj
) !=
294 val
|= FBC_STRIDE_OVERRIDE
| params
->gen9_wa_cfb_stride
;
296 I915_WRITE(CHICKEN_MISC_4
, val
);
300 if (IS_IVYBRIDGE(dev_priv
))
301 dpfc_ctl
|= IVB_DPFC_CTL_PLANE(params
->crtc
.i9xx_plane
);
303 if (params
->fb
.format
->cpp
[0] == 2)
309 dpfc_ctl
|= DPFC_CTL_LIMIT_4X
;
312 dpfc_ctl
|= DPFC_CTL_LIMIT_2X
;
315 dpfc_ctl
|= DPFC_CTL_LIMIT_1X
;
319 if (params
->flags
& PLANE_HAS_FENCE
) {
320 dpfc_ctl
|= IVB_DPFC_CTL_FENCE_EN
;
321 I915_WRITE(SNB_DPFC_CTL_SA
,
322 SNB_CPU_FENCE_ENABLE
|
323 params
->vma
->fence
->id
);
324 I915_WRITE(DPFC_CPU_FENCE_OFFSET
, params
->crtc
.fence_y_offset
);
326 I915_WRITE(SNB_DPFC_CTL_SA
,0);
327 I915_WRITE(DPFC_CPU_FENCE_OFFSET
, 0);
330 if (dev_priv
->fbc
.false_color
)
331 dpfc_ctl
|= FBC_CTL_FALSE_COLOR
;
333 if (IS_IVYBRIDGE(dev_priv
)) {
334 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
335 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
336 I915_READ(ILK_DISPLAY_CHICKEN1
) |
338 } else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
339 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
340 I915_WRITE(CHICKEN_PIPESL_1(params
->crtc
.pipe
),
341 I915_READ(CHICKEN_PIPESL_1(params
->crtc
.pipe
)) |
345 I915_WRITE(ILK_DPFC_CONTROL
, dpfc_ctl
| DPFC_CTL_EN
);
347 intel_fbc_recompress(dev_priv
);
350 static bool intel_fbc_hw_is_active(struct drm_i915_private
*dev_priv
)
352 if (INTEL_GEN(dev_priv
) >= 5)
353 return ilk_fbc_is_active(dev_priv
);
354 else if (IS_GM45(dev_priv
))
355 return g4x_fbc_is_active(dev_priv
);
357 return i8xx_fbc_is_active(dev_priv
);
360 static void intel_fbc_hw_activate(struct drm_i915_private
*dev_priv
)
362 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
366 if (INTEL_GEN(dev_priv
) >= 7)
367 gen7_fbc_activate(dev_priv
);
368 else if (INTEL_GEN(dev_priv
) >= 5)
369 ilk_fbc_activate(dev_priv
);
370 else if (IS_GM45(dev_priv
))
371 g4x_fbc_activate(dev_priv
);
373 i8xx_fbc_activate(dev_priv
);
376 static void intel_fbc_hw_deactivate(struct drm_i915_private
*dev_priv
)
378 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
382 if (INTEL_GEN(dev_priv
) >= 5)
383 ilk_fbc_deactivate(dev_priv
);
384 else if (IS_GM45(dev_priv
))
385 g4x_fbc_deactivate(dev_priv
);
387 i8xx_fbc_deactivate(dev_priv
);
391 * intel_fbc_is_active - Is FBC active?
392 * @dev_priv: i915 device instance
394 * This function is used to verify the current state of FBC.
396 * FIXME: This should be tracked in the plane config eventually
397 * instead of queried at runtime for most callers.
399 bool intel_fbc_is_active(struct drm_i915_private
*dev_priv
)
401 return dev_priv
->fbc
.active
;
404 static void intel_fbc_deactivate(struct drm_i915_private
*dev_priv
,
407 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
409 WARN_ON(!mutex_is_locked(&fbc
->lock
));
412 intel_fbc_hw_deactivate(dev_priv
);
414 fbc
->no_fbc_reason
= reason
;
417 static bool multiple_pipes_ok(struct intel_crtc
*crtc
,
418 struct intel_plane_state
*plane_state
)
420 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
421 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
422 enum pipe pipe
= crtc
->pipe
;
424 /* Don't even bother tracking anything we don't need. */
425 if (!no_fbc_on_multiple_pipes(dev_priv
))
428 if (plane_state
->base
.visible
)
429 fbc
->visible_pipes_mask
|= (1 << pipe
);
431 fbc
->visible_pipes_mask
&= ~(1 << pipe
);
433 return (fbc
->visible_pipes_mask
& ~(1 << pipe
)) != 0;
436 static int find_compression_threshold(struct drm_i915_private
*dev_priv
,
437 struct drm_mm_node
*node
,
441 int compression_threshold
= 1;
445 /* The FBC hardware for BDW/SKL doesn't have access to the stolen
446 * reserved range size, so it always assumes the maximum (8mb) is used.
447 * If we enable FBC using a CFB on that memory range we'll get FIFO
448 * underruns, even if that range is not reserved by the BIOS. */
449 if (IS_BROADWELL(dev_priv
) || IS_GEN9_BC(dev_priv
))
450 end
= resource_size(&dev_priv
->dsm
) - 8 * 1024 * 1024;
454 /* HACK: This code depends on what we will do in *_enable_fbc. If that
455 * code changes, this code needs to change as well.
457 * The enable_fbc code will attempt to use one of our 2 compression
458 * thresholds, therefore, in that case, we only have 1 resort.
461 /* Try to over-allocate to reduce reallocations and fragmentation. */
462 ret
= i915_gem_stolen_insert_node_in_range(dev_priv
, node
, size
<<= 1,
465 return compression_threshold
;
468 /* HW's ability to limit the CFB is 1:4 */
469 if (compression_threshold
> 4 ||
470 (fb_cpp
== 2 && compression_threshold
== 2))
473 ret
= i915_gem_stolen_insert_node_in_range(dev_priv
, node
, size
>>= 1,
475 if (ret
&& INTEL_GEN(dev_priv
) <= 4) {
478 compression_threshold
<<= 1;
481 return compression_threshold
;
485 static int intel_fbc_alloc_cfb(struct intel_crtc
*crtc
)
487 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
488 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
489 struct drm_mm_node
*uninitialized_var(compressed_llb
);
490 int size
, fb_cpp
, ret
;
492 WARN_ON(drm_mm_node_allocated(&fbc
->compressed_fb
));
494 size
= intel_fbc_calculate_cfb_size(dev_priv
, &fbc
->state_cache
);
495 fb_cpp
= fbc
->state_cache
.fb
.format
->cpp
[0];
497 ret
= find_compression_threshold(dev_priv
, &fbc
->compressed_fb
,
502 DRM_INFO("Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.\n");
506 fbc
->threshold
= ret
;
508 if (INTEL_GEN(dev_priv
) >= 5)
509 I915_WRITE(ILK_DPFC_CB_BASE
, fbc
->compressed_fb
.start
);
510 else if (IS_GM45(dev_priv
)) {
511 I915_WRITE(DPFC_CB_BASE
, fbc
->compressed_fb
.start
);
513 compressed_llb
= kzalloc(sizeof(*compressed_llb
), GFP_KERNEL
);
517 ret
= i915_gem_stolen_insert_node(dev_priv
, compressed_llb
,
522 fbc
->compressed_llb
= compressed_llb
;
524 GEM_BUG_ON(range_overflows_t(u64
, dev_priv
->dsm
.start
,
525 fbc
->compressed_fb
.start
,
527 GEM_BUG_ON(range_overflows_t(u64
, dev_priv
->dsm
.start
,
528 fbc
->compressed_llb
->start
,
530 I915_WRITE(FBC_CFB_BASE
,
531 dev_priv
->dsm
.start
+ fbc
->compressed_fb
.start
);
532 I915_WRITE(FBC_LL_BASE
,
533 dev_priv
->dsm
.start
+ compressed_llb
->start
);
536 DRM_DEBUG_KMS("reserved %llu bytes of contiguous stolen space for FBC, threshold: %d\n",
537 fbc
->compressed_fb
.size
, fbc
->threshold
);
542 kfree(compressed_llb
);
543 i915_gem_stolen_remove_node(dev_priv
, &fbc
->compressed_fb
);
545 if (drm_mm_initialized(&dev_priv
->mm
.stolen
))
546 pr_info_once("drm: not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this.\n", size
);
550 static void __intel_fbc_cleanup_cfb(struct drm_i915_private
*dev_priv
)
552 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
554 if (drm_mm_node_allocated(&fbc
->compressed_fb
))
555 i915_gem_stolen_remove_node(dev_priv
, &fbc
->compressed_fb
);
557 if (fbc
->compressed_llb
) {
558 i915_gem_stolen_remove_node(dev_priv
, fbc
->compressed_llb
);
559 kfree(fbc
->compressed_llb
);
563 void intel_fbc_cleanup_cfb(struct drm_i915_private
*dev_priv
)
565 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
567 if (!fbc_supported(dev_priv
))
570 mutex_lock(&fbc
->lock
);
571 __intel_fbc_cleanup_cfb(dev_priv
);
572 mutex_unlock(&fbc
->lock
);
575 static bool stride_is_valid(struct drm_i915_private
*dev_priv
,
578 /* This should have been caught earlier. */
579 if (WARN_ON_ONCE((stride
& (64 - 1)) != 0))
582 /* Below are the additional FBC restrictions. */
586 if (IS_GEN(dev_priv
, 2) || IS_GEN(dev_priv
, 3))
587 return stride
== 4096 || stride
== 8192;
589 if (IS_GEN(dev_priv
, 4) && !IS_G4X(dev_priv
) && stride
< 2048)
598 static bool pixel_format_is_valid(struct drm_i915_private
*dev_priv
,
601 switch (pixel_format
) {
602 case DRM_FORMAT_XRGB8888
:
603 case DRM_FORMAT_XBGR8888
:
605 case DRM_FORMAT_XRGB1555
:
606 case DRM_FORMAT_RGB565
:
607 /* 16bpp not supported on gen2 */
608 if (IS_GEN(dev_priv
, 2))
610 /* WaFbcOnly1to1Ratio:ctg */
611 if (IS_G4X(dev_priv
))
620 * For some reason, the hardware tracking starts looking at whatever we
621 * programmed as the display plane base address register. It does not look at
622 * the X and Y offset registers. That's why we look at the crtc->adjusted{x,y}
623 * variables instead of just looking at the pipe/plane size.
625 static bool intel_fbc_hw_tracking_covers_screen(struct intel_crtc
*crtc
)
627 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
628 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
629 unsigned int effective_w
, effective_h
, max_w
, max_h
;
631 if (INTEL_GEN(dev_priv
) >= 10 || IS_GEMINILAKE(dev_priv
)) {
634 } else if (INTEL_GEN(dev_priv
) >= 8 || IS_HASWELL(dev_priv
)) {
637 } else if (IS_G4X(dev_priv
) || INTEL_GEN(dev_priv
) >= 5) {
645 intel_fbc_get_plane_source_size(&fbc
->state_cache
, &effective_w
,
647 effective_w
+= fbc
->state_cache
.plane
.adjusted_x
;
648 effective_h
+= fbc
->state_cache
.plane
.adjusted_y
;
650 return effective_w
<= max_w
&& effective_h
<= max_h
;
653 static void intel_fbc_update_state_cache(struct intel_crtc
*crtc
,
654 struct intel_crtc_state
*crtc_state
,
655 struct intel_plane_state
*plane_state
)
657 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
658 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
659 struct intel_fbc_state_cache
*cache
= &fbc
->state_cache
;
660 struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
665 cache
->crtc
.mode_flags
= crtc_state
->base
.adjusted_mode
.flags
;
666 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
667 cache
->crtc
.hsw_bdw_pixel_rate
= crtc_state
->pixel_rate
;
669 cache
->plane
.rotation
= plane_state
->base
.rotation
;
671 * Src coordinates are already rotated by 270 degrees for
672 * the 90/270 degree plane rotation cases (to match the
673 * GTT mapping), hence no need to account for rotation here.
675 cache
->plane
.src_w
= drm_rect_width(&plane_state
->base
.src
) >> 16;
676 cache
->plane
.src_h
= drm_rect_height(&plane_state
->base
.src
) >> 16;
677 cache
->plane
.visible
= plane_state
->base
.visible
;
678 cache
->plane
.adjusted_x
= plane_state
->color_plane
[0].x
;
679 cache
->plane
.adjusted_y
= plane_state
->color_plane
[0].y
;
680 cache
->plane
.y
= plane_state
->base
.src
.y1
>> 16;
682 cache
->plane
.pixel_blend_mode
= plane_state
->base
.pixel_blend_mode
;
684 if (!cache
->plane
.visible
)
687 cache
->fb
.format
= fb
->format
;
688 cache
->fb
.stride
= fb
->pitches
[0];
690 cache
->vma
= plane_state
->vma
;
691 cache
->flags
= plane_state
->flags
;
692 if (WARN_ON(cache
->flags
& PLANE_HAS_FENCE
&& !cache
->vma
->fence
))
693 cache
->flags
&= ~PLANE_HAS_FENCE
;
696 static bool intel_fbc_can_activate(struct intel_crtc
*crtc
)
698 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
699 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
700 struct intel_fbc_state_cache
*cache
= &fbc
->state_cache
;
702 /* We don't need to use a state cache here since this information is
703 * global for all CRTC.
705 if (fbc
->underrun_detected
) {
706 fbc
->no_fbc_reason
= "underrun detected";
711 fbc
->no_fbc_reason
= "primary plane not visible";
715 if (cache
->crtc
.mode_flags
& DRM_MODE_FLAG_INTERLACE
) {
716 fbc
->no_fbc_reason
= "incompatible mode";
720 if (!intel_fbc_hw_tracking_covers_screen(crtc
)) {
721 fbc
->no_fbc_reason
= "mode too large for compression";
725 /* The use of a CPU fence is mandatory in order to detect writes
726 * by the CPU to the scanout and trigger updates to the FBC.
728 * Note that is possible for a tiled surface to be unmappable (and
729 * so have no fence associated with it) due to aperture constaints
730 * at the time of pinning.
732 * FIXME with 90/270 degree rotation we should use the fence on
733 * the normal GTT view (the rotated view doesn't even have a
734 * fence). Would need changes to the FBC fence Y offset as well.
735 * For now this will effecively disable FBC with 90/270 degree
738 if (!(cache
->flags
& PLANE_HAS_FENCE
)) {
739 fbc
->no_fbc_reason
= "framebuffer not tiled or fenced";
742 if (INTEL_GEN(dev_priv
) <= 4 && !IS_G4X(dev_priv
) &&
743 cache
->plane
.rotation
!= DRM_MODE_ROTATE_0
) {
744 fbc
->no_fbc_reason
= "rotation unsupported";
748 if (!stride_is_valid(dev_priv
, cache
->fb
.stride
)) {
749 fbc
->no_fbc_reason
= "framebuffer stride not supported";
753 if (!pixel_format_is_valid(dev_priv
, cache
->fb
.format
->format
)) {
754 fbc
->no_fbc_reason
= "pixel format is invalid";
758 if (cache
->plane
.pixel_blend_mode
!= DRM_MODE_BLEND_PIXEL_NONE
&&
759 cache
->fb
.format
->has_alpha
) {
760 fbc
->no_fbc_reason
= "per-pixel alpha blending is incompatible with FBC";
764 /* WaFbcExceedCdClockThreshold:hsw,bdw */
765 if ((IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) &&
766 cache
->crtc
.hsw_bdw_pixel_rate
>= dev_priv
->cdclk
.hw
.cdclk
* 95 / 100) {
767 fbc
->no_fbc_reason
= "pixel rate is too big";
771 /* It is possible for the required CFB size change without a
772 * crtc->disable + crtc->enable since it is possible to change the
773 * stride without triggering a full modeset. Since we try to
774 * over-allocate the CFB, there's a chance we may keep FBC enabled even
775 * if this happens, but if we exceed the current CFB size we'll have to
776 * disable FBC. Notice that it would be possible to disable FBC, wait
777 * for a frame, free the stolen node, then try to reenable FBC in case
778 * we didn't get any invalidate/deactivate calls, but this would require
779 * a lot of tracking just for a specific case. If we conclude it's an
780 * important case, we can implement it later. */
781 if (intel_fbc_calculate_cfb_size(dev_priv
, &fbc
->state_cache
) >
782 fbc
->compressed_fb
.size
* fbc
->threshold
) {
783 fbc
->no_fbc_reason
= "CFB requirements changed";
788 * Work around a problem on GEN9+ HW, where enabling FBC on a plane
789 * having a Y offset that isn't divisible by 4 causes FIFO underrun
790 * and screen flicker.
792 if (IS_GEN_RANGE(dev_priv
, 9, 10) &&
793 (fbc
->state_cache
.plane
.adjusted_y
& 3)) {
794 fbc
->no_fbc_reason
= "plane Y offset is misaligned";
801 static bool intel_fbc_can_enable(struct drm_i915_private
*dev_priv
)
803 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
805 if (intel_vgpu_active(dev_priv
)) {
806 fbc
->no_fbc_reason
= "VGPU is active";
810 if (!i915_modparams
.enable_fbc
) {
811 fbc
->no_fbc_reason
= "disabled per module param or by default";
815 if (fbc
->underrun_detected
) {
816 fbc
->no_fbc_reason
= "underrun detected";
823 static void intel_fbc_get_reg_params(struct intel_crtc
*crtc
,
824 struct intel_fbc_reg_params
*params
)
826 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
827 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
828 struct intel_fbc_state_cache
*cache
= &fbc
->state_cache
;
830 /* Since all our fields are integer types, use memset here so the
831 * comparison function can rely on memcmp because the padding will be
833 memset(params
, 0, sizeof(*params
));
835 params
->vma
= cache
->vma
;
836 params
->flags
= cache
->flags
;
838 params
->crtc
.pipe
= crtc
->pipe
;
839 params
->crtc
.i9xx_plane
= to_intel_plane(crtc
->base
.primary
)->i9xx_plane
;
840 params
->crtc
.fence_y_offset
= get_crtc_fence_y_offset(fbc
);
842 params
->fb
.format
= cache
->fb
.format
;
843 params
->fb
.stride
= cache
->fb
.stride
;
845 params
->cfb_size
= intel_fbc_calculate_cfb_size(dev_priv
, cache
);
847 if (IS_GEN(dev_priv
, 9) && !IS_GEMINILAKE(dev_priv
))
848 params
->gen9_wa_cfb_stride
= DIV_ROUND_UP(cache
->plane
.src_w
,
849 32 * fbc
->threshold
) * 8;
852 void intel_fbc_pre_update(struct intel_crtc
*crtc
,
853 struct intel_crtc_state
*crtc_state
,
854 struct intel_plane_state
*plane_state
)
856 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
857 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
858 const char *reason
= "update pending";
860 if (!fbc_supported(dev_priv
))
863 mutex_lock(&fbc
->lock
);
865 if (!multiple_pipes_ok(crtc
, plane_state
)) {
866 reason
= "more than one pipe active";
870 if (!fbc
->enabled
|| fbc
->crtc
!= crtc
)
873 intel_fbc_update_state_cache(crtc
, crtc_state
, plane_state
);
874 fbc
->flip_pending
= true;
877 intel_fbc_deactivate(dev_priv
, reason
);
879 mutex_unlock(&fbc
->lock
);
883 * __intel_fbc_disable - disable FBC
884 * @dev_priv: i915 device instance
886 * This is the low level function that actually disables FBC. Callers should
889 static void __intel_fbc_disable(struct drm_i915_private
*dev_priv
)
891 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
892 struct intel_crtc
*crtc
= fbc
->crtc
;
894 WARN_ON(!mutex_is_locked(&fbc
->lock
));
895 WARN_ON(!fbc
->enabled
);
896 WARN_ON(fbc
->active
);
898 DRM_DEBUG_KMS("Disabling FBC on pipe %c\n", pipe_name(crtc
->pipe
));
900 __intel_fbc_cleanup_cfb(dev_priv
);
902 fbc
->enabled
= false;
906 static void __intel_fbc_post_update(struct intel_crtc
*crtc
)
908 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
909 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
911 WARN_ON(!mutex_is_locked(&fbc
->lock
));
913 if (!fbc
->enabled
|| fbc
->crtc
!= crtc
)
916 fbc
->flip_pending
= false;
917 WARN_ON(fbc
->active
);
919 if (!i915_modparams
.enable_fbc
) {
920 intel_fbc_deactivate(dev_priv
, "disabled at runtime per module param");
921 __intel_fbc_disable(dev_priv
);
926 intel_fbc_get_reg_params(crtc
, &fbc
->params
);
928 if (!intel_fbc_can_activate(crtc
))
931 if (!fbc
->busy_bits
) {
932 intel_fbc_deactivate(dev_priv
, "FBC enabled (active or scheduled)");
933 intel_fbc_hw_activate(dev_priv
);
935 intel_fbc_deactivate(dev_priv
, "frontbuffer write");
938 void intel_fbc_post_update(struct intel_crtc
*crtc
)
940 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
941 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
943 if (!fbc_supported(dev_priv
))
946 mutex_lock(&fbc
->lock
);
947 __intel_fbc_post_update(crtc
);
948 mutex_unlock(&fbc
->lock
);
951 static unsigned int intel_fbc_get_frontbuffer_bit(struct intel_fbc
*fbc
)
954 return to_intel_plane(fbc
->crtc
->base
.primary
)->frontbuffer_bit
;
956 return fbc
->possible_framebuffer_bits
;
959 void intel_fbc_invalidate(struct drm_i915_private
*dev_priv
,
960 unsigned int frontbuffer_bits
,
961 enum fb_op_origin origin
)
963 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
965 if (!fbc_supported(dev_priv
))
968 if (origin
== ORIGIN_GTT
|| origin
== ORIGIN_FLIP
)
971 mutex_lock(&fbc
->lock
);
973 fbc
->busy_bits
|= intel_fbc_get_frontbuffer_bit(fbc
) & frontbuffer_bits
;
975 if (fbc
->enabled
&& fbc
->busy_bits
)
976 intel_fbc_deactivate(dev_priv
, "frontbuffer write");
978 mutex_unlock(&fbc
->lock
);
981 void intel_fbc_flush(struct drm_i915_private
*dev_priv
,
982 unsigned int frontbuffer_bits
, enum fb_op_origin origin
)
984 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
986 if (!fbc_supported(dev_priv
))
989 mutex_lock(&fbc
->lock
);
991 fbc
->busy_bits
&= ~frontbuffer_bits
;
993 if (origin
== ORIGIN_GTT
|| origin
== ORIGIN_FLIP
)
996 if (!fbc
->busy_bits
&& fbc
->enabled
&&
997 (frontbuffer_bits
& intel_fbc_get_frontbuffer_bit(fbc
))) {
999 intel_fbc_recompress(dev_priv
);
1000 else if (!fbc
->flip_pending
)
1001 __intel_fbc_post_update(fbc
->crtc
);
1005 mutex_unlock(&fbc
->lock
);
1009 * intel_fbc_choose_crtc - select a CRTC to enable FBC on
1010 * @dev_priv: i915 device instance
1011 * @state: the atomic state structure
1013 * This function looks at the proposed state for CRTCs and planes, then chooses
1014 * which pipe is going to have FBC by setting intel_crtc_state->enable_fbc to
1017 * Later, intel_fbc_enable is going to look for state->enable_fbc and then maybe
1018 * enable FBC for the chosen CRTC. If it does, it will set dev_priv->fbc.crtc.
1020 void intel_fbc_choose_crtc(struct drm_i915_private
*dev_priv
,
1021 struct intel_atomic_state
*state
)
1023 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
1024 struct intel_plane
*plane
;
1025 struct intel_plane_state
*plane_state
;
1026 bool crtc_chosen
= false;
1029 mutex_lock(&fbc
->lock
);
1031 /* Does this atomic commit involve the CRTC currently tied to FBC? */
1033 !intel_atomic_get_new_crtc_state(state
, fbc
->crtc
))
1036 if (!intel_fbc_can_enable(dev_priv
))
1039 /* Simply choose the first CRTC that is compatible and has a visible
1040 * plane. We could go for fancier schemes such as checking the plane
1041 * size, but this would just affect the few platforms that don't tie FBC
1042 * to pipe or plane A. */
1043 for_each_new_intel_plane_in_state(state
, plane
, plane_state
, i
) {
1044 struct intel_crtc_state
*crtc_state
;
1045 struct intel_crtc
*crtc
= to_intel_crtc(plane_state
->base
.crtc
);
1047 if (!plane
->has_fbc
)
1050 if (!plane_state
->base
.visible
)
1053 crtc_state
= intel_atomic_get_new_crtc_state(state
, crtc
);
1055 crtc_state
->enable_fbc
= true;
1061 fbc
->no_fbc_reason
= "no suitable CRTC for FBC";
1064 mutex_unlock(&fbc
->lock
);
1068 * intel_fbc_enable: tries to enable FBC on the CRTC
1070 * @crtc_state: corresponding &drm_crtc_state for @crtc
1071 * @plane_state: corresponding &drm_plane_state for the primary plane of @crtc
1073 * This function checks if the given CRTC was chosen for FBC, then enables it if
1074 * possible. Notice that it doesn't activate FBC. It is valid to call
1075 * intel_fbc_enable multiple times for the same pipe without an
1076 * intel_fbc_disable in the middle, as long as it is deactivated.
1078 void intel_fbc_enable(struct intel_crtc
*crtc
,
1079 struct intel_crtc_state
*crtc_state
,
1080 struct intel_plane_state
*plane_state
)
1082 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1083 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
1085 if (!fbc_supported(dev_priv
))
1088 mutex_lock(&fbc
->lock
);
1091 WARN_ON(fbc
->crtc
== NULL
);
1092 if (fbc
->crtc
== crtc
) {
1093 WARN_ON(!crtc_state
->enable_fbc
);
1094 WARN_ON(fbc
->active
);
1099 if (!crtc_state
->enable_fbc
)
1102 WARN_ON(fbc
->active
);
1103 WARN_ON(fbc
->crtc
!= NULL
);
1105 intel_fbc_update_state_cache(crtc
, crtc_state
, plane_state
);
1106 if (intel_fbc_alloc_cfb(crtc
)) {
1107 fbc
->no_fbc_reason
= "not enough stolen memory";
1111 DRM_DEBUG_KMS("Enabling FBC on pipe %c\n", pipe_name(crtc
->pipe
));
1112 fbc
->no_fbc_reason
= "FBC enabled but not active yet\n";
1114 fbc
->enabled
= true;
1117 mutex_unlock(&fbc
->lock
);
1121 * intel_fbc_disable - disable FBC if it's associated with crtc
1124 * This function disables FBC if it's associated with the provided CRTC.
1126 void intel_fbc_disable(struct intel_crtc
*crtc
)
1128 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1129 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
1131 if (!fbc_supported(dev_priv
))
1134 mutex_lock(&fbc
->lock
);
1135 if (fbc
->crtc
== crtc
)
1136 __intel_fbc_disable(dev_priv
);
1137 mutex_unlock(&fbc
->lock
);
1141 * intel_fbc_global_disable - globally disable FBC
1142 * @dev_priv: i915 device instance
1144 * This function disables FBC regardless of which CRTC is associated with it.
1146 void intel_fbc_global_disable(struct drm_i915_private
*dev_priv
)
1148 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
1150 if (!fbc_supported(dev_priv
))
1153 mutex_lock(&fbc
->lock
);
1155 WARN_ON(fbc
->crtc
->active
);
1156 __intel_fbc_disable(dev_priv
);
1158 mutex_unlock(&fbc
->lock
);
1161 static void intel_fbc_underrun_work_fn(struct work_struct
*work
)
1163 struct drm_i915_private
*dev_priv
=
1164 container_of(work
, struct drm_i915_private
, fbc
.underrun_work
);
1165 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
1167 mutex_lock(&fbc
->lock
);
1169 /* Maybe we were scheduled twice. */
1170 if (fbc
->underrun_detected
|| !fbc
->enabled
)
1173 DRM_DEBUG_KMS("Disabling FBC due to FIFO underrun.\n");
1174 fbc
->underrun_detected
= true;
1176 intel_fbc_deactivate(dev_priv
, "FIFO underrun");
1178 mutex_unlock(&fbc
->lock
);
1182 * intel_fbc_reset_underrun - reset FBC fifo underrun status.
1183 * @dev_priv: i915 device instance
1185 * See intel_fbc_handle_fifo_underrun_irq(). For automated testing we
1186 * want to re-enable FBC after an underrun to increase test coverage.
1188 int intel_fbc_reset_underrun(struct drm_i915_private
*dev_priv
)
1192 cancel_work_sync(&dev_priv
->fbc
.underrun_work
);
1194 ret
= mutex_lock_interruptible(&dev_priv
->fbc
.lock
);
1198 if (dev_priv
->fbc
.underrun_detected
) {
1199 DRM_DEBUG_KMS("Re-allowing FBC after fifo underrun\n");
1200 dev_priv
->fbc
.no_fbc_reason
= "FIFO underrun cleared";
1203 dev_priv
->fbc
.underrun_detected
= false;
1204 mutex_unlock(&dev_priv
->fbc
.lock
);
1210 * intel_fbc_handle_fifo_underrun_irq - disable FBC when we get a FIFO underrun
1211 * @dev_priv: i915 device instance
1213 * Without FBC, most underruns are harmless and don't really cause too many
1214 * problems, except for an annoying message on dmesg. With FBC, underruns can
1215 * become black screens or even worse, especially when paired with bad
1216 * watermarks. So in order for us to be on the safe side, completely disable FBC
1217 * in case we ever detect a FIFO underrun on any pipe. An underrun on any pipe
1218 * already suggests that watermarks may be bad, so try to be as safe as
1221 * This function is called from the IRQ handler.
1223 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private
*dev_priv
)
1225 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
1227 if (!fbc_supported(dev_priv
))
1230 /* There's no guarantee that underrun_detected won't be set to true
1231 * right after this check and before the work is scheduled, but that's
1232 * not a problem since we'll check it again under the work function
1233 * while FBC is locked. This check here is just to prevent us from
1234 * unnecessarily scheduling the work, and it relies on the fact that we
1235 * never switch underrun_detect back to false after it's true. */
1236 if (READ_ONCE(fbc
->underrun_detected
))
1239 schedule_work(&fbc
->underrun_work
);
1243 * intel_fbc_init_pipe_state - initialize FBC's CRTC visibility tracking
1244 * @dev_priv: i915 device instance
1246 * The FBC code needs to track CRTC visibility since the older platforms can't
1247 * have FBC enabled while multiple pipes are used. This function does the
1248 * initial setup at driver load to make sure FBC is matching the real hardware.
1250 void intel_fbc_init_pipe_state(struct drm_i915_private
*dev_priv
)
1252 struct intel_crtc
*crtc
;
1254 /* Don't even bother tracking anything if we don't need. */
1255 if (!no_fbc_on_multiple_pipes(dev_priv
))
1258 for_each_intel_crtc(&dev_priv
->drm
, crtc
)
1259 if (intel_crtc_active(crtc
) &&
1260 crtc
->base
.primary
->state
->visible
)
1261 dev_priv
->fbc
.visible_pipes_mask
|= (1 << crtc
->pipe
);
1265 * The DDX driver changes its behavior depending on the value it reads from
1266 * i915.enable_fbc, so sanitize it by translating the default value into either
1267 * 0 or 1 in order to allow it to know what's going on.
1269 * Notice that this is done at driver initialization and we still allow user
1270 * space to change the value during runtime without sanitizing it again. IGT
1271 * relies on being able to change i915.enable_fbc at runtime.
1273 static int intel_sanitize_fbc_option(struct drm_i915_private
*dev_priv
)
1275 if (i915_modparams
.enable_fbc
>= 0)
1276 return !!i915_modparams
.enable_fbc
;
1278 if (!HAS_FBC(dev_priv
))
1281 if (IS_BROADWELL(dev_priv
) || INTEL_GEN(dev_priv
) >= 9)
1287 static bool need_fbc_vtd_wa(struct drm_i915_private
*dev_priv
)
1289 /* WaFbcTurnOffFbcWhenHyperVisorIsUsed:skl,bxt */
1290 if (intel_vtd_active() &&
1291 (IS_SKYLAKE(dev_priv
) || IS_BROXTON(dev_priv
))) {
1292 DRM_INFO("Disabling framebuffer compression (FBC) to prevent screen flicker with VT-d enabled\n");
1300 * intel_fbc_init - Initialize FBC
1301 * @dev_priv: the i915 device
1303 * This function might be called during PM init process.
1305 void intel_fbc_init(struct drm_i915_private
*dev_priv
)
1307 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
1309 INIT_WORK(&fbc
->underrun_work
, intel_fbc_underrun_work_fn
);
1310 mutex_init(&fbc
->lock
);
1311 fbc
->enabled
= false;
1312 fbc
->active
= false;
1314 if (need_fbc_vtd_wa(dev_priv
))
1315 mkwrite_device_info(dev_priv
)->display
.has_fbc
= false;
1317 i915_modparams
.enable_fbc
= intel_sanitize_fbc_option(dev_priv
);
1318 DRM_DEBUG_KMS("Sanitized enable_fbc value: %d\n",
1319 i915_modparams
.enable_fbc
);
1321 if (!HAS_FBC(dev_priv
)) {
1322 fbc
->no_fbc_reason
= "unsupported by this chipset";
1326 /* This value was pulled out of someone's hat */
1327 if (INTEL_GEN(dev_priv
) <= 4 && !IS_GM45(dev_priv
))
1328 I915_WRITE(FBC_CONTROL
, 500 << FBC_CTL_INTERVAL_SHIFT
);
1330 /* We still don't have any sort of hardware state readout for FBC, so
1331 * deactivate it in case the BIOS activated it to make sure software
1332 * matches the hardware state. */
1333 if (intel_fbc_hw_is_active(dev_priv
))
1334 intel_fbc_hw_deactivate(dev_priv
);