2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Daniel Vetter <daniel.vetter@ffwll.ch>
29 #include "intel_drv.h"
30 #include "intel_fbc.h"
33 * DOC: fifo underrun handling
35 * The i915 driver checks for display fifo underruns using the interrupt signals
36 * provided by the hardware. This is enabled by default and fairly useful to
37 * debug display issues, especially watermark settings.
39 * If an underrun is detected this is logged into dmesg. To avoid flooding logs
40 * and occupying the cpu underrun interrupts are disabled after the first
41 * occurrence until the next modeset on a given pipe.
43 * Note that underrun detection on gmch platforms is a bit more ugly since there
44 * is no interrupt (despite that the signalling bit is in the PIPESTAT pipe
45 * interrupt register). Also on some other platforms underrun interrupts are
46 * shared, which means that if we detect an underrun we need to disable underrun
47 * reporting on all pipes.
49 * The code also supports underrun detection on the PCH transcoder.
52 static bool ivb_can_enable_err_int(struct drm_device
*dev
)
54 struct drm_i915_private
*dev_priv
= to_i915(dev
);
55 struct intel_crtc
*crtc
;
58 lockdep_assert_held(&dev_priv
->irq_lock
);
60 for_each_pipe(dev_priv
, pipe
) {
61 crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
63 if (crtc
->cpu_fifo_underrun_disabled
)
70 static bool cpt_can_enable_serr_int(struct drm_device
*dev
)
72 struct drm_i915_private
*dev_priv
= to_i915(dev
);
74 struct intel_crtc
*crtc
;
76 lockdep_assert_held(&dev_priv
->irq_lock
);
78 for_each_pipe(dev_priv
, pipe
) {
79 crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
81 if (crtc
->pch_fifo_underrun_disabled
)
88 static void i9xx_check_fifo_underruns(struct intel_crtc
*crtc
)
90 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
91 i915_reg_t reg
= PIPESTAT(crtc
->pipe
);
94 lockdep_assert_held(&dev_priv
->irq_lock
);
96 if ((I915_READ(reg
) & PIPE_FIFO_UNDERRUN_STATUS
) == 0)
99 enable_mask
= i915_pipestat_enable_mask(dev_priv
, crtc
->pipe
);
100 I915_WRITE(reg
, enable_mask
| PIPE_FIFO_UNDERRUN_STATUS
);
103 trace_intel_cpu_fifo_underrun(dev_priv
, crtc
->pipe
);
104 DRM_ERROR("pipe %c underrun\n", pipe_name(crtc
->pipe
));
107 static void i9xx_set_fifo_underrun_reporting(struct drm_device
*dev
,
109 bool enable
, bool old
)
111 struct drm_i915_private
*dev_priv
= to_i915(dev
);
112 i915_reg_t reg
= PIPESTAT(pipe
);
114 lockdep_assert_held(&dev_priv
->irq_lock
);
117 u32 enable_mask
= i915_pipestat_enable_mask(dev_priv
, pipe
);
119 I915_WRITE(reg
, enable_mask
| PIPE_FIFO_UNDERRUN_STATUS
);
122 if (old
&& I915_READ(reg
) & PIPE_FIFO_UNDERRUN_STATUS
)
123 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe
));
127 static void ironlake_set_fifo_underrun_reporting(struct drm_device
*dev
,
128 enum pipe pipe
, bool enable
)
130 struct drm_i915_private
*dev_priv
= to_i915(dev
);
131 u32 bit
= (pipe
== PIPE_A
) ?
132 DE_PIPEA_FIFO_UNDERRUN
: DE_PIPEB_FIFO_UNDERRUN
;
135 ilk_enable_display_irq(dev_priv
, bit
);
137 ilk_disable_display_irq(dev_priv
, bit
);
140 static void ivybridge_check_fifo_underruns(struct intel_crtc
*crtc
)
142 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
143 enum pipe pipe
= crtc
->pipe
;
144 u32 err_int
= I915_READ(GEN7_ERR_INT
);
146 lockdep_assert_held(&dev_priv
->irq_lock
);
148 if ((err_int
& ERR_INT_FIFO_UNDERRUN(pipe
)) == 0)
151 I915_WRITE(GEN7_ERR_INT
, ERR_INT_FIFO_UNDERRUN(pipe
));
152 POSTING_READ(GEN7_ERR_INT
);
154 trace_intel_cpu_fifo_underrun(dev_priv
, pipe
);
155 DRM_ERROR("fifo underrun on pipe %c\n", pipe_name(pipe
));
158 static void ivybridge_set_fifo_underrun_reporting(struct drm_device
*dev
,
160 bool enable
, bool old
)
162 struct drm_i915_private
*dev_priv
= to_i915(dev
);
164 I915_WRITE(GEN7_ERR_INT
, ERR_INT_FIFO_UNDERRUN(pipe
));
166 if (!ivb_can_enable_err_int(dev
))
169 ilk_enable_display_irq(dev_priv
, DE_ERR_INT_IVB
);
171 ilk_disable_display_irq(dev_priv
, DE_ERR_INT_IVB
);
174 I915_READ(GEN7_ERR_INT
) & ERR_INT_FIFO_UNDERRUN(pipe
)) {
175 DRM_ERROR("uncleared fifo underrun on pipe %c\n",
181 static void broadwell_set_fifo_underrun_reporting(struct drm_device
*dev
,
182 enum pipe pipe
, bool enable
)
184 struct drm_i915_private
*dev_priv
= to_i915(dev
);
187 bdw_enable_pipe_irq(dev_priv
, pipe
, GEN8_PIPE_FIFO_UNDERRUN
);
189 bdw_disable_pipe_irq(dev_priv
, pipe
, GEN8_PIPE_FIFO_UNDERRUN
);
192 static void ibx_set_fifo_underrun_reporting(struct drm_device
*dev
,
193 enum pipe pch_transcoder
,
196 struct drm_i915_private
*dev_priv
= to_i915(dev
);
197 u32 bit
= (pch_transcoder
== PIPE_A
) ?
198 SDE_TRANSA_FIFO_UNDER
: SDE_TRANSB_FIFO_UNDER
;
201 ibx_enable_display_interrupt(dev_priv
, bit
);
203 ibx_disable_display_interrupt(dev_priv
, bit
);
206 static void cpt_check_pch_fifo_underruns(struct intel_crtc
*crtc
)
208 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
209 enum pipe pch_transcoder
= crtc
->pipe
;
210 u32 serr_int
= I915_READ(SERR_INT
);
212 lockdep_assert_held(&dev_priv
->irq_lock
);
214 if ((serr_int
& SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder
)) == 0)
217 I915_WRITE(SERR_INT
, SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder
));
218 POSTING_READ(SERR_INT
);
220 trace_intel_pch_fifo_underrun(dev_priv
, pch_transcoder
);
221 DRM_ERROR("pch fifo underrun on pch transcoder %c\n",
222 pipe_name(pch_transcoder
));
225 static void cpt_set_fifo_underrun_reporting(struct drm_device
*dev
,
226 enum pipe pch_transcoder
,
227 bool enable
, bool old
)
229 struct drm_i915_private
*dev_priv
= to_i915(dev
);
233 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder
));
235 if (!cpt_can_enable_serr_int(dev
))
238 ibx_enable_display_interrupt(dev_priv
, SDE_ERROR_CPT
);
240 ibx_disable_display_interrupt(dev_priv
, SDE_ERROR_CPT
);
242 if (old
&& I915_READ(SERR_INT
) &
243 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder
)) {
244 DRM_ERROR("uncleared pch fifo underrun on pch transcoder %c\n",
245 pipe_name(pch_transcoder
));
250 static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device
*dev
,
251 enum pipe pipe
, bool enable
)
253 struct drm_i915_private
*dev_priv
= to_i915(dev
);
254 struct intel_crtc
*crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
257 lockdep_assert_held(&dev_priv
->irq_lock
);
259 old
= !crtc
->cpu_fifo_underrun_disabled
;
260 crtc
->cpu_fifo_underrun_disabled
= !enable
;
262 if (HAS_GMCH(dev_priv
))
263 i9xx_set_fifo_underrun_reporting(dev
, pipe
, enable
, old
);
264 else if (IS_GEN_RANGE(dev_priv
, 5, 6))
265 ironlake_set_fifo_underrun_reporting(dev
, pipe
, enable
);
266 else if (IS_GEN(dev_priv
, 7))
267 ivybridge_set_fifo_underrun_reporting(dev
, pipe
, enable
, old
);
268 else if (INTEL_GEN(dev_priv
) >= 8)
269 broadwell_set_fifo_underrun_reporting(dev
, pipe
, enable
);
275 * intel_set_cpu_fifo_underrun_reporting - set cpu fifo underrrun reporting state
276 * @dev_priv: i915 device instance
277 * @pipe: (CPU) pipe to set state for
278 * @enable: whether underruns should be reported or not
280 * This function sets the fifo underrun state for @pipe. It is used in the
281 * modeset code to avoid false positives since on many platforms underruns are
282 * expected when disabling or enabling the pipe.
284 * Notice that on some platforms disabling underrun reports for one pipe
285 * disables for all due to shared interrupts. Actual reporting is still per-pipe
288 * Returns the previous state of underrun reporting.
290 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private
*dev_priv
,
291 enum pipe pipe
, bool enable
)
296 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
297 ret
= __intel_set_cpu_fifo_underrun_reporting(&dev_priv
->drm
, pipe
,
299 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
305 * intel_set_pch_fifo_underrun_reporting - set PCH fifo underrun reporting state
306 * @dev_priv: i915 device instance
307 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
308 * @enable: whether underruns should be reported or not
310 * This function makes us disable or enable PCH fifo underruns for a specific
311 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
312 * underrun reporting for one transcoder may also disable all the other PCH
313 * error interruts for the other transcoders, due to the fact that there's just
314 * one interrupt mask/enable bit for all the transcoders.
316 * Returns the previous state of underrun reporting.
318 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private
*dev_priv
,
319 enum pipe pch_transcoder
,
322 struct intel_crtc
*crtc
=
323 intel_get_crtc_for_pipe(dev_priv
, pch_transcoder
);
328 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
329 * has only one pch transcoder A that all pipes can use. To avoid racy
330 * pch transcoder -> pipe lookups from interrupt code simply store the
331 * underrun statistics in crtc A. Since we never expose this anywhere
332 * nor use it outside of the fifo underrun code here using the "wrong"
333 * crtc on LPT won't cause issues.
336 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
338 old
= !crtc
->pch_fifo_underrun_disabled
;
339 crtc
->pch_fifo_underrun_disabled
= !enable
;
341 if (HAS_PCH_IBX(dev_priv
))
342 ibx_set_fifo_underrun_reporting(&dev_priv
->drm
,
346 cpt_set_fifo_underrun_reporting(&dev_priv
->drm
,
350 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
355 * intel_cpu_fifo_underrun_irq_handler - handle CPU fifo underrun interrupt
356 * @dev_priv: i915 device instance
357 * @pipe: (CPU) pipe to set state for
359 * This handles a CPU fifo underrun interrupt, generating an underrun warning
360 * into dmesg if underrun reporting is enabled and then disables the underrun
361 * interrupt to avoid an irq storm.
363 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private
*dev_priv
,
366 struct intel_crtc
*crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
368 /* We may be called too early in init, thanks BIOS! */
372 /* GMCH can't disable fifo underruns, filter them. */
373 if (HAS_GMCH(dev_priv
) &&
374 crtc
->cpu_fifo_underrun_disabled
)
377 if (intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false)) {
378 trace_intel_cpu_fifo_underrun(dev_priv
, pipe
);
379 DRM_ERROR("CPU pipe %c FIFO underrun\n",
383 intel_fbc_handle_fifo_underrun_irq(dev_priv
);
387 * intel_pch_fifo_underrun_irq_handler - handle PCH fifo underrun interrupt
388 * @dev_priv: i915 device instance
389 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
391 * This handles a PCH fifo underrun interrupt, generating an underrun warning
392 * into dmesg if underrun reporting is enabled and then disables the underrun
393 * interrupt to avoid an irq storm.
395 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private
*dev_priv
,
396 enum pipe pch_transcoder
)
398 if (intel_set_pch_fifo_underrun_reporting(dev_priv
, pch_transcoder
,
400 trace_intel_pch_fifo_underrun(dev_priv
, pch_transcoder
);
401 DRM_ERROR("PCH transcoder %c FIFO underrun\n",
402 pipe_name(pch_transcoder
));
407 * intel_check_cpu_fifo_underruns - check for CPU fifo underruns immediately
408 * @dev_priv: i915 device instance
410 * Check for CPU fifo underruns immediately. Useful on IVB/HSW where the shared
411 * error interrupt may have been disabled, and so CPU fifo underruns won't
412 * necessarily raise an interrupt, and on GMCH platforms where underruns never
413 * raise an interrupt.
415 void intel_check_cpu_fifo_underruns(struct drm_i915_private
*dev_priv
)
417 struct intel_crtc
*crtc
;
419 spin_lock_irq(&dev_priv
->irq_lock
);
421 for_each_intel_crtc(&dev_priv
->drm
, crtc
) {
422 if (crtc
->cpu_fifo_underrun_disabled
)
425 if (HAS_GMCH(dev_priv
))
426 i9xx_check_fifo_underruns(crtc
);
427 else if (IS_GEN(dev_priv
, 7))
428 ivybridge_check_fifo_underruns(crtc
);
431 spin_unlock_irq(&dev_priv
->irq_lock
);
435 * intel_check_pch_fifo_underruns - check for PCH fifo underruns immediately
436 * @dev_priv: i915 device instance
438 * Check for PCH fifo underruns immediately. Useful on CPT/PPT where the shared
439 * error interrupt may have been disabled, and so PCH fifo underruns won't
440 * necessarily raise an interrupt.
442 void intel_check_pch_fifo_underruns(struct drm_i915_private
*dev_priv
)
444 struct intel_crtc
*crtc
;
446 spin_lock_irq(&dev_priv
->irq_lock
);
448 for_each_intel_crtc(&dev_priv
->drm
, crtc
) {
449 if (crtc
->pch_fifo_underrun_disabled
)
452 if (HAS_PCH_CPT(dev_priv
))
453 cpt_check_pch_fifo_underruns(crtc
);
456 spin_unlock_irq(&dev_priv
->irq_lock
);