2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Vinit Azad <vinit.azad@intel.com>
25 * Ben Widawsky <ben@bwidawsk.net>
26 * Dave Gordon <david.s.gordon@intel.com>
27 * Alex Dai <yu.dai@intel.com>
30 #include "intel_guc_fw.h"
33 #define SKL_FW_MAJOR 9
34 #define SKL_FW_MINOR 33
36 #define BXT_FW_MAJOR 9
37 #define BXT_FW_MINOR 29
39 #define KBL_FW_MAJOR 9
40 #define KBL_FW_MINOR 39
42 #define GUC_FW_PATH(platform, major, minor) \
43 "i915/" __stringify(platform) "_guc_ver" __stringify(major) "_" __stringify(minor) ".bin"
45 #define I915_SKL_GUC_UCODE GUC_FW_PATH(skl, SKL_FW_MAJOR, SKL_FW_MINOR)
46 MODULE_FIRMWARE(I915_SKL_GUC_UCODE
);
48 #define I915_BXT_GUC_UCODE GUC_FW_PATH(bxt, BXT_FW_MAJOR, BXT_FW_MINOR)
49 MODULE_FIRMWARE(I915_BXT_GUC_UCODE
);
51 #define I915_KBL_GUC_UCODE GUC_FW_PATH(kbl, KBL_FW_MAJOR, KBL_FW_MINOR)
52 MODULE_FIRMWARE(I915_KBL_GUC_UCODE
);
54 static void guc_fw_select(struct intel_uc_fw
*guc_fw
)
56 struct intel_guc
*guc
= container_of(guc_fw
, struct intel_guc
, fw
);
57 struct drm_i915_private
*dev_priv
= guc_to_i915(guc
);
59 GEM_BUG_ON(guc_fw
->type
!= INTEL_UC_FW_TYPE_GUC
);
61 if (!HAS_GUC(dev_priv
))
64 if (i915_modparams
.guc_firmware_path
) {
65 guc_fw
->path
= i915_modparams
.guc_firmware_path
;
66 guc_fw
->major_ver_wanted
= 0;
67 guc_fw
->minor_ver_wanted
= 0;
68 } else if (IS_SKYLAKE(dev_priv
)) {
69 guc_fw
->path
= I915_SKL_GUC_UCODE
;
70 guc_fw
->major_ver_wanted
= SKL_FW_MAJOR
;
71 guc_fw
->minor_ver_wanted
= SKL_FW_MINOR
;
72 } else if (IS_BROXTON(dev_priv
)) {
73 guc_fw
->path
= I915_BXT_GUC_UCODE
;
74 guc_fw
->major_ver_wanted
= BXT_FW_MAJOR
;
75 guc_fw
->minor_ver_wanted
= BXT_FW_MINOR
;
76 } else if (IS_KABYLAKE(dev_priv
) || IS_COFFEELAKE(dev_priv
)) {
77 guc_fw
->path
= I915_KBL_GUC_UCODE
;
78 guc_fw
->major_ver_wanted
= KBL_FW_MAJOR
;
79 guc_fw
->minor_ver_wanted
= KBL_FW_MINOR
;
84 * intel_guc_fw_init_early() - initializes GuC firmware struct
85 * @guc: intel_guc struct
87 * On platforms with GuC selects firmware for uploading
89 void intel_guc_fw_init_early(struct intel_guc
*guc
)
91 struct intel_uc_fw
*guc_fw
= &guc
->fw
;
93 intel_uc_fw_init(guc_fw
, INTEL_UC_FW_TYPE_GUC
);
94 guc_fw_select(guc_fw
);
97 static void guc_prepare_xfer(struct intel_guc
*guc
)
99 struct drm_i915_private
*dev_priv
= guc_to_i915(guc
);
101 /* Must program this register before loading the ucode with DMA */
102 I915_WRITE(GUC_SHIM_CONTROL
, GUC_DISABLE_SRAM_INIT_TO_ZEROES
|
103 GUC_ENABLE_READ_CACHE_LOGIC
|
104 GUC_ENABLE_MIA_CACHING
|
105 GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA
|
106 GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA
|
107 GUC_ENABLE_MIA_CLOCK_GATING
);
109 if (IS_GEN9_LP(dev_priv
))
110 I915_WRITE(GEN9LP_GT_PM_CONFIG
, GT_DOORBELL_ENABLE
);
112 I915_WRITE(GEN9_GT_PM_CONFIG
, GT_DOORBELL_ENABLE
);
114 if (IS_GEN(dev_priv
, 9)) {
115 /* DOP Clock Gating Enable for GuC clocks */
116 I915_WRITE(GEN7_MISCCPCTL
, (GEN8_DOP_CLOCK_GATE_GUC_ENABLE
|
117 I915_READ(GEN7_MISCCPCTL
)));
119 /* allows for 5us (in 10ns units) before GT can go to RC6 */
120 I915_WRITE(GUC_ARAT_C6DIS
, 0x1FF);
124 /* Copy RSA signature from the fw image to HW for verification */
125 static void guc_xfer_rsa(struct intel_guc
*guc
, struct i915_vma
*vma
)
127 struct drm_i915_private
*dev_priv
= guc_to_i915(guc
);
128 u32 rsa
[UOS_RSA_SCRATCH_COUNT
];
131 sg_pcopy_to_buffer(vma
->pages
->sgl
, vma
->pages
->nents
,
132 rsa
, sizeof(rsa
), guc
->fw
.rsa_offset
);
134 for (i
= 0; i
< UOS_RSA_SCRATCH_COUNT
; i
++)
135 I915_WRITE(UOS_RSA_SCRATCH(i
), rsa
[i
]);
138 static bool guc_xfer_completed(struct intel_guc
*guc
, u32
*status
)
140 struct drm_i915_private
*dev_priv
= guc_to_i915(guc
);
142 /* Did we complete the xfer? */
143 *status
= I915_READ(DMA_CTRL
);
144 return !(*status
& START_DMA
);
148 * Read the GuC status register (GUC_STATUS) and store it in the
149 * specified location; then return a boolean indicating whether
150 * the value matches either of two values representing completion
151 * of the GuC boot process.
153 * This is used for polling the GuC status in a wait_for()
156 static inline bool guc_ready(struct intel_guc
*guc
, u32
*status
)
158 struct drm_i915_private
*dev_priv
= guc_to_i915(guc
);
159 u32 val
= I915_READ(GUC_STATUS
);
160 u32 uk_val
= val
& GS_UKERNEL_MASK
;
163 return (uk_val
== GS_UKERNEL_READY
) ||
164 ((val
& GS_MIA_CORE_STATE
) && (uk_val
== GS_UKERNEL_LAPIC_DONE
));
167 static int guc_wait_ucode(struct intel_guc
*guc
)
173 * Wait for the GuC to start up.
174 * NB: Docs recommend not using the interrupt for completion.
175 * Measurements indicate this should take no more than 20ms, so a
176 * timeout here indicates that the GuC has failed and is unusable.
177 * (Higher levels of the driver may decide to reset the GuC and
178 * attempt the ucode load again if this happens.)
180 ret
= wait_for(guc_ready(guc
, &status
), 100);
181 DRM_DEBUG_DRIVER("GuC status %#x\n", status
);
183 if ((status
& GS_BOOTROM_MASK
) == GS_BOOTROM_RSA_FAILED
) {
184 DRM_ERROR("GuC firmware signature verification failed\n");
188 if (ret
== 0 && !guc_xfer_completed(guc
, &status
)) {
189 DRM_ERROR("GuC is ready, but the xfer %08x is incomplete\n",
198 * Transfer the firmware image to RAM for execution by the microcontroller.
200 * Architecturally, the DMA engine is bidirectional, and can potentially even
201 * transfer between GTT locations. This functionality is left out of the API
202 * for now as there is no need for it.
204 static int guc_xfer_ucode(struct intel_guc
*guc
, struct i915_vma
*vma
)
206 struct drm_i915_private
*dev_priv
= guc_to_i915(guc
);
207 struct intel_uc_fw
*guc_fw
= &guc
->fw
;
208 unsigned long offset
;
211 * The header plus uCode will be copied to WOPCM via DMA, excluding any
214 I915_WRITE(DMA_COPY_SIZE
, guc_fw
->header_size
+ guc_fw
->ucode_size
);
216 /* Set the source address for the new blob */
217 offset
= intel_guc_ggtt_offset(guc
, vma
) + guc_fw
->header_offset
;
218 I915_WRITE(DMA_ADDR_0_LOW
, lower_32_bits(offset
));
219 I915_WRITE(DMA_ADDR_0_HIGH
, upper_32_bits(offset
) & 0xFFFF);
222 * Set the DMA destination. Current uCode expects the code to be
223 * loaded at 8k; locations below this are used for the stack.
225 I915_WRITE(DMA_ADDR_1_LOW
, 0x2000);
226 I915_WRITE(DMA_ADDR_1_HIGH
, DMA_ADDRESS_SPACE_WOPCM
);
228 /* Finally start the DMA */
229 I915_WRITE(DMA_CTRL
, _MASKED_BIT_ENABLE(UOS_MOVE
| START_DMA
));
231 return guc_wait_ucode(guc
);
234 * Load the GuC firmware blob into the MinuteIA.
236 static int guc_fw_xfer(struct intel_uc_fw
*guc_fw
, struct i915_vma
*vma
)
238 struct intel_guc
*guc
= container_of(guc_fw
, struct intel_guc
, fw
);
239 struct drm_i915_private
*dev_priv
= guc_to_i915(guc
);
242 GEM_BUG_ON(guc_fw
->type
!= INTEL_UC_FW_TYPE_GUC
);
244 intel_uncore_forcewake_get(&dev_priv
->uncore
, FORCEWAKE_ALL
);
246 guc_prepare_xfer(guc
);
249 * Note that GuC needs the CSS header plus uKernel code to be copied
250 * by the DMA engine in one operation, whereas the RSA signature is
253 guc_xfer_rsa(guc
, vma
);
255 ret
= guc_xfer_ucode(guc
, vma
);
257 intel_uncore_forcewake_put(&dev_priv
->uncore
, FORCEWAKE_ALL
);
263 * intel_guc_fw_upload() - load GuC uCode to device
264 * @guc: intel_guc structure
266 * Called from intel_uc_init_hw() during driver load, resume from sleep and
269 * The firmware image should have already been fetched into memory, so only
270 * check that fetch succeeded, and then transfer the image to the h/w.
272 * Return: non-zero code on error
274 int intel_guc_fw_upload(struct intel_guc
*guc
)
276 return intel_uc_fw_upload(&guc
->fw
, guc_fw_xfer
);