2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2009 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Eric Anholt <eric@anholt.net>
26 * Jesse Barnes <jesse.barnes@intel.com>
29 #include <linux/i2c.h>
30 #include <linux/slab.h>
31 #include <linux/delay.h>
32 #include <linux/hdmi.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_edid.h>
37 #include <drm/drm_scdc_helper.h>
38 #include "intel_drv.h"
39 #include <drm/i915_drm.h>
40 #include <drm/intel_lpe_audio.h>
43 static struct drm_device
*intel_hdmi_to_dev(struct intel_hdmi
*intel_hdmi
)
45 return hdmi_to_dig_port(intel_hdmi
)->base
.base
.dev
;
49 assert_hdmi_port_disabled(struct intel_hdmi
*intel_hdmi
)
51 struct drm_device
*dev
= intel_hdmi_to_dev(intel_hdmi
);
52 struct drm_i915_private
*dev_priv
= to_i915(dev
);
53 uint32_t enabled_bits
;
55 enabled_bits
= HAS_DDI(dev_priv
) ? DDI_BUF_CTL_ENABLE
: SDVO_ENABLE
;
57 WARN(I915_READ(intel_hdmi
->hdmi_reg
) & enabled_bits
,
58 "HDMI port enabled, expecting disabled\n");
61 struct intel_hdmi
*enc_to_intel_hdmi(struct drm_encoder
*encoder
)
63 struct intel_digital_port
*intel_dig_port
=
64 container_of(encoder
, struct intel_digital_port
, base
.base
);
65 return &intel_dig_port
->hdmi
;
68 static struct intel_hdmi
*intel_attached_hdmi(struct drm_connector
*connector
)
70 return enc_to_intel_hdmi(&intel_attached_encoder(connector
)->base
);
73 static u32
g4x_infoframe_index(unsigned int type
)
76 case HDMI_INFOFRAME_TYPE_AVI
:
77 return VIDEO_DIP_SELECT_AVI
;
78 case HDMI_INFOFRAME_TYPE_SPD
:
79 return VIDEO_DIP_SELECT_SPD
;
80 case HDMI_INFOFRAME_TYPE_VENDOR
:
81 return VIDEO_DIP_SELECT_VENDOR
;
88 static u32
g4x_infoframe_enable(unsigned int type
)
91 case HDMI_INFOFRAME_TYPE_AVI
:
92 return VIDEO_DIP_ENABLE_AVI
;
93 case HDMI_INFOFRAME_TYPE_SPD
:
94 return VIDEO_DIP_ENABLE_SPD
;
95 case HDMI_INFOFRAME_TYPE_VENDOR
:
96 return VIDEO_DIP_ENABLE_VENDOR
;
103 static u32
hsw_infoframe_enable(unsigned int type
)
107 return VIDEO_DIP_ENABLE_VSC_HSW
;
108 case HDMI_INFOFRAME_TYPE_AVI
:
109 return VIDEO_DIP_ENABLE_AVI_HSW
;
110 case HDMI_INFOFRAME_TYPE_SPD
:
111 return VIDEO_DIP_ENABLE_SPD_HSW
;
112 case HDMI_INFOFRAME_TYPE_VENDOR
:
113 return VIDEO_DIP_ENABLE_VS_HSW
;
121 hsw_dip_data_reg(struct drm_i915_private
*dev_priv
,
122 enum transcoder cpu_transcoder
,
128 return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder
, i
);
129 case HDMI_INFOFRAME_TYPE_AVI
:
130 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder
, i
);
131 case HDMI_INFOFRAME_TYPE_SPD
:
132 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder
, i
);
133 case HDMI_INFOFRAME_TYPE_VENDOR
:
134 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder
, i
);
137 return INVALID_MMIO_REG
;
141 static void g4x_write_infoframe(struct drm_encoder
*encoder
,
142 const struct intel_crtc_state
*crtc_state
,
144 const void *frame
, ssize_t len
)
146 const uint32_t *data
= frame
;
147 struct drm_device
*dev
= encoder
->dev
;
148 struct drm_i915_private
*dev_priv
= to_i915(dev
);
149 u32 val
= I915_READ(VIDEO_DIP_CTL
);
152 WARN(!(val
& VIDEO_DIP_ENABLE
), "Writing DIP with CTL reg disabled\n");
154 val
&= ~(VIDEO_DIP_SELECT_MASK
| 0xf); /* clear DIP data offset */
155 val
|= g4x_infoframe_index(type
);
157 val
&= ~g4x_infoframe_enable(type
);
159 I915_WRITE(VIDEO_DIP_CTL
, val
);
162 for (i
= 0; i
< len
; i
+= 4) {
163 I915_WRITE(VIDEO_DIP_DATA
, *data
);
166 /* Write every possible data byte to force correct ECC calculation. */
167 for (; i
< VIDEO_DIP_DATA_SIZE
; i
+= 4)
168 I915_WRITE(VIDEO_DIP_DATA
, 0);
171 val
|= g4x_infoframe_enable(type
);
172 val
&= ~VIDEO_DIP_FREQ_MASK
;
173 val
|= VIDEO_DIP_FREQ_VSYNC
;
175 I915_WRITE(VIDEO_DIP_CTL
, val
);
176 POSTING_READ(VIDEO_DIP_CTL
);
179 static bool g4x_infoframe_enabled(struct drm_encoder
*encoder
,
180 const struct intel_crtc_state
*pipe_config
)
182 struct drm_i915_private
*dev_priv
= to_i915(encoder
->dev
);
183 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
184 u32 val
= I915_READ(VIDEO_DIP_CTL
);
186 if ((val
& VIDEO_DIP_ENABLE
) == 0)
189 if ((val
& VIDEO_DIP_PORT_MASK
) != VIDEO_DIP_PORT(intel_dig_port
->port
))
192 return val
& (VIDEO_DIP_ENABLE_AVI
|
193 VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_SPD
);
196 static void ibx_write_infoframe(struct drm_encoder
*encoder
,
197 const struct intel_crtc_state
*crtc_state
,
199 const void *frame
, ssize_t len
)
201 const uint32_t *data
= frame
;
202 struct drm_device
*dev
= encoder
->dev
;
203 struct drm_i915_private
*dev_priv
= to_i915(dev
);
204 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
205 i915_reg_t reg
= TVIDEO_DIP_CTL(intel_crtc
->pipe
);
206 u32 val
= I915_READ(reg
);
209 WARN(!(val
& VIDEO_DIP_ENABLE
), "Writing DIP with CTL reg disabled\n");
211 val
&= ~(VIDEO_DIP_SELECT_MASK
| 0xf); /* clear DIP data offset */
212 val
|= g4x_infoframe_index(type
);
214 val
&= ~g4x_infoframe_enable(type
);
216 I915_WRITE(reg
, val
);
219 for (i
= 0; i
< len
; i
+= 4) {
220 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc
->pipe
), *data
);
223 /* Write every possible data byte to force correct ECC calculation. */
224 for (; i
< VIDEO_DIP_DATA_SIZE
; i
+= 4)
225 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc
->pipe
), 0);
228 val
|= g4x_infoframe_enable(type
);
229 val
&= ~VIDEO_DIP_FREQ_MASK
;
230 val
|= VIDEO_DIP_FREQ_VSYNC
;
232 I915_WRITE(reg
, val
);
236 static bool ibx_infoframe_enabled(struct drm_encoder
*encoder
,
237 const struct intel_crtc_state
*pipe_config
)
239 struct drm_i915_private
*dev_priv
= to_i915(encoder
->dev
);
240 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
241 enum pipe pipe
= to_intel_crtc(pipe_config
->base
.crtc
)->pipe
;
242 i915_reg_t reg
= TVIDEO_DIP_CTL(pipe
);
243 u32 val
= I915_READ(reg
);
245 if ((val
& VIDEO_DIP_ENABLE
) == 0)
248 if ((val
& VIDEO_DIP_PORT_MASK
) != VIDEO_DIP_PORT(intel_dig_port
->port
))
251 return val
& (VIDEO_DIP_ENABLE_AVI
|
252 VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_GAMUT
|
253 VIDEO_DIP_ENABLE_SPD
| VIDEO_DIP_ENABLE_GCP
);
256 static void cpt_write_infoframe(struct drm_encoder
*encoder
,
257 const struct intel_crtc_state
*crtc_state
,
259 const void *frame
, ssize_t len
)
261 const uint32_t *data
= frame
;
262 struct drm_device
*dev
= encoder
->dev
;
263 struct drm_i915_private
*dev_priv
= to_i915(dev
);
264 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
265 i915_reg_t reg
= TVIDEO_DIP_CTL(intel_crtc
->pipe
);
266 u32 val
= I915_READ(reg
);
269 WARN(!(val
& VIDEO_DIP_ENABLE
), "Writing DIP with CTL reg disabled\n");
271 val
&= ~(VIDEO_DIP_SELECT_MASK
| 0xf); /* clear DIP data offset */
272 val
|= g4x_infoframe_index(type
);
274 /* The DIP control register spec says that we need to update the AVI
275 * infoframe without clearing its enable bit */
276 if (type
!= HDMI_INFOFRAME_TYPE_AVI
)
277 val
&= ~g4x_infoframe_enable(type
);
279 I915_WRITE(reg
, val
);
282 for (i
= 0; i
< len
; i
+= 4) {
283 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc
->pipe
), *data
);
286 /* Write every possible data byte to force correct ECC calculation. */
287 for (; i
< VIDEO_DIP_DATA_SIZE
; i
+= 4)
288 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc
->pipe
), 0);
291 val
|= g4x_infoframe_enable(type
);
292 val
&= ~VIDEO_DIP_FREQ_MASK
;
293 val
|= VIDEO_DIP_FREQ_VSYNC
;
295 I915_WRITE(reg
, val
);
299 static bool cpt_infoframe_enabled(struct drm_encoder
*encoder
,
300 const struct intel_crtc_state
*pipe_config
)
302 struct drm_i915_private
*dev_priv
= to_i915(encoder
->dev
);
303 enum pipe pipe
= to_intel_crtc(pipe_config
->base
.crtc
)->pipe
;
304 u32 val
= I915_READ(TVIDEO_DIP_CTL(pipe
));
306 if ((val
& VIDEO_DIP_ENABLE
) == 0)
309 return val
& (VIDEO_DIP_ENABLE_AVI
|
310 VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_GAMUT
|
311 VIDEO_DIP_ENABLE_SPD
| VIDEO_DIP_ENABLE_GCP
);
314 static void vlv_write_infoframe(struct drm_encoder
*encoder
,
315 const struct intel_crtc_state
*crtc_state
,
317 const void *frame
, ssize_t len
)
319 const uint32_t *data
= frame
;
320 struct drm_device
*dev
= encoder
->dev
;
321 struct drm_i915_private
*dev_priv
= to_i915(dev
);
322 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
323 i915_reg_t reg
= VLV_TVIDEO_DIP_CTL(intel_crtc
->pipe
);
324 u32 val
= I915_READ(reg
);
327 WARN(!(val
& VIDEO_DIP_ENABLE
), "Writing DIP with CTL reg disabled\n");
329 val
&= ~(VIDEO_DIP_SELECT_MASK
| 0xf); /* clear DIP data offset */
330 val
|= g4x_infoframe_index(type
);
332 val
&= ~g4x_infoframe_enable(type
);
334 I915_WRITE(reg
, val
);
337 for (i
= 0; i
< len
; i
+= 4) {
338 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc
->pipe
), *data
);
341 /* Write every possible data byte to force correct ECC calculation. */
342 for (; i
< VIDEO_DIP_DATA_SIZE
; i
+= 4)
343 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc
->pipe
), 0);
346 val
|= g4x_infoframe_enable(type
);
347 val
&= ~VIDEO_DIP_FREQ_MASK
;
348 val
|= VIDEO_DIP_FREQ_VSYNC
;
350 I915_WRITE(reg
, val
);
354 static bool vlv_infoframe_enabled(struct drm_encoder
*encoder
,
355 const struct intel_crtc_state
*pipe_config
)
357 struct drm_i915_private
*dev_priv
= to_i915(encoder
->dev
);
358 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
359 enum pipe pipe
= to_intel_crtc(pipe_config
->base
.crtc
)->pipe
;
360 u32 val
= I915_READ(VLV_TVIDEO_DIP_CTL(pipe
));
362 if ((val
& VIDEO_DIP_ENABLE
) == 0)
365 if ((val
& VIDEO_DIP_PORT_MASK
) != VIDEO_DIP_PORT(intel_dig_port
->port
))
368 return val
& (VIDEO_DIP_ENABLE_AVI
|
369 VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_GAMUT
|
370 VIDEO_DIP_ENABLE_SPD
| VIDEO_DIP_ENABLE_GCP
);
373 static void hsw_write_infoframe(struct drm_encoder
*encoder
,
374 const struct intel_crtc_state
*crtc_state
,
376 const void *frame
, ssize_t len
)
378 const uint32_t *data
= frame
;
379 struct drm_device
*dev
= encoder
->dev
;
380 struct drm_i915_private
*dev_priv
= to_i915(dev
);
381 enum transcoder cpu_transcoder
= crtc_state
->cpu_transcoder
;
382 i915_reg_t ctl_reg
= HSW_TVIDEO_DIP_CTL(cpu_transcoder
);
384 int data_size
= type
== DP_SDP_VSC
?
385 VIDEO_DIP_VSC_DATA_SIZE
: VIDEO_DIP_DATA_SIZE
;
387 u32 val
= I915_READ(ctl_reg
);
389 data_reg
= hsw_dip_data_reg(dev_priv
, cpu_transcoder
, type
, 0);
391 val
&= ~hsw_infoframe_enable(type
);
392 I915_WRITE(ctl_reg
, val
);
395 for (i
= 0; i
< len
; i
+= 4) {
396 I915_WRITE(hsw_dip_data_reg(dev_priv
, cpu_transcoder
,
397 type
, i
>> 2), *data
);
400 /* Write every possible data byte to force correct ECC calculation. */
401 for (; i
< data_size
; i
+= 4)
402 I915_WRITE(hsw_dip_data_reg(dev_priv
, cpu_transcoder
,
406 val
|= hsw_infoframe_enable(type
);
407 I915_WRITE(ctl_reg
, val
);
408 POSTING_READ(ctl_reg
);
411 static bool hsw_infoframe_enabled(struct drm_encoder
*encoder
,
412 const struct intel_crtc_state
*pipe_config
)
414 struct drm_i915_private
*dev_priv
= to_i915(encoder
->dev
);
415 u32 val
= I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config
->cpu_transcoder
));
417 return val
& (VIDEO_DIP_ENABLE_VSC_HSW
| VIDEO_DIP_ENABLE_AVI_HSW
|
418 VIDEO_DIP_ENABLE_GCP_HSW
| VIDEO_DIP_ENABLE_VS_HSW
|
419 VIDEO_DIP_ENABLE_GMP_HSW
| VIDEO_DIP_ENABLE_SPD_HSW
);
423 * The data we write to the DIP data buffer registers is 1 byte bigger than the
424 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
425 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
426 * used for both technologies.
428 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
429 * DW1: DB3 | DB2 | DB1 | DB0
430 * DW2: DB7 | DB6 | DB5 | DB4
433 * (HB is Header Byte, DB is Data Byte)
435 * The hdmi pack() functions don't know about that hardware specific hole so we
436 * trick them by giving an offset into the buffer and moving back the header
439 static void intel_write_infoframe(struct drm_encoder
*encoder
,
440 const struct intel_crtc_state
*crtc_state
,
441 union hdmi_infoframe
*frame
)
443 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
444 uint8_t buffer
[VIDEO_DIP_DATA_SIZE
];
447 /* see comment above for the reason for this offset */
448 len
= hdmi_infoframe_pack(frame
, buffer
+ 1, sizeof(buffer
) - 1);
452 /* Insert the 'hole' (see big comment above) at position 3 */
453 buffer
[0] = buffer
[1];
454 buffer
[1] = buffer
[2];
455 buffer
[2] = buffer
[3];
459 intel_dig_port
->write_infoframe(encoder
, crtc_state
, frame
->any
.type
, buffer
, len
);
462 static void intel_hdmi_set_avi_infoframe(struct drm_encoder
*encoder
,
463 const struct intel_crtc_state
*crtc_state
)
465 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
466 const struct drm_display_mode
*adjusted_mode
=
467 &crtc_state
->base
.adjusted_mode
;
468 struct drm_connector
*connector
= &intel_hdmi
->attached_connector
->base
;
469 bool is_hdmi2_sink
= connector
->display_info
.hdmi
.scdc
.supported
;
470 union hdmi_infoframe frame
;
473 ret
= drm_hdmi_avi_infoframe_from_display_mode(&frame
.avi
,
477 DRM_ERROR("couldn't fill AVI infoframe\n");
481 if (crtc_state
->ycbcr420
)
482 frame
.avi
.colorspace
= HDMI_COLORSPACE_YUV420
;
484 frame
.avi
.colorspace
= HDMI_COLORSPACE_RGB
;
486 drm_hdmi_avi_infoframe_quant_range(&frame
.avi
, adjusted_mode
,
487 crtc_state
->limited_color_range
?
488 HDMI_QUANTIZATION_RANGE_LIMITED
:
489 HDMI_QUANTIZATION_RANGE_FULL
,
490 intel_hdmi
->rgb_quant_range_selectable
,
493 /* TODO: handle pixel repetition for YCBCR420 outputs */
494 intel_write_infoframe(encoder
, crtc_state
, &frame
);
497 static void intel_hdmi_set_spd_infoframe(struct drm_encoder
*encoder
,
498 const struct intel_crtc_state
*crtc_state
)
500 union hdmi_infoframe frame
;
503 ret
= hdmi_spd_infoframe_init(&frame
.spd
, "Intel", "Integrated gfx");
505 DRM_ERROR("couldn't fill SPD infoframe\n");
509 frame
.spd
.sdi
= HDMI_SPD_SDI_PC
;
511 intel_write_infoframe(encoder
, crtc_state
, &frame
);
515 intel_hdmi_set_hdmi_infoframe(struct drm_encoder
*encoder
,
516 const struct intel_crtc_state
*crtc_state
,
517 const struct drm_connector_state
*conn_state
)
519 union hdmi_infoframe frame
;
522 ret
= drm_hdmi_vendor_infoframe_from_display_mode(&frame
.vendor
.hdmi
,
523 conn_state
->connector
,
524 &crtc_state
->base
.adjusted_mode
);
528 intel_write_infoframe(encoder
, crtc_state
, &frame
);
531 static void g4x_set_infoframes(struct drm_encoder
*encoder
,
533 const struct intel_crtc_state
*crtc_state
,
534 const struct drm_connector_state
*conn_state
)
536 struct drm_i915_private
*dev_priv
= to_i915(encoder
->dev
);
537 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
538 struct intel_hdmi
*intel_hdmi
= &intel_dig_port
->hdmi
;
539 i915_reg_t reg
= VIDEO_DIP_CTL
;
540 u32 val
= I915_READ(reg
);
541 u32 port
= VIDEO_DIP_PORT(intel_dig_port
->port
);
543 assert_hdmi_port_disabled(intel_hdmi
);
545 /* If the registers were not initialized yet, they might be zeroes,
546 * which means we're selecting the AVI DIP and we're setting its
547 * frequency to once. This seems to really confuse the HW and make
548 * things stop working (the register spec says the AVI always needs to
549 * be sent every VSync). So here we avoid writing to the register more
550 * than we need and also explicitly select the AVI DIP and explicitly
551 * set its frequency to every VSync. Avoiding to write it twice seems to
552 * be enough to solve the problem, but being defensive shouldn't hurt us
554 val
|= VIDEO_DIP_SELECT_AVI
| VIDEO_DIP_FREQ_VSYNC
;
557 if (!(val
& VIDEO_DIP_ENABLE
))
559 if (port
!= (val
& VIDEO_DIP_PORT_MASK
)) {
560 DRM_DEBUG_KMS("video DIP still enabled on port %c\n",
561 (val
& VIDEO_DIP_PORT_MASK
) >> 29);
564 val
&= ~(VIDEO_DIP_ENABLE
| VIDEO_DIP_ENABLE_AVI
|
565 VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_SPD
);
566 I915_WRITE(reg
, val
);
571 if (port
!= (val
& VIDEO_DIP_PORT_MASK
)) {
572 if (val
& VIDEO_DIP_ENABLE
) {
573 DRM_DEBUG_KMS("video DIP already enabled on port %c\n",
574 (val
& VIDEO_DIP_PORT_MASK
) >> 29);
577 val
&= ~VIDEO_DIP_PORT_MASK
;
581 val
|= VIDEO_DIP_ENABLE
;
582 val
&= ~(VIDEO_DIP_ENABLE_AVI
|
583 VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_SPD
);
585 I915_WRITE(reg
, val
);
588 intel_hdmi_set_avi_infoframe(encoder
, crtc_state
);
589 intel_hdmi_set_spd_infoframe(encoder
, crtc_state
);
590 intel_hdmi_set_hdmi_infoframe(encoder
, crtc_state
, conn_state
);
593 static bool hdmi_sink_is_deep_color(const struct drm_connector_state
*conn_state
)
595 struct drm_connector
*connector
= conn_state
->connector
;
598 * HDMI cloning is only supported on g4x which doesn't
599 * support deep color or GCP infoframes anyway so no
600 * need to worry about multiple HDMI sinks here.
603 return connector
->display_info
.bpc
> 8;
607 * Determine if default_phase=1 can be indicated in the GCP infoframe.
609 * From HDMI specification 1.4a:
610 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
611 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
612 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
613 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
616 static bool gcp_default_phase_possible(int pipe_bpp
,
617 const struct drm_display_mode
*mode
)
619 unsigned int pixels_per_group
;
623 /* 4 pixels in 5 clocks */
624 pixels_per_group
= 4;
627 /* 2 pixels in 3 clocks */
628 pixels_per_group
= 2;
631 /* 1 pixel in 2 clocks */
632 pixels_per_group
= 1;
635 /* phase information not relevant for 8bpc */
639 return mode
->crtc_hdisplay
% pixels_per_group
== 0 &&
640 mode
->crtc_htotal
% pixels_per_group
== 0 &&
641 mode
->crtc_hblank_start
% pixels_per_group
== 0 &&
642 mode
->crtc_hblank_end
% pixels_per_group
== 0 &&
643 mode
->crtc_hsync_start
% pixels_per_group
== 0 &&
644 mode
->crtc_hsync_end
% pixels_per_group
== 0 &&
645 ((mode
->flags
& DRM_MODE_FLAG_INTERLACE
) == 0 ||
646 mode
->crtc_htotal
/2 % pixels_per_group
== 0);
649 static bool intel_hdmi_set_gcp_infoframe(struct drm_encoder
*encoder
,
650 const struct intel_crtc_state
*crtc_state
,
651 const struct drm_connector_state
*conn_state
)
653 struct drm_i915_private
*dev_priv
= to_i915(encoder
->dev
);
654 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
658 if (HAS_DDI(dev_priv
))
659 reg
= HSW_TVIDEO_DIP_GCP(crtc_state
->cpu_transcoder
);
660 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
661 reg
= VLV_TVIDEO_DIP_GCP(crtc
->pipe
);
662 else if (HAS_PCH_SPLIT(dev_priv
))
663 reg
= TVIDEO_DIP_GCP(crtc
->pipe
);
667 /* Indicate color depth whenever the sink supports deep color */
668 if (hdmi_sink_is_deep_color(conn_state
))
669 val
|= GCP_COLOR_INDICATION
;
671 /* Enable default_phase whenever the display mode is suitably aligned */
672 if (gcp_default_phase_possible(crtc_state
->pipe_bpp
,
673 &crtc_state
->base
.adjusted_mode
))
674 val
|= GCP_DEFAULT_PHASE_ENABLE
;
676 I915_WRITE(reg
, val
);
681 static void ibx_set_infoframes(struct drm_encoder
*encoder
,
683 const struct intel_crtc_state
*crtc_state
,
684 const struct drm_connector_state
*conn_state
)
686 struct drm_i915_private
*dev_priv
= to_i915(encoder
->dev
);
687 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
688 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
689 struct intel_hdmi
*intel_hdmi
= &intel_dig_port
->hdmi
;
690 i915_reg_t reg
= TVIDEO_DIP_CTL(intel_crtc
->pipe
);
691 u32 val
= I915_READ(reg
);
692 u32 port
= VIDEO_DIP_PORT(intel_dig_port
->port
);
694 assert_hdmi_port_disabled(intel_hdmi
);
696 /* See the big comment in g4x_set_infoframes() */
697 val
|= VIDEO_DIP_SELECT_AVI
| VIDEO_DIP_FREQ_VSYNC
;
700 if (!(val
& VIDEO_DIP_ENABLE
))
702 val
&= ~(VIDEO_DIP_ENABLE
| VIDEO_DIP_ENABLE_AVI
|
703 VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_GAMUT
|
704 VIDEO_DIP_ENABLE_SPD
| VIDEO_DIP_ENABLE_GCP
);
705 I915_WRITE(reg
, val
);
710 if (port
!= (val
& VIDEO_DIP_PORT_MASK
)) {
711 WARN(val
& VIDEO_DIP_ENABLE
,
712 "DIP already enabled on port %c\n",
713 (val
& VIDEO_DIP_PORT_MASK
) >> 29);
714 val
&= ~VIDEO_DIP_PORT_MASK
;
718 val
|= VIDEO_DIP_ENABLE
;
719 val
&= ~(VIDEO_DIP_ENABLE_AVI
|
720 VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_GAMUT
|
721 VIDEO_DIP_ENABLE_SPD
| VIDEO_DIP_ENABLE_GCP
);
723 if (intel_hdmi_set_gcp_infoframe(encoder
, crtc_state
, conn_state
))
724 val
|= VIDEO_DIP_ENABLE_GCP
;
726 I915_WRITE(reg
, val
);
729 intel_hdmi_set_avi_infoframe(encoder
, crtc_state
);
730 intel_hdmi_set_spd_infoframe(encoder
, crtc_state
);
731 intel_hdmi_set_hdmi_infoframe(encoder
, crtc_state
, conn_state
);
734 static void cpt_set_infoframes(struct drm_encoder
*encoder
,
736 const struct intel_crtc_state
*crtc_state
,
737 const struct drm_connector_state
*conn_state
)
739 struct drm_i915_private
*dev_priv
= to_i915(encoder
->dev
);
740 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
741 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
742 i915_reg_t reg
= TVIDEO_DIP_CTL(intel_crtc
->pipe
);
743 u32 val
= I915_READ(reg
);
745 assert_hdmi_port_disabled(intel_hdmi
);
747 /* See the big comment in g4x_set_infoframes() */
748 val
|= VIDEO_DIP_SELECT_AVI
| VIDEO_DIP_FREQ_VSYNC
;
751 if (!(val
& VIDEO_DIP_ENABLE
))
753 val
&= ~(VIDEO_DIP_ENABLE
| VIDEO_DIP_ENABLE_AVI
|
754 VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_GAMUT
|
755 VIDEO_DIP_ENABLE_SPD
| VIDEO_DIP_ENABLE_GCP
);
756 I915_WRITE(reg
, val
);
761 /* Set both together, unset both together: see the spec. */
762 val
|= VIDEO_DIP_ENABLE
| VIDEO_DIP_ENABLE_AVI
;
763 val
&= ~(VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_GAMUT
|
764 VIDEO_DIP_ENABLE_SPD
| VIDEO_DIP_ENABLE_GCP
);
766 if (intel_hdmi_set_gcp_infoframe(encoder
, crtc_state
, conn_state
))
767 val
|= VIDEO_DIP_ENABLE_GCP
;
769 I915_WRITE(reg
, val
);
772 intel_hdmi_set_avi_infoframe(encoder
, crtc_state
);
773 intel_hdmi_set_spd_infoframe(encoder
, crtc_state
);
774 intel_hdmi_set_hdmi_infoframe(encoder
, crtc_state
, conn_state
);
777 static void vlv_set_infoframes(struct drm_encoder
*encoder
,
779 const struct intel_crtc_state
*crtc_state
,
780 const struct drm_connector_state
*conn_state
)
782 struct drm_i915_private
*dev_priv
= to_i915(encoder
->dev
);
783 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
784 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
785 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
786 i915_reg_t reg
= VLV_TVIDEO_DIP_CTL(intel_crtc
->pipe
);
787 u32 val
= I915_READ(reg
);
788 u32 port
= VIDEO_DIP_PORT(intel_dig_port
->port
);
790 assert_hdmi_port_disabled(intel_hdmi
);
792 /* See the big comment in g4x_set_infoframes() */
793 val
|= VIDEO_DIP_SELECT_AVI
| VIDEO_DIP_FREQ_VSYNC
;
796 if (!(val
& VIDEO_DIP_ENABLE
))
798 val
&= ~(VIDEO_DIP_ENABLE
| VIDEO_DIP_ENABLE_AVI
|
799 VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_GAMUT
|
800 VIDEO_DIP_ENABLE_SPD
| VIDEO_DIP_ENABLE_GCP
);
801 I915_WRITE(reg
, val
);
806 if (port
!= (val
& VIDEO_DIP_PORT_MASK
)) {
807 WARN(val
& VIDEO_DIP_ENABLE
,
808 "DIP already enabled on port %c\n",
809 (val
& VIDEO_DIP_PORT_MASK
) >> 29);
810 val
&= ~VIDEO_DIP_PORT_MASK
;
814 val
|= VIDEO_DIP_ENABLE
;
815 val
&= ~(VIDEO_DIP_ENABLE_AVI
|
816 VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_GAMUT
|
817 VIDEO_DIP_ENABLE_SPD
| VIDEO_DIP_ENABLE_GCP
);
819 if (intel_hdmi_set_gcp_infoframe(encoder
, crtc_state
, conn_state
))
820 val
|= VIDEO_DIP_ENABLE_GCP
;
822 I915_WRITE(reg
, val
);
825 intel_hdmi_set_avi_infoframe(encoder
, crtc_state
);
826 intel_hdmi_set_spd_infoframe(encoder
, crtc_state
);
827 intel_hdmi_set_hdmi_infoframe(encoder
, crtc_state
, conn_state
);
830 static void hsw_set_infoframes(struct drm_encoder
*encoder
,
832 const struct intel_crtc_state
*crtc_state
,
833 const struct drm_connector_state
*conn_state
)
835 struct drm_i915_private
*dev_priv
= to_i915(encoder
->dev
);
836 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
837 i915_reg_t reg
= HSW_TVIDEO_DIP_CTL(crtc_state
->cpu_transcoder
);
838 u32 val
= I915_READ(reg
);
840 assert_hdmi_port_disabled(intel_hdmi
);
842 val
&= ~(VIDEO_DIP_ENABLE_VSC_HSW
| VIDEO_DIP_ENABLE_AVI_HSW
|
843 VIDEO_DIP_ENABLE_GCP_HSW
| VIDEO_DIP_ENABLE_VS_HSW
|
844 VIDEO_DIP_ENABLE_GMP_HSW
| VIDEO_DIP_ENABLE_SPD_HSW
);
847 I915_WRITE(reg
, val
);
852 if (intel_hdmi_set_gcp_infoframe(encoder
, crtc_state
, conn_state
))
853 val
|= VIDEO_DIP_ENABLE_GCP_HSW
;
855 I915_WRITE(reg
, val
);
858 intel_hdmi_set_avi_infoframe(encoder
, crtc_state
);
859 intel_hdmi_set_spd_infoframe(encoder
, crtc_state
);
860 intel_hdmi_set_hdmi_infoframe(encoder
, crtc_state
, conn_state
);
863 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi
*hdmi
, bool enable
)
865 struct drm_i915_private
*dev_priv
= to_i915(intel_hdmi_to_dev(hdmi
));
866 struct i2c_adapter
*adapter
=
867 intel_gmbus_get_adapter(dev_priv
, hdmi
->ddc_bus
);
869 if (hdmi
->dp_dual_mode
.type
< DRM_DP_DUAL_MODE_TYPE2_DVI
)
872 DRM_DEBUG_KMS("%s DP dual mode adaptor TMDS output\n",
873 enable
? "Enabling" : "Disabling");
875 drm_dp_dual_mode_set_tmds_output(hdmi
->dp_dual_mode
.type
,
879 static void intel_hdmi_prepare(struct intel_encoder
*encoder
,
880 const struct intel_crtc_state
*crtc_state
)
882 struct drm_device
*dev
= encoder
->base
.dev
;
883 struct drm_i915_private
*dev_priv
= to_i915(dev
);
884 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
885 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
886 const struct drm_display_mode
*adjusted_mode
= &crtc_state
->base
.adjusted_mode
;
889 intel_dp_dual_mode_set_tmds_output(intel_hdmi
, true);
891 hdmi_val
= SDVO_ENCODING_HDMI
;
892 if (!HAS_PCH_SPLIT(dev_priv
) && crtc_state
->limited_color_range
)
893 hdmi_val
|= HDMI_COLOR_RANGE_16_235
;
894 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
895 hdmi_val
|= SDVO_VSYNC_ACTIVE_HIGH
;
896 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
897 hdmi_val
|= SDVO_HSYNC_ACTIVE_HIGH
;
899 if (crtc_state
->pipe_bpp
> 24)
900 hdmi_val
|= HDMI_COLOR_FORMAT_12bpc
;
902 hdmi_val
|= SDVO_COLOR_FORMAT_8bpc
;
904 if (crtc_state
->has_hdmi_sink
)
905 hdmi_val
|= HDMI_MODE_SELECT_HDMI
;
907 if (HAS_PCH_CPT(dev_priv
))
908 hdmi_val
|= SDVO_PIPE_SEL_CPT(crtc
->pipe
);
909 else if (IS_CHERRYVIEW(dev_priv
))
910 hdmi_val
|= SDVO_PIPE_SEL_CHV(crtc
->pipe
);
912 hdmi_val
|= SDVO_PIPE_SEL(crtc
->pipe
);
914 I915_WRITE(intel_hdmi
->hdmi_reg
, hdmi_val
);
915 POSTING_READ(intel_hdmi
->hdmi_reg
);
918 static bool intel_hdmi_get_hw_state(struct intel_encoder
*encoder
,
921 struct drm_device
*dev
= encoder
->base
.dev
;
922 struct drm_i915_private
*dev_priv
= to_i915(dev
);
923 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
927 if (!intel_display_power_get_if_enabled(dev_priv
,
928 encoder
->power_domain
))
933 tmp
= I915_READ(intel_hdmi
->hdmi_reg
);
935 if (!(tmp
& SDVO_ENABLE
))
938 if (HAS_PCH_CPT(dev_priv
))
939 *pipe
= PORT_TO_PIPE_CPT(tmp
);
940 else if (IS_CHERRYVIEW(dev_priv
))
941 *pipe
= SDVO_PORT_TO_PIPE_CHV(tmp
);
943 *pipe
= PORT_TO_PIPE(tmp
);
948 intel_display_power_put(dev_priv
, encoder
->power_domain
);
953 static void intel_hdmi_get_config(struct intel_encoder
*encoder
,
954 struct intel_crtc_state
*pipe_config
)
956 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
957 struct intel_digital_port
*intel_dig_port
= hdmi_to_dig_port(intel_hdmi
);
958 struct drm_device
*dev
= encoder
->base
.dev
;
959 struct drm_i915_private
*dev_priv
= to_i915(dev
);
963 tmp
= I915_READ(intel_hdmi
->hdmi_reg
);
965 if (tmp
& SDVO_HSYNC_ACTIVE_HIGH
)
966 flags
|= DRM_MODE_FLAG_PHSYNC
;
968 flags
|= DRM_MODE_FLAG_NHSYNC
;
970 if (tmp
& SDVO_VSYNC_ACTIVE_HIGH
)
971 flags
|= DRM_MODE_FLAG_PVSYNC
;
973 flags
|= DRM_MODE_FLAG_NVSYNC
;
975 if (tmp
& HDMI_MODE_SELECT_HDMI
)
976 pipe_config
->has_hdmi_sink
= true;
978 if (intel_dig_port
->infoframe_enabled(&encoder
->base
, pipe_config
))
979 pipe_config
->has_infoframe
= true;
981 if (tmp
& SDVO_AUDIO_ENABLE
)
982 pipe_config
->has_audio
= true;
984 if (!HAS_PCH_SPLIT(dev_priv
) &&
985 tmp
& HDMI_COLOR_RANGE_16_235
)
986 pipe_config
->limited_color_range
= true;
988 pipe_config
->base
.adjusted_mode
.flags
|= flags
;
990 if ((tmp
& SDVO_COLOR_FORMAT_MASK
) == HDMI_COLOR_FORMAT_12bpc
)
991 dotclock
= pipe_config
->port_clock
* 2 / 3;
993 dotclock
= pipe_config
->port_clock
;
995 if (pipe_config
->pixel_multiplier
)
996 dotclock
/= pipe_config
->pixel_multiplier
;
998 pipe_config
->base
.adjusted_mode
.crtc_clock
= dotclock
;
1000 pipe_config
->lane_count
= 4;
1003 static void intel_enable_hdmi_audio(struct intel_encoder
*encoder
,
1004 const struct intel_crtc_state
*pipe_config
,
1005 const struct drm_connector_state
*conn_state
)
1007 struct intel_crtc
*crtc
= to_intel_crtc(pipe_config
->base
.crtc
);
1009 WARN_ON(!pipe_config
->has_hdmi_sink
);
1010 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
1011 pipe_name(crtc
->pipe
));
1012 intel_audio_codec_enable(encoder
, pipe_config
, conn_state
);
1015 static void g4x_enable_hdmi(struct intel_encoder
*encoder
,
1016 const struct intel_crtc_state
*pipe_config
,
1017 const struct drm_connector_state
*conn_state
)
1019 struct drm_device
*dev
= encoder
->base
.dev
;
1020 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1021 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
1024 temp
= I915_READ(intel_hdmi
->hdmi_reg
);
1026 temp
|= SDVO_ENABLE
;
1027 if (pipe_config
->has_audio
)
1028 temp
|= SDVO_AUDIO_ENABLE
;
1030 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
);
1031 POSTING_READ(intel_hdmi
->hdmi_reg
);
1033 if (pipe_config
->has_audio
)
1034 intel_enable_hdmi_audio(encoder
, pipe_config
, conn_state
);
1037 static void ibx_enable_hdmi(struct intel_encoder
*encoder
,
1038 const struct intel_crtc_state
*pipe_config
,
1039 const struct drm_connector_state
*conn_state
)
1041 struct drm_device
*dev
= encoder
->base
.dev
;
1042 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1043 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
1046 temp
= I915_READ(intel_hdmi
->hdmi_reg
);
1048 temp
|= SDVO_ENABLE
;
1049 if (pipe_config
->has_audio
)
1050 temp
|= SDVO_AUDIO_ENABLE
;
1053 * HW workaround, need to write this twice for issue
1054 * that may result in first write getting masked.
1056 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
);
1057 POSTING_READ(intel_hdmi
->hdmi_reg
);
1058 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
);
1059 POSTING_READ(intel_hdmi
->hdmi_reg
);
1062 * HW workaround, need to toggle enable bit off and on
1063 * for 12bpc with pixel repeat.
1065 * FIXME: BSpec says this should be done at the end of
1066 * of the modeset sequence, so not sure if this isn't too soon.
1068 if (pipe_config
->pipe_bpp
> 24 &&
1069 pipe_config
->pixel_multiplier
> 1) {
1070 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
& ~SDVO_ENABLE
);
1071 POSTING_READ(intel_hdmi
->hdmi_reg
);
1074 * HW workaround, need to write this twice for issue
1075 * that may result in first write getting masked.
1077 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
);
1078 POSTING_READ(intel_hdmi
->hdmi_reg
);
1079 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
);
1080 POSTING_READ(intel_hdmi
->hdmi_reg
);
1083 if (pipe_config
->has_audio
)
1084 intel_enable_hdmi_audio(encoder
, pipe_config
, conn_state
);
1087 static void cpt_enable_hdmi(struct intel_encoder
*encoder
,
1088 const struct intel_crtc_state
*pipe_config
,
1089 const struct drm_connector_state
*conn_state
)
1091 struct drm_device
*dev
= encoder
->base
.dev
;
1092 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1093 struct intel_crtc
*crtc
= to_intel_crtc(pipe_config
->base
.crtc
);
1094 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
1095 enum pipe pipe
= crtc
->pipe
;
1098 temp
= I915_READ(intel_hdmi
->hdmi_reg
);
1100 temp
|= SDVO_ENABLE
;
1101 if (pipe_config
->has_audio
)
1102 temp
|= SDVO_AUDIO_ENABLE
;
1105 * WaEnableHDMI8bpcBefore12bpc:snb,ivb
1107 * The procedure for 12bpc is as follows:
1108 * 1. disable HDMI clock gating
1109 * 2. enable HDMI with 8bpc
1110 * 3. enable HDMI with 12bpc
1111 * 4. enable HDMI clock gating
1114 if (pipe_config
->pipe_bpp
> 24) {
1115 I915_WRITE(TRANS_CHICKEN1(pipe
),
1116 I915_READ(TRANS_CHICKEN1(pipe
)) |
1117 TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE
);
1119 temp
&= ~SDVO_COLOR_FORMAT_MASK
;
1120 temp
|= SDVO_COLOR_FORMAT_8bpc
;
1123 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
);
1124 POSTING_READ(intel_hdmi
->hdmi_reg
);
1126 if (pipe_config
->pipe_bpp
> 24) {
1127 temp
&= ~SDVO_COLOR_FORMAT_MASK
;
1128 temp
|= HDMI_COLOR_FORMAT_12bpc
;
1130 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
);
1131 POSTING_READ(intel_hdmi
->hdmi_reg
);
1133 I915_WRITE(TRANS_CHICKEN1(pipe
),
1134 I915_READ(TRANS_CHICKEN1(pipe
)) &
1135 ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE
);
1138 if (pipe_config
->has_audio
)
1139 intel_enable_hdmi_audio(encoder
, pipe_config
, conn_state
);
1142 static void vlv_enable_hdmi(struct intel_encoder
*encoder
,
1143 const struct intel_crtc_state
*pipe_config
,
1144 const struct drm_connector_state
*conn_state
)
1148 static void intel_disable_hdmi(struct intel_encoder
*encoder
,
1149 const struct intel_crtc_state
*old_crtc_state
,
1150 const struct drm_connector_state
*old_conn_state
)
1152 struct drm_device
*dev
= encoder
->base
.dev
;
1153 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1154 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
1155 struct intel_digital_port
*intel_dig_port
=
1156 hdmi_to_dig_port(intel_hdmi
);
1157 struct intel_crtc
*crtc
= to_intel_crtc(old_crtc_state
->base
.crtc
);
1160 temp
= I915_READ(intel_hdmi
->hdmi_reg
);
1162 temp
&= ~(SDVO_ENABLE
| SDVO_AUDIO_ENABLE
);
1163 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
);
1164 POSTING_READ(intel_hdmi
->hdmi_reg
);
1167 * HW workaround for IBX, we need to move the port
1168 * to transcoder A after disabling it to allow the
1169 * matching DP port to be enabled on transcoder A.
1171 if (HAS_PCH_IBX(dev_priv
) && crtc
->pipe
== PIPE_B
) {
1173 * We get CPU/PCH FIFO underruns on the other pipe when
1174 * doing the workaround. Sweep them under the rug.
1176 intel_set_cpu_fifo_underrun_reporting(dev_priv
, PIPE_A
, false);
1177 intel_set_pch_fifo_underrun_reporting(dev_priv
, PIPE_A
, false);
1179 temp
&= ~SDVO_PIPE_B_SELECT
;
1180 temp
|= SDVO_ENABLE
;
1182 * HW workaround, need to write this twice for issue
1183 * that may result in first write getting masked.
1185 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
);
1186 POSTING_READ(intel_hdmi
->hdmi_reg
);
1187 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
);
1188 POSTING_READ(intel_hdmi
->hdmi_reg
);
1190 temp
&= ~SDVO_ENABLE
;
1191 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
);
1192 POSTING_READ(intel_hdmi
->hdmi_reg
);
1194 intel_wait_for_vblank_if_active(dev_priv
, PIPE_A
);
1195 intel_set_cpu_fifo_underrun_reporting(dev_priv
, PIPE_A
, true);
1196 intel_set_pch_fifo_underrun_reporting(dev_priv
, PIPE_A
, true);
1199 intel_dig_port
->set_infoframes(&encoder
->base
, false,
1200 old_crtc_state
, old_conn_state
);
1202 intel_dp_dual_mode_set_tmds_output(intel_hdmi
, false);
1205 static void g4x_disable_hdmi(struct intel_encoder
*encoder
,
1206 const struct intel_crtc_state
*old_crtc_state
,
1207 const struct drm_connector_state
*old_conn_state
)
1209 if (old_crtc_state
->has_audio
)
1210 intel_audio_codec_disable(encoder
);
1212 intel_disable_hdmi(encoder
, old_crtc_state
, old_conn_state
);
1215 static void pch_disable_hdmi(struct intel_encoder
*encoder
,
1216 const struct intel_crtc_state
*old_crtc_state
,
1217 const struct drm_connector_state
*old_conn_state
)
1219 if (old_crtc_state
->has_audio
)
1220 intel_audio_codec_disable(encoder
);
1223 static void pch_post_disable_hdmi(struct intel_encoder
*encoder
,
1224 const struct intel_crtc_state
*old_crtc_state
,
1225 const struct drm_connector_state
*old_conn_state
)
1227 intel_disable_hdmi(encoder
, old_crtc_state
, old_conn_state
);
1230 static int intel_hdmi_source_max_tmds_clock(struct drm_i915_private
*dev_priv
)
1232 if (IS_G4X(dev_priv
))
1234 else if (IS_GEMINILAKE(dev_priv
))
1236 else if (IS_HASWELL(dev_priv
) || INTEL_INFO(dev_priv
)->gen
>= 8)
1242 static int hdmi_port_clock_limit(struct intel_hdmi
*hdmi
,
1243 bool respect_downstream_limits
,
1246 struct drm_device
*dev
= intel_hdmi_to_dev(hdmi
);
1247 int max_tmds_clock
= intel_hdmi_source_max_tmds_clock(to_i915(dev
));
1249 if (respect_downstream_limits
) {
1250 struct intel_connector
*connector
= hdmi
->attached_connector
;
1251 const struct drm_display_info
*info
= &connector
->base
.display_info
;
1253 if (hdmi
->dp_dual_mode
.max_tmds_clock
)
1254 max_tmds_clock
= min(max_tmds_clock
,
1255 hdmi
->dp_dual_mode
.max_tmds_clock
);
1257 if (info
->max_tmds_clock
)
1258 max_tmds_clock
= min(max_tmds_clock
,
1259 info
->max_tmds_clock
);
1260 else if (!hdmi
->has_hdmi_sink
|| force_dvi
)
1261 max_tmds_clock
= min(max_tmds_clock
, 165000);
1264 return max_tmds_clock
;
1267 static enum drm_mode_status
1268 hdmi_port_clock_valid(struct intel_hdmi
*hdmi
,
1269 int clock
, bool respect_downstream_limits
,
1272 struct drm_i915_private
*dev_priv
= to_i915(intel_hdmi_to_dev(hdmi
));
1275 return MODE_CLOCK_LOW
;
1276 if (clock
> hdmi_port_clock_limit(hdmi
, respect_downstream_limits
, force_dvi
))
1277 return MODE_CLOCK_HIGH
;
1279 /* BXT DPLL can't generate 223-240 MHz */
1280 if (IS_GEN9_LP(dev_priv
) && clock
> 223333 && clock
< 240000)
1281 return MODE_CLOCK_RANGE
;
1283 /* CHV DPLL can't generate 216-240 MHz */
1284 if (IS_CHERRYVIEW(dev_priv
) && clock
> 216000 && clock
< 240000)
1285 return MODE_CLOCK_RANGE
;
1290 static enum drm_mode_status
1291 intel_hdmi_mode_valid(struct drm_connector
*connector
,
1292 struct drm_display_mode
*mode
)
1294 struct intel_hdmi
*hdmi
= intel_attached_hdmi(connector
);
1295 struct drm_device
*dev
= intel_hdmi_to_dev(hdmi
);
1296 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1297 enum drm_mode_status status
;
1299 int max_dotclk
= to_i915(connector
->dev
)->max_dotclk_freq
;
1301 READ_ONCE(to_intel_digital_connector_state(connector
->state
)->force_audio
) == HDMI_AUDIO_OFF_DVI
;
1303 if (mode
->flags
& DRM_MODE_FLAG_DBLSCAN
)
1304 return MODE_NO_DBLESCAN
;
1306 clock
= mode
->clock
;
1308 if ((mode
->flags
& DRM_MODE_FLAG_3D_MASK
) == DRM_MODE_FLAG_3D_FRAME_PACKING
)
1311 if (clock
> max_dotclk
)
1312 return MODE_CLOCK_HIGH
;
1314 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
1317 if (drm_mode_is_420_only(&connector
->display_info
, mode
))
1320 /* check if we can do 8bpc */
1321 status
= hdmi_port_clock_valid(hdmi
, clock
, true, force_dvi
);
1323 /* if we can't do 8bpc we may still be able to do 12bpc */
1324 if (!HAS_GMCH_DISPLAY(dev_priv
) && status
!= MODE_OK
&& hdmi
->has_hdmi_sink
&& !force_dvi
)
1325 status
= hdmi_port_clock_valid(hdmi
, clock
* 3 / 2, true, force_dvi
);
1330 static bool hdmi_12bpc_possible(const struct intel_crtc_state
*crtc_state
)
1332 struct drm_i915_private
*dev_priv
=
1333 to_i915(crtc_state
->base
.crtc
->dev
);
1334 struct drm_atomic_state
*state
= crtc_state
->base
.state
;
1335 struct drm_connector_state
*connector_state
;
1336 struct drm_connector
*connector
;
1339 if (HAS_GMCH_DISPLAY(dev_priv
))
1343 * HDMI 12bpc affects the clocks, so it's only possible
1344 * when not cloning with other encoder types.
1346 if (crtc_state
->output_types
!= 1 << INTEL_OUTPUT_HDMI
)
1349 for_each_new_connector_in_state(state
, connector
, connector_state
, i
) {
1350 const struct drm_display_info
*info
= &connector
->display_info
;
1352 if (connector_state
->crtc
!= crtc_state
->base
.crtc
)
1355 if (crtc_state
->ycbcr420
) {
1356 const struct drm_hdmi_info
*hdmi
= &info
->hdmi
;
1358 if (!(hdmi
->y420_dc_modes
& DRM_EDID_YCBCR420_DC_36
))
1361 if (!(info
->edid_hdmi_dc_modes
& DRM_EDID_HDMI_DC_36
))
1366 /* Display Wa #1139 */
1367 if (IS_GLK_REVID(dev_priv
, 0, GLK_REVID_A1
) &&
1368 crtc_state
->base
.adjusted_mode
.htotal
> 5460)
1375 intel_hdmi_ycbcr420_config(struct drm_connector
*connector
,
1376 struct intel_crtc_state
*config
,
1377 int *clock_12bpc
, int *clock_8bpc
)
1379 struct intel_crtc
*intel_crtc
= to_intel_crtc(config
->base
.crtc
);
1381 if (!connector
->ycbcr_420_allowed
) {
1382 DRM_ERROR("Platform doesn't support YCBCR420 output\n");
1386 /* YCBCR420 TMDS rate requirement is half the pixel clock */
1387 config
->port_clock
/= 2;
1390 config
->ycbcr420
= true;
1392 /* YCBCR 420 output conversion needs a scaler */
1393 if (skl_update_scaler_crtc(config
)) {
1394 DRM_DEBUG_KMS("Scaler allocation for output failed\n");
1398 intel_pch_panel_fitting(intel_crtc
, config
,
1399 DRM_MODE_SCALE_FULLSCREEN
);
1404 bool intel_hdmi_compute_config(struct intel_encoder
*encoder
,
1405 struct intel_crtc_state
*pipe_config
,
1406 struct drm_connector_state
*conn_state
)
1408 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
1409 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
1410 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
1411 struct drm_connector
*connector
= conn_state
->connector
;
1412 struct drm_scdc
*scdc
= &connector
->display_info
.hdmi
.scdc
;
1413 struct intel_digital_connector_state
*intel_conn_state
=
1414 to_intel_digital_connector_state(conn_state
);
1415 int clock_8bpc
= pipe_config
->base
.adjusted_mode
.crtc_clock
;
1416 int clock_12bpc
= clock_8bpc
* 3 / 2;
1418 bool force_dvi
= intel_conn_state
->force_audio
== HDMI_AUDIO_OFF_DVI
;
1420 pipe_config
->has_hdmi_sink
= !force_dvi
&& intel_hdmi
->has_hdmi_sink
;
1422 if (pipe_config
->has_hdmi_sink
)
1423 pipe_config
->has_infoframe
= true;
1425 if (intel_conn_state
->broadcast_rgb
== INTEL_BROADCAST_RGB_AUTO
) {
1426 /* See CEA-861-E - 5.1 Default Encoding Parameters */
1427 pipe_config
->limited_color_range
=
1428 pipe_config
->has_hdmi_sink
&&
1429 drm_default_rgb_quant_range(adjusted_mode
) ==
1430 HDMI_QUANTIZATION_RANGE_LIMITED
;
1432 pipe_config
->limited_color_range
=
1433 intel_conn_state
->broadcast_rgb
== INTEL_BROADCAST_RGB_LIMITED
;
1436 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
) {
1437 pipe_config
->pixel_multiplier
= 2;
1442 if (drm_mode_is_420_only(&connector
->display_info
, adjusted_mode
)) {
1443 if (!intel_hdmi_ycbcr420_config(connector
, pipe_config
,
1444 &clock_12bpc
, &clock_8bpc
)) {
1445 DRM_ERROR("Can't support YCBCR420 output\n");
1450 if (HAS_PCH_SPLIT(dev_priv
) && !HAS_DDI(dev_priv
))
1451 pipe_config
->has_pch_encoder
= true;
1453 if (pipe_config
->has_hdmi_sink
) {
1454 if (intel_conn_state
->force_audio
== HDMI_AUDIO_AUTO
)
1455 pipe_config
->has_audio
= intel_hdmi
->has_audio
;
1457 pipe_config
->has_audio
=
1458 intel_conn_state
->force_audio
== HDMI_AUDIO_ON
;
1462 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
1463 * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
1464 * outputs. We also need to check that the higher clock still fits
1467 if (pipe_config
->pipe_bpp
> 8*3 && pipe_config
->has_hdmi_sink
&& !force_dvi
&&
1468 hdmi_port_clock_valid(intel_hdmi
, clock_12bpc
, true, force_dvi
) == MODE_OK
&&
1469 hdmi_12bpc_possible(pipe_config
)) {
1470 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
1473 /* Need to adjust the port link by 1.5x for 12bpc. */
1474 pipe_config
->port_clock
= clock_12bpc
;
1476 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
1479 pipe_config
->port_clock
= clock_8bpc
;
1482 if (!pipe_config
->bw_constrained
) {
1483 DRM_DEBUG_KMS("forcing pipe bpp to %i for HDMI\n", desired_bpp
);
1484 pipe_config
->pipe_bpp
= desired_bpp
;
1487 if (hdmi_port_clock_valid(intel_hdmi
, pipe_config
->port_clock
,
1488 false, force_dvi
) != MODE_OK
) {
1489 DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n");
1493 /* Set user selected PAR to incoming mode's member */
1494 adjusted_mode
->picture_aspect_ratio
= conn_state
->picture_aspect_ratio
;
1496 pipe_config
->lane_count
= 4;
1498 if (scdc
->scrambling
.supported
&& IS_GEMINILAKE(dev_priv
)) {
1499 if (scdc
->scrambling
.low_rates
)
1500 pipe_config
->hdmi_scrambling
= true;
1502 if (pipe_config
->port_clock
> 340000) {
1503 pipe_config
->hdmi_scrambling
= true;
1504 pipe_config
->hdmi_high_tmds_clock_ratio
= true;
1512 intel_hdmi_unset_edid(struct drm_connector
*connector
)
1514 struct intel_hdmi
*intel_hdmi
= intel_attached_hdmi(connector
);
1516 intel_hdmi
->has_hdmi_sink
= false;
1517 intel_hdmi
->has_audio
= false;
1518 intel_hdmi
->rgb_quant_range_selectable
= false;
1520 intel_hdmi
->dp_dual_mode
.type
= DRM_DP_DUAL_MODE_NONE
;
1521 intel_hdmi
->dp_dual_mode
.max_tmds_clock
= 0;
1523 kfree(to_intel_connector(connector
)->detect_edid
);
1524 to_intel_connector(connector
)->detect_edid
= NULL
;
1528 intel_hdmi_dp_dual_mode_detect(struct drm_connector
*connector
, bool has_edid
)
1530 struct drm_i915_private
*dev_priv
= to_i915(connector
->dev
);
1531 struct intel_hdmi
*hdmi
= intel_attached_hdmi(connector
);
1532 enum port port
= hdmi_to_dig_port(hdmi
)->port
;
1533 struct i2c_adapter
*adapter
=
1534 intel_gmbus_get_adapter(dev_priv
, hdmi
->ddc_bus
);
1535 enum drm_dp_dual_mode_type type
= drm_dp_dual_mode_detect(adapter
);
1538 * Type 1 DVI adaptors are not required to implement any
1539 * registers, so we can't always detect their presence.
1540 * Ideally we should be able to check the state of the
1541 * CONFIG1 pin, but no such luck on our hardware.
1543 * The only method left to us is to check the VBT to see
1544 * if the port is a dual mode capable DP port. But let's
1545 * only do that when we sucesfully read the EDID, to avoid
1546 * confusing log messages about DP dual mode adaptors when
1547 * there's nothing connected to the port.
1549 if (type
== DRM_DP_DUAL_MODE_UNKNOWN
) {
1551 intel_bios_is_port_dp_dual_mode(dev_priv
, port
)) {
1552 DRM_DEBUG_KMS("Assuming DP dual mode adaptor presence based on VBT\n");
1553 type
= DRM_DP_DUAL_MODE_TYPE1_DVI
;
1555 type
= DRM_DP_DUAL_MODE_NONE
;
1559 if (type
== DRM_DP_DUAL_MODE_NONE
)
1562 hdmi
->dp_dual_mode
.type
= type
;
1563 hdmi
->dp_dual_mode
.max_tmds_clock
=
1564 drm_dp_dual_mode_max_tmds_clock(type
, adapter
);
1566 DRM_DEBUG_KMS("DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n",
1567 drm_dp_get_dual_mode_type_name(type
),
1568 hdmi
->dp_dual_mode
.max_tmds_clock
);
1572 intel_hdmi_set_edid(struct drm_connector
*connector
)
1574 struct drm_i915_private
*dev_priv
= to_i915(connector
->dev
);
1575 struct intel_hdmi
*intel_hdmi
= intel_attached_hdmi(connector
);
1577 bool connected
= false;
1579 intel_display_power_get(dev_priv
, POWER_DOMAIN_GMBUS
);
1581 edid
= drm_get_edid(connector
,
1582 intel_gmbus_get_adapter(dev_priv
,
1583 intel_hdmi
->ddc_bus
));
1585 intel_hdmi_dp_dual_mode_detect(connector
, edid
!= NULL
);
1587 intel_display_power_put(dev_priv
, POWER_DOMAIN_GMBUS
);
1589 to_intel_connector(connector
)->detect_edid
= edid
;
1590 if (edid
&& edid
->input
& DRM_EDID_INPUT_DIGITAL
) {
1591 intel_hdmi
->rgb_quant_range_selectable
=
1592 drm_rgb_quant_range_selectable(edid
);
1594 intel_hdmi
->has_audio
= drm_detect_monitor_audio(edid
);
1595 intel_hdmi
->has_hdmi_sink
= drm_detect_hdmi_monitor(edid
);
1603 static enum drm_connector_status
1604 intel_hdmi_detect(struct drm_connector
*connector
, bool force
)
1606 enum drm_connector_status status
;
1607 struct drm_i915_private
*dev_priv
= to_i915(connector
->dev
);
1609 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1610 connector
->base
.id
, connector
->name
);
1612 intel_display_power_get(dev_priv
, POWER_DOMAIN_GMBUS
);
1614 intel_hdmi_unset_edid(connector
);
1616 if (intel_hdmi_set_edid(connector
)) {
1617 struct intel_hdmi
*intel_hdmi
= intel_attached_hdmi(connector
);
1619 hdmi_to_dig_port(intel_hdmi
)->base
.type
= INTEL_OUTPUT_HDMI
;
1620 status
= connector_status_connected
;
1622 status
= connector_status_disconnected
;
1624 intel_display_power_put(dev_priv
, POWER_DOMAIN_GMBUS
);
1630 intel_hdmi_force(struct drm_connector
*connector
)
1632 struct intel_hdmi
*intel_hdmi
= intel_attached_hdmi(connector
);
1634 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1635 connector
->base
.id
, connector
->name
);
1637 intel_hdmi_unset_edid(connector
);
1639 if (connector
->status
!= connector_status_connected
)
1642 intel_hdmi_set_edid(connector
);
1643 hdmi_to_dig_port(intel_hdmi
)->base
.type
= INTEL_OUTPUT_HDMI
;
1646 static int intel_hdmi_get_modes(struct drm_connector
*connector
)
1650 edid
= to_intel_connector(connector
)->detect_edid
;
1654 return intel_connector_update_modes(connector
, edid
);
1657 static void intel_hdmi_pre_enable(struct intel_encoder
*encoder
,
1658 const struct intel_crtc_state
*pipe_config
,
1659 const struct drm_connector_state
*conn_state
)
1661 struct intel_digital_port
*intel_dig_port
=
1662 enc_to_dig_port(&encoder
->base
);
1664 intel_hdmi_prepare(encoder
, pipe_config
);
1666 intel_dig_port
->set_infoframes(&encoder
->base
,
1667 pipe_config
->has_infoframe
,
1668 pipe_config
, conn_state
);
1671 static void vlv_hdmi_pre_enable(struct intel_encoder
*encoder
,
1672 const struct intel_crtc_state
*pipe_config
,
1673 const struct drm_connector_state
*conn_state
)
1675 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
1676 struct drm_device
*dev
= encoder
->base
.dev
;
1677 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1679 vlv_phy_pre_encoder_enable(encoder
);
1682 vlv_set_phy_signal_level(encoder
, 0x2b245f5f, 0x00002000, 0x5578b83a,
1685 dport
->set_infoframes(&encoder
->base
,
1686 pipe_config
->has_infoframe
,
1687 pipe_config
, conn_state
);
1689 g4x_enable_hdmi(encoder
, pipe_config
, conn_state
);
1691 vlv_wait_port_ready(dev_priv
, dport
, 0x0);
1694 static void vlv_hdmi_pre_pll_enable(struct intel_encoder
*encoder
,
1695 const struct intel_crtc_state
*pipe_config
,
1696 const struct drm_connector_state
*conn_state
)
1698 intel_hdmi_prepare(encoder
, pipe_config
);
1700 vlv_phy_pre_pll_enable(encoder
);
1703 static void chv_hdmi_pre_pll_enable(struct intel_encoder
*encoder
,
1704 const struct intel_crtc_state
*pipe_config
,
1705 const struct drm_connector_state
*conn_state
)
1707 intel_hdmi_prepare(encoder
, pipe_config
);
1709 chv_phy_pre_pll_enable(encoder
);
1712 static void chv_hdmi_post_pll_disable(struct intel_encoder
*encoder
,
1713 const struct intel_crtc_state
*old_crtc_state
,
1714 const struct drm_connector_state
*old_conn_state
)
1716 chv_phy_post_pll_disable(encoder
);
1719 static void vlv_hdmi_post_disable(struct intel_encoder
*encoder
,
1720 const struct intel_crtc_state
*old_crtc_state
,
1721 const struct drm_connector_state
*old_conn_state
)
1723 /* Reset lanes to avoid HDMI flicker (VLV w/a) */
1724 vlv_phy_reset_lanes(encoder
);
1727 static void chv_hdmi_post_disable(struct intel_encoder
*encoder
,
1728 const struct intel_crtc_state
*old_crtc_state
,
1729 const struct drm_connector_state
*old_conn_state
)
1731 struct drm_device
*dev
= encoder
->base
.dev
;
1732 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1734 mutex_lock(&dev_priv
->sb_lock
);
1736 /* Assert data lane reset */
1737 chv_data_lane_soft_reset(encoder
, true);
1739 mutex_unlock(&dev_priv
->sb_lock
);
1742 static void chv_hdmi_pre_enable(struct intel_encoder
*encoder
,
1743 const struct intel_crtc_state
*pipe_config
,
1744 const struct drm_connector_state
*conn_state
)
1746 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
1747 struct drm_device
*dev
= encoder
->base
.dev
;
1748 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1750 chv_phy_pre_encoder_enable(encoder
);
1752 /* FIXME: Program the support xxx V-dB */
1754 chv_set_phy_signal_level(encoder
, 128, 102, false);
1756 dport
->set_infoframes(&encoder
->base
,
1757 pipe_config
->has_infoframe
,
1758 pipe_config
, conn_state
);
1760 g4x_enable_hdmi(encoder
, pipe_config
, conn_state
);
1762 vlv_wait_port_ready(dev_priv
, dport
, 0x0);
1764 /* Second common lane will stay alive on its own now */
1765 chv_phy_release_cl2_override(encoder
);
1768 static void intel_hdmi_destroy(struct drm_connector
*connector
)
1770 kfree(to_intel_connector(connector
)->detect_edid
);
1771 drm_connector_cleanup(connector
);
1775 static const struct drm_connector_funcs intel_hdmi_connector_funcs
= {
1776 .detect
= intel_hdmi_detect
,
1777 .force
= intel_hdmi_force
,
1778 .fill_modes
= drm_helper_probe_single_connector_modes
,
1779 .atomic_get_property
= intel_digital_connector_atomic_get_property
,
1780 .atomic_set_property
= intel_digital_connector_atomic_set_property
,
1781 .late_register
= intel_connector_register
,
1782 .early_unregister
= intel_connector_unregister
,
1783 .destroy
= intel_hdmi_destroy
,
1784 .atomic_destroy_state
= drm_atomic_helper_connector_destroy_state
,
1785 .atomic_duplicate_state
= intel_digital_connector_duplicate_state
,
1788 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs
= {
1789 .get_modes
= intel_hdmi_get_modes
,
1790 .mode_valid
= intel_hdmi_mode_valid
,
1791 .atomic_check
= intel_digital_connector_atomic_check
,
1794 static const struct drm_encoder_funcs intel_hdmi_enc_funcs
= {
1795 .destroy
= intel_encoder_destroy
,
1799 intel_hdmi_add_properties(struct intel_hdmi
*intel_hdmi
, struct drm_connector
*connector
)
1801 intel_attach_force_audio_property(connector
);
1802 intel_attach_broadcast_rgb_property(connector
);
1803 intel_attach_aspect_ratio_property(connector
);
1804 connector
->state
->picture_aspect_ratio
= HDMI_PICTURE_ASPECT_NONE
;
1808 * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup
1809 * @encoder: intel_encoder
1810 * @connector: drm_connector
1811 * @high_tmds_clock_ratio = bool to indicate if the function needs to set
1812 * or reset the high tmds clock ratio for scrambling
1813 * @scrambling: bool to Indicate if the function needs to set or reset
1816 * This function handles scrambling on HDMI 2.0 capable sinks.
1817 * If required clock rate is > 340 Mhz && scrambling is supported by sink
1818 * it enables scrambling. This should be called before enabling the HDMI
1819 * 2.0 port, as the sink can choose to disable the scrambling if it doesn't
1820 * detect a scrambled clock within 100 ms.
1822 void intel_hdmi_handle_sink_scrambling(struct intel_encoder
*encoder
,
1823 struct drm_connector
*connector
,
1824 bool high_tmds_clock_ratio
,
1827 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
1828 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
1829 struct drm_scrambling
*sink_scrambling
=
1830 &connector
->display_info
.hdmi
.scdc
.scrambling
;
1831 struct i2c_adapter
*adptr
= intel_gmbus_get_adapter(dev_priv
,
1832 intel_hdmi
->ddc_bus
);
1835 if (!sink_scrambling
->supported
)
1838 DRM_DEBUG_KMS("Setting sink scrambling for enc:%s connector:%s\n",
1839 encoder
->base
.name
, connector
->name
);
1841 /* Set TMDS bit clock ratio to 1/40 or 1/10 */
1842 ret
= drm_scdc_set_high_tmds_clock_ratio(adptr
, high_tmds_clock_ratio
);
1844 DRM_ERROR("Set TMDS ratio failed\n");
1848 /* Enable/disable sink scrambling */
1849 ret
= drm_scdc_set_scrambling(adptr
, scrambling
);
1851 DRM_ERROR("Set sink scrambling failed\n");
1855 DRM_DEBUG_KMS("sink scrambling handled\n");
1858 static u8
chv_port_to_ddc_pin(struct drm_i915_private
*dev_priv
, enum port port
)
1864 ddc_pin
= GMBUS_PIN_DPB
;
1867 ddc_pin
= GMBUS_PIN_DPC
;
1870 ddc_pin
= GMBUS_PIN_DPD_CHV
;
1874 ddc_pin
= GMBUS_PIN_DPB
;
1880 static u8
bxt_port_to_ddc_pin(struct drm_i915_private
*dev_priv
, enum port port
)
1886 ddc_pin
= GMBUS_PIN_1_BXT
;
1889 ddc_pin
= GMBUS_PIN_2_BXT
;
1893 ddc_pin
= GMBUS_PIN_1_BXT
;
1899 static u8
cnp_port_to_ddc_pin(struct drm_i915_private
*dev_priv
,
1906 ddc_pin
= GMBUS_PIN_1_BXT
;
1909 ddc_pin
= GMBUS_PIN_2_BXT
;
1912 ddc_pin
= GMBUS_PIN_4_CNP
;
1916 ddc_pin
= GMBUS_PIN_1_BXT
;
1922 static u8
g4x_port_to_ddc_pin(struct drm_i915_private
*dev_priv
,
1929 ddc_pin
= GMBUS_PIN_DPB
;
1932 ddc_pin
= GMBUS_PIN_DPC
;
1935 ddc_pin
= GMBUS_PIN_DPD
;
1939 ddc_pin
= GMBUS_PIN_DPB
;
1945 static u8
intel_hdmi_ddc_pin(struct drm_i915_private
*dev_priv
,
1948 const struct ddi_vbt_port_info
*info
=
1949 &dev_priv
->vbt
.ddi_port_info
[port
];
1952 if (info
->alternate_ddc_pin
) {
1953 DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (VBT)\n",
1954 info
->alternate_ddc_pin
, port_name(port
));
1955 return info
->alternate_ddc_pin
;
1958 if (IS_CHERRYVIEW(dev_priv
))
1959 ddc_pin
= chv_port_to_ddc_pin(dev_priv
, port
);
1960 else if (IS_GEN9_LP(dev_priv
))
1961 ddc_pin
= bxt_port_to_ddc_pin(dev_priv
, port
);
1962 else if (HAS_PCH_CNP(dev_priv
))
1963 ddc_pin
= cnp_port_to_ddc_pin(dev_priv
, port
);
1965 ddc_pin
= g4x_port_to_ddc_pin(dev_priv
, port
);
1967 DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (platform default)\n",
1968 ddc_pin
, port_name(port
));
1973 void intel_infoframe_init(struct intel_digital_port
*intel_dig_port
)
1975 struct drm_i915_private
*dev_priv
=
1976 to_i915(intel_dig_port
->base
.base
.dev
);
1978 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
1979 intel_dig_port
->write_infoframe
= vlv_write_infoframe
;
1980 intel_dig_port
->set_infoframes
= vlv_set_infoframes
;
1981 intel_dig_port
->infoframe_enabled
= vlv_infoframe_enabled
;
1982 } else if (IS_G4X(dev_priv
)) {
1983 intel_dig_port
->write_infoframe
= g4x_write_infoframe
;
1984 intel_dig_port
->set_infoframes
= g4x_set_infoframes
;
1985 intel_dig_port
->infoframe_enabled
= g4x_infoframe_enabled
;
1986 } else if (HAS_DDI(dev_priv
)) {
1987 intel_dig_port
->write_infoframe
= hsw_write_infoframe
;
1988 intel_dig_port
->set_infoframes
= hsw_set_infoframes
;
1989 intel_dig_port
->infoframe_enabled
= hsw_infoframe_enabled
;
1990 } else if (HAS_PCH_IBX(dev_priv
)) {
1991 intel_dig_port
->write_infoframe
= ibx_write_infoframe
;
1992 intel_dig_port
->set_infoframes
= ibx_set_infoframes
;
1993 intel_dig_port
->infoframe_enabled
= ibx_infoframe_enabled
;
1995 intel_dig_port
->write_infoframe
= cpt_write_infoframe
;
1996 intel_dig_port
->set_infoframes
= cpt_set_infoframes
;
1997 intel_dig_port
->infoframe_enabled
= cpt_infoframe_enabled
;
2001 void intel_hdmi_init_connector(struct intel_digital_port
*intel_dig_port
,
2002 struct intel_connector
*intel_connector
)
2004 struct drm_connector
*connector
= &intel_connector
->base
;
2005 struct intel_hdmi
*intel_hdmi
= &intel_dig_port
->hdmi
;
2006 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
2007 struct drm_device
*dev
= intel_encoder
->base
.dev
;
2008 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2009 enum port port
= intel_dig_port
->port
;
2011 DRM_DEBUG_KMS("Adding HDMI connector on port %c\n",
2014 if (WARN(intel_dig_port
->max_lanes
< 4,
2015 "Not enough lanes (%d) for HDMI on port %c\n",
2016 intel_dig_port
->max_lanes
, port_name(port
)))
2019 drm_connector_init(dev
, connector
, &intel_hdmi_connector_funcs
,
2020 DRM_MODE_CONNECTOR_HDMIA
);
2021 drm_connector_helper_add(connector
, &intel_hdmi_connector_helper_funcs
);
2023 connector
->interlace_allowed
= 1;
2024 connector
->doublescan_allowed
= 0;
2025 connector
->stereo_allowed
= 1;
2027 if (IS_GEMINILAKE(dev_priv
))
2028 connector
->ycbcr_420_allowed
= true;
2030 intel_hdmi
->ddc_bus
= intel_hdmi_ddc_pin(dev_priv
, port
);
2032 if (WARN_ON(port
== PORT_A
))
2034 intel_encoder
->hpd_pin
= intel_hpd_pin(port
);
2036 if (HAS_DDI(dev_priv
))
2037 intel_connector
->get_hw_state
= intel_ddi_connector_get_hw_state
;
2039 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
2041 intel_hdmi_add_properties(intel_hdmi
, connector
);
2043 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
2044 intel_hdmi
->attached_connector
= intel_connector
;
2046 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2047 * 0xd. Failure to do so will result in spurious interrupts being
2048 * generated on the port when a cable is not attached.
2050 if (IS_G4X(dev_priv
) && !IS_GM45(dev_priv
)) {
2051 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
2052 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);
2056 void intel_hdmi_init(struct drm_i915_private
*dev_priv
,
2057 i915_reg_t hdmi_reg
, enum port port
)
2059 struct intel_digital_port
*intel_dig_port
;
2060 struct intel_encoder
*intel_encoder
;
2061 struct intel_connector
*intel_connector
;
2063 intel_dig_port
= kzalloc(sizeof(*intel_dig_port
), GFP_KERNEL
);
2064 if (!intel_dig_port
)
2067 intel_connector
= intel_connector_alloc();
2068 if (!intel_connector
) {
2069 kfree(intel_dig_port
);
2073 intel_encoder
= &intel_dig_port
->base
;
2075 drm_encoder_init(&dev_priv
->drm
, &intel_encoder
->base
,
2076 &intel_hdmi_enc_funcs
, DRM_MODE_ENCODER_TMDS
,
2077 "HDMI %c", port_name(port
));
2079 intel_encoder
->compute_config
= intel_hdmi_compute_config
;
2080 if (HAS_PCH_SPLIT(dev_priv
)) {
2081 intel_encoder
->disable
= pch_disable_hdmi
;
2082 intel_encoder
->post_disable
= pch_post_disable_hdmi
;
2084 intel_encoder
->disable
= g4x_disable_hdmi
;
2086 intel_encoder
->get_hw_state
= intel_hdmi_get_hw_state
;
2087 intel_encoder
->get_config
= intel_hdmi_get_config
;
2088 if (IS_CHERRYVIEW(dev_priv
)) {
2089 intel_encoder
->pre_pll_enable
= chv_hdmi_pre_pll_enable
;
2090 intel_encoder
->pre_enable
= chv_hdmi_pre_enable
;
2091 intel_encoder
->enable
= vlv_enable_hdmi
;
2092 intel_encoder
->post_disable
= chv_hdmi_post_disable
;
2093 intel_encoder
->post_pll_disable
= chv_hdmi_post_pll_disable
;
2094 } else if (IS_VALLEYVIEW(dev_priv
)) {
2095 intel_encoder
->pre_pll_enable
= vlv_hdmi_pre_pll_enable
;
2096 intel_encoder
->pre_enable
= vlv_hdmi_pre_enable
;
2097 intel_encoder
->enable
= vlv_enable_hdmi
;
2098 intel_encoder
->post_disable
= vlv_hdmi_post_disable
;
2100 intel_encoder
->pre_enable
= intel_hdmi_pre_enable
;
2101 if (HAS_PCH_CPT(dev_priv
))
2102 intel_encoder
->enable
= cpt_enable_hdmi
;
2103 else if (HAS_PCH_IBX(dev_priv
))
2104 intel_encoder
->enable
= ibx_enable_hdmi
;
2106 intel_encoder
->enable
= g4x_enable_hdmi
;
2109 intel_encoder
->type
= INTEL_OUTPUT_HDMI
;
2110 intel_encoder
->power_domain
= intel_port_to_power_domain(port
);
2111 intel_encoder
->port
= port
;
2112 if (IS_CHERRYVIEW(dev_priv
)) {
2114 intel_encoder
->crtc_mask
= 1 << 2;
2116 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1);
2118 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
2120 intel_encoder
->cloneable
= 1 << INTEL_OUTPUT_ANALOG
;
2122 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
2123 * to work on real hardware. And since g4x can send infoframes to
2124 * only one port anyway, nothing is lost by allowing it.
2126 if (IS_G4X(dev_priv
))
2127 intel_encoder
->cloneable
|= 1 << INTEL_OUTPUT_HDMI
;
2129 intel_dig_port
->port
= port
;
2130 intel_dig_port
->hdmi
.hdmi_reg
= hdmi_reg
;
2131 intel_dig_port
->dp
.output_reg
= INVALID_MMIO_REG
;
2132 intel_dig_port
->max_lanes
= 4;
2134 intel_infoframe_init(intel_dig_port
);
2136 intel_hdmi_init_connector(intel_dig_port
, intel_connector
);