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[thirdparty/linux.git] / drivers / gpu / drm / i915 / intel_pm.c
1 /*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28 #include <linux/cpufreq.h>
29 #include <drm/drm_plane_helper.h>
30 #include "i915_drv.h"
31 #include "intel_drv.h"
32 #include "../../../platform/x86/intel_ips.h"
33 #include <linux/module.h>
34 #include <drm/drm_atomic_helper.h>
35
36 /**
37 * DOC: RC6
38 *
39 * RC6 is a special power stage which allows the GPU to enter an very
40 * low-voltage mode when idle, using down to 0V while at this stage. This
41 * stage is entered automatically when the GPU is idle when RC6 support is
42 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
43 *
44 * There are different RC6 modes available in Intel GPU, which differentiate
45 * among each other with the latency required to enter and leave RC6 and
46 * voltage consumed by the GPU in different states.
47 *
48 * The combination of the following flags define which states GPU is allowed
49 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
50 * RC6pp is deepest RC6. Their support by hardware varies according to the
51 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
52 * which brings the most power savings; deeper states save more power, but
53 * require higher latency to switch to and wake up.
54 */
55 #define INTEL_RC6_ENABLE (1<<0)
56 #define INTEL_RC6p_ENABLE (1<<1)
57 #define INTEL_RC6pp_ENABLE (1<<2)
58
59 static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
60 {
61 /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */
62 I915_WRITE(CHICKEN_PAR1_1,
63 I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
64
65 I915_WRITE(GEN8_CONFIG0,
66 I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
67
68 /* WaEnableChickenDCPR:skl,bxt,kbl */
69 I915_WRITE(GEN8_CHICKEN_DCPR_1,
70 I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
71
72 /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */
73 /* WaFbcWakeMemOn:skl,bxt,kbl */
74 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
75 DISP_FBC_WM_DIS |
76 DISP_FBC_MEMORY_WAKE);
77
78 /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl */
79 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
80 ILK_DPFC_DISABLE_DUMMY0);
81 }
82
83 static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
84 {
85 gen9_init_clock_gating(dev_priv);
86
87 /* WaDisableSDEUnitClockGating:bxt */
88 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
89 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
90
91 /*
92 * FIXME:
93 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
94 */
95 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
96 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
97
98 /*
99 * Wa: Backlight PWM may stop in the asserted state, causing backlight
100 * to stay fully on.
101 */
102 if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
103 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
104 PWM1_GATING_DIS | PWM2_GATING_DIS);
105 }
106
107 static void i915_pineview_get_mem_freq(struct drm_i915_private *dev_priv)
108 {
109 u32 tmp;
110
111 tmp = I915_READ(CLKCFG);
112
113 switch (tmp & CLKCFG_FSB_MASK) {
114 case CLKCFG_FSB_533:
115 dev_priv->fsb_freq = 533; /* 133*4 */
116 break;
117 case CLKCFG_FSB_800:
118 dev_priv->fsb_freq = 800; /* 200*4 */
119 break;
120 case CLKCFG_FSB_667:
121 dev_priv->fsb_freq = 667; /* 167*4 */
122 break;
123 case CLKCFG_FSB_400:
124 dev_priv->fsb_freq = 400; /* 100*4 */
125 break;
126 }
127
128 switch (tmp & CLKCFG_MEM_MASK) {
129 case CLKCFG_MEM_533:
130 dev_priv->mem_freq = 533;
131 break;
132 case CLKCFG_MEM_667:
133 dev_priv->mem_freq = 667;
134 break;
135 case CLKCFG_MEM_800:
136 dev_priv->mem_freq = 800;
137 break;
138 }
139
140 /* detect pineview DDR3 setting */
141 tmp = I915_READ(CSHRDDR3CTL);
142 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
143 }
144
145 static void i915_ironlake_get_mem_freq(struct drm_i915_private *dev_priv)
146 {
147 u16 ddrpll, csipll;
148
149 ddrpll = I915_READ16(DDRMPLL1);
150 csipll = I915_READ16(CSIPLL0);
151
152 switch (ddrpll & 0xff) {
153 case 0xc:
154 dev_priv->mem_freq = 800;
155 break;
156 case 0x10:
157 dev_priv->mem_freq = 1066;
158 break;
159 case 0x14:
160 dev_priv->mem_freq = 1333;
161 break;
162 case 0x18:
163 dev_priv->mem_freq = 1600;
164 break;
165 default:
166 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
167 ddrpll & 0xff);
168 dev_priv->mem_freq = 0;
169 break;
170 }
171
172 dev_priv->ips.r_t = dev_priv->mem_freq;
173
174 switch (csipll & 0x3ff) {
175 case 0x00c:
176 dev_priv->fsb_freq = 3200;
177 break;
178 case 0x00e:
179 dev_priv->fsb_freq = 3733;
180 break;
181 case 0x010:
182 dev_priv->fsb_freq = 4266;
183 break;
184 case 0x012:
185 dev_priv->fsb_freq = 4800;
186 break;
187 case 0x014:
188 dev_priv->fsb_freq = 5333;
189 break;
190 case 0x016:
191 dev_priv->fsb_freq = 5866;
192 break;
193 case 0x018:
194 dev_priv->fsb_freq = 6400;
195 break;
196 default:
197 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
198 csipll & 0x3ff);
199 dev_priv->fsb_freq = 0;
200 break;
201 }
202
203 if (dev_priv->fsb_freq == 3200) {
204 dev_priv->ips.c_m = 0;
205 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
206 dev_priv->ips.c_m = 1;
207 } else {
208 dev_priv->ips.c_m = 2;
209 }
210 }
211
212 static const struct cxsr_latency cxsr_latency_table[] = {
213 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
214 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
215 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
216 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
217 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
218
219 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
220 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
221 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
222 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
223 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
224
225 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
226 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
227 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
228 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
229 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
230
231 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
232 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
233 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
234 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
235 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
236
237 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
238 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
239 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
240 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
241 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
242
243 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
244 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
245 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
246 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
247 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
248 };
249
250 static const struct cxsr_latency *intel_get_cxsr_latency(bool is_desktop,
251 bool is_ddr3,
252 int fsb,
253 int mem)
254 {
255 const struct cxsr_latency *latency;
256 int i;
257
258 if (fsb == 0 || mem == 0)
259 return NULL;
260
261 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
262 latency = &cxsr_latency_table[i];
263 if (is_desktop == latency->is_desktop &&
264 is_ddr3 == latency->is_ddr3 &&
265 fsb == latency->fsb_freq && mem == latency->mem_freq)
266 return latency;
267 }
268
269 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
270
271 return NULL;
272 }
273
274 static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
275 {
276 u32 val;
277
278 mutex_lock(&dev_priv->rps.hw_lock);
279
280 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
281 if (enable)
282 val &= ~FORCE_DDR_HIGH_FREQ;
283 else
284 val |= FORCE_DDR_HIGH_FREQ;
285 val &= ~FORCE_DDR_LOW_FREQ;
286 val |= FORCE_DDR_FREQ_REQ_ACK;
287 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
288
289 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
290 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
291 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
292
293 mutex_unlock(&dev_priv->rps.hw_lock);
294 }
295
296 static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
297 {
298 u32 val;
299
300 mutex_lock(&dev_priv->rps.hw_lock);
301
302 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
303 if (enable)
304 val |= DSP_MAXFIFO_PM5_ENABLE;
305 else
306 val &= ~DSP_MAXFIFO_PM5_ENABLE;
307 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
308
309 mutex_unlock(&dev_priv->rps.hw_lock);
310 }
311
312 #define FW_WM(value, plane) \
313 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
314
315 static bool _intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
316 {
317 bool was_enabled;
318 u32 val;
319
320 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
321 was_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
322 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
323 POSTING_READ(FW_BLC_SELF_VLV);
324 } else if (IS_G4X(dev_priv) || IS_I965GM(dev_priv)) {
325 was_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
326 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
327 POSTING_READ(FW_BLC_SELF);
328 } else if (IS_PINEVIEW(dev_priv)) {
329 val = I915_READ(DSPFW3);
330 was_enabled = val & PINEVIEW_SELF_REFRESH_EN;
331 if (enable)
332 val |= PINEVIEW_SELF_REFRESH_EN;
333 else
334 val &= ~PINEVIEW_SELF_REFRESH_EN;
335 I915_WRITE(DSPFW3, val);
336 POSTING_READ(DSPFW3);
337 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) {
338 was_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
339 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
340 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
341 I915_WRITE(FW_BLC_SELF, val);
342 POSTING_READ(FW_BLC_SELF);
343 } else if (IS_I915GM(dev_priv)) {
344 /*
345 * FIXME can't find a bit like this for 915G, and
346 * and yet it does have the related watermark in
347 * FW_BLC_SELF. What's going on?
348 */
349 was_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
350 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
351 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
352 I915_WRITE(INSTPM, val);
353 POSTING_READ(INSTPM);
354 } else {
355 return false;
356 }
357
358 DRM_DEBUG_KMS("memory self-refresh is %s (was %s)\n",
359 enableddisabled(enable),
360 enableddisabled(was_enabled));
361
362 return was_enabled;
363 }
364
365 bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
366 {
367 bool ret;
368
369 mutex_lock(&dev_priv->wm.wm_mutex);
370 ret = _intel_set_memory_cxsr(dev_priv, enable);
371 dev_priv->wm.vlv.cxsr = enable;
372 mutex_unlock(&dev_priv->wm.wm_mutex);
373
374 return ret;
375 }
376
377 /*
378 * Latency for FIFO fetches is dependent on several factors:
379 * - memory configuration (speed, channels)
380 * - chipset
381 * - current MCH state
382 * It can be fairly high in some situations, so here we assume a fairly
383 * pessimal value. It's a tradeoff between extra memory fetches (if we
384 * set this value too high, the FIFO will fetch frequently to stay full)
385 * and power consumption (set it too low to save power and we might see
386 * FIFO underruns and display "flicker").
387 *
388 * A value of 5us seems to be a good balance; safe for very low end
389 * platforms but not overly aggressive on lower latency configs.
390 */
391 static const int pessimal_latency_ns = 5000;
392
393 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
394 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
395
396 static int vlv_get_fifo_size(struct intel_plane *plane)
397 {
398 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
399 int sprite0_start, sprite1_start, size;
400
401 if (plane->id == PLANE_CURSOR)
402 return 63;
403
404 switch (plane->pipe) {
405 uint32_t dsparb, dsparb2, dsparb3;
406 case PIPE_A:
407 dsparb = I915_READ(DSPARB);
408 dsparb2 = I915_READ(DSPARB2);
409 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
410 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
411 break;
412 case PIPE_B:
413 dsparb = I915_READ(DSPARB);
414 dsparb2 = I915_READ(DSPARB2);
415 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
416 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
417 break;
418 case PIPE_C:
419 dsparb2 = I915_READ(DSPARB2);
420 dsparb3 = I915_READ(DSPARB3);
421 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
422 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
423 break;
424 default:
425 return 0;
426 }
427
428 switch (plane->id) {
429 case PLANE_PRIMARY:
430 size = sprite0_start;
431 break;
432 case PLANE_SPRITE0:
433 size = sprite1_start - sprite0_start;
434 break;
435 case PLANE_SPRITE1:
436 size = 512 - 1 - sprite1_start;
437 break;
438 default:
439 return 0;
440 }
441
442 DRM_DEBUG_KMS("%s FIFO size: %d\n", plane->base.name, size);
443
444 return size;
445 }
446
447 static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
448 {
449 uint32_t dsparb = I915_READ(DSPARB);
450 int size;
451
452 size = dsparb & 0x7f;
453 if (plane)
454 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
455
456 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
457 plane ? "B" : "A", size);
458
459 return size;
460 }
461
462 static int i830_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
463 {
464 uint32_t dsparb = I915_READ(DSPARB);
465 int size;
466
467 size = dsparb & 0x1ff;
468 if (plane)
469 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
470 size >>= 1; /* Convert to cachelines */
471
472 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
473 plane ? "B" : "A", size);
474
475 return size;
476 }
477
478 static int i845_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
479 {
480 uint32_t dsparb = I915_READ(DSPARB);
481 int size;
482
483 size = dsparb & 0x7f;
484 size >>= 2; /* Convert to cachelines */
485
486 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
487 plane ? "B" : "A",
488 size);
489
490 return size;
491 }
492
493 /* Pineview has different values for various configs */
494 static const struct intel_watermark_params pineview_display_wm = {
495 .fifo_size = PINEVIEW_DISPLAY_FIFO,
496 .max_wm = PINEVIEW_MAX_WM,
497 .default_wm = PINEVIEW_DFT_WM,
498 .guard_size = PINEVIEW_GUARD_WM,
499 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
500 };
501 static const struct intel_watermark_params pineview_display_hplloff_wm = {
502 .fifo_size = PINEVIEW_DISPLAY_FIFO,
503 .max_wm = PINEVIEW_MAX_WM,
504 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
505 .guard_size = PINEVIEW_GUARD_WM,
506 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
507 };
508 static const struct intel_watermark_params pineview_cursor_wm = {
509 .fifo_size = PINEVIEW_CURSOR_FIFO,
510 .max_wm = PINEVIEW_CURSOR_MAX_WM,
511 .default_wm = PINEVIEW_CURSOR_DFT_WM,
512 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
513 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
514 };
515 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
516 .fifo_size = PINEVIEW_CURSOR_FIFO,
517 .max_wm = PINEVIEW_CURSOR_MAX_WM,
518 .default_wm = PINEVIEW_CURSOR_DFT_WM,
519 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
520 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
521 };
522 static const struct intel_watermark_params g4x_wm_info = {
523 .fifo_size = G4X_FIFO_SIZE,
524 .max_wm = G4X_MAX_WM,
525 .default_wm = G4X_MAX_WM,
526 .guard_size = 2,
527 .cacheline_size = G4X_FIFO_LINE_SIZE,
528 };
529 static const struct intel_watermark_params g4x_cursor_wm_info = {
530 .fifo_size = I965_CURSOR_FIFO,
531 .max_wm = I965_CURSOR_MAX_WM,
532 .default_wm = I965_CURSOR_DFT_WM,
533 .guard_size = 2,
534 .cacheline_size = G4X_FIFO_LINE_SIZE,
535 };
536 static const struct intel_watermark_params i965_cursor_wm_info = {
537 .fifo_size = I965_CURSOR_FIFO,
538 .max_wm = I965_CURSOR_MAX_WM,
539 .default_wm = I965_CURSOR_DFT_WM,
540 .guard_size = 2,
541 .cacheline_size = I915_FIFO_LINE_SIZE,
542 };
543 static const struct intel_watermark_params i945_wm_info = {
544 .fifo_size = I945_FIFO_SIZE,
545 .max_wm = I915_MAX_WM,
546 .default_wm = 1,
547 .guard_size = 2,
548 .cacheline_size = I915_FIFO_LINE_SIZE,
549 };
550 static const struct intel_watermark_params i915_wm_info = {
551 .fifo_size = I915_FIFO_SIZE,
552 .max_wm = I915_MAX_WM,
553 .default_wm = 1,
554 .guard_size = 2,
555 .cacheline_size = I915_FIFO_LINE_SIZE,
556 };
557 static const struct intel_watermark_params i830_a_wm_info = {
558 .fifo_size = I855GM_FIFO_SIZE,
559 .max_wm = I915_MAX_WM,
560 .default_wm = 1,
561 .guard_size = 2,
562 .cacheline_size = I830_FIFO_LINE_SIZE,
563 };
564 static const struct intel_watermark_params i830_bc_wm_info = {
565 .fifo_size = I855GM_FIFO_SIZE,
566 .max_wm = I915_MAX_WM/2,
567 .default_wm = 1,
568 .guard_size = 2,
569 .cacheline_size = I830_FIFO_LINE_SIZE,
570 };
571 static const struct intel_watermark_params i845_wm_info = {
572 .fifo_size = I830_FIFO_SIZE,
573 .max_wm = I915_MAX_WM,
574 .default_wm = 1,
575 .guard_size = 2,
576 .cacheline_size = I830_FIFO_LINE_SIZE,
577 };
578
579 /**
580 * intel_calculate_wm - calculate watermark level
581 * @clock_in_khz: pixel clock
582 * @wm: chip FIFO params
583 * @cpp: bytes per pixel
584 * @latency_ns: memory latency for the platform
585 *
586 * Calculate the watermark level (the level at which the display plane will
587 * start fetching from memory again). Each chip has a different display
588 * FIFO size and allocation, so the caller needs to figure that out and pass
589 * in the correct intel_watermark_params structure.
590 *
591 * As the pixel clock runs, the FIFO will be drained at a rate that depends
592 * on the pixel size. When it reaches the watermark level, it'll start
593 * fetching FIFO line sized based chunks from memory until the FIFO fills
594 * past the watermark point. If the FIFO drains completely, a FIFO underrun
595 * will occur, and a display engine hang could result.
596 */
597 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
598 const struct intel_watermark_params *wm,
599 int fifo_size, int cpp,
600 unsigned long latency_ns)
601 {
602 long entries_required, wm_size;
603
604 /*
605 * Note: we need to make sure we don't overflow for various clock &
606 * latency values.
607 * clocks go from a few thousand to several hundred thousand.
608 * latency is usually a few thousand
609 */
610 entries_required = ((clock_in_khz / 1000) * cpp * latency_ns) /
611 1000;
612 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
613
614 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
615
616 wm_size = fifo_size - (entries_required + wm->guard_size);
617
618 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
619
620 /* Don't promote wm_size to unsigned... */
621 if (wm_size > (long)wm->max_wm)
622 wm_size = wm->max_wm;
623 if (wm_size <= 0)
624 wm_size = wm->default_wm;
625
626 /*
627 * Bspec seems to indicate that the value shouldn't be lower than
628 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
629 * Lets go for 8 which is the burst size since certain platforms
630 * already use a hardcoded 8 (which is what the spec says should be
631 * done).
632 */
633 if (wm_size <= 8)
634 wm_size = 8;
635
636 return wm_size;
637 }
638
639 static struct intel_crtc *single_enabled_crtc(struct drm_i915_private *dev_priv)
640 {
641 struct intel_crtc *crtc, *enabled = NULL;
642
643 for_each_intel_crtc(&dev_priv->drm, crtc) {
644 if (intel_crtc_active(crtc)) {
645 if (enabled)
646 return NULL;
647 enabled = crtc;
648 }
649 }
650
651 return enabled;
652 }
653
654 static void pineview_update_wm(struct intel_crtc *unused_crtc)
655 {
656 struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
657 struct intel_crtc *crtc;
658 const struct cxsr_latency *latency;
659 u32 reg;
660 unsigned long wm;
661
662 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
663 dev_priv->is_ddr3,
664 dev_priv->fsb_freq,
665 dev_priv->mem_freq);
666 if (!latency) {
667 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
668 intel_set_memory_cxsr(dev_priv, false);
669 return;
670 }
671
672 crtc = single_enabled_crtc(dev_priv);
673 if (crtc) {
674 const struct drm_display_mode *adjusted_mode =
675 &crtc->config->base.adjusted_mode;
676 const struct drm_framebuffer *fb =
677 crtc->base.primary->state->fb;
678 int cpp = fb->format->cpp[0];
679 int clock = adjusted_mode->crtc_clock;
680
681 /* Display SR */
682 wm = intel_calculate_wm(clock, &pineview_display_wm,
683 pineview_display_wm.fifo_size,
684 cpp, latency->display_sr);
685 reg = I915_READ(DSPFW1);
686 reg &= ~DSPFW_SR_MASK;
687 reg |= FW_WM(wm, SR);
688 I915_WRITE(DSPFW1, reg);
689 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
690
691 /* cursor SR */
692 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
693 pineview_display_wm.fifo_size,
694 cpp, latency->cursor_sr);
695 reg = I915_READ(DSPFW3);
696 reg &= ~DSPFW_CURSOR_SR_MASK;
697 reg |= FW_WM(wm, CURSOR_SR);
698 I915_WRITE(DSPFW3, reg);
699
700 /* Display HPLL off SR */
701 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
702 pineview_display_hplloff_wm.fifo_size,
703 cpp, latency->display_hpll_disable);
704 reg = I915_READ(DSPFW3);
705 reg &= ~DSPFW_HPLL_SR_MASK;
706 reg |= FW_WM(wm, HPLL_SR);
707 I915_WRITE(DSPFW3, reg);
708
709 /* cursor HPLL off SR */
710 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
711 pineview_display_hplloff_wm.fifo_size,
712 cpp, latency->cursor_hpll_disable);
713 reg = I915_READ(DSPFW3);
714 reg &= ~DSPFW_HPLL_CURSOR_MASK;
715 reg |= FW_WM(wm, HPLL_CURSOR);
716 I915_WRITE(DSPFW3, reg);
717 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
718
719 intel_set_memory_cxsr(dev_priv, true);
720 } else {
721 intel_set_memory_cxsr(dev_priv, false);
722 }
723 }
724
725 static bool g4x_compute_wm0(struct drm_i915_private *dev_priv,
726 int plane,
727 const struct intel_watermark_params *display,
728 int display_latency_ns,
729 const struct intel_watermark_params *cursor,
730 int cursor_latency_ns,
731 int *plane_wm,
732 int *cursor_wm)
733 {
734 struct intel_crtc *crtc;
735 const struct drm_display_mode *adjusted_mode;
736 const struct drm_framebuffer *fb;
737 int htotal, hdisplay, clock, cpp;
738 int line_time_us, line_count;
739 int entries, tlb_miss;
740
741 crtc = intel_get_crtc_for_plane(dev_priv, plane);
742 if (!intel_crtc_active(crtc)) {
743 *cursor_wm = cursor->guard_size;
744 *plane_wm = display->guard_size;
745 return false;
746 }
747
748 adjusted_mode = &crtc->config->base.adjusted_mode;
749 fb = crtc->base.primary->state->fb;
750 clock = adjusted_mode->crtc_clock;
751 htotal = adjusted_mode->crtc_htotal;
752 hdisplay = crtc->config->pipe_src_w;
753 cpp = fb->format->cpp[0];
754
755 /* Use the small buffer method to calculate plane watermark */
756 entries = ((clock * cpp / 1000) * display_latency_ns) / 1000;
757 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
758 if (tlb_miss > 0)
759 entries += tlb_miss;
760 entries = DIV_ROUND_UP(entries, display->cacheline_size);
761 *plane_wm = entries + display->guard_size;
762 if (*plane_wm > (int)display->max_wm)
763 *plane_wm = display->max_wm;
764
765 /* Use the large buffer method to calculate cursor watermark */
766 line_time_us = max(htotal * 1000 / clock, 1);
767 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
768 entries = line_count * crtc->base.cursor->state->crtc_w * cpp;
769 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
770 if (tlb_miss > 0)
771 entries += tlb_miss;
772 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
773 *cursor_wm = entries + cursor->guard_size;
774 if (*cursor_wm > (int)cursor->max_wm)
775 *cursor_wm = (int)cursor->max_wm;
776
777 return true;
778 }
779
780 /*
781 * Check the wm result.
782 *
783 * If any calculated watermark values is larger than the maximum value that
784 * can be programmed into the associated watermark register, that watermark
785 * must be disabled.
786 */
787 static bool g4x_check_srwm(struct drm_i915_private *dev_priv,
788 int display_wm, int cursor_wm,
789 const struct intel_watermark_params *display,
790 const struct intel_watermark_params *cursor)
791 {
792 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
793 display_wm, cursor_wm);
794
795 if (display_wm > display->max_wm) {
796 DRM_DEBUG_KMS("display watermark is too large(%d/%u), disabling\n",
797 display_wm, display->max_wm);
798 return false;
799 }
800
801 if (cursor_wm > cursor->max_wm) {
802 DRM_DEBUG_KMS("cursor watermark is too large(%d/%u), disabling\n",
803 cursor_wm, cursor->max_wm);
804 return false;
805 }
806
807 if (!(display_wm || cursor_wm)) {
808 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
809 return false;
810 }
811
812 return true;
813 }
814
815 static bool g4x_compute_srwm(struct drm_i915_private *dev_priv,
816 int plane,
817 int latency_ns,
818 const struct intel_watermark_params *display,
819 const struct intel_watermark_params *cursor,
820 int *display_wm, int *cursor_wm)
821 {
822 struct intel_crtc *crtc;
823 const struct drm_display_mode *adjusted_mode;
824 const struct drm_framebuffer *fb;
825 int hdisplay, htotal, cpp, clock;
826 unsigned long line_time_us;
827 int line_count, line_size;
828 int small, large;
829 int entries;
830
831 if (!latency_ns) {
832 *display_wm = *cursor_wm = 0;
833 return false;
834 }
835
836 crtc = intel_get_crtc_for_plane(dev_priv, plane);
837 adjusted_mode = &crtc->config->base.adjusted_mode;
838 fb = crtc->base.primary->state->fb;
839 clock = adjusted_mode->crtc_clock;
840 htotal = adjusted_mode->crtc_htotal;
841 hdisplay = crtc->config->pipe_src_w;
842 cpp = fb->format->cpp[0];
843
844 line_time_us = max(htotal * 1000 / clock, 1);
845 line_count = (latency_ns / line_time_us + 1000) / 1000;
846 line_size = hdisplay * cpp;
847
848 /* Use the minimum of the small and large buffer method for primary */
849 small = ((clock * cpp / 1000) * latency_ns) / 1000;
850 large = line_count * line_size;
851
852 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
853 *display_wm = entries + display->guard_size;
854
855 /* calculate the self-refresh watermark for display cursor */
856 entries = line_count * cpp * crtc->base.cursor->state->crtc_w;
857 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
858 *cursor_wm = entries + cursor->guard_size;
859
860 return g4x_check_srwm(dev_priv,
861 *display_wm, *cursor_wm,
862 display, cursor);
863 }
864
865 #define FW_WM_VLV(value, plane) \
866 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
867
868 static void vlv_write_wm_values(struct drm_i915_private *dev_priv,
869 const struct vlv_wm_values *wm)
870 {
871 enum pipe pipe;
872
873 for_each_pipe(dev_priv, pipe) {
874 I915_WRITE(VLV_DDL(pipe),
875 (wm->ddl[pipe].plane[PLANE_CURSOR] << DDL_CURSOR_SHIFT) |
876 (wm->ddl[pipe].plane[PLANE_SPRITE1] << DDL_SPRITE_SHIFT(1)) |
877 (wm->ddl[pipe].plane[PLANE_SPRITE0] << DDL_SPRITE_SHIFT(0)) |
878 (wm->ddl[pipe].plane[PLANE_PRIMARY] << DDL_PLANE_SHIFT));
879 }
880
881 /*
882 * Zero the (unused) WM1 watermarks, and also clear all the
883 * high order bits so that there are no out of bounds values
884 * present in the registers during the reprogramming.
885 */
886 I915_WRITE(DSPHOWM, 0);
887 I915_WRITE(DSPHOWM1, 0);
888 I915_WRITE(DSPFW4, 0);
889 I915_WRITE(DSPFW5, 0);
890 I915_WRITE(DSPFW6, 0);
891
892 I915_WRITE(DSPFW1,
893 FW_WM(wm->sr.plane, SR) |
894 FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) |
895 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) |
896 FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA));
897 I915_WRITE(DSPFW2,
898 FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE1], SPRITEB) |
899 FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) |
900 FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA));
901 I915_WRITE(DSPFW3,
902 FW_WM(wm->sr.cursor, CURSOR_SR));
903
904 if (IS_CHERRYVIEW(dev_priv)) {
905 I915_WRITE(DSPFW7_CHV,
906 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) |
907 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC));
908 I915_WRITE(DSPFW8_CHV,
909 FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE1], SPRITEF) |
910 FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE0], SPRITEE));
911 I915_WRITE(DSPFW9_CHV,
912 FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_PRIMARY], PLANEC) |
913 FW_WM(wm->pipe[PIPE_C].plane[PLANE_CURSOR], CURSORC));
914 I915_WRITE(DSPHOWM,
915 FW_WM(wm->sr.plane >> 9, SR_HI) |
916 FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE1] >> 8, SPRITEF_HI) |
917 FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE0] >> 8, SPRITEE_HI) |
918 FW_WM(wm->pipe[PIPE_C].plane[PLANE_PRIMARY] >> 8, PLANEC_HI) |
919 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) |
920 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) |
921 FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) |
922 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) |
923 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) |
924 FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI));
925 } else {
926 I915_WRITE(DSPFW7,
927 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) |
928 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC));
929 I915_WRITE(DSPHOWM,
930 FW_WM(wm->sr.plane >> 9, SR_HI) |
931 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) |
932 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) |
933 FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) |
934 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) |
935 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) |
936 FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI));
937 }
938
939 POSTING_READ(DSPFW1);
940 }
941
942 #undef FW_WM_VLV
943
944 enum vlv_wm_level {
945 VLV_WM_LEVEL_PM2,
946 VLV_WM_LEVEL_PM5,
947 VLV_WM_LEVEL_DDR_DVFS,
948 };
949
950 /* latency must be in 0.1us units. */
951 static unsigned int vlv_wm_method2(unsigned int pixel_rate,
952 unsigned int pipe_htotal,
953 unsigned int horiz_pixels,
954 unsigned int cpp,
955 unsigned int latency)
956 {
957 unsigned int ret;
958
959 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
960 ret = (ret + 1) * horiz_pixels * cpp;
961 ret = DIV_ROUND_UP(ret, 64);
962
963 return ret;
964 }
965
966 static void vlv_setup_wm_latency(struct drm_i915_private *dev_priv)
967 {
968 /* all latencies in usec */
969 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
970
971 dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
972
973 if (IS_CHERRYVIEW(dev_priv)) {
974 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
975 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
976
977 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
978 }
979 }
980
981 static uint16_t vlv_compute_wm_level(const struct intel_crtc_state *crtc_state,
982 const struct intel_plane_state *plane_state,
983 int level)
984 {
985 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
986 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
987 const struct drm_display_mode *adjusted_mode =
988 &crtc_state->base.adjusted_mode;
989 int clock, htotal, cpp, width, wm;
990
991 if (dev_priv->wm.pri_latency[level] == 0)
992 return USHRT_MAX;
993
994 if (!plane_state->base.visible)
995 return 0;
996
997 cpp = plane_state->base.fb->format->cpp[0];
998 clock = adjusted_mode->crtc_clock;
999 htotal = adjusted_mode->crtc_htotal;
1000 width = crtc_state->pipe_src_w;
1001 if (WARN_ON(htotal == 0))
1002 htotal = 1;
1003
1004 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1005 /*
1006 * FIXME the formula gives values that are
1007 * too big for the cursor FIFO, and hence we
1008 * would never be able to use cursors. For
1009 * now just hardcode the watermark.
1010 */
1011 wm = 63;
1012 } else {
1013 wm = vlv_wm_method2(clock, htotal, width, cpp,
1014 dev_priv->wm.pri_latency[level] * 10);
1015 }
1016
1017 return min_t(int, wm, USHRT_MAX);
1018 }
1019
1020 static void vlv_compute_fifo(struct intel_crtc *crtc)
1021 {
1022 struct drm_device *dev = crtc->base.dev;
1023 struct vlv_wm_state *wm_state = &crtc->wm_state;
1024 struct intel_plane *plane;
1025 unsigned int total_rate = 0;
1026 const int fifo_size = 512 - 1;
1027 int fifo_extra, fifo_left = fifo_size;
1028
1029 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1030 struct intel_plane_state *state =
1031 to_intel_plane_state(plane->base.state);
1032
1033 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1034 continue;
1035
1036 if (state->base.visible) {
1037 wm_state->num_active_planes++;
1038 total_rate += state->base.fb->format->cpp[0];
1039 }
1040 }
1041
1042 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1043 struct intel_plane_state *state =
1044 to_intel_plane_state(plane->base.state);
1045 unsigned int rate;
1046
1047 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1048 plane->wm.fifo_size = 63;
1049 continue;
1050 }
1051
1052 if (!state->base.visible) {
1053 plane->wm.fifo_size = 0;
1054 continue;
1055 }
1056
1057 rate = state->base.fb->format->cpp[0];
1058 plane->wm.fifo_size = fifo_size * rate / total_rate;
1059 fifo_left -= plane->wm.fifo_size;
1060 }
1061
1062 fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1063
1064 /* spread the remainder evenly */
1065 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1066 int plane_extra;
1067
1068 if (fifo_left == 0)
1069 break;
1070
1071 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1072 continue;
1073
1074 /* give it all to the first plane if none are active */
1075 if (plane->wm.fifo_size == 0 &&
1076 wm_state->num_active_planes)
1077 continue;
1078
1079 plane_extra = min(fifo_extra, fifo_left);
1080 plane->wm.fifo_size += plane_extra;
1081 fifo_left -= plane_extra;
1082 }
1083
1084 WARN_ON(fifo_left != 0);
1085 }
1086
1087 static u16 vlv_invert_wm_value(u16 wm, u16 fifo_size)
1088 {
1089 if (wm > fifo_size)
1090 return USHRT_MAX;
1091 else
1092 return fifo_size - wm;
1093 }
1094
1095 static void vlv_invert_wms(struct intel_crtc *crtc)
1096 {
1097 struct vlv_wm_state *wm_state = &crtc->wm_state;
1098 int level;
1099
1100 for (level = 0; level < wm_state->num_levels; level++) {
1101 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1102 const int sr_fifo_size =
1103 INTEL_INFO(dev_priv)->num_pipes * 512 - 1;
1104 struct intel_plane *plane;
1105
1106 wm_state->sr[level].plane =
1107 vlv_invert_wm_value(wm_state->sr[level].plane,
1108 sr_fifo_size);
1109 wm_state->sr[level].cursor =
1110 vlv_invert_wm_value(wm_state->sr[level].cursor,
1111 63);
1112
1113 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
1114 wm_state->wm[level].plane[plane->id] =
1115 vlv_invert_wm_value(wm_state->wm[level].plane[plane->id],
1116 plane->wm.fifo_size);
1117 }
1118 }
1119 }
1120
1121 static void vlv_compute_wm(struct intel_crtc *crtc)
1122 {
1123 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1124 struct vlv_wm_state *wm_state = &crtc->wm_state;
1125 struct intel_plane *plane;
1126 int level;
1127
1128 memset(wm_state, 0, sizeof(*wm_state));
1129
1130 wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
1131 wm_state->num_levels = dev_priv->wm.max_level + 1;
1132
1133 wm_state->num_active_planes = 0;
1134
1135 vlv_compute_fifo(crtc);
1136
1137 if (wm_state->num_active_planes != 1)
1138 wm_state->cxsr = false;
1139
1140 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
1141 struct intel_plane_state *state =
1142 to_intel_plane_state(plane->base.state);
1143 int level;
1144
1145 if (!state->base.visible)
1146 continue;
1147
1148 /* normal watermarks */
1149 for (level = 0; level < wm_state->num_levels; level++) {
1150 int wm = vlv_compute_wm_level(crtc->config, state, level);
1151 int max_wm = plane->wm.fifo_size;
1152
1153 /* hack */
1154 if (WARN_ON(level == 0 && wm > max_wm))
1155 wm = max_wm;
1156
1157 if (wm > max_wm)
1158 break;
1159
1160 wm_state->wm[level].plane[plane->id] = wm;
1161 }
1162
1163 wm_state->num_levels = level;
1164
1165 if (!wm_state->cxsr)
1166 continue;
1167
1168 /* maxfifo watermarks */
1169 if (plane->id == PLANE_CURSOR) {
1170 for (level = 0; level < wm_state->num_levels; level++)
1171 wm_state->sr[level].cursor =
1172 wm_state->wm[level].plane[PLANE_CURSOR];
1173 } else {
1174 for (level = 0; level < wm_state->num_levels; level++)
1175 wm_state->sr[level].plane =
1176 max(wm_state->sr[level].plane,
1177 wm_state->wm[level].plane[plane->id]);
1178 }
1179 }
1180
1181 /* clear any (partially) filled invalid levels */
1182 for (level = wm_state->num_levels; level < dev_priv->wm.max_level + 1; level++) {
1183 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1184 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1185 }
1186
1187 vlv_invert_wms(crtc);
1188 }
1189
1190 #define VLV_FIFO(plane, value) \
1191 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1192
1193 static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1194 {
1195 struct drm_device *dev = crtc->base.dev;
1196 struct drm_i915_private *dev_priv = to_i915(dev);
1197 struct intel_plane *plane;
1198 int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1199
1200 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1201 switch (plane->id) {
1202 case PLANE_PRIMARY:
1203 sprite0_start = plane->wm.fifo_size;
1204 break;
1205 case PLANE_SPRITE0:
1206 sprite1_start = sprite0_start + plane->wm.fifo_size;
1207 break;
1208 case PLANE_SPRITE1:
1209 fifo_size = sprite1_start + plane->wm.fifo_size;
1210 break;
1211 case PLANE_CURSOR:
1212 WARN_ON(plane->wm.fifo_size != 63);
1213 break;
1214 default:
1215 MISSING_CASE(plane->id);
1216 break;
1217 }
1218 }
1219
1220 WARN_ON(fifo_size != 512 - 1);
1221
1222 DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1223 pipe_name(crtc->pipe), sprite0_start,
1224 sprite1_start, fifo_size);
1225
1226 spin_lock(&dev_priv->wm.dsparb_lock);
1227
1228 switch (crtc->pipe) {
1229 uint32_t dsparb, dsparb2, dsparb3;
1230 case PIPE_A:
1231 dsparb = I915_READ(DSPARB);
1232 dsparb2 = I915_READ(DSPARB2);
1233
1234 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1235 VLV_FIFO(SPRITEB, 0xff));
1236 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1237 VLV_FIFO(SPRITEB, sprite1_start));
1238
1239 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1240 VLV_FIFO(SPRITEB_HI, 0x1));
1241 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1242 VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1243
1244 I915_WRITE(DSPARB, dsparb);
1245 I915_WRITE(DSPARB2, dsparb2);
1246 break;
1247 case PIPE_B:
1248 dsparb = I915_READ(DSPARB);
1249 dsparb2 = I915_READ(DSPARB2);
1250
1251 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1252 VLV_FIFO(SPRITED, 0xff));
1253 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1254 VLV_FIFO(SPRITED, sprite1_start));
1255
1256 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1257 VLV_FIFO(SPRITED_HI, 0xff));
1258 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1259 VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1260
1261 I915_WRITE(DSPARB, dsparb);
1262 I915_WRITE(DSPARB2, dsparb2);
1263 break;
1264 case PIPE_C:
1265 dsparb3 = I915_READ(DSPARB3);
1266 dsparb2 = I915_READ(DSPARB2);
1267
1268 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1269 VLV_FIFO(SPRITEF, 0xff));
1270 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1271 VLV_FIFO(SPRITEF, sprite1_start));
1272
1273 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1274 VLV_FIFO(SPRITEF_HI, 0xff));
1275 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1276 VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1277
1278 I915_WRITE(DSPARB3, dsparb3);
1279 I915_WRITE(DSPARB2, dsparb2);
1280 break;
1281 default:
1282 break;
1283 }
1284
1285 POSTING_READ(DSPARB);
1286
1287 spin_unlock(&dev_priv->wm.dsparb_lock);
1288 }
1289
1290 #undef VLV_FIFO
1291
1292 static void vlv_merge_wm(struct drm_i915_private *dev_priv,
1293 struct vlv_wm_values *wm)
1294 {
1295 struct intel_crtc *crtc;
1296 int num_active_crtcs = 0;
1297
1298 wm->level = dev_priv->wm.max_level;
1299 wm->cxsr = true;
1300
1301 for_each_intel_crtc(&dev_priv->drm, crtc) {
1302 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1303
1304 if (!crtc->active)
1305 continue;
1306
1307 if (!wm_state->cxsr)
1308 wm->cxsr = false;
1309
1310 num_active_crtcs++;
1311 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1312 }
1313
1314 if (num_active_crtcs != 1)
1315 wm->cxsr = false;
1316
1317 if (num_active_crtcs > 1)
1318 wm->level = VLV_WM_LEVEL_PM2;
1319
1320 for_each_intel_crtc(&dev_priv->drm, crtc) {
1321 struct vlv_wm_state *wm_state = &crtc->wm_state;
1322 enum pipe pipe = crtc->pipe;
1323
1324 if (!crtc->active)
1325 continue;
1326
1327 wm->pipe[pipe] = wm_state->wm[wm->level];
1328 if (wm->cxsr)
1329 wm->sr = wm_state->sr[wm->level];
1330
1331 wm->ddl[pipe].plane[PLANE_PRIMARY] = DDL_PRECISION_HIGH | 2;
1332 wm->ddl[pipe].plane[PLANE_SPRITE0] = DDL_PRECISION_HIGH | 2;
1333 wm->ddl[pipe].plane[PLANE_SPRITE1] = DDL_PRECISION_HIGH | 2;
1334 wm->ddl[pipe].plane[PLANE_CURSOR] = DDL_PRECISION_HIGH | 2;
1335 }
1336 }
1337
1338 static bool is_disabling(int old, int new, int threshold)
1339 {
1340 return old >= threshold && new < threshold;
1341 }
1342
1343 static bool is_enabling(int old, int new, int threshold)
1344 {
1345 return old < threshold && new >= threshold;
1346 }
1347
1348 static void vlv_update_wm(struct intel_crtc *crtc)
1349 {
1350 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1351 enum pipe pipe = crtc->pipe;
1352 struct vlv_wm_values *old_wm = &dev_priv->wm.vlv;
1353 struct vlv_wm_values new_wm = {};
1354
1355 vlv_compute_wm(crtc);
1356 vlv_merge_wm(dev_priv, &new_wm);
1357
1358 if (memcmp(old_wm, &new_wm, sizeof(new_wm)) == 0) {
1359 /* FIXME should be part of crtc atomic commit */
1360 vlv_pipe_set_fifo_size(crtc);
1361
1362 return;
1363 }
1364
1365 if (is_disabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_DDR_DVFS))
1366 chv_set_memory_dvfs(dev_priv, false);
1367
1368 if (is_disabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_PM5))
1369 chv_set_memory_pm5(dev_priv, false);
1370
1371 if (is_disabling(old_wm->cxsr, new_wm.cxsr, true))
1372 _intel_set_memory_cxsr(dev_priv, false);
1373
1374 /* FIXME should be part of crtc atomic commit */
1375 vlv_pipe_set_fifo_size(crtc);
1376
1377 vlv_write_wm_values(dev_priv, &new_wm);
1378
1379 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1380 "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1381 pipe_name(pipe), new_wm.pipe[pipe].plane[PLANE_PRIMARY], new_wm.pipe[pipe].plane[PLANE_CURSOR],
1382 new_wm.pipe[pipe].plane[PLANE_SPRITE0], new_wm.pipe[pipe].plane[PLANE_SPRITE1],
1383 new_wm.sr.plane, new_wm.sr.cursor, new_wm.level, new_wm.cxsr);
1384
1385 if (is_enabling(old_wm->cxsr, new_wm.cxsr, true))
1386 _intel_set_memory_cxsr(dev_priv, true);
1387
1388 if (is_enabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_PM5))
1389 chv_set_memory_pm5(dev_priv, true);
1390
1391 if (is_enabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_DDR_DVFS))
1392 chv_set_memory_dvfs(dev_priv, true);
1393
1394 *old_wm = new_wm;
1395 }
1396
1397 #define single_plane_enabled(mask) is_power_of_2(mask)
1398
1399 static void g4x_update_wm(struct intel_crtc *crtc)
1400 {
1401 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1402 static const int sr_latency_ns = 12000;
1403 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1404 int plane_sr, cursor_sr;
1405 unsigned int enabled = 0;
1406 bool cxsr_enabled;
1407
1408 if (g4x_compute_wm0(dev_priv, PIPE_A,
1409 &g4x_wm_info, pessimal_latency_ns,
1410 &g4x_cursor_wm_info, pessimal_latency_ns,
1411 &planea_wm, &cursora_wm))
1412 enabled |= 1 << PIPE_A;
1413
1414 if (g4x_compute_wm0(dev_priv, PIPE_B,
1415 &g4x_wm_info, pessimal_latency_ns,
1416 &g4x_cursor_wm_info, pessimal_latency_ns,
1417 &planeb_wm, &cursorb_wm))
1418 enabled |= 1 << PIPE_B;
1419
1420 if (single_plane_enabled(enabled) &&
1421 g4x_compute_srwm(dev_priv, ffs(enabled) - 1,
1422 sr_latency_ns,
1423 &g4x_wm_info,
1424 &g4x_cursor_wm_info,
1425 &plane_sr, &cursor_sr)) {
1426 cxsr_enabled = true;
1427 } else {
1428 cxsr_enabled = false;
1429 intel_set_memory_cxsr(dev_priv, false);
1430 plane_sr = cursor_sr = 0;
1431 }
1432
1433 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1434 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1435 planea_wm, cursora_wm,
1436 planeb_wm, cursorb_wm,
1437 plane_sr, cursor_sr);
1438
1439 I915_WRITE(DSPFW1,
1440 FW_WM(plane_sr, SR) |
1441 FW_WM(cursorb_wm, CURSORB) |
1442 FW_WM(planeb_wm, PLANEB) |
1443 FW_WM(planea_wm, PLANEA));
1444 I915_WRITE(DSPFW2,
1445 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1446 FW_WM(cursora_wm, CURSORA));
1447 /* HPLL off in SR has some issues on G4x... disable it */
1448 I915_WRITE(DSPFW3,
1449 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1450 FW_WM(cursor_sr, CURSOR_SR));
1451
1452 if (cxsr_enabled)
1453 intel_set_memory_cxsr(dev_priv, true);
1454 }
1455
1456 static void i965_update_wm(struct intel_crtc *unused_crtc)
1457 {
1458 struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
1459 struct intel_crtc *crtc;
1460 int srwm = 1;
1461 int cursor_sr = 16;
1462 bool cxsr_enabled;
1463
1464 /* Calc sr entries for one plane configs */
1465 crtc = single_enabled_crtc(dev_priv);
1466 if (crtc) {
1467 /* self-refresh has much higher latency */
1468 static const int sr_latency_ns = 12000;
1469 const struct drm_display_mode *adjusted_mode =
1470 &crtc->config->base.adjusted_mode;
1471 const struct drm_framebuffer *fb =
1472 crtc->base.primary->state->fb;
1473 int clock = adjusted_mode->crtc_clock;
1474 int htotal = adjusted_mode->crtc_htotal;
1475 int hdisplay = crtc->config->pipe_src_w;
1476 int cpp = fb->format->cpp[0];
1477 unsigned long line_time_us;
1478 int entries;
1479
1480 line_time_us = max(htotal * 1000 / clock, 1);
1481
1482 /* Use ns/us then divide to preserve precision */
1483 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1484 cpp * hdisplay;
1485 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1486 srwm = I965_FIFO_SIZE - entries;
1487 if (srwm < 0)
1488 srwm = 1;
1489 srwm &= 0x1ff;
1490 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1491 entries, srwm);
1492
1493 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1494 cpp * crtc->base.cursor->state->crtc_w;
1495 entries = DIV_ROUND_UP(entries,
1496 i965_cursor_wm_info.cacheline_size);
1497 cursor_sr = i965_cursor_wm_info.fifo_size -
1498 (entries + i965_cursor_wm_info.guard_size);
1499
1500 if (cursor_sr > i965_cursor_wm_info.max_wm)
1501 cursor_sr = i965_cursor_wm_info.max_wm;
1502
1503 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1504 "cursor %d\n", srwm, cursor_sr);
1505
1506 cxsr_enabled = true;
1507 } else {
1508 cxsr_enabled = false;
1509 /* Turn off self refresh if both pipes are enabled */
1510 intel_set_memory_cxsr(dev_priv, false);
1511 }
1512
1513 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1514 srwm);
1515
1516 /* 965 has limitations... */
1517 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1518 FW_WM(8, CURSORB) |
1519 FW_WM(8, PLANEB) |
1520 FW_WM(8, PLANEA));
1521 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1522 FW_WM(8, PLANEC_OLD));
1523 /* update cursor SR watermark */
1524 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
1525
1526 if (cxsr_enabled)
1527 intel_set_memory_cxsr(dev_priv, true);
1528 }
1529
1530 #undef FW_WM
1531
1532 static void i9xx_update_wm(struct intel_crtc *unused_crtc)
1533 {
1534 struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
1535 const struct intel_watermark_params *wm_info;
1536 uint32_t fwater_lo;
1537 uint32_t fwater_hi;
1538 int cwm, srwm = 1;
1539 int fifo_size;
1540 int planea_wm, planeb_wm;
1541 struct intel_crtc *crtc, *enabled = NULL;
1542
1543 if (IS_I945GM(dev_priv))
1544 wm_info = &i945_wm_info;
1545 else if (!IS_GEN2(dev_priv))
1546 wm_info = &i915_wm_info;
1547 else
1548 wm_info = &i830_a_wm_info;
1549
1550 fifo_size = dev_priv->display.get_fifo_size(dev_priv, 0);
1551 crtc = intel_get_crtc_for_plane(dev_priv, 0);
1552 if (intel_crtc_active(crtc)) {
1553 const struct drm_display_mode *adjusted_mode =
1554 &crtc->config->base.adjusted_mode;
1555 const struct drm_framebuffer *fb =
1556 crtc->base.primary->state->fb;
1557 int cpp;
1558
1559 if (IS_GEN2(dev_priv))
1560 cpp = 4;
1561 else
1562 cpp = fb->format->cpp[0];
1563
1564 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1565 wm_info, fifo_size, cpp,
1566 pessimal_latency_ns);
1567 enabled = crtc;
1568 } else {
1569 planea_wm = fifo_size - wm_info->guard_size;
1570 if (planea_wm > (long)wm_info->max_wm)
1571 planea_wm = wm_info->max_wm;
1572 }
1573
1574 if (IS_GEN2(dev_priv))
1575 wm_info = &i830_bc_wm_info;
1576
1577 fifo_size = dev_priv->display.get_fifo_size(dev_priv, 1);
1578 crtc = intel_get_crtc_for_plane(dev_priv, 1);
1579 if (intel_crtc_active(crtc)) {
1580 const struct drm_display_mode *adjusted_mode =
1581 &crtc->config->base.adjusted_mode;
1582 const struct drm_framebuffer *fb =
1583 crtc->base.primary->state->fb;
1584 int cpp;
1585
1586 if (IS_GEN2(dev_priv))
1587 cpp = 4;
1588 else
1589 cpp = fb->format->cpp[0];
1590
1591 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1592 wm_info, fifo_size, cpp,
1593 pessimal_latency_ns);
1594 if (enabled == NULL)
1595 enabled = crtc;
1596 else
1597 enabled = NULL;
1598 } else {
1599 planeb_wm = fifo_size - wm_info->guard_size;
1600 if (planeb_wm > (long)wm_info->max_wm)
1601 planeb_wm = wm_info->max_wm;
1602 }
1603
1604 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1605
1606 if (IS_I915GM(dev_priv) && enabled) {
1607 struct drm_i915_gem_object *obj;
1608
1609 obj = intel_fb_obj(enabled->base.primary->state->fb);
1610
1611 /* self-refresh seems busted with untiled */
1612 if (!i915_gem_object_is_tiled(obj))
1613 enabled = NULL;
1614 }
1615
1616 /*
1617 * Overlay gets an aggressive default since video jitter is bad.
1618 */
1619 cwm = 2;
1620
1621 /* Play safe and disable self-refresh before adjusting watermarks. */
1622 intel_set_memory_cxsr(dev_priv, false);
1623
1624 /* Calc sr entries for one plane configs */
1625 if (HAS_FW_BLC(dev_priv) && enabled) {
1626 /* self-refresh has much higher latency */
1627 static const int sr_latency_ns = 6000;
1628 const struct drm_display_mode *adjusted_mode =
1629 &enabled->config->base.adjusted_mode;
1630 const struct drm_framebuffer *fb =
1631 enabled->base.primary->state->fb;
1632 int clock = adjusted_mode->crtc_clock;
1633 int htotal = adjusted_mode->crtc_htotal;
1634 int hdisplay = enabled->config->pipe_src_w;
1635 int cpp;
1636 unsigned long line_time_us;
1637 int entries;
1638
1639 if (IS_I915GM(dev_priv) || IS_I945GM(dev_priv))
1640 cpp = 4;
1641 else
1642 cpp = fb->format->cpp[0];
1643
1644 line_time_us = max(htotal * 1000 / clock, 1);
1645
1646 /* Use ns/us then divide to preserve precision */
1647 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1648 cpp * hdisplay;
1649 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1650 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1651 srwm = wm_info->fifo_size - entries;
1652 if (srwm < 0)
1653 srwm = 1;
1654
1655 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
1656 I915_WRITE(FW_BLC_SELF,
1657 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1658 else
1659 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1660 }
1661
1662 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1663 planea_wm, planeb_wm, cwm, srwm);
1664
1665 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1666 fwater_hi = (cwm & 0x1f);
1667
1668 /* Set request length to 8 cachelines per fetch */
1669 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1670 fwater_hi = fwater_hi | (1 << 8);
1671
1672 I915_WRITE(FW_BLC, fwater_lo);
1673 I915_WRITE(FW_BLC2, fwater_hi);
1674
1675 if (enabled)
1676 intel_set_memory_cxsr(dev_priv, true);
1677 }
1678
1679 static void i845_update_wm(struct intel_crtc *unused_crtc)
1680 {
1681 struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
1682 struct intel_crtc *crtc;
1683 const struct drm_display_mode *adjusted_mode;
1684 uint32_t fwater_lo;
1685 int planea_wm;
1686
1687 crtc = single_enabled_crtc(dev_priv);
1688 if (crtc == NULL)
1689 return;
1690
1691 adjusted_mode = &crtc->config->base.adjusted_mode;
1692 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1693 &i845_wm_info,
1694 dev_priv->display.get_fifo_size(dev_priv, 0),
1695 4, pessimal_latency_ns);
1696 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1697 fwater_lo |= (3<<8) | planea_wm;
1698
1699 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1700
1701 I915_WRITE(FW_BLC, fwater_lo);
1702 }
1703
1704 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
1705 {
1706 uint32_t pixel_rate;
1707
1708 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
1709
1710 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1711 * adjust the pixel_rate here. */
1712
1713 if (pipe_config->pch_pfit.enabled) {
1714 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1715 uint32_t pfit_size = pipe_config->pch_pfit.size;
1716
1717 pipe_w = pipe_config->pipe_src_w;
1718 pipe_h = pipe_config->pipe_src_h;
1719
1720 pfit_w = (pfit_size >> 16) & 0xFFFF;
1721 pfit_h = pfit_size & 0xFFFF;
1722 if (pipe_w < pfit_w)
1723 pipe_w = pfit_w;
1724 if (pipe_h < pfit_h)
1725 pipe_h = pfit_h;
1726
1727 if (WARN_ON(!pfit_w || !pfit_h))
1728 return pixel_rate;
1729
1730 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1731 pfit_w * pfit_h);
1732 }
1733
1734 return pixel_rate;
1735 }
1736
1737 /* latency must be in 0.1us units. */
1738 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
1739 {
1740 uint64_t ret;
1741
1742 if (WARN(latency == 0, "Latency value missing\n"))
1743 return UINT_MAX;
1744
1745 ret = (uint64_t) pixel_rate * cpp * latency;
1746 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1747
1748 return ret;
1749 }
1750
1751 /* latency must be in 0.1us units. */
1752 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1753 uint32_t horiz_pixels, uint8_t cpp,
1754 uint32_t latency)
1755 {
1756 uint32_t ret;
1757
1758 if (WARN(latency == 0, "Latency value missing\n"))
1759 return UINT_MAX;
1760 if (WARN_ON(!pipe_htotal))
1761 return UINT_MAX;
1762
1763 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1764 ret = (ret + 1) * horiz_pixels * cpp;
1765 ret = DIV_ROUND_UP(ret, 64) + 2;
1766 return ret;
1767 }
1768
1769 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1770 uint8_t cpp)
1771 {
1772 /*
1773 * Neither of these should be possible since this function shouldn't be
1774 * called if the CRTC is off or the plane is invisible. But let's be
1775 * extra paranoid to avoid a potential divide-by-zero if we screw up
1776 * elsewhere in the driver.
1777 */
1778 if (WARN_ON(!cpp))
1779 return 0;
1780 if (WARN_ON(!horiz_pixels))
1781 return 0;
1782
1783 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
1784 }
1785
1786 struct ilk_wm_maximums {
1787 uint16_t pri;
1788 uint16_t spr;
1789 uint16_t cur;
1790 uint16_t fbc;
1791 };
1792
1793 /*
1794 * For both WM_PIPE and WM_LP.
1795 * mem_value must be in 0.1us units.
1796 */
1797 static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
1798 const struct intel_plane_state *pstate,
1799 uint32_t mem_value,
1800 bool is_lp)
1801 {
1802 uint32_t method1, method2;
1803 int cpp;
1804
1805 if (!cstate->base.active || !pstate->base.visible)
1806 return 0;
1807
1808 cpp = pstate->base.fb->format->cpp[0];
1809
1810 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
1811
1812 if (!is_lp)
1813 return method1;
1814
1815 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1816 cstate->base.adjusted_mode.crtc_htotal,
1817 drm_rect_width(&pstate->base.dst),
1818 cpp, mem_value);
1819
1820 return min(method1, method2);
1821 }
1822
1823 /*
1824 * For both WM_PIPE and WM_LP.
1825 * mem_value must be in 0.1us units.
1826 */
1827 static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
1828 const struct intel_plane_state *pstate,
1829 uint32_t mem_value)
1830 {
1831 uint32_t method1, method2;
1832 int cpp;
1833
1834 if (!cstate->base.active || !pstate->base.visible)
1835 return 0;
1836
1837 cpp = pstate->base.fb->format->cpp[0];
1838
1839 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
1840 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1841 cstate->base.adjusted_mode.crtc_htotal,
1842 drm_rect_width(&pstate->base.dst),
1843 cpp, mem_value);
1844 return min(method1, method2);
1845 }
1846
1847 /*
1848 * For both WM_PIPE and WM_LP.
1849 * mem_value must be in 0.1us units.
1850 */
1851 static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
1852 const struct intel_plane_state *pstate,
1853 uint32_t mem_value)
1854 {
1855 /*
1856 * We treat the cursor plane as always-on for the purposes of watermark
1857 * calculation. Until we have two-stage watermark programming merged,
1858 * this is necessary to avoid flickering.
1859 */
1860 int cpp = 4;
1861 int width = pstate->base.visible ? pstate->base.crtc_w : 64;
1862
1863 if (!cstate->base.active)
1864 return 0;
1865
1866 return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1867 cstate->base.adjusted_mode.crtc_htotal,
1868 width, cpp, mem_value);
1869 }
1870
1871 /* Only for WM_LP. */
1872 static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
1873 const struct intel_plane_state *pstate,
1874 uint32_t pri_val)
1875 {
1876 int cpp;
1877
1878 if (!cstate->base.active || !pstate->base.visible)
1879 return 0;
1880
1881 cpp = pstate->base.fb->format->cpp[0];
1882
1883 return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->base.dst), cpp);
1884 }
1885
1886 static unsigned int
1887 ilk_display_fifo_size(const struct drm_i915_private *dev_priv)
1888 {
1889 if (INTEL_GEN(dev_priv) >= 8)
1890 return 3072;
1891 else if (INTEL_GEN(dev_priv) >= 7)
1892 return 768;
1893 else
1894 return 512;
1895 }
1896
1897 static unsigned int
1898 ilk_plane_wm_reg_max(const struct drm_i915_private *dev_priv,
1899 int level, bool is_sprite)
1900 {
1901 if (INTEL_GEN(dev_priv) >= 8)
1902 /* BDW primary/sprite plane watermarks */
1903 return level == 0 ? 255 : 2047;
1904 else if (INTEL_GEN(dev_priv) >= 7)
1905 /* IVB/HSW primary/sprite plane watermarks */
1906 return level == 0 ? 127 : 1023;
1907 else if (!is_sprite)
1908 /* ILK/SNB primary plane watermarks */
1909 return level == 0 ? 127 : 511;
1910 else
1911 /* ILK/SNB sprite plane watermarks */
1912 return level == 0 ? 63 : 255;
1913 }
1914
1915 static unsigned int
1916 ilk_cursor_wm_reg_max(const struct drm_i915_private *dev_priv, int level)
1917 {
1918 if (INTEL_GEN(dev_priv) >= 7)
1919 return level == 0 ? 63 : 255;
1920 else
1921 return level == 0 ? 31 : 63;
1922 }
1923
1924 static unsigned int ilk_fbc_wm_reg_max(const struct drm_i915_private *dev_priv)
1925 {
1926 if (INTEL_GEN(dev_priv) >= 8)
1927 return 31;
1928 else
1929 return 15;
1930 }
1931
1932 /* Calculate the maximum primary/sprite plane watermark */
1933 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1934 int level,
1935 const struct intel_wm_config *config,
1936 enum intel_ddb_partitioning ddb_partitioning,
1937 bool is_sprite)
1938 {
1939 struct drm_i915_private *dev_priv = to_i915(dev);
1940 unsigned int fifo_size = ilk_display_fifo_size(dev_priv);
1941
1942 /* if sprites aren't enabled, sprites get nothing */
1943 if (is_sprite && !config->sprites_enabled)
1944 return 0;
1945
1946 /* HSW allows LP1+ watermarks even with multiple pipes */
1947 if (level == 0 || config->num_pipes_active > 1) {
1948 fifo_size /= INTEL_INFO(dev_priv)->num_pipes;
1949
1950 /*
1951 * For some reason the non self refresh
1952 * FIFO size is only half of the self
1953 * refresh FIFO size on ILK/SNB.
1954 */
1955 if (INTEL_GEN(dev_priv) <= 6)
1956 fifo_size /= 2;
1957 }
1958
1959 if (config->sprites_enabled) {
1960 /* level 0 is always calculated with 1:1 split */
1961 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1962 if (is_sprite)
1963 fifo_size *= 5;
1964 fifo_size /= 6;
1965 } else {
1966 fifo_size /= 2;
1967 }
1968 }
1969
1970 /* clamp to max that the registers can hold */
1971 return min(fifo_size, ilk_plane_wm_reg_max(dev_priv, level, is_sprite));
1972 }
1973
1974 /* Calculate the maximum cursor plane watermark */
1975 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
1976 int level,
1977 const struct intel_wm_config *config)
1978 {
1979 /* HSW LP1+ watermarks w/ multiple pipes */
1980 if (level > 0 && config->num_pipes_active > 1)
1981 return 64;
1982
1983 /* otherwise just report max that registers can hold */
1984 return ilk_cursor_wm_reg_max(to_i915(dev), level);
1985 }
1986
1987 static void ilk_compute_wm_maximums(const struct drm_device *dev,
1988 int level,
1989 const struct intel_wm_config *config,
1990 enum intel_ddb_partitioning ddb_partitioning,
1991 struct ilk_wm_maximums *max)
1992 {
1993 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1994 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1995 max->cur = ilk_cursor_wm_max(dev, level, config);
1996 max->fbc = ilk_fbc_wm_reg_max(to_i915(dev));
1997 }
1998
1999 static void ilk_compute_wm_reg_maximums(const struct drm_i915_private *dev_priv,
2000 int level,
2001 struct ilk_wm_maximums *max)
2002 {
2003 max->pri = ilk_plane_wm_reg_max(dev_priv, level, false);
2004 max->spr = ilk_plane_wm_reg_max(dev_priv, level, true);
2005 max->cur = ilk_cursor_wm_reg_max(dev_priv, level);
2006 max->fbc = ilk_fbc_wm_reg_max(dev_priv);
2007 }
2008
2009 static bool ilk_validate_wm_level(int level,
2010 const struct ilk_wm_maximums *max,
2011 struct intel_wm_level *result)
2012 {
2013 bool ret;
2014
2015 /* already determined to be invalid? */
2016 if (!result->enable)
2017 return false;
2018
2019 result->enable = result->pri_val <= max->pri &&
2020 result->spr_val <= max->spr &&
2021 result->cur_val <= max->cur;
2022
2023 ret = result->enable;
2024
2025 /*
2026 * HACK until we can pre-compute everything,
2027 * and thus fail gracefully if LP0 watermarks
2028 * are exceeded...
2029 */
2030 if (level == 0 && !result->enable) {
2031 if (result->pri_val > max->pri)
2032 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2033 level, result->pri_val, max->pri);
2034 if (result->spr_val > max->spr)
2035 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2036 level, result->spr_val, max->spr);
2037 if (result->cur_val > max->cur)
2038 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2039 level, result->cur_val, max->cur);
2040
2041 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2042 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2043 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2044 result->enable = true;
2045 }
2046
2047 return ret;
2048 }
2049
2050 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
2051 const struct intel_crtc *intel_crtc,
2052 int level,
2053 struct intel_crtc_state *cstate,
2054 struct intel_plane_state *pristate,
2055 struct intel_plane_state *sprstate,
2056 struct intel_plane_state *curstate,
2057 struct intel_wm_level *result)
2058 {
2059 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2060 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2061 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2062
2063 /* WM1+ latency values stored in 0.5us units */
2064 if (level > 0) {
2065 pri_latency *= 5;
2066 spr_latency *= 5;
2067 cur_latency *= 5;
2068 }
2069
2070 if (pristate) {
2071 result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2072 pri_latency, level);
2073 result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
2074 }
2075
2076 if (sprstate)
2077 result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2078
2079 if (curstate)
2080 result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2081
2082 result->enable = true;
2083 }
2084
2085 static uint32_t
2086 hsw_compute_linetime_wm(const struct intel_crtc_state *cstate)
2087 {
2088 const struct intel_atomic_state *intel_state =
2089 to_intel_atomic_state(cstate->base.state);
2090 const struct drm_display_mode *adjusted_mode =
2091 &cstate->base.adjusted_mode;
2092 u32 linetime, ips_linetime;
2093
2094 if (!cstate->base.active)
2095 return 0;
2096 if (WARN_ON(adjusted_mode->crtc_clock == 0))
2097 return 0;
2098 if (WARN_ON(intel_state->cdclk == 0))
2099 return 0;
2100
2101 /* The WM are computed with base on how long it takes to fill a single
2102 * row at the given clock rate, multiplied by 8.
2103 * */
2104 linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2105 adjusted_mode->crtc_clock);
2106 ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2107 intel_state->cdclk);
2108
2109 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2110 PIPE_WM_LINETIME_TIME(linetime);
2111 }
2112
2113 static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
2114 uint16_t wm[8])
2115 {
2116 if (IS_GEN9(dev_priv)) {
2117 uint32_t val;
2118 int ret, i;
2119 int level, max_level = ilk_wm_max_level(dev_priv);
2120
2121 /* read the first set of memory latencies[0:3] */
2122 val = 0; /* data0 to be programmed to 0 for first set */
2123 mutex_lock(&dev_priv->rps.hw_lock);
2124 ret = sandybridge_pcode_read(dev_priv,
2125 GEN9_PCODE_READ_MEM_LATENCY,
2126 &val);
2127 mutex_unlock(&dev_priv->rps.hw_lock);
2128
2129 if (ret) {
2130 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2131 return;
2132 }
2133
2134 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2135 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2136 GEN9_MEM_LATENCY_LEVEL_MASK;
2137 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2138 GEN9_MEM_LATENCY_LEVEL_MASK;
2139 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2140 GEN9_MEM_LATENCY_LEVEL_MASK;
2141
2142 /* read the second set of memory latencies[4:7] */
2143 val = 1; /* data0 to be programmed to 1 for second set */
2144 mutex_lock(&dev_priv->rps.hw_lock);
2145 ret = sandybridge_pcode_read(dev_priv,
2146 GEN9_PCODE_READ_MEM_LATENCY,
2147 &val);
2148 mutex_unlock(&dev_priv->rps.hw_lock);
2149 if (ret) {
2150 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2151 return;
2152 }
2153
2154 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2155 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2156 GEN9_MEM_LATENCY_LEVEL_MASK;
2157 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2158 GEN9_MEM_LATENCY_LEVEL_MASK;
2159 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2160 GEN9_MEM_LATENCY_LEVEL_MASK;
2161
2162 /*
2163 * If a level n (n > 1) has a 0us latency, all levels m (m >= n)
2164 * need to be disabled. We make sure to sanitize the values out
2165 * of the punit to satisfy this requirement.
2166 */
2167 for (level = 1; level <= max_level; level++) {
2168 if (wm[level] == 0) {
2169 for (i = level + 1; i <= max_level; i++)
2170 wm[i] = 0;
2171 break;
2172 }
2173 }
2174
2175 /*
2176 * WaWmMemoryReadLatency:skl
2177 *
2178 * punit doesn't take into account the read latency so we need
2179 * to add 2us to the various latency levels we retrieve from the
2180 * punit when level 0 response data us 0us.
2181 */
2182 if (wm[0] == 0) {
2183 wm[0] += 2;
2184 for (level = 1; level <= max_level; level++) {
2185 if (wm[level] == 0)
2186 break;
2187 wm[level] += 2;
2188 }
2189 }
2190
2191 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2192 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2193
2194 wm[0] = (sskpd >> 56) & 0xFF;
2195 if (wm[0] == 0)
2196 wm[0] = sskpd & 0xF;
2197 wm[1] = (sskpd >> 4) & 0xFF;
2198 wm[2] = (sskpd >> 12) & 0xFF;
2199 wm[3] = (sskpd >> 20) & 0x1FF;
2200 wm[4] = (sskpd >> 32) & 0x1FF;
2201 } else if (INTEL_GEN(dev_priv) >= 6) {
2202 uint32_t sskpd = I915_READ(MCH_SSKPD);
2203
2204 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2205 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2206 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2207 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2208 } else if (INTEL_GEN(dev_priv) >= 5) {
2209 uint32_t mltr = I915_READ(MLTR_ILK);
2210
2211 /* ILK primary LP0 latency is 700 ns */
2212 wm[0] = 7;
2213 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2214 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2215 }
2216 }
2217
2218 static void intel_fixup_spr_wm_latency(struct drm_i915_private *dev_priv,
2219 uint16_t wm[5])
2220 {
2221 /* ILK sprite LP0 latency is 1300 ns */
2222 if (IS_GEN5(dev_priv))
2223 wm[0] = 13;
2224 }
2225
2226 static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv,
2227 uint16_t wm[5])
2228 {
2229 /* ILK cursor LP0 latency is 1300 ns */
2230 if (IS_GEN5(dev_priv))
2231 wm[0] = 13;
2232
2233 /* WaDoubleCursorLP3Latency:ivb */
2234 if (IS_IVYBRIDGE(dev_priv))
2235 wm[3] *= 2;
2236 }
2237
2238 int ilk_wm_max_level(const struct drm_i915_private *dev_priv)
2239 {
2240 /* how many WM levels are we expecting */
2241 if (INTEL_GEN(dev_priv) >= 9)
2242 return 7;
2243 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2244 return 4;
2245 else if (INTEL_GEN(dev_priv) >= 6)
2246 return 3;
2247 else
2248 return 2;
2249 }
2250
2251 static void intel_print_wm_latency(struct drm_i915_private *dev_priv,
2252 const char *name,
2253 const uint16_t wm[8])
2254 {
2255 int level, max_level = ilk_wm_max_level(dev_priv);
2256
2257 for (level = 0; level <= max_level; level++) {
2258 unsigned int latency = wm[level];
2259
2260 if (latency == 0) {
2261 DRM_ERROR("%s WM%d latency not provided\n",
2262 name, level);
2263 continue;
2264 }
2265
2266 /*
2267 * - latencies are in us on gen9.
2268 * - before then, WM1+ latency values are in 0.5us units
2269 */
2270 if (IS_GEN9(dev_priv))
2271 latency *= 10;
2272 else if (level > 0)
2273 latency *= 5;
2274
2275 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2276 name, level, wm[level],
2277 latency / 10, latency % 10);
2278 }
2279 }
2280
2281 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2282 uint16_t wm[5], uint16_t min)
2283 {
2284 int level, max_level = ilk_wm_max_level(dev_priv);
2285
2286 if (wm[0] >= min)
2287 return false;
2288
2289 wm[0] = max(wm[0], min);
2290 for (level = 1; level <= max_level; level++)
2291 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2292
2293 return true;
2294 }
2295
2296 static void snb_wm_latency_quirk(struct drm_i915_private *dev_priv)
2297 {
2298 bool changed;
2299
2300 /*
2301 * The BIOS provided WM memory latency values are often
2302 * inadequate for high resolution displays. Adjust them.
2303 */
2304 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2305 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2306 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2307
2308 if (!changed)
2309 return;
2310
2311 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2312 intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
2313 intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
2314 intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
2315 }
2316
2317 static void ilk_setup_wm_latency(struct drm_i915_private *dev_priv)
2318 {
2319 intel_read_wm_latency(dev_priv, dev_priv->wm.pri_latency);
2320
2321 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2322 sizeof(dev_priv->wm.pri_latency));
2323 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2324 sizeof(dev_priv->wm.pri_latency));
2325
2326 intel_fixup_spr_wm_latency(dev_priv, dev_priv->wm.spr_latency);
2327 intel_fixup_cur_wm_latency(dev_priv, dev_priv->wm.cur_latency);
2328
2329 intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
2330 intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
2331 intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
2332
2333 if (IS_GEN6(dev_priv))
2334 snb_wm_latency_quirk(dev_priv);
2335 }
2336
2337 static void skl_setup_wm_latency(struct drm_i915_private *dev_priv)
2338 {
2339 intel_read_wm_latency(dev_priv, dev_priv->wm.skl_latency);
2340 intel_print_wm_latency(dev_priv, "Gen9 Plane", dev_priv->wm.skl_latency);
2341 }
2342
2343 static bool ilk_validate_pipe_wm(struct drm_device *dev,
2344 struct intel_pipe_wm *pipe_wm)
2345 {
2346 /* LP0 watermark maximums depend on this pipe alone */
2347 const struct intel_wm_config config = {
2348 .num_pipes_active = 1,
2349 .sprites_enabled = pipe_wm->sprites_enabled,
2350 .sprites_scaled = pipe_wm->sprites_scaled,
2351 };
2352 struct ilk_wm_maximums max;
2353
2354 /* LP0 watermarks always use 1/2 DDB partitioning */
2355 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2356
2357 /* At least LP0 must be valid */
2358 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
2359 DRM_DEBUG_KMS("LP0 watermark invalid\n");
2360 return false;
2361 }
2362
2363 return true;
2364 }
2365
2366 /* Compute new watermarks for the pipe */
2367 static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
2368 {
2369 struct drm_atomic_state *state = cstate->base.state;
2370 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2371 struct intel_pipe_wm *pipe_wm;
2372 struct drm_device *dev = state->dev;
2373 const struct drm_i915_private *dev_priv = to_i915(dev);
2374 struct intel_plane *intel_plane;
2375 struct intel_plane_state *pristate = NULL;
2376 struct intel_plane_state *sprstate = NULL;
2377 struct intel_plane_state *curstate = NULL;
2378 int level, max_level = ilk_wm_max_level(dev_priv), usable_level;
2379 struct ilk_wm_maximums max;
2380
2381 pipe_wm = &cstate->wm.ilk.optimal;
2382
2383 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2384 struct intel_plane_state *ps;
2385
2386 ps = intel_atomic_get_existing_plane_state(state,
2387 intel_plane);
2388 if (!ps)
2389 continue;
2390
2391 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
2392 pristate = ps;
2393 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
2394 sprstate = ps;
2395 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
2396 curstate = ps;
2397 }
2398
2399 pipe_wm->pipe_enabled = cstate->base.active;
2400 if (sprstate) {
2401 pipe_wm->sprites_enabled = sprstate->base.visible;
2402 pipe_wm->sprites_scaled = sprstate->base.visible &&
2403 (drm_rect_width(&sprstate->base.dst) != drm_rect_width(&sprstate->base.src) >> 16 ||
2404 drm_rect_height(&sprstate->base.dst) != drm_rect_height(&sprstate->base.src) >> 16);
2405 }
2406
2407 usable_level = max_level;
2408
2409 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2410 if (INTEL_GEN(dev_priv) <= 6 && pipe_wm->sprites_enabled)
2411 usable_level = 1;
2412
2413 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2414 if (pipe_wm->sprites_scaled)
2415 usable_level = 0;
2416
2417 ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
2418 pristate, sprstate, curstate, &pipe_wm->raw_wm[0]);
2419
2420 memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
2421 pipe_wm->wm[0] = pipe_wm->raw_wm[0];
2422
2423 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2424 pipe_wm->linetime = hsw_compute_linetime_wm(cstate);
2425
2426 if (!ilk_validate_pipe_wm(dev, pipe_wm))
2427 return -EINVAL;
2428
2429 ilk_compute_wm_reg_maximums(dev_priv, 1, &max);
2430
2431 for (level = 1; level <= max_level; level++) {
2432 struct intel_wm_level *wm = &pipe_wm->raw_wm[level];
2433
2434 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
2435 pristate, sprstate, curstate, wm);
2436
2437 /*
2438 * Disable any watermark level that exceeds the
2439 * register maximums since such watermarks are
2440 * always invalid.
2441 */
2442 if (level > usable_level)
2443 continue;
2444
2445 if (ilk_validate_wm_level(level, &max, wm))
2446 pipe_wm->wm[level] = *wm;
2447 else
2448 usable_level = level;
2449 }
2450
2451 return 0;
2452 }
2453
2454 /*
2455 * Build a set of 'intermediate' watermark values that satisfy both the old
2456 * state and the new state. These can be programmed to the hardware
2457 * immediately.
2458 */
2459 static int ilk_compute_intermediate_wm(struct drm_device *dev,
2460 struct intel_crtc *intel_crtc,
2461 struct intel_crtc_state *newstate)
2462 {
2463 struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
2464 struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk;
2465 int level, max_level = ilk_wm_max_level(to_i915(dev));
2466
2467 /*
2468 * Start with the final, target watermarks, then combine with the
2469 * currently active watermarks to get values that are safe both before
2470 * and after the vblank.
2471 */
2472 *a = newstate->wm.ilk.optimal;
2473 a->pipe_enabled |= b->pipe_enabled;
2474 a->sprites_enabled |= b->sprites_enabled;
2475 a->sprites_scaled |= b->sprites_scaled;
2476
2477 for (level = 0; level <= max_level; level++) {
2478 struct intel_wm_level *a_wm = &a->wm[level];
2479 const struct intel_wm_level *b_wm = &b->wm[level];
2480
2481 a_wm->enable &= b_wm->enable;
2482 a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
2483 a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
2484 a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
2485 a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
2486 }
2487
2488 /*
2489 * We need to make sure that these merged watermark values are
2490 * actually a valid configuration themselves. If they're not,
2491 * there's no safe way to transition from the old state to
2492 * the new state, so we need to fail the atomic transaction.
2493 */
2494 if (!ilk_validate_pipe_wm(dev, a))
2495 return -EINVAL;
2496
2497 /*
2498 * If our intermediate WM are identical to the final WM, then we can
2499 * omit the post-vblank programming; only update if it's different.
2500 */
2501 if (memcmp(a, &newstate->wm.ilk.optimal, sizeof(*a)) == 0)
2502 newstate->wm.need_postvbl_update = false;
2503
2504 return 0;
2505 }
2506
2507 /*
2508 * Merge the watermarks from all active pipes for a specific level.
2509 */
2510 static void ilk_merge_wm_level(struct drm_device *dev,
2511 int level,
2512 struct intel_wm_level *ret_wm)
2513 {
2514 const struct intel_crtc *intel_crtc;
2515
2516 ret_wm->enable = true;
2517
2518 for_each_intel_crtc(dev, intel_crtc) {
2519 const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
2520 const struct intel_wm_level *wm = &active->wm[level];
2521
2522 if (!active->pipe_enabled)
2523 continue;
2524
2525 /*
2526 * The watermark values may have been used in the past,
2527 * so we must maintain them in the registers for some
2528 * time even if the level is now disabled.
2529 */
2530 if (!wm->enable)
2531 ret_wm->enable = false;
2532
2533 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2534 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2535 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2536 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2537 }
2538 }
2539
2540 /*
2541 * Merge all low power watermarks for all active pipes.
2542 */
2543 static void ilk_wm_merge(struct drm_device *dev,
2544 const struct intel_wm_config *config,
2545 const struct ilk_wm_maximums *max,
2546 struct intel_pipe_wm *merged)
2547 {
2548 struct drm_i915_private *dev_priv = to_i915(dev);
2549 int level, max_level = ilk_wm_max_level(dev_priv);
2550 int last_enabled_level = max_level;
2551
2552 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2553 if ((INTEL_GEN(dev_priv) <= 6 || IS_IVYBRIDGE(dev_priv)) &&
2554 config->num_pipes_active > 1)
2555 last_enabled_level = 0;
2556
2557 /* ILK: FBC WM must be disabled always */
2558 merged->fbc_wm_enabled = INTEL_GEN(dev_priv) >= 6;
2559
2560 /* merge each WM1+ level */
2561 for (level = 1; level <= max_level; level++) {
2562 struct intel_wm_level *wm = &merged->wm[level];
2563
2564 ilk_merge_wm_level(dev, level, wm);
2565
2566 if (level > last_enabled_level)
2567 wm->enable = false;
2568 else if (!ilk_validate_wm_level(level, max, wm))
2569 /* make sure all following levels get disabled */
2570 last_enabled_level = level - 1;
2571
2572 /*
2573 * The spec says it is preferred to disable
2574 * FBC WMs instead of disabling a WM level.
2575 */
2576 if (wm->fbc_val > max->fbc) {
2577 if (wm->enable)
2578 merged->fbc_wm_enabled = false;
2579 wm->fbc_val = 0;
2580 }
2581 }
2582
2583 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2584 /*
2585 * FIXME this is racy. FBC might get enabled later.
2586 * What we should check here is whether FBC can be
2587 * enabled sometime later.
2588 */
2589 if (IS_GEN5(dev_priv) && !merged->fbc_wm_enabled &&
2590 intel_fbc_is_active(dev_priv)) {
2591 for (level = 2; level <= max_level; level++) {
2592 struct intel_wm_level *wm = &merged->wm[level];
2593
2594 wm->enable = false;
2595 }
2596 }
2597 }
2598
2599 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2600 {
2601 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2602 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2603 }
2604
2605 /* The value we need to program into the WM_LPx latency field */
2606 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2607 {
2608 struct drm_i915_private *dev_priv = to_i915(dev);
2609
2610 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2611 return 2 * level;
2612 else
2613 return dev_priv->wm.pri_latency[level];
2614 }
2615
2616 static void ilk_compute_wm_results(struct drm_device *dev,
2617 const struct intel_pipe_wm *merged,
2618 enum intel_ddb_partitioning partitioning,
2619 struct ilk_wm_values *results)
2620 {
2621 struct drm_i915_private *dev_priv = to_i915(dev);
2622 struct intel_crtc *intel_crtc;
2623 int level, wm_lp;
2624
2625 results->enable_fbc_wm = merged->fbc_wm_enabled;
2626 results->partitioning = partitioning;
2627
2628 /* LP1+ register values */
2629 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2630 const struct intel_wm_level *r;
2631
2632 level = ilk_wm_lp_to_level(wm_lp, merged);
2633
2634 r = &merged->wm[level];
2635
2636 /*
2637 * Maintain the watermark values even if the level is
2638 * disabled. Doing otherwise could cause underruns.
2639 */
2640 results->wm_lp[wm_lp - 1] =
2641 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2642 (r->pri_val << WM1_LP_SR_SHIFT) |
2643 r->cur_val;
2644
2645 if (r->enable)
2646 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2647
2648 if (INTEL_GEN(dev_priv) >= 8)
2649 results->wm_lp[wm_lp - 1] |=
2650 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2651 else
2652 results->wm_lp[wm_lp - 1] |=
2653 r->fbc_val << WM1_LP_FBC_SHIFT;
2654
2655 /*
2656 * Always set WM1S_LP_EN when spr_val != 0, even if the
2657 * level is disabled. Doing otherwise could cause underruns.
2658 */
2659 if (INTEL_GEN(dev_priv) <= 6 && r->spr_val) {
2660 WARN_ON(wm_lp != 1);
2661 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2662 } else
2663 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2664 }
2665
2666 /* LP0 register values */
2667 for_each_intel_crtc(dev, intel_crtc) {
2668 enum pipe pipe = intel_crtc->pipe;
2669 const struct intel_wm_level *r =
2670 &intel_crtc->wm.active.ilk.wm[0];
2671
2672 if (WARN_ON(!r->enable))
2673 continue;
2674
2675 results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime;
2676
2677 results->wm_pipe[pipe] =
2678 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2679 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2680 r->cur_val;
2681 }
2682 }
2683
2684 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2685 * case both are at the same level. Prefer r1 in case they're the same. */
2686 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2687 struct intel_pipe_wm *r1,
2688 struct intel_pipe_wm *r2)
2689 {
2690 int level, max_level = ilk_wm_max_level(to_i915(dev));
2691 int level1 = 0, level2 = 0;
2692
2693 for (level = 1; level <= max_level; level++) {
2694 if (r1->wm[level].enable)
2695 level1 = level;
2696 if (r2->wm[level].enable)
2697 level2 = level;
2698 }
2699
2700 if (level1 == level2) {
2701 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2702 return r2;
2703 else
2704 return r1;
2705 } else if (level1 > level2) {
2706 return r1;
2707 } else {
2708 return r2;
2709 }
2710 }
2711
2712 /* dirty bits used to track which watermarks need changes */
2713 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2714 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2715 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2716 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2717 #define WM_DIRTY_FBC (1 << 24)
2718 #define WM_DIRTY_DDB (1 << 25)
2719
2720 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
2721 const struct ilk_wm_values *old,
2722 const struct ilk_wm_values *new)
2723 {
2724 unsigned int dirty = 0;
2725 enum pipe pipe;
2726 int wm_lp;
2727
2728 for_each_pipe(dev_priv, pipe) {
2729 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2730 dirty |= WM_DIRTY_LINETIME(pipe);
2731 /* Must disable LP1+ watermarks too */
2732 dirty |= WM_DIRTY_LP_ALL;
2733 }
2734
2735 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2736 dirty |= WM_DIRTY_PIPE(pipe);
2737 /* Must disable LP1+ watermarks too */
2738 dirty |= WM_DIRTY_LP_ALL;
2739 }
2740 }
2741
2742 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2743 dirty |= WM_DIRTY_FBC;
2744 /* Must disable LP1+ watermarks too */
2745 dirty |= WM_DIRTY_LP_ALL;
2746 }
2747
2748 if (old->partitioning != new->partitioning) {
2749 dirty |= WM_DIRTY_DDB;
2750 /* Must disable LP1+ watermarks too */
2751 dirty |= WM_DIRTY_LP_ALL;
2752 }
2753
2754 /* LP1+ watermarks already deemed dirty, no need to continue */
2755 if (dirty & WM_DIRTY_LP_ALL)
2756 return dirty;
2757
2758 /* Find the lowest numbered LP1+ watermark in need of an update... */
2759 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2760 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2761 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2762 break;
2763 }
2764
2765 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2766 for (; wm_lp <= 3; wm_lp++)
2767 dirty |= WM_DIRTY_LP(wm_lp);
2768
2769 return dirty;
2770 }
2771
2772 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2773 unsigned int dirty)
2774 {
2775 struct ilk_wm_values *previous = &dev_priv->wm.hw;
2776 bool changed = false;
2777
2778 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2779 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2780 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2781 changed = true;
2782 }
2783 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2784 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2785 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2786 changed = true;
2787 }
2788 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2789 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2790 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2791 changed = true;
2792 }
2793
2794 /*
2795 * Don't touch WM1S_LP_EN here.
2796 * Doing so could cause underruns.
2797 */
2798
2799 return changed;
2800 }
2801
2802 /*
2803 * The spec says we shouldn't write when we don't need, because every write
2804 * causes WMs to be re-evaluated, expending some power.
2805 */
2806 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2807 struct ilk_wm_values *results)
2808 {
2809 struct ilk_wm_values *previous = &dev_priv->wm.hw;
2810 unsigned int dirty;
2811 uint32_t val;
2812
2813 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
2814 if (!dirty)
2815 return;
2816
2817 _ilk_disable_lp_wm(dev_priv, dirty);
2818
2819 if (dirty & WM_DIRTY_PIPE(PIPE_A))
2820 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2821 if (dirty & WM_DIRTY_PIPE(PIPE_B))
2822 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2823 if (dirty & WM_DIRTY_PIPE(PIPE_C))
2824 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2825
2826 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2827 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2828 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2829 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2830 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2831 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2832
2833 if (dirty & WM_DIRTY_DDB) {
2834 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2835 val = I915_READ(WM_MISC);
2836 if (results->partitioning == INTEL_DDB_PART_1_2)
2837 val &= ~WM_MISC_DATA_PARTITION_5_6;
2838 else
2839 val |= WM_MISC_DATA_PARTITION_5_6;
2840 I915_WRITE(WM_MISC, val);
2841 } else {
2842 val = I915_READ(DISP_ARB_CTL2);
2843 if (results->partitioning == INTEL_DDB_PART_1_2)
2844 val &= ~DISP_DATA_PARTITION_5_6;
2845 else
2846 val |= DISP_DATA_PARTITION_5_6;
2847 I915_WRITE(DISP_ARB_CTL2, val);
2848 }
2849 }
2850
2851 if (dirty & WM_DIRTY_FBC) {
2852 val = I915_READ(DISP_ARB_CTL);
2853 if (results->enable_fbc_wm)
2854 val &= ~DISP_FBC_WM_DIS;
2855 else
2856 val |= DISP_FBC_WM_DIS;
2857 I915_WRITE(DISP_ARB_CTL, val);
2858 }
2859
2860 if (dirty & WM_DIRTY_LP(1) &&
2861 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2862 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2863
2864 if (INTEL_GEN(dev_priv) >= 7) {
2865 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2866 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2867 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2868 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2869 }
2870
2871 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2872 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2873 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2874 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2875 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2876 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2877
2878 dev_priv->wm.hw = *results;
2879 }
2880
2881 bool ilk_disable_lp_wm(struct drm_device *dev)
2882 {
2883 struct drm_i915_private *dev_priv = to_i915(dev);
2884
2885 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2886 }
2887
2888 #define SKL_SAGV_BLOCK_TIME 30 /* µs */
2889
2890 /*
2891 * FIXME: We still don't have the proper code detect if we need to apply the WA,
2892 * so assume we'll always need it in order to avoid underruns.
2893 */
2894 static bool skl_needs_memory_bw_wa(struct intel_atomic_state *state)
2895 {
2896 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2897
2898 if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv) ||
2899 IS_KABYLAKE(dev_priv))
2900 return true;
2901
2902 return false;
2903 }
2904
2905 static bool
2906 intel_has_sagv(struct drm_i915_private *dev_priv)
2907 {
2908 if (IS_KABYLAKE(dev_priv))
2909 return true;
2910
2911 if (IS_SKYLAKE(dev_priv) &&
2912 dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED)
2913 return true;
2914
2915 return false;
2916 }
2917
2918 /*
2919 * SAGV dynamically adjusts the system agent voltage and clock frequencies
2920 * depending on power and performance requirements. The display engine access
2921 * to system memory is blocked during the adjustment time. Because of the
2922 * blocking time, having this enabled can cause full system hangs and/or pipe
2923 * underruns if we don't meet all of the following requirements:
2924 *
2925 * - <= 1 pipe enabled
2926 * - All planes can enable watermarks for latencies >= SAGV engine block time
2927 * - We're not using an interlaced display configuration
2928 */
2929 int
2930 intel_enable_sagv(struct drm_i915_private *dev_priv)
2931 {
2932 int ret;
2933
2934 if (!intel_has_sagv(dev_priv))
2935 return 0;
2936
2937 if (dev_priv->sagv_status == I915_SAGV_ENABLED)
2938 return 0;
2939
2940 DRM_DEBUG_KMS("Enabling the SAGV\n");
2941 mutex_lock(&dev_priv->rps.hw_lock);
2942
2943 ret = sandybridge_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL,
2944 GEN9_SAGV_ENABLE);
2945
2946 /* We don't need to wait for the SAGV when enabling */
2947 mutex_unlock(&dev_priv->rps.hw_lock);
2948
2949 /*
2950 * Some skl systems, pre-release machines in particular,
2951 * don't actually have an SAGV.
2952 */
2953 if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
2954 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
2955 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
2956 return 0;
2957 } else if (ret < 0) {
2958 DRM_ERROR("Failed to enable the SAGV\n");
2959 return ret;
2960 }
2961
2962 dev_priv->sagv_status = I915_SAGV_ENABLED;
2963 return 0;
2964 }
2965
2966 int
2967 intel_disable_sagv(struct drm_i915_private *dev_priv)
2968 {
2969 int ret;
2970
2971 if (!intel_has_sagv(dev_priv))
2972 return 0;
2973
2974 if (dev_priv->sagv_status == I915_SAGV_DISABLED)
2975 return 0;
2976
2977 DRM_DEBUG_KMS("Disabling the SAGV\n");
2978 mutex_lock(&dev_priv->rps.hw_lock);
2979
2980 /* bspec says to keep retrying for at least 1 ms */
2981 ret = skl_pcode_request(dev_priv, GEN9_PCODE_SAGV_CONTROL,
2982 GEN9_SAGV_DISABLE,
2983 GEN9_SAGV_IS_DISABLED, GEN9_SAGV_IS_DISABLED,
2984 1);
2985 mutex_unlock(&dev_priv->rps.hw_lock);
2986
2987 /*
2988 * Some skl systems, pre-release machines in particular,
2989 * don't actually have an SAGV.
2990 */
2991 if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
2992 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
2993 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
2994 return 0;
2995 } else if (ret < 0) {
2996 DRM_ERROR("Failed to disable the SAGV (%d)\n", ret);
2997 return ret;
2998 }
2999
3000 dev_priv->sagv_status = I915_SAGV_DISABLED;
3001 return 0;
3002 }
3003
3004 bool intel_can_enable_sagv(struct drm_atomic_state *state)
3005 {
3006 struct drm_device *dev = state->dev;
3007 struct drm_i915_private *dev_priv = to_i915(dev);
3008 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3009 struct intel_crtc *crtc;
3010 struct intel_plane *plane;
3011 struct intel_crtc_state *cstate;
3012 enum pipe pipe;
3013 int level, latency;
3014
3015 if (!intel_has_sagv(dev_priv))
3016 return false;
3017
3018 /*
3019 * SKL workaround: bspec recommends we disable the SAGV when we have
3020 * more then one pipe enabled
3021 *
3022 * If there are no active CRTCs, no additional checks need be performed
3023 */
3024 if (hweight32(intel_state->active_crtcs) == 0)
3025 return true;
3026 else if (hweight32(intel_state->active_crtcs) > 1)
3027 return false;
3028
3029 /* Since we're now guaranteed to only have one active CRTC... */
3030 pipe = ffs(intel_state->active_crtcs) - 1;
3031 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
3032 cstate = to_intel_crtc_state(crtc->base.state);
3033
3034 if (crtc->base.state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
3035 return false;
3036
3037 for_each_intel_plane_on_crtc(dev, crtc, plane) {
3038 struct skl_plane_wm *wm =
3039 &cstate->wm.skl.optimal.planes[plane->id];
3040
3041 /* Skip this plane if it's not enabled */
3042 if (!wm->wm[0].plane_en)
3043 continue;
3044
3045 /* Find the highest enabled wm level for this plane */
3046 for (level = ilk_wm_max_level(dev_priv);
3047 !wm->wm[level].plane_en; --level)
3048 { }
3049
3050 latency = dev_priv->wm.skl_latency[level];
3051
3052 if (skl_needs_memory_bw_wa(intel_state) &&
3053 plane->base.state->fb->modifier ==
3054 I915_FORMAT_MOD_X_TILED)
3055 latency += 15;
3056
3057 /*
3058 * If any of the planes on this pipe don't enable wm levels
3059 * that incur memory latencies higher then 30µs we can't enable
3060 * the SAGV
3061 */
3062 if (latency < SKL_SAGV_BLOCK_TIME)
3063 return false;
3064 }
3065
3066 return true;
3067 }
3068
3069 static void
3070 skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
3071 const struct intel_crtc_state *cstate,
3072 struct skl_ddb_entry *alloc, /* out */
3073 int *num_active /* out */)
3074 {
3075 struct drm_atomic_state *state = cstate->base.state;
3076 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3077 struct drm_i915_private *dev_priv = to_i915(dev);
3078 struct drm_crtc *for_crtc = cstate->base.crtc;
3079 unsigned int pipe_size, ddb_size;
3080 int nth_active_pipe;
3081
3082 if (WARN_ON(!state) || !cstate->base.active) {
3083 alloc->start = 0;
3084 alloc->end = 0;
3085 *num_active = hweight32(dev_priv->active_crtcs);
3086 return;
3087 }
3088
3089 if (intel_state->active_pipe_changes)
3090 *num_active = hweight32(intel_state->active_crtcs);
3091 else
3092 *num_active = hweight32(dev_priv->active_crtcs);
3093
3094 ddb_size = INTEL_INFO(dev_priv)->ddb_size;
3095 WARN_ON(ddb_size == 0);
3096
3097 ddb_size -= 4; /* 4 blocks for bypass path allocation */
3098
3099 /*
3100 * If the state doesn't change the active CRTC's, then there's
3101 * no need to recalculate; the existing pipe allocation limits
3102 * should remain unchanged. Note that we're safe from racing
3103 * commits since any racing commit that changes the active CRTC
3104 * list would need to grab _all_ crtc locks, including the one
3105 * we currently hold.
3106 */
3107 if (!intel_state->active_pipe_changes) {
3108 /*
3109 * alloc may be cleared by clear_intel_crtc_state,
3110 * copy from old state to be sure
3111 */
3112 *alloc = to_intel_crtc_state(for_crtc->state)->wm.skl.ddb;
3113 return;
3114 }
3115
3116 nth_active_pipe = hweight32(intel_state->active_crtcs &
3117 (drm_crtc_mask(for_crtc) - 1));
3118 pipe_size = ddb_size / hweight32(intel_state->active_crtcs);
3119 alloc->start = nth_active_pipe * ddb_size / *num_active;
3120 alloc->end = alloc->start + pipe_size;
3121 }
3122
3123 static unsigned int skl_cursor_allocation(int num_active)
3124 {
3125 if (num_active == 1)
3126 return 32;
3127
3128 return 8;
3129 }
3130
3131 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
3132 {
3133 entry->start = reg & 0x3ff;
3134 entry->end = (reg >> 16) & 0x3ff;
3135 if (entry->end)
3136 entry->end += 1;
3137 }
3138
3139 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
3140 struct skl_ddb_allocation *ddb /* out */)
3141 {
3142 struct intel_crtc *crtc;
3143
3144 memset(ddb, 0, sizeof(*ddb));
3145
3146 for_each_intel_crtc(&dev_priv->drm, crtc) {
3147 enum intel_display_power_domain power_domain;
3148 enum plane_id plane_id;
3149 enum pipe pipe = crtc->pipe;
3150
3151 power_domain = POWER_DOMAIN_PIPE(pipe);
3152 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
3153 continue;
3154
3155 for_each_plane_id_on_crtc(crtc, plane_id) {
3156 u32 val;
3157
3158 if (plane_id != PLANE_CURSOR)
3159 val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
3160 else
3161 val = I915_READ(CUR_BUF_CFG(pipe));
3162
3163 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane_id], val);
3164 }
3165
3166 intel_display_power_put(dev_priv, power_domain);
3167 }
3168 }
3169
3170 /*
3171 * Determines the downscale amount of a plane for the purposes of watermark calculations.
3172 * The bspec defines downscale amount as:
3173 *
3174 * """
3175 * Horizontal down scale amount = maximum[1, Horizontal source size /
3176 * Horizontal destination size]
3177 * Vertical down scale amount = maximum[1, Vertical source size /
3178 * Vertical destination size]
3179 * Total down scale amount = Horizontal down scale amount *
3180 * Vertical down scale amount
3181 * """
3182 *
3183 * Return value is provided in 16.16 fixed point form to retain fractional part.
3184 * Caller should take care of dividing & rounding off the value.
3185 */
3186 static uint32_t
3187 skl_plane_downscale_amount(const struct intel_plane_state *pstate)
3188 {
3189 uint32_t downscale_h, downscale_w;
3190 uint32_t src_w, src_h, dst_w, dst_h;
3191
3192 if (WARN_ON(!pstate->base.visible))
3193 return DRM_PLANE_HELPER_NO_SCALING;
3194
3195 /* n.b., src is 16.16 fixed point, dst is whole integer */
3196 src_w = drm_rect_width(&pstate->base.src);
3197 src_h = drm_rect_height(&pstate->base.src);
3198 dst_w = drm_rect_width(&pstate->base.dst);
3199 dst_h = drm_rect_height(&pstate->base.dst);
3200 if (drm_rotation_90_or_270(pstate->base.rotation))
3201 swap(dst_w, dst_h);
3202
3203 downscale_h = max(src_h / dst_h, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3204 downscale_w = max(src_w / dst_w, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3205
3206 /* Provide result in 16.16 fixed point */
3207 return (uint64_t)downscale_w * downscale_h >> 16;
3208 }
3209
3210 static unsigned int
3211 skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
3212 const struct drm_plane_state *pstate,
3213 int y)
3214 {
3215 struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
3216 uint32_t down_scale_amount, data_rate;
3217 uint32_t width = 0, height = 0;
3218 struct drm_framebuffer *fb;
3219 u32 format;
3220
3221 if (!intel_pstate->base.visible)
3222 return 0;
3223
3224 fb = pstate->fb;
3225 format = fb->format->format;
3226
3227 if (pstate->plane->type == DRM_PLANE_TYPE_CURSOR)
3228 return 0;
3229 if (y && format != DRM_FORMAT_NV12)
3230 return 0;
3231
3232 width = drm_rect_width(&intel_pstate->base.src) >> 16;
3233 height = drm_rect_height(&intel_pstate->base.src) >> 16;
3234
3235 if (drm_rotation_90_or_270(pstate->rotation))
3236 swap(width, height);
3237
3238 /* for planar format */
3239 if (format == DRM_FORMAT_NV12) {
3240 if (y) /* y-plane data rate */
3241 data_rate = width * height *
3242 fb->format->cpp[0];
3243 else /* uv-plane data rate */
3244 data_rate = (width / 2) * (height / 2) *
3245 fb->format->cpp[1];
3246 } else {
3247 /* for packed formats */
3248 data_rate = width * height * fb->format->cpp[0];
3249 }
3250
3251 down_scale_amount = skl_plane_downscale_amount(intel_pstate);
3252
3253 return (uint64_t)data_rate * down_scale_amount >> 16;
3254 }
3255
3256 /*
3257 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
3258 * a 8192x4096@32bpp framebuffer:
3259 * 3 * 4096 * 8192 * 4 < 2^32
3260 */
3261 static unsigned int
3262 skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate,
3263 unsigned *plane_data_rate,
3264 unsigned *plane_y_data_rate)
3265 {
3266 struct drm_crtc_state *cstate = &intel_cstate->base;
3267 struct drm_atomic_state *state = cstate->state;
3268 struct drm_plane *plane;
3269 const struct drm_plane_state *pstate;
3270 unsigned int total_data_rate = 0;
3271
3272 if (WARN_ON(!state))
3273 return 0;
3274
3275 /* Calculate and cache data rate for each plane */
3276 drm_atomic_crtc_state_for_each_plane_state(plane, pstate, cstate) {
3277 enum plane_id plane_id = to_intel_plane(plane)->id;
3278 unsigned int rate;
3279
3280 /* packed/uv */
3281 rate = skl_plane_relative_data_rate(intel_cstate,
3282 pstate, 0);
3283 plane_data_rate[plane_id] = rate;
3284
3285 total_data_rate += rate;
3286
3287 /* y-plane */
3288 rate = skl_plane_relative_data_rate(intel_cstate,
3289 pstate, 1);
3290 plane_y_data_rate[plane_id] = rate;
3291
3292 total_data_rate += rate;
3293 }
3294
3295 return total_data_rate;
3296 }
3297
3298 static uint16_t
3299 skl_ddb_min_alloc(const struct drm_plane_state *pstate,
3300 const int y)
3301 {
3302 struct drm_framebuffer *fb = pstate->fb;
3303 struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
3304 uint32_t src_w, src_h;
3305 uint32_t min_scanlines = 8;
3306 uint8_t plane_bpp;
3307
3308 if (WARN_ON(!fb))
3309 return 0;
3310
3311 /* For packed formats, no y-plane, return 0 */
3312 if (y && fb->format->format != DRM_FORMAT_NV12)
3313 return 0;
3314
3315 /* For Non Y-tile return 8-blocks */
3316 if (fb->modifier != I915_FORMAT_MOD_Y_TILED &&
3317 fb->modifier != I915_FORMAT_MOD_Yf_TILED)
3318 return 8;
3319
3320 src_w = drm_rect_width(&intel_pstate->base.src) >> 16;
3321 src_h = drm_rect_height(&intel_pstate->base.src) >> 16;
3322
3323 if (drm_rotation_90_or_270(pstate->rotation))
3324 swap(src_w, src_h);
3325
3326 /* Halve UV plane width and height for NV12 */
3327 if (fb->format->format == DRM_FORMAT_NV12 && !y) {
3328 src_w /= 2;
3329 src_h /= 2;
3330 }
3331
3332 if (fb->format->format == DRM_FORMAT_NV12 && !y)
3333 plane_bpp = fb->format->cpp[1];
3334 else
3335 plane_bpp = fb->format->cpp[0];
3336
3337 if (drm_rotation_90_or_270(pstate->rotation)) {
3338 switch (plane_bpp) {
3339 case 1:
3340 min_scanlines = 32;
3341 break;
3342 case 2:
3343 min_scanlines = 16;
3344 break;
3345 case 4:
3346 min_scanlines = 8;
3347 break;
3348 case 8:
3349 min_scanlines = 4;
3350 break;
3351 default:
3352 WARN(1, "Unsupported pixel depth %u for rotation",
3353 plane_bpp);
3354 min_scanlines = 32;
3355 }
3356 }
3357
3358 return DIV_ROUND_UP((4 * src_w * plane_bpp), 512) * min_scanlines/4 + 3;
3359 }
3360
3361 static void
3362 skl_ddb_calc_min(const struct intel_crtc_state *cstate, int num_active,
3363 uint16_t *minimum, uint16_t *y_minimum)
3364 {
3365 const struct drm_plane_state *pstate;
3366 struct drm_plane *plane;
3367
3368 drm_atomic_crtc_state_for_each_plane_state(plane, pstate, &cstate->base) {
3369 enum plane_id plane_id = to_intel_plane(plane)->id;
3370
3371 if (plane_id == PLANE_CURSOR)
3372 continue;
3373
3374 if (!pstate->visible)
3375 continue;
3376
3377 minimum[plane_id] = skl_ddb_min_alloc(pstate, 0);
3378 y_minimum[plane_id] = skl_ddb_min_alloc(pstate, 1);
3379 }
3380
3381 minimum[PLANE_CURSOR] = skl_cursor_allocation(num_active);
3382 }
3383
3384 static int
3385 skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
3386 struct skl_ddb_allocation *ddb /* out */)
3387 {
3388 struct drm_atomic_state *state = cstate->base.state;
3389 struct drm_crtc *crtc = cstate->base.crtc;
3390 struct drm_device *dev = crtc->dev;
3391 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3392 enum pipe pipe = intel_crtc->pipe;
3393 struct skl_ddb_entry *alloc = &cstate->wm.skl.ddb;
3394 uint16_t alloc_size, start;
3395 uint16_t minimum[I915_MAX_PLANES] = {};
3396 uint16_t y_minimum[I915_MAX_PLANES] = {};
3397 unsigned int total_data_rate;
3398 enum plane_id plane_id;
3399 int num_active;
3400 unsigned plane_data_rate[I915_MAX_PLANES] = {};
3401 unsigned plane_y_data_rate[I915_MAX_PLANES] = {};
3402
3403 /* Clear the partitioning for disabled planes. */
3404 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3405 memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe]));
3406
3407 if (WARN_ON(!state))
3408 return 0;
3409
3410 if (!cstate->base.active) {
3411 alloc->start = alloc->end = 0;
3412 return 0;
3413 }
3414
3415 skl_ddb_get_pipe_allocation_limits(dev, cstate, alloc, &num_active);
3416 alloc_size = skl_ddb_entry_size(alloc);
3417 if (alloc_size == 0) {
3418 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3419 return 0;
3420 }
3421
3422 skl_ddb_calc_min(cstate, num_active, minimum, y_minimum);
3423
3424 /*
3425 * 1. Allocate the mininum required blocks for each active plane
3426 * and allocate the cursor, it doesn't require extra allocation
3427 * proportional to the data rate.
3428 */
3429
3430 for_each_plane_id_on_crtc(intel_crtc, plane_id) {
3431 alloc_size -= minimum[plane_id];
3432 alloc_size -= y_minimum[plane_id];
3433 }
3434
3435 ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - minimum[PLANE_CURSOR];
3436 ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
3437
3438 /*
3439 * 2. Distribute the remaining space in proportion to the amount of
3440 * data each plane needs to fetch from memory.
3441 *
3442 * FIXME: we may not allocate every single block here.
3443 */
3444 total_data_rate = skl_get_total_relative_data_rate(cstate,
3445 plane_data_rate,
3446 plane_y_data_rate);
3447 if (total_data_rate == 0)
3448 return 0;
3449
3450 start = alloc->start;
3451 for_each_plane_id_on_crtc(intel_crtc, plane_id) {
3452 unsigned int data_rate, y_data_rate;
3453 uint16_t plane_blocks, y_plane_blocks = 0;
3454
3455 if (plane_id == PLANE_CURSOR)
3456 continue;
3457
3458 data_rate = plane_data_rate[plane_id];
3459
3460 /*
3461 * allocation for (packed formats) or (uv-plane part of planar format):
3462 * promote the expression to 64 bits to avoid overflowing, the
3463 * result is < available as data_rate / total_data_rate < 1
3464 */
3465 plane_blocks = minimum[plane_id];
3466 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3467 total_data_rate);
3468
3469 /* Leave disabled planes at (0,0) */
3470 if (data_rate) {
3471 ddb->plane[pipe][plane_id].start = start;
3472 ddb->plane[pipe][plane_id].end = start + plane_blocks;
3473 }
3474
3475 start += plane_blocks;
3476
3477 /*
3478 * allocation for y_plane part of planar format:
3479 */
3480 y_data_rate = plane_y_data_rate[plane_id];
3481
3482 y_plane_blocks = y_minimum[plane_id];
3483 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3484 total_data_rate);
3485
3486 if (y_data_rate) {
3487 ddb->y_plane[pipe][plane_id].start = start;
3488 ddb->y_plane[pipe][plane_id].end = start + y_plane_blocks;
3489 }
3490
3491 start += y_plane_blocks;
3492 }
3493
3494 return 0;
3495 }
3496
3497 /*
3498 * The max latency should be 257 (max the punit can code is 255 and we add 2us
3499 * for the read latency) and cpp should always be <= 8, so that
3500 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3501 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3502 */
3503 static uint_fixed_16_16_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp,
3504 uint32_t latency)
3505 {
3506 uint32_t wm_intermediate_val;
3507 uint_fixed_16_16_t ret;
3508
3509 if (latency == 0)
3510 return FP_16_16_MAX;
3511
3512 wm_intermediate_val = latency * pixel_rate * cpp;
3513 ret = fixed_16_16_div_round_up_u64(wm_intermediate_val, 1000 * 512);
3514 return ret;
3515 }
3516
3517 static uint_fixed_16_16_t skl_wm_method2(uint32_t pixel_rate,
3518 uint32_t pipe_htotal,
3519 uint32_t latency,
3520 uint_fixed_16_16_t plane_blocks_per_line)
3521 {
3522 uint32_t wm_intermediate_val;
3523 uint_fixed_16_16_t ret;
3524
3525 if (latency == 0)
3526 return FP_16_16_MAX;
3527
3528 wm_intermediate_val = latency * pixel_rate;
3529 wm_intermediate_val = DIV_ROUND_UP(wm_intermediate_val,
3530 pipe_htotal * 1000);
3531 ret = mul_u32_fixed_16_16(wm_intermediate_val, plane_blocks_per_line);
3532 return ret;
3533 }
3534
3535 static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate,
3536 struct intel_plane_state *pstate)
3537 {
3538 uint64_t adjusted_pixel_rate;
3539 uint64_t downscale_amount;
3540 uint64_t pixel_rate;
3541
3542 /* Shouldn't reach here on disabled planes... */
3543 if (WARN_ON(!pstate->base.visible))
3544 return 0;
3545
3546 /*
3547 * Adjusted plane pixel rate is just the pipe's adjusted pixel rate
3548 * with additional adjustments for plane-specific scaling.
3549 */
3550 adjusted_pixel_rate = ilk_pipe_pixel_rate(cstate);
3551 downscale_amount = skl_plane_downscale_amount(pstate);
3552
3553 pixel_rate = adjusted_pixel_rate * downscale_amount >> 16;
3554 WARN_ON(pixel_rate != clamp_t(uint32_t, pixel_rate, 0, ~0));
3555
3556 return pixel_rate;
3557 }
3558
3559 static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3560 struct intel_crtc_state *cstate,
3561 struct intel_plane_state *intel_pstate,
3562 uint16_t ddb_allocation,
3563 int level,
3564 uint16_t *out_blocks, /* out */
3565 uint8_t *out_lines, /* out */
3566 bool *enabled /* out */)
3567 {
3568 struct drm_plane_state *pstate = &intel_pstate->base;
3569 struct drm_framebuffer *fb = pstate->fb;
3570 uint32_t latency = dev_priv->wm.skl_latency[level];
3571 uint_fixed_16_16_t method1, method2;
3572 uint_fixed_16_16_t plane_blocks_per_line;
3573 uint_fixed_16_16_t selected_result;
3574 uint32_t interm_pbpl;
3575 uint32_t plane_bytes_per_line;
3576 uint32_t res_blocks, res_lines;
3577 uint8_t cpp;
3578 uint32_t width = 0, height = 0;
3579 uint32_t plane_pixel_rate;
3580 uint_fixed_16_16_t y_tile_minimum;
3581 uint32_t y_min_scanlines;
3582 struct intel_atomic_state *state =
3583 to_intel_atomic_state(cstate->base.state);
3584 bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state);
3585 bool y_tiled, x_tiled;
3586
3587 if (latency == 0 || !cstate->base.active || !intel_pstate->base.visible) {
3588 *enabled = false;
3589 return 0;
3590 }
3591
3592 y_tiled = fb->modifier == I915_FORMAT_MOD_Y_TILED ||
3593 fb->modifier == I915_FORMAT_MOD_Yf_TILED;
3594 x_tiled = fb->modifier == I915_FORMAT_MOD_X_TILED;
3595
3596 /* Display WA #1141: kbl. */
3597 if (IS_KABYLAKE(dev_priv) && dev_priv->ipc_enabled)
3598 latency += 4;
3599
3600 if (apply_memory_bw_wa && x_tiled)
3601 latency += 15;
3602
3603 width = drm_rect_width(&intel_pstate->base.src) >> 16;
3604 height = drm_rect_height(&intel_pstate->base.src) >> 16;
3605
3606 if (drm_rotation_90_or_270(pstate->rotation))
3607 swap(width, height);
3608
3609 cpp = fb->format->cpp[0];
3610 plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate, intel_pstate);
3611
3612 if (drm_rotation_90_or_270(pstate->rotation)) {
3613 int cpp = (fb->format->format == DRM_FORMAT_NV12) ?
3614 fb->format->cpp[1] :
3615 fb->format->cpp[0];
3616
3617 switch (cpp) {
3618 case 1:
3619 y_min_scanlines = 16;
3620 break;
3621 case 2:
3622 y_min_scanlines = 8;
3623 break;
3624 case 4:
3625 y_min_scanlines = 4;
3626 break;
3627 default:
3628 MISSING_CASE(cpp);
3629 return -EINVAL;
3630 }
3631 } else {
3632 y_min_scanlines = 4;
3633 }
3634
3635 if (apply_memory_bw_wa)
3636 y_min_scanlines *= 2;
3637
3638 plane_bytes_per_line = width * cpp;
3639 if (y_tiled) {
3640 interm_pbpl = DIV_ROUND_UP(plane_bytes_per_line *
3641 y_min_scanlines, 512);
3642 plane_blocks_per_line =
3643 fixed_16_16_div_round_up(interm_pbpl, y_min_scanlines);
3644 } else if (x_tiled) {
3645 interm_pbpl = DIV_ROUND_UP(plane_bytes_per_line, 512);
3646 plane_blocks_per_line = u32_to_fixed_16_16(interm_pbpl);
3647 } else {
3648 interm_pbpl = DIV_ROUND_UP(plane_bytes_per_line, 512) + 1;
3649 plane_blocks_per_line = u32_to_fixed_16_16(interm_pbpl);
3650 }
3651
3652 method1 = skl_wm_method1(plane_pixel_rate, cpp, latency);
3653 method2 = skl_wm_method2(plane_pixel_rate,
3654 cstate->base.adjusted_mode.crtc_htotal,
3655 latency,
3656 plane_blocks_per_line);
3657
3658 y_tile_minimum = mul_u32_fixed_16_16(y_min_scanlines,
3659 plane_blocks_per_line);
3660
3661 if (y_tiled) {
3662 selected_result = max_fixed_16_16(method2, y_tile_minimum);
3663 } else {
3664 if ((cpp * cstate->base.adjusted_mode.crtc_htotal / 512 < 1) &&
3665 (plane_bytes_per_line / 512 < 1))
3666 selected_result = method2;
3667 else if ((ddb_allocation /
3668 fixed_16_16_to_u32_round_up(plane_blocks_per_line)) >= 1)
3669 selected_result = min_fixed_16_16(method1, method2);
3670 else
3671 selected_result = method1;
3672 }
3673
3674 res_blocks = fixed_16_16_to_u32_round_up(selected_result) + 1;
3675 res_lines = DIV_ROUND_UP(selected_result.val,
3676 plane_blocks_per_line.val);
3677
3678 if (level >= 1 && level <= 7) {
3679 if (y_tiled) {
3680 res_blocks += fixed_16_16_to_u32_round_up(y_tile_minimum);
3681 res_lines += y_min_scanlines;
3682 } else {
3683 res_blocks++;
3684 }
3685 }
3686
3687 if (res_blocks >= ddb_allocation || res_lines > 31) {
3688 *enabled = false;
3689
3690 /*
3691 * If there are no valid level 0 watermarks, then we can't
3692 * support this display configuration.
3693 */
3694 if (level) {
3695 return 0;
3696 } else {
3697 struct drm_plane *plane = pstate->plane;
3698
3699 DRM_DEBUG_KMS("Requested display configuration exceeds system watermark limitations\n");
3700 DRM_DEBUG_KMS("[PLANE:%d:%s] blocks required = %u/%u, lines required = %u/31\n",
3701 plane->base.id, plane->name,
3702 res_blocks, ddb_allocation, res_lines);
3703 return -EINVAL;
3704 }
3705 }
3706
3707 *out_blocks = res_blocks;
3708 *out_lines = res_lines;
3709 *enabled = true;
3710
3711 return 0;
3712 }
3713
3714 static int
3715 skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3716 struct skl_ddb_allocation *ddb,
3717 struct intel_crtc_state *cstate,
3718 struct intel_plane *intel_plane,
3719 int level,
3720 struct skl_wm_level *result)
3721 {
3722 struct drm_atomic_state *state = cstate->base.state;
3723 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3724 struct drm_plane *plane = &intel_plane->base;
3725 struct intel_plane_state *intel_pstate = NULL;
3726 uint16_t ddb_blocks;
3727 enum pipe pipe = intel_crtc->pipe;
3728 int ret;
3729
3730 if (state)
3731 intel_pstate =
3732 intel_atomic_get_existing_plane_state(state,
3733 intel_plane);
3734
3735 /*
3736 * Note: If we start supporting multiple pending atomic commits against
3737 * the same planes/CRTC's in the future, plane->state will no longer be
3738 * the correct pre-state to use for the calculations here and we'll
3739 * need to change where we get the 'unchanged' plane data from.
3740 *
3741 * For now this is fine because we only allow one queued commit against
3742 * a CRTC. Even if the plane isn't modified by this transaction and we
3743 * don't have a plane lock, we still have the CRTC's lock, so we know
3744 * that no other transactions are racing with us to update it.
3745 */
3746 if (!intel_pstate)
3747 intel_pstate = to_intel_plane_state(plane->state);
3748
3749 WARN_ON(!intel_pstate->base.fb);
3750
3751 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][intel_plane->id]);
3752
3753 ret = skl_compute_plane_wm(dev_priv,
3754 cstate,
3755 intel_pstate,
3756 ddb_blocks,
3757 level,
3758 &result->plane_res_b,
3759 &result->plane_res_l,
3760 &result->plane_en);
3761 if (ret)
3762 return ret;
3763
3764 return 0;
3765 }
3766
3767 static uint32_t
3768 skl_compute_linetime_wm(struct intel_crtc_state *cstate)
3769 {
3770 struct drm_atomic_state *state = cstate->base.state;
3771 struct drm_i915_private *dev_priv = to_i915(state->dev);
3772 uint32_t pixel_rate;
3773 uint32_t linetime_wm;
3774
3775 if (!cstate->base.active)
3776 return 0;
3777
3778 pixel_rate = ilk_pipe_pixel_rate(cstate);
3779
3780 if (WARN_ON(pixel_rate == 0))
3781 return 0;
3782
3783 linetime_wm = DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal *
3784 1000, pixel_rate);
3785
3786 /* Display WA #1135: bxt. */
3787 if (IS_BROXTON(dev_priv) && dev_priv->ipc_enabled)
3788 linetime_wm = DIV_ROUND_UP(linetime_wm, 2);
3789
3790 return linetime_wm;
3791 }
3792
3793 static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
3794 struct skl_wm_level *trans_wm /* out */)
3795 {
3796 if (!cstate->base.active)
3797 return;
3798
3799 /* Until we know more, just disable transition WMs */
3800 trans_wm->plane_en = false;
3801 }
3802
3803 static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
3804 struct skl_ddb_allocation *ddb,
3805 struct skl_pipe_wm *pipe_wm)
3806 {
3807 struct drm_device *dev = cstate->base.crtc->dev;
3808 const struct drm_i915_private *dev_priv = to_i915(dev);
3809 struct intel_plane *intel_plane;
3810 struct skl_plane_wm *wm;
3811 int level, max_level = ilk_wm_max_level(dev_priv);
3812 int ret;
3813
3814 /*
3815 * We'll only calculate watermarks for planes that are actually
3816 * enabled, so make sure all other planes are set as disabled.
3817 */
3818 memset(pipe_wm->planes, 0, sizeof(pipe_wm->planes));
3819
3820 for_each_intel_plane_mask(&dev_priv->drm,
3821 intel_plane,
3822 cstate->base.plane_mask) {
3823 wm = &pipe_wm->planes[intel_plane->id];
3824
3825 for (level = 0; level <= max_level; level++) {
3826 ret = skl_compute_wm_level(dev_priv, ddb, cstate,
3827 intel_plane, level,
3828 &wm->wm[level]);
3829 if (ret)
3830 return ret;
3831 }
3832 skl_compute_transition_wm(cstate, &wm->trans_wm);
3833 }
3834 pipe_wm->linetime = skl_compute_linetime_wm(cstate);
3835
3836 return 0;
3837 }
3838
3839 static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
3840 i915_reg_t reg,
3841 const struct skl_ddb_entry *entry)
3842 {
3843 if (entry->end)
3844 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3845 else
3846 I915_WRITE(reg, 0);
3847 }
3848
3849 static void skl_write_wm_level(struct drm_i915_private *dev_priv,
3850 i915_reg_t reg,
3851 const struct skl_wm_level *level)
3852 {
3853 uint32_t val = 0;
3854
3855 if (level->plane_en) {
3856 val |= PLANE_WM_EN;
3857 val |= level->plane_res_b;
3858 val |= level->plane_res_l << PLANE_WM_LINES_SHIFT;
3859 }
3860
3861 I915_WRITE(reg, val);
3862 }
3863
3864 static void skl_write_plane_wm(struct intel_crtc *intel_crtc,
3865 const struct skl_plane_wm *wm,
3866 const struct skl_ddb_allocation *ddb,
3867 enum plane_id plane_id)
3868 {
3869 struct drm_crtc *crtc = &intel_crtc->base;
3870 struct drm_device *dev = crtc->dev;
3871 struct drm_i915_private *dev_priv = to_i915(dev);
3872 int level, max_level = ilk_wm_max_level(dev_priv);
3873 enum pipe pipe = intel_crtc->pipe;
3874
3875 for (level = 0; level <= max_level; level++) {
3876 skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane_id, level),
3877 &wm->wm[level]);
3878 }
3879 skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id),
3880 &wm->trans_wm);
3881
3882 skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id),
3883 &ddb->plane[pipe][plane_id]);
3884 skl_ddb_entry_write(dev_priv, PLANE_NV12_BUF_CFG(pipe, plane_id),
3885 &ddb->y_plane[pipe][plane_id]);
3886 }
3887
3888 static void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
3889 const struct skl_plane_wm *wm,
3890 const struct skl_ddb_allocation *ddb)
3891 {
3892 struct drm_crtc *crtc = &intel_crtc->base;
3893 struct drm_device *dev = crtc->dev;
3894 struct drm_i915_private *dev_priv = to_i915(dev);
3895 int level, max_level = ilk_wm_max_level(dev_priv);
3896 enum pipe pipe = intel_crtc->pipe;
3897
3898 for (level = 0; level <= max_level; level++) {
3899 skl_write_wm_level(dev_priv, CUR_WM(pipe, level),
3900 &wm->wm[level]);
3901 }
3902 skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe), &wm->trans_wm);
3903
3904 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3905 &ddb->plane[pipe][PLANE_CURSOR]);
3906 }
3907
3908 bool skl_wm_level_equals(const struct skl_wm_level *l1,
3909 const struct skl_wm_level *l2)
3910 {
3911 if (l1->plane_en != l2->plane_en)
3912 return false;
3913
3914 /* If both planes aren't enabled, the rest shouldn't matter */
3915 if (!l1->plane_en)
3916 return true;
3917
3918 return (l1->plane_res_l == l2->plane_res_l &&
3919 l1->plane_res_b == l2->plane_res_b);
3920 }
3921
3922 static inline bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a,
3923 const struct skl_ddb_entry *b)
3924 {
3925 return a->start < b->end && b->start < a->end;
3926 }
3927
3928 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry **entries,
3929 const struct skl_ddb_entry *ddb,
3930 int ignore)
3931 {
3932 int i;
3933
3934 for (i = 0; i < I915_MAX_PIPES; i++)
3935 if (i != ignore && entries[i] &&
3936 skl_ddb_entries_overlap(ddb, entries[i]))
3937 return true;
3938
3939 return false;
3940 }
3941
3942 static int skl_update_pipe_wm(struct drm_crtc_state *cstate,
3943 const struct skl_pipe_wm *old_pipe_wm,
3944 struct skl_pipe_wm *pipe_wm, /* out */
3945 struct skl_ddb_allocation *ddb, /* out */
3946 bool *changed /* out */)
3947 {
3948 struct intel_crtc_state *intel_cstate = to_intel_crtc_state(cstate);
3949 int ret;
3950
3951 ret = skl_build_pipe_wm(intel_cstate, ddb, pipe_wm);
3952 if (ret)
3953 return ret;
3954
3955 if (!memcmp(old_pipe_wm, pipe_wm, sizeof(*pipe_wm)))
3956 *changed = false;
3957 else
3958 *changed = true;
3959
3960 return 0;
3961 }
3962
3963 static uint32_t
3964 pipes_modified(struct drm_atomic_state *state)
3965 {
3966 struct drm_crtc *crtc;
3967 struct drm_crtc_state *cstate;
3968 uint32_t i, ret = 0;
3969
3970 for_each_crtc_in_state(state, crtc, cstate, i)
3971 ret |= drm_crtc_mask(crtc);
3972
3973 return ret;
3974 }
3975
3976 static int
3977 skl_ddb_add_affected_planes(struct intel_crtc_state *cstate)
3978 {
3979 struct drm_atomic_state *state = cstate->base.state;
3980 struct drm_device *dev = state->dev;
3981 struct drm_crtc *crtc = cstate->base.crtc;
3982 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3983 struct drm_i915_private *dev_priv = to_i915(dev);
3984 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3985 struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
3986 struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
3987 struct drm_plane_state *plane_state;
3988 struct drm_plane *plane;
3989 enum pipe pipe = intel_crtc->pipe;
3990
3991 WARN_ON(!drm_atomic_get_existing_crtc_state(state, crtc));
3992
3993 drm_for_each_plane_mask(plane, dev, cstate->base.plane_mask) {
3994 enum plane_id plane_id = to_intel_plane(plane)->id;
3995
3996 if (skl_ddb_entry_equal(&cur_ddb->plane[pipe][plane_id],
3997 &new_ddb->plane[pipe][plane_id]) &&
3998 skl_ddb_entry_equal(&cur_ddb->y_plane[pipe][plane_id],
3999 &new_ddb->y_plane[pipe][plane_id]))
4000 continue;
4001
4002 plane_state = drm_atomic_get_plane_state(state, plane);
4003 if (IS_ERR(plane_state))
4004 return PTR_ERR(plane_state);
4005 }
4006
4007 return 0;
4008 }
4009
4010 static int
4011 skl_compute_ddb(struct drm_atomic_state *state)
4012 {
4013 struct drm_device *dev = state->dev;
4014 struct drm_i915_private *dev_priv = to_i915(dev);
4015 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4016 struct intel_crtc *intel_crtc;
4017 struct skl_ddb_allocation *ddb = &intel_state->wm_results.ddb;
4018 uint32_t realloc_pipes = pipes_modified(state);
4019 int ret;
4020
4021 /*
4022 * If this is our first atomic update following hardware readout,
4023 * we can't trust the DDB that the BIOS programmed for us. Let's
4024 * pretend that all pipes switched active status so that we'll
4025 * ensure a full DDB recompute.
4026 */
4027 if (dev_priv->wm.distrust_bios_wm) {
4028 ret = drm_modeset_lock(&dev->mode_config.connection_mutex,
4029 state->acquire_ctx);
4030 if (ret)
4031 return ret;
4032
4033 intel_state->active_pipe_changes = ~0;
4034
4035 /*
4036 * We usually only initialize intel_state->active_crtcs if we
4037 * we're doing a modeset; make sure this field is always
4038 * initialized during the sanitization process that happens
4039 * on the first commit too.
4040 */
4041 if (!intel_state->modeset)
4042 intel_state->active_crtcs = dev_priv->active_crtcs;
4043 }
4044
4045 /*
4046 * If the modeset changes which CRTC's are active, we need to
4047 * recompute the DDB allocation for *all* active pipes, even
4048 * those that weren't otherwise being modified in any way by this
4049 * atomic commit. Due to the shrinking of the per-pipe allocations
4050 * when new active CRTC's are added, it's possible for a pipe that
4051 * we were already using and aren't changing at all here to suddenly
4052 * become invalid if its DDB needs exceeds its new allocation.
4053 *
4054 * Note that if we wind up doing a full DDB recompute, we can't let
4055 * any other display updates race with this transaction, so we need
4056 * to grab the lock on *all* CRTC's.
4057 */
4058 if (intel_state->active_pipe_changes) {
4059 realloc_pipes = ~0;
4060 intel_state->wm_results.dirty_pipes = ~0;
4061 }
4062
4063 /*
4064 * We're not recomputing for the pipes not included in the commit, so
4065 * make sure we start with the current state.
4066 */
4067 memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb));
4068
4069 for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
4070 struct intel_crtc_state *cstate;
4071
4072 cstate = intel_atomic_get_crtc_state(state, intel_crtc);
4073 if (IS_ERR(cstate))
4074 return PTR_ERR(cstate);
4075
4076 ret = skl_allocate_pipe_ddb(cstate, ddb);
4077 if (ret)
4078 return ret;
4079
4080 ret = skl_ddb_add_affected_planes(cstate);
4081 if (ret)
4082 return ret;
4083 }
4084
4085 return 0;
4086 }
4087
4088 static void
4089 skl_copy_wm_for_pipe(struct skl_wm_values *dst,
4090 struct skl_wm_values *src,
4091 enum pipe pipe)
4092 {
4093 memcpy(dst->ddb.y_plane[pipe], src->ddb.y_plane[pipe],
4094 sizeof(dst->ddb.y_plane[pipe]));
4095 memcpy(dst->ddb.plane[pipe], src->ddb.plane[pipe],
4096 sizeof(dst->ddb.plane[pipe]));
4097 }
4098
4099 static void
4100 skl_print_wm_changes(const struct drm_atomic_state *state)
4101 {
4102 const struct drm_device *dev = state->dev;
4103 const struct drm_i915_private *dev_priv = to_i915(dev);
4104 const struct intel_atomic_state *intel_state =
4105 to_intel_atomic_state(state);
4106 const struct drm_crtc *crtc;
4107 const struct drm_crtc_state *cstate;
4108 const struct intel_plane *intel_plane;
4109 const struct skl_ddb_allocation *old_ddb = &dev_priv->wm.skl_hw.ddb;
4110 const struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
4111 int i;
4112
4113 for_each_crtc_in_state(state, crtc, cstate, i) {
4114 const struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4115 enum pipe pipe = intel_crtc->pipe;
4116
4117 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
4118 enum plane_id plane_id = intel_plane->id;
4119 const struct skl_ddb_entry *old, *new;
4120
4121 old = &old_ddb->plane[pipe][plane_id];
4122 new = &new_ddb->plane[pipe][plane_id];
4123
4124 if (skl_ddb_entry_equal(old, new))
4125 continue;
4126
4127 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] ddb (%d - %d) -> (%d - %d)\n",
4128 intel_plane->base.base.id,
4129 intel_plane->base.name,
4130 old->start, old->end,
4131 new->start, new->end);
4132 }
4133 }
4134 }
4135
4136 static int
4137 skl_compute_wm(struct drm_atomic_state *state)
4138 {
4139 struct drm_crtc *crtc;
4140 struct drm_crtc_state *cstate;
4141 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4142 struct skl_wm_values *results = &intel_state->wm_results;
4143 struct skl_pipe_wm *pipe_wm;
4144 bool changed = false;
4145 int ret, i;
4146
4147 /*
4148 * If this transaction isn't actually touching any CRTC's, don't
4149 * bother with watermark calculation. Note that if we pass this
4150 * test, we're guaranteed to hold at least one CRTC state mutex,
4151 * which means we can safely use values like dev_priv->active_crtcs
4152 * since any racing commits that want to update them would need to
4153 * hold _all_ CRTC state mutexes.
4154 */
4155 for_each_crtc_in_state(state, crtc, cstate, i)
4156 changed = true;
4157 if (!changed)
4158 return 0;
4159
4160 /* Clear all dirty flags */
4161 results->dirty_pipes = 0;
4162
4163 ret = skl_compute_ddb(state);
4164 if (ret)
4165 return ret;
4166
4167 /*
4168 * Calculate WM's for all pipes that are part of this transaction.
4169 * Note that the DDB allocation above may have added more CRTC's that
4170 * weren't otherwise being modified (and set bits in dirty_pipes) if
4171 * pipe allocations had to change.
4172 *
4173 * FIXME: Now that we're doing this in the atomic check phase, we
4174 * should allow skl_update_pipe_wm() to return failure in cases where
4175 * no suitable watermark values can be found.
4176 */
4177 for_each_crtc_in_state(state, crtc, cstate, i) {
4178 struct intel_crtc_state *intel_cstate =
4179 to_intel_crtc_state(cstate);
4180 const struct skl_pipe_wm *old_pipe_wm =
4181 &to_intel_crtc_state(crtc->state)->wm.skl.optimal;
4182
4183 pipe_wm = &intel_cstate->wm.skl.optimal;
4184 ret = skl_update_pipe_wm(cstate, old_pipe_wm, pipe_wm,
4185 &results->ddb, &changed);
4186 if (ret)
4187 return ret;
4188
4189 if (changed)
4190 results->dirty_pipes |= drm_crtc_mask(crtc);
4191
4192 if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
4193 /* This pipe's WM's did not change */
4194 continue;
4195
4196 intel_cstate->update_wm_pre = true;
4197 }
4198
4199 skl_print_wm_changes(state);
4200
4201 return 0;
4202 }
4203
4204 static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
4205 struct intel_crtc_state *cstate)
4206 {
4207 struct intel_crtc *crtc = to_intel_crtc(cstate->base.crtc);
4208 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
4209 struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
4210 const struct skl_ddb_allocation *ddb = &state->wm_results.ddb;
4211 enum pipe pipe = crtc->pipe;
4212 enum plane_id plane_id;
4213
4214 if (!(state->wm_results.dirty_pipes & drm_crtc_mask(&crtc->base)))
4215 return;
4216
4217 I915_WRITE(PIPE_WM_LINETIME(pipe), pipe_wm->linetime);
4218
4219 for_each_plane_id_on_crtc(crtc, plane_id) {
4220 if (plane_id != PLANE_CURSOR)
4221 skl_write_plane_wm(crtc, &pipe_wm->planes[plane_id],
4222 ddb, plane_id);
4223 else
4224 skl_write_cursor_wm(crtc, &pipe_wm->planes[plane_id],
4225 ddb);
4226 }
4227 }
4228
4229 static void skl_initial_wm(struct intel_atomic_state *state,
4230 struct intel_crtc_state *cstate)
4231 {
4232 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
4233 struct drm_device *dev = intel_crtc->base.dev;
4234 struct drm_i915_private *dev_priv = to_i915(dev);
4235 struct skl_wm_values *results = &state->wm_results;
4236 struct skl_wm_values *hw_vals = &dev_priv->wm.skl_hw;
4237 enum pipe pipe = intel_crtc->pipe;
4238
4239 if ((results->dirty_pipes & drm_crtc_mask(&intel_crtc->base)) == 0)
4240 return;
4241
4242 mutex_lock(&dev_priv->wm.wm_mutex);
4243
4244 if (cstate->base.active_changed)
4245 skl_atomic_update_crtc_wm(state, cstate);
4246
4247 skl_copy_wm_for_pipe(hw_vals, results, pipe);
4248
4249 mutex_unlock(&dev_priv->wm.wm_mutex);
4250 }
4251
4252 static void ilk_compute_wm_config(struct drm_device *dev,
4253 struct intel_wm_config *config)
4254 {
4255 struct intel_crtc *crtc;
4256
4257 /* Compute the currently _active_ config */
4258 for_each_intel_crtc(dev, crtc) {
4259 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
4260
4261 if (!wm->pipe_enabled)
4262 continue;
4263
4264 config->sprites_enabled |= wm->sprites_enabled;
4265 config->sprites_scaled |= wm->sprites_scaled;
4266 config->num_pipes_active++;
4267 }
4268 }
4269
4270 static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
4271 {
4272 struct drm_device *dev = &dev_priv->drm;
4273 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
4274 struct ilk_wm_maximums max;
4275 struct intel_wm_config config = {};
4276 struct ilk_wm_values results = {};
4277 enum intel_ddb_partitioning partitioning;
4278
4279 ilk_compute_wm_config(dev, &config);
4280
4281 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
4282 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
4283
4284 /* 5/6 split only in single pipe config on IVB+ */
4285 if (INTEL_GEN(dev_priv) >= 7 &&
4286 config.num_pipes_active == 1 && config.sprites_enabled) {
4287 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
4288 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
4289
4290 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
4291 } else {
4292 best_lp_wm = &lp_wm_1_2;
4293 }
4294
4295 partitioning = (best_lp_wm == &lp_wm_1_2) ?
4296 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
4297
4298 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
4299
4300 ilk_write_wm_values(dev_priv, &results);
4301 }
4302
4303 static void ilk_initial_watermarks(struct intel_atomic_state *state,
4304 struct intel_crtc_state *cstate)
4305 {
4306 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4307 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
4308
4309 mutex_lock(&dev_priv->wm.wm_mutex);
4310 intel_crtc->wm.active.ilk = cstate->wm.ilk.intermediate;
4311 ilk_program_watermarks(dev_priv);
4312 mutex_unlock(&dev_priv->wm.wm_mutex);
4313 }
4314
4315 static void ilk_optimize_watermarks(struct intel_atomic_state *state,
4316 struct intel_crtc_state *cstate)
4317 {
4318 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4319 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
4320
4321 mutex_lock(&dev_priv->wm.wm_mutex);
4322 if (cstate->wm.need_postvbl_update) {
4323 intel_crtc->wm.active.ilk = cstate->wm.ilk.optimal;
4324 ilk_program_watermarks(dev_priv);
4325 }
4326 mutex_unlock(&dev_priv->wm.wm_mutex);
4327 }
4328
4329 static inline void skl_wm_level_from_reg_val(uint32_t val,
4330 struct skl_wm_level *level)
4331 {
4332 level->plane_en = val & PLANE_WM_EN;
4333 level->plane_res_b = val & PLANE_WM_BLOCKS_MASK;
4334 level->plane_res_l = (val >> PLANE_WM_LINES_SHIFT) &
4335 PLANE_WM_LINES_MASK;
4336 }
4337
4338 void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
4339 struct skl_pipe_wm *out)
4340 {
4341 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
4342 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4343 enum pipe pipe = intel_crtc->pipe;
4344 int level, max_level;
4345 enum plane_id plane_id;
4346 uint32_t val;
4347
4348 max_level = ilk_wm_max_level(dev_priv);
4349
4350 for_each_plane_id_on_crtc(intel_crtc, plane_id) {
4351 struct skl_plane_wm *wm = &out->planes[plane_id];
4352
4353 for (level = 0; level <= max_level; level++) {
4354 if (plane_id != PLANE_CURSOR)
4355 val = I915_READ(PLANE_WM(pipe, plane_id, level));
4356 else
4357 val = I915_READ(CUR_WM(pipe, level));
4358
4359 skl_wm_level_from_reg_val(val, &wm->wm[level]);
4360 }
4361
4362 if (plane_id != PLANE_CURSOR)
4363 val = I915_READ(PLANE_WM_TRANS(pipe, plane_id));
4364 else
4365 val = I915_READ(CUR_WM_TRANS(pipe));
4366
4367 skl_wm_level_from_reg_val(val, &wm->trans_wm);
4368 }
4369
4370 if (!intel_crtc->active)
4371 return;
4372
4373 out->linetime = I915_READ(PIPE_WM_LINETIME(pipe));
4374 }
4375
4376 void skl_wm_get_hw_state(struct drm_device *dev)
4377 {
4378 struct drm_i915_private *dev_priv = to_i915(dev);
4379 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
4380 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
4381 struct drm_crtc *crtc;
4382 struct intel_crtc *intel_crtc;
4383 struct intel_crtc_state *cstate;
4384
4385 skl_ddb_get_hw_state(dev_priv, ddb);
4386 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4387 intel_crtc = to_intel_crtc(crtc);
4388 cstate = to_intel_crtc_state(crtc->state);
4389
4390 skl_pipe_wm_get_hw_state(crtc, &cstate->wm.skl.optimal);
4391
4392 if (intel_crtc->active)
4393 hw->dirty_pipes |= drm_crtc_mask(crtc);
4394 }
4395
4396 if (dev_priv->active_crtcs) {
4397 /* Fully recompute DDB on first atomic commit */
4398 dev_priv->wm.distrust_bios_wm = true;
4399 } else {
4400 /* Easy/common case; just sanitize DDB now if everything off */
4401 memset(ddb, 0, sizeof(*ddb));
4402 }
4403 }
4404
4405 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
4406 {
4407 struct drm_device *dev = crtc->dev;
4408 struct drm_i915_private *dev_priv = to_i915(dev);
4409 struct ilk_wm_values *hw = &dev_priv->wm.hw;
4410 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4411 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
4412 struct intel_pipe_wm *active = &cstate->wm.ilk.optimal;
4413 enum pipe pipe = intel_crtc->pipe;
4414 static const i915_reg_t wm0_pipe_reg[] = {
4415 [PIPE_A] = WM0_PIPEA_ILK,
4416 [PIPE_B] = WM0_PIPEB_ILK,
4417 [PIPE_C] = WM0_PIPEC_IVB,
4418 };
4419
4420 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
4421 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
4422 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
4423
4424 memset(active, 0, sizeof(*active));
4425
4426 active->pipe_enabled = intel_crtc->active;
4427
4428 if (active->pipe_enabled) {
4429 u32 tmp = hw->wm_pipe[pipe];
4430
4431 /*
4432 * For active pipes LP0 watermark is marked as
4433 * enabled, and LP1+ watermaks as disabled since
4434 * we can't really reverse compute them in case
4435 * multiple pipes are active.
4436 */
4437 active->wm[0].enable = true;
4438 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
4439 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
4440 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
4441 active->linetime = hw->wm_linetime[pipe];
4442 } else {
4443 int level, max_level = ilk_wm_max_level(dev_priv);
4444
4445 /*
4446 * For inactive pipes, all watermark levels
4447 * should be marked as enabled but zeroed,
4448 * which is what we'd compute them to.
4449 */
4450 for (level = 0; level <= max_level; level++)
4451 active->wm[level].enable = true;
4452 }
4453
4454 intel_crtc->wm.active.ilk = *active;
4455 }
4456
4457 #define _FW_WM(value, plane) \
4458 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
4459 #define _FW_WM_VLV(value, plane) \
4460 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
4461
4462 static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
4463 struct vlv_wm_values *wm)
4464 {
4465 enum pipe pipe;
4466 uint32_t tmp;
4467
4468 for_each_pipe(dev_priv, pipe) {
4469 tmp = I915_READ(VLV_DDL(pipe));
4470
4471 wm->ddl[pipe].plane[PLANE_PRIMARY] =
4472 (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4473 wm->ddl[pipe].plane[PLANE_CURSOR] =
4474 (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4475 wm->ddl[pipe].plane[PLANE_SPRITE0] =
4476 (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4477 wm->ddl[pipe].plane[PLANE_SPRITE1] =
4478 (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4479 }
4480
4481 tmp = I915_READ(DSPFW1);
4482 wm->sr.plane = _FW_WM(tmp, SR);
4483 wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB);
4484 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEB);
4485 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEA);
4486
4487 tmp = I915_READ(DSPFW2);
4488 wm->pipe[PIPE_A].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEB);
4489 wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA);
4490 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEA);
4491
4492 tmp = I915_READ(DSPFW3);
4493 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
4494
4495 if (IS_CHERRYVIEW(dev_priv)) {
4496 tmp = I915_READ(DSPFW7_CHV);
4497 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED);
4498 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC);
4499
4500 tmp = I915_READ(DSPFW8_CHV);
4501 wm->pipe[PIPE_C].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEF);
4502 wm->pipe[PIPE_C].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEE);
4503
4504 tmp = I915_READ(DSPFW9_CHV);
4505 wm->pipe[PIPE_C].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEC);
4506 wm->pipe[PIPE_C].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORC);
4507
4508 tmp = I915_READ(DSPHOWM);
4509 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4510 wm->pipe[PIPE_C].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
4511 wm->pipe[PIPE_C].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
4512 wm->pipe[PIPE_C].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEC_HI) << 8;
4513 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4514 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4515 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8;
4516 wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4517 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4518 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8;
4519 } else {
4520 tmp = I915_READ(DSPFW7);
4521 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED);
4522 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC);
4523
4524 tmp = I915_READ(DSPHOWM);
4525 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4526 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4527 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4528 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8;
4529 wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4530 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4531 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8;
4532 }
4533 }
4534
4535 #undef _FW_WM
4536 #undef _FW_WM_VLV
4537
4538 void vlv_wm_get_hw_state(struct drm_device *dev)
4539 {
4540 struct drm_i915_private *dev_priv = to_i915(dev);
4541 struct vlv_wm_values *wm = &dev_priv->wm.vlv;
4542 struct intel_plane *plane;
4543 enum pipe pipe;
4544 u32 val;
4545
4546 vlv_read_wm_values(dev_priv, wm);
4547
4548 for_each_intel_plane(dev, plane)
4549 plane->wm.fifo_size = vlv_get_fifo_size(plane);
4550
4551 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4552 wm->level = VLV_WM_LEVEL_PM2;
4553
4554 if (IS_CHERRYVIEW(dev_priv)) {
4555 mutex_lock(&dev_priv->rps.hw_lock);
4556
4557 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4558 if (val & DSP_MAXFIFO_PM5_ENABLE)
4559 wm->level = VLV_WM_LEVEL_PM5;
4560
4561 /*
4562 * If DDR DVFS is disabled in the BIOS, Punit
4563 * will never ack the request. So if that happens
4564 * assume we don't have to enable/disable DDR DVFS
4565 * dynamically. To test that just set the REQ_ACK
4566 * bit to poke the Punit, but don't change the
4567 * HIGH/LOW bits so that we don't actually change
4568 * the current state.
4569 */
4570 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4571 val |= FORCE_DDR_FREQ_REQ_ACK;
4572 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
4573
4574 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4575 FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4576 DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4577 "assuming DDR DVFS is disabled\n");
4578 dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4579 } else {
4580 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4581 if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4582 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4583 }
4584
4585 mutex_unlock(&dev_priv->rps.hw_lock);
4586 }
4587
4588 for_each_pipe(dev_priv, pipe)
4589 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4590 pipe_name(pipe),
4591 wm->pipe[pipe].plane[PLANE_PRIMARY],
4592 wm->pipe[pipe].plane[PLANE_CURSOR],
4593 wm->pipe[pipe].plane[PLANE_SPRITE0],
4594 wm->pipe[pipe].plane[PLANE_SPRITE1]);
4595
4596 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4597 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4598 }
4599
4600 void ilk_wm_get_hw_state(struct drm_device *dev)
4601 {
4602 struct drm_i915_private *dev_priv = to_i915(dev);
4603 struct ilk_wm_values *hw = &dev_priv->wm.hw;
4604 struct drm_crtc *crtc;
4605
4606 for_each_crtc(dev, crtc)
4607 ilk_pipe_wm_get_hw_state(crtc);
4608
4609 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4610 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4611 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4612
4613 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
4614 if (INTEL_GEN(dev_priv) >= 7) {
4615 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4616 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4617 }
4618
4619 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
4620 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4621 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4622 else if (IS_IVYBRIDGE(dev_priv))
4623 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4624 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4625
4626 hw->enable_fbc_wm =
4627 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4628 }
4629
4630 /**
4631 * intel_update_watermarks - update FIFO watermark values based on current modes
4632 *
4633 * Calculate watermark values for the various WM regs based on current mode
4634 * and plane configuration.
4635 *
4636 * There are several cases to deal with here:
4637 * - normal (i.e. non-self-refresh)
4638 * - self-refresh (SR) mode
4639 * - lines are large relative to FIFO size (buffer can hold up to 2)
4640 * - lines are small relative to FIFO size (buffer can hold more than 2
4641 * lines), so need to account for TLB latency
4642 *
4643 * The normal calculation is:
4644 * watermark = dotclock * bytes per pixel * latency
4645 * where latency is platform & configuration dependent (we assume pessimal
4646 * values here).
4647 *
4648 * The SR calculation is:
4649 * watermark = (trunc(latency/line time)+1) * surface width *
4650 * bytes per pixel
4651 * where
4652 * line time = htotal / dotclock
4653 * surface width = hdisplay for normal plane and 64 for cursor
4654 * and latency is assumed to be high, as above.
4655 *
4656 * The final value programmed to the register should always be rounded up,
4657 * and include an extra 2 entries to account for clock crossings.
4658 *
4659 * We don't use the sprite, so we can ignore that. And on Crestline we have
4660 * to set the non-SR watermarks to 8.
4661 */
4662 void intel_update_watermarks(struct intel_crtc *crtc)
4663 {
4664 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4665
4666 if (dev_priv->display.update_wm)
4667 dev_priv->display.update_wm(crtc);
4668 }
4669
4670 /*
4671 * Lock protecting IPS related data structures
4672 */
4673 DEFINE_SPINLOCK(mchdev_lock);
4674
4675 /* Global for IPS driver to get at the current i915 device. Protected by
4676 * mchdev_lock. */
4677 static struct drm_i915_private *i915_mch_dev;
4678
4679 bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val)
4680 {
4681 u16 rgvswctl;
4682
4683 assert_spin_locked(&mchdev_lock);
4684
4685 rgvswctl = I915_READ16(MEMSWCTL);
4686 if (rgvswctl & MEMCTL_CMD_STS) {
4687 DRM_DEBUG("gpu busy, RCS change rejected\n");
4688 return false; /* still busy with another command */
4689 }
4690
4691 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4692 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4693 I915_WRITE16(MEMSWCTL, rgvswctl);
4694 POSTING_READ16(MEMSWCTL);
4695
4696 rgvswctl |= MEMCTL_CMD_STS;
4697 I915_WRITE16(MEMSWCTL, rgvswctl);
4698
4699 return true;
4700 }
4701
4702 static void ironlake_enable_drps(struct drm_i915_private *dev_priv)
4703 {
4704 u32 rgvmodectl;
4705 u8 fmax, fmin, fstart, vstart;
4706
4707 spin_lock_irq(&mchdev_lock);
4708
4709 rgvmodectl = I915_READ(MEMMODECTL);
4710
4711 /* Enable temp reporting */
4712 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4713 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4714
4715 /* 100ms RC evaluation intervals */
4716 I915_WRITE(RCUPEI, 100000);
4717 I915_WRITE(RCDNEI, 100000);
4718
4719 /* Set max/min thresholds to 90ms and 80ms respectively */
4720 I915_WRITE(RCBMAXAVG, 90000);
4721 I915_WRITE(RCBMINAVG, 80000);
4722
4723 I915_WRITE(MEMIHYST, 1);
4724
4725 /* Set up min, max, and cur for interrupt handling */
4726 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4727 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4728 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4729 MEMMODE_FSTART_SHIFT;
4730
4731 vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
4732 PXVFREQ_PX_SHIFT;
4733
4734 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4735 dev_priv->ips.fstart = fstart;
4736
4737 dev_priv->ips.max_delay = fstart;
4738 dev_priv->ips.min_delay = fmin;
4739 dev_priv->ips.cur_delay = fstart;
4740
4741 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4742 fmax, fmin, fstart);
4743
4744 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4745
4746 /*
4747 * Interrupts will be enabled in ironlake_irq_postinstall
4748 */
4749
4750 I915_WRITE(VIDSTART, vstart);
4751 POSTING_READ(VIDSTART);
4752
4753 rgvmodectl |= MEMMODE_SWMODE_EN;
4754 I915_WRITE(MEMMODECTL, rgvmodectl);
4755
4756 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
4757 DRM_ERROR("stuck trying to change perf mode\n");
4758 mdelay(1);
4759
4760 ironlake_set_drps(dev_priv, fstart);
4761
4762 dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4763 I915_READ(DDREC) + I915_READ(CSIEC);
4764 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
4765 dev_priv->ips.last_count2 = I915_READ(GFXEC);
4766 dev_priv->ips.last_time2 = ktime_get_raw_ns();
4767
4768 spin_unlock_irq(&mchdev_lock);
4769 }
4770
4771 static void ironlake_disable_drps(struct drm_i915_private *dev_priv)
4772 {
4773 u16 rgvswctl;
4774
4775 spin_lock_irq(&mchdev_lock);
4776
4777 rgvswctl = I915_READ16(MEMSWCTL);
4778
4779 /* Ack interrupts, disable EFC interrupt */
4780 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4781 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4782 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4783 I915_WRITE(DEIIR, DE_PCU_EVENT);
4784 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4785
4786 /* Go back to the starting frequency */
4787 ironlake_set_drps(dev_priv, dev_priv->ips.fstart);
4788 mdelay(1);
4789 rgvswctl |= MEMCTL_CMD_STS;
4790 I915_WRITE(MEMSWCTL, rgvswctl);
4791 mdelay(1);
4792
4793 spin_unlock_irq(&mchdev_lock);
4794 }
4795
4796 /* There's a funny hw issue where the hw returns all 0 when reading from
4797 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4798 * ourselves, instead of doing a rmw cycle (which might result in us clearing
4799 * all limits and the gpu stuck at whatever frequency it is at atm).
4800 */
4801 static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
4802 {
4803 u32 limits;
4804
4805 /* Only set the down limit when we've reached the lowest level to avoid
4806 * getting more interrupts, otherwise leave this clear. This prevents a
4807 * race in the hw when coming out of rc6: There's a tiny window where
4808 * the hw runs at the minimal clock before selecting the desired
4809 * frequency, if the down threshold expires in that window we will not
4810 * receive a down interrupt. */
4811 if (IS_GEN9(dev_priv)) {
4812 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4813 if (val <= dev_priv->rps.min_freq_softlimit)
4814 limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4815 } else {
4816 limits = dev_priv->rps.max_freq_softlimit << 24;
4817 if (val <= dev_priv->rps.min_freq_softlimit)
4818 limits |= dev_priv->rps.min_freq_softlimit << 16;
4819 }
4820
4821 return limits;
4822 }
4823
4824 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4825 {
4826 int new_power;
4827 u32 threshold_up = 0, threshold_down = 0; /* in % */
4828 u32 ei_up = 0, ei_down = 0;
4829
4830 new_power = dev_priv->rps.power;
4831 switch (dev_priv->rps.power) {
4832 case LOW_POWER:
4833 if (val > dev_priv->rps.efficient_freq + 1 &&
4834 val > dev_priv->rps.cur_freq)
4835 new_power = BETWEEN;
4836 break;
4837
4838 case BETWEEN:
4839 if (val <= dev_priv->rps.efficient_freq &&
4840 val < dev_priv->rps.cur_freq)
4841 new_power = LOW_POWER;
4842 else if (val >= dev_priv->rps.rp0_freq &&
4843 val > dev_priv->rps.cur_freq)
4844 new_power = HIGH_POWER;
4845 break;
4846
4847 case HIGH_POWER:
4848 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 &&
4849 val < dev_priv->rps.cur_freq)
4850 new_power = BETWEEN;
4851 break;
4852 }
4853 /* Max/min bins are special */
4854 if (val <= dev_priv->rps.min_freq_softlimit)
4855 new_power = LOW_POWER;
4856 if (val >= dev_priv->rps.max_freq_softlimit)
4857 new_power = HIGH_POWER;
4858 if (new_power == dev_priv->rps.power)
4859 return;
4860
4861 /* Note the units here are not exactly 1us, but 1280ns. */
4862 switch (new_power) {
4863 case LOW_POWER:
4864 /* Upclock if more than 95% busy over 16ms */
4865 ei_up = 16000;
4866 threshold_up = 95;
4867
4868 /* Downclock if less than 85% busy over 32ms */
4869 ei_down = 32000;
4870 threshold_down = 85;
4871 break;
4872
4873 case BETWEEN:
4874 /* Upclock if more than 90% busy over 13ms */
4875 ei_up = 13000;
4876 threshold_up = 90;
4877
4878 /* Downclock if less than 75% busy over 32ms */
4879 ei_down = 32000;
4880 threshold_down = 75;
4881 break;
4882
4883 case HIGH_POWER:
4884 /* Upclock if more than 85% busy over 10ms */
4885 ei_up = 10000;
4886 threshold_up = 85;
4887
4888 /* Downclock if less than 60% busy over 32ms */
4889 ei_down = 32000;
4890 threshold_down = 60;
4891 break;
4892 }
4893
4894 /* When byt can survive without system hang with dynamic
4895 * sw freq adjustments, this restriction can be lifted.
4896 */
4897 if (IS_VALLEYVIEW(dev_priv))
4898 goto skip_hw_write;
4899
4900 I915_WRITE(GEN6_RP_UP_EI,
4901 GT_INTERVAL_FROM_US(dev_priv, ei_up));
4902 I915_WRITE(GEN6_RP_UP_THRESHOLD,
4903 GT_INTERVAL_FROM_US(dev_priv,
4904 ei_up * threshold_up / 100));
4905
4906 I915_WRITE(GEN6_RP_DOWN_EI,
4907 GT_INTERVAL_FROM_US(dev_priv, ei_down));
4908 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4909 GT_INTERVAL_FROM_US(dev_priv,
4910 ei_down * threshold_down / 100));
4911
4912 I915_WRITE(GEN6_RP_CONTROL,
4913 GEN6_RP_MEDIA_TURBO |
4914 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4915 GEN6_RP_MEDIA_IS_GFX |
4916 GEN6_RP_ENABLE |
4917 GEN6_RP_UP_BUSY_AVG |
4918 GEN6_RP_DOWN_IDLE_AVG);
4919
4920 skip_hw_write:
4921 dev_priv->rps.power = new_power;
4922 dev_priv->rps.up_threshold = threshold_up;
4923 dev_priv->rps.down_threshold = threshold_down;
4924 dev_priv->rps.last_adj = 0;
4925 }
4926
4927 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4928 {
4929 u32 mask = 0;
4930
4931 /* We use UP_EI_EXPIRED interupts for both up/down in manual mode */
4932 if (val > dev_priv->rps.min_freq_softlimit)
4933 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
4934 if (val < dev_priv->rps.max_freq_softlimit)
4935 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
4936
4937 mask &= dev_priv->pm_rps_events;
4938
4939 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
4940 }
4941
4942 /* gen6_set_rps is called to update the frequency request, but should also be
4943 * called when the range (min_delay and max_delay) is modified so that we can
4944 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
4945 static void gen6_set_rps(struct drm_i915_private *dev_priv, u8 val)
4946 {
4947 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4948 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
4949 return;
4950
4951 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4952 WARN_ON(val > dev_priv->rps.max_freq);
4953 WARN_ON(val < dev_priv->rps.min_freq);
4954
4955 /* min/max delay may still have been modified so be sure to
4956 * write the limits value.
4957 */
4958 if (val != dev_priv->rps.cur_freq) {
4959 gen6_set_rps_thresholds(dev_priv, val);
4960
4961 if (IS_GEN9(dev_priv))
4962 I915_WRITE(GEN6_RPNSWREQ,
4963 GEN9_FREQUENCY(val));
4964 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
4965 I915_WRITE(GEN6_RPNSWREQ,
4966 HSW_FREQUENCY(val));
4967 else
4968 I915_WRITE(GEN6_RPNSWREQ,
4969 GEN6_FREQUENCY(val) |
4970 GEN6_OFFSET(0) |
4971 GEN6_AGGRESSIVE_TURBO);
4972 }
4973
4974 /* Make sure we continue to get interrupts
4975 * until we hit the minimum or maximum frequencies.
4976 */
4977 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
4978 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4979
4980 POSTING_READ(GEN6_RPNSWREQ);
4981
4982 dev_priv->rps.cur_freq = val;
4983 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4984 }
4985
4986 static void valleyview_set_rps(struct drm_i915_private *dev_priv, u8 val)
4987 {
4988 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4989 WARN_ON(val > dev_priv->rps.max_freq);
4990 WARN_ON(val < dev_priv->rps.min_freq);
4991
4992 if (WARN_ONCE(IS_CHERRYVIEW(dev_priv) && (val & 1),
4993 "Odd GPU freq value\n"))
4994 val &= ~1;
4995
4996 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4997
4998 if (val != dev_priv->rps.cur_freq) {
4999 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
5000 if (!IS_CHERRYVIEW(dev_priv))
5001 gen6_set_rps_thresholds(dev_priv, val);
5002 }
5003
5004 dev_priv->rps.cur_freq = val;
5005 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
5006 }
5007
5008 /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
5009 *
5010 * * If Gfx is Idle, then
5011 * 1. Forcewake Media well.
5012 * 2. Request idle freq.
5013 * 3. Release Forcewake of Media well.
5014 */
5015 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
5016 {
5017 u32 val = dev_priv->rps.idle_freq;
5018
5019 if (dev_priv->rps.cur_freq <= val)
5020 return;
5021
5022 /* The punit delays the write of the frequency and voltage until it
5023 * determines the GPU is awake. During normal usage we don't want to
5024 * waste power changing the frequency if the GPU is sleeping (rc6).
5025 * However, the GPU and driver is now idle and we do not want to delay
5026 * switching to minimum voltage (reducing power whilst idle) as we do
5027 * not expect to be woken in the near future and so must flush the
5028 * change by waking the device.
5029 *
5030 * We choose to take the media powerwell (either would do to trick the
5031 * punit into committing the voltage change) as that takes a lot less
5032 * power than the render powerwell.
5033 */
5034 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
5035 valleyview_set_rps(dev_priv, val);
5036 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
5037 }
5038
5039 void gen6_rps_busy(struct drm_i915_private *dev_priv)
5040 {
5041 mutex_lock(&dev_priv->rps.hw_lock);
5042 if (dev_priv->rps.enabled) {
5043 if (dev_priv->pm_rps_events & GEN6_PM_RP_UP_EI_EXPIRED)
5044 gen6_rps_reset_ei(dev_priv);
5045 I915_WRITE(GEN6_PMINTRMSK,
5046 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
5047
5048 gen6_enable_rps_interrupts(dev_priv);
5049
5050 /* Ensure we start at the user's desired frequency */
5051 intel_set_rps(dev_priv,
5052 clamp(dev_priv->rps.cur_freq,
5053 dev_priv->rps.min_freq_softlimit,
5054 dev_priv->rps.max_freq_softlimit));
5055 }
5056 mutex_unlock(&dev_priv->rps.hw_lock);
5057 }
5058
5059 void gen6_rps_idle(struct drm_i915_private *dev_priv)
5060 {
5061 /* Flush our bottom-half so that it does not race with us
5062 * setting the idle frequency and so that it is bounded by
5063 * our rpm wakeref. And then disable the interrupts to stop any
5064 * futher RPS reclocking whilst we are asleep.
5065 */
5066 gen6_disable_rps_interrupts(dev_priv);
5067
5068 mutex_lock(&dev_priv->rps.hw_lock);
5069 if (dev_priv->rps.enabled) {
5070 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5071 vlv_set_rps_idle(dev_priv);
5072 else
5073 gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
5074 dev_priv->rps.last_adj = 0;
5075 I915_WRITE(GEN6_PMINTRMSK,
5076 gen6_sanitize_rps_pm_mask(dev_priv, ~0));
5077 }
5078 mutex_unlock(&dev_priv->rps.hw_lock);
5079
5080 spin_lock(&dev_priv->rps.client_lock);
5081 while (!list_empty(&dev_priv->rps.clients))
5082 list_del_init(dev_priv->rps.clients.next);
5083 spin_unlock(&dev_priv->rps.client_lock);
5084 }
5085
5086 void gen6_rps_boost(struct drm_i915_private *dev_priv,
5087 struct intel_rps_client *rps,
5088 unsigned long submitted)
5089 {
5090 /* This is intentionally racy! We peek at the state here, then
5091 * validate inside the RPS worker.
5092 */
5093 if (!(dev_priv->gt.awake &&
5094 dev_priv->rps.enabled &&
5095 dev_priv->rps.cur_freq < dev_priv->rps.boost_freq))
5096 return;
5097
5098 /* Force a RPS boost (and don't count it against the client) if
5099 * the GPU is severely congested.
5100 */
5101 if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
5102 rps = NULL;
5103
5104 spin_lock(&dev_priv->rps.client_lock);
5105 if (rps == NULL || list_empty(&rps->link)) {
5106 spin_lock_irq(&dev_priv->irq_lock);
5107 if (dev_priv->rps.interrupts_enabled) {
5108 dev_priv->rps.client_boost = true;
5109 schedule_work(&dev_priv->rps.work);
5110 }
5111 spin_unlock_irq(&dev_priv->irq_lock);
5112
5113 if (rps != NULL) {
5114 list_add(&rps->link, &dev_priv->rps.clients);
5115 rps->boosts++;
5116 } else
5117 dev_priv->rps.boosts++;
5118 }
5119 spin_unlock(&dev_priv->rps.client_lock);
5120 }
5121
5122 void intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
5123 {
5124 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5125 valleyview_set_rps(dev_priv, val);
5126 else
5127 gen6_set_rps(dev_priv, val);
5128 }
5129
5130 static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
5131 {
5132 I915_WRITE(GEN6_RC_CONTROL, 0);
5133 I915_WRITE(GEN9_PG_ENABLE, 0);
5134 }
5135
5136 static void gen9_disable_rps(struct drm_i915_private *dev_priv)
5137 {
5138 I915_WRITE(GEN6_RP_CONTROL, 0);
5139 }
5140
5141 static void gen6_disable_rps(struct drm_i915_private *dev_priv)
5142 {
5143 I915_WRITE(GEN6_RC_CONTROL, 0);
5144 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
5145 I915_WRITE(GEN6_RP_CONTROL, 0);
5146 }
5147
5148 static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
5149 {
5150 I915_WRITE(GEN6_RC_CONTROL, 0);
5151 }
5152
5153 static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
5154 {
5155 /* we're doing forcewake before Disabling RC6,
5156 * This what the BIOS expects when going into suspend */
5157 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5158
5159 I915_WRITE(GEN6_RC_CONTROL, 0);
5160
5161 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5162 }
5163
5164 static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode)
5165 {
5166 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5167 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
5168 mode = GEN6_RC_CTL_RC6_ENABLE;
5169 else
5170 mode = 0;
5171 }
5172 if (HAS_RC6p(dev_priv))
5173 DRM_DEBUG_DRIVER("Enabling RC6 states: "
5174 "RC6 %s RC6p %s RC6pp %s\n",
5175 onoff(mode & GEN6_RC_CTL_RC6_ENABLE),
5176 onoff(mode & GEN6_RC_CTL_RC6p_ENABLE),
5177 onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE));
5178
5179 else
5180 DRM_DEBUG_DRIVER("Enabling RC6 states: RC6 %s\n",
5181 onoff(mode & GEN6_RC_CTL_RC6_ENABLE));
5182 }
5183
5184 static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv)
5185 {
5186 struct i915_ggtt *ggtt = &dev_priv->ggtt;
5187 bool enable_rc6 = true;
5188 unsigned long rc6_ctx_base;
5189 u32 rc_ctl;
5190 int rc_sw_target;
5191
5192 rc_ctl = I915_READ(GEN6_RC_CONTROL);
5193 rc_sw_target = (I915_READ(GEN6_RC_STATE) & RC_SW_TARGET_STATE_MASK) >>
5194 RC_SW_TARGET_STATE_SHIFT;
5195 DRM_DEBUG_DRIVER("BIOS enabled RC states: "
5196 "HW_CTRL %s HW_RC6 %s SW_TARGET_STATE %x\n",
5197 onoff(rc_ctl & GEN6_RC_CTL_HW_ENABLE),
5198 onoff(rc_ctl & GEN6_RC_CTL_RC6_ENABLE),
5199 rc_sw_target);
5200
5201 if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
5202 DRM_DEBUG_DRIVER("RC6 Base location not set properly.\n");
5203 enable_rc6 = false;
5204 }
5205
5206 /*
5207 * The exact context size is not known for BXT, so assume a page size
5208 * for this check.
5209 */
5210 rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
5211 if (!((rc6_ctx_base >= ggtt->stolen_reserved_base) &&
5212 (rc6_ctx_base + PAGE_SIZE <= ggtt->stolen_reserved_base +
5213 ggtt->stolen_reserved_size))) {
5214 DRM_DEBUG_DRIVER("RC6 Base address not as expected.\n");
5215 enable_rc6 = false;
5216 }
5217
5218 if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) &&
5219 ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&
5220 ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&
5221 ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {
5222 DRM_DEBUG_DRIVER("Engine Idle wait time not set properly.\n");
5223 enable_rc6 = false;
5224 }
5225
5226 if (!I915_READ(GEN8_PUSHBUS_CONTROL) ||
5227 !I915_READ(GEN8_PUSHBUS_ENABLE) ||
5228 !I915_READ(GEN8_PUSHBUS_SHIFT)) {
5229 DRM_DEBUG_DRIVER("Pushbus not setup properly.\n");
5230 enable_rc6 = false;
5231 }
5232
5233 if (!I915_READ(GEN6_GFXPAUSE)) {
5234 DRM_DEBUG_DRIVER("GFX pause not setup properly.\n");
5235 enable_rc6 = false;
5236 }
5237
5238 if (!I915_READ(GEN8_MISC_CTRL0)) {
5239 DRM_DEBUG_DRIVER("GPM control not setup properly.\n");
5240 enable_rc6 = false;
5241 }
5242
5243 return enable_rc6;
5244 }
5245
5246 int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6)
5247 {
5248 /* No RC6 before Ironlake and code is gone for ilk. */
5249 if (INTEL_INFO(dev_priv)->gen < 6)
5250 return 0;
5251
5252 if (!enable_rc6)
5253 return 0;
5254
5255 if (IS_GEN9_LP(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
5256 DRM_INFO("RC6 disabled by BIOS\n");
5257 return 0;
5258 }
5259
5260 /* Respect the kernel parameter if it is set */
5261 if (enable_rc6 >= 0) {
5262 int mask;
5263
5264 if (HAS_RC6p(dev_priv))
5265 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
5266 INTEL_RC6pp_ENABLE;
5267 else
5268 mask = INTEL_RC6_ENABLE;
5269
5270 if ((enable_rc6 & mask) != enable_rc6)
5271 DRM_DEBUG_DRIVER("Adjusting RC6 mask to %d "
5272 "(requested %d, valid %d)\n",
5273 enable_rc6 & mask, enable_rc6, mask);
5274
5275 return enable_rc6 & mask;
5276 }
5277
5278 if (IS_IVYBRIDGE(dev_priv))
5279 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
5280
5281 return INTEL_RC6_ENABLE;
5282 }
5283
5284 static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
5285 {
5286 /* All of these values are in units of 50MHz */
5287
5288 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
5289 if (IS_GEN9_LP(dev_priv)) {
5290 u32 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
5291 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
5292 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
5293 dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff;
5294 } else {
5295 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
5296 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
5297 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
5298 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
5299 }
5300 /* hw_max = RP0 until we check for overclocking */
5301 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
5302
5303 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
5304 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
5305 IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5306 u32 ddcc_status = 0;
5307
5308 if (sandybridge_pcode_read(dev_priv,
5309 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
5310 &ddcc_status) == 0)
5311 dev_priv->rps.efficient_freq =
5312 clamp_t(u8,
5313 ((ddcc_status >> 8) & 0xff),
5314 dev_priv->rps.min_freq,
5315 dev_priv->rps.max_freq);
5316 }
5317
5318 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5319 /* Store the frequency values in 16.66 MHZ units, which is
5320 * the natural hardware unit for SKL
5321 */
5322 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
5323 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
5324 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
5325 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
5326 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
5327 }
5328 }
5329
5330 static void reset_rps(struct drm_i915_private *dev_priv,
5331 void (*set)(struct drm_i915_private *, u8))
5332 {
5333 u8 freq = dev_priv->rps.cur_freq;
5334
5335 /* force a reset */
5336 dev_priv->rps.power = -1;
5337 dev_priv->rps.cur_freq = -1;
5338
5339 set(dev_priv, freq);
5340 }
5341
5342 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
5343 static void gen9_enable_rps(struct drm_i915_private *dev_priv)
5344 {
5345 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5346
5347 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
5348 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
5349 /*
5350 * BIOS could leave the Hw Turbo enabled, so need to explicitly
5351 * clear out the Control register just to avoid inconsitency
5352 * with debugfs interface, which will show Turbo as enabled
5353 * only and that is not expected by the User after adding the
5354 * WaGsvDisableTurbo. Apart from this there is no problem even
5355 * if the Turbo is left enabled in the Control register, as the
5356 * Up/Down interrupts would remain masked.
5357 */
5358 gen9_disable_rps(dev_priv);
5359 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5360 return;
5361 }
5362
5363 /* Program defaults and thresholds for RPS*/
5364 I915_WRITE(GEN6_RC_VIDEO_FREQ,
5365 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
5366
5367 /* 1 second timeout*/
5368 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
5369 GT_INTERVAL_FROM_US(dev_priv, 1000000));
5370
5371 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
5372
5373 /* Leaning on the below call to gen6_set_rps to program/setup the
5374 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
5375 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
5376 reset_rps(dev_priv, gen6_set_rps);
5377
5378 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5379 }
5380
5381 static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
5382 {
5383 struct intel_engine_cs *engine;
5384 enum intel_engine_id id;
5385 uint32_t rc6_mask = 0;
5386
5387 /* 1a: Software RC state - RC0 */
5388 I915_WRITE(GEN6_RC_STATE, 0);
5389
5390 /* 1b: Get forcewake during program sequence. Although the driver
5391 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5392 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5393
5394 /* 2a: Disable RC states. */
5395 I915_WRITE(GEN6_RC_CONTROL, 0);
5396
5397 /* 2b: Program RC6 thresholds.*/
5398
5399 /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
5400 if (IS_SKYLAKE(dev_priv))
5401 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
5402 else
5403 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
5404 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5405 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5406 for_each_engine(engine, dev_priv, id)
5407 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5408
5409 if (HAS_GUC(dev_priv))
5410 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
5411
5412 I915_WRITE(GEN6_RC_SLEEP, 0);
5413
5414 /* 2c: Program Coarse Power Gating Policies. */
5415 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
5416 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
5417
5418 /* 3a: Enable RC6 */
5419 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
5420 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
5421 DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
5422 /* WaRsUseTimeoutMode:bxt */
5423 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
5424 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
5425 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5426 GEN7_RC_CTL_TO_MODE |
5427 rc6_mask);
5428 } else {
5429 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
5430 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5431 GEN6_RC_CTL_EI_MODE(1) |
5432 rc6_mask);
5433 }
5434
5435 /*
5436 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
5437 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
5438 */
5439 if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
5440 I915_WRITE(GEN9_PG_ENABLE, 0);
5441 else
5442 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
5443 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
5444
5445 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5446 }
5447
5448 static void gen8_enable_rps(struct drm_i915_private *dev_priv)
5449 {
5450 struct intel_engine_cs *engine;
5451 enum intel_engine_id id;
5452 uint32_t rc6_mask = 0;
5453
5454 /* 1a: Software RC state - RC0 */
5455 I915_WRITE(GEN6_RC_STATE, 0);
5456
5457 /* 1c & 1d: Get forcewake during program sequence. Although the driver
5458 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5459 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5460
5461 /* 2a: Disable RC states. */
5462 I915_WRITE(GEN6_RC_CONTROL, 0);
5463
5464 /* 2b: Program RC6 thresholds.*/
5465 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5466 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5467 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5468 for_each_engine(engine, dev_priv, id)
5469 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5470 I915_WRITE(GEN6_RC_SLEEP, 0);
5471 if (IS_BROADWELL(dev_priv))
5472 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
5473 else
5474 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
5475
5476 /* 3: Enable RC6 */
5477 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
5478 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
5479 intel_print_rc6_info(dev_priv, rc6_mask);
5480 if (IS_BROADWELL(dev_priv))
5481 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5482 GEN7_RC_CTL_TO_MODE |
5483 rc6_mask);
5484 else
5485 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5486 GEN6_RC_CTL_EI_MODE(1) |
5487 rc6_mask);
5488
5489 /* 4 Program defaults and thresholds for RPS*/
5490 I915_WRITE(GEN6_RPNSWREQ,
5491 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
5492 I915_WRITE(GEN6_RC_VIDEO_FREQ,
5493 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
5494 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
5495 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
5496
5497 /* Docs recommend 900MHz, and 300 MHz respectively */
5498 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
5499 dev_priv->rps.max_freq_softlimit << 24 |
5500 dev_priv->rps.min_freq_softlimit << 16);
5501
5502 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
5503 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
5504 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
5505 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
5506
5507 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5508
5509 /* 5: Enable RPS */
5510 I915_WRITE(GEN6_RP_CONTROL,
5511 GEN6_RP_MEDIA_TURBO |
5512 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5513 GEN6_RP_MEDIA_IS_GFX |
5514 GEN6_RP_ENABLE |
5515 GEN6_RP_UP_BUSY_AVG |
5516 GEN6_RP_DOWN_IDLE_AVG);
5517
5518 /* 6: Ring frequency + overclocking (our driver does this later */
5519
5520 reset_rps(dev_priv, gen6_set_rps);
5521
5522 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5523 }
5524
5525 static void gen6_enable_rps(struct drm_i915_private *dev_priv)
5526 {
5527 struct intel_engine_cs *engine;
5528 enum intel_engine_id id;
5529 u32 rc6vids, rc6_mask = 0;
5530 u32 gtfifodbg;
5531 int rc6_mode;
5532 int ret;
5533
5534 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5535
5536 /* Here begins a magic sequence of register writes to enable
5537 * auto-downclocking.
5538 *
5539 * Perhaps there might be some value in exposing these to
5540 * userspace...
5541 */
5542 I915_WRITE(GEN6_RC_STATE, 0);
5543
5544 /* Clear the DBG now so we don't confuse earlier errors */
5545 gtfifodbg = I915_READ(GTFIFODBG);
5546 if (gtfifodbg) {
5547 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
5548 I915_WRITE(GTFIFODBG, gtfifodbg);
5549 }
5550
5551 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5552
5553 /* disable the counters and set deterministic thresholds */
5554 I915_WRITE(GEN6_RC_CONTROL, 0);
5555
5556 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
5557 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
5558 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
5559 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5560 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5561
5562 for_each_engine(engine, dev_priv, id)
5563 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5564
5565 I915_WRITE(GEN6_RC_SLEEP, 0);
5566 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
5567 if (IS_IVYBRIDGE(dev_priv))
5568 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
5569 else
5570 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
5571 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
5572 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
5573
5574 /* Check if we are enabling RC6 */
5575 rc6_mode = intel_enable_rc6();
5576 if (rc6_mode & INTEL_RC6_ENABLE)
5577 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
5578
5579 /* We don't use those on Haswell */
5580 if (!IS_HASWELL(dev_priv)) {
5581 if (rc6_mode & INTEL_RC6p_ENABLE)
5582 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
5583
5584 if (rc6_mode & INTEL_RC6pp_ENABLE)
5585 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
5586 }
5587
5588 intel_print_rc6_info(dev_priv, rc6_mask);
5589
5590 I915_WRITE(GEN6_RC_CONTROL,
5591 rc6_mask |
5592 GEN6_RC_CTL_EI_MODE(1) |
5593 GEN6_RC_CTL_HW_ENABLE);
5594
5595 /* Power down if completely idle for over 50ms */
5596 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
5597 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5598
5599 reset_rps(dev_priv, gen6_set_rps);
5600
5601 rc6vids = 0;
5602 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
5603 if (IS_GEN6(dev_priv) && ret) {
5604 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
5605 } else if (IS_GEN6(dev_priv) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
5606 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5607 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5608 rc6vids &= 0xffff00;
5609 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5610 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5611 if (ret)
5612 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5613 }
5614
5615 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5616 }
5617
5618 static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
5619 {
5620 int min_freq = 15;
5621 unsigned int gpu_freq;
5622 unsigned int max_ia_freq, min_ring_freq;
5623 unsigned int max_gpu_freq, min_gpu_freq;
5624 int scaling_factor = 180;
5625 struct cpufreq_policy *policy;
5626
5627 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5628
5629 policy = cpufreq_cpu_get(0);
5630 if (policy) {
5631 max_ia_freq = policy->cpuinfo.max_freq;
5632 cpufreq_cpu_put(policy);
5633 } else {
5634 /*
5635 * Default to measured freq if none found, PCU will ensure we
5636 * don't go over
5637 */
5638 max_ia_freq = tsc_khz;
5639 }
5640
5641 /* Convert from kHz to MHz */
5642 max_ia_freq /= 1000;
5643
5644 min_ring_freq = I915_READ(DCLK) & 0xf;
5645 /* convert DDR frequency from units of 266.6MHz to bandwidth */
5646 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
5647
5648 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5649 /* Convert GT frequency to 50 HZ units */
5650 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5651 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5652 } else {
5653 min_gpu_freq = dev_priv->rps.min_freq;
5654 max_gpu_freq = dev_priv->rps.max_freq;
5655 }
5656
5657 /*
5658 * For each potential GPU frequency, load a ring frequency we'd like
5659 * to use for memory access. We do this by specifying the IA frequency
5660 * the PCU should use as a reference to determine the ring frequency.
5661 */
5662 for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5663 int diff = max_gpu_freq - gpu_freq;
5664 unsigned int ia_freq = 0, ring_freq = 0;
5665
5666 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5667 /*
5668 * ring_freq = 2 * GT. ring_freq is in 100MHz units
5669 * No floor required for ring frequency on SKL.
5670 */
5671 ring_freq = gpu_freq;
5672 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
5673 /* max(2 * GT, DDR). NB: GT is 50MHz units */
5674 ring_freq = max(min_ring_freq, gpu_freq);
5675 } else if (IS_HASWELL(dev_priv)) {
5676 ring_freq = mult_frac(gpu_freq, 5, 4);
5677 ring_freq = max(min_ring_freq, ring_freq);
5678 /* leave ia_freq as the default, chosen by cpufreq */
5679 } else {
5680 /* On older processors, there is no separate ring
5681 * clock domain, so in order to boost the bandwidth
5682 * of the ring, we need to upclock the CPU (ia_freq).
5683 *
5684 * For GPU frequencies less than 750MHz,
5685 * just use the lowest ring freq.
5686 */
5687 if (gpu_freq < min_freq)
5688 ia_freq = 800;
5689 else
5690 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5691 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5692 }
5693
5694 sandybridge_pcode_write(dev_priv,
5695 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
5696 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5697 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5698 gpu_freq);
5699 }
5700 }
5701
5702 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
5703 {
5704 u32 val, rp0;
5705
5706 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5707
5708 switch (INTEL_INFO(dev_priv)->sseu.eu_total) {
5709 case 8:
5710 /* (2 * 4) config */
5711 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5712 break;
5713 case 12:
5714 /* (2 * 6) config */
5715 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5716 break;
5717 case 16:
5718 /* (2 * 8) config */
5719 default:
5720 /* Setting (2 * 8) Min RP0 for any other combination */
5721 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5722 break;
5723 }
5724
5725 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5726
5727 return rp0;
5728 }
5729
5730 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5731 {
5732 u32 val, rpe;
5733
5734 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5735 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5736
5737 return rpe;
5738 }
5739
5740 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5741 {
5742 u32 val, rp1;
5743
5744 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5745 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5746
5747 return rp1;
5748 }
5749
5750 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5751 {
5752 u32 val, rp1;
5753
5754 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5755
5756 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5757
5758 return rp1;
5759 }
5760
5761 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
5762 {
5763 u32 val, rp0;
5764
5765 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5766
5767 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5768 /* Clamp to max */
5769 rp0 = min_t(u32, rp0, 0xea);
5770
5771 return rp0;
5772 }
5773
5774 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5775 {
5776 u32 val, rpe;
5777
5778 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
5779 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
5780 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
5781 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5782
5783 return rpe;
5784 }
5785
5786 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
5787 {
5788 u32 val;
5789
5790 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5791 /*
5792 * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
5793 * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
5794 * a BYT-M B0 the above register contains 0xbf. Moreover when setting
5795 * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
5796 * to make sure it matches what Punit accepts.
5797 */
5798 return max_t(u32, val, 0xc0);
5799 }
5800
5801 /* Check that the pctx buffer wasn't move under us. */
5802 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5803 {
5804 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5805
5806 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5807 dev_priv->vlv_pctx->stolen->start);
5808 }
5809
5810
5811 /* Check that the pcbr address is not empty. */
5812 static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5813 {
5814 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5815
5816 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5817 }
5818
5819 static void cherryview_setup_pctx(struct drm_i915_private *dev_priv)
5820 {
5821 struct i915_ggtt *ggtt = &dev_priv->ggtt;
5822 unsigned long pctx_paddr, paddr;
5823 u32 pcbr;
5824 int pctx_size = 32*1024;
5825
5826 pcbr = I915_READ(VLV_PCBR);
5827 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
5828 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5829 paddr = (dev_priv->mm.stolen_base +
5830 (ggtt->stolen_size - pctx_size));
5831
5832 pctx_paddr = (paddr & (~4095));
5833 I915_WRITE(VLV_PCBR, pctx_paddr);
5834 }
5835
5836 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5837 }
5838
5839 static void valleyview_setup_pctx(struct drm_i915_private *dev_priv)
5840 {
5841 struct drm_i915_gem_object *pctx;
5842 unsigned long pctx_paddr;
5843 u32 pcbr;
5844 int pctx_size = 24*1024;
5845
5846 pcbr = I915_READ(VLV_PCBR);
5847 if (pcbr) {
5848 /* BIOS set it up already, grab the pre-alloc'd space */
5849 int pcbr_offset;
5850
5851 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5852 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv,
5853 pcbr_offset,
5854 I915_GTT_OFFSET_NONE,
5855 pctx_size);
5856 goto out;
5857 }
5858
5859 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5860
5861 /*
5862 * From the Gunit register HAS:
5863 * The Gfx driver is expected to program this register and ensure
5864 * proper allocation within Gfx stolen memory. For example, this
5865 * register should be programmed such than the PCBR range does not
5866 * overlap with other ranges, such as the frame buffer, protected
5867 * memory, or any other relevant ranges.
5868 */
5869 pctx = i915_gem_object_create_stolen(dev_priv, pctx_size);
5870 if (!pctx) {
5871 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
5872 goto out;
5873 }
5874
5875 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5876 I915_WRITE(VLV_PCBR, pctx_paddr);
5877
5878 out:
5879 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5880 dev_priv->vlv_pctx = pctx;
5881 }
5882
5883 static void valleyview_cleanup_pctx(struct drm_i915_private *dev_priv)
5884 {
5885 if (WARN_ON(!dev_priv->vlv_pctx))
5886 return;
5887
5888 i915_gem_object_put(dev_priv->vlv_pctx);
5889 dev_priv->vlv_pctx = NULL;
5890 }
5891
5892 static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv)
5893 {
5894 dev_priv->rps.gpll_ref_freq =
5895 vlv_get_cck_clock(dev_priv, "GPLL ref",
5896 CCK_GPLL_CLOCK_CONTROL,
5897 dev_priv->czclk_freq);
5898
5899 DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
5900 dev_priv->rps.gpll_ref_freq);
5901 }
5902
5903 static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv)
5904 {
5905 u32 val;
5906
5907 valleyview_setup_pctx(dev_priv);
5908
5909 vlv_init_gpll_ref_freq(dev_priv);
5910
5911 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5912 switch ((val >> 6) & 3) {
5913 case 0:
5914 case 1:
5915 dev_priv->mem_freq = 800;
5916 break;
5917 case 2:
5918 dev_priv->mem_freq = 1066;
5919 break;
5920 case 3:
5921 dev_priv->mem_freq = 1333;
5922 break;
5923 }
5924 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5925
5926 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5927 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5928 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5929 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5930 dev_priv->rps.max_freq);
5931
5932 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5933 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5934 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5935 dev_priv->rps.efficient_freq);
5936
5937 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5938 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
5939 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5940 dev_priv->rps.rp1_freq);
5941
5942 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5943 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5944 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5945 dev_priv->rps.min_freq);
5946 }
5947
5948 static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv)
5949 {
5950 u32 val;
5951
5952 cherryview_setup_pctx(dev_priv);
5953
5954 vlv_init_gpll_ref_freq(dev_priv);
5955
5956 mutex_lock(&dev_priv->sb_lock);
5957 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
5958 mutex_unlock(&dev_priv->sb_lock);
5959
5960 switch ((val >> 2) & 0x7) {
5961 case 3:
5962 dev_priv->mem_freq = 2000;
5963 break;
5964 default:
5965 dev_priv->mem_freq = 1600;
5966 break;
5967 }
5968 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5969
5970 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5971 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5972 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5973 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5974 dev_priv->rps.max_freq);
5975
5976 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5977 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5978 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5979 dev_priv->rps.efficient_freq);
5980
5981 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5982 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
5983 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5984 dev_priv->rps.rp1_freq);
5985
5986 /* PUnit validated range is only [RPe, RP0] */
5987 dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
5988 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5989 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5990 dev_priv->rps.min_freq);
5991
5992 WARN_ONCE((dev_priv->rps.max_freq |
5993 dev_priv->rps.efficient_freq |
5994 dev_priv->rps.rp1_freq |
5995 dev_priv->rps.min_freq) & 1,
5996 "Odd GPU freq values\n");
5997 }
5998
5999 static void valleyview_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
6000 {
6001 valleyview_cleanup_pctx(dev_priv);
6002 }
6003
6004 static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
6005 {
6006 struct intel_engine_cs *engine;
6007 enum intel_engine_id id;
6008 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
6009
6010 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6011
6012 gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV |
6013 GT_FIFO_FREE_ENTRIES_CHV);
6014 if (gtfifodbg) {
6015 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
6016 gtfifodbg);
6017 I915_WRITE(GTFIFODBG, gtfifodbg);
6018 }
6019
6020 cherryview_check_pctx(dev_priv);
6021
6022 /* 1a & 1b: Get forcewake during program sequence. Although the driver
6023 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
6024 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6025
6026 /* Disable RC states. */
6027 I915_WRITE(GEN6_RC_CONTROL, 0);
6028
6029 /* 2a: Program RC6 thresholds.*/
6030 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
6031 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
6032 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
6033
6034 for_each_engine(engine, dev_priv, id)
6035 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6036 I915_WRITE(GEN6_RC_SLEEP, 0);
6037
6038 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
6039 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
6040
6041 /* allows RC6 residency counter to work */
6042 I915_WRITE(VLV_COUNTER_CONTROL,
6043 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
6044 VLV_MEDIA_RC6_COUNT_EN |
6045 VLV_RENDER_RC6_COUNT_EN));
6046
6047 /* For now we assume BIOS is allocating and populating the PCBR */
6048 pcbr = I915_READ(VLV_PCBR);
6049
6050 /* 3: Enable RC6 */
6051 if ((intel_enable_rc6() & INTEL_RC6_ENABLE) &&
6052 (pcbr >> VLV_PCBR_ADDR_SHIFT))
6053 rc6_mode = GEN7_RC_CTL_TO_MODE;
6054
6055 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
6056
6057 /* 4 Program defaults and thresholds for RPS*/
6058 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
6059 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
6060 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
6061 I915_WRITE(GEN6_RP_UP_EI, 66000);
6062 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
6063
6064 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6065
6066 /* 5: Enable RPS */
6067 I915_WRITE(GEN6_RP_CONTROL,
6068 GEN6_RP_MEDIA_HW_NORMAL_MODE |
6069 GEN6_RP_MEDIA_IS_GFX |
6070 GEN6_RP_ENABLE |
6071 GEN6_RP_UP_BUSY_AVG |
6072 GEN6_RP_DOWN_IDLE_AVG);
6073
6074 /* Setting Fixed Bias */
6075 val = VLV_OVERRIDE_EN |
6076 VLV_SOC_TDP_EN |
6077 CHV_BIAS_CPU_50_SOC_50;
6078 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
6079
6080 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
6081
6082 /* RPS code assumes GPLL is used */
6083 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
6084
6085 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
6086 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6087
6088 reset_rps(dev_priv, valleyview_set_rps);
6089
6090 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6091 }
6092
6093 static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
6094 {
6095 struct intel_engine_cs *engine;
6096 enum intel_engine_id id;
6097 u32 gtfifodbg, val, rc6_mode = 0;
6098
6099 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6100
6101 valleyview_check_pctx(dev_priv);
6102
6103 gtfifodbg = I915_READ(GTFIFODBG);
6104 if (gtfifodbg) {
6105 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
6106 gtfifodbg);
6107 I915_WRITE(GTFIFODBG, gtfifodbg);
6108 }
6109
6110 /* If VLV, Forcewake all wells, else re-direct to regular path */
6111 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6112
6113 /* Disable RC states. */
6114 I915_WRITE(GEN6_RC_CONTROL, 0);
6115
6116 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
6117 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
6118 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
6119 I915_WRITE(GEN6_RP_UP_EI, 66000);
6120 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
6121
6122 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6123
6124 I915_WRITE(GEN6_RP_CONTROL,
6125 GEN6_RP_MEDIA_TURBO |
6126 GEN6_RP_MEDIA_HW_NORMAL_MODE |
6127 GEN6_RP_MEDIA_IS_GFX |
6128 GEN6_RP_ENABLE |
6129 GEN6_RP_UP_BUSY_AVG |
6130 GEN6_RP_DOWN_IDLE_CONT);
6131
6132 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
6133 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
6134 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
6135
6136 for_each_engine(engine, dev_priv, id)
6137 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6138
6139 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
6140
6141 /* allows RC6 residency counter to work */
6142 I915_WRITE(VLV_COUNTER_CONTROL,
6143 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
6144 VLV_RENDER_RC0_COUNT_EN |
6145 VLV_MEDIA_RC6_COUNT_EN |
6146 VLV_RENDER_RC6_COUNT_EN));
6147
6148 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
6149 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
6150
6151 intel_print_rc6_info(dev_priv, rc6_mode);
6152
6153 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
6154
6155 /* Setting Fixed Bias */
6156 val = VLV_OVERRIDE_EN |
6157 VLV_SOC_TDP_EN |
6158 VLV_BIAS_CPU_125_SOC_875;
6159 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
6160
6161 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
6162
6163 /* RPS code assumes GPLL is used */
6164 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
6165
6166 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
6167 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6168
6169 reset_rps(dev_priv, valleyview_set_rps);
6170
6171 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6172 }
6173
6174 static unsigned long intel_pxfreq(u32 vidfreq)
6175 {
6176 unsigned long freq;
6177 int div = (vidfreq & 0x3f0000) >> 16;
6178 int post = (vidfreq & 0x3000) >> 12;
6179 int pre = (vidfreq & 0x7);
6180
6181 if (!pre)
6182 return 0;
6183
6184 freq = ((div * 133333) / ((1<<post) * pre));
6185
6186 return freq;
6187 }
6188
6189 static const struct cparams {
6190 u16 i;
6191 u16 t;
6192 u16 m;
6193 u16 c;
6194 } cparams[] = {
6195 { 1, 1333, 301, 28664 },
6196 { 1, 1066, 294, 24460 },
6197 { 1, 800, 294, 25192 },
6198 { 0, 1333, 276, 27605 },
6199 { 0, 1066, 276, 27605 },
6200 { 0, 800, 231, 23784 },
6201 };
6202
6203 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
6204 {
6205 u64 total_count, diff, ret;
6206 u32 count1, count2, count3, m = 0, c = 0;
6207 unsigned long now = jiffies_to_msecs(jiffies), diff1;
6208 int i;
6209
6210 assert_spin_locked(&mchdev_lock);
6211
6212 diff1 = now - dev_priv->ips.last_time1;
6213
6214 /* Prevent division-by-zero if we are asking too fast.
6215 * Also, we don't get interesting results if we are polling
6216 * faster than once in 10ms, so just return the saved value
6217 * in such cases.
6218 */
6219 if (diff1 <= 10)
6220 return dev_priv->ips.chipset_power;
6221
6222 count1 = I915_READ(DMIEC);
6223 count2 = I915_READ(DDREC);
6224 count3 = I915_READ(CSIEC);
6225
6226 total_count = count1 + count2 + count3;
6227
6228 /* FIXME: handle per-counter overflow */
6229 if (total_count < dev_priv->ips.last_count1) {
6230 diff = ~0UL - dev_priv->ips.last_count1;
6231 diff += total_count;
6232 } else {
6233 diff = total_count - dev_priv->ips.last_count1;
6234 }
6235
6236 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
6237 if (cparams[i].i == dev_priv->ips.c_m &&
6238 cparams[i].t == dev_priv->ips.r_t) {
6239 m = cparams[i].m;
6240 c = cparams[i].c;
6241 break;
6242 }
6243 }
6244
6245 diff = div_u64(diff, diff1);
6246 ret = ((m * diff) + c);
6247 ret = div_u64(ret, 10);
6248
6249 dev_priv->ips.last_count1 = total_count;
6250 dev_priv->ips.last_time1 = now;
6251
6252 dev_priv->ips.chipset_power = ret;
6253
6254 return ret;
6255 }
6256
6257 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
6258 {
6259 unsigned long val;
6260
6261 if (INTEL_INFO(dev_priv)->gen != 5)
6262 return 0;
6263
6264 spin_lock_irq(&mchdev_lock);
6265
6266 val = __i915_chipset_val(dev_priv);
6267
6268 spin_unlock_irq(&mchdev_lock);
6269
6270 return val;
6271 }
6272
6273 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
6274 {
6275 unsigned long m, x, b;
6276 u32 tsfs;
6277
6278 tsfs = I915_READ(TSFS);
6279
6280 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
6281 x = I915_READ8(TR1);
6282
6283 b = tsfs & TSFS_INTR_MASK;
6284
6285 return ((m * x) / 127) - b;
6286 }
6287
6288 static int _pxvid_to_vd(u8 pxvid)
6289 {
6290 if (pxvid == 0)
6291 return 0;
6292
6293 if (pxvid >= 8 && pxvid < 31)
6294 pxvid = 31;
6295
6296 return (pxvid + 2) * 125;
6297 }
6298
6299 static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
6300 {
6301 const int vd = _pxvid_to_vd(pxvid);
6302 const int vm = vd - 1125;
6303
6304 if (INTEL_INFO(dev_priv)->is_mobile)
6305 return vm > 0 ? vm : 0;
6306
6307 return vd;
6308 }
6309
6310 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
6311 {
6312 u64 now, diff, diffms;
6313 u32 count;
6314
6315 assert_spin_locked(&mchdev_lock);
6316
6317 now = ktime_get_raw_ns();
6318 diffms = now - dev_priv->ips.last_time2;
6319 do_div(diffms, NSEC_PER_MSEC);
6320
6321 /* Don't divide by 0 */
6322 if (!diffms)
6323 return;
6324
6325 count = I915_READ(GFXEC);
6326
6327 if (count < dev_priv->ips.last_count2) {
6328 diff = ~0UL - dev_priv->ips.last_count2;
6329 diff += count;
6330 } else {
6331 diff = count - dev_priv->ips.last_count2;
6332 }
6333
6334 dev_priv->ips.last_count2 = count;
6335 dev_priv->ips.last_time2 = now;
6336
6337 /* More magic constants... */
6338 diff = diff * 1181;
6339 diff = div_u64(diff, diffms * 10);
6340 dev_priv->ips.gfx_power = diff;
6341 }
6342
6343 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
6344 {
6345 if (INTEL_INFO(dev_priv)->gen != 5)
6346 return;
6347
6348 spin_lock_irq(&mchdev_lock);
6349
6350 __i915_update_gfx_val(dev_priv);
6351
6352 spin_unlock_irq(&mchdev_lock);
6353 }
6354
6355 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
6356 {
6357 unsigned long t, corr, state1, corr2, state2;
6358 u32 pxvid, ext_v;
6359
6360 assert_spin_locked(&mchdev_lock);
6361
6362 pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
6363 pxvid = (pxvid >> 24) & 0x7f;
6364 ext_v = pvid_to_extvid(dev_priv, pxvid);
6365
6366 state1 = ext_v;
6367
6368 t = i915_mch_val(dev_priv);
6369
6370 /* Revel in the empirically derived constants */
6371
6372 /* Correction factor in 1/100000 units */
6373 if (t > 80)
6374 corr = ((t * 2349) + 135940);
6375 else if (t >= 50)
6376 corr = ((t * 964) + 29317);
6377 else /* < 50 */
6378 corr = ((t * 301) + 1004);
6379
6380 corr = corr * ((150142 * state1) / 10000 - 78642);
6381 corr /= 100000;
6382 corr2 = (corr * dev_priv->ips.corr);
6383
6384 state2 = (corr2 * state1) / 10000;
6385 state2 /= 100; /* convert to mW */
6386
6387 __i915_update_gfx_val(dev_priv);
6388
6389 return dev_priv->ips.gfx_power + state2;
6390 }
6391
6392 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
6393 {
6394 unsigned long val;
6395
6396 if (INTEL_INFO(dev_priv)->gen != 5)
6397 return 0;
6398
6399 spin_lock_irq(&mchdev_lock);
6400
6401 val = __i915_gfx_val(dev_priv);
6402
6403 spin_unlock_irq(&mchdev_lock);
6404
6405 return val;
6406 }
6407
6408 /**
6409 * i915_read_mch_val - return value for IPS use
6410 *
6411 * Calculate and return a value for the IPS driver to use when deciding whether
6412 * we have thermal and power headroom to increase CPU or GPU power budget.
6413 */
6414 unsigned long i915_read_mch_val(void)
6415 {
6416 struct drm_i915_private *dev_priv;
6417 unsigned long chipset_val, graphics_val, ret = 0;
6418
6419 spin_lock_irq(&mchdev_lock);
6420 if (!i915_mch_dev)
6421 goto out_unlock;
6422 dev_priv = i915_mch_dev;
6423
6424 chipset_val = __i915_chipset_val(dev_priv);
6425 graphics_val = __i915_gfx_val(dev_priv);
6426
6427 ret = chipset_val + graphics_val;
6428
6429 out_unlock:
6430 spin_unlock_irq(&mchdev_lock);
6431
6432 return ret;
6433 }
6434 EXPORT_SYMBOL_GPL(i915_read_mch_val);
6435
6436 /**
6437 * i915_gpu_raise - raise GPU frequency limit
6438 *
6439 * Raise the limit; IPS indicates we have thermal headroom.
6440 */
6441 bool i915_gpu_raise(void)
6442 {
6443 struct drm_i915_private *dev_priv;
6444 bool ret = true;
6445
6446 spin_lock_irq(&mchdev_lock);
6447 if (!i915_mch_dev) {
6448 ret = false;
6449 goto out_unlock;
6450 }
6451 dev_priv = i915_mch_dev;
6452
6453 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
6454 dev_priv->ips.max_delay--;
6455
6456 out_unlock:
6457 spin_unlock_irq(&mchdev_lock);
6458
6459 return ret;
6460 }
6461 EXPORT_SYMBOL_GPL(i915_gpu_raise);
6462
6463 /**
6464 * i915_gpu_lower - lower GPU frequency limit
6465 *
6466 * IPS indicates we're close to a thermal limit, so throttle back the GPU
6467 * frequency maximum.
6468 */
6469 bool i915_gpu_lower(void)
6470 {
6471 struct drm_i915_private *dev_priv;
6472 bool ret = true;
6473
6474 spin_lock_irq(&mchdev_lock);
6475 if (!i915_mch_dev) {
6476 ret = false;
6477 goto out_unlock;
6478 }
6479 dev_priv = i915_mch_dev;
6480
6481 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
6482 dev_priv->ips.max_delay++;
6483
6484 out_unlock:
6485 spin_unlock_irq(&mchdev_lock);
6486
6487 return ret;
6488 }
6489 EXPORT_SYMBOL_GPL(i915_gpu_lower);
6490
6491 /**
6492 * i915_gpu_busy - indicate GPU business to IPS
6493 *
6494 * Tell the IPS driver whether or not the GPU is busy.
6495 */
6496 bool i915_gpu_busy(void)
6497 {
6498 bool ret = false;
6499
6500 spin_lock_irq(&mchdev_lock);
6501 if (i915_mch_dev)
6502 ret = i915_mch_dev->gt.awake;
6503 spin_unlock_irq(&mchdev_lock);
6504
6505 return ret;
6506 }
6507 EXPORT_SYMBOL_GPL(i915_gpu_busy);
6508
6509 /**
6510 * i915_gpu_turbo_disable - disable graphics turbo
6511 *
6512 * Disable graphics turbo by resetting the max frequency and setting the
6513 * current frequency to the default.
6514 */
6515 bool i915_gpu_turbo_disable(void)
6516 {
6517 struct drm_i915_private *dev_priv;
6518 bool ret = true;
6519
6520 spin_lock_irq(&mchdev_lock);
6521 if (!i915_mch_dev) {
6522 ret = false;
6523 goto out_unlock;
6524 }
6525 dev_priv = i915_mch_dev;
6526
6527 dev_priv->ips.max_delay = dev_priv->ips.fstart;
6528
6529 if (!ironlake_set_drps(dev_priv, dev_priv->ips.fstart))
6530 ret = false;
6531
6532 out_unlock:
6533 spin_unlock_irq(&mchdev_lock);
6534
6535 return ret;
6536 }
6537 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6538
6539 /**
6540 * Tells the intel_ips driver that the i915 driver is now loaded, if
6541 * IPS got loaded first.
6542 *
6543 * This awkward dance is so that neither module has to depend on the
6544 * other in order for IPS to do the appropriate communication of
6545 * GPU turbo limits to i915.
6546 */
6547 static void
6548 ips_ping_for_i915_load(void)
6549 {
6550 void (*link)(void);
6551
6552 link = symbol_get(ips_link_to_i915_driver);
6553 if (link) {
6554 link();
6555 symbol_put(ips_link_to_i915_driver);
6556 }
6557 }
6558
6559 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6560 {
6561 /* We only register the i915 ips part with intel-ips once everything is
6562 * set up, to avoid intel-ips sneaking in and reading bogus values. */
6563 spin_lock_irq(&mchdev_lock);
6564 i915_mch_dev = dev_priv;
6565 spin_unlock_irq(&mchdev_lock);
6566
6567 ips_ping_for_i915_load();
6568 }
6569
6570 void intel_gpu_ips_teardown(void)
6571 {
6572 spin_lock_irq(&mchdev_lock);
6573 i915_mch_dev = NULL;
6574 spin_unlock_irq(&mchdev_lock);
6575 }
6576
6577 static void intel_init_emon(struct drm_i915_private *dev_priv)
6578 {
6579 u32 lcfuse;
6580 u8 pxw[16];
6581 int i;
6582
6583 /* Disable to program */
6584 I915_WRITE(ECR, 0);
6585 POSTING_READ(ECR);
6586
6587 /* Program energy weights for various events */
6588 I915_WRITE(SDEW, 0x15040d00);
6589 I915_WRITE(CSIEW0, 0x007f0000);
6590 I915_WRITE(CSIEW1, 0x1e220004);
6591 I915_WRITE(CSIEW2, 0x04000004);
6592
6593 for (i = 0; i < 5; i++)
6594 I915_WRITE(PEW(i), 0);
6595 for (i = 0; i < 3; i++)
6596 I915_WRITE(DEW(i), 0);
6597
6598 /* Program P-state weights to account for frequency power adjustment */
6599 for (i = 0; i < 16; i++) {
6600 u32 pxvidfreq = I915_READ(PXVFREQ(i));
6601 unsigned long freq = intel_pxfreq(pxvidfreq);
6602 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6603 PXVFREQ_PX_SHIFT;
6604 unsigned long val;
6605
6606 val = vid * vid;
6607 val *= (freq / 1000);
6608 val *= 255;
6609 val /= (127*127*900);
6610 if (val > 0xff)
6611 DRM_ERROR("bad pxval: %ld\n", val);
6612 pxw[i] = val;
6613 }
6614 /* Render standby states get 0 weight */
6615 pxw[14] = 0;
6616 pxw[15] = 0;
6617
6618 for (i = 0; i < 4; i++) {
6619 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6620 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
6621 I915_WRITE(PXW(i), val);
6622 }
6623
6624 /* Adjust magic regs to magic values (more experimental results) */
6625 I915_WRITE(OGW0, 0);
6626 I915_WRITE(OGW1, 0);
6627 I915_WRITE(EG0, 0x00007f00);
6628 I915_WRITE(EG1, 0x0000000e);
6629 I915_WRITE(EG2, 0x000e0000);
6630 I915_WRITE(EG3, 0x68000300);
6631 I915_WRITE(EG4, 0x42000000);
6632 I915_WRITE(EG5, 0x00140031);
6633 I915_WRITE(EG6, 0);
6634 I915_WRITE(EG7, 0);
6635
6636 for (i = 0; i < 8; i++)
6637 I915_WRITE(PXWL(i), 0);
6638
6639 /* Enable PMON + select events */
6640 I915_WRITE(ECR, 0x80000019);
6641
6642 lcfuse = I915_READ(LCFUSE02);
6643
6644 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
6645 }
6646
6647 void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
6648 {
6649 /*
6650 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6651 * requirement.
6652 */
6653 if (!i915.enable_rc6) {
6654 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6655 intel_runtime_pm_get(dev_priv);
6656 }
6657
6658 mutex_lock(&dev_priv->drm.struct_mutex);
6659 mutex_lock(&dev_priv->rps.hw_lock);
6660
6661 /* Initialize RPS limits (for userspace) */
6662 if (IS_CHERRYVIEW(dev_priv))
6663 cherryview_init_gt_powersave(dev_priv);
6664 else if (IS_VALLEYVIEW(dev_priv))
6665 valleyview_init_gt_powersave(dev_priv);
6666 else if (INTEL_GEN(dev_priv) >= 6)
6667 gen6_init_rps_frequencies(dev_priv);
6668
6669 /* Derive initial user preferences/limits from the hardware limits */
6670 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
6671 dev_priv->rps.cur_freq = dev_priv->rps.idle_freq;
6672
6673 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
6674 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
6675
6676 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
6677 dev_priv->rps.min_freq_softlimit =
6678 max_t(int,
6679 dev_priv->rps.efficient_freq,
6680 intel_freq_opcode(dev_priv, 450));
6681
6682 /* After setting max-softlimit, find the overclock max freq */
6683 if (IS_GEN6(dev_priv) ||
6684 IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
6685 u32 params = 0;
6686
6687 sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &params);
6688 if (params & BIT(31)) { /* OC supported */
6689 DRM_DEBUG_DRIVER("Overclocking supported, max: %dMHz, overclock: %dMHz\n",
6690 (dev_priv->rps.max_freq & 0xff) * 50,
6691 (params & 0xff) * 50);
6692 dev_priv->rps.max_freq = params & 0xff;
6693 }
6694 }
6695
6696 /* Finally allow us to boost to max by default */
6697 dev_priv->rps.boost_freq = dev_priv->rps.max_freq;
6698
6699 mutex_unlock(&dev_priv->rps.hw_lock);
6700 mutex_unlock(&dev_priv->drm.struct_mutex);
6701
6702 intel_autoenable_gt_powersave(dev_priv);
6703 }
6704
6705 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
6706 {
6707 if (IS_VALLEYVIEW(dev_priv))
6708 valleyview_cleanup_gt_powersave(dev_priv);
6709
6710 if (!i915.enable_rc6)
6711 intel_runtime_pm_put(dev_priv);
6712 }
6713
6714 /**
6715 * intel_suspend_gt_powersave - suspend PM work and helper threads
6716 * @dev_priv: i915 device
6717 *
6718 * We don't want to disable RC6 or other features here, we just want
6719 * to make sure any work we've queued has finished and won't bother
6720 * us while we're suspended.
6721 */
6722 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
6723 {
6724 if (INTEL_GEN(dev_priv) < 6)
6725 return;
6726
6727 if (cancel_delayed_work_sync(&dev_priv->rps.autoenable_work))
6728 intel_runtime_pm_put(dev_priv);
6729
6730 /* gen6_rps_idle() will be called later to disable interrupts */
6731 }
6732
6733 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
6734 {
6735 dev_priv->rps.enabled = true; /* force disabling */
6736 intel_disable_gt_powersave(dev_priv);
6737
6738 gen6_reset_rps_interrupts(dev_priv);
6739 }
6740
6741 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
6742 {
6743 if (!READ_ONCE(dev_priv->rps.enabled))
6744 return;
6745
6746 mutex_lock(&dev_priv->rps.hw_lock);
6747
6748 if (INTEL_GEN(dev_priv) >= 9) {
6749 gen9_disable_rc6(dev_priv);
6750 gen9_disable_rps(dev_priv);
6751 } else if (IS_CHERRYVIEW(dev_priv)) {
6752 cherryview_disable_rps(dev_priv);
6753 } else if (IS_VALLEYVIEW(dev_priv)) {
6754 valleyview_disable_rps(dev_priv);
6755 } else if (INTEL_GEN(dev_priv) >= 6) {
6756 gen6_disable_rps(dev_priv);
6757 } else if (IS_IRONLAKE_M(dev_priv)) {
6758 ironlake_disable_drps(dev_priv);
6759 }
6760
6761 dev_priv->rps.enabled = false;
6762 mutex_unlock(&dev_priv->rps.hw_lock);
6763 }
6764
6765 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
6766 {
6767 /* We shouldn't be disabling as we submit, so this should be less
6768 * racy than it appears!
6769 */
6770 if (READ_ONCE(dev_priv->rps.enabled))
6771 return;
6772
6773 /* Powersaving is controlled by the host when inside a VM */
6774 if (intel_vgpu_active(dev_priv))
6775 return;
6776
6777 mutex_lock(&dev_priv->rps.hw_lock);
6778
6779 if (IS_CHERRYVIEW(dev_priv)) {
6780 cherryview_enable_rps(dev_priv);
6781 } else if (IS_VALLEYVIEW(dev_priv)) {
6782 valleyview_enable_rps(dev_priv);
6783 } else if (INTEL_GEN(dev_priv) >= 9) {
6784 gen9_enable_rc6(dev_priv);
6785 gen9_enable_rps(dev_priv);
6786 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
6787 gen6_update_ring_freq(dev_priv);
6788 } else if (IS_BROADWELL(dev_priv)) {
6789 gen8_enable_rps(dev_priv);
6790 gen6_update_ring_freq(dev_priv);
6791 } else if (INTEL_GEN(dev_priv) >= 6) {
6792 gen6_enable_rps(dev_priv);
6793 gen6_update_ring_freq(dev_priv);
6794 } else if (IS_IRONLAKE_M(dev_priv)) {
6795 ironlake_enable_drps(dev_priv);
6796 intel_init_emon(dev_priv);
6797 }
6798
6799 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6800 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6801
6802 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6803 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6804
6805 dev_priv->rps.enabled = true;
6806 mutex_unlock(&dev_priv->rps.hw_lock);
6807 }
6808
6809 static void __intel_autoenable_gt_powersave(struct work_struct *work)
6810 {
6811 struct drm_i915_private *dev_priv =
6812 container_of(work, typeof(*dev_priv), rps.autoenable_work.work);
6813 struct intel_engine_cs *rcs;
6814 struct drm_i915_gem_request *req;
6815
6816 if (READ_ONCE(dev_priv->rps.enabled))
6817 goto out;
6818
6819 rcs = dev_priv->engine[RCS];
6820 if (rcs->last_retired_context)
6821 goto out;
6822
6823 if (!rcs->init_context)
6824 goto out;
6825
6826 mutex_lock(&dev_priv->drm.struct_mutex);
6827
6828 req = i915_gem_request_alloc(rcs, dev_priv->kernel_context);
6829 if (IS_ERR(req))
6830 goto unlock;
6831
6832 if (!i915.enable_execlists && i915_switch_context(req) == 0)
6833 rcs->init_context(req);
6834
6835 /* Mark the device busy, calling intel_enable_gt_powersave() */
6836 i915_add_request_no_flush(req);
6837
6838 unlock:
6839 mutex_unlock(&dev_priv->drm.struct_mutex);
6840 out:
6841 intel_runtime_pm_put(dev_priv);
6842 }
6843
6844 void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv)
6845 {
6846 if (READ_ONCE(dev_priv->rps.enabled))
6847 return;
6848
6849 if (IS_IRONLAKE_M(dev_priv)) {
6850 ironlake_enable_drps(dev_priv);
6851 intel_init_emon(dev_priv);
6852 } else if (INTEL_INFO(dev_priv)->gen >= 6) {
6853 /*
6854 * PCU communication is slow and this doesn't need to be
6855 * done at any specific time, so do this out of our fast path
6856 * to make resume and init faster.
6857 *
6858 * We depend on the HW RC6 power context save/restore
6859 * mechanism when entering D3 through runtime PM suspend. So
6860 * disable RPM until RPS/RC6 is properly setup. We can only
6861 * get here via the driver load/system resume/runtime resume
6862 * paths, so the _noresume version is enough (and in case of
6863 * runtime resume it's necessary).
6864 */
6865 if (queue_delayed_work(dev_priv->wq,
6866 &dev_priv->rps.autoenable_work,
6867 round_jiffies_up_relative(HZ)))
6868 intel_runtime_pm_get_noresume(dev_priv);
6869 }
6870 }
6871
6872 static void ibx_init_clock_gating(struct drm_i915_private *dev_priv)
6873 {
6874 /*
6875 * On Ibex Peak and Cougar Point, we need to disable clock
6876 * gating for the panel power sequencer or it will fail to
6877 * start up when no ports are active.
6878 */
6879 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6880 }
6881
6882 static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv)
6883 {
6884 enum pipe pipe;
6885
6886 for_each_pipe(dev_priv, pipe) {
6887 I915_WRITE(DSPCNTR(pipe),
6888 I915_READ(DSPCNTR(pipe)) |
6889 DISPPLANE_TRICKLE_FEED_DISABLE);
6890
6891 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6892 POSTING_READ(DSPSURF(pipe));
6893 }
6894 }
6895
6896 static void ilk_init_lp_watermarks(struct drm_i915_private *dev_priv)
6897 {
6898 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6899 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6900 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6901
6902 /*
6903 * Don't touch WM1S_LP_EN here.
6904 * Doing so could cause underruns.
6905 */
6906 }
6907
6908 static void ironlake_init_clock_gating(struct drm_i915_private *dev_priv)
6909 {
6910 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6911
6912 /*
6913 * Required for FBC
6914 * WaFbcDisableDpfcClockGating:ilk
6915 */
6916 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6917 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6918 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6919
6920 I915_WRITE(PCH_3DCGDIS0,
6921 MARIUNIT_CLOCK_GATE_DISABLE |
6922 SVSMUNIT_CLOCK_GATE_DISABLE);
6923 I915_WRITE(PCH_3DCGDIS1,
6924 VFMUNIT_CLOCK_GATE_DISABLE);
6925
6926 /*
6927 * According to the spec the following bits should be set in
6928 * order to enable memory self-refresh
6929 * The bit 22/21 of 0x42004
6930 * The bit 5 of 0x42020
6931 * The bit 15 of 0x45000
6932 */
6933 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6934 (I915_READ(ILK_DISPLAY_CHICKEN2) |
6935 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
6936 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6937 I915_WRITE(DISP_ARB_CTL,
6938 (I915_READ(DISP_ARB_CTL) |
6939 DISP_FBC_WM_DIS));
6940
6941 ilk_init_lp_watermarks(dev_priv);
6942
6943 /*
6944 * Based on the document from hardware guys the following bits
6945 * should be set unconditionally in order to enable FBC.
6946 * The bit 22 of 0x42000
6947 * The bit 22 of 0x42004
6948 * The bit 7,8,9 of 0x42020.
6949 */
6950 if (IS_IRONLAKE_M(dev_priv)) {
6951 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6952 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6953 I915_READ(ILK_DISPLAY_CHICKEN1) |
6954 ILK_FBCQ_DIS);
6955 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6956 I915_READ(ILK_DISPLAY_CHICKEN2) |
6957 ILK_DPARB_GATE);
6958 }
6959
6960 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6961
6962 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6963 I915_READ(ILK_DISPLAY_CHICKEN2) |
6964 ILK_ELPIN_409_SELECT);
6965 I915_WRITE(_3D_CHICKEN2,
6966 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6967 _3D_CHICKEN2_WM_READ_PIPELINED);
6968
6969 /* WaDisableRenderCachePipelinedFlush:ilk */
6970 I915_WRITE(CACHE_MODE_0,
6971 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6972
6973 /* WaDisable_RenderCache_OperationalFlush:ilk */
6974 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6975
6976 g4x_disable_trickle_feed(dev_priv);
6977
6978 ibx_init_clock_gating(dev_priv);
6979 }
6980
6981 static void cpt_init_clock_gating(struct drm_i915_private *dev_priv)
6982 {
6983 int pipe;
6984 uint32_t val;
6985
6986 /*
6987 * On Ibex Peak and Cougar Point, we need to disable clock
6988 * gating for the panel power sequencer or it will fail to
6989 * start up when no ports are active.
6990 */
6991 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6992 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6993 PCH_CPUNIT_CLOCK_GATE_DISABLE);
6994 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6995 DPLS_EDP_PPS_FIX_DIS);
6996 /* The below fixes the weird display corruption, a few pixels shifted
6997 * downward, on (only) LVDS of some HP laptops with IVY.
6998 */
6999 for_each_pipe(dev_priv, pipe) {
7000 val = I915_READ(TRANS_CHICKEN2(pipe));
7001 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
7002 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
7003 if (dev_priv->vbt.fdi_rx_polarity_inverted)
7004 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
7005 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
7006 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
7007 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
7008 I915_WRITE(TRANS_CHICKEN2(pipe), val);
7009 }
7010 /* WADP0ClockGatingDisable */
7011 for_each_pipe(dev_priv, pipe) {
7012 I915_WRITE(TRANS_CHICKEN1(pipe),
7013 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
7014 }
7015 }
7016
7017 static void gen6_check_mch_setup(struct drm_i915_private *dev_priv)
7018 {
7019 uint32_t tmp;
7020
7021 tmp = I915_READ(MCH_SSKPD);
7022 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
7023 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
7024 tmp);
7025 }
7026
7027 static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
7028 {
7029 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
7030
7031 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
7032
7033 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7034 I915_READ(ILK_DISPLAY_CHICKEN2) |
7035 ILK_ELPIN_409_SELECT);
7036
7037 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
7038 I915_WRITE(_3D_CHICKEN,
7039 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
7040
7041 /* WaDisable_RenderCache_OperationalFlush:snb */
7042 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7043
7044 /*
7045 * BSpec recoomends 8x4 when MSAA is used,
7046 * however in practice 16x4 seems fastest.
7047 *
7048 * Note that PS/WM thread counts depend on the WIZ hashing
7049 * disable bit, which we don't touch here, but it's good
7050 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7051 */
7052 I915_WRITE(GEN6_GT_MODE,
7053 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7054
7055 ilk_init_lp_watermarks(dev_priv);
7056
7057 I915_WRITE(CACHE_MODE_0,
7058 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
7059
7060 I915_WRITE(GEN6_UCGCTL1,
7061 I915_READ(GEN6_UCGCTL1) |
7062 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
7063 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
7064
7065 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
7066 * gating disable must be set. Failure to set it results in
7067 * flickering pixels due to Z write ordering failures after
7068 * some amount of runtime in the Mesa "fire" demo, and Unigine
7069 * Sanctuary and Tropics, and apparently anything else with
7070 * alpha test or pixel discard.
7071 *
7072 * According to the spec, bit 11 (RCCUNIT) must also be set,
7073 * but we didn't debug actual testcases to find it out.
7074 *
7075 * WaDisableRCCUnitClockGating:snb
7076 * WaDisableRCPBUnitClockGating:snb
7077 */
7078 I915_WRITE(GEN6_UCGCTL2,
7079 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
7080 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
7081
7082 /* WaStripsFansDisableFastClipPerformanceFix:snb */
7083 I915_WRITE(_3D_CHICKEN3,
7084 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
7085
7086 /*
7087 * Bspec says:
7088 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
7089 * 3DSTATE_SF number of SF output attributes is more than 16."
7090 */
7091 I915_WRITE(_3D_CHICKEN3,
7092 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
7093
7094 /*
7095 * According to the spec the following bits should be
7096 * set in order to enable memory self-refresh and fbc:
7097 * The bit21 and bit22 of 0x42000
7098 * The bit21 and bit22 of 0x42004
7099 * The bit5 and bit7 of 0x42020
7100 * The bit14 of 0x70180
7101 * The bit14 of 0x71180
7102 *
7103 * WaFbcAsynchFlipDisableFbcQueue:snb
7104 */
7105 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7106 I915_READ(ILK_DISPLAY_CHICKEN1) |
7107 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7108 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7109 I915_READ(ILK_DISPLAY_CHICKEN2) |
7110 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
7111 I915_WRITE(ILK_DSPCLK_GATE_D,
7112 I915_READ(ILK_DSPCLK_GATE_D) |
7113 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
7114 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
7115
7116 g4x_disable_trickle_feed(dev_priv);
7117
7118 cpt_init_clock_gating(dev_priv);
7119
7120 gen6_check_mch_setup(dev_priv);
7121 }
7122
7123 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
7124 {
7125 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
7126
7127 /*
7128 * WaVSThreadDispatchOverride:ivb,vlv
7129 *
7130 * This actually overrides the dispatch
7131 * mode for all thread types.
7132 */
7133 reg &= ~GEN7_FF_SCHED_MASK;
7134 reg |= GEN7_FF_TS_SCHED_HW;
7135 reg |= GEN7_FF_VS_SCHED_HW;
7136 reg |= GEN7_FF_DS_SCHED_HW;
7137
7138 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
7139 }
7140
7141 static void lpt_init_clock_gating(struct drm_i915_private *dev_priv)
7142 {
7143 /*
7144 * TODO: this bit should only be enabled when really needed, then
7145 * disabled when not needed anymore in order to save power.
7146 */
7147 if (HAS_PCH_LPT_LP(dev_priv))
7148 I915_WRITE(SOUTH_DSPCLK_GATE_D,
7149 I915_READ(SOUTH_DSPCLK_GATE_D) |
7150 PCH_LP_PARTITION_LEVEL_DISABLE);
7151
7152 /* WADPOClockGatingDisable:hsw */
7153 I915_WRITE(TRANS_CHICKEN1(PIPE_A),
7154 I915_READ(TRANS_CHICKEN1(PIPE_A)) |
7155 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
7156 }
7157
7158 static void lpt_suspend_hw(struct drm_i915_private *dev_priv)
7159 {
7160 if (HAS_PCH_LPT_LP(dev_priv)) {
7161 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
7162
7163 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7164 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7165 }
7166 }
7167
7168 static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
7169 int general_prio_credits,
7170 int high_prio_credits)
7171 {
7172 u32 misccpctl;
7173
7174 /* WaTempDisableDOPClkGating:bdw */
7175 misccpctl = I915_READ(GEN7_MISCCPCTL);
7176 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
7177
7178 I915_WRITE(GEN8_L3SQCREG1,
7179 L3_GENERAL_PRIO_CREDITS(general_prio_credits) |
7180 L3_HIGH_PRIO_CREDITS(high_prio_credits));
7181
7182 /*
7183 * Wait at least 100 clocks before re-enabling clock gating.
7184 * See the definition of L3SQCREG1 in BSpec.
7185 */
7186 POSTING_READ(GEN8_L3SQCREG1);
7187 udelay(1);
7188 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
7189 }
7190
7191 static void kabylake_init_clock_gating(struct drm_i915_private *dev_priv)
7192 {
7193 gen9_init_clock_gating(dev_priv);
7194
7195 /* WaDisableSDEUnitClockGating:kbl */
7196 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7197 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7198 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7199
7200 /* WaDisableGamClockGating:kbl */
7201 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7202 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7203 GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
7204
7205 /* WaFbcNukeOnHostModify:kbl */
7206 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7207 ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
7208 }
7209
7210 static void skylake_init_clock_gating(struct drm_i915_private *dev_priv)
7211 {
7212 gen9_init_clock_gating(dev_priv);
7213
7214 /* WAC6entrylatency:skl */
7215 I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
7216 FBC_LLC_FULLY_OPEN);
7217
7218 /* WaFbcNukeOnHostModify:skl */
7219 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7220 ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
7221 }
7222
7223 static void broadwell_init_clock_gating(struct drm_i915_private *dev_priv)
7224 {
7225 enum pipe pipe;
7226
7227 ilk_init_lp_watermarks(dev_priv);
7228
7229 /* WaSwitchSolVfFArbitrationPriority:bdw */
7230 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7231
7232 /* WaPsrDPAMaskVBlankInSRD:bdw */
7233 I915_WRITE(CHICKEN_PAR1_1,
7234 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
7235
7236 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
7237 for_each_pipe(dev_priv, pipe) {
7238 I915_WRITE(CHICKEN_PIPESL_1(pipe),
7239 I915_READ(CHICKEN_PIPESL_1(pipe)) |
7240 BDW_DPRS_MASK_VBLANK_SRD);
7241 }
7242
7243 /* WaVSRefCountFullforceMissDisable:bdw */
7244 /* WaDSRefCountFullforceMissDisable:bdw */
7245 I915_WRITE(GEN7_FF_THREAD_MODE,
7246 I915_READ(GEN7_FF_THREAD_MODE) &
7247 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
7248
7249 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7250 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
7251
7252 /* WaDisableSDEUnitClockGating:bdw */
7253 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7254 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7255
7256 /* WaProgramL3SqcReg1Default:bdw */
7257 gen8_set_l3sqc_credits(dev_priv, 30, 2);
7258
7259 /*
7260 * WaGttCachingOffByDefault:bdw
7261 * GTT cache may not work with big pages, so if those
7262 * are ever enabled GTT cache may need to be disabled.
7263 */
7264 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
7265
7266 /* WaKVMNotificationOnConfigChange:bdw */
7267 I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
7268 | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
7269
7270 lpt_init_clock_gating(dev_priv);
7271 }
7272
7273 static void haswell_init_clock_gating(struct drm_i915_private *dev_priv)
7274 {
7275 ilk_init_lp_watermarks(dev_priv);
7276
7277 /* L3 caching of data atomics doesn't work -- disable it. */
7278 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
7279 I915_WRITE(HSW_ROW_CHICKEN3,
7280 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
7281
7282 /* This is required by WaCatErrorRejectionIssue:hsw */
7283 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7284 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7285 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7286
7287 /* WaVSRefCountFullforceMissDisable:hsw */
7288 I915_WRITE(GEN7_FF_THREAD_MODE,
7289 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
7290
7291 /* WaDisable_RenderCache_OperationalFlush:hsw */
7292 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7293
7294 /* enable HiZ Raw Stall Optimization */
7295 I915_WRITE(CACHE_MODE_0_GEN7,
7296 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7297
7298 /* WaDisable4x2SubspanOptimization:hsw */
7299 I915_WRITE(CACHE_MODE_1,
7300 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7301
7302 /*
7303 * BSpec recommends 8x4 when MSAA is used,
7304 * however in practice 16x4 seems fastest.
7305 *
7306 * Note that PS/WM thread counts depend on the WIZ hashing
7307 * disable bit, which we don't touch here, but it's good
7308 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7309 */
7310 I915_WRITE(GEN7_GT_MODE,
7311 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7312
7313 /* WaSampleCChickenBitEnable:hsw */
7314 I915_WRITE(HALF_SLICE_CHICKEN3,
7315 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
7316
7317 /* WaSwitchSolVfFArbitrationPriority:hsw */
7318 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7319
7320 /* WaRsPkgCStateDisplayPMReq:hsw */
7321 I915_WRITE(CHICKEN_PAR1_1,
7322 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
7323
7324 lpt_init_clock_gating(dev_priv);
7325 }
7326
7327 static void ivybridge_init_clock_gating(struct drm_i915_private *dev_priv)
7328 {
7329 uint32_t snpcr;
7330
7331 ilk_init_lp_watermarks(dev_priv);
7332
7333 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
7334
7335 /* WaDisableEarlyCull:ivb */
7336 I915_WRITE(_3D_CHICKEN3,
7337 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7338
7339 /* WaDisableBackToBackFlipFix:ivb */
7340 I915_WRITE(IVB_CHICKEN3,
7341 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7342 CHICKEN3_DGMG_DONE_FIX_DISABLE);
7343
7344 /* WaDisablePSDDualDispatchEnable:ivb */
7345 if (IS_IVB_GT1(dev_priv))
7346 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
7347 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
7348
7349 /* WaDisable_RenderCache_OperationalFlush:ivb */
7350 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7351
7352 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
7353 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
7354 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
7355
7356 /* WaApplyL3ControlAndL3ChickenMode:ivb */
7357 I915_WRITE(GEN7_L3CNTLREG1,
7358 GEN7_WA_FOR_GEN7_L3_CONTROL);
7359 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
7360 GEN7_WA_L3_CHICKEN_MODE);
7361 if (IS_IVB_GT1(dev_priv))
7362 I915_WRITE(GEN7_ROW_CHICKEN2,
7363 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7364 else {
7365 /* must write both registers */
7366 I915_WRITE(GEN7_ROW_CHICKEN2,
7367 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7368 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
7369 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7370 }
7371
7372 /* WaForceL3Serialization:ivb */
7373 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7374 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7375
7376 /*
7377 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
7378 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
7379 */
7380 I915_WRITE(GEN6_UCGCTL2,
7381 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
7382
7383 /* This is required by WaCatErrorRejectionIssue:ivb */
7384 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7385 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7386 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7387
7388 g4x_disable_trickle_feed(dev_priv);
7389
7390 gen7_setup_fixed_func_scheduler(dev_priv);
7391
7392 if (0) { /* causes HiZ corruption on ivb:gt1 */
7393 /* enable HiZ Raw Stall Optimization */
7394 I915_WRITE(CACHE_MODE_0_GEN7,
7395 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7396 }
7397
7398 /* WaDisable4x2SubspanOptimization:ivb */
7399 I915_WRITE(CACHE_MODE_1,
7400 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7401
7402 /*
7403 * BSpec recommends 8x4 when MSAA is used,
7404 * however in practice 16x4 seems fastest.
7405 *
7406 * Note that PS/WM thread counts depend on the WIZ hashing
7407 * disable bit, which we don't touch here, but it's good
7408 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7409 */
7410 I915_WRITE(GEN7_GT_MODE,
7411 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7412
7413 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
7414 snpcr &= ~GEN6_MBC_SNPCR_MASK;
7415 snpcr |= GEN6_MBC_SNPCR_MED;
7416 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
7417
7418 if (!HAS_PCH_NOP(dev_priv))
7419 cpt_init_clock_gating(dev_priv);
7420
7421 gen6_check_mch_setup(dev_priv);
7422 }
7423
7424 static void valleyview_init_clock_gating(struct drm_i915_private *dev_priv)
7425 {
7426 /* WaDisableEarlyCull:vlv */
7427 I915_WRITE(_3D_CHICKEN3,
7428 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7429
7430 /* WaDisableBackToBackFlipFix:vlv */
7431 I915_WRITE(IVB_CHICKEN3,
7432 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7433 CHICKEN3_DGMG_DONE_FIX_DISABLE);
7434
7435 /* WaPsdDispatchEnable:vlv */
7436 /* WaDisablePSDDualDispatchEnable:vlv */
7437 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
7438 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
7439 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
7440
7441 /* WaDisable_RenderCache_OperationalFlush:vlv */
7442 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7443
7444 /* WaForceL3Serialization:vlv */
7445 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7446 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7447
7448 /* WaDisableDopClockGating:vlv */
7449 I915_WRITE(GEN7_ROW_CHICKEN2,
7450 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7451
7452 /* This is required by WaCatErrorRejectionIssue:vlv */
7453 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7454 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7455 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7456
7457 gen7_setup_fixed_func_scheduler(dev_priv);
7458
7459 /*
7460 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
7461 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
7462 */
7463 I915_WRITE(GEN6_UCGCTL2,
7464 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
7465
7466 /* WaDisableL3Bank2xClockGate:vlv
7467 * Disabling L3 clock gating- MMIO 940c[25] = 1
7468 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
7469 I915_WRITE(GEN7_UCGCTL4,
7470 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
7471
7472 /*
7473 * BSpec says this must be set, even though
7474 * WaDisable4x2SubspanOptimization isn't listed for VLV.
7475 */
7476 I915_WRITE(CACHE_MODE_1,
7477 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7478
7479 /*
7480 * BSpec recommends 8x4 when MSAA is used,
7481 * however in practice 16x4 seems fastest.
7482 *
7483 * Note that PS/WM thread counts depend on the WIZ hashing
7484 * disable bit, which we don't touch here, but it's good
7485 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7486 */
7487 I915_WRITE(GEN7_GT_MODE,
7488 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7489
7490 /*
7491 * WaIncreaseL3CreditsForVLVB0:vlv
7492 * This is the hardware default actually.
7493 */
7494 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
7495
7496 /*
7497 * WaDisableVLVClockGating_VBIIssue:vlv
7498 * Disable clock gating on th GCFG unit to prevent a delay
7499 * in the reporting of vblank events.
7500 */
7501 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
7502 }
7503
7504 static void cherryview_init_clock_gating(struct drm_i915_private *dev_priv)
7505 {
7506 /* WaVSRefCountFullforceMissDisable:chv */
7507 /* WaDSRefCountFullforceMissDisable:chv */
7508 I915_WRITE(GEN7_FF_THREAD_MODE,
7509 I915_READ(GEN7_FF_THREAD_MODE) &
7510 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
7511
7512 /* WaDisableSemaphoreAndSyncFlipWait:chv */
7513 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7514 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
7515
7516 /* WaDisableCSUnitClockGating:chv */
7517 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7518 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
7519
7520 /* WaDisableSDEUnitClockGating:chv */
7521 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7522 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7523
7524 /*
7525 * WaProgramL3SqcReg1Default:chv
7526 * See gfxspecs/Related Documents/Performance Guide/
7527 * LSQC Setting Recommendations.
7528 */
7529 gen8_set_l3sqc_credits(dev_priv, 38, 2);
7530
7531 /*
7532 * GTT cache may not work with big pages, so if those
7533 * are ever enabled GTT cache may need to be disabled.
7534 */
7535 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
7536 }
7537
7538 static void g4x_init_clock_gating(struct drm_i915_private *dev_priv)
7539 {
7540 uint32_t dspclk_gate;
7541
7542 I915_WRITE(RENCLK_GATE_D1, 0);
7543 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7544 GS_UNIT_CLOCK_GATE_DISABLE |
7545 CL_UNIT_CLOCK_GATE_DISABLE);
7546 I915_WRITE(RAMCLK_GATE_D, 0);
7547 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7548 OVRUNIT_CLOCK_GATE_DISABLE |
7549 OVCUNIT_CLOCK_GATE_DISABLE;
7550 if (IS_GM45(dev_priv))
7551 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7552 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
7553
7554 /* WaDisableRenderCachePipelinedFlush */
7555 I915_WRITE(CACHE_MODE_0,
7556 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
7557
7558 /* WaDisable_RenderCache_OperationalFlush:g4x */
7559 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7560
7561 g4x_disable_trickle_feed(dev_priv);
7562 }
7563
7564 static void crestline_init_clock_gating(struct drm_i915_private *dev_priv)
7565 {
7566 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7567 I915_WRITE(RENCLK_GATE_D2, 0);
7568 I915_WRITE(DSPCLK_GATE_D, 0);
7569 I915_WRITE(RAMCLK_GATE_D, 0);
7570 I915_WRITE16(DEUC, 0);
7571 I915_WRITE(MI_ARB_STATE,
7572 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7573
7574 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7575 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7576 }
7577
7578 static void broadwater_init_clock_gating(struct drm_i915_private *dev_priv)
7579 {
7580 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7581 I965_RCC_CLOCK_GATE_DISABLE |
7582 I965_RCPB_CLOCK_GATE_DISABLE |
7583 I965_ISC_CLOCK_GATE_DISABLE |
7584 I965_FBC_CLOCK_GATE_DISABLE);
7585 I915_WRITE(RENCLK_GATE_D2, 0);
7586 I915_WRITE(MI_ARB_STATE,
7587 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7588
7589 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7590 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7591 }
7592
7593 static void gen3_init_clock_gating(struct drm_i915_private *dev_priv)
7594 {
7595 u32 dstate = I915_READ(D_STATE);
7596
7597 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7598 DSTATE_DOT_CLOCK_GATING;
7599 I915_WRITE(D_STATE, dstate);
7600
7601 if (IS_PINEVIEW(dev_priv))
7602 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
7603
7604 /* IIR "flip pending" means done if this bit is set */
7605 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
7606
7607 /* interrupts should cause a wake up from C3 */
7608 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
7609
7610 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7611 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
7612
7613 I915_WRITE(MI_ARB_STATE,
7614 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7615 }
7616
7617 static void i85x_init_clock_gating(struct drm_i915_private *dev_priv)
7618 {
7619 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7620
7621 /* interrupts should cause a wake up from C3 */
7622 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7623 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
7624
7625 I915_WRITE(MEM_MODE,
7626 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
7627 }
7628
7629 static void i830_init_clock_gating(struct drm_i915_private *dev_priv)
7630 {
7631 I915_WRITE(MEM_MODE,
7632 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7633 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
7634 }
7635
7636 void intel_init_clock_gating(struct drm_i915_private *dev_priv)
7637 {
7638 dev_priv->display.init_clock_gating(dev_priv);
7639 }
7640
7641 void intel_suspend_hw(struct drm_i915_private *dev_priv)
7642 {
7643 if (HAS_PCH_LPT(dev_priv))
7644 lpt_suspend_hw(dev_priv);
7645 }
7646
7647 static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
7648 {
7649 DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
7650 }
7651
7652 /**
7653 * intel_init_clock_gating_hooks - setup the clock gating hooks
7654 * @dev_priv: device private
7655 *
7656 * Setup the hooks that configure which clocks of a given platform can be
7657 * gated and also apply various GT and display specific workarounds for these
7658 * platforms. Note that some GT specific workarounds are applied separately
7659 * when GPU contexts or batchbuffers start their execution.
7660 */
7661 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
7662 {
7663 if (IS_SKYLAKE(dev_priv))
7664 dev_priv->display.init_clock_gating = skylake_init_clock_gating;
7665 else if (IS_KABYLAKE(dev_priv))
7666 dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
7667 else if (IS_GEN9_LP(dev_priv))
7668 dev_priv->display.init_clock_gating = bxt_init_clock_gating;
7669 else if (IS_BROADWELL(dev_priv))
7670 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7671 else if (IS_CHERRYVIEW(dev_priv))
7672 dev_priv->display.init_clock_gating = cherryview_init_clock_gating;
7673 else if (IS_HASWELL(dev_priv))
7674 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7675 else if (IS_IVYBRIDGE(dev_priv))
7676 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7677 else if (IS_VALLEYVIEW(dev_priv))
7678 dev_priv->display.init_clock_gating = valleyview_init_clock_gating;
7679 else if (IS_GEN6(dev_priv))
7680 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7681 else if (IS_GEN5(dev_priv))
7682 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7683 else if (IS_G4X(dev_priv))
7684 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7685 else if (IS_I965GM(dev_priv))
7686 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7687 else if (IS_I965G(dev_priv))
7688 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7689 else if (IS_GEN3(dev_priv))
7690 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7691 else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
7692 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7693 else if (IS_GEN2(dev_priv))
7694 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7695 else {
7696 MISSING_CASE(INTEL_DEVID(dev_priv));
7697 dev_priv->display.init_clock_gating = nop_init_clock_gating;
7698 }
7699 }
7700
7701 /* Set up chip specific power management-related functions */
7702 void intel_init_pm(struct drm_i915_private *dev_priv)
7703 {
7704 intel_fbc_init(dev_priv);
7705
7706 /* For cxsr */
7707 if (IS_PINEVIEW(dev_priv))
7708 i915_pineview_get_mem_freq(dev_priv);
7709 else if (IS_GEN5(dev_priv))
7710 i915_ironlake_get_mem_freq(dev_priv);
7711
7712 /* For FIFO watermark updates */
7713 if (INTEL_GEN(dev_priv) >= 9) {
7714 skl_setup_wm_latency(dev_priv);
7715 dev_priv->display.initial_watermarks = skl_initial_wm;
7716 dev_priv->display.atomic_update_watermarks = skl_atomic_update_crtc_wm;
7717 dev_priv->display.compute_global_watermarks = skl_compute_wm;
7718 } else if (HAS_PCH_SPLIT(dev_priv)) {
7719 ilk_setup_wm_latency(dev_priv);
7720
7721 if ((IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[1] &&
7722 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7723 (!IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[0] &&
7724 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
7725 dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
7726 dev_priv->display.compute_intermediate_wm =
7727 ilk_compute_intermediate_wm;
7728 dev_priv->display.initial_watermarks =
7729 ilk_initial_watermarks;
7730 dev_priv->display.optimize_watermarks =
7731 ilk_optimize_watermarks;
7732 } else {
7733 DRM_DEBUG_KMS("Failed to read display plane latency. "
7734 "Disable CxSR\n");
7735 }
7736 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
7737 vlv_setup_wm_latency(dev_priv);
7738 dev_priv->display.update_wm = vlv_update_wm;
7739 } else if (IS_PINEVIEW(dev_priv)) {
7740 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
7741 dev_priv->is_ddr3,
7742 dev_priv->fsb_freq,
7743 dev_priv->mem_freq)) {
7744 DRM_INFO("failed to find known CxSR latency "
7745 "(found ddr%s fsb freq %d, mem freq %d), "
7746 "disabling CxSR\n",
7747 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7748 dev_priv->fsb_freq, dev_priv->mem_freq);
7749 /* Disable CxSR and never update its watermark again */
7750 intel_set_memory_cxsr(dev_priv, false);
7751 dev_priv->display.update_wm = NULL;
7752 } else
7753 dev_priv->display.update_wm = pineview_update_wm;
7754 } else if (IS_G4X(dev_priv)) {
7755 dev_priv->display.update_wm = g4x_update_wm;
7756 } else if (IS_GEN4(dev_priv)) {
7757 dev_priv->display.update_wm = i965_update_wm;
7758 } else if (IS_GEN3(dev_priv)) {
7759 dev_priv->display.update_wm = i9xx_update_wm;
7760 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7761 } else if (IS_GEN2(dev_priv)) {
7762 if (INTEL_INFO(dev_priv)->num_pipes == 1) {
7763 dev_priv->display.update_wm = i845_update_wm;
7764 dev_priv->display.get_fifo_size = i845_get_fifo_size;
7765 } else {
7766 dev_priv->display.update_wm = i9xx_update_wm;
7767 dev_priv->display.get_fifo_size = i830_get_fifo_size;
7768 }
7769 } else {
7770 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
7771 }
7772 }
7773
7774 static inline int gen6_check_mailbox_status(struct drm_i915_private *dev_priv)
7775 {
7776 uint32_t flags =
7777 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
7778
7779 switch (flags) {
7780 case GEN6_PCODE_SUCCESS:
7781 return 0;
7782 case GEN6_PCODE_UNIMPLEMENTED_CMD:
7783 case GEN6_PCODE_ILLEGAL_CMD:
7784 return -ENXIO;
7785 case GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7786 case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7787 return -EOVERFLOW;
7788 case GEN6_PCODE_TIMEOUT:
7789 return -ETIMEDOUT;
7790 default:
7791 MISSING_CASE(flags)
7792 return 0;
7793 }
7794 }
7795
7796 static inline int gen7_check_mailbox_status(struct drm_i915_private *dev_priv)
7797 {
7798 uint32_t flags =
7799 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
7800
7801 switch (flags) {
7802 case GEN6_PCODE_SUCCESS:
7803 return 0;
7804 case GEN6_PCODE_ILLEGAL_CMD:
7805 return -ENXIO;
7806 case GEN7_PCODE_TIMEOUT:
7807 return -ETIMEDOUT;
7808 case GEN7_PCODE_ILLEGAL_DATA:
7809 return -EINVAL;
7810 case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7811 return -EOVERFLOW;
7812 default:
7813 MISSING_CASE(flags);
7814 return 0;
7815 }
7816 }
7817
7818 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
7819 {
7820 int status;
7821
7822 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7823
7824 /* GEN6_PCODE_* are outside of the forcewake domain, we can
7825 * use te fw I915_READ variants to reduce the amount of work
7826 * required when reading/writing.
7827 */
7828
7829 if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7830 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7831 return -EAGAIN;
7832 }
7833
7834 I915_WRITE_FW(GEN6_PCODE_DATA, *val);
7835 I915_WRITE_FW(GEN6_PCODE_DATA1, 0);
7836 I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7837
7838 if (intel_wait_for_register_fw(dev_priv,
7839 GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7840 500)) {
7841 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7842 return -ETIMEDOUT;
7843 }
7844
7845 *val = I915_READ_FW(GEN6_PCODE_DATA);
7846 I915_WRITE_FW(GEN6_PCODE_DATA, 0);
7847
7848 if (INTEL_GEN(dev_priv) > 6)
7849 status = gen7_check_mailbox_status(dev_priv);
7850 else
7851 status = gen6_check_mailbox_status(dev_priv);
7852
7853 if (status) {
7854 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed: %d\n",
7855 status);
7856 return status;
7857 }
7858
7859 return 0;
7860 }
7861
7862 int sandybridge_pcode_write(struct drm_i915_private *dev_priv,
7863 u32 mbox, u32 val)
7864 {
7865 int status;
7866
7867 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7868
7869 /* GEN6_PCODE_* are outside of the forcewake domain, we can
7870 * use te fw I915_READ variants to reduce the amount of work
7871 * required when reading/writing.
7872 */
7873
7874 if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7875 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7876 return -EAGAIN;
7877 }
7878
7879 I915_WRITE_FW(GEN6_PCODE_DATA, val);
7880 I915_WRITE_FW(GEN6_PCODE_DATA1, 0);
7881 I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7882
7883 if (intel_wait_for_register_fw(dev_priv,
7884 GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7885 500)) {
7886 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7887 return -ETIMEDOUT;
7888 }
7889
7890 I915_WRITE_FW(GEN6_PCODE_DATA, 0);
7891
7892 if (INTEL_GEN(dev_priv) > 6)
7893 status = gen7_check_mailbox_status(dev_priv);
7894 else
7895 status = gen6_check_mailbox_status(dev_priv);
7896
7897 if (status) {
7898 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed: %d\n",
7899 status);
7900 return status;
7901 }
7902
7903 return 0;
7904 }
7905
7906 static bool skl_pcode_try_request(struct drm_i915_private *dev_priv, u32 mbox,
7907 u32 request, u32 reply_mask, u32 reply,
7908 u32 *status)
7909 {
7910 u32 val = request;
7911
7912 *status = sandybridge_pcode_read(dev_priv, mbox, &val);
7913
7914 return *status || ((val & reply_mask) == reply);
7915 }
7916
7917 /**
7918 * skl_pcode_request - send PCODE request until acknowledgment
7919 * @dev_priv: device private
7920 * @mbox: PCODE mailbox ID the request is targeted for
7921 * @request: request ID
7922 * @reply_mask: mask used to check for request acknowledgment
7923 * @reply: value used to check for request acknowledgment
7924 * @timeout_base_ms: timeout for polling with preemption enabled
7925 *
7926 * Keep resending the @request to @mbox until PCODE acknowledges it, PCODE
7927 * reports an error or an overall timeout of @timeout_base_ms+50 ms expires.
7928 * The request is acknowledged once the PCODE reply dword equals @reply after
7929 * applying @reply_mask. Polling is first attempted with preemption enabled
7930 * for @timeout_base_ms and if this times out for another 50 ms with
7931 * preemption disabled.
7932 *
7933 * Returns 0 on success, %-ETIMEDOUT in case of a timeout, <0 in case of some
7934 * other error as reported by PCODE.
7935 */
7936 int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
7937 u32 reply_mask, u32 reply, int timeout_base_ms)
7938 {
7939 u32 status;
7940 int ret;
7941
7942 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7943
7944 #define COND skl_pcode_try_request(dev_priv, mbox, request, reply_mask, reply, \
7945 &status)
7946
7947 /*
7948 * Prime the PCODE by doing a request first. Normally it guarantees
7949 * that a subsequent request, at most @timeout_base_ms later, succeeds.
7950 * _wait_for() doesn't guarantee when its passed condition is evaluated
7951 * first, so send the first request explicitly.
7952 */
7953 if (COND) {
7954 ret = 0;
7955 goto out;
7956 }
7957 ret = _wait_for(COND, timeout_base_ms * 1000, 10);
7958 if (!ret)
7959 goto out;
7960
7961 /*
7962 * The above can time out if the number of requests was low (2 in the
7963 * worst case) _and_ PCODE was busy for some reason even after a
7964 * (queued) request and @timeout_base_ms delay. As a workaround retry
7965 * the poll with preemption disabled to maximize the number of
7966 * requests. Increase the timeout from @timeout_base_ms to 50ms to
7967 * account for interrupts that could reduce the number of these
7968 * requests, and for any quirks of the PCODE firmware that delays
7969 * the request completion.
7970 */
7971 DRM_DEBUG_KMS("PCODE timeout, retrying with preemption disabled\n");
7972 WARN_ON_ONCE(timeout_base_ms > 3);
7973 preempt_disable();
7974 ret = wait_for_atomic(COND, 50);
7975 preempt_enable();
7976
7977 out:
7978 return ret ? ret : status;
7979 #undef COND
7980 }
7981
7982 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7983 {
7984 /*
7985 * N = val - 0xb7
7986 * Slow = Fast = GPLL ref * N
7987 */
7988 return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * (val - 0xb7), 1000);
7989 }
7990
7991 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
7992 {
7993 return DIV_ROUND_CLOSEST(1000 * val, dev_priv->rps.gpll_ref_freq) + 0xb7;
7994 }
7995
7996 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7997 {
7998 /*
7999 * N = val / 2
8000 * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
8001 */
8002 return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * val, 2 * 2 * 1000);
8003 }
8004
8005 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
8006 {
8007 /* CHV needs even values */
8008 return DIV_ROUND_CLOSEST(2 * 1000 * val, dev_priv->rps.gpll_ref_freq) * 2;
8009 }
8010
8011 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
8012 {
8013 if (IS_GEN9(dev_priv))
8014 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
8015 GEN9_FREQ_SCALER);
8016 else if (IS_CHERRYVIEW(dev_priv))
8017 return chv_gpu_freq(dev_priv, val);
8018 else if (IS_VALLEYVIEW(dev_priv))
8019 return byt_gpu_freq(dev_priv, val);
8020 else
8021 return val * GT_FREQUENCY_MULTIPLIER;
8022 }
8023
8024 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
8025 {
8026 if (IS_GEN9(dev_priv))
8027 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
8028 GT_FREQUENCY_MULTIPLIER);
8029 else if (IS_CHERRYVIEW(dev_priv))
8030 return chv_freq_opcode(dev_priv, val);
8031 else if (IS_VALLEYVIEW(dev_priv))
8032 return byt_freq_opcode(dev_priv, val);
8033 else
8034 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
8035 }
8036
8037 struct request_boost {
8038 struct work_struct work;
8039 struct drm_i915_gem_request *req;
8040 };
8041
8042 static void __intel_rps_boost_work(struct work_struct *work)
8043 {
8044 struct request_boost *boost = container_of(work, struct request_boost, work);
8045 struct drm_i915_gem_request *req = boost->req;
8046
8047 if (!i915_gem_request_completed(req))
8048 gen6_rps_boost(req->i915, NULL, req->emitted_jiffies);
8049
8050 i915_gem_request_put(req);
8051 kfree(boost);
8052 }
8053
8054 void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req)
8055 {
8056 struct request_boost *boost;
8057
8058 if (req == NULL || INTEL_GEN(req->i915) < 6)
8059 return;
8060
8061 if (i915_gem_request_completed(req))
8062 return;
8063
8064 boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
8065 if (boost == NULL)
8066 return;
8067
8068 boost->req = i915_gem_request_get(req);
8069
8070 INIT_WORK(&boost->work, __intel_rps_boost_work);
8071 queue_work(req->i915->wq, &boost->work);
8072 }
8073
8074 void intel_pm_setup(struct drm_i915_private *dev_priv)
8075 {
8076 mutex_init(&dev_priv->rps.hw_lock);
8077 spin_lock_init(&dev_priv->rps.client_lock);
8078
8079 INIT_DELAYED_WORK(&dev_priv->rps.autoenable_work,
8080 __intel_autoenable_gt_powersave);
8081 INIT_LIST_HEAD(&dev_priv->rps.clients);
8082
8083 dev_priv->pm.suspended = false;
8084 atomic_set(&dev_priv->pm.wakeref_count, 0);
8085 }
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