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Merge tag 'v3.6-rc2' into drm-intel-next
[thirdparty/linux.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
1 /*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
30 #include "drmP.h"
31 #include "drm.h"
32 #include "i915_drv.h"
33 #include "i915_drm.h"
34 #include "i915_trace.h"
35 #include "intel_drv.h"
36
37 /*
38 * 965+ support PIPE_CONTROL commands, which provide finer grained control
39 * over cache flushing.
40 */
41 struct pipe_control {
42 struct drm_i915_gem_object *obj;
43 volatile u32 *cpu_page;
44 u32 gtt_offset;
45 };
46
47 static inline int ring_space(struct intel_ring_buffer *ring)
48 {
49 int space = (ring->head & HEAD_ADDR) - (ring->tail + 8);
50 if (space < 0)
51 space += ring->size;
52 return space;
53 }
54
55 static int
56 gen2_render_ring_flush(struct intel_ring_buffer *ring,
57 u32 invalidate_domains,
58 u32 flush_domains)
59 {
60 u32 cmd;
61 int ret;
62
63 cmd = MI_FLUSH;
64 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
65 cmd |= MI_NO_WRITE_FLUSH;
66
67 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
68 cmd |= MI_READ_FLUSH;
69
70 ret = intel_ring_begin(ring, 2);
71 if (ret)
72 return ret;
73
74 intel_ring_emit(ring, cmd);
75 intel_ring_emit(ring, MI_NOOP);
76 intel_ring_advance(ring);
77
78 return 0;
79 }
80
81 static int
82 gen4_render_ring_flush(struct intel_ring_buffer *ring,
83 u32 invalidate_domains,
84 u32 flush_domains)
85 {
86 struct drm_device *dev = ring->dev;
87 u32 cmd;
88 int ret;
89
90 /*
91 * read/write caches:
92 *
93 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
94 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
95 * also flushed at 2d versus 3d pipeline switches.
96 *
97 * read-only caches:
98 *
99 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
100 * MI_READ_FLUSH is set, and is always flushed on 965.
101 *
102 * I915_GEM_DOMAIN_COMMAND may not exist?
103 *
104 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
105 * invalidated when MI_EXE_FLUSH is set.
106 *
107 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
108 * invalidated with every MI_FLUSH.
109 *
110 * TLBs:
111 *
112 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
113 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
114 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
115 * are flushed at any MI_FLUSH.
116 */
117
118 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
119 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
120 cmd &= ~MI_NO_WRITE_FLUSH;
121 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
122 cmd |= MI_EXE_FLUSH;
123
124 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
125 (IS_G4X(dev) || IS_GEN5(dev)))
126 cmd |= MI_INVALIDATE_ISP;
127
128 ret = intel_ring_begin(ring, 2);
129 if (ret)
130 return ret;
131
132 intel_ring_emit(ring, cmd);
133 intel_ring_emit(ring, MI_NOOP);
134 intel_ring_advance(ring);
135
136 return 0;
137 }
138
139 /**
140 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
141 * implementing two workarounds on gen6. From section 1.4.7.1
142 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
143 *
144 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
145 * produced by non-pipelined state commands), software needs to first
146 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
147 * 0.
148 *
149 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
150 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
151 *
152 * And the workaround for these two requires this workaround first:
153 *
154 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
155 * BEFORE the pipe-control with a post-sync op and no write-cache
156 * flushes.
157 *
158 * And this last workaround is tricky because of the requirements on
159 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
160 * volume 2 part 1:
161 *
162 * "1 of the following must also be set:
163 * - Render Target Cache Flush Enable ([12] of DW1)
164 * - Depth Cache Flush Enable ([0] of DW1)
165 * - Stall at Pixel Scoreboard ([1] of DW1)
166 * - Depth Stall ([13] of DW1)
167 * - Post-Sync Operation ([13] of DW1)
168 * - Notify Enable ([8] of DW1)"
169 *
170 * The cache flushes require the workaround flush that triggered this
171 * one, so we can't use it. Depth stall would trigger the same.
172 * Post-sync nonzero is what triggered this second workaround, so we
173 * can't use that one either. Notify enable is IRQs, which aren't
174 * really our business. That leaves only stall at scoreboard.
175 */
176 static int
177 intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring)
178 {
179 struct pipe_control *pc = ring->private;
180 u32 scratch_addr = pc->gtt_offset + 128;
181 int ret;
182
183
184 ret = intel_ring_begin(ring, 6);
185 if (ret)
186 return ret;
187
188 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
189 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
190 PIPE_CONTROL_STALL_AT_SCOREBOARD);
191 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
192 intel_ring_emit(ring, 0); /* low dword */
193 intel_ring_emit(ring, 0); /* high dword */
194 intel_ring_emit(ring, MI_NOOP);
195 intel_ring_advance(ring);
196
197 ret = intel_ring_begin(ring, 6);
198 if (ret)
199 return ret;
200
201 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
202 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
203 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
204 intel_ring_emit(ring, 0);
205 intel_ring_emit(ring, 0);
206 intel_ring_emit(ring, MI_NOOP);
207 intel_ring_advance(ring);
208
209 return 0;
210 }
211
212 static int
213 gen6_render_ring_flush(struct intel_ring_buffer *ring,
214 u32 invalidate_domains, u32 flush_domains)
215 {
216 u32 flags = 0;
217 struct pipe_control *pc = ring->private;
218 u32 scratch_addr = pc->gtt_offset + 128;
219 int ret;
220
221 /* Just flush everything. Experiments have shown that reducing the
222 * number of bits based on the write domains has little performance
223 * impact.
224 */
225 if (flush_domains) {
226 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
227 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
228 /*
229 * Ensure that any following seqno writes only happen
230 * when the render cache is indeed flushed.
231 */
232 flags |= PIPE_CONTROL_CS_STALL;
233 }
234 if (invalidate_domains) {
235 flags |= PIPE_CONTROL_TLB_INVALIDATE;
236 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
237 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
238 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
239 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
240 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
241 /*
242 * TLB invalidate requires a post-sync write.
243 */
244 flags |= PIPE_CONTROL_QW_WRITE;
245 }
246
247 ret = intel_ring_begin(ring, 4);
248 if (ret)
249 return ret;
250
251 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
252 intel_ring_emit(ring, flags);
253 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
254 intel_ring_emit(ring, 0);
255 intel_ring_advance(ring);
256
257 return 0;
258 }
259
260 static int
261 gen6_render_ring_flush__wa(struct intel_ring_buffer *ring,
262 u32 invalidate_domains, u32 flush_domains)
263 {
264 int ret;
265
266 /* Force SNB workarounds for PIPE_CONTROL flushes */
267 ret = intel_emit_post_sync_nonzero_flush(ring);
268 if (ret)
269 return ret;
270
271 return gen6_render_ring_flush(ring, invalidate_domains, flush_domains);
272 }
273
274 static void ring_write_tail(struct intel_ring_buffer *ring,
275 u32 value)
276 {
277 drm_i915_private_t *dev_priv = ring->dev->dev_private;
278 I915_WRITE_TAIL(ring, value);
279 }
280
281 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
282 {
283 drm_i915_private_t *dev_priv = ring->dev->dev_private;
284 u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
285 RING_ACTHD(ring->mmio_base) : ACTHD;
286
287 return I915_READ(acthd_reg);
288 }
289
290 static int init_ring_common(struct intel_ring_buffer *ring)
291 {
292 struct drm_device *dev = ring->dev;
293 drm_i915_private_t *dev_priv = dev->dev_private;
294 struct drm_i915_gem_object *obj = ring->obj;
295 int ret = 0;
296 u32 head;
297
298 if (HAS_FORCE_WAKE(dev))
299 gen6_gt_force_wake_get(dev_priv);
300
301 /* Stop the ring if it's running. */
302 I915_WRITE_CTL(ring, 0);
303 I915_WRITE_HEAD(ring, 0);
304 ring->write_tail(ring, 0);
305
306 head = I915_READ_HEAD(ring) & HEAD_ADDR;
307
308 /* G45 ring initialization fails to reset head to zero */
309 if (head != 0) {
310 DRM_DEBUG_KMS("%s head not reset to zero "
311 "ctl %08x head %08x tail %08x start %08x\n",
312 ring->name,
313 I915_READ_CTL(ring),
314 I915_READ_HEAD(ring),
315 I915_READ_TAIL(ring),
316 I915_READ_START(ring));
317
318 I915_WRITE_HEAD(ring, 0);
319
320 if (I915_READ_HEAD(ring) & HEAD_ADDR) {
321 DRM_ERROR("failed to set %s head to zero "
322 "ctl %08x head %08x tail %08x start %08x\n",
323 ring->name,
324 I915_READ_CTL(ring),
325 I915_READ_HEAD(ring),
326 I915_READ_TAIL(ring),
327 I915_READ_START(ring));
328 }
329 }
330
331 /* Initialize the ring. This must happen _after_ we've cleared the ring
332 * registers with the above sequence (the readback of the HEAD registers
333 * also enforces ordering), otherwise the hw might lose the new ring
334 * register values. */
335 I915_WRITE_START(ring, obj->gtt_offset);
336 I915_WRITE_CTL(ring,
337 ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
338 | RING_VALID);
339
340 /* If the head is still not zero, the ring is dead */
341 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
342 I915_READ_START(ring) == obj->gtt_offset &&
343 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
344 DRM_ERROR("%s initialization failed "
345 "ctl %08x head %08x tail %08x start %08x\n",
346 ring->name,
347 I915_READ_CTL(ring),
348 I915_READ_HEAD(ring),
349 I915_READ_TAIL(ring),
350 I915_READ_START(ring));
351 ret = -EIO;
352 goto out;
353 }
354
355 if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
356 i915_kernel_lost_context(ring->dev);
357 else {
358 ring->head = I915_READ_HEAD(ring);
359 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
360 ring->space = ring_space(ring);
361 ring->last_retired_head = -1;
362 }
363
364 out:
365 if (HAS_FORCE_WAKE(dev))
366 gen6_gt_force_wake_put(dev_priv);
367
368 return ret;
369 }
370
371 static int
372 init_pipe_control(struct intel_ring_buffer *ring)
373 {
374 struct pipe_control *pc;
375 struct drm_i915_gem_object *obj;
376 int ret;
377
378 if (ring->private)
379 return 0;
380
381 pc = kmalloc(sizeof(*pc), GFP_KERNEL);
382 if (!pc)
383 return -ENOMEM;
384
385 obj = i915_gem_alloc_object(ring->dev, 4096);
386 if (obj == NULL) {
387 DRM_ERROR("Failed to allocate seqno page\n");
388 ret = -ENOMEM;
389 goto err;
390 }
391
392 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
393
394 ret = i915_gem_object_pin(obj, 4096, true);
395 if (ret)
396 goto err_unref;
397
398 pc->gtt_offset = obj->gtt_offset;
399 pc->cpu_page = kmap(obj->pages[0]);
400 if (pc->cpu_page == NULL)
401 goto err_unpin;
402
403 pc->obj = obj;
404 ring->private = pc;
405 return 0;
406
407 err_unpin:
408 i915_gem_object_unpin(obj);
409 err_unref:
410 drm_gem_object_unreference(&obj->base);
411 err:
412 kfree(pc);
413 return ret;
414 }
415
416 static void
417 cleanup_pipe_control(struct intel_ring_buffer *ring)
418 {
419 struct pipe_control *pc = ring->private;
420 struct drm_i915_gem_object *obj;
421
422 if (!ring->private)
423 return;
424
425 obj = pc->obj;
426 kunmap(obj->pages[0]);
427 i915_gem_object_unpin(obj);
428 drm_gem_object_unreference(&obj->base);
429
430 kfree(pc);
431 ring->private = NULL;
432 }
433
434 static int init_render_ring(struct intel_ring_buffer *ring)
435 {
436 struct drm_device *dev = ring->dev;
437 struct drm_i915_private *dev_priv = dev->dev_private;
438 int ret = init_ring_common(ring);
439
440 if (INTEL_INFO(dev)->gen > 3) {
441 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
442 if (IS_GEN7(dev))
443 I915_WRITE(GFX_MODE_GEN7,
444 _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
445 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
446 }
447
448 if (INTEL_INFO(dev)->gen >= 5) {
449 ret = init_pipe_control(ring);
450 if (ret)
451 return ret;
452 }
453
454 if (IS_GEN6(dev)) {
455 /* From the Sandybridge PRM, volume 1 part 3, page 24:
456 * "If this bit is set, STCunit will have LRA as replacement
457 * policy. [...] This bit must be reset. LRA replacement
458 * policy is not supported."
459 */
460 I915_WRITE(CACHE_MODE_0,
461 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
462
463 /* This is not explicitly set for GEN6, so read the register.
464 * see intel_ring_mi_set_context() for why we care.
465 * TODO: consider explicitly setting the bit for GEN5
466 */
467 ring->itlb_before_ctx_switch =
468 !!(I915_READ(GFX_MODE) & GFX_TLB_INVALIDATE_ALWAYS);
469 }
470
471 if (INTEL_INFO(dev)->gen >= 6)
472 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
473
474 if (HAS_L3_GPU_CACHE(dev))
475 I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR);
476
477 return ret;
478 }
479
480 static void render_ring_cleanup(struct intel_ring_buffer *ring)
481 {
482 if (!ring->private)
483 return;
484
485 cleanup_pipe_control(ring);
486 }
487
488 static void
489 update_mboxes(struct intel_ring_buffer *ring,
490 u32 seqno,
491 u32 mmio_offset)
492 {
493 intel_ring_emit(ring, MI_SEMAPHORE_MBOX |
494 MI_SEMAPHORE_GLOBAL_GTT |
495 MI_SEMAPHORE_REGISTER |
496 MI_SEMAPHORE_UPDATE);
497 intel_ring_emit(ring, seqno);
498 intel_ring_emit(ring, mmio_offset);
499 }
500
501 /**
502 * gen6_add_request - Update the semaphore mailbox registers
503 *
504 * @ring - ring that is adding a request
505 * @seqno - return seqno stuck into the ring
506 *
507 * Update the mailbox registers in the *other* rings with the current seqno.
508 * This acts like a signal in the canonical semaphore.
509 */
510 static int
511 gen6_add_request(struct intel_ring_buffer *ring,
512 u32 *seqno)
513 {
514 u32 mbox1_reg;
515 u32 mbox2_reg;
516 int ret;
517
518 ret = intel_ring_begin(ring, 10);
519 if (ret)
520 return ret;
521
522 mbox1_reg = ring->signal_mbox[0];
523 mbox2_reg = ring->signal_mbox[1];
524
525 *seqno = i915_gem_next_request_seqno(ring);
526
527 update_mboxes(ring, *seqno, mbox1_reg);
528 update_mboxes(ring, *seqno, mbox2_reg);
529 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
530 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
531 intel_ring_emit(ring, *seqno);
532 intel_ring_emit(ring, MI_USER_INTERRUPT);
533 intel_ring_advance(ring);
534
535 return 0;
536 }
537
538 /**
539 * intel_ring_sync - sync the waiter to the signaller on seqno
540 *
541 * @waiter - ring that is waiting
542 * @signaller - ring which has, or will signal
543 * @seqno - seqno which the waiter will block on
544 */
545 static int
546 gen6_ring_sync(struct intel_ring_buffer *waiter,
547 struct intel_ring_buffer *signaller,
548 u32 seqno)
549 {
550 int ret;
551 u32 dw1 = MI_SEMAPHORE_MBOX |
552 MI_SEMAPHORE_COMPARE |
553 MI_SEMAPHORE_REGISTER;
554
555 /* Throughout all of the GEM code, seqno passed implies our current
556 * seqno is >= the last seqno executed. However for hardware the
557 * comparison is strictly greater than.
558 */
559 seqno -= 1;
560
561 WARN_ON(signaller->semaphore_register[waiter->id] ==
562 MI_SEMAPHORE_SYNC_INVALID);
563
564 ret = intel_ring_begin(waiter, 4);
565 if (ret)
566 return ret;
567
568 intel_ring_emit(waiter,
569 dw1 | signaller->semaphore_register[waiter->id]);
570 intel_ring_emit(waiter, seqno);
571 intel_ring_emit(waiter, 0);
572 intel_ring_emit(waiter, MI_NOOP);
573 intel_ring_advance(waiter);
574
575 return 0;
576 }
577
578 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
579 do { \
580 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
581 PIPE_CONTROL_DEPTH_STALL); \
582 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
583 intel_ring_emit(ring__, 0); \
584 intel_ring_emit(ring__, 0); \
585 } while (0)
586
587 static int
588 pc_render_add_request(struct intel_ring_buffer *ring,
589 u32 *result)
590 {
591 u32 seqno = i915_gem_next_request_seqno(ring);
592 struct pipe_control *pc = ring->private;
593 u32 scratch_addr = pc->gtt_offset + 128;
594 int ret;
595
596 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
597 * incoherent with writes to memory, i.e. completely fubar,
598 * so we need to use PIPE_NOTIFY instead.
599 *
600 * However, we also need to workaround the qword write
601 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
602 * memory before requesting an interrupt.
603 */
604 ret = intel_ring_begin(ring, 32);
605 if (ret)
606 return ret;
607
608 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
609 PIPE_CONTROL_WRITE_FLUSH |
610 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
611 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
612 intel_ring_emit(ring, seqno);
613 intel_ring_emit(ring, 0);
614 PIPE_CONTROL_FLUSH(ring, scratch_addr);
615 scratch_addr += 128; /* write to separate cachelines */
616 PIPE_CONTROL_FLUSH(ring, scratch_addr);
617 scratch_addr += 128;
618 PIPE_CONTROL_FLUSH(ring, scratch_addr);
619 scratch_addr += 128;
620 PIPE_CONTROL_FLUSH(ring, scratch_addr);
621 scratch_addr += 128;
622 PIPE_CONTROL_FLUSH(ring, scratch_addr);
623 scratch_addr += 128;
624 PIPE_CONTROL_FLUSH(ring, scratch_addr);
625
626 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
627 PIPE_CONTROL_WRITE_FLUSH |
628 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
629 PIPE_CONTROL_NOTIFY);
630 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
631 intel_ring_emit(ring, seqno);
632 intel_ring_emit(ring, 0);
633 intel_ring_advance(ring);
634
635 *result = seqno;
636 return 0;
637 }
638
639 static u32
640 gen6_ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
641 {
642 /* Workaround to force correct ordering between irq and seqno writes on
643 * ivb (and maybe also on snb) by reading from a CS register (like
644 * ACTHD) before reading the status page. */
645 if (!lazy_coherency)
646 intel_ring_get_active_head(ring);
647 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
648 }
649
650 static u32
651 ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
652 {
653 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
654 }
655
656 static u32
657 pc_render_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
658 {
659 struct pipe_control *pc = ring->private;
660 return pc->cpu_page[0];
661 }
662
663 static bool
664 gen5_ring_get_irq(struct intel_ring_buffer *ring)
665 {
666 struct drm_device *dev = ring->dev;
667 drm_i915_private_t *dev_priv = dev->dev_private;
668 unsigned long flags;
669
670 if (!dev->irq_enabled)
671 return false;
672
673 spin_lock_irqsave(&dev_priv->irq_lock, flags);
674 if (ring->irq_refcount++ == 0) {
675 dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
676 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
677 POSTING_READ(GTIMR);
678 }
679 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
680
681 return true;
682 }
683
684 static void
685 gen5_ring_put_irq(struct intel_ring_buffer *ring)
686 {
687 struct drm_device *dev = ring->dev;
688 drm_i915_private_t *dev_priv = dev->dev_private;
689 unsigned long flags;
690
691 spin_lock_irqsave(&dev_priv->irq_lock, flags);
692 if (--ring->irq_refcount == 0) {
693 dev_priv->gt_irq_mask |= ring->irq_enable_mask;
694 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
695 POSTING_READ(GTIMR);
696 }
697 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
698 }
699
700 static bool
701 i9xx_ring_get_irq(struct intel_ring_buffer *ring)
702 {
703 struct drm_device *dev = ring->dev;
704 drm_i915_private_t *dev_priv = dev->dev_private;
705 unsigned long flags;
706
707 if (!dev->irq_enabled)
708 return false;
709
710 spin_lock_irqsave(&dev_priv->irq_lock, flags);
711 if (ring->irq_refcount++ == 0) {
712 dev_priv->irq_mask &= ~ring->irq_enable_mask;
713 I915_WRITE(IMR, dev_priv->irq_mask);
714 POSTING_READ(IMR);
715 }
716 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
717
718 return true;
719 }
720
721 static void
722 i9xx_ring_put_irq(struct intel_ring_buffer *ring)
723 {
724 struct drm_device *dev = ring->dev;
725 drm_i915_private_t *dev_priv = dev->dev_private;
726 unsigned long flags;
727
728 spin_lock_irqsave(&dev_priv->irq_lock, flags);
729 if (--ring->irq_refcount == 0) {
730 dev_priv->irq_mask |= ring->irq_enable_mask;
731 I915_WRITE(IMR, dev_priv->irq_mask);
732 POSTING_READ(IMR);
733 }
734 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
735 }
736
737 static bool
738 i8xx_ring_get_irq(struct intel_ring_buffer *ring)
739 {
740 struct drm_device *dev = ring->dev;
741 drm_i915_private_t *dev_priv = dev->dev_private;
742 unsigned long flags;
743
744 if (!dev->irq_enabled)
745 return false;
746
747 spin_lock_irqsave(&dev_priv->irq_lock, flags);
748 if (ring->irq_refcount++ == 0) {
749 dev_priv->irq_mask &= ~ring->irq_enable_mask;
750 I915_WRITE16(IMR, dev_priv->irq_mask);
751 POSTING_READ16(IMR);
752 }
753 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
754
755 return true;
756 }
757
758 static void
759 i8xx_ring_put_irq(struct intel_ring_buffer *ring)
760 {
761 struct drm_device *dev = ring->dev;
762 drm_i915_private_t *dev_priv = dev->dev_private;
763 unsigned long flags;
764
765 spin_lock_irqsave(&dev_priv->irq_lock, flags);
766 if (--ring->irq_refcount == 0) {
767 dev_priv->irq_mask |= ring->irq_enable_mask;
768 I915_WRITE16(IMR, dev_priv->irq_mask);
769 POSTING_READ16(IMR);
770 }
771 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
772 }
773
774 void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
775 {
776 struct drm_device *dev = ring->dev;
777 drm_i915_private_t *dev_priv = ring->dev->dev_private;
778 u32 mmio = 0;
779
780 /* The ring status page addresses are no longer next to the rest of
781 * the ring registers as of gen7.
782 */
783 if (IS_GEN7(dev)) {
784 switch (ring->id) {
785 case RCS:
786 mmio = RENDER_HWS_PGA_GEN7;
787 break;
788 case BCS:
789 mmio = BLT_HWS_PGA_GEN7;
790 break;
791 case VCS:
792 mmio = BSD_HWS_PGA_GEN7;
793 break;
794 }
795 } else if (IS_GEN6(ring->dev)) {
796 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
797 } else {
798 mmio = RING_HWS_PGA(ring->mmio_base);
799 }
800
801 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
802 POSTING_READ(mmio);
803 }
804
805 static int
806 bsd_ring_flush(struct intel_ring_buffer *ring,
807 u32 invalidate_domains,
808 u32 flush_domains)
809 {
810 int ret;
811
812 ret = intel_ring_begin(ring, 2);
813 if (ret)
814 return ret;
815
816 intel_ring_emit(ring, MI_FLUSH);
817 intel_ring_emit(ring, MI_NOOP);
818 intel_ring_advance(ring);
819 return 0;
820 }
821
822 static int
823 i9xx_add_request(struct intel_ring_buffer *ring,
824 u32 *result)
825 {
826 u32 seqno;
827 int ret;
828
829 ret = intel_ring_begin(ring, 4);
830 if (ret)
831 return ret;
832
833 seqno = i915_gem_next_request_seqno(ring);
834
835 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
836 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
837 intel_ring_emit(ring, seqno);
838 intel_ring_emit(ring, MI_USER_INTERRUPT);
839 intel_ring_advance(ring);
840
841 *result = seqno;
842 return 0;
843 }
844
845 static bool
846 gen6_ring_get_irq(struct intel_ring_buffer *ring)
847 {
848 struct drm_device *dev = ring->dev;
849 drm_i915_private_t *dev_priv = dev->dev_private;
850 unsigned long flags;
851
852 if (!dev->irq_enabled)
853 return false;
854
855 /* It looks like we need to prevent the gt from suspending while waiting
856 * for an notifiy irq, otherwise irqs seem to get lost on at least the
857 * blt/bsd rings on ivb. */
858 gen6_gt_force_wake_get(dev_priv);
859
860 spin_lock_irqsave(&dev_priv->irq_lock, flags);
861 if (ring->irq_refcount++ == 0) {
862 if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
863 I915_WRITE_IMR(ring, ~(ring->irq_enable_mask |
864 GEN6_RENDER_L3_PARITY_ERROR));
865 else
866 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
867 dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
868 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
869 POSTING_READ(GTIMR);
870 }
871 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
872
873 return true;
874 }
875
876 static void
877 gen6_ring_put_irq(struct intel_ring_buffer *ring)
878 {
879 struct drm_device *dev = ring->dev;
880 drm_i915_private_t *dev_priv = dev->dev_private;
881 unsigned long flags;
882
883 spin_lock_irqsave(&dev_priv->irq_lock, flags);
884 if (--ring->irq_refcount == 0) {
885 if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
886 I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR);
887 else
888 I915_WRITE_IMR(ring, ~0);
889 dev_priv->gt_irq_mask |= ring->irq_enable_mask;
890 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
891 POSTING_READ(GTIMR);
892 }
893 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
894
895 gen6_gt_force_wake_put(dev_priv);
896 }
897
898 static int
899 i965_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length)
900 {
901 int ret;
902
903 ret = intel_ring_begin(ring, 2);
904 if (ret)
905 return ret;
906
907 intel_ring_emit(ring,
908 MI_BATCH_BUFFER_START |
909 MI_BATCH_GTT |
910 MI_BATCH_NON_SECURE_I965);
911 intel_ring_emit(ring, offset);
912 intel_ring_advance(ring);
913
914 return 0;
915 }
916
917 static int
918 i830_dispatch_execbuffer(struct intel_ring_buffer *ring,
919 u32 offset, u32 len)
920 {
921 int ret;
922
923 ret = intel_ring_begin(ring, 4);
924 if (ret)
925 return ret;
926
927 intel_ring_emit(ring, MI_BATCH_BUFFER);
928 intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
929 intel_ring_emit(ring, offset + len - 8);
930 intel_ring_emit(ring, 0);
931 intel_ring_advance(ring);
932
933 return 0;
934 }
935
936 static int
937 i915_dispatch_execbuffer(struct intel_ring_buffer *ring,
938 u32 offset, u32 len)
939 {
940 int ret;
941
942 ret = intel_ring_begin(ring, 2);
943 if (ret)
944 return ret;
945
946 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
947 intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
948 intel_ring_advance(ring);
949
950 return 0;
951 }
952
953 static void cleanup_status_page(struct intel_ring_buffer *ring)
954 {
955 struct drm_i915_gem_object *obj;
956
957 obj = ring->status_page.obj;
958 if (obj == NULL)
959 return;
960
961 kunmap(obj->pages[0]);
962 i915_gem_object_unpin(obj);
963 drm_gem_object_unreference(&obj->base);
964 ring->status_page.obj = NULL;
965 }
966
967 static int init_status_page(struct intel_ring_buffer *ring)
968 {
969 struct drm_device *dev = ring->dev;
970 struct drm_i915_gem_object *obj;
971 int ret;
972
973 obj = i915_gem_alloc_object(dev, 4096);
974 if (obj == NULL) {
975 DRM_ERROR("Failed to allocate status page\n");
976 ret = -ENOMEM;
977 goto err;
978 }
979
980 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
981
982 ret = i915_gem_object_pin(obj, 4096, true);
983 if (ret != 0) {
984 goto err_unref;
985 }
986
987 ring->status_page.gfx_addr = obj->gtt_offset;
988 ring->status_page.page_addr = kmap(obj->pages[0]);
989 if (ring->status_page.page_addr == NULL) {
990 ret = -ENOMEM;
991 goto err_unpin;
992 }
993 ring->status_page.obj = obj;
994 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
995
996 intel_ring_setup_status_page(ring);
997 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
998 ring->name, ring->status_page.gfx_addr);
999
1000 return 0;
1001
1002 err_unpin:
1003 i915_gem_object_unpin(obj);
1004 err_unref:
1005 drm_gem_object_unreference(&obj->base);
1006 err:
1007 return ret;
1008 }
1009
1010 static int intel_init_ring_buffer(struct drm_device *dev,
1011 struct intel_ring_buffer *ring)
1012 {
1013 struct drm_i915_gem_object *obj;
1014 struct drm_i915_private *dev_priv = dev->dev_private;
1015 int ret;
1016
1017 ring->dev = dev;
1018 INIT_LIST_HEAD(&ring->active_list);
1019 INIT_LIST_HEAD(&ring->request_list);
1020 ring->size = 32 * PAGE_SIZE;
1021
1022 init_waitqueue_head(&ring->irq_queue);
1023
1024 if (I915_NEED_GFX_HWS(dev)) {
1025 ret = init_status_page(ring);
1026 if (ret)
1027 return ret;
1028 }
1029
1030 obj = i915_gem_alloc_object(dev, ring->size);
1031 if (obj == NULL) {
1032 DRM_ERROR("Failed to allocate ringbuffer\n");
1033 ret = -ENOMEM;
1034 goto err_hws;
1035 }
1036
1037 ring->obj = obj;
1038
1039 ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
1040 if (ret)
1041 goto err_unref;
1042
1043 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1044 if (ret)
1045 goto err_unpin;
1046
1047 ring->virtual_start =
1048 ioremap_wc(dev_priv->mm.gtt->gma_bus_addr + obj->gtt_offset,
1049 ring->size);
1050 if (ring->virtual_start == NULL) {
1051 DRM_ERROR("Failed to map ringbuffer.\n");
1052 ret = -EINVAL;
1053 goto err_unpin;
1054 }
1055
1056 ret = ring->init(ring);
1057 if (ret)
1058 goto err_unmap;
1059
1060 /* Workaround an erratum on the i830 which causes a hang if
1061 * the TAIL pointer points to within the last 2 cachelines
1062 * of the buffer.
1063 */
1064 ring->effective_size = ring->size;
1065 if (IS_I830(ring->dev) || IS_845G(ring->dev))
1066 ring->effective_size -= 128;
1067
1068 return 0;
1069
1070 err_unmap:
1071 iounmap(ring->virtual_start);
1072 err_unpin:
1073 i915_gem_object_unpin(obj);
1074 err_unref:
1075 drm_gem_object_unreference(&obj->base);
1076 ring->obj = NULL;
1077 err_hws:
1078 cleanup_status_page(ring);
1079 return ret;
1080 }
1081
1082 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
1083 {
1084 struct drm_i915_private *dev_priv;
1085 int ret;
1086
1087 if (ring->obj == NULL)
1088 return;
1089
1090 /* Disable the ring buffer. The ring must be idle at this point */
1091 dev_priv = ring->dev->dev_private;
1092 ret = intel_wait_ring_idle(ring);
1093 if (ret)
1094 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1095 ring->name, ret);
1096
1097 I915_WRITE_CTL(ring, 0);
1098
1099 iounmap(ring->virtual_start);
1100
1101 i915_gem_object_unpin(ring->obj);
1102 drm_gem_object_unreference(&ring->obj->base);
1103 ring->obj = NULL;
1104
1105 if (ring->cleanup)
1106 ring->cleanup(ring);
1107
1108 cleanup_status_page(ring);
1109 }
1110
1111 static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
1112 {
1113 uint32_t __iomem *virt;
1114 int rem = ring->size - ring->tail;
1115
1116 if (ring->space < rem) {
1117 int ret = intel_wait_ring_buffer(ring, rem);
1118 if (ret)
1119 return ret;
1120 }
1121
1122 virt = ring->virtual_start + ring->tail;
1123 rem /= 4;
1124 while (rem--)
1125 iowrite32(MI_NOOP, virt++);
1126
1127 ring->tail = 0;
1128 ring->space = ring_space(ring);
1129
1130 return 0;
1131 }
1132
1133 static int intel_ring_wait_seqno(struct intel_ring_buffer *ring, u32 seqno)
1134 {
1135 int ret;
1136
1137 ret = i915_wait_seqno(ring, seqno);
1138 if (!ret)
1139 i915_gem_retire_requests_ring(ring);
1140
1141 return ret;
1142 }
1143
1144 static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n)
1145 {
1146 struct drm_i915_gem_request *request;
1147 u32 seqno = 0;
1148 int ret;
1149
1150 i915_gem_retire_requests_ring(ring);
1151
1152 if (ring->last_retired_head != -1) {
1153 ring->head = ring->last_retired_head;
1154 ring->last_retired_head = -1;
1155 ring->space = ring_space(ring);
1156 if (ring->space >= n)
1157 return 0;
1158 }
1159
1160 list_for_each_entry(request, &ring->request_list, list) {
1161 int space;
1162
1163 if (request->tail == -1)
1164 continue;
1165
1166 space = request->tail - (ring->tail + 8);
1167 if (space < 0)
1168 space += ring->size;
1169 if (space >= n) {
1170 seqno = request->seqno;
1171 break;
1172 }
1173
1174 /* Consume this request in case we need more space than
1175 * is available and so need to prevent a race between
1176 * updating last_retired_head and direct reads of
1177 * I915_RING_HEAD. It also provides a nice sanity check.
1178 */
1179 request->tail = -1;
1180 }
1181
1182 if (seqno == 0)
1183 return -ENOSPC;
1184
1185 ret = intel_ring_wait_seqno(ring, seqno);
1186 if (ret)
1187 return ret;
1188
1189 if (WARN_ON(ring->last_retired_head == -1))
1190 return -ENOSPC;
1191
1192 ring->head = ring->last_retired_head;
1193 ring->last_retired_head = -1;
1194 ring->space = ring_space(ring);
1195 if (WARN_ON(ring->space < n))
1196 return -ENOSPC;
1197
1198 return 0;
1199 }
1200
1201 int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n)
1202 {
1203 struct drm_device *dev = ring->dev;
1204 struct drm_i915_private *dev_priv = dev->dev_private;
1205 unsigned long end;
1206 int ret;
1207
1208 ret = intel_ring_wait_request(ring, n);
1209 if (ret != -ENOSPC)
1210 return ret;
1211
1212 trace_i915_ring_wait_begin(ring);
1213 /* With GEM the hangcheck timer should kick us out of the loop,
1214 * leaving it early runs the risk of corrupting GEM state (due
1215 * to running on almost untested codepaths). But on resume
1216 * timers don't work yet, so prevent a complete hang in that
1217 * case by choosing an insanely large timeout. */
1218 end = jiffies + 60 * HZ;
1219
1220 do {
1221 ring->head = I915_READ_HEAD(ring);
1222 ring->space = ring_space(ring);
1223 if (ring->space >= n) {
1224 trace_i915_ring_wait_end(ring);
1225 return 0;
1226 }
1227
1228 if (dev->primary->master) {
1229 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1230 if (master_priv->sarea_priv)
1231 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1232 }
1233
1234 msleep(1);
1235
1236 ret = i915_gem_check_wedge(dev_priv, dev_priv->mm.interruptible);
1237 if (ret)
1238 return ret;
1239 } while (!time_after(jiffies, end));
1240 trace_i915_ring_wait_end(ring);
1241 return -EBUSY;
1242 }
1243
1244 int intel_ring_begin(struct intel_ring_buffer *ring,
1245 int num_dwords)
1246 {
1247 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1248 int n = 4*num_dwords;
1249 int ret;
1250
1251 ret = i915_gem_check_wedge(dev_priv, dev_priv->mm.interruptible);
1252 if (ret)
1253 return ret;
1254
1255 if (unlikely(ring->tail + n > ring->effective_size)) {
1256 ret = intel_wrap_ring_buffer(ring);
1257 if (unlikely(ret))
1258 return ret;
1259 }
1260
1261 if (unlikely(ring->space < n)) {
1262 ret = intel_wait_ring_buffer(ring, n);
1263 if (unlikely(ret))
1264 return ret;
1265 }
1266
1267 ring->space -= n;
1268 return 0;
1269 }
1270
1271 void intel_ring_advance(struct intel_ring_buffer *ring)
1272 {
1273 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1274
1275 ring->tail &= ring->size - 1;
1276 if (dev_priv->stop_rings & intel_ring_flag(ring))
1277 return;
1278 ring->write_tail(ring, ring->tail);
1279 }
1280
1281
1282 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
1283 u32 value)
1284 {
1285 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1286
1287 /* Every tail move must follow the sequence below */
1288
1289 /* Disable notification that the ring is IDLE. The GT
1290 * will then assume that it is busy and bring it out of rc6.
1291 */
1292 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1293 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1294
1295 /* Clear the context id. Here be magic! */
1296 I915_WRITE64(GEN6_BSD_RNCID, 0x0);
1297
1298 /* Wait for the ring not to be idle, i.e. for it to wake up. */
1299 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1300 GEN6_BSD_SLEEP_INDICATOR) == 0,
1301 50))
1302 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
1303
1304 /* Now that the ring is fully powered up, update the tail */
1305 I915_WRITE_TAIL(ring, value);
1306 POSTING_READ(RING_TAIL(ring->mmio_base));
1307
1308 /* Let the ring send IDLE messages to the GT again,
1309 * and so let it sleep to conserve power when idle.
1310 */
1311 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1312 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1313 }
1314
1315 static int gen6_ring_flush(struct intel_ring_buffer *ring,
1316 u32 invalidate, u32 flush)
1317 {
1318 uint32_t cmd;
1319 int ret;
1320
1321 ret = intel_ring_begin(ring, 4);
1322 if (ret)
1323 return ret;
1324
1325 cmd = MI_FLUSH_DW;
1326 if (invalidate & I915_GEM_GPU_DOMAINS)
1327 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
1328 intel_ring_emit(ring, cmd);
1329 intel_ring_emit(ring, 0);
1330 intel_ring_emit(ring, 0);
1331 intel_ring_emit(ring, MI_NOOP);
1332 intel_ring_advance(ring);
1333 return 0;
1334 }
1335
1336 static int
1337 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1338 u32 offset, u32 len)
1339 {
1340 int ret;
1341
1342 ret = intel_ring_begin(ring, 2);
1343 if (ret)
1344 return ret;
1345
1346 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965);
1347 /* bit0-7 is the length on GEN6+ */
1348 intel_ring_emit(ring, offset);
1349 intel_ring_advance(ring);
1350
1351 return 0;
1352 }
1353
1354 /* Blitter support (SandyBridge+) */
1355
1356 static int blt_ring_flush(struct intel_ring_buffer *ring,
1357 u32 invalidate, u32 flush)
1358 {
1359 uint32_t cmd;
1360 int ret;
1361
1362 ret = intel_ring_begin(ring, 4);
1363 if (ret)
1364 return ret;
1365
1366 cmd = MI_FLUSH_DW;
1367 if (invalidate & I915_GEM_DOMAIN_RENDER)
1368 cmd |= MI_INVALIDATE_TLB;
1369 intel_ring_emit(ring, cmd);
1370 intel_ring_emit(ring, 0);
1371 intel_ring_emit(ring, 0);
1372 intel_ring_emit(ring, MI_NOOP);
1373 intel_ring_advance(ring);
1374 return 0;
1375 }
1376
1377 int intel_init_render_ring_buffer(struct drm_device *dev)
1378 {
1379 drm_i915_private_t *dev_priv = dev->dev_private;
1380 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1381
1382 ring->name = "render ring";
1383 ring->id = RCS;
1384 ring->mmio_base = RENDER_RING_BASE;
1385
1386 if (INTEL_INFO(dev)->gen >= 6) {
1387 ring->add_request = gen6_add_request;
1388 ring->flush = gen6_render_ring_flush;
1389 if (INTEL_INFO(dev)->gen == 6)
1390 ring->flush = gen6_render_ring_flush__wa;
1391 ring->irq_get = gen6_ring_get_irq;
1392 ring->irq_put = gen6_ring_put_irq;
1393 ring->irq_enable_mask = GT_USER_INTERRUPT;
1394 ring->get_seqno = gen6_ring_get_seqno;
1395 ring->sync_to = gen6_ring_sync;
1396 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_INVALID;
1397 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_RV;
1398 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_RB;
1399 ring->signal_mbox[0] = GEN6_VRSYNC;
1400 ring->signal_mbox[1] = GEN6_BRSYNC;
1401 } else if (IS_GEN5(dev)) {
1402 ring->add_request = pc_render_add_request;
1403 ring->flush = gen4_render_ring_flush;
1404 ring->get_seqno = pc_render_get_seqno;
1405 ring->irq_get = gen5_ring_get_irq;
1406 ring->irq_put = gen5_ring_put_irq;
1407 ring->irq_enable_mask = GT_USER_INTERRUPT | GT_PIPE_NOTIFY;
1408 } else {
1409 ring->add_request = i9xx_add_request;
1410 if (INTEL_INFO(dev)->gen < 4)
1411 ring->flush = gen2_render_ring_flush;
1412 else
1413 ring->flush = gen4_render_ring_flush;
1414 ring->get_seqno = ring_get_seqno;
1415 if (IS_GEN2(dev)) {
1416 ring->irq_get = i8xx_ring_get_irq;
1417 ring->irq_put = i8xx_ring_put_irq;
1418 } else {
1419 ring->irq_get = i9xx_ring_get_irq;
1420 ring->irq_put = i9xx_ring_put_irq;
1421 }
1422 ring->irq_enable_mask = I915_USER_INTERRUPT;
1423 }
1424 ring->write_tail = ring_write_tail;
1425 if (INTEL_INFO(dev)->gen >= 6)
1426 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1427 else if (INTEL_INFO(dev)->gen >= 4)
1428 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1429 else if (IS_I830(dev) || IS_845G(dev))
1430 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1431 else
1432 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1433 ring->init = init_render_ring;
1434 ring->cleanup = render_ring_cleanup;
1435
1436
1437 if (!I915_NEED_GFX_HWS(dev)) {
1438 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1439 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1440 }
1441
1442 return intel_init_ring_buffer(dev, ring);
1443 }
1444
1445 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
1446 {
1447 drm_i915_private_t *dev_priv = dev->dev_private;
1448 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1449
1450 ring->name = "render ring";
1451 ring->id = RCS;
1452 ring->mmio_base = RENDER_RING_BASE;
1453
1454 if (INTEL_INFO(dev)->gen >= 6) {
1455 /* non-kms not supported on gen6+ */
1456 return -ENODEV;
1457 }
1458
1459 /* Note: gem is not supported on gen5/ilk without kms (the corresponding
1460 * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
1461 * the special gen5 functions. */
1462 ring->add_request = i9xx_add_request;
1463 if (INTEL_INFO(dev)->gen < 4)
1464 ring->flush = gen2_render_ring_flush;
1465 else
1466 ring->flush = gen4_render_ring_flush;
1467 ring->get_seqno = ring_get_seqno;
1468 if (IS_GEN2(dev)) {
1469 ring->irq_get = i8xx_ring_get_irq;
1470 ring->irq_put = i8xx_ring_put_irq;
1471 } else {
1472 ring->irq_get = i9xx_ring_get_irq;
1473 ring->irq_put = i9xx_ring_put_irq;
1474 }
1475 ring->irq_enable_mask = I915_USER_INTERRUPT;
1476 ring->write_tail = ring_write_tail;
1477 if (INTEL_INFO(dev)->gen >= 4)
1478 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1479 else if (IS_I830(dev) || IS_845G(dev))
1480 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1481 else
1482 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1483 ring->init = init_render_ring;
1484 ring->cleanup = render_ring_cleanup;
1485
1486 if (!I915_NEED_GFX_HWS(dev))
1487 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1488
1489 ring->dev = dev;
1490 INIT_LIST_HEAD(&ring->active_list);
1491 INIT_LIST_HEAD(&ring->request_list);
1492
1493 ring->size = size;
1494 ring->effective_size = ring->size;
1495 if (IS_I830(ring->dev))
1496 ring->effective_size -= 128;
1497
1498 ring->virtual_start = ioremap_wc(start, size);
1499 if (ring->virtual_start == NULL) {
1500 DRM_ERROR("can not ioremap virtual address for"
1501 " ring buffer\n");
1502 return -ENOMEM;
1503 }
1504
1505 return 0;
1506 }
1507
1508 int intel_init_bsd_ring_buffer(struct drm_device *dev)
1509 {
1510 drm_i915_private_t *dev_priv = dev->dev_private;
1511 struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
1512
1513 ring->name = "bsd ring";
1514 ring->id = VCS;
1515
1516 ring->write_tail = ring_write_tail;
1517 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1518 ring->mmio_base = GEN6_BSD_RING_BASE;
1519 /* gen6 bsd needs a special wa for tail updates */
1520 if (IS_GEN6(dev))
1521 ring->write_tail = gen6_bsd_ring_write_tail;
1522 ring->flush = gen6_ring_flush;
1523 ring->add_request = gen6_add_request;
1524 ring->get_seqno = gen6_ring_get_seqno;
1525 ring->irq_enable_mask = GEN6_BSD_USER_INTERRUPT;
1526 ring->irq_get = gen6_ring_get_irq;
1527 ring->irq_put = gen6_ring_put_irq;
1528 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1529 ring->sync_to = gen6_ring_sync;
1530 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_VR;
1531 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_INVALID;
1532 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_VB;
1533 ring->signal_mbox[0] = GEN6_RVSYNC;
1534 ring->signal_mbox[1] = GEN6_BVSYNC;
1535 } else {
1536 ring->mmio_base = BSD_RING_BASE;
1537 ring->flush = bsd_ring_flush;
1538 ring->add_request = i9xx_add_request;
1539 ring->get_seqno = ring_get_seqno;
1540 if (IS_GEN5(dev)) {
1541 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
1542 ring->irq_get = gen5_ring_get_irq;
1543 ring->irq_put = gen5_ring_put_irq;
1544 } else {
1545 ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
1546 ring->irq_get = i9xx_ring_get_irq;
1547 ring->irq_put = i9xx_ring_put_irq;
1548 }
1549 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1550 }
1551 ring->init = init_ring_common;
1552
1553
1554 return intel_init_ring_buffer(dev, ring);
1555 }
1556
1557 int intel_init_blt_ring_buffer(struct drm_device *dev)
1558 {
1559 drm_i915_private_t *dev_priv = dev->dev_private;
1560 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
1561
1562 ring->name = "blitter ring";
1563 ring->id = BCS;
1564
1565 ring->mmio_base = BLT_RING_BASE;
1566 ring->write_tail = ring_write_tail;
1567 ring->flush = blt_ring_flush;
1568 ring->add_request = gen6_add_request;
1569 ring->get_seqno = gen6_ring_get_seqno;
1570 ring->irq_enable_mask = GEN6_BLITTER_USER_INTERRUPT;
1571 ring->irq_get = gen6_ring_get_irq;
1572 ring->irq_put = gen6_ring_put_irq;
1573 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1574 ring->sync_to = gen6_ring_sync;
1575 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_BR;
1576 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_BV;
1577 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_INVALID;
1578 ring->signal_mbox[0] = GEN6_RBSYNC;
1579 ring->signal_mbox[1] = GEN6_VBSYNC;
1580 ring->init = init_ring_common;
1581
1582 return intel_init_ring_buffer(dev, ring);
1583 }
1584
1585 int
1586 intel_ring_flush_all_caches(struct intel_ring_buffer *ring)
1587 {
1588 int ret;
1589
1590 if (!ring->gpu_caches_dirty)
1591 return 0;
1592
1593 ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
1594 if (ret)
1595 return ret;
1596
1597 trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
1598
1599 ring->gpu_caches_dirty = false;
1600 return 0;
1601 }
1602
1603 int
1604 intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring)
1605 {
1606 uint32_t flush_domains;
1607 int ret;
1608
1609 flush_domains = 0;
1610 if (ring->gpu_caches_dirty)
1611 flush_domains = I915_GEM_GPU_DOMAINS;
1612
1613 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
1614 if (ret)
1615 return ret;
1616
1617 trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
1618
1619 ring->gpu_caches_dirty = false;
1620 return 0;
1621 }
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