1 /* SPDX-License-Identifier: MIT */
2 #ifndef _INTEL_RINGBUFFER_H_
3 #define _INTEL_RINGBUFFER_H_
5 #include <drm/drm_util.h>
7 #include <linux/hashtable.h>
8 #include <linux/seqlock.h>
10 #include "i915_gem_batch_pool.h"
14 #include "i915_request.h"
15 #include "i915_selftest.h"
16 #include "i915_timeline.h"
17 #include "intel_gpu_commands.h"
18 #include "intel_workarounds.h"
21 struct i915_sched_attr
;
23 #define I915_CMD_HASH_ORDER 9
25 /* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill,
26 * but keeps the logic simple. Indeed, the whole purpose of this macro is just
27 * to give some inclination as to some of the magic values used in the various
30 #define CACHELINE_BYTES 64
31 #define CACHELINE_DWORDS (CACHELINE_BYTES / sizeof(uint32_t))
33 struct intel_hw_status_page
{
39 #define I915_READ_TAIL(engine) I915_READ(RING_TAIL((engine)->mmio_base))
40 #define I915_WRITE_TAIL(engine, val) I915_WRITE(RING_TAIL((engine)->mmio_base), val)
42 #define I915_READ_START(engine) I915_READ(RING_START((engine)->mmio_base))
43 #define I915_WRITE_START(engine, val) I915_WRITE(RING_START((engine)->mmio_base), val)
45 #define I915_READ_HEAD(engine) I915_READ(RING_HEAD((engine)->mmio_base))
46 #define I915_WRITE_HEAD(engine, val) I915_WRITE(RING_HEAD((engine)->mmio_base), val)
48 #define I915_READ_CTL(engine) I915_READ(RING_CTL((engine)->mmio_base))
49 #define I915_WRITE_CTL(engine, val) I915_WRITE(RING_CTL((engine)->mmio_base), val)
51 #define I915_READ_IMR(engine) I915_READ(RING_IMR((engine)->mmio_base))
52 #define I915_WRITE_IMR(engine, val) I915_WRITE(RING_IMR((engine)->mmio_base), val)
54 #define I915_READ_MODE(engine) I915_READ(RING_MI_MODE((engine)->mmio_base))
55 #define I915_WRITE_MODE(engine, val) I915_WRITE(RING_MI_MODE((engine)->mmio_base), val)
57 /* seqno size is actually only a uint32, but since we plan to use MI_FLUSH_DW to
58 * do the writes, and that must have qw aligned offsets, simply pretend it's 8b.
60 enum intel_engine_hangcheck_action
{
65 ENGINE_ACTIVE_SUBUNITS
,
70 static inline const char *
71 hangcheck_action_to_str(const enum intel_engine_hangcheck_action a
)
78 case ENGINE_ACTIVE_SEQNO
:
79 return "active seqno";
80 case ENGINE_ACTIVE_HEAD
:
82 case ENGINE_ACTIVE_SUBUNITS
:
83 return "active subunits";
84 case ENGINE_WAIT_KICK
:
93 #define I915_MAX_SLICES 3
94 #define I915_MAX_SUBSLICES 8
96 #define instdone_slice_mask(dev_priv__) \
97 (IS_GEN7(dev_priv__) ? \
98 1 : INTEL_INFO(dev_priv__)->sseu.slice_mask)
100 #define instdone_subslice_mask(dev_priv__) \
101 (IS_GEN7(dev_priv__) ? \
102 1 : INTEL_INFO(dev_priv__)->sseu.subslice_mask[0])
104 #define for_each_instdone_slice_subslice(dev_priv__, slice__, subslice__) \
105 for ((slice__) = 0, (subslice__) = 0; \
106 (slice__) < I915_MAX_SLICES; \
107 (subslice__) = ((subslice__) + 1) < I915_MAX_SUBSLICES ? (subslice__) + 1 : 0, \
108 (slice__) += ((subslice__) == 0)) \
109 for_each_if((BIT(slice__) & instdone_slice_mask(dev_priv__)) && \
110 (BIT(subslice__) & instdone_subslice_mask(dev_priv__)))
112 struct intel_instdone
{
114 /* The following exist only in the RCS engine */
116 u32 sampler
[I915_MAX_SLICES
][I915_MAX_SUBSLICES
];
117 u32 row
[I915_MAX_SLICES
][I915_MAX_SUBSLICES
];
120 struct intel_engine_hangcheck
{
123 enum intel_engine_hangcheck_action action
;
124 unsigned long action_timestamp
;
126 struct intel_instdone instdone
;
127 struct i915_request
*active_request
;
133 struct i915_vma
*vma
;
136 struct i915_timeline
*timeline
;
137 struct list_head request_list
;
138 struct list_head active_link
;
149 struct i915_gem_context
;
150 struct drm_i915_reg_table
;
153 * we use a single page to load ctx workarounds so all of these
154 * values are referred in terms of dwords
156 * struct i915_wa_ctx_bb:
157 * offset: specifies batch starting position, also helpful in case
158 * if we want to have multiple batches at different offsets based on
159 * some criteria. It is not a requirement at the moment but provides
160 * an option for future use.
161 * size: size of the batch in DWORDS
163 struct i915_ctx_workarounds
{
164 struct i915_wa_ctx_bb
{
167 } indirect_ctx
, per_ctx
;
168 struct i915_vma
*vma
;
173 #define I915_MAX_VCS 4
174 #define I915_MAX_VECS 2
177 * Engine IDs definitions.
178 * Keep instances of the same type engine together.
180 enum intel_engine_id
{
187 #define _VCS(n) (VCS + (n))
190 #define _VECS(n) (VECS + (n))
193 struct i915_priolist
{
194 struct list_head requests
[I915_PRIORITY_COUNT
];
200 #define priolist_for_each_request(it, plist, idx) \
201 for (idx = 0; idx < ARRAY_SIZE((plist)->requests); idx++) \
202 list_for_each_entry(it, &(plist)->requests[idx], sched.link)
204 #define priolist_for_each_request_consume(it, n, plist, idx) \
205 for (; (idx = ffs((plist)->used)); (plist)->used &= ~BIT(idx - 1)) \
206 list_for_each_entry_safe(it, n, \
207 &(plist)->requests[idx - 1], \
210 struct st_preempt_hang
{
211 struct completion completion
;
216 * struct intel_engine_execlists - execlist submission queue and port state
218 * The struct intel_engine_execlists represents the combined logical state of
219 * driver and the hardware state for execlist mode of submission.
221 struct intel_engine_execlists
{
223 * @tasklet: softirq tasklet for bottom handler
225 struct tasklet_struct tasklet
;
228 * @default_priolist: priority list for I915_PRIORITY_NORMAL
230 struct i915_priolist default_priolist
;
233 * @no_priolist: priority lists disabled
238 * @submit_reg: gen-specific execlist submission register
239 * set to the ExecList Submission Port (elsp) register pre-Gen11 and to
240 * the ExecList Submission Queue Contents register array for Gen11+
242 u32 __iomem
*submit_reg
;
245 * @ctrl_reg: the enhanced execlists control register, used to load the
246 * submit queue on the HW and to request preemptions to idle
248 u32 __iomem
*ctrl_reg
;
251 * @port: execlist port states
253 * For each hardware ELSP (ExecList Submission Port) we keep
254 * track of the last request and the number of times we submitted
255 * that port to hw. We then count the number of times the hw reports
256 * a context completion or preemption. As only one context can
257 * be active on hw, we limit resubmission of context to port[0]. This
258 * is called Lite Restore, of the context.
260 struct execlist_port
{
262 * @request_count: combined request and submission count
264 struct i915_request
*request_count
;
265 #define EXECLIST_COUNT_BITS 2
266 #define port_request(p) ptr_mask_bits((p)->request_count, EXECLIST_COUNT_BITS)
267 #define port_count(p) ptr_unmask_bits((p)->request_count, EXECLIST_COUNT_BITS)
268 #define port_pack(rq, count) ptr_pack_bits(rq, count, EXECLIST_COUNT_BITS)
269 #define port_unpack(p, count) ptr_unpack_bits((p)->request_count, count, EXECLIST_COUNT_BITS)
270 #define port_set(p, packed) ((p)->request_count = (packed))
271 #define port_isset(p) ((p)->request_count)
272 #define port_index(p, execlists) ((p) - (execlists)->port)
275 * @context_id: context ID for port
277 GEM_DEBUG_DECL(u32 context_id
);
279 #define EXECLIST_MAX_PORTS 2
280 } port
[EXECLIST_MAX_PORTS
];
283 * @active: is the HW active? We consider the HW as active after
284 * submitting any context for execution and until we have seen the
285 * last context completion event. After that, we do not expect any
286 * more events until we submit, and so can park the HW.
288 * As we have a small number of different sources from which we feed
289 * the HW, we track the state of each inside a single bitfield.
292 #define EXECLISTS_ACTIVE_USER 0
293 #define EXECLISTS_ACTIVE_PREEMPT 1
294 #define EXECLISTS_ACTIVE_HWACK 2
297 * @port_mask: number of execlist ports - 1
299 unsigned int port_mask
;
302 * @queue_priority: Highest pending priority.
304 * When we add requests into the queue, or adjust the priority of
305 * executing requests, we compute the maximum priority of those
306 * pending requests. We can then use this value to determine if
307 * we need to preempt the executing requests to service the queue.
312 * @queue: queue of requests, in priority lists
314 struct rb_root_cached queue
;
317 * @csb_write: control register for Context Switch buffer
319 * Note this register may be either mmio or HWSP shadow.
324 * @csb_status: status array for Context Switch buffer
326 * Note these register may be either mmio or HWSP shadow.
331 * @preempt_complete_status: expected CSB upon completing preemption
333 u32 preempt_complete_status
;
336 * @csb_head: context status buffer head
340 I915_SELFTEST_DECLARE(struct st_preempt_hang preempt_hang
;)
343 #define INTEL_ENGINE_CS_MAX_NAME 8
345 struct intel_engine_cs
{
346 struct drm_i915_private
*i915
;
347 char name
[INTEL_ENGINE_CS_MAX_NAME
];
349 enum intel_engine_id id
;
361 struct intel_ring
*buffer
;
363 struct i915_timeline timeline
;
365 struct drm_i915_gem_object
*default_state
;
366 void *pinned_default_state
;
368 unsigned long irq_posted
;
369 #define ENGINE_IRQ_BREADCRUMB 0
371 /* Rather than have every client wait upon all user interrupts,
372 * with the herd waking after every interrupt and each doing the
373 * heavyweight seqno dance, we delegate the task (of being the
374 * bottom-half of the user interrupt) to the first client. After
375 * every interrupt, we wake up one client, who does the heavyweight
376 * coherent seqno read and either goes back to sleep (if incomplete),
377 * or wakes up all the completed clients in parallel, before then
378 * transferring the bottom-half status to the next client in the queue.
380 * Compared to walking the entire list of waiters in a single dedicated
381 * bottom-half, we reduce the latency of the first waiter by avoiding
382 * a context switch, but incur additional coherent seqno reads when
383 * following the chain of request breadcrumbs. Since it is most likely
384 * that we have a single client waiting on each seqno, then reducing
385 * the overhead of waking that client is much preferred.
387 struct intel_breadcrumbs
{
388 spinlock_t irq_lock
; /* protects irq_*; irqsafe */
389 struct intel_wait
*irq_wait
; /* oldest waiter by retirement */
391 spinlock_t rb_lock
; /* protects the rb and wraps irq_lock */
392 struct rb_root waiters
; /* sorted by retirement, priority */
393 struct list_head signals
; /* sorted by retirement */
394 struct task_struct
*signaler
; /* used for fence signalling */
396 struct timer_list fake_irq
; /* used after a missed interrupt */
397 struct timer_list hangcheck
; /* detect missed interrupts */
399 unsigned int hangcheck_interrupts
;
400 unsigned int irq_enabled
;
401 unsigned int irq_count
;
404 I915_SELFTEST_DECLARE(bool mock
: 1);
409 * @enable: Bitmask of enable sample events on this engine.
411 * Bits correspond to sample event types, for instance
412 * I915_SAMPLE_QUEUED is bit 0 etc.
416 * @enable_count: Reference count for the enabled samplers.
418 * Index number corresponds to the bit number from @enable.
420 unsigned int enable_count
[I915_PMU_SAMPLE_BITS
];
422 * @sample: Counter values for sampling events.
424 * Our internal timer stores the current counters in this field.
426 #define I915_ENGINE_SAMPLE_MAX (I915_SAMPLE_SEMA + 1)
427 struct i915_pmu_sample sample
[I915_ENGINE_SAMPLE_MAX
];
431 * A pool of objects to use as shadow copies of client batch buffers
432 * when the command parser is enabled. Prevents the client from
433 * modifying the batch contents after software parsing.
435 struct i915_gem_batch_pool batch_pool
;
437 struct intel_hw_status_page status_page
;
438 struct i915_ctx_workarounds wa_ctx
;
439 struct i915_wa_list ctx_wa_list
;
440 struct i915_wa_list wa_list
;
441 struct i915_wa_list whitelist
;
443 u32 irq_keep_mask
; /* always keep these interrupts */
444 u32 irq_enable_mask
; /* bitmask to enable ring interrupt */
445 void (*irq_enable
)(struct intel_engine_cs
*engine
);
446 void (*irq_disable
)(struct intel_engine_cs
*engine
);
448 int (*init_hw
)(struct intel_engine_cs
*engine
);
451 struct i915_request
*(*prepare
)(struct intel_engine_cs
*engine
);
452 void (*reset
)(struct intel_engine_cs
*engine
,
453 struct i915_request
*rq
);
454 void (*finish
)(struct intel_engine_cs
*engine
);
457 void (*park
)(struct intel_engine_cs
*engine
);
458 void (*unpark
)(struct intel_engine_cs
*engine
);
460 void (*set_default_submission
)(struct intel_engine_cs
*engine
);
462 struct intel_context
*(*context_pin
)(struct intel_engine_cs
*engine
,
463 struct i915_gem_context
*ctx
);
465 int (*request_alloc
)(struct i915_request
*rq
);
466 int (*init_context
)(struct i915_request
*rq
);
468 int (*emit_flush
)(struct i915_request
*request
, u32 mode
);
469 #define EMIT_INVALIDATE BIT(0)
470 #define EMIT_FLUSH BIT(1)
471 #define EMIT_BARRIER (EMIT_INVALIDATE | EMIT_FLUSH)
472 int (*emit_bb_start
)(struct i915_request
*rq
,
473 u64 offset
, u32 length
,
474 unsigned int dispatch_flags
);
475 #define I915_DISPATCH_SECURE BIT(0)
476 #define I915_DISPATCH_PINNED BIT(1)
477 void (*emit_breadcrumb
)(struct i915_request
*rq
, u32
*cs
);
478 int emit_breadcrumb_sz
;
480 /* Pass the request to the hardware queue (e.g. directly into
481 * the legacy ringbuffer or to the end of an execlist).
483 * This is called from an atomic context with irqs disabled; must
486 void (*submit_request
)(struct i915_request
*rq
);
489 * Call when the priority on a request has changed and it and its
490 * dependencies may need rescheduling. Note the request itself may
491 * not be ready to run!
493 void (*schedule
)(struct i915_request
*request
,
494 const struct i915_sched_attr
*attr
);
497 * Cancel all requests on the hardware, or queued for execution.
498 * This should only cancel the ready requests that have been
499 * submitted to the engine (via the engine->submit_request callback).
500 * This is called when marking the device as wedged.
502 void (*cancel_requests
)(struct intel_engine_cs
*engine
);
504 /* Some chipsets are not quite as coherent as advertised and need
505 * an expensive kick to force a true read of the up-to-date seqno.
506 * However, the up-to-date seqno is not always required and the last
507 * seen value is good enough. Note that the seqno will always be
508 * monotonic, even if not coherent.
510 void (*irq_seqno_barrier
)(struct intel_engine_cs
*engine
);
511 void (*cleanup
)(struct intel_engine_cs
*engine
);
513 /* GEN8 signal/wait table - never trust comments!
514 * signal to signal to signal to signal to signal to
515 * RCS VCS BCS VECS VCS2
516 * --------------------------------------------------------------------
517 * RCS | NOP (0x00) | VCS (0x08) | BCS (0x10) | VECS (0x18) | VCS2 (0x20) |
518 * |-------------------------------------------------------------------
519 * VCS | RCS (0x28) | NOP (0x30) | BCS (0x38) | VECS (0x40) | VCS2 (0x48) |
520 * |-------------------------------------------------------------------
521 * BCS | RCS (0x50) | VCS (0x58) | NOP (0x60) | VECS (0x68) | VCS2 (0x70) |
522 * |-------------------------------------------------------------------
523 * VECS | RCS (0x78) | VCS (0x80) | BCS (0x88) | NOP (0x90) | VCS2 (0x98) |
524 * |-------------------------------------------------------------------
525 * VCS2 | RCS (0xa0) | VCS (0xa8) | BCS (0xb0) | VECS (0xb8) | NOP (0xc0) |
526 * |-------------------------------------------------------------------
529 * f(x, y) := (x->id * NUM_RINGS * seqno_size) + (seqno_size * y->id)
530 * ie. transpose of g(x, y)
532 * sync from sync from sync from sync from sync from
533 * RCS VCS BCS VECS VCS2
534 * --------------------------------------------------------------------
535 * RCS | NOP (0x00) | VCS (0x28) | BCS (0x50) | VECS (0x78) | VCS2 (0xa0) |
536 * |-------------------------------------------------------------------
537 * VCS | RCS (0x08) | NOP (0x30) | BCS (0x58) | VECS (0x80) | VCS2 (0xa8) |
538 * |-------------------------------------------------------------------
539 * BCS | RCS (0x10) | VCS (0x38) | NOP (0x60) | VECS (0x88) | VCS2 (0xb0) |
540 * |-------------------------------------------------------------------
541 * VECS | RCS (0x18) | VCS (0x40) | BCS (0x68) | NOP (0x90) | VCS2 (0xb8) |
542 * |-------------------------------------------------------------------
543 * VCS2 | RCS (0x20) | VCS (0x48) | BCS (0x70) | VECS (0x98) | NOP (0xc0) |
544 * |-------------------------------------------------------------------
547 * g(x, y) := (y->id * NUM_RINGS * seqno_size) + (seqno_size * x->id)
548 * ie. transpose of f(x, y)
551 #define GEN6_SEMAPHORE_LAST VECS_HW
552 #define GEN6_NUM_SEMAPHORES (GEN6_SEMAPHORE_LAST + 1)
553 #define GEN6_SEMAPHORES_MASK GENMASK(GEN6_SEMAPHORE_LAST, 0)
555 /* our mbox written by others */
556 u32 wait
[GEN6_NUM_SEMAPHORES
];
557 /* mboxes this ring signals to */
558 i915_reg_t signal
[GEN6_NUM_SEMAPHORES
];
562 int (*sync_to
)(struct i915_request
*rq
,
563 struct i915_request
*signal
);
564 u32
*(*signal
)(struct i915_request
*rq
, u32
*cs
);
567 struct intel_engine_execlists execlists
;
569 /* Contexts are pinned whilst they are active on the GPU. The last
570 * context executed remains active whilst the GPU is idle - the
571 * switch away and write to the context object only occurs on the
572 * next execution. Contexts are only unpinned on retirement of the
573 * following request ensuring that we can always write to the object
574 * on the context switch even after idling. Across suspend, we switch
575 * to the kernel context and trash it as the save may not happen
576 * before the hardware is powered down.
578 struct intel_context
*last_retired_context
;
580 /* status_notifier: list of callbacks for context-switch changes */
581 struct atomic_notifier_head context_status_notifier
;
583 struct intel_engine_hangcheck hangcheck
;
585 #define I915_ENGINE_NEEDS_CMD_PARSER BIT(0)
586 #define I915_ENGINE_SUPPORTS_STATS BIT(1)
587 #define I915_ENGINE_HAS_PREEMPTION BIT(2)
591 * Table of commands the command parser needs to know about
594 DECLARE_HASHTABLE(cmd_hash
, I915_CMD_HASH_ORDER
);
597 * Table of registers allowed in commands that read/write registers.
599 const struct drm_i915_reg_table
*reg_tables
;
603 * Returns the bitmask for the length field of the specified command.
604 * Return 0 for an unrecognized/invalid command.
606 * If the command parser finds an entry for a command in the engine's
607 * cmd_tables, it gets the command's length based on the table entry.
608 * If not, it calls this function to determine the per-engine length
609 * field encoding for the command (i.e. different opcode ranges use
610 * certain bits to encode the command length in the header).
612 u32 (*get_cmd_length_mask
)(u32 cmd_header
);
616 * @lock: Lock protecting the below fields.
620 * @enabled: Reference count indicating number of listeners.
622 unsigned int enabled
;
624 * @active: Number of contexts currently scheduled in.
628 * @enabled_at: Timestamp when busy stats were enabled.
632 * @start: Timestamp of the last idle to active transition.
634 * Idle is defined as active == 0, active is active > 0.
638 * @total: Total time this engine was busy.
640 * Accumulated time not counting the most recent block in cases
641 * where engine is currently busy (active > 0).
648 intel_engine_needs_cmd_parser(const struct intel_engine_cs
*engine
)
650 return engine
->flags
& I915_ENGINE_NEEDS_CMD_PARSER
;
654 intel_engine_supports_stats(const struct intel_engine_cs
*engine
)
656 return engine
->flags
& I915_ENGINE_SUPPORTS_STATS
;
660 intel_engine_has_preemption(const struct intel_engine_cs
*engine
)
662 return engine
->flags
& I915_ENGINE_HAS_PREEMPTION
;
665 static inline bool __execlists_need_preempt(int prio
, int last
)
667 return prio
> max(0, last
);
671 execlists_set_active(struct intel_engine_execlists
*execlists
,
674 __set_bit(bit
, (unsigned long *)&execlists
->active
);
678 execlists_set_active_once(struct intel_engine_execlists
*execlists
,
681 return !__test_and_set_bit(bit
, (unsigned long *)&execlists
->active
);
685 execlists_clear_active(struct intel_engine_execlists
*execlists
,
688 __clear_bit(bit
, (unsigned long *)&execlists
->active
);
692 execlists_clear_all_active(struct intel_engine_execlists
*execlists
)
694 execlists
->active
= 0;
698 execlists_is_active(const struct intel_engine_execlists
*execlists
,
701 return test_bit(bit
, (unsigned long *)&execlists
->active
);
704 void execlists_user_begin(struct intel_engine_execlists
*execlists
,
705 const struct execlist_port
*port
);
706 void execlists_user_end(struct intel_engine_execlists
*execlists
);
709 execlists_cancel_port_requests(struct intel_engine_execlists
* const execlists
);
712 execlists_unwind_incomplete_requests(struct intel_engine_execlists
*execlists
);
714 static inline unsigned int
715 execlists_num_ports(const struct intel_engine_execlists
* const execlists
)
717 return execlists
->port_mask
+ 1;
720 static inline struct execlist_port
*
721 execlists_port_complete(struct intel_engine_execlists
* const execlists
,
722 struct execlist_port
* const port
)
724 const unsigned int m
= execlists
->port_mask
;
726 GEM_BUG_ON(port_index(port
, execlists
) != 0);
727 GEM_BUG_ON(!execlists_is_active(execlists
, EXECLISTS_ACTIVE_USER
));
729 memmove(port
, port
+ 1, m
* sizeof(struct execlist_port
));
730 memset(port
+ m
, 0, sizeof(struct execlist_port
));
735 static inline unsigned int
736 intel_engine_flag(const struct intel_engine_cs
*engine
)
738 return BIT(engine
->id
);
742 intel_read_status_page(const struct intel_engine_cs
*engine
, int reg
)
744 /* Ensure that the compiler doesn't optimize away the load. */
745 return READ_ONCE(engine
->status_page
.page_addr
[reg
]);
749 intel_write_status_page(struct intel_engine_cs
*engine
, int reg
, u32 value
)
751 /* Writing into the status page should be done sparingly. Since
752 * we do when we are uncertain of the device state, we take a bit
753 * of extra paranoia to try and ensure that the HWS takes the value
754 * we give and that it doesn't end up trapped inside the CPU!
756 if (static_cpu_has(X86_FEATURE_CLFLUSH
)) {
758 clflush(&engine
->status_page
.page_addr
[reg
]);
759 engine
->status_page
.page_addr
[reg
] = value
;
760 clflush(&engine
->status_page
.page_addr
[reg
]);
763 WRITE_ONCE(engine
->status_page
.page_addr
[reg
], value
);
768 * Reads a dword out of the status page, which is written to from the command
769 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
772 * The following dwords have a reserved meaning:
773 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
774 * 0x04: ring 0 head pointer
775 * 0x05: ring 1 head pointer (915-class)
776 * 0x06: ring 2 head pointer (915-class)
777 * 0x10-0x1b: Context status DWords (GM45)
778 * 0x1f: Last written status offset. (GM45)
779 * 0x20-0x2f: Reserved (Gen6+)
781 * The area from dword 0x30 to 0x3ff is available for driver usage.
783 #define I915_GEM_HWS_INDEX 0x30
784 #define I915_GEM_HWS_INDEX_ADDR (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
785 #define I915_GEM_HWS_PREEMPT_INDEX 0x32
786 #define I915_GEM_HWS_PREEMPT_ADDR (I915_GEM_HWS_PREEMPT_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
787 #define I915_GEM_HWS_SCRATCH_INDEX 0x40
788 #define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
790 #define I915_HWS_CSB_BUF0_INDEX 0x10
791 #define I915_HWS_CSB_WRITE_INDEX 0x1f
792 #define CNL_HWS_CSB_WRITE_INDEX 0x2f
795 intel_engine_create_ring(struct intel_engine_cs
*engine
,
796 struct i915_timeline
*timeline
,
798 int intel_ring_pin(struct intel_ring
*ring
);
799 void intel_ring_reset(struct intel_ring
*ring
, u32 tail
);
800 unsigned int intel_ring_update_space(struct intel_ring
*ring
);
801 void intel_ring_unpin(struct intel_ring
*ring
);
802 void intel_ring_free(struct intel_ring
*ring
);
804 void intel_engine_stop(struct intel_engine_cs
*engine
);
805 void intel_engine_cleanup(struct intel_engine_cs
*engine
);
807 void intel_legacy_submission_resume(struct drm_i915_private
*dev_priv
);
809 int __must_check
intel_ring_cacheline_align(struct i915_request
*rq
);
811 int intel_ring_wait_for_space(struct intel_ring
*ring
, unsigned int bytes
);
812 u32 __must_check
*intel_ring_begin(struct i915_request
*rq
, unsigned int n
);
814 static inline void intel_ring_advance(struct i915_request
*rq
, u32
*cs
)
818 * This serves as a placeholder in the code so that the reader
819 * can compare against the preceding intel_ring_begin() and
820 * check that the number of dwords emitted matches the space
821 * reserved for the command packet (i.e. the value passed to
822 * intel_ring_begin()).
824 GEM_BUG_ON((rq
->ring
->vaddr
+ rq
->ring
->emit
) != cs
);
827 static inline u32
intel_ring_wrap(const struct intel_ring
*ring
, u32 pos
)
829 return pos
& (ring
->size
- 1);
833 intel_ring_offset_valid(const struct intel_ring
*ring
,
836 if (pos
& -ring
->size
) /* must be strictly within the ring */
839 if (!IS_ALIGNED(pos
, 8)) /* must be qword aligned */
845 static inline u32
intel_ring_offset(const struct i915_request
*rq
, void *addr
)
847 /* Don't write ring->size (equivalent to 0) as that hangs some GPUs. */
848 u32 offset
= addr
- rq
->ring
->vaddr
;
849 GEM_BUG_ON(offset
> rq
->ring
->size
);
850 return intel_ring_wrap(rq
->ring
, offset
);
854 assert_ring_tail_valid(const struct intel_ring
*ring
, unsigned int tail
)
856 GEM_BUG_ON(!intel_ring_offset_valid(ring
, tail
));
860 * Gen2 BSpec "1. Programming Environment" / 1.4.4.6
861 * Gen3 BSpec "1c Memory Interface Functions" / 2.3.4.5
862 * Gen4+ BSpec "1c Memory Interface and Command Stream" / 5.3.4.5
863 * "If the Ring Buffer Head Pointer and the Tail Pointer are on the
864 * same cacheline, the Head Pointer must not be greater than the Tail
867 * We use ring->head as the last known location of the actual RING_HEAD,
868 * it may have advanced but in the worst case it is equally the same
869 * as ring->head and so we should never program RING_TAIL to advance
870 * into the same cacheline as ring->head.
872 #define cacheline(a) round_down(a, CACHELINE_BYTES)
873 GEM_BUG_ON(cacheline(tail
) == cacheline(ring
->head
) &&
878 static inline unsigned int
879 intel_ring_set_tail(struct intel_ring
*ring
, unsigned int tail
)
881 /* Whilst writes to the tail are strictly order, there is no
882 * serialisation between readers and the writers. The tail may be
883 * read by i915_request_retire() just as it is being updated
884 * by execlists, as although the breadcrumb is complete, the context
885 * switch hasn't been seen.
887 assert_ring_tail_valid(ring
, tail
);
892 void intel_engine_init_global_seqno(struct intel_engine_cs
*engine
, u32 seqno
);
894 void intel_engine_setup_common(struct intel_engine_cs
*engine
);
895 int intel_engine_init_common(struct intel_engine_cs
*engine
);
896 void intel_engine_cleanup_common(struct intel_engine_cs
*engine
);
898 int intel_init_render_ring_buffer(struct intel_engine_cs
*engine
);
899 int intel_init_bsd_ring_buffer(struct intel_engine_cs
*engine
);
900 int intel_init_blt_ring_buffer(struct intel_engine_cs
*engine
);
901 int intel_init_vebox_ring_buffer(struct intel_engine_cs
*engine
);
903 int intel_engine_stop_cs(struct intel_engine_cs
*engine
);
904 void intel_engine_cancel_stop_cs(struct intel_engine_cs
*engine
);
906 u64
intel_engine_get_active_head(const struct intel_engine_cs
*engine
);
907 u64
intel_engine_get_last_batch_head(const struct intel_engine_cs
*engine
);
909 static inline u32
intel_engine_last_submit(struct intel_engine_cs
*engine
)
912 * We are only peeking at the tail of the submit queue (and not the
913 * queue itself) in order to gain a hint as to the current active
914 * state of the engine. Callers are not expected to be taking
915 * engine->timeline->lock, nor are they expected to be concerned
916 * wtih serialising this hint with anything, so document it as
917 * a hint and nothing more.
919 return READ_ONCE(engine
->timeline
.seqno
);
922 static inline u32
intel_engine_get_seqno(struct intel_engine_cs
*engine
)
924 return intel_read_status_page(engine
, I915_GEM_HWS_INDEX
);
927 static inline bool intel_engine_signaled(struct intel_engine_cs
*engine
,
930 return i915_seqno_passed(intel_engine_get_seqno(engine
), seqno
);
933 static inline bool intel_engine_has_completed(struct intel_engine_cs
*engine
,
937 return intel_engine_signaled(engine
, seqno
);
940 static inline bool intel_engine_has_started(struct intel_engine_cs
*engine
,
944 return intel_engine_signaled(engine
, seqno
- 1);
947 void intel_engine_get_instdone(struct intel_engine_cs
*engine
,
948 struct intel_instdone
*instdone
);
951 * Arbitrary size for largest possible 'add request' sequence. The code paths
952 * are complex and variable. Empirical measurement shows that the worst case
953 * is BDW at 192 bytes (6 + 6 + 36 dwords), then ILK at 136 bytes. However,
954 * we need to allocate double the largest single packet within that emission
955 * to account for tail wraparound (so 6 + 6 + 72 dwords for BDW).
957 #define MIN_SPACE_FOR_ADD_REQUEST 336
959 static inline u32
intel_hws_seqno_address(struct intel_engine_cs
*engine
)
961 return engine
->status_page
.ggtt_offset
+ I915_GEM_HWS_INDEX_ADDR
;
964 static inline u32
intel_hws_preempt_done_address(struct intel_engine_cs
*engine
)
966 return engine
->status_page
.ggtt_offset
+ I915_GEM_HWS_PREEMPT_ADDR
;
969 /* intel_breadcrumbs.c -- user interrupt bottom-half for waiters */
970 int intel_engine_init_breadcrumbs(struct intel_engine_cs
*engine
);
972 static inline void intel_wait_init(struct intel_wait
*wait
)
975 wait
->request
= NULL
;
978 static inline void intel_wait_init_for_seqno(struct intel_wait
*wait
, u32 seqno
)
984 static inline bool intel_wait_has_seqno(const struct intel_wait
*wait
)
990 intel_wait_update_seqno(struct intel_wait
*wait
, u32 seqno
)
993 return intel_wait_has_seqno(wait
);
997 intel_wait_update_request(struct intel_wait
*wait
,
998 const struct i915_request
*rq
)
1000 return intel_wait_update_seqno(wait
, i915_request_global_seqno(rq
));
1004 intel_wait_check_seqno(const struct intel_wait
*wait
, u32 seqno
)
1006 return wait
->seqno
== seqno
;
1010 intel_wait_check_request(const struct intel_wait
*wait
,
1011 const struct i915_request
*rq
)
1013 return intel_wait_check_seqno(wait
, i915_request_global_seqno(rq
));
1016 static inline bool intel_wait_complete(const struct intel_wait
*wait
)
1018 return RB_EMPTY_NODE(&wait
->node
);
1021 bool intel_engine_add_wait(struct intel_engine_cs
*engine
,
1022 struct intel_wait
*wait
);
1023 void intel_engine_remove_wait(struct intel_engine_cs
*engine
,
1024 struct intel_wait
*wait
);
1025 bool intel_engine_enable_signaling(struct i915_request
*request
, bool wakeup
);
1026 void intel_engine_cancel_signaling(struct i915_request
*request
);
1028 static inline bool intel_engine_has_waiter(const struct intel_engine_cs
*engine
)
1030 return READ_ONCE(engine
->breadcrumbs
.irq_wait
);
1033 unsigned int intel_engine_wakeup(struct intel_engine_cs
*engine
);
1034 #define ENGINE_WAKEUP_WAITER BIT(0)
1035 #define ENGINE_WAKEUP_ASLEEP BIT(1)
1037 void intel_engine_pin_breadcrumbs_irq(struct intel_engine_cs
*engine
);
1038 void intel_engine_unpin_breadcrumbs_irq(struct intel_engine_cs
*engine
);
1040 void __intel_engine_disarm_breadcrumbs(struct intel_engine_cs
*engine
);
1041 void intel_engine_disarm_breadcrumbs(struct intel_engine_cs
*engine
);
1043 void intel_engine_reset_breadcrumbs(struct intel_engine_cs
*engine
);
1044 void intel_engine_fini_breadcrumbs(struct intel_engine_cs
*engine
);
1046 static inline u32
*gen8_emit_pipe_control(u32
*batch
, u32 flags
, u32 offset
)
1048 memset(batch
, 0, 6 * sizeof(u32
));
1050 batch
[0] = GFX_OP_PIPE_CONTROL(6);
1058 gen8_emit_ggtt_write_rcs(u32
*cs
, u32 value
, u32 gtt_offset
)
1060 /* We're using qword write, offset should be aligned to 8 bytes. */
1061 GEM_BUG_ON(!IS_ALIGNED(gtt_offset
, 8));
1063 /* w/a for post sync ops following a GPGPU operation we
1064 * need a prior CS_STALL, which is emitted by the flush
1065 * following the batch.
1067 *cs
++ = GFX_OP_PIPE_CONTROL(6);
1068 *cs
++ = PIPE_CONTROL_GLOBAL_GTT_IVB
| PIPE_CONTROL_CS_STALL
|
1069 PIPE_CONTROL_QW_WRITE
;
1073 /* We're thrashing one dword of HWS. */
1080 gen8_emit_ggtt_write(u32
*cs
, u32 value
, u32 gtt_offset
)
1082 /* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */
1083 GEM_BUG_ON(gtt_offset
& (1 << 5));
1084 /* Offset should be aligned to 8 bytes for both (QW/DW) write types */
1085 GEM_BUG_ON(!IS_ALIGNED(gtt_offset
, 8));
1087 *cs
++ = (MI_FLUSH_DW
+ 1) | MI_FLUSH_DW_OP_STOREDW
;
1088 *cs
++ = gtt_offset
| MI_FLUSH_DW_USE_GTT
;
1095 void intel_engines_sanitize(struct drm_i915_private
*i915
);
1097 bool intel_engine_is_idle(struct intel_engine_cs
*engine
);
1098 bool intel_engines_are_idle(struct drm_i915_private
*dev_priv
);
1100 bool intel_engine_has_kernel_context(const struct intel_engine_cs
*engine
);
1101 void intel_engine_lost_context(struct intel_engine_cs
*engine
);
1103 void intel_engines_park(struct drm_i915_private
*i915
);
1104 void intel_engines_unpark(struct drm_i915_private
*i915
);
1106 void intel_engines_reset_default_submission(struct drm_i915_private
*i915
);
1107 unsigned int intel_engines_has_context_isolation(struct drm_i915_private
*i915
);
1109 bool intel_engine_can_store_dword(struct intel_engine_cs
*engine
);
1112 void intel_engine_dump(struct intel_engine_cs
*engine
,
1113 struct drm_printer
*m
,
1114 const char *header
, ...);
1116 struct intel_engine_cs
*
1117 intel_engine_lookup_user(struct drm_i915_private
*i915
, u8
class, u8 instance
);
1119 static inline void intel_engine_context_in(struct intel_engine_cs
*engine
)
1121 unsigned long flags
;
1123 if (READ_ONCE(engine
->stats
.enabled
) == 0)
1126 write_seqlock_irqsave(&engine
->stats
.lock
, flags
);
1128 if (engine
->stats
.enabled
> 0) {
1129 if (engine
->stats
.active
++ == 0)
1130 engine
->stats
.start
= ktime_get();
1131 GEM_BUG_ON(engine
->stats
.active
== 0);
1134 write_sequnlock_irqrestore(&engine
->stats
.lock
, flags
);
1137 static inline void intel_engine_context_out(struct intel_engine_cs
*engine
)
1139 unsigned long flags
;
1141 if (READ_ONCE(engine
->stats
.enabled
) == 0)
1144 write_seqlock_irqsave(&engine
->stats
.lock
, flags
);
1146 if (engine
->stats
.enabled
> 0) {
1149 if (engine
->stats
.active
&& --engine
->stats
.active
== 0) {
1151 * Decrement the active context count and in case GPU
1152 * is now idle add up to the running total.
1154 last
= ktime_sub(ktime_get(), engine
->stats
.start
);
1156 engine
->stats
.total
= ktime_add(engine
->stats
.total
,
1158 } else if (engine
->stats
.active
== 0) {
1160 * After turning on engine stats, context out might be
1161 * the first event in which case we account from the
1162 * time stats gathering was turned on.
1164 last
= ktime_sub(ktime_get(), engine
->stats
.enabled_at
);
1166 engine
->stats
.total
= ktime_add(engine
->stats
.total
,
1171 write_sequnlock_irqrestore(&engine
->stats
.lock
, flags
);
1174 int intel_enable_engine_stats(struct intel_engine_cs
*engine
);
1175 void intel_disable_engine_stats(struct intel_engine_cs
*engine
);
1177 ktime_t
intel_engine_get_busy_time(struct intel_engine_cs
*engine
);
1179 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1181 static inline bool inject_preempt_hang(struct intel_engine_execlists
*execlists
)
1183 if (!execlists
->preempt_hang
.inject_hang
)
1186 complete(&execlists
->preempt_hang
.completion
);
1192 static inline bool inject_preempt_hang(struct intel_engine_execlists
*execlists
)
1199 #endif /* _INTEL_RINGBUFFER_H_ */