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drm/i915: extract intel_connector.h from intel_drv.h
[thirdparty/kernel/stable.git] / drivers / gpu / drm / i915 / intel_sdvo.c
1 /*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2007 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 */
28
29 #include <linux/delay.h>
30 #include <linux/export.h>
31 #include <linux/i2c.h>
32 #include <linux/slab.h>
33
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_edid.h>
37 #include <drm/i915_drm.h>
38
39 #include "i915_drv.h"
40 #include "intel_connector.h"
41 #include "intel_drv.h"
42 #include "intel_sdvo_regs.h"
43
44 #define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
45 #define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
46 #define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
47 #define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0)
48
49 #define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
50 SDVO_TV_MASK)
51
52 #define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
53 #define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK)
54 #define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
55 #define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
56 #define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK))
57
58
59 static const char * const tv_format_names[] = {
60 "NTSC_M" , "NTSC_J" , "NTSC_443",
61 "PAL_B" , "PAL_D" , "PAL_G" ,
62 "PAL_H" , "PAL_I" , "PAL_M" ,
63 "PAL_N" , "PAL_NC" , "PAL_60" ,
64 "SECAM_B" , "SECAM_D" , "SECAM_G" ,
65 "SECAM_K" , "SECAM_K1", "SECAM_L" ,
66 "SECAM_60"
67 };
68
69 #define TV_FORMAT_NUM ARRAY_SIZE(tv_format_names)
70
71 struct intel_sdvo {
72 struct intel_encoder base;
73
74 struct i2c_adapter *i2c;
75 u8 slave_addr;
76
77 struct i2c_adapter ddc;
78
79 /* Register for the SDVO device: SDVOB or SDVOC */
80 i915_reg_t sdvo_reg;
81
82 /* Active outputs controlled by this SDVO output */
83 u16 controlled_output;
84
85 /*
86 * Capabilities of the SDVO device returned by
87 * intel_sdvo_get_capabilities()
88 */
89 struct intel_sdvo_caps caps;
90
91 /* Pixel clock limitations reported by the SDVO device, in kHz */
92 int pixel_clock_min, pixel_clock_max;
93
94 /*
95 * For multiple function SDVO device,
96 * this is for current attached outputs.
97 */
98 u16 attached_output;
99
100 /*
101 * Hotplug activation bits for this device
102 */
103 u16 hotplug_active;
104
105 enum port port;
106
107 bool has_hdmi_monitor;
108 bool has_hdmi_audio;
109
110 /* DDC bus used by this SDVO encoder */
111 u8 ddc_bus;
112
113 /*
114 * the sdvo flag gets lost in round trip: dtd->adjusted_mode->dtd
115 */
116 u8 dtd_sdvo_flags;
117 };
118
119 struct intel_sdvo_connector {
120 struct intel_connector base;
121
122 /* Mark the type of connector */
123 u16 output_flag;
124
125 /* This contains all current supported TV format */
126 u8 tv_format_supported[TV_FORMAT_NUM];
127 int format_supported_num;
128 struct drm_property *tv_format;
129
130 /* add the property for the SDVO-TV */
131 struct drm_property *left;
132 struct drm_property *right;
133 struct drm_property *top;
134 struct drm_property *bottom;
135 struct drm_property *hpos;
136 struct drm_property *vpos;
137 struct drm_property *contrast;
138 struct drm_property *saturation;
139 struct drm_property *hue;
140 struct drm_property *sharpness;
141 struct drm_property *flicker_filter;
142 struct drm_property *flicker_filter_adaptive;
143 struct drm_property *flicker_filter_2d;
144 struct drm_property *tv_chroma_filter;
145 struct drm_property *tv_luma_filter;
146 struct drm_property *dot_crawl;
147
148 /* add the property for the SDVO-TV/LVDS */
149 struct drm_property *brightness;
150
151 /* this is to get the range of margin.*/
152 u32 max_hscan, max_vscan;
153
154 /**
155 * This is set if we treat the device as HDMI, instead of DVI.
156 */
157 bool is_hdmi;
158 };
159
160 struct intel_sdvo_connector_state {
161 /* base.base: tv.saturation/contrast/hue/brightness */
162 struct intel_digital_connector_state base;
163
164 struct {
165 unsigned overscan_h, overscan_v, hpos, vpos, sharpness;
166 unsigned flicker_filter, flicker_filter_2d, flicker_filter_adaptive;
167 unsigned chroma_filter, luma_filter, dot_crawl;
168 } tv;
169 };
170
171 static struct intel_sdvo *to_sdvo(struct intel_encoder *encoder)
172 {
173 return container_of(encoder, struct intel_sdvo, base);
174 }
175
176 static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector)
177 {
178 return to_sdvo(intel_attached_encoder(connector));
179 }
180
181 static struct intel_sdvo_connector *
182 to_intel_sdvo_connector(struct drm_connector *connector)
183 {
184 return container_of(connector, struct intel_sdvo_connector, base.base);
185 }
186
187 #define to_intel_sdvo_connector_state(conn_state) \
188 container_of((conn_state), struct intel_sdvo_connector_state, base.base)
189
190 static bool
191 intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, u16 flags);
192 static bool
193 intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
194 struct intel_sdvo_connector *intel_sdvo_connector,
195 int type);
196 static bool
197 intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
198 struct intel_sdvo_connector *intel_sdvo_connector);
199
200 /*
201 * Writes the SDVOB or SDVOC with the given value, but always writes both
202 * SDVOB and SDVOC to work around apparent hardware issues (according to
203 * comments in the BIOS).
204 */
205 static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
206 {
207 struct drm_device *dev = intel_sdvo->base.base.dev;
208 struct drm_i915_private *dev_priv = to_i915(dev);
209 u32 bval = val, cval = val;
210 int i;
211
212 if (HAS_PCH_SPLIT(dev_priv)) {
213 I915_WRITE(intel_sdvo->sdvo_reg, val);
214 POSTING_READ(intel_sdvo->sdvo_reg);
215 /*
216 * HW workaround, need to write this twice for issue
217 * that may result in first write getting masked.
218 */
219 if (HAS_PCH_IBX(dev_priv)) {
220 I915_WRITE(intel_sdvo->sdvo_reg, val);
221 POSTING_READ(intel_sdvo->sdvo_reg);
222 }
223 return;
224 }
225
226 if (intel_sdvo->port == PORT_B)
227 cval = I915_READ(GEN3_SDVOC);
228 else
229 bval = I915_READ(GEN3_SDVOB);
230
231 /*
232 * Write the registers twice for luck. Sometimes,
233 * writing them only once doesn't appear to 'stick'.
234 * The BIOS does this too. Yay, magic
235 */
236 for (i = 0; i < 2; i++) {
237 I915_WRITE(GEN3_SDVOB, bval);
238 POSTING_READ(GEN3_SDVOB);
239
240 I915_WRITE(GEN3_SDVOC, cval);
241 POSTING_READ(GEN3_SDVOC);
242 }
243 }
244
245 static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
246 {
247 struct i2c_msg msgs[] = {
248 {
249 .addr = intel_sdvo->slave_addr,
250 .flags = 0,
251 .len = 1,
252 .buf = &addr,
253 },
254 {
255 .addr = intel_sdvo->slave_addr,
256 .flags = I2C_M_RD,
257 .len = 1,
258 .buf = ch,
259 }
260 };
261 int ret;
262
263 if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2)
264 return true;
265
266 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
267 return false;
268 }
269
270 #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
271 /** Mapping of command numbers to names, for debug output */
272 static const struct _sdvo_cmd_name {
273 u8 cmd;
274 const char *name;
275 } __attribute__ ((packed)) sdvo_cmd_names[] = {
276 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
277 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
278 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
279 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
280 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
281 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
282 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
283 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
284 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
285 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
286 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
287 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
288 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
289 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
290 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
291 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
292 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
293 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
294 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
295 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
296 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
297 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
298 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
299 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
300 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
301 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
302 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
303 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
304 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
305 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
306 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
307 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
308 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
309 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
310 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
311 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
319
320 /* Add the op code for SDVO enhancements */
321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
324 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
325 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
327 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
329 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
330 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
331 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
335 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
336 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
337 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
339 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
340 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
341 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
342 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
343 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
344 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
345 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
354 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
355 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
356 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
357 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
358 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
359 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
360 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
361 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
362 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
363 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
364 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
365
366 /* HDMI op code */
367 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
368 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
369 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
370 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
371 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
372 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
373 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
374 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
375 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
376 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
377 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
378 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
379 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
380 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
381 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
382 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
383 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
384 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
385 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
386 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
387 };
388
389 #define SDVO_NAME(svdo) ((svdo)->port == PORT_B ? "SDVOB" : "SDVOC")
390
391 static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
392 const void *args, int args_len)
393 {
394 int i, pos = 0;
395 #define BUF_LEN 256
396 char buffer[BUF_LEN];
397
398 #define BUF_PRINT(args...) \
399 pos += snprintf(buffer + pos, max_t(int, BUF_LEN - pos, 0), args)
400
401
402 for (i = 0; i < args_len; i++) {
403 BUF_PRINT("%02X ", ((u8 *)args)[i]);
404 }
405 for (; i < 8; i++) {
406 BUF_PRINT(" ");
407 }
408 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
409 if (cmd == sdvo_cmd_names[i].cmd) {
410 BUF_PRINT("(%s)", sdvo_cmd_names[i].name);
411 break;
412 }
413 }
414 if (i == ARRAY_SIZE(sdvo_cmd_names)) {
415 BUF_PRINT("(%02X)", cmd);
416 }
417 BUG_ON(pos >= BUF_LEN - 1);
418 #undef BUF_PRINT
419 #undef BUF_LEN
420
421 DRM_DEBUG_KMS("%s: W: %02X %s\n", SDVO_NAME(intel_sdvo), cmd, buffer);
422 }
423
424 static const char * const cmd_status_names[] = {
425 "Power on",
426 "Success",
427 "Not supported",
428 "Invalid arg",
429 "Pending",
430 "Target not specified",
431 "Scaling not supported"
432 };
433
434 static bool __intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
435 const void *args, int args_len,
436 bool unlocked)
437 {
438 u8 *buf, status;
439 struct i2c_msg *msgs;
440 int i, ret = true;
441
442 /* Would be simpler to allocate both in one go ? */
443 buf = kzalloc(args_len * 2 + 2, GFP_KERNEL);
444 if (!buf)
445 return false;
446
447 msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL);
448 if (!msgs) {
449 kfree(buf);
450 return false;
451 }
452
453 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
454
455 for (i = 0; i < args_len; i++) {
456 msgs[i].addr = intel_sdvo->slave_addr;
457 msgs[i].flags = 0;
458 msgs[i].len = 2;
459 msgs[i].buf = buf + 2 *i;
460 buf[2*i + 0] = SDVO_I2C_ARG_0 - i;
461 buf[2*i + 1] = ((u8*)args)[i];
462 }
463 msgs[i].addr = intel_sdvo->slave_addr;
464 msgs[i].flags = 0;
465 msgs[i].len = 2;
466 msgs[i].buf = buf + 2*i;
467 buf[2*i + 0] = SDVO_I2C_OPCODE;
468 buf[2*i + 1] = cmd;
469
470 /* the following two are to read the response */
471 status = SDVO_I2C_CMD_STATUS;
472 msgs[i+1].addr = intel_sdvo->slave_addr;
473 msgs[i+1].flags = 0;
474 msgs[i+1].len = 1;
475 msgs[i+1].buf = &status;
476
477 msgs[i+2].addr = intel_sdvo->slave_addr;
478 msgs[i+2].flags = I2C_M_RD;
479 msgs[i+2].len = 1;
480 msgs[i+2].buf = &status;
481
482 if (unlocked)
483 ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3);
484 else
485 ret = __i2c_transfer(intel_sdvo->i2c, msgs, i+3);
486 if (ret < 0) {
487 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
488 ret = false;
489 goto out;
490 }
491 if (ret != i+3) {
492 /* failure in I2C transfer */
493 DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3);
494 ret = false;
495 }
496
497 out:
498 kfree(msgs);
499 kfree(buf);
500 return ret;
501 }
502
503 static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
504 const void *args, int args_len)
505 {
506 return __intel_sdvo_write_cmd(intel_sdvo, cmd, args, args_len, true);
507 }
508
509 static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
510 void *response, int response_len)
511 {
512 u8 retry = 15; /* 5 quick checks, followed by 10 long checks */
513 u8 status;
514 int i, pos = 0;
515 #define BUF_LEN 256
516 char buffer[BUF_LEN];
517
518
519 /*
520 * The documentation states that all commands will be
521 * processed within 15µs, and that we need only poll
522 * the status byte a maximum of 3 times in order for the
523 * command to be complete.
524 *
525 * Check 5 times in case the hardware failed to read the docs.
526 *
527 * Also beware that the first response by many devices is to
528 * reply PENDING and stall for time. TVs are notorious for
529 * requiring longer than specified to complete their replies.
530 * Originally (in the DDX long ago), the delay was only ever 15ms
531 * with an additional delay of 30ms applied for TVs added later after
532 * many experiments. To accommodate both sets of delays, we do a
533 * sequence of slow checks if the device is falling behind and fails
534 * to reply within 5*15µs.
535 */
536 if (!intel_sdvo_read_byte(intel_sdvo,
537 SDVO_I2C_CMD_STATUS,
538 &status))
539 goto log_fail;
540
541 while ((status == SDVO_CMD_STATUS_PENDING ||
542 status == SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED) && --retry) {
543 if (retry < 10)
544 msleep(15);
545 else
546 udelay(15);
547
548 if (!intel_sdvo_read_byte(intel_sdvo,
549 SDVO_I2C_CMD_STATUS,
550 &status))
551 goto log_fail;
552 }
553
554 #define BUF_PRINT(args...) \
555 pos += snprintf(buffer + pos, max_t(int, BUF_LEN - pos, 0), args)
556
557 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
558 BUF_PRINT("(%s)", cmd_status_names[status]);
559 else
560 BUF_PRINT("(??? %d)", status);
561
562 if (status != SDVO_CMD_STATUS_SUCCESS)
563 goto log_fail;
564
565 /* Read the command response */
566 for (i = 0; i < response_len; i++) {
567 if (!intel_sdvo_read_byte(intel_sdvo,
568 SDVO_I2C_RETURN_0 + i,
569 &((u8 *)response)[i]))
570 goto log_fail;
571 BUF_PRINT(" %02X", ((u8 *)response)[i]);
572 }
573 BUG_ON(pos >= BUF_LEN - 1);
574 #undef BUF_PRINT
575 #undef BUF_LEN
576
577 DRM_DEBUG_KMS("%s: R: %s\n", SDVO_NAME(intel_sdvo), buffer);
578 return true;
579
580 log_fail:
581 DRM_DEBUG_KMS("%s: R: ... failed\n", SDVO_NAME(intel_sdvo));
582 return false;
583 }
584
585 static int intel_sdvo_get_pixel_multiplier(const struct drm_display_mode *adjusted_mode)
586 {
587 if (adjusted_mode->crtc_clock >= 100000)
588 return 1;
589 else if (adjusted_mode->crtc_clock >= 50000)
590 return 2;
591 else
592 return 4;
593 }
594
595 static bool __intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
596 u8 ddc_bus)
597 {
598 /* This must be the immediately preceding write before the i2c xfer */
599 return __intel_sdvo_write_cmd(intel_sdvo,
600 SDVO_CMD_SET_CONTROL_BUS_SWITCH,
601 &ddc_bus, 1, false);
602 }
603
604 static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
605 {
606 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
607 return false;
608
609 return intel_sdvo_read_response(intel_sdvo, NULL, 0);
610 }
611
612 static bool
613 intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)
614 {
615 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
616 return false;
617
618 return intel_sdvo_read_response(intel_sdvo, value, len);
619 }
620
621 static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
622 {
623 struct intel_sdvo_set_target_input_args targets = {0};
624 return intel_sdvo_set_value(intel_sdvo,
625 SDVO_CMD_SET_TARGET_INPUT,
626 &targets, sizeof(targets));
627 }
628
629 /*
630 * Return whether each input is trained.
631 *
632 * This function is making an assumption about the layout of the response,
633 * which should be checked against the docs.
634 */
635 static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
636 {
637 struct intel_sdvo_get_trained_inputs_response response;
638
639 BUILD_BUG_ON(sizeof(response) != 1);
640 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
641 &response, sizeof(response)))
642 return false;
643
644 *input_1 = response.input0_trained;
645 *input_2 = response.input1_trained;
646 return true;
647 }
648
649 static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
650 u16 outputs)
651 {
652 return intel_sdvo_set_value(intel_sdvo,
653 SDVO_CMD_SET_ACTIVE_OUTPUTS,
654 &outputs, sizeof(outputs));
655 }
656
657 static bool intel_sdvo_get_active_outputs(struct intel_sdvo *intel_sdvo,
658 u16 *outputs)
659 {
660 return intel_sdvo_get_value(intel_sdvo,
661 SDVO_CMD_GET_ACTIVE_OUTPUTS,
662 outputs, sizeof(*outputs));
663 }
664
665 static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
666 int mode)
667 {
668 u8 state = SDVO_ENCODER_STATE_ON;
669
670 switch (mode) {
671 case DRM_MODE_DPMS_ON:
672 state = SDVO_ENCODER_STATE_ON;
673 break;
674 case DRM_MODE_DPMS_STANDBY:
675 state = SDVO_ENCODER_STATE_STANDBY;
676 break;
677 case DRM_MODE_DPMS_SUSPEND:
678 state = SDVO_ENCODER_STATE_SUSPEND;
679 break;
680 case DRM_MODE_DPMS_OFF:
681 state = SDVO_ENCODER_STATE_OFF;
682 break;
683 }
684
685 return intel_sdvo_set_value(intel_sdvo,
686 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
687 }
688
689 static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
690 int *clock_min,
691 int *clock_max)
692 {
693 struct intel_sdvo_pixel_clock_range clocks;
694
695 BUILD_BUG_ON(sizeof(clocks) != 4);
696 if (!intel_sdvo_get_value(intel_sdvo,
697 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
698 &clocks, sizeof(clocks)))
699 return false;
700
701 /* Convert the values from units of 10 kHz to kHz. */
702 *clock_min = clocks.min * 10;
703 *clock_max = clocks.max * 10;
704 return true;
705 }
706
707 static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
708 u16 outputs)
709 {
710 return intel_sdvo_set_value(intel_sdvo,
711 SDVO_CMD_SET_TARGET_OUTPUT,
712 &outputs, sizeof(outputs));
713 }
714
715 static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
716 struct intel_sdvo_dtd *dtd)
717 {
718 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
719 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
720 }
721
722 static bool intel_sdvo_get_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
723 struct intel_sdvo_dtd *dtd)
724 {
725 return intel_sdvo_get_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
726 intel_sdvo_get_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
727 }
728
729 static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
730 struct intel_sdvo_dtd *dtd)
731 {
732 return intel_sdvo_set_timing(intel_sdvo,
733 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
734 }
735
736 static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
737 struct intel_sdvo_dtd *dtd)
738 {
739 return intel_sdvo_set_timing(intel_sdvo,
740 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
741 }
742
743 static bool intel_sdvo_get_input_timing(struct intel_sdvo *intel_sdvo,
744 struct intel_sdvo_dtd *dtd)
745 {
746 return intel_sdvo_get_timing(intel_sdvo,
747 SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd);
748 }
749
750 static bool
751 intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
752 struct intel_sdvo_connector *intel_sdvo_connector,
753 u16 clock,
754 u16 width,
755 u16 height)
756 {
757 struct intel_sdvo_preferred_input_timing_args args;
758
759 memset(&args, 0, sizeof(args));
760 args.clock = clock;
761 args.width = width;
762 args.height = height;
763 args.interlace = 0;
764
765 if (IS_LVDS(intel_sdvo_connector)) {
766 const struct drm_display_mode *fixed_mode =
767 intel_sdvo_connector->base.panel.fixed_mode;
768
769 if (fixed_mode->hdisplay != width ||
770 fixed_mode->vdisplay != height)
771 args.scaled = 1;
772 }
773
774 return intel_sdvo_set_value(intel_sdvo,
775 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
776 &args, sizeof(args));
777 }
778
779 static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
780 struct intel_sdvo_dtd *dtd)
781 {
782 BUILD_BUG_ON(sizeof(dtd->part1) != 8);
783 BUILD_BUG_ON(sizeof(dtd->part2) != 8);
784 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
785 &dtd->part1, sizeof(dtd->part1)) &&
786 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
787 &dtd->part2, sizeof(dtd->part2));
788 }
789
790 static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
791 {
792 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
793 }
794
795 static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
796 const struct drm_display_mode *mode)
797 {
798 u16 width, height;
799 u16 h_blank_len, h_sync_len, v_blank_len, v_sync_len;
800 u16 h_sync_offset, v_sync_offset;
801 int mode_clock;
802
803 memset(dtd, 0, sizeof(*dtd));
804
805 width = mode->hdisplay;
806 height = mode->vdisplay;
807
808 /* do some mode translations */
809 h_blank_len = mode->htotal - mode->hdisplay;
810 h_sync_len = mode->hsync_end - mode->hsync_start;
811
812 v_blank_len = mode->vtotal - mode->vdisplay;
813 v_sync_len = mode->vsync_end - mode->vsync_start;
814
815 h_sync_offset = mode->hsync_start - mode->hdisplay;
816 v_sync_offset = mode->vsync_start - mode->vdisplay;
817
818 mode_clock = mode->clock;
819 mode_clock /= 10;
820 dtd->part1.clock = mode_clock;
821
822 dtd->part1.h_active = width & 0xff;
823 dtd->part1.h_blank = h_blank_len & 0xff;
824 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
825 ((h_blank_len >> 8) & 0xf);
826 dtd->part1.v_active = height & 0xff;
827 dtd->part1.v_blank = v_blank_len & 0xff;
828 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
829 ((v_blank_len >> 8) & 0xf);
830
831 dtd->part2.h_sync_off = h_sync_offset & 0xff;
832 dtd->part2.h_sync_width = h_sync_len & 0xff;
833 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
834 (v_sync_len & 0xf);
835 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
836 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
837 ((v_sync_len & 0x30) >> 4);
838
839 dtd->part2.dtd_flags = 0x18;
840 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
841 dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE;
842 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
843 dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE;
844 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
845 dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE;
846
847 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
848 }
849
850 static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode *pmode,
851 const struct intel_sdvo_dtd *dtd)
852 {
853 struct drm_display_mode mode = {};
854
855 mode.hdisplay = dtd->part1.h_active;
856 mode.hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
857 mode.hsync_start = mode.hdisplay + dtd->part2.h_sync_off;
858 mode.hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
859 mode.hsync_end = mode.hsync_start + dtd->part2.h_sync_width;
860 mode.hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
861 mode.htotal = mode.hdisplay + dtd->part1.h_blank;
862 mode.htotal += (dtd->part1.h_high & 0xf) << 8;
863
864 mode.vdisplay = dtd->part1.v_active;
865 mode.vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
866 mode.vsync_start = mode.vdisplay;
867 mode.vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
868 mode.vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
869 mode.vsync_start += dtd->part2.v_sync_off_high & 0xc0;
870 mode.vsync_end = mode.vsync_start +
871 (dtd->part2.v_sync_off_width & 0xf);
872 mode.vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
873 mode.vtotal = mode.vdisplay + dtd->part1.v_blank;
874 mode.vtotal += (dtd->part1.v_high & 0xf) << 8;
875
876 mode.clock = dtd->part1.clock * 10;
877
878 if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE)
879 mode.flags |= DRM_MODE_FLAG_INTERLACE;
880 if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
881 mode.flags |= DRM_MODE_FLAG_PHSYNC;
882 else
883 mode.flags |= DRM_MODE_FLAG_NHSYNC;
884 if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
885 mode.flags |= DRM_MODE_FLAG_PVSYNC;
886 else
887 mode.flags |= DRM_MODE_FLAG_NVSYNC;
888
889 drm_mode_set_crtcinfo(&mode, 0);
890
891 drm_mode_copy(pmode, &mode);
892 }
893
894 static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo)
895 {
896 struct intel_sdvo_encode encode;
897
898 BUILD_BUG_ON(sizeof(encode) != 2);
899 return intel_sdvo_get_value(intel_sdvo,
900 SDVO_CMD_GET_SUPP_ENCODE,
901 &encode, sizeof(encode));
902 }
903
904 static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
905 u8 mode)
906 {
907 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
908 }
909
910 static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
911 u8 mode)
912 {
913 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
914 }
915
916 #if 0
917 static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
918 {
919 int i, j;
920 u8 set_buf_index[2];
921 u8 av_split;
922 u8 buf_size;
923 u8 buf[48];
924 u8 *pos;
925
926 intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
927
928 for (i = 0; i <= av_split; i++) {
929 set_buf_index[0] = i; set_buf_index[1] = 0;
930 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
931 set_buf_index, 2);
932 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
933 intel_sdvo_read_response(encoder, &buf_size, 1);
934
935 pos = buf;
936 for (j = 0; j <= buf_size; j += 8) {
937 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
938 NULL, 0);
939 intel_sdvo_read_response(encoder, pos, 8);
940 pos += 8;
941 }
942 }
943 }
944 #endif
945
946 static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo,
947 unsigned int if_index, u8 tx_rate,
948 const u8 *data, unsigned int length)
949 {
950 u8 set_buf_index[2] = { if_index, 0 };
951 u8 hbuf_size, tmp[8];
952 int i;
953
954 if (!intel_sdvo_set_value(intel_sdvo,
955 SDVO_CMD_SET_HBUF_INDEX,
956 set_buf_index, 2))
957 return false;
958
959 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO,
960 &hbuf_size, 1))
961 return false;
962
963 /* Buffer size is 0 based, hooray! */
964 hbuf_size++;
965
966 DRM_DEBUG_KMS("writing sdvo hbuf: %i, hbuf_size %i, hbuf_size: %i\n",
967 if_index, length, hbuf_size);
968
969 for (i = 0; i < hbuf_size; i += 8) {
970 memset(tmp, 0, 8);
971 if (i < length)
972 memcpy(tmp, data + i, min_t(unsigned, 8, length - i));
973
974 if (!intel_sdvo_set_value(intel_sdvo,
975 SDVO_CMD_SET_HBUF_DATA,
976 tmp, 8))
977 return false;
978 }
979
980 return intel_sdvo_set_value(intel_sdvo,
981 SDVO_CMD_SET_HBUF_TXRATE,
982 &tx_rate, 1);
983 }
984
985 static ssize_t intel_sdvo_read_infoframe(struct intel_sdvo *intel_sdvo,
986 unsigned int if_index,
987 u8 *data, unsigned int length)
988 {
989 u8 set_buf_index[2] = { if_index, 0 };
990 u8 hbuf_size, tx_rate, av_split;
991 int i;
992
993 if (!intel_sdvo_get_value(intel_sdvo,
994 SDVO_CMD_GET_HBUF_AV_SPLIT,
995 &av_split, 1))
996 return -ENXIO;
997
998 if (av_split < if_index)
999 return 0;
1000
1001 if (!intel_sdvo_get_value(intel_sdvo,
1002 SDVO_CMD_GET_HBUF_TXRATE,
1003 &tx_rate, 1))
1004 return -ENXIO;
1005
1006 if (tx_rate == SDVO_HBUF_TX_DISABLED)
1007 return 0;
1008
1009 if (!intel_sdvo_set_value(intel_sdvo,
1010 SDVO_CMD_SET_HBUF_INDEX,
1011 set_buf_index, 2))
1012 return -ENXIO;
1013
1014 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO,
1015 &hbuf_size, 1))
1016 return -ENXIO;
1017
1018 /* Buffer size is 0 based, hooray! */
1019 hbuf_size++;
1020
1021 DRM_DEBUG_KMS("reading sdvo hbuf: %i, hbuf_size %i, hbuf_size: %i\n",
1022 if_index, length, hbuf_size);
1023
1024 hbuf_size = min_t(unsigned int, length, hbuf_size);
1025
1026 for (i = 0; i < hbuf_size; i += 8) {
1027 if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_HBUF_DATA, NULL, 0))
1028 return -ENXIO;
1029 if (!intel_sdvo_read_response(intel_sdvo, &data[i],
1030 min_t(unsigned int, 8, hbuf_size - i)))
1031 return -ENXIO;
1032 }
1033
1034 return hbuf_size;
1035 }
1036
1037 static bool intel_sdvo_compute_avi_infoframe(struct intel_sdvo *intel_sdvo,
1038 struct intel_crtc_state *crtc_state,
1039 struct drm_connector_state *conn_state)
1040 {
1041 struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi;
1042 const struct drm_display_mode *adjusted_mode =
1043 &crtc_state->base.adjusted_mode;
1044 int ret;
1045
1046 if (!crtc_state->has_hdmi_sink)
1047 return true;
1048
1049 crtc_state->infoframes.enable |=
1050 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI);
1051
1052 ret = drm_hdmi_avi_infoframe_from_display_mode(frame,
1053 conn_state->connector,
1054 adjusted_mode);
1055 if (ret)
1056 return false;
1057
1058 drm_hdmi_avi_infoframe_quant_range(frame,
1059 conn_state->connector,
1060 adjusted_mode,
1061 crtc_state->limited_color_range ?
1062 HDMI_QUANTIZATION_RANGE_LIMITED :
1063 HDMI_QUANTIZATION_RANGE_FULL);
1064
1065 ret = hdmi_avi_infoframe_check(frame);
1066 if (WARN_ON(ret))
1067 return false;
1068
1069 return true;
1070 }
1071
1072 static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo,
1073 const struct intel_crtc_state *crtc_state)
1074 {
1075 u8 sdvo_data[HDMI_INFOFRAME_SIZE(AVI)];
1076 const union hdmi_infoframe *frame = &crtc_state->infoframes.avi;
1077 ssize_t len;
1078
1079 if ((crtc_state->infoframes.enable &
1080 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI)) == 0)
1081 return true;
1082
1083 if (WARN_ON(frame->any.type != HDMI_INFOFRAME_TYPE_AVI))
1084 return false;
1085
1086 len = hdmi_infoframe_pack_only(frame, sdvo_data, sizeof(sdvo_data));
1087 if (WARN_ON(len < 0))
1088 return false;
1089
1090 return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF,
1091 SDVO_HBUF_TX_VSYNC,
1092 sdvo_data, sizeof(sdvo_data));
1093 }
1094
1095 static void intel_sdvo_get_avi_infoframe(struct intel_sdvo *intel_sdvo,
1096 struct intel_crtc_state *crtc_state)
1097 {
1098 u8 sdvo_data[HDMI_INFOFRAME_SIZE(AVI)];
1099 union hdmi_infoframe *frame = &crtc_state->infoframes.avi;
1100 ssize_t len;
1101 int ret;
1102
1103 if (!crtc_state->has_hdmi_sink)
1104 return;
1105
1106 len = intel_sdvo_read_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF,
1107 sdvo_data, sizeof(sdvo_data));
1108 if (len < 0) {
1109 DRM_DEBUG_KMS("failed to read AVI infoframe\n");
1110 return;
1111 } else if (len == 0) {
1112 return;
1113 }
1114
1115 crtc_state->infoframes.enable |=
1116 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI);
1117
1118 ret = hdmi_infoframe_unpack(frame, sdvo_data, sizeof(sdvo_data));
1119 if (ret) {
1120 DRM_DEBUG_KMS("Failed to unpack AVI infoframe\n");
1121 return;
1122 }
1123
1124 if (frame->any.type != HDMI_INFOFRAME_TYPE_AVI)
1125 DRM_DEBUG_KMS("Found the wrong infoframe type 0x%x (expected 0x%02x)\n",
1126 frame->any.type, HDMI_INFOFRAME_TYPE_AVI);
1127 }
1128
1129 static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo,
1130 const struct drm_connector_state *conn_state)
1131 {
1132 struct intel_sdvo_tv_format format;
1133 u32 format_map;
1134
1135 format_map = 1 << conn_state->tv.mode;
1136 memset(&format, 0, sizeof(format));
1137 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
1138
1139 BUILD_BUG_ON(sizeof(format) != 6);
1140 return intel_sdvo_set_value(intel_sdvo,
1141 SDVO_CMD_SET_TV_FORMAT,
1142 &format, sizeof(format));
1143 }
1144
1145 static bool
1146 intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
1147 const struct drm_display_mode *mode)
1148 {
1149 struct intel_sdvo_dtd output_dtd;
1150
1151 if (!intel_sdvo_set_target_output(intel_sdvo,
1152 intel_sdvo->attached_output))
1153 return false;
1154
1155 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
1156 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1157 return false;
1158
1159 return true;
1160 }
1161
1162 /*
1163 * Asks the sdvo controller for the preferred input mode given the output mode.
1164 * Unfortunately we have to set up the full output mode to do that.
1165 */
1166 static bool
1167 intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo,
1168 struct intel_sdvo_connector *intel_sdvo_connector,
1169 const struct drm_display_mode *mode,
1170 struct drm_display_mode *adjusted_mode)
1171 {
1172 struct intel_sdvo_dtd input_dtd;
1173
1174 /* Reset the input timing to the screen. Assume always input 0. */
1175 if (!intel_sdvo_set_target_input(intel_sdvo))
1176 return false;
1177
1178 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
1179 intel_sdvo_connector,
1180 mode->clock / 10,
1181 mode->hdisplay,
1182 mode->vdisplay))
1183 return false;
1184
1185 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
1186 &input_dtd))
1187 return false;
1188
1189 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
1190 intel_sdvo->dtd_sdvo_flags = input_dtd.part2.sdvo_flags;
1191
1192 return true;
1193 }
1194
1195 static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_state *pipe_config)
1196 {
1197 unsigned dotclock = pipe_config->port_clock;
1198 struct dpll *clock = &pipe_config->dpll;
1199
1200 /*
1201 * SDVO TV has fixed PLL values depend on its clock range,
1202 * this mirrors vbios setting.
1203 */
1204 if (dotclock >= 100000 && dotclock < 140500) {
1205 clock->p1 = 2;
1206 clock->p2 = 10;
1207 clock->n = 3;
1208 clock->m1 = 16;
1209 clock->m2 = 8;
1210 } else if (dotclock >= 140500 && dotclock <= 200000) {
1211 clock->p1 = 1;
1212 clock->p2 = 10;
1213 clock->n = 6;
1214 clock->m1 = 12;
1215 clock->m2 = 8;
1216 } else {
1217 WARN(1, "SDVO TV clock out of range: %i\n", dotclock);
1218 }
1219
1220 pipe_config->clock_set = true;
1221 }
1222
1223 static int intel_sdvo_compute_config(struct intel_encoder *encoder,
1224 struct intel_crtc_state *pipe_config,
1225 struct drm_connector_state *conn_state)
1226 {
1227 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1228 struct intel_sdvo_connector_state *intel_sdvo_state =
1229 to_intel_sdvo_connector_state(conn_state);
1230 struct intel_sdvo_connector *intel_sdvo_connector =
1231 to_intel_sdvo_connector(conn_state->connector);
1232 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1233 struct drm_display_mode *mode = &pipe_config->base.mode;
1234
1235 DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n");
1236 pipe_config->pipe_bpp = 8*3;
1237 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
1238
1239 if (HAS_PCH_SPLIT(to_i915(encoder->base.dev)))
1240 pipe_config->has_pch_encoder = true;
1241
1242 /*
1243 * We need to construct preferred input timings based on our
1244 * output timings. To do that, we have to set the output
1245 * timings, even though this isn't really the right place in
1246 * the sequence to do it. Oh well.
1247 */
1248 if (IS_TV(intel_sdvo_connector)) {
1249 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
1250 return -EINVAL;
1251
1252 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
1253 intel_sdvo_connector,
1254 mode,
1255 adjusted_mode);
1256 pipe_config->sdvo_tv_clock = true;
1257 } else if (IS_LVDS(intel_sdvo_connector)) {
1258 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
1259 intel_sdvo_connector->base.panel.fixed_mode))
1260 return -EINVAL;
1261
1262 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
1263 intel_sdvo_connector,
1264 mode,
1265 adjusted_mode);
1266 }
1267
1268 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
1269 return -EINVAL;
1270
1271 /*
1272 * Make the CRTC code factor in the SDVO pixel multiplier. The
1273 * SDVO device will factor out the multiplier during mode_set.
1274 */
1275 pipe_config->pixel_multiplier =
1276 intel_sdvo_get_pixel_multiplier(adjusted_mode);
1277
1278 if (intel_sdvo_state->base.force_audio != HDMI_AUDIO_OFF_DVI)
1279 pipe_config->has_hdmi_sink = intel_sdvo->has_hdmi_monitor;
1280
1281 if (intel_sdvo_state->base.force_audio == HDMI_AUDIO_ON ||
1282 (intel_sdvo_state->base.force_audio == HDMI_AUDIO_AUTO && intel_sdvo->has_hdmi_audio))
1283 pipe_config->has_audio = true;
1284
1285 if (intel_sdvo_state->base.broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
1286 /*
1287 * See CEA-861-E - 5.1 Default Encoding Parameters
1288 *
1289 * FIXME: This bit is only valid when using TMDS encoding and 8
1290 * bit per color mode.
1291 */
1292 if (pipe_config->has_hdmi_sink &&
1293 drm_match_cea_mode(adjusted_mode) > 1)
1294 pipe_config->limited_color_range = true;
1295 } else {
1296 if (pipe_config->has_hdmi_sink &&
1297 intel_sdvo_state->base.broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED)
1298 pipe_config->limited_color_range = true;
1299 }
1300
1301 /* Clock computation needs to happen after pixel multiplier. */
1302 if (IS_TV(intel_sdvo_connector))
1303 i9xx_adjust_sdvo_tv_clock(pipe_config);
1304
1305 /* Set user selected PAR to incoming mode's member */
1306 if (intel_sdvo_connector->is_hdmi)
1307 adjusted_mode->picture_aspect_ratio = conn_state->picture_aspect_ratio;
1308
1309 if (!intel_sdvo_compute_avi_infoframe(intel_sdvo,
1310 pipe_config, conn_state)) {
1311 DRM_DEBUG_KMS("bad AVI infoframe\n");
1312 return -EINVAL;
1313 }
1314
1315 return 0;
1316 }
1317
1318 #define UPDATE_PROPERTY(input, NAME) \
1319 do { \
1320 val = input; \
1321 intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_##NAME, &val, sizeof(val)); \
1322 } while (0)
1323
1324 static void intel_sdvo_update_props(struct intel_sdvo *intel_sdvo,
1325 const struct intel_sdvo_connector_state *sdvo_state)
1326 {
1327 const struct drm_connector_state *conn_state = &sdvo_state->base.base;
1328 struct intel_sdvo_connector *intel_sdvo_conn =
1329 to_intel_sdvo_connector(conn_state->connector);
1330 u16 val;
1331
1332 if (intel_sdvo_conn->left)
1333 UPDATE_PROPERTY(sdvo_state->tv.overscan_h, OVERSCAN_H);
1334
1335 if (intel_sdvo_conn->top)
1336 UPDATE_PROPERTY(sdvo_state->tv.overscan_v, OVERSCAN_V);
1337
1338 if (intel_sdvo_conn->hpos)
1339 UPDATE_PROPERTY(sdvo_state->tv.hpos, HPOS);
1340
1341 if (intel_sdvo_conn->vpos)
1342 UPDATE_PROPERTY(sdvo_state->tv.vpos, VPOS);
1343
1344 if (intel_sdvo_conn->saturation)
1345 UPDATE_PROPERTY(conn_state->tv.saturation, SATURATION);
1346
1347 if (intel_sdvo_conn->contrast)
1348 UPDATE_PROPERTY(conn_state->tv.contrast, CONTRAST);
1349
1350 if (intel_sdvo_conn->hue)
1351 UPDATE_PROPERTY(conn_state->tv.hue, HUE);
1352
1353 if (intel_sdvo_conn->brightness)
1354 UPDATE_PROPERTY(conn_state->tv.brightness, BRIGHTNESS);
1355
1356 if (intel_sdvo_conn->sharpness)
1357 UPDATE_PROPERTY(sdvo_state->tv.sharpness, SHARPNESS);
1358
1359 if (intel_sdvo_conn->flicker_filter)
1360 UPDATE_PROPERTY(sdvo_state->tv.flicker_filter, FLICKER_FILTER);
1361
1362 if (intel_sdvo_conn->flicker_filter_2d)
1363 UPDATE_PROPERTY(sdvo_state->tv.flicker_filter_2d, FLICKER_FILTER_2D);
1364
1365 if (intel_sdvo_conn->flicker_filter_adaptive)
1366 UPDATE_PROPERTY(sdvo_state->tv.flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
1367
1368 if (intel_sdvo_conn->tv_chroma_filter)
1369 UPDATE_PROPERTY(sdvo_state->tv.chroma_filter, TV_CHROMA_FILTER);
1370
1371 if (intel_sdvo_conn->tv_luma_filter)
1372 UPDATE_PROPERTY(sdvo_state->tv.luma_filter, TV_LUMA_FILTER);
1373
1374 if (intel_sdvo_conn->dot_crawl)
1375 UPDATE_PROPERTY(sdvo_state->tv.dot_crawl, DOT_CRAWL);
1376
1377 #undef UPDATE_PROPERTY
1378 }
1379
1380 static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder,
1381 const struct intel_crtc_state *crtc_state,
1382 const struct drm_connector_state *conn_state)
1383 {
1384 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
1385 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1386 const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
1387 const struct intel_sdvo_connector_state *sdvo_state =
1388 to_intel_sdvo_connector_state(conn_state);
1389 const struct intel_sdvo_connector *intel_sdvo_connector =
1390 to_intel_sdvo_connector(conn_state->connector);
1391 const struct drm_display_mode *mode = &crtc_state->base.mode;
1392 struct intel_sdvo *intel_sdvo = to_sdvo(intel_encoder);
1393 u32 sdvox;
1394 struct intel_sdvo_in_out_map in_out;
1395 struct intel_sdvo_dtd input_dtd, output_dtd;
1396 int rate;
1397
1398 intel_sdvo_update_props(intel_sdvo, sdvo_state);
1399
1400 /*
1401 * First, set the input mapping for the first input to our controlled
1402 * output. This is only correct if we're a single-input device, in
1403 * which case the first input is the output from the appropriate SDVO
1404 * channel on the motherboard. In a two-input device, the first input
1405 * will be SDVOB and the second SDVOC.
1406 */
1407 in_out.in0 = intel_sdvo->attached_output;
1408 in_out.in1 = 0;
1409
1410 intel_sdvo_set_value(intel_sdvo,
1411 SDVO_CMD_SET_IN_OUT_MAP,
1412 &in_out, sizeof(in_out));
1413
1414 /* Set the output timings to the screen */
1415 if (!intel_sdvo_set_target_output(intel_sdvo,
1416 intel_sdvo->attached_output))
1417 return;
1418
1419 /* lvds has a special fixed output timing. */
1420 if (IS_LVDS(intel_sdvo_connector))
1421 intel_sdvo_get_dtd_from_mode(&output_dtd,
1422 intel_sdvo_connector->base.panel.fixed_mode);
1423 else
1424 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
1425 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1426 DRM_INFO("Setting output timings on %s failed\n",
1427 SDVO_NAME(intel_sdvo));
1428
1429 /* Set the input timing to the screen. Assume always input 0. */
1430 if (!intel_sdvo_set_target_input(intel_sdvo))
1431 return;
1432
1433 if (crtc_state->has_hdmi_sink) {
1434 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
1435 intel_sdvo_set_colorimetry(intel_sdvo,
1436 SDVO_COLORIMETRY_RGB256);
1437 intel_sdvo_set_avi_infoframe(intel_sdvo, crtc_state);
1438 } else
1439 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI);
1440
1441 if (IS_TV(intel_sdvo_connector) &&
1442 !intel_sdvo_set_tv_format(intel_sdvo, conn_state))
1443 return;
1444
1445 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
1446
1447 if (IS_TV(intel_sdvo_connector) || IS_LVDS(intel_sdvo_connector))
1448 input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags;
1449 if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd))
1450 DRM_INFO("Setting input timings on %s failed\n",
1451 SDVO_NAME(intel_sdvo));
1452
1453 switch (crtc_state->pixel_multiplier) {
1454 default:
1455 WARN(1, "unknown pixel multiplier specified\n");
1456 /* fall through */
1457 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
1458 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
1459 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
1460 }
1461 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
1462 return;
1463
1464 /* Set the SDVO control regs. */
1465 if (INTEL_GEN(dev_priv) >= 4) {
1466 /* The real mode polarity is set by the SDVO commands, using
1467 * struct intel_sdvo_dtd. */
1468 sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
1469 if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range)
1470 sdvox |= HDMI_COLOR_RANGE_16_235;
1471 if (INTEL_GEN(dev_priv) < 5)
1472 sdvox |= SDVO_BORDER_ENABLE;
1473 } else {
1474 sdvox = I915_READ(intel_sdvo->sdvo_reg);
1475 if (intel_sdvo->port == PORT_B)
1476 sdvox &= SDVOB_PRESERVE_MASK;
1477 else
1478 sdvox &= SDVOC_PRESERVE_MASK;
1479 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1480 }
1481
1482 if (HAS_PCH_CPT(dev_priv))
1483 sdvox |= SDVO_PIPE_SEL_CPT(crtc->pipe);
1484 else
1485 sdvox |= SDVO_PIPE_SEL(crtc->pipe);
1486
1487 if (crtc_state->has_audio) {
1488 WARN_ON_ONCE(INTEL_GEN(dev_priv) < 4);
1489 sdvox |= SDVO_AUDIO_ENABLE;
1490 }
1491
1492 if (INTEL_GEN(dev_priv) >= 4) {
1493 /* done in crtc_mode_set as the dpll_md reg must be written early */
1494 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
1495 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
1496 /* done in crtc_mode_set as it lives inside the dpll register */
1497 } else {
1498 sdvox |= (crtc_state->pixel_multiplier - 1)
1499 << SDVO_PORT_MULTIPLY_SHIFT;
1500 }
1501
1502 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
1503 INTEL_GEN(dev_priv) < 5)
1504 sdvox |= SDVO_STALL_SELECT;
1505 intel_sdvo_write_sdvox(intel_sdvo, sdvox);
1506 }
1507
1508 static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector)
1509 {
1510 struct intel_sdvo_connector *intel_sdvo_connector =
1511 to_intel_sdvo_connector(&connector->base);
1512 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(&connector->base);
1513 u16 active_outputs = 0;
1514
1515 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
1516
1517 return active_outputs & intel_sdvo_connector->output_flag;
1518 }
1519
1520 bool intel_sdvo_port_enabled(struct drm_i915_private *dev_priv,
1521 i915_reg_t sdvo_reg, enum pipe *pipe)
1522 {
1523 u32 val;
1524
1525 val = I915_READ(sdvo_reg);
1526
1527 /* asserts want to know the pipe even if the port is disabled */
1528 if (HAS_PCH_CPT(dev_priv))
1529 *pipe = (val & SDVO_PIPE_SEL_MASK_CPT) >> SDVO_PIPE_SEL_SHIFT_CPT;
1530 else if (IS_CHERRYVIEW(dev_priv))
1531 *pipe = (val & SDVO_PIPE_SEL_MASK_CHV) >> SDVO_PIPE_SEL_SHIFT_CHV;
1532 else
1533 *pipe = (val & SDVO_PIPE_SEL_MASK) >> SDVO_PIPE_SEL_SHIFT;
1534
1535 return val & SDVO_ENABLE;
1536 }
1537
1538 static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder,
1539 enum pipe *pipe)
1540 {
1541 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1542 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1543 u16 active_outputs = 0;
1544 bool ret;
1545
1546 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
1547
1548 ret = intel_sdvo_port_enabled(dev_priv, intel_sdvo->sdvo_reg, pipe);
1549
1550 return ret || active_outputs;
1551 }
1552
1553 static void intel_sdvo_get_config(struct intel_encoder *encoder,
1554 struct intel_crtc_state *pipe_config)
1555 {
1556 struct drm_device *dev = encoder->base.dev;
1557 struct drm_i915_private *dev_priv = to_i915(dev);
1558 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1559 struct intel_sdvo_dtd dtd;
1560 int encoder_pixel_multiplier = 0;
1561 int dotclock;
1562 u32 flags = 0, sdvox;
1563 u8 val;
1564 bool ret;
1565
1566 pipe_config->output_types |= BIT(INTEL_OUTPUT_SDVO);
1567
1568 sdvox = I915_READ(intel_sdvo->sdvo_reg);
1569
1570 ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd);
1571 if (!ret) {
1572 /*
1573 * Some sdvo encoders are not spec compliant and don't
1574 * implement the mandatory get_timings function.
1575 */
1576 DRM_DEBUG_DRIVER("failed to retrieve SDVO DTD\n");
1577 pipe_config->quirks |= PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS;
1578 } else {
1579 if (dtd.part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
1580 flags |= DRM_MODE_FLAG_PHSYNC;
1581 else
1582 flags |= DRM_MODE_FLAG_NHSYNC;
1583
1584 if (dtd.part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
1585 flags |= DRM_MODE_FLAG_PVSYNC;
1586 else
1587 flags |= DRM_MODE_FLAG_NVSYNC;
1588 }
1589
1590 pipe_config->base.adjusted_mode.flags |= flags;
1591
1592 /*
1593 * pixel multiplier readout is tricky: Only on i915g/gm it is stored in
1594 * the sdvo port register, on all other platforms it is part of the dpll
1595 * state. Since the general pipe state readout happens before the
1596 * encoder->get_config we so already have a valid pixel multplier on all
1597 * other platfroms.
1598 */
1599 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
1600 pipe_config->pixel_multiplier =
1601 ((sdvox & SDVO_PORT_MULTIPLY_MASK)
1602 >> SDVO_PORT_MULTIPLY_SHIFT) + 1;
1603 }
1604
1605 dotclock = pipe_config->port_clock;
1606
1607 if (pipe_config->pixel_multiplier)
1608 dotclock /= pipe_config->pixel_multiplier;
1609
1610 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1611
1612 /* Cross check the port pixel multiplier with the sdvo encoder state. */
1613 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT,
1614 &val, 1)) {
1615 switch (val) {
1616 case SDVO_CLOCK_RATE_MULT_1X:
1617 encoder_pixel_multiplier = 1;
1618 break;
1619 case SDVO_CLOCK_RATE_MULT_2X:
1620 encoder_pixel_multiplier = 2;
1621 break;
1622 case SDVO_CLOCK_RATE_MULT_4X:
1623 encoder_pixel_multiplier = 4;
1624 break;
1625 }
1626 }
1627
1628 WARN(encoder_pixel_multiplier != pipe_config->pixel_multiplier,
1629 "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n",
1630 pipe_config->pixel_multiplier, encoder_pixel_multiplier);
1631
1632 if (sdvox & HDMI_COLOR_RANGE_16_235)
1633 pipe_config->limited_color_range = true;
1634
1635 if (sdvox & SDVO_AUDIO_ENABLE)
1636 pipe_config->has_audio = true;
1637
1638 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ENCODE,
1639 &val, 1)) {
1640 if (val == SDVO_ENCODE_HDMI)
1641 pipe_config->has_hdmi_sink = true;
1642 }
1643
1644 intel_sdvo_get_avi_infoframe(intel_sdvo, pipe_config);
1645 }
1646
1647 static void intel_disable_sdvo(struct intel_encoder *encoder,
1648 const struct intel_crtc_state *old_crtc_state,
1649 const struct drm_connector_state *conn_state)
1650 {
1651 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1652 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1653 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
1654 u32 temp;
1655
1656 intel_sdvo_set_active_outputs(intel_sdvo, 0);
1657 if (0)
1658 intel_sdvo_set_encoder_power_state(intel_sdvo,
1659 DRM_MODE_DPMS_OFF);
1660
1661 temp = I915_READ(intel_sdvo->sdvo_reg);
1662
1663 temp &= ~SDVO_ENABLE;
1664 intel_sdvo_write_sdvox(intel_sdvo, temp);
1665
1666 /*
1667 * HW workaround for IBX, we need to move the port
1668 * to transcoder A after disabling it to allow the
1669 * matching DP port to be enabled on transcoder A.
1670 */
1671 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {
1672 /*
1673 * We get CPU/PCH FIFO underruns on the other pipe when
1674 * doing the workaround. Sweep them under the rug.
1675 */
1676 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1677 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1678
1679 temp &= ~SDVO_PIPE_SEL_MASK;
1680 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A);
1681 intel_sdvo_write_sdvox(intel_sdvo, temp);
1682
1683 temp &= ~SDVO_ENABLE;
1684 intel_sdvo_write_sdvox(intel_sdvo, temp);
1685
1686 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
1687 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1688 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1689 }
1690 }
1691
1692 static void pch_disable_sdvo(struct intel_encoder *encoder,
1693 const struct intel_crtc_state *old_crtc_state,
1694 const struct drm_connector_state *old_conn_state)
1695 {
1696 }
1697
1698 static void pch_post_disable_sdvo(struct intel_encoder *encoder,
1699 const struct intel_crtc_state *old_crtc_state,
1700 const struct drm_connector_state *old_conn_state)
1701 {
1702 intel_disable_sdvo(encoder, old_crtc_state, old_conn_state);
1703 }
1704
1705 static void intel_enable_sdvo(struct intel_encoder *encoder,
1706 const struct intel_crtc_state *pipe_config,
1707 const struct drm_connector_state *conn_state)
1708 {
1709 struct drm_device *dev = encoder->base.dev;
1710 struct drm_i915_private *dev_priv = to_i915(dev);
1711 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1712 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
1713 u32 temp;
1714 bool input1, input2;
1715 int i;
1716 bool success;
1717
1718 temp = I915_READ(intel_sdvo->sdvo_reg);
1719 temp |= SDVO_ENABLE;
1720 intel_sdvo_write_sdvox(intel_sdvo, temp);
1721
1722 for (i = 0; i < 2; i++)
1723 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
1724
1725 success = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
1726 /*
1727 * Warn if the device reported failure to sync.
1728 *
1729 * A lot of SDVO devices fail to notify of sync, but it's
1730 * a given it the status is a success, we succeeded.
1731 */
1732 if (success && !input1) {
1733 DRM_DEBUG_KMS("First %s output reported failure to "
1734 "sync\n", SDVO_NAME(intel_sdvo));
1735 }
1736
1737 if (0)
1738 intel_sdvo_set_encoder_power_state(intel_sdvo,
1739 DRM_MODE_DPMS_ON);
1740 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
1741 }
1742
1743 static enum drm_mode_status
1744 intel_sdvo_mode_valid(struct drm_connector *connector,
1745 struct drm_display_mode *mode)
1746 {
1747 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1748 struct intel_sdvo_connector *intel_sdvo_connector =
1749 to_intel_sdvo_connector(connector);
1750 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
1751
1752 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1753 return MODE_NO_DBLESCAN;
1754
1755 if (intel_sdvo->pixel_clock_min > mode->clock)
1756 return MODE_CLOCK_LOW;
1757
1758 if (intel_sdvo->pixel_clock_max < mode->clock)
1759 return MODE_CLOCK_HIGH;
1760
1761 if (mode->clock > max_dotclk)
1762 return MODE_CLOCK_HIGH;
1763
1764 if (IS_LVDS(intel_sdvo_connector)) {
1765 const struct drm_display_mode *fixed_mode =
1766 intel_sdvo_connector->base.panel.fixed_mode;
1767
1768 if (mode->hdisplay > fixed_mode->hdisplay)
1769 return MODE_PANEL;
1770
1771 if (mode->vdisplay > fixed_mode->vdisplay)
1772 return MODE_PANEL;
1773 }
1774
1775 return MODE_OK;
1776 }
1777
1778 static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
1779 {
1780 BUILD_BUG_ON(sizeof(*caps) != 8);
1781 if (!intel_sdvo_get_value(intel_sdvo,
1782 SDVO_CMD_GET_DEVICE_CAPS,
1783 caps, sizeof(*caps)))
1784 return false;
1785
1786 DRM_DEBUG_KMS("SDVO capabilities:\n"
1787 " vendor_id: %d\n"
1788 " device_id: %d\n"
1789 " device_rev_id: %d\n"
1790 " sdvo_version_major: %d\n"
1791 " sdvo_version_minor: %d\n"
1792 " sdvo_inputs_mask: %d\n"
1793 " smooth_scaling: %d\n"
1794 " sharp_scaling: %d\n"
1795 " up_scaling: %d\n"
1796 " down_scaling: %d\n"
1797 " stall_support: %d\n"
1798 " output_flags: %d\n",
1799 caps->vendor_id,
1800 caps->device_id,
1801 caps->device_rev_id,
1802 caps->sdvo_version_major,
1803 caps->sdvo_version_minor,
1804 caps->sdvo_inputs_mask,
1805 caps->smooth_scaling,
1806 caps->sharp_scaling,
1807 caps->up_scaling,
1808 caps->down_scaling,
1809 caps->stall_support,
1810 caps->output_flags);
1811
1812 return true;
1813 }
1814
1815 static u16 intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo)
1816 {
1817 struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev);
1818 u16 hotplug;
1819
1820 if (!I915_HAS_HOTPLUG(dev_priv))
1821 return 0;
1822
1823 /*
1824 * HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise
1825 * on the line.
1826 */
1827 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
1828 return 0;
1829
1830 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
1831 &hotplug, sizeof(hotplug)))
1832 return 0;
1833
1834 return hotplug;
1835 }
1836
1837 static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder)
1838 {
1839 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1840
1841 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG,
1842 &intel_sdvo->hotplug_active, 2);
1843 }
1844
1845 static bool intel_sdvo_hotplug(struct intel_encoder *encoder,
1846 struct intel_connector *connector)
1847 {
1848 intel_sdvo_enable_hotplug(encoder);
1849
1850 return intel_encoder_hotplug(encoder, connector);
1851 }
1852
1853 static bool
1854 intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
1855 {
1856 /* Is there more than one type of output? */
1857 return hweight16(intel_sdvo->caps.output_flags) > 1;
1858 }
1859
1860 static struct edid *
1861 intel_sdvo_get_edid(struct drm_connector *connector)
1862 {
1863 struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
1864 return drm_get_edid(connector, &sdvo->ddc);
1865 }
1866
1867 /* Mac mini hack -- use the same DDC as the analog connector */
1868 static struct edid *
1869 intel_sdvo_get_analog_edid(struct drm_connector *connector)
1870 {
1871 struct drm_i915_private *dev_priv = to_i915(connector->dev);
1872
1873 return drm_get_edid(connector,
1874 intel_gmbus_get_adapter(dev_priv,
1875 dev_priv->vbt.crt_ddc_pin));
1876 }
1877
1878 static enum drm_connector_status
1879 intel_sdvo_tmds_sink_detect(struct drm_connector *connector)
1880 {
1881 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1882 struct intel_sdvo_connector *intel_sdvo_connector =
1883 to_intel_sdvo_connector(connector);
1884 enum drm_connector_status status;
1885 struct edid *edid;
1886
1887 edid = intel_sdvo_get_edid(connector);
1888
1889 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) {
1890 u8 ddc, saved_ddc = intel_sdvo->ddc_bus;
1891
1892 /*
1893 * Don't use the 1 as the argument of DDC bus switch to get
1894 * the EDID. It is used for SDVO SPD ROM.
1895 */
1896 for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) {
1897 intel_sdvo->ddc_bus = ddc;
1898 edid = intel_sdvo_get_edid(connector);
1899 if (edid)
1900 break;
1901 }
1902 /*
1903 * If we found the EDID on the other bus,
1904 * assume that is the correct DDC bus.
1905 */
1906 if (edid == NULL)
1907 intel_sdvo->ddc_bus = saved_ddc;
1908 }
1909
1910 /*
1911 * When there is no edid and no monitor is connected with VGA
1912 * port, try to use the CRT ddc to read the EDID for DVI-connector.
1913 */
1914 if (edid == NULL)
1915 edid = intel_sdvo_get_analog_edid(connector);
1916
1917 status = connector_status_unknown;
1918 if (edid != NULL) {
1919 /* DDC bus is shared, match EDID to connector type */
1920 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
1921 status = connector_status_connected;
1922 if (intel_sdvo_connector->is_hdmi) {
1923 intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid);
1924 intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid);
1925 }
1926 } else
1927 status = connector_status_disconnected;
1928 kfree(edid);
1929 }
1930
1931 return status;
1932 }
1933
1934 static bool
1935 intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo,
1936 struct edid *edid)
1937 {
1938 bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
1939 bool connector_is_digital = !!IS_DIGITAL(sdvo);
1940
1941 DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n",
1942 connector_is_digital, monitor_is_digital);
1943 return connector_is_digital == monitor_is_digital;
1944 }
1945
1946 static enum drm_connector_status
1947 intel_sdvo_detect(struct drm_connector *connector, bool force)
1948 {
1949 u16 response;
1950 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1951 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
1952 enum drm_connector_status ret;
1953
1954 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1955 connector->base.id, connector->name);
1956
1957 if (!intel_sdvo_get_value(intel_sdvo,
1958 SDVO_CMD_GET_ATTACHED_DISPLAYS,
1959 &response, 2))
1960 return connector_status_unknown;
1961
1962 DRM_DEBUG_KMS("SDVO response %d %d [%x]\n",
1963 response & 0xff, response >> 8,
1964 intel_sdvo_connector->output_flag);
1965
1966 if (response == 0)
1967 return connector_status_disconnected;
1968
1969 intel_sdvo->attached_output = response;
1970
1971 intel_sdvo->has_hdmi_monitor = false;
1972 intel_sdvo->has_hdmi_audio = false;
1973
1974 if ((intel_sdvo_connector->output_flag & response) == 0)
1975 ret = connector_status_disconnected;
1976 else if (IS_TMDS(intel_sdvo_connector))
1977 ret = intel_sdvo_tmds_sink_detect(connector);
1978 else {
1979 struct edid *edid;
1980
1981 /* if we have an edid check it matches the connection */
1982 edid = intel_sdvo_get_edid(connector);
1983 if (edid == NULL)
1984 edid = intel_sdvo_get_analog_edid(connector);
1985 if (edid != NULL) {
1986 if (intel_sdvo_connector_matches_edid(intel_sdvo_connector,
1987 edid))
1988 ret = connector_status_connected;
1989 else
1990 ret = connector_status_disconnected;
1991
1992 kfree(edid);
1993 } else
1994 ret = connector_status_connected;
1995 }
1996
1997 return ret;
1998 }
1999
2000 static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
2001 {
2002 struct edid *edid;
2003
2004 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
2005 connector->base.id, connector->name);
2006
2007 /* set the bus switch and get the modes */
2008 edid = intel_sdvo_get_edid(connector);
2009
2010 /*
2011 * Mac mini hack. On this device, the DVI-I connector shares one DDC
2012 * link between analog and digital outputs. So, if the regular SDVO
2013 * DDC fails, check to see if the analog output is disconnected, in
2014 * which case we'll look there for the digital DDC data.
2015 */
2016 if (edid == NULL)
2017 edid = intel_sdvo_get_analog_edid(connector);
2018
2019 if (edid != NULL) {
2020 if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector),
2021 edid)) {
2022 drm_connector_update_edid_property(connector, edid);
2023 drm_add_edid_modes(connector, edid);
2024 }
2025
2026 kfree(edid);
2027 }
2028 }
2029
2030 /*
2031 * Set of SDVO TV modes.
2032 * Note! This is in reply order (see loop in get_tv_modes).
2033 * XXX: all 60Hz refresh?
2034 */
2035 static const struct drm_display_mode sdvo_tv_modes[] = {
2036 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
2037 416, 0, 200, 201, 232, 233, 0,
2038 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2039 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
2040 416, 0, 240, 241, 272, 273, 0,
2041 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2042 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
2043 496, 0, 300, 301, 332, 333, 0,
2044 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2045 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
2046 736, 0, 350, 351, 382, 383, 0,
2047 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2048 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
2049 736, 0, 400, 401, 432, 433, 0,
2050 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2051 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
2052 736, 0, 480, 481, 512, 513, 0,
2053 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2054 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
2055 800, 0, 480, 481, 512, 513, 0,
2056 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2057 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
2058 800, 0, 576, 577, 608, 609, 0,
2059 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2060 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
2061 816, 0, 350, 351, 382, 383, 0,
2062 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2063 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
2064 816, 0, 400, 401, 432, 433, 0,
2065 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2066 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
2067 816, 0, 480, 481, 512, 513, 0,
2068 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2069 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
2070 816, 0, 540, 541, 572, 573, 0,
2071 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2072 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
2073 816, 0, 576, 577, 608, 609, 0,
2074 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2075 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
2076 864, 0, 576, 577, 608, 609, 0,
2077 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2078 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
2079 896, 0, 600, 601, 632, 633, 0,
2080 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2081 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
2082 928, 0, 624, 625, 656, 657, 0,
2083 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2084 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
2085 1016, 0, 766, 767, 798, 799, 0,
2086 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2087 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
2088 1120, 0, 768, 769, 800, 801, 0,
2089 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2090 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
2091 1376, 0, 1024, 1025, 1056, 1057, 0,
2092 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2093 };
2094
2095 static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
2096 {
2097 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
2098 const struct drm_connector_state *conn_state = connector->state;
2099 struct intel_sdvo_sdtv_resolution_request tv_res;
2100 u32 reply = 0, format_map = 0;
2101 int i;
2102
2103 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
2104 connector->base.id, connector->name);
2105
2106 /*
2107 * Read the list of supported input resolutions for the selected TV
2108 * format.
2109 */
2110 format_map = 1 << conn_state->tv.mode;
2111 memcpy(&tv_res, &format_map,
2112 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
2113
2114 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output))
2115 return;
2116
2117 BUILD_BUG_ON(sizeof(tv_res) != 3);
2118 if (!intel_sdvo_write_cmd(intel_sdvo,
2119 SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
2120 &tv_res, sizeof(tv_res)))
2121 return;
2122 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
2123 return;
2124
2125 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
2126 if (reply & (1 << i)) {
2127 struct drm_display_mode *nmode;
2128 nmode = drm_mode_duplicate(connector->dev,
2129 &sdvo_tv_modes[i]);
2130 if (nmode)
2131 drm_mode_probed_add(connector, nmode);
2132 }
2133 }
2134
2135 static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
2136 {
2137 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
2138 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2139 struct drm_display_mode *newmode;
2140
2141 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
2142 connector->base.id, connector->name);
2143
2144 /*
2145 * Fetch modes from VBT. For SDVO prefer the VBT mode since some
2146 * SDVO->LVDS transcoders can't cope with the EDID mode.
2147 */
2148 if (dev_priv->vbt.sdvo_lvds_vbt_mode != NULL) {
2149 newmode = drm_mode_duplicate(connector->dev,
2150 dev_priv->vbt.sdvo_lvds_vbt_mode);
2151 if (newmode != NULL) {
2152 /* Guarantee the mode is preferred */
2153 newmode->type = (DRM_MODE_TYPE_PREFERRED |
2154 DRM_MODE_TYPE_DRIVER);
2155 drm_mode_probed_add(connector, newmode);
2156 }
2157 }
2158
2159 /*
2160 * Attempt to get the mode list from DDC.
2161 * Assume that the preferred modes are
2162 * arranged in priority order.
2163 */
2164 intel_ddc_get_modes(connector, &intel_sdvo->ddc);
2165 }
2166
2167 static int intel_sdvo_get_modes(struct drm_connector *connector)
2168 {
2169 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
2170
2171 if (IS_TV(intel_sdvo_connector))
2172 intel_sdvo_get_tv_modes(connector);
2173 else if (IS_LVDS(intel_sdvo_connector))
2174 intel_sdvo_get_lvds_modes(connector);
2175 else
2176 intel_sdvo_get_ddc_modes(connector);
2177
2178 return !list_empty(&connector->probed_modes);
2179 }
2180
2181 static int
2182 intel_sdvo_connector_atomic_get_property(struct drm_connector *connector,
2183 const struct drm_connector_state *state,
2184 struct drm_property *property,
2185 u64 *val)
2186 {
2187 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
2188 const struct intel_sdvo_connector_state *sdvo_state = to_intel_sdvo_connector_state((void *)state);
2189
2190 if (property == intel_sdvo_connector->tv_format) {
2191 int i;
2192
2193 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
2194 if (state->tv.mode == intel_sdvo_connector->tv_format_supported[i]) {
2195 *val = i;
2196
2197 return 0;
2198 }
2199
2200 WARN_ON(1);
2201 *val = 0;
2202 } else if (property == intel_sdvo_connector->top ||
2203 property == intel_sdvo_connector->bottom)
2204 *val = intel_sdvo_connector->max_vscan - sdvo_state->tv.overscan_v;
2205 else if (property == intel_sdvo_connector->left ||
2206 property == intel_sdvo_connector->right)
2207 *val = intel_sdvo_connector->max_hscan - sdvo_state->tv.overscan_h;
2208 else if (property == intel_sdvo_connector->hpos)
2209 *val = sdvo_state->tv.hpos;
2210 else if (property == intel_sdvo_connector->vpos)
2211 *val = sdvo_state->tv.vpos;
2212 else if (property == intel_sdvo_connector->saturation)
2213 *val = state->tv.saturation;
2214 else if (property == intel_sdvo_connector->contrast)
2215 *val = state->tv.contrast;
2216 else if (property == intel_sdvo_connector->hue)
2217 *val = state->tv.hue;
2218 else if (property == intel_sdvo_connector->brightness)
2219 *val = state->tv.brightness;
2220 else if (property == intel_sdvo_connector->sharpness)
2221 *val = sdvo_state->tv.sharpness;
2222 else if (property == intel_sdvo_connector->flicker_filter)
2223 *val = sdvo_state->tv.flicker_filter;
2224 else if (property == intel_sdvo_connector->flicker_filter_2d)
2225 *val = sdvo_state->tv.flicker_filter_2d;
2226 else if (property == intel_sdvo_connector->flicker_filter_adaptive)
2227 *val = sdvo_state->tv.flicker_filter_adaptive;
2228 else if (property == intel_sdvo_connector->tv_chroma_filter)
2229 *val = sdvo_state->tv.chroma_filter;
2230 else if (property == intel_sdvo_connector->tv_luma_filter)
2231 *val = sdvo_state->tv.luma_filter;
2232 else if (property == intel_sdvo_connector->dot_crawl)
2233 *val = sdvo_state->tv.dot_crawl;
2234 else
2235 return intel_digital_connector_atomic_get_property(connector, state, property, val);
2236
2237 return 0;
2238 }
2239
2240 static int
2241 intel_sdvo_connector_atomic_set_property(struct drm_connector *connector,
2242 struct drm_connector_state *state,
2243 struct drm_property *property,
2244 u64 val)
2245 {
2246 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
2247 struct intel_sdvo_connector_state *sdvo_state = to_intel_sdvo_connector_state(state);
2248
2249 if (property == intel_sdvo_connector->tv_format) {
2250 state->tv.mode = intel_sdvo_connector->tv_format_supported[val];
2251
2252 if (state->crtc) {
2253 struct drm_crtc_state *crtc_state =
2254 drm_atomic_get_new_crtc_state(state->state, state->crtc);
2255
2256 crtc_state->connectors_changed = true;
2257 }
2258 } else if (property == intel_sdvo_connector->top ||
2259 property == intel_sdvo_connector->bottom)
2260 /* Cannot set these independent from each other */
2261 sdvo_state->tv.overscan_v = intel_sdvo_connector->max_vscan - val;
2262 else if (property == intel_sdvo_connector->left ||
2263 property == intel_sdvo_connector->right)
2264 /* Cannot set these independent from each other */
2265 sdvo_state->tv.overscan_h = intel_sdvo_connector->max_hscan - val;
2266 else if (property == intel_sdvo_connector->hpos)
2267 sdvo_state->tv.hpos = val;
2268 else if (property == intel_sdvo_connector->vpos)
2269 sdvo_state->tv.vpos = val;
2270 else if (property == intel_sdvo_connector->saturation)
2271 state->tv.saturation = val;
2272 else if (property == intel_sdvo_connector->contrast)
2273 state->tv.contrast = val;
2274 else if (property == intel_sdvo_connector->hue)
2275 state->tv.hue = val;
2276 else if (property == intel_sdvo_connector->brightness)
2277 state->tv.brightness = val;
2278 else if (property == intel_sdvo_connector->sharpness)
2279 sdvo_state->tv.sharpness = val;
2280 else if (property == intel_sdvo_connector->flicker_filter)
2281 sdvo_state->tv.flicker_filter = val;
2282 else if (property == intel_sdvo_connector->flicker_filter_2d)
2283 sdvo_state->tv.flicker_filter_2d = val;
2284 else if (property == intel_sdvo_connector->flicker_filter_adaptive)
2285 sdvo_state->tv.flicker_filter_adaptive = val;
2286 else if (property == intel_sdvo_connector->tv_chroma_filter)
2287 sdvo_state->tv.chroma_filter = val;
2288 else if (property == intel_sdvo_connector->tv_luma_filter)
2289 sdvo_state->tv.luma_filter = val;
2290 else if (property == intel_sdvo_connector->dot_crawl)
2291 sdvo_state->tv.dot_crawl = val;
2292 else
2293 return intel_digital_connector_atomic_set_property(connector, state, property, val);
2294
2295 return 0;
2296 }
2297
2298 static int
2299 intel_sdvo_connector_register(struct drm_connector *connector)
2300 {
2301 struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
2302 int ret;
2303
2304 ret = intel_connector_register(connector);
2305 if (ret)
2306 return ret;
2307
2308 return sysfs_create_link(&connector->kdev->kobj,
2309 &sdvo->ddc.dev.kobj,
2310 sdvo->ddc.dev.kobj.name);
2311 }
2312
2313 static void
2314 intel_sdvo_connector_unregister(struct drm_connector *connector)
2315 {
2316 struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
2317
2318 sysfs_remove_link(&connector->kdev->kobj,
2319 sdvo->ddc.dev.kobj.name);
2320 intel_connector_unregister(connector);
2321 }
2322
2323 static struct drm_connector_state *
2324 intel_sdvo_connector_duplicate_state(struct drm_connector *connector)
2325 {
2326 struct intel_sdvo_connector_state *state;
2327
2328 state = kmemdup(connector->state, sizeof(*state), GFP_KERNEL);
2329 if (!state)
2330 return NULL;
2331
2332 __drm_atomic_helper_connector_duplicate_state(connector, &state->base.base);
2333 return &state->base.base;
2334 }
2335
2336 static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
2337 .detect = intel_sdvo_detect,
2338 .fill_modes = drm_helper_probe_single_connector_modes,
2339 .atomic_get_property = intel_sdvo_connector_atomic_get_property,
2340 .atomic_set_property = intel_sdvo_connector_atomic_set_property,
2341 .late_register = intel_sdvo_connector_register,
2342 .early_unregister = intel_sdvo_connector_unregister,
2343 .destroy = intel_connector_destroy,
2344 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2345 .atomic_duplicate_state = intel_sdvo_connector_duplicate_state,
2346 };
2347
2348 static int intel_sdvo_atomic_check(struct drm_connector *conn,
2349 struct drm_connector_state *new_conn_state)
2350 {
2351 struct drm_atomic_state *state = new_conn_state->state;
2352 struct drm_connector_state *old_conn_state =
2353 drm_atomic_get_old_connector_state(state, conn);
2354 struct intel_sdvo_connector_state *old_state =
2355 to_intel_sdvo_connector_state(old_conn_state);
2356 struct intel_sdvo_connector_state *new_state =
2357 to_intel_sdvo_connector_state(new_conn_state);
2358
2359 if (new_conn_state->crtc &&
2360 (memcmp(&old_state->tv, &new_state->tv, sizeof(old_state->tv)) ||
2361 memcmp(&old_conn_state->tv, &new_conn_state->tv, sizeof(old_conn_state->tv)))) {
2362 struct drm_crtc_state *crtc_state =
2363 drm_atomic_get_new_crtc_state(new_conn_state->state,
2364 new_conn_state->crtc);
2365
2366 crtc_state->connectors_changed = true;
2367 }
2368
2369 return intel_digital_connector_atomic_check(conn, new_conn_state);
2370 }
2371
2372 static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
2373 .get_modes = intel_sdvo_get_modes,
2374 .mode_valid = intel_sdvo_mode_valid,
2375 .atomic_check = intel_sdvo_atomic_check,
2376 };
2377
2378 static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
2379 {
2380 struct intel_sdvo *intel_sdvo = to_sdvo(to_intel_encoder(encoder));
2381
2382 i2c_del_adapter(&intel_sdvo->ddc);
2383 intel_encoder_destroy(encoder);
2384 }
2385
2386 static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
2387 .destroy = intel_sdvo_enc_destroy,
2388 };
2389
2390 static void
2391 intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
2392 {
2393 u16 mask = 0;
2394 unsigned int num_bits;
2395
2396 /*
2397 * Make a mask of outputs less than or equal to our own priority in the
2398 * list.
2399 */
2400 switch (sdvo->controlled_output) {
2401 case SDVO_OUTPUT_LVDS1:
2402 mask |= SDVO_OUTPUT_LVDS1;
2403 /* fall through */
2404 case SDVO_OUTPUT_LVDS0:
2405 mask |= SDVO_OUTPUT_LVDS0;
2406 /* fall through */
2407 case SDVO_OUTPUT_TMDS1:
2408 mask |= SDVO_OUTPUT_TMDS1;
2409 /* fall through */
2410 case SDVO_OUTPUT_TMDS0:
2411 mask |= SDVO_OUTPUT_TMDS0;
2412 /* fall through */
2413 case SDVO_OUTPUT_RGB1:
2414 mask |= SDVO_OUTPUT_RGB1;
2415 /* fall through */
2416 case SDVO_OUTPUT_RGB0:
2417 mask |= SDVO_OUTPUT_RGB0;
2418 break;
2419 }
2420
2421 /* Count bits to find what number we are in the priority list. */
2422 mask &= sdvo->caps.output_flags;
2423 num_bits = hweight16(mask);
2424 /* If more than 3 outputs, default to DDC bus 3 for now. */
2425 if (num_bits > 3)
2426 num_bits = 3;
2427
2428 /* Corresponds to SDVO_CONTROL_BUS_DDCx */
2429 sdvo->ddc_bus = 1 << num_bits;
2430 }
2431
2432 /*
2433 * Choose the appropriate DDC bus for control bus switch command for this
2434 * SDVO output based on the controlled output.
2435 *
2436 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
2437 * outputs, then LVDS outputs.
2438 */
2439 static void
2440 intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
2441 struct intel_sdvo *sdvo)
2442 {
2443 struct sdvo_device_mapping *mapping;
2444
2445 if (sdvo->port == PORT_B)
2446 mapping = &dev_priv->vbt.sdvo_mappings[0];
2447 else
2448 mapping = &dev_priv->vbt.sdvo_mappings[1];
2449
2450 if (mapping->initialized)
2451 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
2452 else
2453 intel_sdvo_guess_ddc_bus(sdvo);
2454 }
2455
2456 static void
2457 intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv,
2458 struct intel_sdvo *sdvo)
2459 {
2460 struct sdvo_device_mapping *mapping;
2461 u8 pin;
2462
2463 if (sdvo->port == PORT_B)
2464 mapping = &dev_priv->vbt.sdvo_mappings[0];
2465 else
2466 mapping = &dev_priv->vbt.sdvo_mappings[1];
2467
2468 if (mapping->initialized &&
2469 intel_gmbus_is_valid_pin(dev_priv, mapping->i2c_pin))
2470 pin = mapping->i2c_pin;
2471 else
2472 pin = GMBUS_PIN_DPB;
2473
2474 sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin);
2475
2476 /*
2477 * With gmbus we should be able to drive sdvo i2c at 2MHz, but somehow
2478 * our code totally fails once we start using gmbus. Hence fall back to
2479 * bit banging for now.
2480 */
2481 intel_gmbus_force_bit(sdvo->i2c, true);
2482 }
2483
2484 /* undo any changes intel_sdvo_select_i2c_bus() did to sdvo->i2c */
2485 static void
2486 intel_sdvo_unselect_i2c_bus(struct intel_sdvo *sdvo)
2487 {
2488 intel_gmbus_force_bit(sdvo->i2c, false);
2489 }
2490
2491 static bool
2492 intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device)
2493 {
2494 return intel_sdvo_check_supp_encode(intel_sdvo);
2495 }
2496
2497 static u8
2498 intel_sdvo_get_slave_addr(struct drm_i915_private *dev_priv,
2499 struct intel_sdvo *sdvo)
2500 {
2501 struct sdvo_device_mapping *my_mapping, *other_mapping;
2502
2503 if (sdvo->port == PORT_B) {
2504 my_mapping = &dev_priv->vbt.sdvo_mappings[0];
2505 other_mapping = &dev_priv->vbt.sdvo_mappings[1];
2506 } else {
2507 my_mapping = &dev_priv->vbt.sdvo_mappings[1];
2508 other_mapping = &dev_priv->vbt.sdvo_mappings[0];
2509 }
2510
2511 /* If the BIOS described our SDVO device, take advantage of it. */
2512 if (my_mapping->slave_addr)
2513 return my_mapping->slave_addr;
2514
2515 /*
2516 * If the BIOS only described a different SDVO device, use the
2517 * address that it isn't using.
2518 */
2519 if (other_mapping->slave_addr) {
2520 if (other_mapping->slave_addr == 0x70)
2521 return 0x72;
2522 else
2523 return 0x70;
2524 }
2525
2526 /*
2527 * No SDVO device info is found for another DVO port,
2528 * so use mapping assumption we had before BIOS parsing.
2529 */
2530 if (sdvo->port == PORT_B)
2531 return 0x70;
2532 else
2533 return 0x72;
2534 }
2535
2536 static int
2537 intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
2538 struct intel_sdvo *encoder)
2539 {
2540 struct drm_connector *drm_connector;
2541 int ret;
2542
2543 drm_connector = &connector->base.base;
2544 ret = drm_connector_init(encoder->base.base.dev,
2545 drm_connector,
2546 &intel_sdvo_connector_funcs,
2547 connector->base.base.connector_type);
2548 if (ret < 0)
2549 return ret;
2550
2551 drm_connector_helper_add(drm_connector,
2552 &intel_sdvo_connector_helper_funcs);
2553
2554 connector->base.base.interlace_allowed = 1;
2555 connector->base.base.doublescan_allowed = 0;
2556 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
2557 connector->base.get_hw_state = intel_sdvo_connector_get_hw_state;
2558
2559 intel_connector_attach_encoder(&connector->base, &encoder->base);
2560
2561 return 0;
2562 }
2563
2564 static void
2565 intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo,
2566 struct intel_sdvo_connector *connector)
2567 {
2568 struct drm_i915_private *dev_priv = to_i915(connector->base.base.dev);
2569
2570 intel_attach_force_audio_property(&connector->base.base);
2571 if (INTEL_GEN(dev_priv) >= 4 && IS_MOBILE(dev_priv)) {
2572 intel_attach_broadcast_rgb_property(&connector->base.base);
2573 }
2574 intel_attach_aspect_ratio_property(&connector->base.base);
2575 connector->base.base.state->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
2576 }
2577
2578 static struct intel_sdvo_connector *intel_sdvo_connector_alloc(void)
2579 {
2580 struct intel_sdvo_connector *sdvo_connector;
2581 struct intel_sdvo_connector_state *conn_state;
2582
2583 sdvo_connector = kzalloc(sizeof(*sdvo_connector), GFP_KERNEL);
2584 if (!sdvo_connector)
2585 return NULL;
2586
2587 conn_state = kzalloc(sizeof(*conn_state), GFP_KERNEL);
2588 if (!conn_state) {
2589 kfree(sdvo_connector);
2590 return NULL;
2591 }
2592
2593 __drm_atomic_helper_connector_reset(&sdvo_connector->base.base,
2594 &conn_state->base.base);
2595
2596 return sdvo_connector;
2597 }
2598
2599 static bool
2600 intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
2601 {
2602 struct drm_encoder *encoder = &intel_sdvo->base.base;
2603 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
2604 struct drm_connector *connector;
2605 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
2606 struct intel_connector *intel_connector;
2607 struct intel_sdvo_connector *intel_sdvo_connector;
2608
2609 DRM_DEBUG_KMS("initialising DVI device %d\n", device);
2610
2611 intel_sdvo_connector = intel_sdvo_connector_alloc();
2612 if (!intel_sdvo_connector)
2613 return false;
2614
2615 if (device == 0) {
2616 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
2617 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
2618 } else if (device == 1) {
2619 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
2620 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
2621 }
2622
2623 intel_connector = &intel_sdvo_connector->base;
2624 connector = &intel_connector->base;
2625 if (intel_sdvo_get_hotplug_support(intel_sdvo) &
2626 intel_sdvo_connector->output_flag) {
2627 intel_sdvo->hotplug_active |= intel_sdvo_connector->output_flag;
2628 /*
2629 * Some SDVO devices have one-shot hotplug interrupts.
2630 * Ensure that they get re-enabled when an interrupt happens.
2631 */
2632 intel_encoder->hotplug = intel_sdvo_hotplug;
2633 intel_sdvo_enable_hotplug(intel_encoder);
2634 } else {
2635 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
2636 }
2637 encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
2638 connector->connector_type = DRM_MODE_CONNECTOR_DVID;
2639
2640 /* gen3 doesn't do the hdmi bits in the SDVO register */
2641 if (INTEL_GEN(dev_priv) >= 4 &&
2642 intel_sdvo_is_hdmi_connector(intel_sdvo, device)) {
2643 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
2644 intel_sdvo_connector->is_hdmi = true;
2645 }
2646
2647 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2648 kfree(intel_sdvo_connector);
2649 return false;
2650 }
2651
2652 if (intel_sdvo_connector->is_hdmi)
2653 intel_sdvo_add_hdmi_properties(intel_sdvo, intel_sdvo_connector);
2654
2655 return true;
2656 }
2657
2658 static bool
2659 intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
2660 {
2661 struct drm_encoder *encoder = &intel_sdvo->base.base;
2662 struct drm_connector *connector;
2663 struct intel_connector *intel_connector;
2664 struct intel_sdvo_connector *intel_sdvo_connector;
2665
2666 DRM_DEBUG_KMS("initialising TV type %d\n", type);
2667
2668 intel_sdvo_connector = intel_sdvo_connector_alloc();
2669 if (!intel_sdvo_connector)
2670 return false;
2671
2672 intel_connector = &intel_sdvo_connector->base;
2673 connector = &intel_connector->base;
2674 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2675 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
2676
2677 intel_sdvo->controlled_output |= type;
2678 intel_sdvo_connector->output_flag = type;
2679
2680 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2681 kfree(intel_sdvo_connector);
2682 return false;
2683 }
2684
2685 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
2686 goto err;
2687
2688 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
2689 goto err;
2690
2691 return true;
2692
2693 err:
2694 intel_connector_destroy(connector);
2695 return false;
2696 }
2697
2698 static bool
2699 intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
2700 {
2701 struct drm_encoder *encoder = &intel_sdvo->base.base;
2702 struct drm_connector *connector;
2703 struct intel_connector *intel_connector;
2704 struct intel_sdvo_connector *intel_sdvo_connector;
2705
2706 DRM_DEBUG_KMS("initialising analog device %d\n", device);
2707
2708 intel_sdvo_connector = intel_sdvo_connector_alloc();
2709 if (!intel_sdvo_connector)
2710 return false;
2711
2712 intel_connector = &intel_sdvo_connector->base;
2713 connector = &intel_connector->base;
2714 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
2715 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2716 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2717
2718 if (device == 0) {
2719 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
2720 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
2721 } else if (device == 1) {
2722 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
2723 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
2724 }
2725
2726 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2727 kfree(intel_sdvo_connector);
2728 return false;
2729 }
2730
2731 return true;
2732 }
2733
2734 static bool
2735 intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
2736 {
2737 struct drm_encoder *encoder = &intel_sdvo->base.base;
2738 struct drm_connector *connector;
2739 struct intel_connector *intel_connector;
2740 struct intel_sdvo_connector *intel_sdvo_connector;
2741 struct drm_display_mode *mode;
2742
2743 DRM_DEBUG_KMS("initialising LVDS device %d\n", device);
2744
2745 intel_sdvo_connector = intel_sdvo_connector_alloc();
2746 if (!intel_sdvo_connector)
2747 return false;
2748
2749 intel_connector = &intel_sdvo_connector->base;
2750 connector = &intel_connector->base;
2751 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2752 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2753
2754 if (device == 0) {
2755 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
2756 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
2757 } else if (device == 1) {
2758 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
2759 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
2760 }
2761
2762 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2763 kfree(intel_sdvo_connector);
2764 return false;
2765 }
2766
2767 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
2768 goto err;
2769
2770 intel_sdvo_get_lvds_modes(connector);
2771
2772 list_for_each_entry(mode, &connector->probed_modes, head) {
2773 if (mode->type & DRM_MODE_TYPE_PREFERRED) {
2774 struct drm_display_mode *fixed_mode =
2775 drm_mode_duplicate(connector->dev, mode);
2776
2777 intel_panel_init(&intel_connector->panel,
2778 fixed_mode, NULL);
2779 break;
2780 }
2781 }
2782
2783 if (!intel_connector->panel.fixed_mode)
2784 goto err;
2785
2786 return true;
2787
2788 err:
2789 intel_connector_destroy(connector);
2790 return false;
2791 }
2792
2793 static bool
2794 intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, u16 flags)
2795 {
2796 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
2797
2798 if (flags & SDVO_OUTPUT_TMDS0)
2799 if (!intel_sdvo_dvi_init(intel_sdvo, 0))
2800 return false;
2801
2802 if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
2803 if (!intel_sdvo_dvi_init(intel_sdvo, 1))
2804 return false;
2805
2806 /* TV has no XXX1 function block */
2807 if (flags & SDVO_OUTPUT_SVID0)
2808 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0))
2809 return false;
2810
2811 if (flags & SDVO_OUTPUT_CVBS0)
2812 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0))
2813 return false;
2814
2815 if (flags & SDVO_OUTPUT_YPRPB0)
2816 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_YPRPB0))
2817 return false;
2818
2819 if (flags & SDVO_OUTPUT_RGB0)
2820 if (!intel_sdvo_analog_init(intel_sdvo, 0))
2821 return false;
2822
2823 if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
2824 if (!intel_sdvo_analog_init(intel_sdvo, 1))
2825 return false;
2826
2827 if (flags & SDVO_OUTPUT_LVDS0)
2828 if (!intel_sdvo_lvds_init(intel_sdvo, 0))
2829 return false;
2830
2831 if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
2832 if (!intel_sdvo_lvds_init(intel_sdvo, 1))
2833 return false;
2834
2835 if ((flags & SDVO_OUTPUT_MASK) == 0) {
2836 unsigned char bytes[2];
2837
2838 intel_sdvo->controlled_output = 0;
2839 memcpy(bytes, &intel_sdvo->caps.output_flags, 2);
2840 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
2841 SDVO_NAME(intel_sdvo),
2842 bytes[0], bytes[1]);
2843 return false;
2844 }
2845 intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2846
2847 return true;
2848 }
2849
2850 static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo)
2851 {
2852 struct drm_device *dev = intel_sdvo->base.base.dev;
2853 struct drm_connector *connector, *tmp;
2854
2855 list_for_each_entry_safe(connector, tmp,
2856 &dev->mode_config.connector_list, head) {
2857 if (intel_attached_encoder(connector) == &intel_sdvo->base) {
2858 drm_connector_unregister(connector);
2859 intel_connector_destroy(connector);
2860 }
2861 }
2862 }
2863
2864 static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
2865 struct intel_sdvo_connector *intel_sdvo_connector,
2866 int type)
2867 {
2868 struct drm_device *dev = intel_sdvo->base.base.dev;
2869 struct intel_sdvo_tv_format format;
2870 u32 format_map, i;
2871
2872 if (!intel_sdvo_set_target_output(intel_sdvo, type))
2873 return false;
2874
2875 BUILD_BUG_ON(sizeof(format) != 6);
2876 if (!intel_sdvo_get_value(intel_sdvo,
2877 SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
2878 &format, sizeof(format)))
2879 return false;
2880
2881 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
2882
2883 if (format_map == 0)
2884 return false;
2885
2886 intel_sdvo_connector->format_supported_num = 0;
2887 for (i = 0 ; i < TV_FORMAT_NUM; i++)
2888 if (format_map & (1 << i))
2889 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
2890
2891
2892 intel_sdvo_connector->tv_format =
2893 drm_property_create(dev, DRM_MODE_PROP_ENUM,
2894 "mode", intel_sdvo_connector->format_supported_num);
2895 if (!intel_sdvo_connector->tv_format)
2896 return false;
2897
2898 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
2899 drm_property_add_enum(intel_sdvo_connector->tv_format, i,
2900 tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
2901
2902 intel_sdvo_connector->base.base.state->tv.mode = intel_sdvo_connector->tv_format_supported[0];
2903 drm_object_attach_property(&intel_sdvo_connector->base.base.base,
2904 intel_sdvo_connector->tv_format, 0);
2905 return true;
2906
2907 }
2908
2909 #define _ENHANCEMENT(state_assignment, name, NAME) do { \
2910 if (enhancements.name) { \
2911 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
2912 !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
2913 return false; \
2914 intel_sdvo_connector->name = \
2915 drm_property_create_range(dev, 0, #name, 0, data_value[0]); \
2916 if (!intel_sdvo_connector->name) return false; \
2917 state_assignment = response; \
2918 drm_object_attach_property(&connector->base, \
2919 intel_sdvo_connector->name, 0); \
2920 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
2921 data_value[0], data_value[1], response); \
2922 } \
2923 } while (0)
2924
2925 #define ENHANCEMENT(state, name, NAME) _ENHANCEMENT((state)->name, name, NAME)
2926
2927 static bool
2928 intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
2929 struct intel_sdvo_connector *intel_sdvo_connector,
2930 struct intel_sdvo_enhancements_reply enhancements)
2931 {
2932 struct drm_device *dev = intel_sdvo->base.base.dev;
2933 struct drm_connector *connector = &intel_sdvo_connector->base.base;
2934 struct drm_connector_state *conn_state = connector->state;
2935 struct intel_sdvo_connector_state *sdvo_state =
2936 to_intel_sdvo_connector_state(conn_state);
2937 u16 response, data_value[2];
2938
2939 /* when horizontal overscan is supported, Add the left/right property */
2940 if (enhancements.overscan_h) {
2941 if (!intel_sdvo_get_value(intel_sdvo,
2942 SDVO_CMD_GET_MAX_OVERSCAN_H,
2943 &data_value, 4))
2944 return false;
2945
2946 if (!intel_sdvo_get_value(intel_sdvo,
2947 SDVO_CMD_GET_OVERSCAN_H,
2948 &response, 2))
2949 return false;
2950
2951 sdvo_state->tv.overscan_h = response;
2952
2953 intel_sdvo_connector->max_hscan = data_value[0];
2954 intel_sdvo_connector->left =
2955 drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]);
2956 if (!intel_sdvo_connector->left)
2957 return false;
2958
2959 drm_object_attach_property(&connector->base,
2960 intel_sdvo_connector->left, 0);
2961
2962 intel_sdvo_connector->right =
2963 drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]);
2964 if (!intel_sdvo_connector->right)
2965 return false;
2966
2967 drm_object_attach_property(&connector->base,
2968 intel_sdvo_connector->right, 0);
2969 DRM_DEBUG_KMS("h_overscan: max %d, "
2970 "default %d, current %d\n",
2971 data_value[0], data_value[1], response);
2972 }
2973
2974 if (enhancements.overscan_v) {
2975 if (!intel_sdvo_get_value(intel_sdvo,
2976 SDVO_CMD_GET_MAX_OVERSCAN_V,
2977 &data_value, 4))
2978 return false;
2979
2980 if (!intel_sdvo_get_value(intel_sdvo,
2981 SDVO_CMD_GET_OVERSCAN_V,
2982 &response, 2))
2983 return false;
2984
2985 sdvo_state->tv.overscan_v = response;
2986
2987 intel_sdvo_connector->max_vscan = data_value[0];
2988 intel_sdvo_connector->top =
2989 drm_property_create_range(dev, 0,
2990 "top_margin", 0, data_value[0]);
2991 if (!intel_sdvo_connector->top)
2992 return false;
2993
2994 drm_object_attach_property(&connector->base,
2995 intel_sdvo_connector->top, 0);
2996
2997 intel_sdvo_connector->bottom =
2998 drm_property_create_range(dev, 0,
2999 "bottom_margin", 0, data_value[0]);
3000 if (!intel_sdvo_connector->bottom)
3001 return false;
3002
3003 drm_object_attach_property(&connector->base,
3004 intel_sdvo_connector->bottom, 0);
3005 DRM_DEBUG_KMS("v_overscan: max %d, "
3006 "default %d, current %d\n",
3007 data_value[0], data_value[1], response);
3008 }
3009
3010 ENHANCEMENT(&sdvo_state->tv, hpos, HPOS);
3011 ENHANCEMENT(&sdvo_state->tv, vpos, VPOS);
3012 ENHANCEMENT(&conn_state->tv, saturation, SATURATION);
3013 ENHANCEMENT(&conn_state->tv, contrast, CONTRAST);
3014 ENHANCEMENT(&conn_state->tv, hue, HUE);
3015 ENHANCEMENT(&conn_state->tv, brightness, BRIGHTNESS);
3016 ENHANCEMENT(&sdvo_state->tv, sharpness, SHARPNESS);
3017 ENHANCEMENT(&sdvo_state->tv, flicker_filter, FLICKER_FILTER);
3018 ENHANCEMENT(&sdvo_state->tv, flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
3019 ENHANCEMENT(&sdvo_state->tv, flicker_filter_2d, FLICKER_FILTER_2D);
3020 _ENHANCEMENT(sdvo_state->tv.chroma_filter, tv_chroma_filter, TV_CHROMA_FILTER);
3021 _ENHANCEMENT(sdvo_state->tv.luma_filter, tv_luma_filter, TV_LUMA_FILTER);
3022
3023 if (enhancements.dot_crawl) {
3024 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
3025 return false;
3026
3027 sdvo_state->tv.dot_crawl = response & 0x1;
3028 intel_sdvo_connector->dot_crawl =
3029 drm_property_create_range(dev, 0, "dot_crawl", 0, 1);
3030 if (!intel_sdvo_connector->dot_crawl)
3031 return false;
3032
3033 drm_object_attach_property(&connector->base,
3034 intel_sdvo_connector->dot_crawl, 0);
3035 DRM_DEBUG_KMS("dot crawl: current %d\n", response);
3036 }
3037
3038 return true;
3039 }
3040
3041 static bool
3042 intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
3043 struct intel_sdvo_connector *intel_sdvo_connector,
3044 struct intel_sdvo_enhancements_reply enhancements)
3045 {
3046 struct drm_device *dev = intel_sdvo->base.base.dev;
3047 struct drm_connector *connector = &intel_sdvo_connector->base.base;
3048 u16 response, data_value[2];
3049
3050 ENHANCEMENT(&connector->state->tv, brightness, BRIGHTNESS);
3051
3052 return true;
3053 }
3054 #undef ENHANCEMENT
3055 #undef _ENHANCEMENT
3056
3057 static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
3058 struct intel_sdvo_connector *intel_sdvo_connector)
3059 {
3060 union {
3061 struct intel_sdvo_enhancements_reply reply;
3062 u16 response;
3063 } enhancements;
3064
3065 BUILD_BUG_ON(sizeof(enhancements) != 2);
3066
3067 if (!intel_sdvo_get_value(intel_sdvo,
3068 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
3069 &enhancements, sizeof(enhancements)) ||
3070 enhancements.response == 0) {
3071 DRM_DEBUG_KMS("No enhancement is supported\n");
3072 return true;
3073 }
3074
3075 if (IS_TV(intel_sdvo_connector))
3076 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
3077 else if (IS_LVDS(intel_sdvo_connector))
3078 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
3079 else
3080 return true;
3081 }
3082
3083 static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter,
3084 struct i2c_msg *msgs,
3085 int num)
3086 {
3087 struct intel_sdvo *sdvo = adapter->algo_data;
3088
3089 if (!__intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus))
3090 return -EIO;
3091
3092 return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num);
3093 }
3094
3095 static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter)
3096 {
3097 struct intel_sdvo *sdvo = adapter->algo_data;
3098 return sdvo->i2c->algo->functionality(sdvo->i2c);
3099 }
3100
3101 static const struct i2c_algorithm intel_sdvo_ddc_proxy = {
3102 .master_xfer = intel_sdvo_ddc_proxy_xfer,
3103 .functionality = intel_sdvo_ddc_proxy_func
3104 };
3105
3106 static void proxy_lock_bus(struct i2c_adapter *adapter,
3107 unsigned int flags)
3108 {
3109 struct intel_sdvo *sdvo = adapter->algo_data;
3110 sdvo->i2c->lock_ops->lock_bus(sdvo->i2c, flags);
3111 }
3112
3113 static int proxy_trylock_bus(struct i2c_adapter *adapter,
3114 unsigned int flags)
3115 {
3116 struct intel_sdvo *sdvo = adapter->algo_data;
3117 return sdvo->i2c->lock_ops->trylock_bus(sdvo->i2c, flags);
3118 }
3119
3120 static void proxy_unlock_bus(struct i2c_adapter *adapter,
3121 unsigned int flags)
3122 {
3123 struct intel_sdvo *sdvo = adapter->algo_data;
3124 sdvo->i2c->lock_ops->unlock_bus(sdvo->i2c, flags);
3125 }
3126
3127 static const struct i2c_lock_operations proxy_lock_ops = {
3128 .lock_bus = proxy_lock_bus,
3129 .trylock_bus = proxy_trylock_bus,
3130 .unlock_bus = proxy_unlock_bus,
3131 };
3132
3133 static bool
3134 intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo,
3135 struct drm_i915_private *dev_priv)
3136 {
3137 struct pci_dev *pdev = dev_priv->drm.pdev;
3138
3139 sdvo->ddc.owner = THIS_MODULE;
3140 sdvo->ddc.class = I2C_CLASS_DDC;
3141 snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy");
3142 sdvo->ddc.dev.parent = &pdev->dev;
3143 sdvo->ddc.algo_data = sdvo;
3144 sdvo->ddc.algo = &intel_sdvo_ddc_proxy;
3145 sdvo->ddc.lock_ops = &proxy_lock_ops;
3146
3147 return i2c_add_adapter(&sdvo->ddc) == 0;
3148 }
3149
3150 static void assert_sdvo_port_valid(const struct drm_i915_private *dev_priv,
3151 enum port port)
3152 {
3153 if (HAS_PCH_SPLIT(dev_priv))
3154 WARN_ON(port != PORT_B);
3155 else
3156 WARN_ON(port != PORT_B && port != PORT_C);
3157 }
3158
3159 bool intel_sdvo_init(struct drm_i915_private *dev_priv,
3160 i915_reg_t sdvo_reg, enum port port)
3161 {
3162 struct intel_encoder *intel_encoder;
3163 struct intel_sdvo *intel_sdvo;
3164 int i;
3165
3166 assert_sdvo_port_valid(dev_priv, port);
3167
3168 intel_sdvo = kzalloc(sizeof(*intel_sdvo), GFP_KERNEL);
3169 if (!intel_sdvo)
3170 return false;
3171
3172 intel_sdvo->sdvo_reg = sdvo_reg;
3173 intel_sdvo->port = port;
3174 intel_sdvo->slave_addr =
3175 intel_sdvo_get_slave_addr(dev_priv, intel_sdvo) >> 1;
3176 intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo);
3177 if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev_priv))
3178 goto err_i2c_bus;
3179
3180 /* encoder type will be decided later */
3181 intel_encoder = &intel_sdvo->base;
3182 intel_encoder->type = INTEL_OUTPUT_SDVO;
3183 intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER;
3184 intel_encoder->port = port;
3185 drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
3186 &intel_sdvo_enc_funcs, 0,
3187 "SDVO %c", port_name(port));
3188
3189 /* Read the regs to test if we can talk to the device */
3190 for (i = 0; i < 0x40; i++) {
3191 u8 byte;
3192
3193 if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) {
3194 DRM_DEBUG_KMS("No SDVO device found on %s\n",
3195 SDVO_NAME(intel_sdvo));
3196 goto err;
3197 }
3198 }
3199
3200 intel_encoder->compute_config = intel_sdvo_compute_config;
3201 if (HAS_PCH_SPLIT(dev_priv)) {
3202 intel_encoder->disable = pch_disable_sdvo;
3203 intel_encoder->post_disable = pch_post_disable_sdvo;
3204 } else {
3205 intel_encoder->disable = intel_disable_sdvo;
3206 }
3207 intel_encoder->pre_enable = intel_sdvo_pre_enable;
3208 intel_encoder->enable = intel_enable_sdvo;
3209 intel_encoder->get_hw_state = intel_sdvo_get_hw_state;
3210 intel_encoder->get_config = intel_sdvo_get_config;
3211
3212 /* In default case sdvo lvds is false */
3213 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
3214 goto err;
3215
3216 if (intel_sdvo_output_setup(intel_sdvo,
3217 intel_sdvo->caps.output_flags) != true) {
3218 DRM_DEBUG_KMS("SDVO output failed to setup on %s\n",
3219 SDVO_NAME(intel_sdvo));
3220 /* Output_setup can leave behind connectors! */
3221 goto err_output;
3222 }
3223
3224 /*
3225 * Only enable the hotplug irq if we need it, to work around noisy
3226 * hotplug lines.
3227 */
3228 if (intel_sdvo->hotplug_active) {
3229 if (intel_sdvo->port == PORT_B)
3230 intel_encoder->hpd_pin = HPD_SDVO_B;
3231 else
3232 intel_encoder->hpd_pin = HPD_SDVO_C;
3233 }
3234
3235 /*
3236 * Cloning SDVO with anything is often impossible, since the SDVO
3237 * encoder can request a special input timing mode. And even if that's
3238 * not the case we have evidence that cloning a plain unscaled mode with
3239 * VGA doesn't really work. Furthermore the cloning flags are way too
3240 * simplistic anyway to express such constraints, so just give up on
3241 * cloning for SDVO encoders.
3242 */
3243 intel_sdvo->base.cloneable = 0;
3244
3245 intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo);
3246
3247 /* Set the input timing to the screen. Assume always input 0. */
3248 if (!intel_sdvo_set_target_input(intel_sdvo))
3249 goto err_output;
3250
3251 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
3252 &intel_sdvo->pixel_clock_min,
3253 &intel_sdvo->pixel_clock_max))
3254 goto err_output;
3255
3256 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
3257 "clock range %dMHz - %dMHz, "
3258 "input 1: %c, input 2: %c, "
3259 "output 1: %c, output 2: %c\n",
3260 SDVO_NAME(intel_sdvo),
3261 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
3262 intel_sdvo->caps.device_rev_id,
3263 intel_sdvo->pixel_clock_min / 1000,
3264 intel_sdvo->pixel_clock_max / 1000,
3265 (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
3266 (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
3267 /* check currently supported outputs */
3268 intel_sdvo->caps.output_flags &
3269 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
3270 intel_sdvo->caps.output_flags &
3271 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
3272 return true;
3273
3274 err_output:
3275 intel_sdvo_output_cleanup(intel_sdvo);
3276
3277 err:
3278 drm_encoder_cleanup(&intel_encoder->base);
3279 i2c_del_adapter(&intel_sdvo->ddc);
3280 err_i2c_bus:
3281 intel_sdvo_unselect_i2c_bus(intel_sdvo);
3282 kfree(intel_sdvo);
3283
3284 return false;
3285 }
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