1 // SPDX-License-Identifier: GPL-2.0+
3 * i.MX IPUv3 Graphics driver
5 * Copyright (C) 2011 Sascha Hauer, Pengutronix
9 #include <linux/component.h>
10 #include <linux/device.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/errno.h>
13 #include <linux/export.h>
14 #include <linux/module.h>
15 #include <linux/platform_device.h>
17 #include <video/imx-ipu-v3.h>
19 #include <drm/drm_atomic.h>
20 #include <drm/drm_atomic_helper.h>
21 #include <drm/drm_fb_cma_helper.h>
22 #include <drm/drm_gem_cma_helper.h>
23 #include <drm/drm_managed.h>
24 #include <drm/drm_probe_helper.h>
25 #include <drm/drm_vblank.h>
28 #include "ipuv3-plane.h"
30 #define DRIVER_DESC "i.MX IPUv3 Graphics"
36 /* plane[0] is the full plane, plane[1] is the partial plane */
37 struct ipu_plane
*plane
[2];
42 struct drm_pending_vblank_event
*event
;
45 static inline struct ipu_crtc
*to_ipu_crtc(struct drm_crtc
*crtc
)
47 return container_of(crtc
, struct ipu_crtc
, base
);
50 static void ipu_crtc_atomic_enable(struct drm_crtc
*crtc
,
51 struct drm_atomic_state
*state
)
53 struct ipu_crtc
*ipu_crtc
= to_ipu_crtc(crtc
);
54 struct ipu_soc
*ipu
= dev_get_drvdata(ipu_crtc
->dev
->parent
);
58 ipu_dc_enable_channel(ipu_crtc
->dc
);
59 ipu_di_enable(ipu_crtc
->di
);
62 static void ipu_crtc_disable_planes(struct ipu_crtc
*ipu_crtc
,
63 struct drm_crtc_state
*old_crtc_state
)
65 bool disable_partial
= false;
66 bool disable_full
= false;
67 struct drm_plane
*plane
;
69 drm_atomic_crtc_state_for_each_plane(plane
, old_crtc_state
) {
70 if (plane
== &ipu_crtc
->plane
[0]->base
)
72 if (ipu_crtc
->plane
[1] && plane
== &ipu_crtc
->plane
[1]->base
)
73 disable_partial
= true;
77 ipu_plane_disable(ipu_crtc
->plane
[1], true);
79 ipu_plane_disable(ipu_crtc
->plane
[0], true);
82 static void ipu_crtc_atomic_disable(struct drm_crtc
*crtc
,
83 struct drm_atomic_state
*state
)
85 struct drm_crtc_state
*old_crtc_state
= drm_atomic_get_old_crtc_state(state
,
87 struct ipu_crtc
*ipu_crtc
= to_ipu_crtc(crtc
);
88 struct ipu_soc
*ipu
= dev_get_drvdata(ipu_crtc
->dev
->parent
);
90 ipu_dc_disable_channel(ipu_crtc
->dc
);
91 ipu_di_disable(ipu_crtc
->di
);
93 * Planes must be disabled before DC clock is removed, as otherwise the
94 * attached IDMACs will be left in undefined state, possibly hanging
95 * the IPU or even system.
97 ipu_crtc_disable_planes(ipu_crtc
, old_crtc_state
);
101 drm_crtc_vblank_off(crtc
);
103 spin_lock_irq(&crtc
->dev
->event_lock
);
104 if (crtc
->state
->event
&& !crtc
->state
->active
) {
105 drm_crtc_send_vblank_event(crtc
, crtc
->state
->event
);
106 crtc
->state
->event
= NULL
;
108 spin_unlock_irq(&crtc
->dev
->event_lock
);
111 static void imx_drm_crtc_reset(struct drm_crtc
*crtc
)
113 struct imx_crtc_state
*state
;
116 __drm_atomic_helper_crtc_destroy_state(crtc
->state
);
118 kfree(to_imx_crtc_state(crtc
->state
));
121 state
= kzalloc(sizeof(*state
), GFP_KERNEL
);
123 __drm_atomic_helper_crtc_reset(crtc
, &state
->base
);
126 static struct drm_crtc_state
*imx_drm_crtc_duplicate_state(struct drm_crtc
*crtc
)
128 struct imx_crtc_state
*state
;
130 state
= kzalloc(sizeof(*state
), GFP_KERNEL
);
134 __drm_atomic_helper_crtc_duplicate_state(crtc
, &state
->base
);
136 WARN_ON(state
->base
.crtc
!= crtc
);
137 state
->base
.crtc
= crtc
;
142 static void imx_drm_crtc_destroy_state(struct drm_crtc
*crtc
,
143 struct drm_crtc_state
*state
)
145 __drm_atomic_helper_crtc_destroy_state(state
);
146 kfree(to_imx_crtc_state(state
));
149 static int ipu_enable_vblank(struct drm_crtc
*crtc
)
151 struct ipu_crtc
*ipu_crtc
= to_ipu_crtc(crtc
);
153 enable_irq(ipu_crtc
->irq
);
158 static void ipu_disable_vblank(struct drm_crtc
*crtc
)
160 struct ipu_crtc
*ipu_crtc
= to_ipu_crtc(crtc
);
162 disable_irq_nosync(ipu_crtc
->irq
);
165 static const struct drm_crtc_funcs ipu_crtc_funcs
= {
166 .set_config
= drm_atomic_helper_set_config
,
167 .page_flip
= drm_atomic_helper_page_flip
,
168 .reset
= imx_drm_crtc_reset
,
169 .atomic_duplicate_state
= imx_drm_crtc_duplicate_state
,
170 .atomic_destroy_state
= imx_drm_crtc_destroy_state
,
171 .enable_vblank
= ipu_enable_vblank
,
172 .disable_vblank
= ipu_disable_vblank
,
175 static irqreturn_t
ipu_irq_handler(int irq
, void *dev_id
)
177 struct ipu_crtc
*ipu_crtc
= dev_id
;
178 struct drm_crtc
*crtc
= &ipu_crtc
->base
;
182 drm_crtc_handle_vblank(crtc
);
184 if (ipu_crtc
->event
) {
185 for (i
= 0; i
< ARRAY_SIZE(ipu_crtc
->plane
); i
++) {
186 struct ipu_plane
*plane
= ipu_crtc
->plane
[i
];
191 if (ipu_plane_atomic_update_pending(&plane
->base
))
195 if (i
== ARRAY_SIZE(ipu_crtc
->plane
)) {
196 spin_lock_irqsave(&crtc
->dev
->event_lock
, flags
);
197 drm_crtc_send_vblank_event(crtc
, ipu_crtc
->event
);
198 ipu_crtc
->event
= NULL
;
199 drm_crtc_vblank_put(crtc
);
200 spin_unlock_irqrestore(&crtc
->dev
->event_lock
, flags
);
207 static bool ipu_crtc_mode_fixup(struct drm_crtc
*crtc
,
208 const struct drm_display_mode
*mode
,
209 struct drm_display_mode
*adjusted_mode
)
211 struct ipu_crtc
*ipu_crtc
= to_ipu_crtc(crtc
);
215 drm_display_mode_to_videomode(adjusted_mode
, &vm
);
217 ret
= ipu_di_adjust_videomode(ipu_crtc
->di
, &vm
);
221 if ((vm
.vsync_len
== 0) || (vm
.hsync_len
== 0))
224 drm_display_mode_from_videomode(&vm
, adjusted_mode
);
229 static int ipu_crtc_atomic_check(struct drm_crtc
*crtc
,
230 struct drm_atomic_state
*state
)
232 struct drm_crtc_state
*crtc_state
= drm_atomic_get_new_crtc_state(state
,
234 u32 primary_plane_mask
= drm_plane_mask(crtc
->primary
);
236 if (crtc_state
->active
&& (primary_plane_mask
& crtc_state
->plane_mask
) == 0)
242 static void ipu_crtc_atomic_begin(struct drm_crtc
*crtc
,
243 struct drm_atomic_state
*state
)
245 drm_crtc_vblank_on(crtc
);
248 static void ipu_crtc_atomic_flush(struct drm_crtc
*crtc
,
249 struct drm_atomic_state
*state
)
251 spin_lock_irq(&crtc
->dev
->event_lock
);
252 if (crtc
->state
->event
) {
253 struct ipu_crtc
*ipu_crtc
= to_ipu_crtc(crtc
);
255 WARN_ON(drm_crtc_vblank_get(crtc
));
256 ipu_crtc
->event
= crtc
->state
->event
;
257 crtc
->state
->event
= NULL
;
259 spin_unlock_irq(&crtc
->dev
->event_lock
);
262 static void ipu_crtc_mode_set_nofb(struct drm_crtc
*crtc
)
264 struct drm_device
*dev
= crtc
->dev
;
265 struct drm_encoder
*encoder
;
266 struct ipu_crtc
*ipu_crtc
= to_ipu_crtc(crtc
);
267 struct drm_display_mode
*mode
= &crtc
->state
->adjusted_mode
;
268 struct imx_crtc_state
*imx_crtc_state
= to_imx_crtc_state(crtc
->state
);
269 struct ipu_di_signal_cfg sig_cfg
= {};
270 unsigned long encoder_types
= 0;
272 dev_dbg(ipu_crtc
->dev
, "%s: mode->hdisplay: %d\n", __func__
,
274 dev_dbg(ipu_crtc
->dev
, "%s: mode->vdisplay: %d\n", __func__
,
277 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
278 if (encoder
->crtc
== crtc
)
279 encoder_types
|= BIT(encoder
->encoder_type
);
282 dev_dbg(ipu_crtc
->dev
, "%s: attached to encoder types 0x%lx\n",
283 __func__
, encoder_types
);
286 * If we have DAC or LDB, then we need the IPU DI clock to be
287 * the same as the LDB DI clock. For TVDAC, derive the IPU DI
288 * clock from 27 MHz TVE_DI clock, but allow to divide it.
290 if (encoder_types
& (BIT(DRM_MODE_ENCODER_DAC
) |
291 BIT(DRM_MODE_ENCODER_LVDS
)))
292 sig_cfg
.clkflags
= IPU_DI_CLKMODE_SYNC
| IPU_DI_CLKMODE_EXT
;
293 else if (encoder_types
& BIT(DRM_MODE_ENCODER_TVDAC
))
294 sig_cfg
.clkflags
= IPU_DI_CLKMODE_EXT
;
296 sig_cfg
.clkflags
= 0;
298 sig_cfg
.enable_pol
= !(imx_crtc_state
->bus_flags
& DRM_BUS_FLAG_DE_LOW
);
299 /* Default to driving pixel data on negative clock edges */
300 sig_cfg
.clk_pol
= !!(imx_crtc_state
->bus_flags
&
301 DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE
);
302 sig_cfg
.bus_format
= imx_crtc_state
->bus_format
;
303 sig_cfg
.v_to_h_sync
= 0;
304 sig_cfg
.hsync_pin
= imx_crtc_state
->di_hsync_pin
;
305 sig_cfg
.vsync_pin
= imx_crtc_state
->di_vsync_pin
;
307 drm_display_mode_to_videomode(mode
, &sig_cfg
.mode
);
308 if (!IS_ALIGNED(sig_cfg
.mode
.hactive
, 8)) {
309 unsigned int new_hactive
= ALIGN(sig_cfg
.mode
.hactive
, 8);
311 dev_warn(ipu_crtc
->dev
, "8-pixel align hactive %d -> %d\n",
312 sig_cfg
.mode
.hactive
, new_hactive
);
314 sig_cfg
.mode
.hfront_porch
= new_hactive
- sig_cfg
.mode
.hactive
;
315 sig_cfg
.mode
.hactive
= new_hactive
;
318 ipu_dc_init_sync(ipu_crtc
->dc
, ipu_crtc
->di
,
319 mode
->flags
& DRM_MODE_FLAG_INTERLACE
,
320 imx_crtc_state
->bus_format
, sig_cfg
.mode
.hactive
);
321 ipu_di_init_sync_panel(ipu_crtc
->di
, &sig_cfg
);
324 static const struct drm_crtc_helper_funcs ipu_helper_funcs
= {
325 .mode_fixup
= ipu_crtc_mode_fixup
,
326 .mode_set_nofb
= ipu_crtc_mode_set_nofb
,
327 .atomic_check
= ipu_crtc_atomic_check
,
328 .atomic_begin
= ipu_crtc_atomic_begin
,
329 .atomic_flush
= ipu_crtc_atomic_flush
,
330 .atomic_disable
= ipu_crtc_atomic_disable
,
331 .atomic_enable
= ipu_crtc_atomic_enable
,
334 static void ipu_put_resources(struct drm_device
*dev
, void *ptr
)
336 struct ipu_crtc
*ipu_crtc
= ptr
;
338 if (!IS_ERR_OR_NULL(ipu_crtc
->dc
))
339 ipu_dc_put(ipu_crtc
->dc
);
340 if (!IS_ERR_OR_NULL(ipu_crtc
->di
))
341 ipu_di_put(ipu_crtc
->di
);
344 static int ipu_get_resources(struct drm_device
*dev
, struct ipu_crtc
*ipu_crtc
,
345 struct ipu_client_platformdata
*pdata
)
347 struct ipu_soc
*ipu
= dev_get_drvdata(ipu_crtc
->dev
->parent
);
350 ipu_crtc
->dc
= ipu_dc_get(ipu
, pdata
->dc
);
351 if (IS_ERR(ipu_crtc
->dc
))
352 return PTR_ERR(ipu_crtc
->dc
);
354 ret
= drmm_add_action_or_reset(dev
, ipu_put_resources
, ipu_crtc
);
358 ipu_crtc
->di
= ipu_di_get(ipu
, pdata
->di
);
359 if (IS_ERR(ipu_crtc
->di
))
360 return PTR_ERR(ipu_crtc
->di
);
365 static int ipu_drm_bind(struct device
*dev
, struct device
*master
, void *data
)
367 struct ipu_client_platformdata
*pdata
= dev
->platform_data
;
368 struct ipu_soc
*ipu
= dev_get_drvdata(dev
->parent
);
369 struct drm_device
*drm
= data
;
370 struct ipu_plane
*primary_plane
;
371 struct ipu_crtc
*ipu_crtc
;
372 struct drm_crtc
*crtc
;
377 dp
= IPU_DP_FLOW_SYNC_BG
;
378 primary_plane
= ipu_plane_init(drm
, ipu
, pdata
->dma
[0], dp
, 0,
379 DRM_PLANE_TYPE_PRIMARY
);
380 if (IS_ERR(primary_plane
))
381 return PTR_ERR(primary_plane
);
383 ipu_crtc
= drmm_crtc_alloc_with_planes(drm
, struct ipu_crtc
, base
,
384 &primary_plane
->base
, NULL
,
385 &ipu_crtc_funcs
, NULL
);
386 if (IS_ERR(ipu_crtc
))
387 return PTR_ERR(ipu_crtc
);
390 ipu_crtc
->plane
[0] = primary_plane
;
392 crtc
= &ipu_crtc
->base
;
393 crtc
->port
= pdata
->of_node
;
394 drm_crtc_helper_add(crtc
, &ipu_helper_funcs
);
396 ret
= ipu_get_resources(drm
, ipu_crtc
, pdata
);
398 dev_err(ipu_crtc
->dev
, "getting resources failed with %d.\n",
403 /* If this crtc is using the DP, add an overlay plane */
404 if (pdata
->dp
>= 0 && pdata
->dma
[1] > 0) {
405 ipu_crtc
->plane
[1] = ipu_plane_init(drm
, ipu
, pdata
->dma
[1],
407 drm_crtc_mask(&ipu_crtc
->base
),
408 DRM_PLANE_TYPE_OVERLAY
);
409 if (IS_ERR(ipu_crtc
->plane
[1]))
410 ipu_crtc
->plane
[1] = NULL
;
413 ipu_crtc
->irq
= ipu_plane_irq(ipu_crtc
->plane
[0]);
414 ret
= devm_request_irq(ipu_crtc
->dev
, ipu_crtc
->irq
, ipu_irq_handler
, 0,
415 "imx_drm", ipu_crtc
);
417 dev_err(ipu_crtc
->dev
, "irq request failed with %d.\n", ret
);
420 /* Only enable IRQ when we actually need it to trigger work. */
421 disable_irq(ipu_crtc
->irq
);
426 static const struct component_ops ipu_crtc_ops
= {
427 .bind
= ipu_drm_bind
,
430 static int ipu_drm_probe(struct platform_device
*pdev
)
432 struct device
*dev
= &pdev
->dev
;
435 if (!dev
->platform_data
)
438 ret
= dma_set_coherent_mask(dev
, DMA_BIT_MASK(32));
442 return component_add(dev
, &ipu_crtc_ops
);
445 static int ipu_drm_remove(struct platform_device
*pdev
)
447 component_del(&pdev
->dev
, &ipu_crtc_ops
);
451 struct platform_driver ipu_drm_driver
= {
453 .name
= "imx-ipuv3-crtc",
455 .probe
= ipu_drm_probe
,
456 .remove
= ipu_drm_remove
,