2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: Jie Qiu <jie.qiu@mediatek.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #include <drm/drm_atomic_helper.h>
16 #include <drm/drm_crtc.h>
17 #include <drm/drm_crtc_helper.h>
18 #include <drm/drm_edid.h>
19 #include <linux/arm-smccc.h>
20 #include <linux/clk.h>
21 #include <linux/delay.h>
22 #include <linux/hdmi.h>
23 #include <linux/i2c.h>
25 #include <linux/kernel.h>
26 #include <linux/mfd/syscon.h>
27 #include <linux/of_platform.h>
29 #include <linux/of_gpio.h>
30 #include <linux/of_graph.h>
31 #include <linux/phy/phy.h>
32 #include <linux/platform_device.h>
33 #include <linux/regmap.h>
34 #include <sound/hdmi-codec.h>
37 #include "mtk_hdmi_regs.h"
41 enum mtk_hdmi_clk_id
{
42 MTK_HDMI_CLK_HDMI_PIXEL
,
43 MTK_HDMI_CLK_HDMI_PLL
,
44 MTK_HDMI_CLK_AUD_BCLK
,
45 MTK_HDMI_CLK_AUD_SPDIF
,
49 enum hdmi_aud_input_type
{
50 HDMI_AUD_INPUT_I2S
= 0,
54 enum hdmi_aud_i2s_fmt
{
55 HDMI_I2S_MODE_RJT_24BIT
= 0,
56 HDMI_I2S_MODE_RJT_16BIT
,
57 HDMI_I2S_MODE_LJT_24BIT
,
58 HDMI_I2S_MODE_LJT_16BIT
,
59 HDMI_I2S_MODE_I2S_24BIT
,
60 HDMI_I2S_MODE_I2S_16BIT
73 enum hdmi_aud_channel_type
{
74 HDMI_AUD_CHAN_TYPE_1_0
= 0,
75 HDMI_AUD_CHAN_TYPE_1_1
,
76 HDMI_AUD_CHAN_TYPE_2_0
,
77 HDMI_AUD_CHAN_TYPE_2_1
,
78 HDMI_AUD_CHAN_TYPE_3_0
,
79 HDMI_AUD_CHAN_TYPE_3_1
,
80 HDMI_AUD_CHAN_TYPE_4_0
,
81 HDMI_AUD_CHAN_TYPE_4_1
,
82 HDMI_AUD_CHAN_TYPE_5_0
,
83 HDMI_AUD_CHAN_TYPE_5_1
,
84 HDMI_AUD_CHAN_TYPE_6_0
,
85 HDMI_AUD_CHAN_TYPE_6_1
,
86 HDMI_AUD_CHAN_TYPE_7_0
,
87 HDMI_AUD_CHAN_TYPE_7_1
,
88 HDMI_AUD_CHAN_TYPE_3_0_LRS
,
89 HDMI_AUD_CHAN_TYPE_3_1_LRS
,
90 HDMI_AUD_CHAN_TYPE_4_0_CLRS
,
91 HDMI_AUD_CHAN_TYPE_4_1_CLRS
,
92 HDMI_AUD_CHAN_TYPE_6_1_CS
,
93 HDMI_AUD_CHAN_TYPE_6_1_CH
,
94 HDMI_AUD_CHAN_TYPE_6_1_OH
,
95 HDMI_AUD_CHAN_TYPE_6_1_CHR
,
96 HDMI_AUD_CHAN_TYPE_7_1_LH_RH
,
97 HDMI_AUD_CHAN_TYPE_7_1_LSR_RSR
,
98 HDMI_AUD_CHAN_TYPE_7_1_LC_RC
,
99 HDMI_AUD_CHAN_TYPE_7_1_LW_RW
,
100 HDMI_AUD_CHAN_TYPE_7_1_LSD_RSD
,
101 HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS
,
102 HDMI_AUD_CHAN_TYPE_7_1_LHS_RHS
,
103 HDMI_AUD_CHAN_TYPE_7_1_CS_CH
,
104 HDMI_AUD_CHAN_TYPE_7_1_CS_OH
,
105 HDMI_AUD_CHAN_TYPE_7_1_CS_CHR
,
106 HDMI_AUD_CHAN_TYPE_7_1_CH_OH
,
107 HDMI_AUD_CHAN_TYPE_7_1_CH_CHR
,
108 HDMI_AUD_CHAN_TYPE_7_1_OH_CHR
,
109 HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS_LSR_RSR
,
110 HDMI_AUD_CHAN_TYPE_6_0_CS
,
111 HDMI_AUD_CHAN_TYPE_6_0_CH
,
112 HDMI_AUD_CHAN_TYPE_6_0_OH
,
113 HDMI_AUD_CHAN_TYPE_6_0_CHR
,
114 HDMI_AUD_CHAN_TYPE_7_0_LH_RH
,
115 HDMI_AUD_CHAN_TYPE_7_0_LSR_RSR
,
116 HDMI_AUD_CHAN_TYPE_7_0_LC_RC
,
117 HDMI_AUD_CHAN_TYPE_7_0_LW_RW
,
118 HDMI_AUD_CHAN_TYPE_7_0_LSD_RSD
,
119 HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS
,
120 HDMI_AUD_CHAN_TYPE_7_0_LHS_RHS
,
121 HDMI_AUD_CHAN_TYPE_7_0_CS_CH
,
122 HDMI_AUD_CHAN_TYPE_7_0_CS_OH
,
123 HDMI_AUD_CHAN_TYPE_7_0_CS_CHR
,
124 HDMI_AUD_CHAN_TYPE_7_0_CH_OH
,
125 HDMI_AUD_CHAN_TYPE_7_0_CH_CHR
,
126 HDMI_AUD_CHAN_TYPE_7_0_OH_CHR
,
127 HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS_LSR_RSR
,
128 HDMI_AUD_CHAN_TYPE_8_0_LH_RH_CS
,
129 HDMI_AUD_CHAN_TYPE_UNKNOWN
= 0xFF
132 enum hdmi_aud_channel_swap_type
{
134 HDMI_AUD_SWAP_LFE_CC
,
136 HDMI_AUD_SWAP_RLS_RRS
,
137 HDMI_AUD_SWAP_LR_STATUS
,
140 struct hdmi_audio_param
{
141 enum hdmi_audio_coding_type aud_codec
;
142 enum hdmi_audio_sample_size aud_sampe_size
;
143 enum hdmi_aud_input_type aud_input_type
;
144 enum hdmi_aud_i2s_fmt aud_i2s_fmt
;
145 enum hdmi_aud_mclk aud_mclk
;
146 enum hdmi_aud_channel_type aud_input_chan_type
;
147 struct hdmi_codec_params codec_params
;
151 struct drm_bridge bridge
;
152 struct drm_bridge
*next_bridge
;
153 struct drm_connector conn
;
156 struct device
*cec_dev
;
157 struct i2c_adapter
*ddc_adpt
;
158 struct clk
*clk
[MTK_HDMI_CLK_COUNT
];
159 struct drm_display_mode mode
;
167 struct regmap
*sys_regmap
;
168 unsigned int sys_offset
;
170 enum hdmi_colorspace csp
;
171 struct hdmi_audio_param aud_param
;
177 static inline struct mtk_hdmi
*hdmi_ctx_from_bridge(struct drm_bridge
*b
)
179 return container_of(b
, struct mtk_hdmi
, bridge
);
182 static inline struct mtk_hdmi
*hdmi_ctx_from_conn(struct drm_connector
*c
)
184 return container_of(c
, struct mtk_hdmi
, conn
);
187 static u32
mtk_hdmi_read(struct mtk_hdmi
*hdmi
, u32 offset
)
189 return readl(hdmi
->regs
+ offset
);
192 static void mtk_hdmi_write(struct mtk_hdmi
*hdmi
, u32 offset
, u32 val
)
194 writel(val
, hdmi
->regs
+ offset
);
197 static void mtk_hdmi_clear_bits(struct mtk_hdmi
*hdmi
, u32 offset
, u32 bits
)
199 void __iomem
*reg
= hdmi
->regs
+ offset
;
207 static void mtk_hdmi_set_bits(struct mtk_hdmi
*hdmi
, u32 offset
, u32 bits
)
209 void __iomem
*reg
= hdmi
->regs
+ offset
;
217 static void mtk_hdmi_mask(struct mtk_hdmi
*hdmi
, u32 offset
, u32 val
, u32 mask
)
219 void __iomem
*reg
= hdmi
->regs
+ offset
;
223 tmp
= (tmp
& ~mask
) | (val
& mask
);
227 static void mtk_hdmi_hw_vid_black(struct mtk_hdmi
*hdmi
, bool black
)
229 mtk_hdmi_mask(hdmi
, VIDEO_CFG_4
, black
? GEN_RGB
: NORMAL_PATH
,
233 static void mtk_hdmi_hw_make_reg_writable(struct mtk_hdmi
*hdmi
, bool enable
)
235 struct arm_smccc_res res
;
236 struct mtk_hdmi_phy
*hdmi_phy
= phy_get_drvdata(hdmi
->phy
);
239 * MT8173 HDMI hardware has an output control bit to enable/disable HDMI
240 * output. This bit can only be controlled in ARM supervisor mode.
241 * The ARM trusted firmware provides an API for the HDMI driver to set
242 * this control bit to enable HDMI output in supervisor mode.
244 if (hdmi_phy
->conf
&& hdmi_phy
->conf
->tz_disabled
)
245 regmap_update_bits(hdmi
->sys_regmap
,
246 hdmi
->sys_offset
+ HDMI_SYS_CFG20
,
247 0x80008005, enable
? 0x80000005 : 0x8000);
249 arm_smccc_smc(MTK_SIP_SET_AUTHORIZED_SECURE_REG
, 0x14000904,
250 0x80000000, 0, 0, 0, 0, 0, &res
);
252 regmap_update_bits(hdmi
->sys_regmap
, hdmi
->sys_offset
+ HDMI_SYS_CFG20
,
253 HDMI_PCLK_FREE_RUN
, enable
? HDMI_PCLK_FREE_RUN
: 0);
254 regmap_update_bits(hdmi
->sys_regmap
, hdmi
->sys_offset
+ HDMI_SYS_CFG1C
,
255 HDMI_ON
| ANLG_ON
, enable
? (HDMI_ON
| ANLG_ON
) : 0);
258 static void mtk_hdmi_hw_1p4_version_enable(struct mtk_hdmi
*hdmi
, bool enable
)
260 regmap_update_bits(hdmi
->sys_regmap
, hdmi
->sys_offset
+ HDMI_SYS_CFG20
,
261 HDMI2P0_EN
, enable
? 0 : HDMI2P0_EN
);
264 static void mtk_hdmi_hw_aud_mute(struct mtk_hdmi
*hdmi
)
266 mtk_hdmi_set_bits(hdmi
, GRL_AUDIO_CFG
, AUDIO_ZERO
);
269 static void mtk_hdmi_hw_aud_unmute(struct mtk_hdmi
*hdmi
)
271 mtk_hdmi_clear_bits(hdmi
, GRL_AUDIO_CFG
, AUDIO_ZERO
);
274 static void mtk_hdmi_hw_reset(struct mtk_hdmi
*hdmi
)
276 regmap_update_bits(hdmi
->sys_regmap
, hdmi
->sys_offset
+ HDMI_SYS_CFG1C
,
278 regmap_update_bits(hdmi
->sys_regmap
, hdmi
->sys_offset
+ HDMI_SYS_CFG1C
,
280 mtk_hdmi_clear_bits(hdmi
, GRL_CFG3
, CFG3_CONTROL_PACKET_DELAY
);
281 regmap_update_bits(hdmi
->sys_regmap
, hdmi
->sys_offset
+ HDMI_SYS_CFG1C
,
285 static void mtk_hdmi_hw_enable_notice(struct mtk_hdmi
*hdmi
, bool enable_notice
)
287 mtk_hdmi_mask(hdmi
, GRL_CFG2
, enable_notice
? CFG2_NOTICE_EN
: 0,
291 static void mtk_hdmi_hw_write_int_mask(struct mtk_hdmi
*hdmi
, u32 int_mask
)
293 mtk_hdmi_write(hdmi
, GRL_INT_MASK
, int_mask
);
296 static void mtk_hdmi_hw_enable_dvi_mode(struct mtk_hdmi
*hdmi
, bool enable
)
298 mtk_hdmi_mask(hdmi
, GRL_CFG1
, enable
? CFG1_DVI
: 0, CFG1_DVI
);
301 static void mtk_hdmi_hw_send_info_frame(struct mtk_hdmi
*hdmi
, u8
*buffer
,
304 u32 ctrl_reg
= GRL_CTRL
;
307 enum hdmi_infoframe_type frame_type
;
311 int ctrl_frame_en
= 0;
313 frame_type
= *buffer
;
324 "frame_type:0x%x,frame_ver:0x%x,frame_len:0x%x,checksum:0x%x\n",
325 frame_type
, frame_ver
, frame_len
, checksum
);
327 switch (frame_type
) {
328 case HDMI_INFOFRAME_TYPE_AVI
:
329 ctrl_frame_en
= CTRL_AVI_EN
;
332 case HDMI_INFOFRAME_TYPE_SPD
:
333 ctrl_frame_en
= CTRL_SPD_EN
;
336 case HDMI_INFOFRAME_TYPE_AUDIO
:
337 ctrl_frame_en
= CTRL_AUDIO_EN
;
340 case HDMI_INFOFRAME_TYPE_VENDOR
:
341 ctrl_frame_en
= VS_EN
;
342 ctrl_reg
= GRL_ACP_ISRC_CTRL
;
345 mtk_hdmi_clear_bits(hdmi
, ctrl_reg
, ctrl_frame_en
);
346 mtk_hdmi_write(hdmi
, GRL_INFOFRM_TYPE
, frame_type
);
347 mtk_hdmi_write(hdmi
, GRL_INFOFRM_VER
, frame_ver
);
348 mtk_hdmi_write(hdmi
, GRL_INFOFRM_LNG
, frame_len
);
350 mtk_hdmi_write(hdmi
, GRL_IFM_PORT
, checksum
);
351 for (i
= 0; i
< frame_len
; i
++)
352 mtk_hdmi_write(hdmi
, GRL_IFM_PORT
, frame_data
[i
]);
354 mtk_hdmi_set_bits(hdmi
, ctrl_reg
, ctrl_frame_en
);
357 static void mtk_hdmi_hw_send_aud_packet(struct mtk_hdmi
*hdmi
, bool enable
)
359 mtk_hdmi_mask(hdmi
, GRL_SHIFT_R2
, enable
? 0 : AUDIO_PACKET_OFF
,
363 static void mtk_hdmi_hw_config_sys(struct mtk_hdmi
*hdmi
)
365 regmap_update_bits(hdmi
->sys_regmap
, hdmi
->sys_offset
+ HDMI_SYS_CFG20
,
366 HDMI_OUT_FIFO_EN
| MHL_MODE_ON
, 0);
367 usleep_range(2000, 4000);
368 regmap_update_bits(hdmi
->sys_regmap
, hdmi
->sys_offset
+ HDMI_SYS_CFG20
,
369 HDMI_OUT_FIFO_EN
| MHL_MODE_ON
, HDMI_OUT_FIFO_EN
);
372 static void mtk_hdmi_hw_set_deep_color_mode(struct mtk_hdmi
*hdmi
)
374 regmap_update_bits(hdmi
->sys_regmap
, hdmi
->sys_offset
+ HDMI_SYS_CFG20
,
375 DEEP_COLOR_MODE_MASK
| DEEP_COLOR_EN
,
379 static void mtk_hdmi_hw_send_av_mute(struct mtk_hdmi
*hdmi
)
381 mtk_hdmi_clear_bits(hdmi
, GRL_CFG4
, CTRL_AVMUTE
);
382 usleep_range(2000, 4000);
383 mtk_hdmi_set_bits(hdmi
, GRL_CFG4
, CTRL_AVMUTE
);
386 static void mtk_hdmi_hw_send_av_unmute(struct mtk_hdmi
*hdmi
)
388 mtk_hdmi_mask(hdmi
, GRL_CFG4
, CFG4_AV_UNMUTE_EN
,
389 CFG4_AV_UNMUTE_EN
| CFG4_AV_UNMUTE_SET
);
390 usleep_range(2000, 4000);
391 mtk_hdmi_mask(hdmi
, GRL_CFG4
, CFG4_AV_UNMUTE_SET
,
392 CFG4_AV_UNMUTE_EN
| CFG4_AV_UNMUTE_SET
);
395 static void mtk_hdmi_hw_ncts_enable(struct mtk_hdmi
*hdmi
, bool on
)
397 mtk_hdmi_mask(hdmi
, GRL_CTS_CTRL
, on
? 0 : CTS_CTRL_SOFT
,
401 static void mtk_hdmi_hw_ncts_auto_write_enable(struct mtk_hdmi
*hdmi
,
404 mtk_hdmi_mask(hdmi
, GRL_CTS_CTRL
, enable
? NCTS_WRI_ANYTIME
: 0,
408 static void mtk_hdmi_hw_msic_setting(struct mtk_hdmi
*hdmi
,
409 struct drm_display_mode
*mode
)
411 mtk_hdmi_clear_bits(hdmi
, GRL_CFG4
, CFG4_MHL_MODE
);
413 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
&&
414 mode
->clock
== 74250 &&
415 mode
->vdisplay
== 1080)
416 mtk_hdmi_clear_bits(hdmi
, GRL_CFG2
, CFG2_MHL_DE_SEL
);
418 mtk_hdmi_set_bits(hdmi
, GRL_CFG2
, CFG2_MHL_DE_SEL
);
421 static void mtk_hdmi_hw_aud_set_channel_swap(struct mtk_hdmi
*hdmi
,
422 enum hdmi_aud_channel_swap_type swap
)
427 case HDMI_AUD_SWAP_LR
:
430 case HDMI_AUD_SWAP_LFE_CC
:
431 swap_bit
= LFE_CC_SWAP
;
433 case HDMI_AUD_SWAP_LSRS
:
434 swap_bit
= LSRS_SWAP
;
436 case HDMI_AUD_SWAP_RLS_RRS
:
437 swap_bit
= RLS_RRS_SWAP
;
439 case HDMI_AUD_SWAP_LR_STATUS
:
440 swap_bit
= LR_STATUS_SWAP
;
443 swap_bit
= LFE_CC_SWAP
;
446 mtk_hdmi_mask(hdmi
, GRL_CH_SWAP
, swap_bit
, 0xff);
449 static void mtk_hdmi_hw_aud_set_bit_num(struct mtk_hdmi
*hdmi
,
450 enum hdmi_audio_sample_size bit_num
)
455 case HDMI_AUDIO_SAMPLE_SIZE_16
:
458 case HDMI_AUDIO_SAMPLE_SIZE_20
:
461 case HDMI_AUDIO_SAMPLE_SIZE_24
:
462 case HDMI_AUDIO_SAMPLE_SIZE_STREAM
:
467 mtk_hdmi_mask(hdmi
, GRL_AOUT_CFG
, val
, AOUT_BNUM_SEL_MASK
);
470 static void mtk_hdmi_hw_aud_set_i2s_fmt(struct mtk_hdmi
*hdmi
,
471 enum hdmi_aud_i2s_fmt i2s_fmt
)
475 val
= mtk_hdmi_read(hdmi
, GRL_CFG0
);
476 val
&= ~(CFG0_W_LENGTH_MASK
| CFG0_I2S_MODE_MASK
);
479 case HDMI_I2S_MODE_RJT_24BIT
:
480 val
|= CFG0_I2S_MODE_RTJ
| CFG0_W_LENGTH_24BIT
;
482 case HDMI_I2S_MODE_RJT_16BIT
:
483 val
|= CFG0_I2S_MODE_RTJ
| CFG0_W_LENGTH_16BIT
;
485 case HDMI_I2S_MODE_LJT_24BIT
:
487 val
|= CFG0_I2S_MODE_LTJ
| CFG0_W_LENGTH_24BIT
;
489 case HDMI_I2S_MODE_LJT_16BIT
:
490 val
|= CFG0_I2S_MODE_LTJ
| CFG0_W_LENGTH_16BIT
;
492 case HDMI_I2S_MODE_I2S_24BIT
:
493 val
|= CFG0_I2S_MODE_I2S
| CFG0_W_LENGTH_24BIT
;
495 case HDMI_I2S_MODE_I2S_16BIT
:
496 val
|= CFG0_I2S_MODE_I2S
| CFG0_W_LENGTH_16BIT
;
499 mtk_hdmi_write(hdmi
, GRL_CFG0
, val
);
502 static void mtk_hdmi_hw_audio_config(struct mtk_hdmi
*hdmi
, bool dst
)
504 const u8 mask
= HIGH_BIT_RATE
| DST_NORMAL_DOUBLE
| SACD_DST
| DSD_SEL
;
507 /* Disable high bitrate, set DST packet normal/double */
508 mtk_hdmi_clear_bits(hdmi
, GRL_AOUT_CFG
, HIGH_BIT_RATE_PACKET_ALIGN
);
511 val
= DST_NORMAL_DOUBLE
| SACD_DST
;
515 mtk_hdmi_mask(hdmi
, GRL_AUDIO_CFG
, val
, mask
);
518 static void mtk_hdmi_hw_aud_set_i2s_chan_num(struct mtk_hdmi
*hdmi
,
519 enum hdmi_aud_channel_type channel_type
,
522 unsigned int ch_switch
;
525 ch_switch
= CH_SWITCH(7, 7) | CH_SWITCH(6, 6) |
526 CH_SWITCH(5, 5) | CH_SWITCH(4, 4) |
527 CH_SWITCH(3, 3) | CH_SWITCH(1, 2) |
528 CH_SWITCH(2, 1) | CH_SWITCH(0, 0);
530 if (channel_count
== 2) {
531 i2s_uv
= I2S_UV_CH_EN(0);
532 } else if (channel_count
== 3 || channel_count
== 4) {
533 if (channel_count
== 4 &&
534 (channel_type
== HDMI_AUD_CHAN_TYPE_3_0_LRS
||
535 channel_type
== HDMI_AUD_CHAN_TYPE_4_0
))
536 i2s_uv
= I2S_UV_CH_EN(2) | I2S_UV_CH_EN(0);
538 i2s_uv
= I2S_UV_CH_EN(3) | I2S_UV_CH_EN(2);
539 } else if (channel_count
== 6 || channel_count
== 5) {
540 if (channel_count
== 6 &&
541 channel_type
!= HDMI_AUD_CHAN_TYPE_5_1
&&
542 channel_type
!= HDMI_AUD_CHAN_TYPE_4_1_CLRS
) {
543 i2s_uv
= I2S_UV_CH_EN(3) | I2S_UV_CH_EN(2) |
544 I2S_UV_CH_EN(1) | I2S_UV_CH_EN(0);
546 i2s_uv
= I2S_UV_CH_EN(2) | I2S_UV_CH_EN(1) |
549 } else if (channel_count
== 8 || channel_count
== 7) {
550 i2s_uv
= I2S_UV_CH_EN(3) | I2S_UV_CH_EN(2) |
551 I2S_UV_CH_EN(1) | I2S_UV_CH_EN(0);
553 i2s_uv
= I2S_UV_CH_EN(0);
556 mtk_hdmi_write(hdmi
, GRL_CH_SW0
, ch_switch
& 0xff);
557 mtk_hdmi_write(hdmi
, GRL_CH_SW1
, (ch_switch
>> 8) & 0xff);
558 mtk_hdmi_write(hdmi
, GRL_CH_SW2
, (ch_switch
>> 16) & 0xff);
559 mtk_hdmi_write(hdmi
, GRL_I2S_UV
, i2s_uv
);
562 static void mtk_hdmi_hw_aud_set_input_type(struct mtk_hdmi
*hdmi
,
563 enum hdmi_aud_input_type input_type
)
567 val
= mtk_hdmi_read(hdmi
, GRL_CFG1
);
568 if (input_type
== HDMI_AUD_INPUT_I2S
&&
569 (val
& CFG1_SPDIF
) == CFG1_SPDIF
) {
571 } else if (input_type
== HDMI_AUD_INPUT_SPDIF
&&
572 (val
& CFG1_SPDIF
) == 0) {
575 mtk_hdmi_write(hdmi
, GRL_CFG1
, val
);
578 static void mtk_hdmi_hw_aud_set_channel_status(struct mtk_hdmi
*hdmi
,
583 for (i
= 0; i
< 5; i
++) {
584 mtk_hdmi_write(hdmi
, GRL_I2S_C_STA0
+ i
* 4, channel_status
[i
]);
585 mtk_hdmi_write(hdmi
, GRL_L_STATUS_0
+ i
* 4, channel_status
[i
]);
586 mtk_hdmi_write(hdmi
, GRL_R_STATUS_0
+ i
* 4, channel_status
[i
]);
588 for (; i
< 24; i
++) {
589 mtk_hdmi_write(hdmi
, GRL_L_STATUS_0
+ i
* 4, 0);
590 mtk_hdmi_write(hdmi
, GRL_R_STATUS_0
+ i
* 4, 0);
594 static void mtk_hdmi_hw_aud_src_reenable(struct mtk_hdmi
*hdmi
)
598 val
= mtk_hdmi_read(hdmi
, GRL_MIX_CTRL
);
599 if (val
& MIX_CTRL_SRC_EN
) {
600 val
&= ~MIX_CTRL_SRC_EN
;
601 mtk_hdmi_write(hdmi
, GRL_MIX_CTRL
, val
);
602 usleep_range(255, 512);
603 val
|= MIX_CTRL_SRC_EN
;
604 mtk_hdmi_write(hdmi
, GRL_MIX_CTRL
, val
);
608 static void mtk_hdmi_hw_aud_src_disable(struct mtk_hdmi
*hdmi
)
612 val
= mtk_hdmi_read(hdmi
, GRL_MIX_CTRL
);
613 val
&= ~MIX_CTRL_SRC_EN
;
614 mtk_hdmi_write(hdmi
, GRL_MIX_CTRL
, val
);
615 mtk_hdmi_write(hdmi
, GRL_SHIFT_L1
, 0x00);
618 static void mtk_hdmi_hw_aud_set_mclk(struct mtk_hdmi
*hdmi
,
619 enum hdmi_aud_mclk mclk
)
623 val
= mtk_hdmi_read(hdmi
, GRL_CFG5
);
624 val
&= CFG5_CD_RATIO_MASK
;
627 case HDMI_AUD_MCLK_128FS
:
630 case HDMI_AUD_MCLK_256FS
:
633 case HDMI_AUD_MCLK_384FS
:
636 case HDMI_AUD_MCLK_512FS
:
639 case HDMI_AUD_MCLK_768FS
:
646 mtk_hdmi_write(hdmi
, GRL_CFG5
, val
);
654 /* Recommended N values from HDMI specification, tables 7-1 to 7-3 */
655 static const struct hdmi_acr_n hdmi_rec_n_table
[] = {
656 /* Clock, N: 32kHz 44.1kHz 48kHz */
657 { 25175, { 4576, 7007, 6864 } },
658 { 74176, { 11648, 17836, 11648 } },
659 { 148352, { 11648, 8918, 5824 } },
660 { 296703, { 5824, 4459, 5824 } },
661 { 297000, { 3072, 4704, 5120 } },
662 { 0, { 4096, 6272, 6144 } }, /* all other TMDS clocks */
666 * hdmi_recommended_n() - Return N value recommended by HDMI specification
667 * @freq: audio sample rate in Hz
668 * @clock: rounded TMDS clock in kHz
670 static unsigned int hdmi_recommended_n(unsigned int freq
, unsigned int clock
)
672 const struct hdmi_acr_n
*recommended
;
675 for (i
= 0; i
< ARRAY_SIZE(hdmi_rec_n_table
) - 1; i
++) {
676 if (clock
== hdmi_rec_n_table
[i
].clock
)
679 recommended
= hdmi_rec_n_table
+ i
;
683 return recommended
->n
[0];
685 return recommended
->n
[1];
687 return recommended
->n
[2];
689 return recommended
->n
[1] * 2;
691 return recommended
->n
[2] * 2;
693 return recommended
->n
[1] * 4;
695 return recommended
->n
[2] * 4;
697 return (128 * freq
) / 1000;
701 static unsigned int hdmi_mode_clock_to_hz(unsigned int clock
)
705 return 25174825; /* 25.2/1.001 MHz */
707 return 74175824; /* 74.25/1.001 MHz */
709 return 148351648; /* 148.5/1.001 MHz */
711 return 296703297; /* 297/1.001 MHz */
717 static unsigned int hdmi_expected_cts(unsigned int audio_sample_rate
,
718 unsigned int tmds_clock
, unsigned int n
)
720 return DIV_ROUND_CLOSEST_ULL((u64
)hdmi_mode_clock_to_hz(tmds_clock
) * n
,
721 128 * audio_sample_rate
);
724 static void do_hdmi_hw_aud_set_ncts(struct mtk_hdmi
*hdmi
, unsigned int n
,
727 unsigned char val
[NCTS_BYTES
];
730 mtk_hdmi_write(hdmi
, GRL_NCTS
, 0);
731 mtk_hdmi_write(hdmi
, GRL_NCTS
, 0);
732 mtk_hdmi_write(hdmi
, GRL_NCTS
, 0);
733 memset(val
, 0, sizeof(val
));
735 val
[0] = (cts
>> 24) & 0xff;
736 val
[1] = (cts
>> 16) & 0xff;
737 val
[2] = (cts
>> 8) & 0xff;
740 val
[4] = (n
>> 16) & 0xff;
741 val
[5] = (n
>> 8) & 0xff;
744 for (i
= 0; i
< NCTS_BYTES
; i
++)
745 mtk_hdmi_write(hdmi
, GRL_NCTS
, val
[i
]);
748 static void mtk_hdmi_hw_aud_set_ncts(struct mtk_hdmi
*hdmi
,
749 unsigned int sample_rate
,
754 n
= hdmi_recommended_n(sample_rate
, clock
);
755 cts
= hdmi_expected_cts(sample_rate
, clock
, n
);
757 dev_dbg(hdmi
->dev
, "%s: sample_rate=%u, clock=%d, cts=%u, n=%u\n",
758 __func__
, sample_rate
, clock
, n
, cts
);
760 mtk_hdmi_mask(hdmi
, DUMMY_304
, AUDIO_I2S_NCTS_SEL_64
,
762 do_hdmi_hw_aud_set_ncts(hdmi
, n
, cts
);
765 static u8
mtk_hdmi_aud_get_chnl_count(enum hdmi_aud_channel_type channel_type
)
767 switch (channel_type
) {
768 case HDMI_AUD_CHAN_TYPE_1_0
:
769 case HDMI_AUD_CHAN_TYPE_1_1
:
770 case HDMI_AUD_CHAN_TYPE_2_0
:
772 case HDMI_AUD_CHAN_TYPE_2_1
:
773 case HDMI_AUD_CHAN_TYPE_3_0
:
775 case HDMI_AUD_CHAN_TYPE_3_1
:
776 case HDMI_AUD_CHAN_TYPE_4_0
:
777 case HDMI_AUD_CHAN_TYPE_3_0_LRS
:
779 case HDMI_AUD_CHAN_TYPE_4_1
:
780 case HDMI_AUD_CHAN_TYPE_5_0
:
781 case HDMI_AUD_CHAN_TYPE_3_1_LRS
:
782 case HDMI_AUD_CHAN_TYPE_4_0_CLRS
:
784 case HDMI_AUD_CHAN_TYPE_5_1
:
785 case HDMI_AUD_CHAN_TYPE_6_0
:
786 case HDMI_AUD_CHAN_TYPE_4_1_CLRS
:
787 case HDMI_AUD_CHAN_TYPE_6_0_CS
:
788 case HDMI_AUD_CHAN_TYPE_6_0_CH
:
789 case HDMI_AUD_CHAN_TYPE_6_0_OH
:
790 case HDMI_AUD_CHAN_TYPE_6_0_CHR
:
792 case HDMI_AUD_CHAN_TYPE_6_1
:
793 case HDMI_AUD_CHAN_TYPE_6_1_CS
:
794 case HDMI_AUD_CHAN_TYPE_6_1_CH
:
795 case HDMI_AUD_CHAN_TYPE_6_1_OH
:
796 case HDMI_AUD_CHAN_TYPE_6_1_CHR
:
797 case HDMI_AUD_CHAN_TYPE_7_0
:
798 case HDMI_AUD_CHAN_TYPE_7_0_LH_RH
:
799 case HDMI_AUD_CHAN_TYPE_7_0_LSR_RSR
:
800 case HDMI_AUD_CHAN_TYPE_7_0_LC_RC
:
801 case HDMI_AUD_CHAN_TYPE_7_0_LW_RW
:
802 case HDMI_AUD_CHAN_TYPE_7_0_LSD_RSD
:
803 case HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS
:
804 case HDMI_AUD_CHAN_TYPE_7_0_LHS_RHS
:
805 case HDMI_AUD_CHAN_TYPE_7_0_CS_CH
:
806 case HDMI_AUD_CHAN_TYPE_7_0_CS_OH
:
807 case HDMI_AUD_CHAN_TYPE_7_0_CS_CHR
:
808 case HDMI_AUD_CHAN_TYPE_7_0_CH_OH
:
809 case HDMI_AUD_CHAN_TYPE_7_0_CH_CHR
:
810 case HDMI_AUD_CHAN_TYPE_7_0_OH_CHR
:
811 case HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS_LSR_RSR
:
812 case HDMI_AUD_CHAN_TYPE_8_0_LH_RH_CS
:
814 case HDMI_AUD_CHAN_TYPE_7_1
:
815 case HDMI_AUD_CHAN_TYPE_7_1_LH_RH
:
816 case HDMI_AUD_CHAN_TYPE_7_1_LSR_RSR
:
817 case HDMI_AUD_CHAN_TYPE_7_1_LC_RC
:
818 case HDMI_AUD_CHAN_TYPE_7_1_LW_RW
:
819 case HDMI_AUD_CHAN_TYPE_7_1_LSD_RSD
:
820 case HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS
:
821 case HDMI_AUD_CHAN_TYPE_7_1_LHS_RHS
:
822 case HDMI_AUD_CHAN_TYPE_7_1_CS_CH
:
823 case HDMI_AUD_CHAN_TYPE_7_1_CS_OH
:
824 case HDMI_AUD_CHAN_TYPE_7_1_CS_CHR
:
825 case HDMI_AUD_CHAN_TYPE_7_1_CH_OH
:
826 case HDMI_AUD_CHAN_TYPE_7_1_CH_CHR
:
827 case HDMI_AUD_CHAN_TYPE_7_1_OH_CHR
:
828 case HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS_LSR_RSR
:
835 static int mtk_hdmi_video_change_vpll(struct mtk_hdmi
*hdmi
, u32 clock
)
840 /* The DPI driver already should have set TVDPLL to the correct rate */
841 ret
= clk_set_rate(hdmi
->clk
[MTK_HDMI_CLK_HDMI_PLL
], clock
);
843 dev_err(hdmi
->dev
, "Failed to set PLL to %u Hz: %d\n", clock
,
848 rate
= clk_get_rate(hdmi
->clk
[MTK_HDMI_CLK_HDMI_PLL
]);
850 if (DIV_ROUND_CLOSEST(rate
, 1000) != DIV_ROUND_CLOSEST(clock
, 1000))
851 dev_warn(hdmi
->dev
, "Want PLL %u Hz, got %lu Hz\n", clock
,
854 dev_dbg(hdmi
->dev
, "Want PLL %u Hz, got %lu Hz\n", clock
, rate
);
856 mtk_hdmi_hw_config_sys(hdmi
);
857 mtk_hdmi_hw_set_deep_color_mode(hdmi
);
861 static void mtk_hdmi_video_set_display_mode(struct mtk_hdmi
*hdmi
,
862 struct drm_display_mode
*mode
)
864 mtk_hdmi_hw_reset(hdmi
);
865 mtk_hdmi_hw_enable_notice(hdmi
, true);
866 mtk_hdmi_hw_write_int_mask(hdmi
, 0xff);
867 mtk_hdmi_hw_enable_dvi_mode(hdmi
, hdmi
->dvi_mode
);
868 mtk_hdmi_hw_ncts_auto_write_enable(hdmi
, true);
870 mtk_hdmi_hw_msic_setting(hdmi
, mode
);
873 static int mtk_hdmi_aud_enable_packet(struct mtk_hdmi
*hdmi
, bool enable
)
875 mtk_hdmi_hw_send_aud_packet(hdmi
, enable
);
879 static int mtk_hdmi_aud_on_off_hw_ncts(struct mtk_hdmi
*hdmi
, bool on
)
881 mtk_hdmi_hw_ncts_enable(hdmi
, on
);
885 static int mtk_hdmi_aud_set_input(struct mtk_hdmi
*hdmi
)
887 enum hdmi_aud_channel_type chan_type
;
891 mtk_hdmi_hw_aud_set_channel_swap(hdmi
, HDMI_AUD_SWAP_LFE_CC
);
892 mtk_hdmi_set_bits(hdmi
, GRL_MIX_CTRL
, MIX_CTRL_FLAT
);
894 if (hdmi
->aud_param
.aud_input_type
== HDMI_AUD_INPUT_SPDIF
&&
895 hdmi
->aud_param
.aud_codec
== HDMI_AUDIO_CODING_TYPE_DST
) {
896 mtk_hdmi_hw_aud_set_bit_num(hdmi
, HDMI_AUDIO_SAMPLE_SIZE_24
);
897 } else if (hdmi
->aud_param
.aud_i2s_fmt
== HDMI_I2S_MODE_LJT_24BIT
) {
898 hdmi
->aud_param
.aud_i2s_fmt
= HDMI_I2S_MODE_LJT_16BIT
;
901 mtk_hdmi_hw_aud_set_i2s_fmt(hdmi
, hdmi
->aud_param
.aud_i2s_fmt
);
902 mtk_hdmi_hw_aud_set_bit_num(hdmi
, HDMI_AUDIO_SAMPLE_SIZE_24
);
904 dst
= ((hdmi
->aud_param
.aud_input_type
== HDMI_AUD_INPUT_SPDIF
) &&
905 (hdmi
->aud_param
.aud_codec
== HDMI_AUDIO_CODING_TYPE_DST
));
906 mtk_hdmi_hw_audio_config(hdmi
, dst
);
908 if (hdmi
->aud_param
.aud_input_type
== HDMI_AUD_INPUT_SPDIF
)
909 chan_type
= HDMI_AUD_CHAN_TYPE_2_0
;
911 chan_type
= hdmi
->aud_param
.aud_input_chan_type
;
912 chan_count
= mtk_hdmi_aud_get_chnl_count(chan_type
);
913 mtk_hdmi_hw_aud_set_i2s_chan_num(hdmi
, chan_type
, chan_count
);
914 mtk_hdmi_hw_aud_set_input_type(hdmi
, hdmi
->aud_param
.aud_input_type
);
919 static int mtk_hdmi_aud_set_src(struct mtk_hdmi
*hdmi
,
920 struct drm_display_mode
*display_mode
)
922 unsigned int sample_rate
= hdmi
->aud_param
.codec_params
.sample_rate
;
924 mtk_hdmi_aud_on_off_hw_ncts(hdmi
, false);
925 mtk_hdmi_hw_aud_src_disable(hdmi
);
926 mtk_hdmi_clear_bits(hdmi
, GRL_CFG2
, CFG2_ACLK_INV
);
928 if (hdmi
->aud_param
.aud_input_type
== HDMI_AUD_INPUT_I2S
) {
929 switch (sample_rate
) {
939 mtk_hdmi_hw_aud_set_mclk(hdmi
, hdmi
->aud_param
.aud_mclk
);
941 switch (sample_rate
) {
949 mtk_hdmi_hw_aud_set_mclk(hdmi
, HDMI_AUD_MCLK_128FS
);
952 mtk_hdmi_hw_aud_set_ncts(hdmi
, sample_rate
, display_mode
->clock
);
954 mtk_hdmi_hw_aud_src_reenable(hdmi
);
958 static int mtk_hdmi_aud_output_config(struct mtk_hdmi
*hdmi
,
959 struct drm_display_mode
*display_mode
)
961 mtk_hdmi_hw_aud_mute(hdmi
);
962 mtk_hdmi_aud_enable_packet(hdmi
, false);
964 mtk_hdmi_aud_set_input(hdmi
);
965 mtk_hdmi_aud_set_src(hdmi
, display_mode
);
966 mtk_hdmi_hw_aud_set_channel_status(hdmi
,
967 hdmi
->aud_param
.codec_params
.iec
.status
);
969 usleep_range(50, 100);
971 mtk_hdmi_aud_on_off_hw_ncts(hdmi
, true);
972 mtk_hdmi_aud_enable_packet(hdmi
, true);
973 mtk_hdmi_hw_aud_unmute(hdmi
);
977 static int mtk_hdmi_setup_avi_infoframe(struct mtk_hdmi
*hdmi
,
978 struct drm_display_mode
*mode
)
980 struct hdmi_avi_infoframe frame
;
984 err
= drm_hdmi_avi_infoframe_from_display_mode(&frame
, mode
, false);
987 "Failed to get AVI infoframe from mode: %zd\n", err
);
991 err
= hdmi_avi_infoframe_pack(&frame
, buffer
, sizeof(buffer
));
993 dev_err(hdmi
->dev
, "Failed to pack AVI infoframe: %zd\n", err
);
997 mtk_hdmi_hw_send_info_frame(hdmi
, buffer
, sizeof(buffer
));
1001 static int mtk_hdmi_setup_spd_infoframe(struct mtk_hdmi
*hdmi
,
1003 const char *product
)
1005 struct hdmi_spd_infoframe frame
;
1009 err
= hdmi_spd_infoframe_init(&frame
, vendor
, product
);
1011 dev_err(hdmi
->dev
, "Failed to initialize SPD infoframe: %zd\n",
1016 err
= hdmi_spd_infoframe_pack(&frame
, buffer
, sizeof(buffer
));
1018 dev_err(hdmi
->dev
, "Failed to pack SDP infoframe: %zd\n", err
);
1022 mtk_hdmi_hw_send_info_frame(hdmi
, buffer
, sizeof(buffer
));
1026 static int mtk_hdmi_setup_audio_infoframe(struct mtk_hdmi
*hdmi
)
1028 struct hdmi_audio_infoframe frame
;
1032 err
= hdmi_audio_infoframe_init(&frame
);
1034 dev_err(hdmi
->dev
, "Failed to setup audio infoframe: %zd\n",
1039 frame
.coding_type
= HDMI_AUDIO_CODING_TYPE_STREAM
;
1040 frame
.sample_frequency
= HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM
;
1041 frame
.sample_size
= HDMI_AUDIO_SAMPLE_SIZE_STREAM
;
1042 frame
.channels
= mtk_hdmi_aud_get_chnl_count(
1043 hdmi
->aud_param
.aud_input_chan_type
);
1045 err
= hdmi_audio_infoframe_pack(&frame
, buffer
, sizeof(buffer
));
1047 dev_err(hdmi
->dev
, "Failed to pack audio infoframe: %zd\n",
1052 mtk_hdmi_hw_send_info_frame(hdmi
, buffer
, sizeof(buffer
));
1056 static int mtk_hdmi_setup_vendor_specific_infoframe(struct mtk_hdmi
*hdmi
,
1057 struct drm_display_mode
*mode
)
1059 struct hdmi_vendor_infoframe frame
;
1063 err
= drm_hdmi_vendor_infoframe_from_display_mode(&frame
,
1067 "Failed to get vendor infoframe from mode: %zd\n", err
);
1071 err
= hdmi_vendor_infoframe_pack(&frame
, buffer
, sizeof(buffer
));
1073 dev_err(hdmi
->dev
, "Failed to pack vendor infoframe: %zd\n",
1078 mtk_hdmi_hw_send_info_frame(hdmi
, buffer
, sizeof(buffer
));
1082 static int mtk_hdmi_output_init(struct mtk_hdmi
*hdmi
)
1084 struct hdmi_audio_param
*aud_param
= &hdmi
->aud_param
;
1086 hdmi
->csp
= HDMI_COLORSPACE_RGB
;
1087 aud_param
->aud_codec
= HDMI_AUDIO_CODING_TYPE_PCM
;
1088 aud_param
->aud_sampe_size
= HDMI_AUDIO_SAMPLE_SIZE_16
;
1089 aud_param
->aud_input_type
= HDMI_AUD_INPUT_I2S
;
1090 aud_param
->aud_i2s_fmt
= HDMI_I2S_MODE_I2S_24BIT
;
1091 aud_param
->aud_mclk
= HDMI_AUD_MCLK_128FS
;
1092 aud_param
->aud_input_chan_type
= HDMI_AUD_CHAN_TYPE_2_0
;
1097 static void mtk_hdmi_audio_enable(struct mtk_hdmi
*hdmi
)
1099 mtk_hdmi_aud_enable_packet(hdmi
, true);
1100 hdmi
->audio_enable
= true;
1103 static void mtk_hdmi_audio_disable(struct mtk_hdmi
*hdmi
)
1105 mtk_hdmi_aud_enable_packet(hdmi
, false);
1106 hdmi
->audio_enable
= false;
1109 static int mtk_hdmi_audio_set_param(struct mtk_hdmi
*hdmi
,
1110 struct hdmi_audio_param
*param
)
1112 if (!hdmi
->audio_enable
) {
1113 dev_err(hdmi
->dev
, "hdmi audio is in disable state!\n");
1116 dev_dbg(hdmi
->dev
, "codec:%d, input:%d, channel:%d, fs:%d\n",
1117 param
->aud_codec
, param
->aud_input_type
,
1118 param
->aud_input_chan_type
, param
->codec_params
.sample_rate
);
1119 memcpy(&hdmi
->aud_param
, param
, sizeof(*param
));
1120 return mtk_hdmi_aud_output_config(hdmi
, &hdmi
->mode
);
1123 static int mtk_hdmi_output_set_display_mode(struct mtk_hdmi
*hdmi
,
1124 struct drm_display_mode
*mode
)
1128 mtk_hdmi_hw_vid_black(hdmi
, true);
1129 mtk_hdmi_hw_aud_mute(hdmi
);
1130 mtk_hdmi_hw_send_av_mute(hdmi
);
1131 phy_power_off(hdmi
->phy
);
1133 ret
= mtk_hdmi_video_change_vpll(hdmi
,
1134 mode
->clock
* 1000);
1136 dev_err(hdmi
->dev
, "Failed to set vpll: %d\n", ret
);
1139 mtk_hdmi_video_set_display_mode(hdmi
, mode
);
1141 phy_power_on(hdmi
->phy
);
1142 mtk_hdmi_aud_output_config(hdmi
, mode
);
1144 mtk_hdmi_hw_vid_black(hdmi
, false);
1145 mtk_hdmi_hw_aud_unmute(hdmi
);
1146 mtk_hdmi_hw_send_av_unmute(hdmi
);
1151 static const char * const mtk_hdmi_clk_names
[MTK_HDMI_CLK_COUNT
] = {
1152 [MTK_HDMI_CLK_HDMI_PIXEL
] = "pixel",
1153 [MTK_HDMI_CLK_HDMI_PLL
] = "pll",
1154 [MTK_HDMI_CLK_AUD_BCLK
] = "bclk",
1155 [MTK_HDMI_CLK_AUD_SPDIF
] = "spdif",
1158 static int mtk_hdmi_get_all_clk(struct mtk_hdmi
*hdmi
,
1159 struct device_node
*np
)
1163 for (i
= 0; i
< ARRAY_SIZE(mtk_hdmi_clk_names
); i
++) {
1164 hdmi
->clk
[i
] = of_clk_get_by_name(np
,
1165 mtk_hdmi_clk_names
[i
]);
1166 if (IS_ERR(hdmi
->clk
[i
]))
1167 return PTR_ERR(hdmi
->clk
[i
]);
1172 static int mtk_hdmi_clk_enable_audio(struct mtk_hdmi
*hdmi
)
1176 ret
= clk_prepare_enable(hdmi
->clk
[MTK_HDMI_CLK_AUD_BCLK
]);
1180 ret
= clk_prepare_enable(hdmi
->clk
[MTK_HDMI_CLK_AUD_SPDIF
]);
1186 clk_disable_unprepare(hdmi
->clk
[MTK_HDMI_CLK_AUD_BCLK
]);
1190 static void mtk_hdmi_clk_disable_audio(struct mtk_hdmi
*hdmi
)
1192 clk_disable_unprepare(hdmi
->clk
[MTK_HDMI_CLK_AUD_BCLK
]);
1193 clk_disable_unprepare(hdmi
->clk
[MTK_HDMI_CLK_AUD_SPDIF
]);
1196 static enum drm_connector_status
hdmi_conn_detect(struct drm_connector
*conn
,
1199 struct mtk_hdmi
*hdmi
= hdmi_ctx_from_conn(conn
);
1201 return mtk_cec_hpd_high(hdmi
->cec_dev
) ?
1202 connector_status_connected
: connector_status_disconnected
;
1205 static void hdmi_conn_destroy(struct drm_connector
*conn
)
1207 struct mtk_hdmi
*hdmi
= hdmi_ctx_from_conn(conn
);
1209 mtk_cec_set_hpd_event(hdmi
->cec_dev
, NULL
, NULL
);
1211 drm_connector_cleanup(conn
);
1214 static int mtk_hdmi_conn_get_modes(struct drm_connector
*conn
)
1216 struct mtk_hdmi
*hdmi
= hdmi_ctx_from_conn(conn
);
1220 if (!hdmi
->ddc_adpt
)
1223 edid
= drm_get_edid(conn
, hdmi
->ddc_adpt
);
1227 hdmi
->dvi_mode
= !drm_detect_monitor_audio(edid
);
1229 drm_connector_update_edid_property(conn
, edid
);
1231 ret
= drm_add_edid_modes(conn
, edid
);
1236 static int mtk_hdmi_conn_mode_valid(struct drm_connector
*conn
,
1237 struct drm_display_mode
*mode
)
1239 struct mtk_hdmi
*hdmi
= hdmi_ctx_from_conn(conn
);
1241 dev_dbg(hdmi
->dev
, "xres=%d, yres=%d, refresh=%d, intl=%d clock=%d\n",
1242 mode
->hdisplay
, mode
->vdisplay
, mode
->vrefresh
,
1243 !!(mode
->flags
& DRM_MODE_FLAG_INTERLACE
), mode
->clock
* 1000);
1245 if (hdmi
->bridge
.next
) {
1246 struct drm_display_mode adjusted_mode
;
1248 drm_mode_copy(&adjusted_mode
, mode
);
1249 if (!drm_bridge_mode_fixup(hdmi
->bridge
.next
, mode
,
1254 if (mode
->clock
< 27000)
1255 return MODE_CLOCK_LOW
;
1256 if (mode
->clock
> 297000)
1257 return MODE_CLOCK_HIGH
;
1259 return drm_mode_validate_size(mode
, 0x1fff, 0x1fff);
1262 static struct drm_encoder
*mtk_hdmi_conn_best_enc(struct drm_connector
*conn
)
1264 struct mtk_hdmi
*hdmi
= hdmi_ctx_from_conn(conn
);
1266 return hdmi
->bridge
.encoder
;
1269 static const struct drm_connector_funcs mtk_hdmi_connector_funcs
= {
1270 .detect
= hdmi_conn_detect
,
1271 .fill_modes
= drm_helper_probe_single_connector_modes
,
1272 .destroy
= hdmi_conn_destroy
,
1273 .reset
= drm_atomic_helper_connector_reset
,
1274 .atomic_duplicate_state
= drm_atomic_helper_connector_duplicate_state
,
1275 .atomic_destroy_state
= drm_atomic_helper_connector_destroy_state
,
1278 static const struct drm_connector_helper_funcs
1279 mtk_hdmi_connector_helper_funcs
= {
1280 .get_modes
= mtk_hdmi_conn_get_modes
,
1281 .mode_valid
= mtk_hdmi_conn_mode_valid
,
1282 .best_encoder
= mtk_hdmi_conn_best_enc
,
1285 static void mtk_hdmi_hpd_event(bool hpd
, struct device
*dev
)
1287 struct mtk_hdmi
*hdmi
= dev_get_drvdata(dev
);
1289 if (hdmi
&& hdmi
->bridge
.encoder
&& hdmi
->bridge
.encoder
->dev
)
1290 drm_helper_hpd_irq_event(hdmi
->bridge
.encoder
->dev
);
1297 static int mtk_hdmi_bridge_attach(struct drm_bridge
*bridge
)
1299 struct mtk_hdmi
*hdmi
= hdmi_ctx_from_bridge(bridge
);
1302 ret
= drm_connector_init(bridge
->encoder
->dev
, &hdmi
->conn
,
1303 &mtk_hdmi_connector_funcs
,
1304 DRM_MODE_CONNECTOR_HDMIA
);
1306 dev_err(hdmi
->dev
, "Failed to initialize connector: %d\n", ret
);
1309 drm_connector_helper_add(&hdmi
->conn
, &mtk_hdmi_connector_helper_funcs
);
1311 hdmi
->conn
.polled
= DRM_CONNECTOR_POLL_HPD
;
1312 hdmi
->conn
.interlace_allowed
= true;
1313 hdmi
->conn
.doublescan_allowed
= false;
1315 ret
= drm_connector_attach_encoder(&hdmi
->conn
,
1319 "Failed to attach connector to encoder: %d\n", ret
);
1323 if (hdmi
->next_bridge
) {
1324 ret
= drm_bridge_attach(bridge
->encoder
, hdmi
->next_bridge
,
1328 "Failed to attach external bridge: %d\n", ret
);
1333 mtk_cec_set_hpd_event(hdmi
->cec_dev
, mtk_hdmi_hpd_event
, hdmi
->dev
);
1338 static bool mtk_hdmi_bridge_mode_fixup(struct drm_bridge
*bridge
,
1339 const struct drm_display_mode
*mode
,
1340 struct drm_display_mode
*adjusted_mode
)
1345 static void mtk_hdmi_bridge_disable(struct drm_bridge
*bridge
)
1347 struct mtk_hdmi
*hdmi
= hdmi_ctx_from_bridge(bridge
);
1352 phy_power_off(hdmi
->phy
);
1353 clk_disable_unprepare(hdmi
->clk
[MTK_HDMI_CLK_HDMI_PIXEL
]);
1354 clk_disable_unprepare(hdmi
->clk
[MTK_HDMI_CLK_HDMI_PLL
]);
1356 hdmi
->enabled
= false;
1359 static void mtk_hdmi_bridge_post_disable(struct drm_bridge
*bridge
)
1361 struct mtk_hdmi
*hdmi
= hdmi_ctx_from_bridge(bridge
);
1366 mtk_hdmi_hw_1p4_version_enable(hdmi
, true);
1367 mtk_hdmi_hw_make_reg_writable(hdmi
, false);
1369 hdmi
->powered
= false;
1372 static void mtk_hdmi_bridge_mode_set(struct drm_bridge
*bridge
,
1373 struct drm_display_mode
*mode
,
1374 struct drm_display_mode
*adjusted_mode
)
1376 struct mtk_hdmi
*hdmi
= hdmi_ctx_from_bridge(bridge
);
1378 dev_dbg(hdmi
->dev
, "cur info: name:%s, hdisplay:%d\n",
1379 adjusted_mode
->name
, adjusted_mode
->hdisplay
);
1380 dev_dbg(hdmi
->dev
, "hsync_start:%d,hsync_end:%d, htotal:%d",
1381 adjusted_mode
->hsync_start
, adjusted_mode
->hsync_end
,
1382 adjusted_mode
->htotal
);
1383 dev_dbg(hdmi
->dev
, "hskew:%d, vdisplay:%d\n",
1384 adjusted_mode
->hskew
, adjusted_mode
->vdisplay
);
1385 dev_dbg(hdmi
->dev
, "vsync_start:%d, vsync_end:%d, vtotal:%d",
1386 adjusted_mode
->vsync_start
, adjusted_mode
->vsync_end
,
1387 adjusted_mode
->vtotal
);
1388 dev_dbg(hdmi
->dev
, "vscan:%d, flag:%d\n",
1389 adjusted_mode
->vscan
, adjusted_mode
->flags
);
1391 drm_mode_copy(&hdmi
->mode
, adjusted_mode
);
1394 static void mtk_hdmi_bridge_pre_enable(struct drm_bridge
*bridge
)
1396 struct mtk_hdmi
*hdmi
= hdmi_ctx_from_bridge(bridge
);
1398 mtk_hdmi_hw_make_reg_writable(hdmi
, true);
1399 mtk_hdmi_hw_1p4_version_enable(hdmi
, true);
1401 hdmi
->powered
= true;
1404 static void mtk_hdmi_send_infoframe(struct mtk_hdmi
*hdmi
,
1405 struct drm_display_mode
*mode
)
1407 mtk_hdmi_setup_audio_infoframe(hdmi
);
1408 mtk_hdmi_setup_avi_infoframe(hdmi
, mode
);
1409 mtk_hdmi_setup_spd_infoframe(hdmi
, "mediatek", "On-chip HDMI");
1410 if (mode
->flags
& DRM_MODE_FLAG_3D_MASK
)
1411 mtk_hdmi_setup_vendor_specific_infoframe(hdmi
, mode
);
1414 static void mtk_hdmi_bridge_enable(struct drm_bridge
*bridge
)
1416 struct mtk_hdmi
*hdmi
= hdmi_ctx_from_bridge(bridge
);
1418 mtk_hdmi_output_set_display_mode(hdmi
, &hdmi
->mode
);
1419 clk_prepare_enable(hdmi
->clk
[MTK_HDMI_CLK_HDMI_PLL
]);
1420 clk_prepare_enable(hdmi
->clk
[MTK_HDMI_CLK_HDMI_PIXEL
]);
1421 phy_power_on(hdmi
->phy
);
1422 mtk_hdmi_send_infoframe(hdmi
, &hdmi
->mode
);
1424 hdmi
->enabled
= true;
1427 static const struct drm_bridge_funcs mtk_hdmi_bridge_funcs
= {
1428 .attach
= mtk_hdmi_bridge_attach
,
1429 .mode_fixup
= mtk_hdmi_bridge_mode_fixup
,
1430 .disable
= mtk_hdmi_bridge_disable
,
1431 .post_disable
= mtk_hdmi_bridge_post_disable
,
1432 .mode_set
= mtk_hdmi_bridge_mode_set
,
1433 .pre_enable
= mtk_hdmi_bridge_pre_enable
,
1434 .enable
= mtk_hdmi_bridge_enable
,
1437 static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi
*hdmi
,
1438 struct platform_device
*pdev
)
1440 struct device
*dev
= &pdev
->dev
;
1441 struct device_node
*np
= dev
->of_node
;
1442 struct device_node
*cec_np
, *remote
, *i2c_np
;
1443 struct platform_device
*cec_pdev
;
1444 struct regmap
*regmap
;
1445 struct resource
*mem
;
1448 ret
= mtk_hdmi_get_all_clk(hdmi
, np
);
1450 dev_err(dev
, "Failed to get clocks: %d\n", ret
);
1454 /* The CEC module handles HDMI hotplug detection */
1455 cec_np
= of_get_compatible_child(np
->parent
, "mediatek,mt8173-cec");
1457 dev_err(dev
, "Failed to find CEC node\n");
1461 cec_pdev
= of_find_device_by_node(cec_np
);
1463 dev_err(hdmi
->dev
, "Waiting for CEC device %pOF\n",
1465 of_node_put(cec_np
);
1466 return -EPROBE_DEFER
;
1468 of_node_put(cec_np
);
1469 hdmi
->cec_dev
= &cec_pdev
->dev
;
1472 * The mediatek,syscon-hdmi property contains a phandle link to the
1473 * MMSYS_CONFIG device and the register offset of the HDMI_SYS_CFG
1474 * registers it contains.
1476 regmap
= syscon_regmap_lookup_by_phandle(np
, "mediatek,syscon-hdmi");
1477 ret
= of_property_read_u32_index(np
, "mediatek,syscon-hdmi", 1,
1480 ret
= PTR_ERR(regmap
);
1482 ret
= PTR_ERR(regmap
);
1484 "Failed to get system configuration registers: %d\n",
1488 hdmi
->sys_regmap
= regmap
;
1490 mem
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1491 hdmi
->regs
= devm_ioremap_resource(dev
, mem
);
1492 if (IS_ERR(hdmi
->regs
))
1493 return PTR_ERR(hdmi
->regs
);
1495 remote
= of_graph_get_remote_node(np
, 1, 0);
1499 if (!of_device_is_compatible(remote
, "hdmi-connector")) {
1500 hdmi
->next_bridge
= of_drm_find_bridge(remote
);
1501 if (!hdmi
->next_bridge
) {
1502 dev_err(dev
, "Waiting for external bridge\n");
1503 of_node_put(remote
);
1504 return -EPROBE_DEFER
;
1508 i2c_np
= of_parse_phandle(remote
, "ddc-i2c-bus", 0);
1510 dev_err(dev
, "Failed to find ddc-i2c-bus node in %pOF\n",
1512 of_node_put(remote
);
1515 of_node_put(remote
);
1517 hdmi
->ddc_adpt
= of_find_i2c_adapter_by_node(i2c_np
);
1518 if (!hdmi
->ddc_adpt
) {
1519 dev_err(dev
, "Failed to get ddc i2c adapter by node\n");
1527 * HDMI audio codec callbacks
1530 static int mtk_hdmi_audio_hw_params(struct device
*dev
, void *data
,
1531 struct hdmi_codec_daifmt
*daifmt
,
1532 struct hdmi_codec_params
*params
)
1534 struct mtk_hdmi
*hdmi
= dev_get_drvdata(dev
);
1535 struct hdmi_audio_param hdmi_params
;
1536 unsigned int chan
= params
->cea
.channels
;
1538 dev_dbg(hdmi
->dev
, "%s: %u Hz, %d bit, %d channels\n", __func__
,
1539 params
->sample_rate
, params
->sample_width
, chan
);
1541 if (!hdmi
->bridge
.encoder
)
1546 hdmi_params
.aud_input_chan_type
= HDMI_AUD_CHAN_TYPE_2_0
;
1549 hdmi_params
.aud_input_chan_type
= HDMI_AUD_CHAN_TYPE_4_0
;
1552 hdmi_params
.aud_input_chan_type
= HDMI_AUD_CHAN_TYPE_5_1
;
1555 hdmi_params
.aud_input_chan_type
= HDMI_AUD_CHAN_TYPE_7_1
;
1558 dev_err(hdmi
->dev
, "channel[%d] not supported!\n", chan
);
1562 switch (params
->sample_rate
) {
1572 dev_err(hdmi
->dev
, "rate[%d] not supported!\n",
1573 params
->sample_rate
);
1577 switch (daifmt
->fmt
) {
1579 hdmi_params
.aud_codec
= HDMI_AUDIO_CODING_TYPE_PCM
;
1580 hdmi_params
.aud_sampe_size
= HDMI_AUDIO_SAMPLE_SIZE_16
;
1581 hdmi_params
.aud_input_type
= HDMI_AUD_INPUT_I2S
;
1582 hdmi_params
.aud_i2s_fmt
= HDMI_I2S_MODE_I2S_24BIT
;
1583 hdmi_params
.aud_mclk
= HDMI_AUD_MCLK_128FS
;
1586 hdmi_params
.aud_codec
= HDMI_AUDIO_CODING_TYPE_PCM
;
1587 hdmi_params
.aud_sampe_size
= HDMI_AUDIO_SAMPLE_SIZE_16
;
1588 hdmi_params
.aud_input_type
= HDMI_AUD_INPUT_SPDIF
;
1591 dev_err(hdmi
->dev
, "%s: Invalid DAI format %d\n", __func__
,
1596 memcpy(&hdmi_params
.codec_params
, params
,
1597 sizeof(hdmi_params
.codec_params
));
1599 mtk_hdmi_audio_set_param(hdmi
, &hdmi_params
);
1604 static int mtk_hdmi_audio_startup(struct device
*dev
, void *data
)
1606 struct mtk_hdmi
*hdmi
= dev_get_drvdata(dev
);
1608 dev_dbg(dev
, "%s\n", __func__
);
1610 mtk_hdmi_audio_enable(hdmi
);
1615 static void mtk_hdmi_audio_shutdown(struct device
*dev
, void *data
)
1617 struct mtk_hdmi
*hdmi
= dev_get_drvdata(dev
);
1619 dev_dbg(dev
, "%s\n", __func__
);
1621 mtk_hdmi_audio_disable(hdmi
);
1625 mtk_hdmi_audio_digital_mute(struct device
*dev
, void *data
, bool enable
)
1627 struct mtk_hdmi
*hdmi
= dev_get_drvdata(dev
);
1629 dev_dbg(dev
, "%s(%d)\n", __func__
, enable
);
1632 mtk_hdmi_hw_aud_mute(hdmi
);
1634 mtk_hdmi_hw_aud_unmute(hdmi
);
1639 static int mtk_hdmi_audio_get_eld(struct device
*dev
, void *data
, uint8_t *buf
, size_t len
)
1641 struct mtk_hdmi
*hdmi
= dev_get_drvdata(dev
);
1643 dev_dbg(dev
, "%s\n", __func__
);
1645 memcpy(buf
, hdmi
->conn
.eld
, min(sizeof(hdmi
->conn
.eld
), len
));
1650 static const struct hdmi_codec_ops mtk_hdmi_audio_codec_ops
= {
1651 .hw_params
= mtk_hdmi_audio_hw_params
,
1652 .audio_startup
= mtk_hdmi_audio_startup
,
1653 .audio_shutdown
= mtk_hdmi_audio_shutdown
,
1654 .digital_mute
= mtk_hdmi_audio_digital_mute
,
1655 .get_eld
= mtk_hdmi_audio_get_eld
,
1658 static void mtk_hdmi_register_audio_driver(struct device
*dev
)
1660 struct hdmi_codec_pdata codec_data
= {
1661 .ops
= &mtk_hdmi_audio_codec_ops
,
1662 .max_i2s_channels
= 2,
1665 struct platform_device
*pdev
;
1667 pdev
= platform_device_register_data(dev
, HDMI_CODEC_DRV_NAME
,
1668 PLATFORM_DEVID_AUTO
, &codec_data
,
1669 sizeof(codec_data
));
1673 DRM_INFO("%s driver bound to HDMI\n", HDMI_CODEC_DRV_NAME
);
1676 static int mtk_drm_hdmi_probe(struct platform_device
*pdev
)
1678 struct mtk_hdmi
*hdmi
;
1679 struct device
*dev
= &pdev
->dev
;
1682 hdmi
= devm_kzalloc(dev
, sizeof(*hdmi
), GFP_KERNEL
);
1688 ret
= mtk_hdmi_dt_parse_pdata(hdmi
, pdev
);
1692 hdmi
->phy
= devm_phy_get(dev
, "hdmi");
1693 if (IS_ERR(hdmi
->phy
)) {
1694 ret
= PTR_ERR(hdmi
->phy
);
1695 dev_err(dev
, "Failed to get HDMI PHY: %d\n", ret
);
1699 platform_set_drvdata(pdev
, hdmi
);
1701 ret
= mtk_hdmi_output_init(hdmi
);
1703 dev_err(dev
, "Failed to initialize hdmi output\n");
1707 mtk_hdmi_register_audio_driver(dev
);
1709 hdmi
->bridge
.funcs
= &mtk_hdmi_bridge_funcs
;
1710 hdmi
->bridge
.of_node
= pdev
->dev
.of_node
;
1711 drm_bridge_add(&hdmi
->bridge
);
1713 ret
= mtk_hdmi_clk_enable_audio(hdmi
);
1715 dev_err(dev
, "Failed to enable audio clocks: %d\n", ret
);
1716 goto err_bridge_remove
;
1719 dev_dbg(dev
, "mediatek hdmi probe success\n");
1723 drm_bridge_remove(&hdmi
->bridge
);
1727 static int mtk_drm_hdmi_remove(struct platform_device
*pdev
)
1729 struct mtk_hdmi
*hdmi
= platform_get_drvdata(pdev
);
1731 drm_bridge_remove(&hdmi
->bridge
);
1732 mtk_hdmi_clk_disable_audio(hdmi
);
1736 #ifdef CONFIG_PM_SLEEP
1737 static int mtk_hdmi_suspend(struct device
*dev
)
1739 struct mtk_hdmi
*hdmi
= dev_get_drvdata(dev
);
1741 mtk_hdmi_clk_disable_audio(hdmi
);
1742 dev_dbg(dev
, "hdmi suspend success!\n");
1746 static int mtk_hdmi_resume(struct device
*dev
)
1748 struct mtk_hdmi
*hdmi
= dev_get_drvdata(dev
);
1751 ret
= mtk_hdmi_clk_enable_audio(hdmi
);
1753 dev_err(dev
, "hdmi resume failed!\n");
1757 dev_dbg(dev
, "hdmi resume success!\n");
1761 static SIMPLE_DEV_PM_OPS(mtk_hdmi_pm_ops
,
1762 mtk_hdmi_suspend
, mtk_hdmi_resume
);
1764 static const struct of_device_id mtk_drm_hdmi_of_ids
[] = {
1765 { .compatible
= "mediatek,mt8173-hdmi", },
1769 static struct platform_driver mtk_hdmi_driver
= {
1770 .probe
= mtk_drm_hdmi_probe
,
1771 .remove
= mtk_drm_hdmi_remove
,
1773 .name
= "mediatek-drm-hdmi",
1774 .of_match_table
= mtk_drm_hdmi_of_ids
,
1775 .pm
= &mtk_hdmi_pm_ops
,
1779 static struct platform_driver
* const mtk_hdmi_drivers
[] = {
1780 &mtk_hdmi_phy_driver
,
1781 &mtk_hdmi_ddc_driver
,
1786 static int __init
mtk_hdmitx_init(void)
1788 return platform_register_drivers(mtk_hdmi_drivers
,
1789 ARRAY_SIZE(mtk_hdmi_drivers
));
1792 static void __exit
mtk_hdmitx_exit(void)
1794 platform_unregister_drivers(mtk_hdmi_drivers
,
1795 ARRAY_SIZE(mtk_hdmi_drivers
));
1798 module_init(mtk_hdmitx_init
);
1799 module_exit(mtk_hdmitx_exit
);
1801 MODULE_AUTHOR("Jie Qiu <jie.qiu@mediatek.com>");
1802 MODULE_DESCRIPTION("MediaTek HDMI Driver");
1803 MODULE_LICENSE("GPL v2");