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[thirdparty/linux.git] / drivers / gpu / drm / msm / disp / dpu1 / dpu_encoder.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.
4 * Copyright (C) 2013 Red Hat
5 * Author: Rob Clark <robdclark@gmail.com>
6 */
7
8 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
9 #include <linux/kthread.h>
10 #include <linux/debugfs.h>
11 #include <linux/seq_file.h>
12
13 #include "msm_drv.h"
14 #include "dpu_kms.h"
15 #include <drm/drm_crtc.h>
16 #include <drm/drm_probe_helper.h>
17 #include "dpu_hwio.h"
18 #include "dpu_hw_catalog.h"
19 #include "dpu_hw_intf.h"
20 #include "dpu_hw_ctl.h"
21 #include "dpu_formats.h"
22 #include "dpu_encoder_phys.h"
23 #include "dpu_crtc.h"
24 #include "dpu_trace.h"
25 #include "dpu_core_irq.h"
26
27 #define DPU_DEBUG_ENC(e, fmt, ...) DPU_DEBUG("enc%d " fmt,\
28 (e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
29
30 #define DPU_ERROR_ENC(e, fmt, ...) DPU_ERROR("enc%d " fmt,\
31 (e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
32
33 #define DPU_DEBUG_PHYS(p, fmt, ...) DPU_DEBUG("enc%d intf%d pp%d " fmt,\
34 (p) ? (p)->parent->base.id : -1, \
35 (p) ? (p)->intf_idx - INTF_0 : -1, \
36 (p) ? ((p)->hw_pp ? (p)->hw_pp->idx - PINGPONG_0 : -1) : -1, \
37 ##__VA_ARGS__)
38
39 #define DPU_ERROR_PHYS(p, fmt, ...) DPU_ERROR("enc%d intf%d pp%d " fmt,\
40 (p) ? (p)->parent->base.id : -1, \
41 (p) ? (p)->intf_idx - INTF_0 : -1, \
42 (p) ? ((p)->hw_pp ? (p)->hw_pp->idx - PINGPONG_0 : -1) : -1, \
43 ##__VA_ARGS__)
44
45 /*
46 * Two to anticipate panels that can do cmd/vid dynamic switching
47 * plan is to create all possible physical encoder types, and switch between
48 * them at runtime
49 */
50 #define NUM_PHYS_ENCODER_TYPES 2
51
52 #define MAX_PHYS_ENCODERS_PER_VIRTUAL \
53 (MAX_H_TILES_PER_DISPLAY * NUM_PHYS_ENCODER_TYPES)
54
55 #define MAX_CHANNELS_PER_ENC 2
56
57 #define IDLE_SHORT_TIMEOUT 1
58
59 #define MAX_VDISPLAY_SPLIT 1080
60
61 /* timeout in frames waiting for frame done */
62 #define DPU_ENCODER_FRAME_DONE_TIMEOUT_FRAMES 5
63
64 /**
65 * enum dpu_enc_rc_events - events for resource control state machine
66 * @DPU_ENC_RC_EVENT_KICKOFF:
67 * This event happens at NORMAL priority.
68 * Event that signals the start of the transfer. When this event is
69 * received, enable MDP/DSI core clocks. Regardless of the previous
70 * state, the resource should be in ON state at the end of this event.
71 * @DPU_ENC_RC_EVENT_FRAME_DONE:
72 * This event happens at INTERRUPT level.
73 * Event signals the end of the data transfer after the PP FRAME_DONE
74 * event. At the end of this event, a delayed work is scheduled to go to
75 * IDLE_PC state after IDLE_TIMEOUT time.
76 * @DPU_ENC_RC_EVENT_PRE_STOP:
77 * This event happens at NORMAL priority.
78 * This event, when received during the ON state, leave the RC STATE
79 * in the PRE_OFF state. It should be followed by the STOP event as
80 * part of encoder disable.
81 * If received during IDLE or OFF states, it will do nothing.
82 * @DPU_ENC_RC_EVENT_STOP:
83 * This event happens at NORMAL priority.
84 * When this event is received, disable all the MDP/DSI core clocks, and
85 * disable IRQs. It should be called from the PRE_OFF or IDLE states.
86 * IDLE is expected when IDLE_PC has run, and PRE_OFF did nothing.
87 * PRE_OFF is expected when PRE_STOP was executed during the ON state.
88 * Resource state should be in OFF at the end of the event.
89 * @DPU_ENC_RC_EVENT_ENTER_IDLE:
90 * This event happens at NORMAL priority from a work item.
91 * Event signals that there were no frame updates for IDLE_TIMEOUT time.
92 * This would disable MDP/DSI core clocks and change the resource state
93 * to IDLE.
94 */
95 enum dpu_enc_rc_events {
96 DPU_ENC_RC_EVENT_KICKOFF = 1,
97 DPU_ENC_RC_EVENT_FRAME_DONE,
98 DPU_ENC_RC_EVENT_PRE_STOP,
99 DPU_ENC_RC_EVENT_STOP,
100 DPU_ENC_RC_EVENT_ENTER_IDLE
101 };
102
103 /*
104 * enum dpu_enc_rc_states - states that the resource control maintains
105 * @DPU_ENC_RC_STATE_OFF: Resource is in OFF state
106 * @DPU_ENC_RC_STATE_PRE_OFF: Resource is transitioning to OFF state
107 * @DPU_ENC_RC_STATE_ON: Resource is in ON state
108 * @DPU_ENC_RC_STATE_MODESET: Resource is in modeset state
109 * @DPU_ENC_RC_STATE_IDLE: Resource is in IDLE state
110 */
111 enum dpu_enc_rc_states {
112 DPU_ENC_RC_STATE_OFF,
113 DPU_ENC_RC_STATE_PRE_OFF,
114 DPU_ENC_RC_STATE_ON,
115 DPU_ENC_RC_STATE_IDLE
116 };
117
118 /**
119 * struct dpu_encoder_virt - virtual encoder. Container of one or more physical
120 * encoders. Virtual encoder manages one "logical" display. Physical
121 * encoders manage one intf block, tied to a specific panel/sub-panel.
122 * Virtual encoder defers as much as possible to the physical encoders.
123 * Virtual encoder registers itself with the DRM Framework as the encoder.
124 * @base: drm_encoder base class for registration with DRM
125 * @enc_spinlock: Virtual-Encoder-Wide Spin Lock for IRQ purposes
126 * @bus_scaling_client: Client handle to the bus scaling interface
127 * @enabled: True if the encoder is active, protected by enc_lock
128 * @num_phys_encs: Actual number of physical encoders contained.
129 * @phys_encs: Container of physical encoders managed.
130 * @cur_master: Pointer to the current master in this mode. Optimization
131 * Only valid after enable. Cleared as disable.
132 * @hw_pp Handle to the pingpong blocks used for the display. No.
133 * pingpong blocks can be different than num_phys_encs.
134 * @intfs_swapped Whether or not the phys_enc interfaces have been swapped
135 * for partial update right-only cases, such as pingpong
136 * split where virtual pingpong does not generate IRQs
137 * @crtc: Pointer to the currently assigned crtc. Normally you
138 * would use crtc->state->encoder_mask to determine the
139 * link between encoder/crtc. However in this case we need
140 * to track crtc in the disable() hook which is called
141 * _after_ encoder_mask is cleared.
142 * @crtc_kickoff_cb: Callback into CRTC that will flush & start
143 * all CTL paths
144 * @crtc_kickoff_cb_data: Opaque user data given to crtc_kickoff_cb
145 * @debugfs_root: Debug file system root file node
146 * @enc_lock: Lock around physical encoder
147 * create/destroy/enable/disable
148 * @frame_busy_mask: Bitmask tracking which phys_enc we are still
149 * busy processing current command.
150 * Bit0 = phys_encs[0] etc.
151 * @crtc_frame_event_cb: callback handler for frame event
152 * @crtc_frame_event_cb_data: callback handler private data
153 * @frame_done_timeout_ms: frame done timeout in ms
154 * @frame_done_timer: watchdog timer for frame done event
155 * @vsync_event_timer: vsync timer
156 * @disp_info: local copy of msm_display_info struct
157 * @idle_pc_supported: indicate if idle power collaps is supported
158 * @rc_lock: resource control mutex lock to protect
159 * virt encoder over various state changes
160 * @rc_state: resource controller state
161 * @delayed_off_work: delayed worker to schedule disabling of
162 * clks and resources after IDLE_TIMEOUT time.
163 * @vsync_event_work: worker to handle vsync event for autorefresh
164 * @topology: topology of the display
165 * @mode_set_complete: flag to indicate modeset completion
166 * @idle_timeout: idle timeout duration in milliseconds
167 */
168 struct dpu_encoder_virt {
169 struct drm_encoder base;
170 spinlock_t enc_spinlock;
171 uint32_t bus_scaling_client;
172
173 bool enabled;
174
175 unsigned int num_phys_encs;
176 struct dpu_encoder_phys *phys_encs[MAX_PHYS_ENCODERS_PER_VIRTUAL];
177 struct dpu_encoder_phys *cur_master;
178 struct dpu_encoder_phys *cur_slave;
179 struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
180
181 bool intfs_swapped;
182
183 struct drm_crtc *crtc;
184
185 struct dentry *debugfs_root;
186 struct mutex enc_lock;
187 DECLARE_BITMAP(frame_busy_mask, MAX_PHYS_ENCODERS_PER_VIRTUAL);
188 void (*crtc_frame_event_cb)(void *, u32 event);
189 void *crtc_frame_event_cb_data;
190
191 atomic_t frame_done_timeout_ms;
192 struct timer_list frame_done_timer;
193 struct timer_list vsync_event_timer;
194
195 struct msm_display_info disp_info;
196
197 bool idle_pc_supported;
198 struct mutex rc_lock;
199 enum dpu_enc_rc_states rc_state;
200 struct delayed_work delayed_off_work;
201 struct kthread_work vsync_event_work;
202 struct msm_display_topology topology;
203 bool mode_set_complete;
204
205 u32 idle_timeout;
206 };
207
208 #define to_dpu_encoder_virt(x) container_of(x, struct dpu_encoder_virt, base)
209
210 void dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys *phys_enc,
211 enum dpu_intr_idx intr_idx)
212 {
213 DRM_ERROR("irq timeout id=%u, intf=%d, pp=%d, intr=%d\n",
214 DRMID(phys_enc->parent), phys_enc->intf_idx - INTF_0,
215 phys_enc->hw_pp->idx - PINGPONG_0, intr_idx);
216
217 if (phys_enc->parent_ops->handle_frame_done)
218 phys_enc->parent_ops->handle_frame_done(
219 phys_enc->parent, phys_enc,
220 DPU_ENCODER_FRAME_EVENT_ERROR);
221 }
222
223 static int dpu_encoder_helper_wait_event_timeout(int32_t drm_id,
224 int32_t hw_id, struct dpu_encoder_wait_info *info);
225
226 int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc,
227 enum dpu_intr_idx intr_idx,
228 struct dpu_encoder_wait_info *wait_info)
229 {
230 struct dpu_encoder_irq *irq;
231 u32 irq_status;
232 int ret;
233
234 if (!phys_enc || !wait_info || intr_idx >= INTR_IDX_MAX) {
235 DPU_ERROR("invalid params\n");
236 return -EINVAL;
237 }
238 irq = &phys_enc->irq[intr_idx];
239
240 /* note: do master / slave checking outside */
241
242 /* return EWOULDBLOCK since we know the wait isn't necessary */
243 if (phys_enc->enable_state == DPU_ENC_DISABLED) {
244 DRM_ERROR("encoder is disabled id=%u, intr=%d, hw=%d, irq=%d",
245 DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
246 irq->irq_idx);
247 return -EWOULDBLOCK;
248 }
249
250 if (irq->irq_idx < 0) {
251 DRM_DEBUG_KMS("skip irq wait id=%u, intr=%d, hw=%d, irq=%s",
252 DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
253 irq->name);
254 return 0;
255 }
256
257 DRM_DEBUG_KMS("id=%u, intr=%d, hw=%d, irq=%d, pp=%d, pending_cnt=%d",
258 DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
259 irq->irq_idx, phys_enc->hw_pp->idx - PINGPONG_0,
260 atomic_read(wait_info->atomic_cnt));
261
262 ret = dpu_encoder_helper_wait_event_timeout(
263 DRMID(phys_enc->parent),
264 irq->hw_idx,
265 wait_info);
266
267 if (ret <= 0) {
268 irq_status = dpu_core_irq_read(phys_enc->dpu_kms,
269 irq->irq_idx, true);
270 if (irq_status) {
271 unsigned long flags;
272
273 DRM_DEBUG_KMS("irq not triggered id=%u, intr=%d, "
274 "hw=%d, irq=%d, pp=%d, atomic_cnt=%d",
275 DRMID(phys_enc->parent), intr_idx,
276 irq->hw_idx, irq->irq_idx,
277 phys_enc->hw_pp->idx - PINGPONG_0,
278 atomic_read(wait_info->atomic_cnt));
279 local_irq_save(flags);
280 irq->cb.func(phys_enc, irq->irq_idx);
281 local_irq_restore(flags);
282 ret = 0;
283 } else {
284 ret = -ETIMEDOUT;
285 DRM_DEBUG_KMS("irq timeout id=%u, intr=%d, "
286 "hw=%d, irq=%d, pp=%d, atomic_cnt=%d",
287 DRMID(phys_enc->parent), intr_idx,
288 irq->hw_idx, irq->irq_idx,
289 phys_enc->hw_pp->idx - PINGPONG_0,
290 atomic_read(wait_info->atomic_cnt));
291 }
292 } else {
293 ret = 0;
294 trace_dpu_enc_irq_wait_success(DRMID(phys_enc->parent),
295 intr_idx, irq->hw_idx, irq->irq_idx,
296 phys_enc->hw_pp->idx - PINGPONG_0,
297 atomic_read(wait_info->atomic_cnt));
298 }
299
300 return ret;
301 }
302
303 int dpu_encoder_helper_register_irq(struct dpu_encoder_phys *phys_enc,
304 enum dpu_intr_idx intr_idx)
305 {
306 struct dpu_encoder_irq *irq;
307 int ret = 0;
308
309 if (!phys_enc || intr_idx >= INTR_IDX_MAX) {
310 DPU_ERROR("invalid params\n");
311 return -EINVAL;
312 }
313 irq = &phys_enc->irq[intr_idx];
314
315 if (irq->irq_idx >= 0) {
316 DPU_DEBUG_PHYS(phys_enc,
317 "skipping already registered irq %s type %d\n",
318 irq->name, irq->intr_type);
319 return 0;
320 }
321
322 irq->irq_idx = dpu_core_irq_idx_lookup(phys_enc->dpu_kms,
323 irq->intr_type, irq->hw_idx);
324 if (irq->irq_idx < 0) {
325 DPU_ERROR_PHYS(phys_enc,
326 "failed to lookup IRQ index for %s type:%d\n",
327 irq->name, irq->intr_type);
328 return -EINVAL;
329 }
330
331 ret = dpu_core_irq_register_callback(phys_enc->dpu_kms, irq->irq_idx,
332 &irq->cb);
333 if (ret) {
334 DPU_ERROR_PHYS(phys_enc,
335 "failed to register IRQ callback for %s\n",
336 irq->name);
337 irq->irq_idx = -EINVAL;
338 return ret;
339 }
340
341 ret = dpu_core_irq_enable(phys_enc->dpu_kms, &irq->irq_idx, 1);
342 if (ret) {
343 DRM_ERROR("enable failed id=%u, intr=%d, hw=%d, irq=%d",
344 DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
345 irq->irq_idx);
346 dpu_core_irq_unregister_callback(phys_enc->dpu_kms,
347 irq->irq_idx, &irq->cb);
348 irq->irq_idx = -EINVAL;
349 return ret;
350 }
351
352 trace_dpu_enc_irq_register_success(DRMID(phys_enc->parent), intr_idx,
353 irq->hw_idx, irq->irq_idx);
354
355 return ret;
356 }
357
358 int dpu_encoder_helper_unregister_irq(struct dpu_encoder_phys *phys_enc,
359 enum dpu_intr_idx intr_idx)
360 {
361 struct dpu_encoder_irq *irq;
362 int ret;
363
364 if (!phys_enc) {
365 DPU_ERROR("invalid encoder\n");
366 return -EINVAL;
367 }
368 irq = &phys_enc->irq[intr_idx];
369
370 /* silently skip irqs that weren't registered */
371 if (irq->irq_idx < 0) {
372 DRM_ERROR("duplicate unregister id=%u, intr=%d, hw=%d, irq=%d",
373 DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
374 irq->irq_idx);
375 return 0;
376 }
377
378 ret = dpu_core_irq_disable(phys_enc->dpu_kms, &irq->irq_idx, 1);
379 if (ret) {
380 DRM_ERROR("disable failed id=%u, intr=%d, hw=%d, irq=%d ret=%d",
381 DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
382 irq->irq_idx, ret);
383 }
384
385 ret = dpu_core_irq_unregister_callback(phys_enc->dpu_kms, irq->irq_idx,
386 &irq->cb);
387 if (ret) {
388 DRM_ERROR("unreg cb fail id=%u, intr=%d, hw=%d, irq=%d ret=%d",
389 DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
390 irq->irq_idx, ret);
391 }
392
393 trace_dpu_enc_irq_unregister_success(DRMID(phys_enc->parent), intr_idx,
394 irq->hw_idx, irq->irq_idx);
395
396 irq->irq_idx = -EINVAL;
397
398 return 0;
399 }
400
401 void dpu_encoder_get_hw_resources(struct drm_encoder *drm_enc,
402 struct dpu_encoder_hw_resources *hw_res)
403 {
404 struct dpu_encoder_virt *dpu_enc = NULL;
405 int i = 0;
406
407 dpu_enc = to_dpu_encoder_virt(drm_enc);
408 DPU_DEBUG_ENC(dpu_enc, "\n");
409
410 /* Query resources used by phys encs, expected to be without overlap */
411 memset(hw_res, 0, sizeof(*hw_res));
412
413 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
414 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
415
416 if (phys && phys->ops.get_hw_resources)
417 phys->ops.get_hw_resources(phys, hw_res);
418 }
419 }
420
421 static void dpu_encoder_destroy(struct drm_encoder *drm_enc)
422 {
423 struct dpu_encoder_virt *dpu_enc = NULL;
424 int i = 0;
425
426 if (!drm_enc) {
427 DPU_ERROR("invalid encoder\n");
428 return;
429 }
430
431 dpu_enc = to_dpu_encoder_virt(drm_enc);
432 DPU_DEBUG_ENC(dpu_enc, "\n");
433
434 mutex_lock(&dpu_enc->enc_lock);
435
436 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
437 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
438
439 if (phys && phys->ops.destroy) {
440 phys->ops.destroy(phys);
441 --dpu_enc->num_phys_encs;
442 dpu_enc->phys_encs[i] = NULL;
443 }
444 }
445
446 if (dpu_enc->num_phys_encs)
447 DPU_ERROR_ENC(dpu_enc, "expected 0 num_phys_encs not %d\n",
448 dpu_enc->num_phys_encs);
449 dpu_enc->num_phys_encs = 0;
450 mutex_unlock(&dpu_enc->enc_lock);
451
452 drm_encoder_cleanup(drm_enc);
453 mutex_destroy(&dpu_enc->enc_lock);
454 }
455
456 void dpu_encoder_helper_split_config(
457 struct dpu_encoder_phys *phys_enc,
458 enum dpu_intf interface)
459 {
460 struct dpu_encoder_virt *dpu_enc;
461 struct split_pipe_cfg cfg = { 0 };
462 struct dpu_hw_mdp *hw_mdptop;
463 struct msm_display_info *disp_info;
464
465 if (!phys_enc || !phys_enc->hw_mdptop || !phys_enc->parent) {
466 DPU_ERROR("invalid arg(s), encoder %d\n", phys_enc != 0);
467 return;
468 }
469
470 dpu_enc = to_dpu_encoder_virt(phys_enc->parent);
471 hw_mdptop = phys_enc->hw_mdptop;
472 disp_info = &dpu_enc->disp_info;
473
474 if (disp_info->intf_type != DRM_MODE_ENCODER_DSI)
475 return;
476
477 /**
478 * disable split modes since encoder will be operating in as the only
479 * encoder, either for the entire use case in the case of, for example,
480 * single DSI, or for this frame in the case of left/right only partial
481 * update.
482 */
483 if (phys_enc->split_role == ENC_ROLE_SOLO) {
484 if (hw_mdptop->ops.setup_split_pipe)
485 hw_mdptop->ops.setup_split_pipe(hw_mdptop, &cfg);
486 return;
487 }
488
489 cfg.en = true;
490 cfg.mode = phys_enc->intf_mode;
491 cfg.intf = interface;
492
493 if (cfg.en && phys_enc->ops.needs_single_flush &&
494 phys_enc->ops.needs_single_flush(phys_enc))
495 cfg.split_flush_en = true;
496
497 if (phys_enc->split_role == ENC_ROLE_MASTER) {
498 DPU_DEBUG_ENC(dpu_enc, "enable %d\n", cfg.en);
499
500 if (hw_mdptop->ops.setup_split_pipe)
501 hw_mdptop->ops.setup_split_pipe(hw_mdptop, &cfg);
502 }
503 }
504
505 static void _dpu_encoder_adjust_mode(struct drm_connector *connector,
506 struct drm_display_mode *adj_mode)
507 {
508 struct drm_display_mode *cur_mode;
509
510 if (!connector || !adj_mode)
511 return;
512
513 list_for_each_entry(cur_mode, &connector->modes, head) {
514 if (cur_mode->vdisplay == adj_mode->vdisplay &&
515 cur_mode->hdisplay == adj_mode->hdisplay &&
516 drm_mode_vrefresh(cur_mode) == drm_mode_vrefresh(adj_mode)) {
517 adj_mode->private = cur_mode->private;
518 adj_mode->private_flags |= cur_mode->private_flags;
519 }
520 }
521 }
522
523 static struct msm_display_topology dpu_encoder_get_topology(
524 struct dpu_encoder_virt *dpu_enc,
525 struct dpu_kms *dpu_kms,
526 struct drm_display_mode *mode)
527 {
528 struct msm_display_topology topology;
529 int i, intf_count = 0;
530
531 for (i = 0; i < MAX_PHYS_ENCODERS_PER_VIRTUAL; i++)
532 if (dpu_enc->phys_encs[i])
533 intf_count++;
534
535 /* User split topology for width > 1080 */
536 topology.num_lm = (mode->vdisplay > MAX_VDISPLAY_SPLIT) ? 2 : 1;
537 topology.num_enc = 0;
538 topology.num_intf = intf_count;
539
540 return topology;
541 }
542 static int dpu_encoder_virt_atomic_check(
543 struct drm_encoder *drm_enc,
544 struct drm_crtc_state *crtc_state,
545 struct drm_connector_state *conn_state)
546 {
547 struct dpu_encoder_virt *dpu_enc;
548 struct msm_drm_private *priv;
549 struct dpu_kms *dpu_kms;
550 const struct drm_display_mode *mode;
551 struct drm_display_mode *adj_mode;
552 struct msm_display_topology topology;
553 int i = 0;
554 int ret = 0;
555
556 if (!drm_enc || !crtc_state || !conn_state) {
557 DPU_ERROR("invalid arg(s), drm_enc %d, crtc/conn state %d/%d\n",
558 drm_enc != 0, crtc_state != 0, conn_state != 0);
559 return -EINVAL;
560 }
561
562 dpu_enc = to_dpu_encoder_virt(drm_enc);
563 DPU_DEBUG_ENC(dpu_enc, "\n");
564
565 priv = drm_enc->dev->dev_private;
566 dpu_kms = to_dpu_kms(priv->kms);
567 mode = &crtc_state->mode;
568 adj_mode = &crtc_state->adjusted_mode;
569 trace_dpu_enc_atomic_check(DRMID(drm_enc));
570
571 /*
572 * display drivers may populate private fields of the drm display mode
573 * structure while registering possible modes of a connector with DRM.
574 * These private fields are not populated back while DRM invokes
575 * the mode_set callbacks. This module retrieves and populates the
576 * private fields of the given mode.
577 */
578 _dpu_encoder_adjust_mode(conn_state->connector, adj_mode);
579
580 /* perform atomic check on the first physical encoder (master) */
581 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
582 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
583
584 if (phys && phys->ops.atomic_check)
585 ret = phys->ops.atomic_check(phys, crtc_state,
586 conn_state);
587 else if (phys && phys->ops.mode_fixup)
588 if (!phys->ops.mode_fixup(phys, mode, adj_mode))
589 ret = -EINVAL;
590
591 if (ret) {
592 DPU_ERROR_ENC(dpu_enc,
593 "mode unsupported, phys idx %d\n", i);
594 break;
595 }
596 }
597
598 topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode);
599
600 /* Reserve dynamic resources now. Indicating AtomicTest phase */
601 if (!ret) {
602 /*
603 * Avoid reserving resources when mode set is pending. Topology
604 * info may not be available to complete reservation.
605 */
606 if (drm_atomic_crtc_needs_modeset(crtc_state)
607 && dpu_enc->mode_set_complete) {
608 ret = dpu_rm_reserve(&dpu_kms->rm, drm_enc, crtc_state,
609 topology, true);
610 dpu_enc->mode_set_complete = false;
611 }
612 }
613
614 if (!ret)
615 drm_mode_set_crtcinfo(adj_mode, 0);
616
617 trace_dpu_enc_atomic_check_flags(DRMID(drm_enc), adj_mode->flags,
618 adj_mode->private_flags);
619
620 return ret;
621 }
622
623 static void _dpu_encoder_update_vsync_source(struct dpu_encoder_virt *dpu_enc,
624 struct msm_display_info *disp_info)
625 {
626 struct dpu_vsync_source_cfg vsync_cfg = { 0 };
627 struct msm_drm_private *priv;
628 struct dpu_kms *dpu_kms;
629 struct dpu_hw_mdp *hw_mdptop;
630 struct drm_encoder *drm_enc;
631 int i;
632
633 if (!dpu_enc || !disp_info) {
634 DPU_ERROR("invalid param dpu_enc:%d or disp_info:%d\n",
635 dpu_enc != NULL, disp_info != NULL);
636 return;
637 } else if (dpu_enc->num_phys_encs > ARRAY_SIZE(dpu_enc->hw_pp)) {
638 DPU_ERROR("invalid num phys enc %d/%d\n",
639 dpu_enc->num_phys_encs,
640 (int) ARRAY_SIZE(dpu_enc->hw_pp));
641 return;
642 }
643
644 drm_enc = &dpu_enc->base;
645 /* this pointers are checked in virt_enable_helper */
646 priv = drm_enc->dev->dev_private;
647
648 dpu_kms = to_dpu_kms(priv->kms);
649 if (!dpu_kms) {
650 DPU_ERROR("invalid dpu_kms\n");
651 return;
652 }
653
654 hw_mdptop = dpu_kms->hw_mdp;
655 if (!hw_mdptop) {
656 DPU_ERROR("invalid mdptop\n");
657 return;
658 }
659
660 if (hw_mdptop->ops.setup_vsync_source &&
661 disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) {
662 for (i = 0; i < dpu_enc->num_phys_encs; i++)
663 vsync_cfg.ppnumber[i] = dpu_enc->hw_pp[i]->idx;
664
665 vsync_cfg.pp_count = dpu_enc->num_phys_encs;
666 if (disp_info->is_te_using_watchdog_timer)
667 vsync_cfg.vsync_source = DPU_VSYNC_SOURCE_WD_TIMER_0;
668 else
669 vsync_cfg.vsync_source = DPU_VSYNC0_SOURCE_GPIO;
670
671 hw_mdptop->ops.setup_vsync_source(hw_mdptop, &vsync_cfg);
672 }
673 }
674
675 static void _dpu_encoder_irq_control(struct drm_encoder *drm_enc, bool enable)
676 {
677 struct dpu_encoder_virt *dpu_enc;
678 int i;
679
680 if (!drm_enc) {
681 DPU_ERROR("invalid encoder\n");
682 return;
683 }
684
685 dpu_enc = to_dpu_encoder_virt(drm_enc);
686
687 DPU_DEBUG_ENC(dpu_enc, "enable:%d\n", enable);
688 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
689 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
690
691 if (phys && phys->ops.irq_control)
692 phys->ops.irq_control(phys, enable);
693 }
694
695 }
696
697 static void _dpu_encoder_resource_control_helper(struct drm_encoder *drm_enc,
698 bool enable)
699 {
700 struct msm_drm_private *priv;
701 struct dpu_kms *dpu_kms;
702 struct dpu_encoder_virt *dpu_enc;
703
704 dpu_enc = to_dpu_encoder_virt(drm_enc);
705 priv = drm_enc->dev->dev_private;
706 dpu_kms = to_dpu_kms(priv->kms);
707
708 trace_dpu_enc_rc_helper(DRMID(drm_enc), enable);
709
710 if (!dpu_enc->cur_master) {
711 DPU_ERROR("encoder master not set\n");
712 return;
713 }
714
715 if (enable) {
716 /* enable DPU core clks */
717 pm_runtime_get_sync(&dpu_kms->pdev->dev);
718
719 /* enable all the irq */
720 _dpu_encoder_irq_control(drm_enc, true);
721
722 } else {
723 /* disable all the irq */
724 _dpu_encoder_irq_control(drm_enc, false);
725
726 /* disable DPU core clks */
727 pm_runtime_put_sync(&dpu_kms->pdev->dev);
728 }
729
730 }
731
732 static int dpu_encoder_resource_control(struct drm_encoder *drm_enc,
733 u32 sw_event)
734 {
735 struct dpu_encoder_virt *dpu_enc;
736 struct msm_drm_private *priv;
737 bool is_vid_mode = false;
738
739 if (!drm_enc || !drm_enc->dev || !drm_enc->dev->dev_private ||
740 !drm_enc->crtc) {
741 DPU_ERROR("invalid parameters\n");
742 return -EINVAL;
743 }
744 dpu_enc = to_dpu_encoder_virt(drm_enc);
745 priv = drm_enc->dev->dev_private;
746 is_vid_mode = dpu_enc->disp_info.capabilities &
747 MSM_DISPLAY_CAP_VID_MODE;
748
749 /*
750 * when idle_pc is not supported, process only KICKOFF, STOP and MODESET
751 * events and return early for other events (ie wb display).
752 */
753 if (!dpu_enc->idle_pc_supported &&
754 (sw_event != DPU_ENC_RC_EVENT_KICKOFF &&
755 sw_event != DPU_ENC_RC_EVENT_STOP &&
756 sw_event != DPU_ENC_RC_EVENT_PRE_STOP))
757 return 0;
758
759 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, dpu_enc->idle_pc_supported,
760 dpu_enc->rc_state, "begin");
761
762 switch (sw_event) {
763 case DPU_ENC_RC_EVENT_KICKOFF:
764 /* cancel delayed off work, if any */
765 if (cancel_delayed_work_sync(&dpu_enc->delayed_off_work))
766 DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, work cancelled\n",
767 sw_event);
768
769 mutex_lock(&dpu_enc->rc_lock);
770
771 /* return if the resource control is already in ON state */
772 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_ON) {
773 DRM_DEBUG_KMS("id;%u, sw_event:%d, rc in ON state\n",
774 DRMID(drm_enc), sw_event);
775 mutex_unlock(&dpu_enc->rc_lock);
776 return 0;
777 } else if (dpu_enc->rc_state != DPU_ENC_RC_STATE_OFF &&
778 dpu_enc->rc_state != DPU_ENC_RC_STATE_IDLE) {
779 DRM_DEBUG_KMS("id;%u, sw_event:%d, rc in state %d\n",
780 DRMID(drm_enc), sw_event,
781 dpu_enc->rc_state);
782 mutex_unlock(&dpu_enc->rc_lock);
783 return -EINVAL;
784 }
785
786 if (is_vid_mode && dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE)
787 _dpu_encoder_irq_control(drm_enc, true);
788 else
789 _dpu_encoder_resource_control_helper(drm_enc, true);
790
791 dpu_enc->rc_state = DPU_ENC_RC_STATE_ON;
792
793 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
794 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
795 "kickoff");
796
797 mutex_unlock(&dpu_enc->rc_lock);
798 break;
799
800 case DPU_ENC_RC_EVENT_FRAME_DONE:
801 /*
802 * mutex lock is not used as this event happens at interrupt
803 * context. And locking is not required as, the other events
804 * like KICKOFF and STOP does a wait-for-idle before executing
805 * the resource_control
806 */
807 if (dpu_enc->rc_state != DPU_ENC_RC_STATE_ON) {
808 DRM_DEBUG_KMS("id:%d, sw_event:%d,rc:%d-unexpected\n",
809 DRMID(drm_enc), sw_event,
810 dpu_enc->rc_state);
811 return -EINVAL;
812 }
813
814 /*
815 * schedule off work item only when there are no
816 * frames pending
817 */
818 if (dpu_crtc_frame_pending(drm_enc->crtc) > 1) {
819 DRM_DEBUG_KMS("id:%d skip schedule work\n",
820 DRMID(drm_enc));
821 return 0;
822 }
823
824 queue_delayed_work(priv->wq, &dpu_enc->delayed_off_work,
825 msecs_to_jiffies(dpu_enc->idle_timeout));
826
827 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
828 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
829 "frame done");
830 break;
831
832 case DPU_ENC_RC_EVENT_PRE_STOP:
833 /* cancel delayed off work, if any */
834 if (cancel_delayed_work_sync(&dpu_enc->delayed_off_work))
835 DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, work cancelled\n",
836 sw_event);
837
838 mutex_lock(&dpu_enc->rc_lock);
839
840 if (is_vid_mode &&
841 dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) {
842 _dpu_encoder_irq_control(drm_enc, true);
843 }
844 /* skip if is already OFF or IDLE, resources are off already */
845 else if (dpu_enc->rc_state == DPU_ENC_RC_STATE_OFF ||
846 dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) {
847 DRM_DEBUG_KMS("id:%u, sw_event:%d, rc in %d state\n",
848 DRMID(drm_enc), sw_event,
849 dpu_enc->rc_state);
850 mutex_unlock(&dpu_enc->rc_lock);
851 return 0;
852 }
853
854 dpu_enc->rc_state = DPU_ENC_RC_STATE_PRE_OFF;
855
856 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
857 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
858 "pre stop");
859
860 mutex_unlock(&dpu_enc->rc_lock);
861 break;
862
863 case DPU_ENC_RC_EVENT_STOP:
864 mutex_lock(&dpu_enc->rc_lock);
865
866 /* return if the resource control is already in OFF state */
867 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_OFF) {
868 DRM_DEBUG_KMS("id: %u, sw_event:%d, rc in OFF state\n",
869 DRMID(drm_enc), sw_event);
870 mutex_unlock(&dpu_enc->rc_lock);
871 return 0;
872 } else if (dpu_enc->rc_state == DPU_ENC_RC_STATE_ON) {
873 DRM_ERROR("id: %u, sw_event:%d, rc in state %d\n",
874 DRMID(drm_enc), sw_event, dpu_enc->rc_state);
875 mutex_unlock(&dpu_enc->rc_lock);
876 return -EINVAL;
877 }
878
879 /**
880 * expect to arrive here only if in either idle state or pre-off
881 * and in IDLE state the resources are already disabled
882 */
883 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_PRE_OFF)
884 _dpu_encoder_resource_control_helper(drm_enc, false);
885
886 dpu_enc->rc_state = DPU_ENC_RC_STATE_OFF;
887
888 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
889 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
890 "stop");
891
892 mutex_unlock(&dpu_enc->rc_lock);
893 break;
894
895 case DPU_ENC_RC_EVENT_ENTER_IDLE:
896 mutex_lock(&dpu_enc->rc_lock);
897
898 if (dpu_enc->rc_state != DPU_ENC_RC_STATE_ON) {
899 DRM_ERROR("id: %u, sw_event:%d, rc:%d !ON state\n",
900 DRMID(drm_enc), sw_event, dpu_enc->rc_state);
901 mutex_unlock(&dpu_enc->rc_lock);
902 return 0;
903 }
904
905 /*
906 * if we are in ON but a frame was just kicked off,
907 * ignore the IDLE event, it's probably a stale timer event
908 */
909 if (dpu_enc->frame_busy_mask[0]) {
910 DRM_ERROR("id:%u, sw_event:%d, rc:%d frame pending\n",
911 DRMID(drm_enc), sw_event, dpu_enc->rc_state);
912 mutex_unlock(&dpu_enc->rc_lock);
913 return 0;
914 }
915
916 if (is_vid_mode)
917 _dpu_encoder_irq_control(drm_enc, false);
918 else
919 _dpu_encoder_resource_control_helper(drm_enc, false);
920
921 dpu_enc->rc_state = DPU_ENC_RC_STATE_IDLE;
922
923 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
924 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
925 "idle");
926
927 mutex_unlock(&dpu_enc->rc_lock);
928 break;
929
930 default:
931 DRM_ERROR("id:%u, unexpected sw_event: %d\n", DRMID(drm_enc),
932 sw_event);
933 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
934 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
935 "error");
936 break;
937 }
938
939 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
940 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
941 "end");
942 return 0;
943 }
944
945 static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc,
946 struct drm_display_mode *mode,
947 struct drm_display_mode *adj_mode)
948 {
949 struct dpu_encoder_virt *dpu_enc;
950 struct msm_drm_private *priv;
951 struct dpu_kms *dpu_kms;
952 struct list_head *connector_list;
953 struct drm_connector *conn = NULL, *conn_iter;
954 struct drm_crtc *drm_crtc;
955 struct dpu_crtc_state *cstate;
956 struct dpu_rm_hw_iter hw_iter;
957 struct msm_display_topology topology;
958 struct dpu_hw_ctl *hw_ctl[MAX_CHANNELS_PER_ENC] = { NULL };
959 struct dpu_hw_mixer *hw_lm[MAX_CHANNELS_PER_ENC] = { NULL };
960 int num_lm = 0, num_ctl = 0;
961 int i, j, ret;
962
963 if (!drm_enc) {
964 DPU_ERROR("invalid encoder\n");
965 return;
966 }
967
968 dpu_enc = to_dpu_encoder_virt(drm_enc);
969 DPU_DEBUG_ENC(dpu_enc, "\n");
970
971 priv = drm_enc->dev->dev_private;
972 dpu_kms = to_dpu_kms(priv->kms);
973 connector_list = &dpu_kms->dev->mode_config.connector_list;
974
975 trace_dpu_enc_mode_set(DRMID(drm_enc));
976
977 list_for_each_entry(conn_iter, connector_list, head)
978 if (conn_iter->encoder == drm_enc)
979 conn = conn_iter;
980
981 if (!conn) {
982 DPU_ERROR_ENC(dpu_enc, "failed to find attached connector\n");
983 return;
984 } else if (!conn->state) {
985 DPU_ERROR_ENC(dpu_enc, "invalid connector state\n");
986 return;
987 }
988
989 drm_for_each_crtc(drm_crtc, drm_enc->dev)
990 if (drm_crtc->state->encoder_mask & drm_encoder_mask(drm_enc))
991 break;
992
993 topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode);
994
995 /* Reserve dynamic resources now. Indicating non-AtomicTest phase */
996 ret = dpu_rm_reserve(&dpu_kms->rm, drm_enc, drm_crtc->state,
997 topology, false);
998 if (ret) {
999 DPU_ERROR_ENC(dpu_enc,
1000 "failed to reserve hw resources, %d\n", ret);
1001 return;
1002 }
1003
1004 dpu_rm_init_hw_iter(&hw_iter, drm_enc->base.id, DPU_HW_BLK_PINGPONG);
1005 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
1006 dpu_enc->hw_pp[i] = NULL;
1007 if (!dpu_rm_get_hw(&dpu_kms->rm, &hw_iter))
1008 break;
1009 dpu_enc->hw_pp[i] = (struct dpu_hw_pingpong *) hw_iter.hw;
1010 }
1011
1012 dpu_rm_init_hw_iter(&hw_iter, drm_enc->base.id, DPU_HW_BLK_CTL);
1013 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
1014 if (!dpu_rm_get_hw(&dpu_kms->rm, &hw_iter))
1015 break;
1016 hw_ctl[i] = (struct dpu_hw_ctl *)hw_iter.hw;
1017 num_ctl++;
1018 }
1019
1020 dpu_rm_init_hw_iter(&hw_iter, drm_enc->base.id, DPU_HW_BLK_LM);
1021 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
1022 if (!dpu_rm_get_hw(&dpu_kms->rm, &hw_iter))
1023 break;
1024 hw_lm[i] = (struct dpu_hw_mixer *)hw_iter.hw;
1025 num_lm++;
1026 }
1027
1028 cstate = to_dpu_crtc_state(drm_crtc->state);
1029
1030 for (i = 0; i < num_lm; i++) {
1031 int ctl_idx = (i < num_ctl) ? i : (num_ctl-1);
1032
1033 cstate->mixers[i].hw_lm = hw_lm[i];
1034 cstate->mixers[i].lm_ctl = hw_ctl[ctl_idx];
1035 }
1036
1037 cstate->num_mixers = num_lm;
1038
1039 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1040 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1041
1042 if (phys) {
1043 if (!dpu_enc->hw_pp[i]) {
1044 DPU_ERROR_ENC(dpu_enc, "no pp block assigned"
1045 "at idx: %d\n", i);
1046 goto error;
1047 }
1048
1049 if (!hw_ctl[i]) {
1050 DPU_ERROR_ENC(dpu_enc, "no ctl block assigned"
1051 "at idx: %d\n", i);
1052 goto error;
1053 }
1054
1055 phys->hw_pp = dpu_enc->hw_pp[i];
1056 phys->hw_ctl = hw_ctl[i];
1057
1058 dpu_rm_init_hw_iter(&hw_iter, drm_enc->base.id,
1059 DPU_HW_BLK_INTF);
1060 for (j = 0; j < MAX_CHANNELS_PER_ENC; j++) {
1061 struct dpu_hw_intf *hw_intf;
1062
1063 if (!dpu_rm_get_hw(&dpu_kms->rm, &hw_iter))
1064 break;
1065
1066 hw_intf = (struct dpu_hw_intf *)hw_iter.hw;
1067 if (hw_intf->idx == phys->intf_idx)
1068 phys->hw_intf = hw_intf;
1069 }
1070
1071 if (!phys->hw_intf) {
1072 DPU_ERROR_ENC(dpu_enc,
1073 "no intf block assigned at idx: %d\n",
1074 i);
1075 goto error;
1076 }
1077
1078 phys->connector = conn->state->connector;
1079 if (phys->ops.mode_set)
1080 phys->ops.mode_set(phys, mode, adj_mode);
1081 }
1082 }
1083
1084 dpu_enc->mode_set_complete = true;
1085
1086 error:
1087 dpu_rm_release(&dpu_kms->rm, drm_enc);
1088 }
1089
1090 static void _dpu_encoder_virt_enable_helper(struct drm_encoder *drm_enc)
1091 {
1092 struct dpu_encoder_virt *dpu_enc = NULL;
1093 struct msm_drm_private *priv;
1094 struct dpu_kms *dpu_kms;
1095
1096 if (!drm_enc || !drm_enc->dev || !drm_enc->dev->dev_private) {
1097 DPU_ERROR("invalid parameters\n");
1098 return;
1099 }
1100
1101 priv = drm_enc->dev->dev_private;
1102 dpu_kms = to_dpu_kms(priv->kms);
1103 if (!dpu_kms) {
1104 DPU_ERROR("invalid dpu_kms\n");
1105 return;
1106 }
1107
1108 dpu_enc = to_dpu_encoder_virt(drm_enc);
1109 if (!dpu_enc || !dpu_enc->cur_master) {
1110 DPU_ERROR("invalid dpu encoder/master\n");
1111 return;
1112 }
1113
1114 if (dpu_enc->cur_master->hw_mdptop &&
1115 dpu_enc->cur_master->hw_mdptop->ops.reset_ubwc)
1116 dpu_enc->cur_master->hw_mdptop->ops.reset_ubwc(
1117 dpu_enc->cur_master->hw_mdptop,
1118 dpu_kms->catalog);
1119
1120 _dpu_encoder_update_vsync_source(dpu_enc, &dpu_enc->disp_info);
1121 }
1122
1123 void dpu_encoder_virt_runtime_resume(struct drm_encoder *drm_enc)
1124 {
1125 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1126
1127 mutex_lock(&dpu_enc->enc_lock);
1128
1129 if (!dpu_enc->enabled)
1130 goto out;
1131
1132 if (dpu_enc->cur_slave && dpu_enc->cur_slave->ops.restore)
1133 dpu_enc->cur_slave->ops.restore(dpu_enc->cur_slave);
1134 if (dpu_enc->cur_master && dpu_enc->cur_master->ops.restore)
1135 dpu_enc->cur_master->ops.restore(dpu_enc->cur_master);
1136
1137 _dpu_encoder_virt_enable_helper(drm_enc);
1138
1139 out:
1140 mutex_unlock(&dpu_enc->enc_lock);
1141 }
1142
1143 static void dpu_encoder_virt_enable(struct drm_encoder *drm_enc)
1144 {
1145 struct dpu_encoder_virt *dpu_enc = NULL;
1146 int ret = 0;
1147 struct drm_display_mode *cur_mode = NULL;
1148
1149 if (!drm_enc) {
1150 DPU_ERROR("invalid encoder\n");
1151 return;
1152 }
1153 dpu_enc = to_dpu_encoder_virt(drm_enc);
1154
1155 mutex_lock(&dpu_enc->enc_lock);
1156 cur_mode = &dpu_enc->base.crtc->state->adjusted_mode;
1157
1158 trace_dpu_enc_enable(DRMID(drm_enc), cur_mode->hdisplay,
1159 cur_mode->vdisplay);
1160
1161 /* always enable slave encoder before master */
1162 if (dpu_enc->cur_slave && dpu_enc->cur_slave->ops.enable)
1163 dpu_enc->cur_slave->ops.enable(dpu_enc->cur_slave);
1164
1165 if (dpu_enc->cur_master && dpu_enc->cur_master->ops.enable)
1166 dpu_enc->cur_master->ops.enable(dpu_enc->cur_master);
1167
1168 ret = dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_KICKOFF);
1169 if (ret) {
1170 DPU_ERROR_ENC(dpu_enc, "dpu resource control failed: %d\n",
1171 ret);
1172 goto out;
1173 }
1174
1175 _dpu_encoder_virt_enable_helper(drm_enc);
1176
1177 dpu_enc->enabled = true;
1178
1179 out:
1180 mutex_unlock(&dpu_enc->enc_lock);
1181 }
1182
1183 static void dpu_encoder_virt_disable(struct drm_encoder *drm_enc)
1184 {
1185 struct dpu_encoder_virt *dpu_enc = NULL;
1186 struct msm_drm_private *priv;
1187 struct dpu_kms *dpu_kms;
1188 struct drm_display_mode *mode;
1189 int i = 0;
1190
1191 if (!drm_enc) {
1192 DPU_ERROR("invalid encoder\n");
1193 return;
1194 } else if (!drm_enc->dev) {
1195 DPU_ERROR("invalid dev\n");
1196 return;
1197 } else if (!drm_enc->dev->dev_private) {
1198 DPU_ERROR("invalid dev_private\n");
1199 return;
1200 }
1201
1202 dpu_enc = to_dpu_encoder_virt(drm_enc);
1203 DPU_DEBUG_ENC(dpu_enc, "\n");
1204
1205 mutex_lock(&dpu_enc->enc_lock);
1206 dpu_enc->enabled = false;
1207
1208 mode = &drm_enc->crtc->state->adjusted_mode;
1209
1210 priv = drm_enc->dev->dev_private;
1211 dpu_kms = to_dpu_kms(priv->kms);
1212
1213 trace_dpu_enc_disable(DRMID(drm_enc));
1214
1215 /* wait for idle */
1216 dpu_encoder_wait_for_event(drm_enc, MSM_ENC_TX_COMPLETE);
1217
1218 dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_PRE_STOP);
1219
1220 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1221 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1222
1223 if (phys && phys->ops.disable)
1224 phys->ops.disable(phys);
1225 }
1226
1227 /* after phys waits for frame-done, should be no more frames pending */
1228 if (atomic_xchg(&dpu_enc->frame_done_timeout_ms, 0)) {
1229 DPU_ERROR("enc%d timeout pending\n", drm_enc->base.id);
1230 del_timer_sync(&dpu_enc->frame_done_timer);
1231 }
1232
1233 dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_STOP);
1234
1235 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1236 if (dpu_enc->phys_encs[i])
1237 dpu_enc->phys_encs[i]->connector = NULL;
1238 }
1239
1240 DPU_DEBUG_ENC(dpu_enc, "encoder disabled\n");
1241
1242 dpu_rm_release(&dpu_kms->rm, drm_enc);
1243
1244 mutex_unlock(&dpu_enc->enc_lock);
1245 }
1246
1247 static enum dpu_intf dpu_encoder_get_intf(struct dpu_mdss_cfg *catalog,
1248 enum dpu_intf_type type, u32 controller_id)
1249 {
1250 int i = 0;
1251
1252 for (i = 0; i < catalog->intf_count; i++) {
1253 if (catalog->intf[i].type == type
1254 && catalog->intf[i].controller_id == controller_id) {
1255 return catalog->intf[i].id;
1256 }
1257 }
1258
1259 return INTF_MAX;
1260 }
1261
1262 static void dpu_encoder_vblank_callback(struct drm_encoder *drm_enc,
1263 struct dpu_encoder_phys *phy_enc)
1264 {
1265 struct dpu_encoder_virt *dpu_enc = NULL;
1266 unsigned long lock_flags;
1267
1268 if (!drm_enc || !phy_enc)
1269 return;
1270
1271 DPU_ATRACE_BEGIN("encoder_vblank_callback");
1272 dpu_enc = to_dpu_encoder_virt(drm_enc);
1273
1274 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1275 if (dpu_enc->crtc)
1276 dpu_crtc_vblank_callback(dpu_enc->crtc);
1277 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1278
1279 atomic_inc(&phy_enc->vsync_cnt);
1280 DPU_ATRACE_END("encoder_vblank_callback");
1281 }
1282
1283 static void dpu_encoder_underrun_callback(struct drm_encoder *drm_enc,
1284 struct dpu_encoder_phys *phy_enc)
1285 {
1286 if (!phy_enc)
1287 return;
1288
1289 DPU_ATRACE_BEGIN("encoder_underrun_callback");
1290 atomic_inc(&phy_enc->underrun_cnt);
1291 trace_dpu_enc_underrun_cb(DRMID(drm_enc),
1292 atomic_read(&phy_enc->underrun_cnt));
1293 DPU_ATRACE_END("encoder_underrun_callback");
1294 }
1295
1296 void dpu_encoder_assign_crtc(struct drm_encoder *drm_enc, struct drm_crtc *crtc)
1297 {
1298 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1299 unsigned long lock_flags;
1300
1301 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1302 /* crtc should always be cleared before re-assigning */
1303 WARN_ON(crtc && dpu_enc->crtc);
1304 dpu_enc->crtc = crtc;
1305 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1306 }
1307
1308 void dpu_encoder_toggle_vblank_for_crtc(struct drm_encoder *drm_enc,
1309 struct drm_crtc *crtc, bool enable)
1310 {
1311 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1312 unsigned long lock_flags;
1313 int i;
1314
1315 trace_dpu_enc_vblank_cb(DRMID(drm_enc), enable);
1316
1317 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1318 if (dpu_enc->crtc != crtc) {
1319 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1320 return;
1321 }
1322 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1323
1324 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1325 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1326
1327 if (phys && phys->ops.control_vblank_irq)
1328 phys->ops.control_vblank_irq(phys, enable);
1329 }
1330 }
1331
1332 void dpu_encoder_register_frame_event_callback(struct drm_encoder *drm_enc,
1333 void (*frame_event_cb)(void *, u32 event),
1334 void *frame_event_cb_data)
1335 {
1336 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1337 unsigned long lock_flags;
1338 bool enable;
1339
1340 enable = frame_event_cb ? true : false;
1341
1342 if (!drm_enc) {
1343 DPU_ERROR("invalid encoder\n");
1344 return;
1345 }
1346 trace_dpu_enc_frame_event_cb(DRMID(drm_enc), enable);
1347
1348 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1349 dpu_enc->crtc_frame_event_cb = frame_event_cb;
1350 dpu_enc->crtc_frame_event_cb_data = frame_event_cb_data;
1351 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1352 }
1353
1354 static void dpu_encoder_frame_done_callback(
1355 struct drm_encoder *drm_enc,
1356 struct dpu_encoder_phys *ready_phys, u32 event)
1357 {
1358 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1359 unsigned int i;
1360
1361 if (event & (DPU_ENCODER_FRAME_EVENT_DONE
1362 | DPU_ENCODER_FRAME_EVENT_ERROR
1363 | DPU_ENCODER_FRAME_EVENT_PANEL_DEAD)) {
1364
1365 if (!dpu_enc->frame_busy_mask[0]) {
1366 /**
1367 * suppress frame_done without waiter,
1368 * likely autorefresh
1369 */
1370 trace_dpu_enc_frame_done_cb_not_busy(DRMID(drm_enc),
1371 event, ready_phys->intf_idx);
1372 return;
1373 }
1374
1375 /* One of the physical encoders has become idle */
1376 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1377 if (dpu_enc->phys_encs[i] == ready_phys) {
1378 trace_dpu_enc_frame_done_cb(DRMID(drm_enc), i,
1379 dpu_enc->frame_busy_mask[0]);
1380 clear_bit(i, dpu_enc->frame_busy_mask);
1381 }
1382 }
1383
1384 if (!dpu_enc->frame_busy_mask[0]) {
1385 atomic_set(&dpu_enc->frame_done_timeout_ms, 0);
1386 del_timer(&dpu_enc->frame_done_timer);
1387
1388 dpu_encoder_resource_control(drm_enc,
1389 DPU_ENC_RC_EVENT_FRAME_DONE);
1390
1391 if (dpu_enc->crtc_frame_event_cb)
1392 dpu_enc->crtc_frame_event_cb(
1393 dpu_enc->crtc_frame_event_cb_data,
1394 event);
1395 }
1396 } else {
1397 if (dpu_enc->crtc_frame_event_cb)
1398 dpu_enc->crtc_frame_event_cb(
1399 dpu_enc->crtc_frame_event_cb_data, event);
1400 }
1401 }
1402
1403 static void dpu_encoder_off_work(struct work_struct *work)
1404 {
1405 struct dpu_encoder_virt *dpu_enc = container_of(work,
1406 struct dpu_encoder_virt, delayed_off_work.work);
1407
1408 if (!dpu_enc) {
1409 DPU_ERROR("invalid dpu encoder\n");
1410 return;
1411 }
1412
1413 dpu_encoder_resource_control(&dpu_enc->base,
1414 DPU_ENC_RC_EVENT_ENTER_IDLE);
1415
1416 dpu_encoder_frame_done_callback(&dpu_enc->base, NULL,
1417 DPU_ENCODER_FRAME_EVENT_IDLE);
1418 }
1419
1420 /**
1421 * _dpu_encoder_trigger_flush - trigger flush for a physical encoder
1422 * drm_enc: Pointer to drm encoder structure
1423 * phys: Pointer to physical encoder structure
1424 * extra_flush_bits: Additional bit mask to include in flush trigger
1425 */
1426 static void _dpu_encoder_trigger_flush(struct drm_encoder *drm_enc,
1427 struct dpu_encoder_phys *phys, uint32_t extra_flush_bits,
1428 bool async)
1429 {
1430 struct dpu_hw_ctl *ctl;
1431 int pending_kickoff_cnt;
1432 u32 ret = UINT_MAX;
1433
1434 if (!drm_enc || !phys) {
1435 DPU_ERROR("invalid argument(s), drm_enc %d, phys_enc %d\n",
1436 drm_enc != 0, phys != 0);
1437 return;
1438 }
1439
1440 if (!phys->hw_pp) {
1441 DPU_ERROR("invalid pingpong hw\n");
1442 return;
1443 }
1444
1445 ctl = phys->hw_ctl;
1446 if (!ctl || !ctl->ops.trigger_flush) {
1447 DPU_ERROR("missing trigger cb\n");
1448 return;
1449 }
1450
1451 if (!async)
1452 pending_kickoff_cnt = dpu_encoder_phys_inc_pending(phys);
1453 else
1454 pending_kickoff_cnt = atomic_read(&phys->pending_kickoff_cnt);
1455
1456 if (extra_flush_bits && ctl->ops.update_pending_flush)
1457 ctl->ops.update_pending_flush(ctl, extra_flush_bits);
1458
1459 ctl->ops.trigger_flush(ctl);
1460
1461 if (ctl->ops.get_pending_flush)
1462 ret = ctl->ops.get_pending_flush(ctl);
1463
1464 trace_dpu_enc_trigger_flush(DRMID(drm_enc), phys->intf_idx,
1465 pending_kickoff_cnt, ctl->idx,
1466 extra_flush_bits, ret);
1467 }
1468
1469 /**
1470 * _dpu_encoder_trigger_start - trigger start for a physical encoder
1471 * phys: Pointer to physical encoder structure
1472 */
1473 static void _dpu_encoder_trigger_start(struct dpu_encoder_phys *phys)
1474 {
1475 if (!phys) {
1476 DPU_ERROR("invalid argument(s)\n");
1477 return;
1478 }
1479
1480 if (!phys->hw_pp) {
1481 DPU_ERROR("invalid pingpong hw\n");
1482 return;
1483 }
1484
1485 if (phys->ops.trigger_start && phys->enable_state != DPU_ENC_DISABLED)
1486 phys->ops.trigger_start(phys);
1487 }
1488
1489 void dpu_encoder_helper_trigger_start(struct dpu_encoder_phys *phys_enc)
1490 {
1491 struct dpu_hw_ctl *ctl;
1492
1493 if (!phys_enc) {
1494 DPU_ERROR("invalid encoder\n");
1495 return;
1496 }
1497
1498 ctl = phys_enc->hw_ctl;
1499 if (ctl && ctl->ops.trigger_start) {
1500 ctl->ops.trigger_start(ctl);
1501 trace_dpu_enc_trigger_start(DRMID(phys_enc->parent), ctl->idx);
1502 }
1503 }
1504
1505 static int dpu_encoder_helper_wait_event_timeout(
1506 int32_t drm_id,
1507 int32_t hw_id,
1508 struct dpu_encoder_wait_info *info)
1509 {
1510 int rc = 0;
1511 s64 expected_time = ktime_to_ms(ktime_get()) + info->timeout_ms;
1512 s64 jiffies = msecs_to_jiffies(info->timeout_ms);
1513 s64 time;
1514
1515 do {
1516 rc = wait_event_timeout(*(info->wq),
1517 atomic_read(info->atomic_cnt) == 0, jiffies);
1518 time = ktime_to_ms(ktime_get());
1519
1520 trace_dpu_enc_wait_event_timeout(drm_id, hw_id, rc, time,
1521 expected_time,
1522 atomic_read(info->atomic_cnt));
1523 /* If we timed out, counter is valid and time is less, wait again */
1524 } while (atomic_read(info->atomic_cnt) && (rc == 0) &&
1525 (time < expected_time));
1526
1527 return rc;
1528 }
1529
1530 static void dpu_encoder_helper_hw_reset(struct dpu_encoder_phys *phys_enc)
1531 {
1532 struct dpu_encoder_virt *dpu_enc;
1533 struct dpu_hw_ctl *ctl;
1534 int rc;
1535
1536 if (!phys_enc) {
1537 DPU_ERROR("invalid encoder\n");
1538 return;
1539 }
1540 dpu_enc = to_dpu_encoder_virt(phys_enc->parent);
1541 ctl = phys_enc->hw_ctl;
1542
1543 if (!ctl || !ctl->ops.reset)
1544 return;
1545
1546 DRM_DEBUG_KMS("id:%u ctl %d reset\n", DRMID(phys_enc->parent),
1547 ctl->idx);
1548
1549 rc = ctl->ops.reset(ctl);
1550 if (rc)
1551 DPU_ERROR_ENC(dpu_enc, "ctl %d reset failure\n", ctl->idx);
1552
1553 phys_enc->enable_state = DPU_ENC_ENABLED;
1554 }
1555
1556 /**
1557 * _dpu_encoder_kickoff_phys - handle physical encoder kickoff
1558 * Iterate through the physical encoders and perform consolidated flush
1559 * and/or control start triggering as needed. This is done in the virtual
1560 * encoder rather than the individual physical ones in order to handle
1561 * use cases that require visibility into multiple physical encoders at
1562 * a time.
1563 * dpu_enc: Pointer to virtual encoder structure
1564 */
1565 static void _dpu_encoder_kickoff_phys(struct dpu_encoder_virt *dpu_enc,
1566 bool async)
1567 {
1568 struct dpu_hw_ctl *ctl;
1569 uint32_t i, pending_flush;
1570 unsigned long lock_flags;
1571
1572 if (!dpu_enc) {
1573 DPU_ERROR("invalid encoder\n");
1574 return;
1575 }
1576
1577 pending_flush = 0x0;
1578
1579 /* update pending counts and trigger kickoff ctl flush atomically */
1580 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1581
1582 /* don't perform flush/start operations for slave encoders */
1583 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1584 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1585
1586 if (!phys || phys->enable_state == DPU_ENC_DISABLED)
1587 continue;
1588
1589 ctl = phys->hw_ctl;
1590 if (!ctl)
1591 continue;
1592
1593 /*
1594 * This is cleared in frame_done worker, which isn't invoked
1595 * for async commits. So don't set this for async, since it'll
1596 * roll over to the next commit.
1597 */
1598 if (!async && phys->split_role != ENC_ROLE_SLAVE)
1599 set_bit(i, dpu_enc->frame_busy_mask);
1600
1601 if (!phys->ops.needs_single_flush ||
1602 !phys->ops.needs_single_flush(phys))
1603 _dpu_encoder_trigger_flush(&dpu_enc->base, phys, 0x0,
1604 async);
1605 else if (ctl->ops.get_pending_flush)
1606 pending_flush |= ctl->ops.get_pending_flush(ctl);
1607 }
1608
1609 /* for split flush, combine pending flush masks and send to master */
1610 if (pending_flush && dpu_enc->cur_master) {
1611 _dpu_encoder_trigger_flush(
1612 &dpu_enc->base,
1613 dpu_enc->cur_master,
1614 pending_flush, async);
1615 }
1616
1617 _dpu_encoder_trigger_start(dpu_enc->cur_master);
1618
1619 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1620 }
1621
1622 void dpu_encoder_trigger_kickoff_pending(struct drm_encoder *drm_enc)
1623 {
1624 struct dpu_encoder_virt *dpu_enc;
1625 struct dpu_encoder_phys *phys;
1626 unsigned int i;
1627 struct dpu_hw_ctl *ctl;
1628 struct msm_display_info *disp_info;
1629
1630 if (!drm_enc) {
1631 DPU_ERROR("invalid encoder\n");
1632 return;
1633 }
1634 dpu_enc = to_dpu_encoder_virt(drm_enc);
1635 disp_info = &dpu_enc->disp_info;
1636
1637 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1638 phys = dpu_enc->phys_encs[i];
1639
1640 if (phys && phys->hw_ctl) {
1641 ctl = phys->hw_ctl;
1642 if (ctl->ops.clear_pending_flush)
1643 ctl->ops.clear_pending_flush(ctl);
1644
1645 /* update only for command mode primary ctl */
1646 if ((phys == dpu_enc->cur_master) &&
1647 (disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE)
1648 && ctl->ops.trigger_pending)
1649 ctl->ops.trigger_pending(ctl);
1650 }
1651 }
1652 }
1653
1654 static u32 _dpu_encoder_calculate_linetime(struct dpu_encoder_virt *dpu_enc,
1655 struct drm_display_mode *mode)
1656 {
1657 u64 pclk_rate;
1658 u32 pclk_period;
1659 u32 line_time;
1660
1661 /*
1662 * For linetime calculation, only operate on master encoder.
1663 */
1664 if (!dpu_enc->cur_master)
1665 return 0;
1666
1667 if (!dpu_enc->cur_master->ops.get_line_count) {
1668 DPU_ERROR("get_line_count function not defined\n");
1669 return 0;
1670 }
1671
1672 pclk_rate = mode->clock; /* pixel clock in kHz */
1673 if (pclk_rate == 0) {
1674 DPU_ERROR("pclk is 0, cannot calculate line time\n");
1675 return 0;
1676 }
1677
1678 pclk_period = DIV_ROUND_UP_ULL(1000000000ull, pclk_rate);
1679 if (pclk_period == 0) {
1680 DPU_ERROR("pclk period is 0\n");
1681 return 0;
1682 }
1683
1684 /*
1685 * Line time calculation based on Pixel clock and HTOTAL.
1686 * Final unit is in ns.
1687 */
1688 line_time = (pclk_period * mode->htotal) / 1000;
1689 if (line_time == 0) {
1690 DPU_ERROR("line time calculation is 0\n");
1691 return 0;
1692 }
1693
1694 DPU_DEBUG_ENC(dpu_enc,
1695 "clk_rate=%lldkHz, clk_period=%d, linetime=%dns\n",
1696 pclk_rate, pclk_period, line_time);
1697
1698 return line_time;
1699 }
1700
1701 static int _dpu_encoder_wakeup_time(struct drm_encoder *drm_enc,
1702 ktime_t *wakeup_time)
1703 {
1704 struct drm_display_mode *mode;
1705 struct dpu_encoder_virt *dpu_enc;
1706 u32 cur_line;
1707 u32 line_time;
1708 u32 vtotal, time_to_vsync;
1709 ktime_t cur_time;
1710
1711 dpu_enc = to_dpu_encoder_virt(drm_enc);
1712
1713 if (!drm_enc->crtc || !drm_enc->crtc->state) {
1714 DPU_ERROR("crtc/crtc state object is NULL\n");
1715 return -EINVAL;
1716 }
1717 mode = &drm_enc->crtc->state->adjusted_mode;
1718
1719 line_time = _dpu_encoder_calculate_linetime(dpu_enc, mode);
1720 if (!line_time)
1721 return -EINVAL;
1722
1723 cur_line = dpu_enc->cur_master->ops.get_line_count(dpu_enc->cur_master);
1724
1725 vtotal = mode->vtotal;
1726 if (cur_line >= vtotal)
1727 time_to_vsync = line_time * vtotal;
1728 else
1729 time_to_vsync = line_time * (vtotal - cur_line);
1730
1731 if (time_to_vsync == 0) {
1732 DPU_ERROR("time to vsync should not be zero, vtotal=%d\n",
1733 vtotal);
1734 return -EINVAL;
1735 }
1736
1737 cur_time = ktime_get();
1738 *wakeup_time = ktime_add_ns(cur_time, time_to_vsync);
1739
1740 DPU_DEBUG_ENC(dpu_enc,
1741 "cur_line=%u vtotal=%u time_to_vsync=%u, cur_time=%lld, wakeup_time=%lld\n",
1742 cur_line, vtotal, time_to_vsync,
1743 ktime_to_ms(cur_time),
1744 ktime_to_ms(*wakeup_time));
1745 return 0;
1746 }
1747
1748 static void dpu_encoder_vsync_event_handler(struct timer_list *t)
1749 {
1750 struct dpu_encoder_virt *dpu_enc = from_timer(dpu_enc, t,
1751 vsync_event_timer);
1752 struct drm_encoder *drm_enc = &dpu_enc->base;
1753 struct msm_drm_private *priv;
1754 struct msm_drm_thread *event_thread;
1755
1756 if (!drm_enc->dev || !drm_enc->dev->dev_private ||
1757 !drm_enc->crtc) {
1758 DPU_ERROR("invalid parameters\n");
1759 return;
1760 }
1761
1762 priv = drm_enc->dev->dev_private;
1763
1764 if (drm_enc->crtc->index >= ARRAY_SIZE(priv->event_thread)) {
1765 DPU_ERROR("invalid crtc index\n");
1766 return;
1767 }
1768 event_thread = &priv->event_thread[drm_enc->crtc->index];
1769 if (!event_thread) {
1770 DPU_ERROR("event_thread not found for crtc:%d\n",
1771 drm_enc->crtc->index);
1772 return;
1773 }
1774
1775 del_timer(&dpu_enc->vsync_event_timer);
1776 }
1777
1778 static void dpu_encoder_vsync_event_work_handler(struct kthread_work *work)
1779 {
1780 struct dpu_encoder_virt *dpu_enc = container_of(work,
1781 struct dpu_encoder_virt, vsync_event_work);
1782 ktime_t wakeup_time;
1783
1784 if (!dpu_enc) {
1785 DPU_ERROR("invalid dpu encoder\n");
1786 return;
1787 }
1788
1789 if (_dpu_encoder_wakeup_time(&dpu_enc->base, &wakeup_time))
1790 return;
1791
1792 trace_dpu_enc_vsync_event_work(DRMID(&dpu_enc->base), wakeup_time);
1793 mod_timer(&dpu_enc->vsync_event_timer,
1794 nsecs_to_jiffies(ktime_to_ns(wakeup_time)));
1795 }
1796
1797 void dpu_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc, bool async)
1798 {
1799 struct dpu_encoder_virt *dpu_enc;
1800 struct dpu_encoder_phys *phys;
1801 bool needs_hw_reset = false;
1802 unsigned int i;
1803
1804 if (!drm_enc) {
1805 DPU_ERROR("invalid args\n");
1806 return;
1807 }
1808 dpu_enc = to_dpu_encoder_virt(drm_enc);
1809
1810 trace_dpu_enc_prepare_kickoff(DRMID(drm_enc));
1811
1812 /* prepare for next kickoff, may include waiting on previous kickoff */
1813 DPU_ATRACE_BEGIN("enc_prepare_for_kickoff");
1814 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1815 phys = dpu_enc->phys_encs[i];
1816 if (phys) {
1817 if (phys->ops.prepare_for_kickoff)
1818 phys->ops.prepare_for_kickoff(phys);
1819 if (phys->enable_state == DPU_ENC_ERR_NEEDS_HW_RESET)
1820 needs_hw_reset = true;
1821 }
1822 }
1823 DPU_ATRACE_END("enc_prepare_for_kickoff");
1824
1825 dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_KICKOFF);
1826
1827 /* if any phys needs reset, reset all phys, in-order */
1828 if (needs_hw_reset) {
1829 trace_dpu_enc_prepare_kickoff_reset(DRMID(drm_enc));
1830 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1831 dpu_encoder_helper_hw_reset(dpu_enc->phys_encs[i]);
1832 }
1833 }
1834 }
1835
1836 void dpu_encoder_kickoff(struct drm_encoder *drm_enc, bool async)
1837 {
1838 struct dpu_encoder_virt *dpu_enc;
1839 struct dpu_encoder_phys *phys;
1840 ktime_t wakeup_time;
1841 unsigned int i;
1842
1843 if (!drm_enc) {
1844 DPU_ERROR("invalid encoder\n");
1845 return;
1846 }
1847 DPU_ATRACE_BEGIN("encoder_kickoff");
1848 dpu_enc = to_dpu_encoder_virt(drm_enc);
1849
1850 trace_dpu_enc_kickoff(DRMID(drm_enc));
1851
1852 /*
1853 * Asynchronous frames don't handle FRAME_DONE events. As such, they
1854 * shouldn't enable the frame_done watchdog since it will always time
1855 * out.
1856 */
1857 if (!async) {
1858 unsigned long timeout_ms;
1859 timeout_ms = DPU_ENCODER_FRAME_DONE_TIMEOUT_FRAMES * 1000 /
1860 drm_mode_vrefresh(&drm_enc->crtc->state->adjusted_mode);
1861
1862 atomic_set(&dpu_enc->frame_done_timeout_ms, timeout_ms);
1863 mod_timer(&dpu_enc->frame_done_timer,
1864 jiffies + msecs_to_jiffies(timeout_ms));
1865 }
1866
1867 /* All phys encs are ready to go, trigger the kickoff */
1868 _dpu_encoder_kickoff_phys(dpu_enc, async);
1869
1870 /* allow phys encs to handle any post-kickoff business */
1871 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1872 phys = dpu_enc->phys_encs[i];
1873 if (phys && phys->ops.handle_post_kickoff)
1874 phys->ops.handle_post_kickoff(phys);
1875 }
1876
1877 if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_DSI &&
1878 !_dpu_encoder_wakeup_time(drm_enc, &wakeup_time)) {
1879 trace_dpu_enc_early_kickoff(DRMID(drm_enc),
1880 ktime_to_ms(wakeup_time));
1881 mod_timer(&dpu_enc->vsync_event_timer,
1882 nsecs_to_jiffies(ktime_to_ns(wakeup_time)));
1883 }
1884
1885 DPU_ATRACE_END("encoder_kickoff");
1886 }
1887
1888 void dpu_encoder_prepare_commit(struct drm_encoder *drm_enc)
1889 {
1890 struct dpu_encoder_virt *dpu_enc;
1891 struct dpu_encoder_phys *phys;
1892 int i;
1893
1894 if (!drm_enc) {
1895 DPU_ERROR("invalid encoder\n");
1896 return;
1897 }
1898 dpu_enc = to_dpu_encoder_virt(drm_enc);
1899
1900 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1901 phys = dpu_enc->phys_encs[i];
1902 if (phys && phys->ops.prepare_commit)
1903 phys->ops.prepare_commit(phys);
1904 }
1905 }
1906
1907 #ifdef CONFIG_DEBUG_FS
1908 static int _dpu_encoder_status_show(struct seq_file *s, void *data)
1909 {
1910 struct dpu_encoder_virt *dpu_enc = s->private;
1911 int i;
1912
1913 mutex_lock(&dpu_enc->enc_lock);
1914 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1915 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1916
1917 if (!phys)
1918 continue;
1919
1920 seq_printf(s, "intf:%d vsync:%8d underrun:%8d ",
1921 phys->intf_idx - INTF_0,
1922 atomic_read(&phys->vsync_cnt),
1923 atomic_read(&phys->underrun_cnt));
1924
1925 switch (phys->intf_mode) {
1926 case INTF_MODE_VIDEO:
1927 seq_puts(s, "mode: video\n");
1928 break;
1929 case INTF_MODE_CMD:
1930 seq_puts(s, "mode: command\n");
1931 break;
1932 default:
1933 seq_puts(s, "mode: ???\n");
1934 break;
1935 }
1936 }
1937 mutex_unlock(&dpu_enc->enc_lock);
1938
1939 return 0;
1940 }
1941
1942 static int _dpu_encoder_debugfs_status_open(struct inode *inode,
1943 struct file *file)
1944 {
1945 return single_open(file, _dpu_encoder_status_show, inode->i_private);
1946 }
1947
1948 static int _dpu_encoder_init_debugfs(struct drm_encoder *drm_enc)
1949 {
1950 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1951 struct msm_drm_private *priv;
1952 struct dpu_kms *dpu_kms;
1953 int i;
1954
1955 static const struct file_operations debugfs_status_fops = {
1956 .open = _dpu_encoder_debugfs_status_open,
1957 .read = seq_read,
1958 .llseek = seq_lseek,
1959 .release = single_release,
1960 };
1961
1962 char name[DPU_NAME_SIZE];
1963
1964 if (!drm_enc->dev || !drm_enc->dev->dev_private) {
1965 DPU_ERROR("invalid encoder or kms\n");
1966 return -EINVAL;
1967 }
1968
1969 priv = drm_enc->dev->dev_private;
1970 dpu_kms = to_dpu_kms(priv->kms);
1971
1972 snprintf(name, DPU_NAME_SIZE, "encoder%u", drm_enc->base.id);
1973
1974 /* create overall sub-directory for the encoder */
1975 dpu_enc->debugfs_root = debugfs_create_dir(name,
1976 drm_enc->dev->primary->debugfs_root);
1977 if (!dpu_enc->debugfs_root)
1978 return -ENOMEM;
1979
1980 /* don't error check these */
1981 debugfs_create_file("status", 0600,
1982 dpu_enc->debugfs_root, dpu_enc, &debugfs_status_fops);
1983
1984 for (i = 0; i < dpu_enc->num_phys_encs; i++)
1985 if (dpu_enc->phys_encs[i] &&
1986 dpu_enc->phys_encs[i]->ops.late_register)
1987 dpu_enc->phys_encs[i]->ops.late_register(
1988 dpu_enc->phys_encs[i],
1989 dpu_enc->debugfs_root);
1990
1991 return 0;
1992 }
1993 #else
1994 static int _dpu_encoder_init_debugfs(struct drm_encoder *drm_enc)
1995 {
1996 return 0;
1997 }
1998 #endif
1999
2000 static int dpu_encoder_late_register(struct drm_encoder *encoder)
2001 {
2002 return _dpu_encoder_init_debugfs(encoder);
2003 }
2004
2005 static void dpu_encoder_early_unregister(struct drm_encoder *encoder)
2006 {
2007 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(encoder);
2008
2009 debugfs_remove_recursive(dpu_enc->debugfs_root);
2010 }
2011
2012 static int dpu_encoder_virt_add_phys_encs(
2013 u32 display_caps,
2014 struct dpu_encoder_virt *dpu_enc,
2015 struct dpu_enc_phys_init_params *params)
2016 {
2017 struct dpu_encoder_phys *enc = NULL;
2018
2019 DPU_DEBUG_ENC(dpu_enc, "\n");
2020
2021 /*
2022 * We may create up to NUM_PHYS_ENCODER_TYPES physical encoder types
2023 * in this function, check up-front.
2024 */
2025 if (dpu_enc->num_phys_encs + NUM_PHYS_ENCODER_TYPES >=
2026 ARRAY_SIZE(dpu_enc->phys_encs)) {
2027 DPU_ERROR_ENC(dpu_enc, "too many physical encoders %d\n",
2028 dpu_enc->num_phys_encs);
2029 return -EINVAL;
2030 }
2031
2032 if (display_caps & MSM_DISPLAY_CAP_VID_MODE) {
2033 enc = dpu_encoder_phys_vid_init(params);
2034
2035 if (IS_ERR_OR_NULL(enc)) {
2036 DPU_ERROR_ENC(dpu_enc, "failed to init vid enc: %ld\n",
2037 PTR_ERR(enc));
2038 return enc == 0 ? -EINVAL : PTR_ERR(enc);
2039 }
2040
2041 dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc;
2042 ++dpu_enc->num_phys_encs;
2043 }
2044
2045 if (display_caps & MSM_DISPLAY_CAP_CMD_MODE) {
2046 enc = dpu_encoder_phys_cmd_init(params);
2047
2048 if (IS_ERR_OR_NULL(enc)) {
2049 DPU_ERROR_ENC(dpu_enc, "failed to init cmd enc: %ld\n",
2050 PTR_ERR(enc));
2051 return enc == 0 ? -EINVAL : PTR_ERR(enc);
2052 }
2053
2054 dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc;
2055 ++dpu_enc->num_phys_encs;
2056 }
2057
2058 if (params->split_role == ENC_ROLE_SLAVE)
2059 dpu_enc->cur_slave = enc;
2060 else
2061 dpu_enc->cur_master = enc;
2062
2063 return 0;
2064 }
2065
2066 static const struct dpu_encoder_virt_ops dpu_encoder_parent_ops = {
2067 .handle_vblank_virt = dpu_encoder_vblank_callback,
2068 .handle_underrun_virt = dpu_encoder_underrun_callback,
2069 .handle_frame_done = dpu_encoder_frame_done_callback,
2070 };
2071
2072 static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc,
2073 struct dpu_kms *dpu_kms,
2074 struct msm_display_info *disp_info)
2075 {
2076 int ret = 0;
2077 int i = 0;
2078 enum dpu_intf_type intf_type;
2079 struct dpu_enc_phys_init_params phys_params;
2080
2081 if (!dpu_enc || !dpu_kms) {
2082 DPU_ERROR("invalid arg(s), enc %d kms %d\n",
2083 dpu_enc != 0, dpu_kms != 0);
2084 return -EINVAL;
2085 }
2086
2087 dpu_enc->cur_master = NULL;
2088
2089 memset(&phys_params, 0, sizeof(phys_params));
2090 phys_params.dpu_kms = dpu_kms;
2091 phys_params.parent = &dpu_enc->base;
2092 phys_params.parent_ops = &dpu_encoder_parent_ops;
2093 phys_params.enc_spinlock = &dpu_enc->enc_spinlock;
2094
2095 DPU_DEBUG("\n");
2096
2097 switch (disp_info->intf_type) {
2098 case DRM_MODE_ENCODER_DSI:
2099 intf_type = INTF_DSI;
2100 break;
2101 default:
2102 DPU_ERROR_ENC(dpu_enc, "unsupported display interface type\n");
2103 return -EINVAL;
2104 }
2105
2106 WARN_ON(disp_info->num_of_h_tiles < 1);
2107
2108 DPU_DEBUG("dsi_info->num_of_h_tiles %d\n", disp_info->num_of_h_tiles);
2109
2110 if ((disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) ||
2111 (disp_info->capabilities & MSM_DISPLAY_CAP_VID_MODE))
2112 dpu_enc->idle_pc_supported =
2113 dpu_kms->catalog->caps->has_idle_pc;
2114
2115 mutex_lock(&dpu_enc->enc_lock);
2116 for (i = 0; i < disp_info->num_of_h_tiles && !ret; i++) {
2117 /*
2118 * Left-most tile is at index 0, content is controller id
2119 * h_tile_instance_ids[2] = {0, 1}; DSI0 = left, DSI1 = right
2120 * h_tile_instance_ids[2] = {1, 0}; DSI1 = left, DSI0 = right
2121 */
2122 u32 controller_id = disp_info->h_tile_instance[i];
2123
2124 if (disp_info->num_of_h_tiles > 1) {
2125 if (i == 0)
2126 phys_params.split_role = ENC_ROLE_MASTER;
2127 else
2128 phys_params.split_role = ENC_ROLE_SLAVE;
2129 } else {
2130 phys_params.split_role = ENC_ROLE_SOLO;
2131 }
2132
2133 DPU_DEBUG("h_tile_instance %d = %d, split_role %d\n",
2134 i, controller_id, phys_params.split_role);
2135
2136 phys_params.intf_idx = dpu_encoder_get_intf(dpu_kms->catalog,
2137 intf_type,
2138 controller_id);
2139 if (phys_params.intf_idx == INTF_MAX) {
2140 DPU_ERROR_ENC(dpu_enc, "could not get intf: type %d, id %d\n",
2141 intf_type, controller_id);
2142 ret = -EINVAL;
2143 }
2144
2145 if (!ret) {
2146 ret = dpu_encoder_virt_add_phys_encs(disp_info->capabilities,
2147 dpu_enc,
2148 &phys_params);
2149 if (ret)
2150 DPU_ERROR_ENC(dpu_enc, "failed to add phys encs\n");
2151 }
2152 }
2153
2154 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
2155 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
2156
2157 if (phys) {
2158 atomic_set(&phys->vsync_cnt, 0);
2159 atomic_set(&phys->underrun_cnt, 0);
2160 }
2161 }
2162 mutex_unlock(&dpu_enc->enc_lock);
2163
2164 return ret;
2165 }
2166
2167 static void dpu_encoder_frame_done_timeout(struct timer_list *t)
2168 {
2169 struct dpu_encoder_virt *dpu_enc = from_timer(dpu_enc, t,
2170 frame_done_timer);
2171 struct drm_encoder *drm_enc = &dpu_enc->base;
2172 struct msm_drm_private *priv;
2173 u32 event;
2174
2175 if (!drm_enc->dev || !drm_enc->dev->dev_private) {
2176 DPU_ERROR("invalid parameters\n");
2177 return;
2178 }
2179 priv = drm_enc->dev->dev_private;
2180
2181 if (!dpu_enc->frame_busy_mask[0] || !dpu_enc->crtc_frame_event_cb) {
2182 DRM_DEBUG_KMS("id:%u invalid timeout frame_busy_mask=%lu\n",
2183 DRMID(drm_enc), dpu_enc->frame_busy_mask[0]);
2184 return;
2185 } else if (!atomic_xchg(&dpu_enc->frame_done_timeout_ms, 0)) {
2186 DRM_DEBUG_KMS("id:%u invalid timeout\n", DRMID(drm_enc));
2187 return;
2188 }
2189
2190 DPU_ERROR_ENC(dpu_enc, "frame done timeout\n");
2191
2192 event = DPU_ENCODER_FRAME_EVENT_ERROR;
2193 trace_dpu_enc_frame_done_timeout(DRMID(drm_enc), event);
2194 dpu_enc->crtc_frame_event_cb(dpu_enc->crtc_frame_event_cb_data, event);
2195 }
2196
2197 static const struct drm_encoder_helper_funcs dpu_encoder_helper_funcs = {
2198 .mode_set = dpu_encoder_virt_mode_set,
2199 .disable = dpu_encoder_virt_disable,
2200 .enable = dpu_kms_encoder_enable,
2201 .atomic_check = dpu_encoder_virt_atomic_check,
2202
2203 /* This is called by dpu_kms_encoder_enable */
2204 .commit = dpu_encoder_virt_enable,
2205 };
2206
2207 static const struct drm_encoder_funcs dpu_encoder_funcs = {
2208 .destroy = dpu_encoder_destroy,
2209 .late_register = dpu_encoder_late_register,
2210 .early_unregister = dpu_encoder_early_unregister,
2211 };
2212
2213 int dpu_encoder_setup(struct drm_device *dev, struct drm_encoder *enc,
2214 struct msm_display_info *disp_info)
2215 {
2216 struct msm_drm_private *priv = dev->dev_private;
2217 struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms);
2218 struct drm_encoder *drm_enc = NULL;
2219 struct dpu_encoder_virt *dpu_enc = NULL;
2220 int ret = 0;
2221
2222 dpu_enc = to_dpu_encoder_virt(enc);
2223
2224 mutex_init(&dpu_enc->enc_lock);
2225 ret = dpu_encoder_setup_display(dpu_enc, dpu_kms, disp_info);
2226 if (ret)
2227 goto fail;
2228
2229 spin_lock_init(&dpu_enc->enc_spinlock);
2230
2231 atomic_set(&dpu_enc->frame_done_timeout_ms, 0);
2232 timer_setup(&dpu_enc->frame_done_timer,
2233 dpu_encoder_frame_done_timeout, 0);
2234
2235 if (disp_info->intf_type == DRM_MODE_ENCODER_DSI)
2236 timer_setup(&dpu_enc->vsync_event_timer,
2237 dpu_encoder_vsync_event_handler,
2238 0);
2239
2240
2241 mutex_init(&dpu_enc->rc_lock);
2242 INIT_DELAYED_WORK(&dpu_enc->delayed_off_work,
2243 dpu_encoder_off_work);
2244 dpu_enc->idle_timeout = IDLE_TIMEOUT;
2245
2246 kthread_init_work(&dpu_enc->vsync_event_work,
2247 dpu_encoder_vsync_event_work_handler);
2248
2249 memcpy(&dpu_enc->disp_info, disp_info, sizeof(*disp_info));
2250
2251 DPU_DEBUG_ENC(dpu_enc, "created\n");
2252
2253 return ret;
2254
2255 fail:
2256 DPU_ERROR("failed to create encoder\n");
2257 if (drm_enc)
2258 dpu_encoder_destroy(drm_enc);
2259
2260 return ret;
2261
2262
2263 }
2264
2265 struct drm_encoder *dpu_encoder_init(struct drm_device *dev,
2266 int drm_enc_mode)
2267 {
2268 struct dpu_encoder_virt *dpu_enc = NULL;
2269 int rc = 0;
2270
2271 dpu_enc = devm_kzalloc(dev->dev, sizeof(*dpu_enc), GFP_KERNEL);
2272 if (!dpu_enc)
2273 return ERR_PTR(ENOMEM);
2274
2275 rc = drm_encoder_init(dev, &dpu_enc->base, &dpu_encoder_funcs,
2276 drm_enc_mode, NULL);
2277 if (rc) {
2278 devm_kfree(dev->dev, dpu_enc);
2279 return ERR_PTR(rc);
2280 }
2281
2282 drm_encoder_helper_add(&dpu_enc->base, &dpu_encoder_helper_funcs);
2283
2284 dpu_enc->enabled = false;
2285
2286 return &dpu_enc->base;
2287 }
2288
2289 int dpu_encoder_wait_for_event(struct drm_encoder *drm_enc,
2290 enum msm_event_wait event)
2291 {
2292 int (*fn_wait)(struct dpu_encoder_phys *phys_enc) = NULL;
2293 struct dpu_encoder_virt *dpu_enc = NULL;
2294 int i, ret = 0;
2295
2296 if (!drm_enc) {
2297 DPU_ERROR("invalid encoder\n");
2298 return -EINVAL;
2299 }
2300 dpu_enc = to_dpu_encoder_virt(drm_enc);
2301 DPU_DEBUG_ENC(dpu_enc, "\n");
2302
2303 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
2304 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
2305 if (!phys)
2306 continue;
2307
2308 switch (event) {
2309 case MSM_ENC_COMMIT_DONE:
2310 fn_wait = phys->ops.wait_for_commit_done;
2311 break;
2312 case MSM_ENC_TX_COMPLETE:
2313 fn_wait = phys->ops.wait_for_tx_complete;
2314 break;
2315 case MSM_ENC_VBLANK:
2316 fn_wait = phys->ops.wait_for_vblank;
2317 break;
2318 default:
2319 DPU_ERROR_ENC(dpu_enc, "unknown wait event %d\n",
2320 event);
2321 return -EINVAL;
2322 };
2323
2324 if (fn_wait) {
2325 DPU_ATRACE_BEGIN("wait_for_completion_event");
2326 ret = fn_wait(phys);
2327 DPU_ATRACE_END("wait_for_completion_event");
2328 if (ret)
2329 return ret;
2330 }
2331 }
2332
2333 return ret;
2334 }
2335
2336 enum dpu_intf_mode dpu_encoder_get_intf_mode(struct drm_encoder *encoder)
2337 {
2338 struct dpu_encoder_virt *dpu_enc = NULL;
2339 int i;
2340
2341 if (!encoder) {
2342 DPU_ERROR("invalid encoder\n");
2343 return INTF_MODE_NONE;
2344 }
2345 dpu_enc = to_dpu_encoder_virt(encoder);
2346
2347 if (dpu_enc->cur_master)
2348 return dpu_enc->cur_master->intf_mode;
2349
2350 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
2351 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
2352
2353 if (phys)
2354 return phys->intf_mode;
2355 }
2356
2357 return INTF_MODE_NONE;
2358 }
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