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Merge tag 'kvm-x86-docs-6.7' of https://github.com/kvm-x86/linux into HEAD
[thirdparty/kernel/stable.git] / drivers / gpu / drm / msm / dp / dp_ctrl.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved.
4 */
5
6 #define pr_fmt(fmt) "[drm-dp] %s: " fmt, __func__
7
8 #include <linux/types.h>
9 #include <linux/completion.h>
10 #include <linux/delay.h>
11 #include <linux/phy/phy.h>
12 #include <linux/phy/phy-dp.h>
13 #include <linux/pm_opp.h>
14
15 #include <drm/display/drm_dp_helper.h>
16 #include <drm/drm_fixed.h>
17 #include <drm/drm_print.h>
18
19 #include "dp_reg.h"
20 #include "dp_ctrl.h"
21 #include "dp_link.h"
22
23 #define DP_KHZ_TO_HZ 1000
24 #define IDLE_PATTERN_COMPLETION_TIMEOUT_JIFFIES (30 * HZ / 1000) /* 30 ms */
25 #define PSR_OPERATION_COMPLETION_TIMEOUT_JIFFIES (300 * HZ / 1000) /* 300 ms */
26 #define WAIT_FOR_VIDEO_READY_TIMEOUT_JIFFIES (HZ / 2)
27
28 #define DP_CTRL_INTR_READY_FOR_VIDEO BIT(0)
29 #define DP_CTRL_INTR_IDLE_PATTERN_SENT BIT(3)
30
31 #define MR_LINK_TRAINING1 0x8
32 #define MR_LINK_SYMBOL_ERM 0x80
33 #define MR_LINK_PRBS7 0x100
34 #define MR_LINK_CUSTOM80 0x200
35 #define MR_LINK_TRAINING4 0x40
36
37 enum {
38 DP_TRAINING_NONE,
39 DP_TRAINING_1,
40 DP_TRAINING_2,
41 };
42
43 struct dp_tu_calc_input {
44 u64 lclk; /* 162, 270, 540 and 810 */
45 u64 pclk_khz; /* in KHz */
46 u64 hactive; /* active h-width */
47 u64 hporch; /* bp + fp + pulse */
48 int nlanes; /* no.of.lanes */
49 int bpp; /* bits */
50 int pixel_enc; /* 444, 420, 422 */
51 int dsc_en; /* dsc on/off */
52 int async_en; /* async mode */
53 int fec_en; /* fec */
54 int compress_ratio; /* 2:1 = 200, 3:1 = 300, 3.75:1 = 375 */
55 int num_of_dsc_slices; /* number of slices per line */
56 };
57
58 struct dp_vc_tu_mapping_table {
59 u32 vic;
60 u8 lanes;
61 u8 lrate; /* DP_LINK_RATE -> 162(6), 270(10), 540(20), 810 (30) */
62 u8 bpp;
63 u8 valid_boundary_link;
64 u16 delay_start_link;
65 bool boundary_moderation_en;
66 u8 valid_lower_boundary_link;
67 u8 upper_boundary_count;
68 u8 lower_boundary_count;
69 u8 tu_size_minus1;
70 };
71
72 struct dp_ctrl_private {
73 struct dp_ctrl dp_ctrl;
74 struct drm_device *drm_dev;
75 struct device *dev;
76 struct drm_dp_aux *aux;
77 struct dp_panel *panel;
78 struct dp_link *link;
79 struct dp_power *power;
80 struct dp_parser *parser;
81 struct dp_catalog *catalog;
82
83 struct completion idle_comp;
84 struct completion psr_op_comp;
85 struct completion video_comp;
86 };
87
88 static int dp_aux_link_configure(struct drm_dp_aux *aux,
89 struct dp_link_info *link)
90 {
91 u8 values[2];
92 int err;
93
94 values[0] = drm_dp_link_rate_to_bw_code(link->rate);
95 values[1] = link->num_lanes;
96
97 if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
98 values[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
99
100 err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, values, sizeof(values));
101 if (err < 0)
102 return err;
103
104 return 0;
105 }
106
107 void dp_ctrl_push_idle(struct dp_ctrl *dp_ctrl)
108 {
109 struct dp_ctrl_private *ctrl;
110
111 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
112
113 reinit_completion(&ctrl->idle_comp);
114 dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_PUSH_IDLE);
115
116 if (!wait_for_completion_timeout(&ctrl->idle_comp,
117 IDLE_PATTERN_COMPLETION_TIMEOUT_JIFFIES))
118 pr_warn("PUSH_IDLE pattern timedout\n");
119
120 drm_dbg_dp(ctrl->drm_dev, "mainlink off\n");
121 }
122
123 static void dp_ctrl_config_ctrl(struct dp_ctrl_private *ctrl)
124 {
125 u32 config = 0, tbd;
126 const u8 *dpcd = ctrl->panel->dpcd;
127
128 /* Default-> LSCLK DIV: 1/4 LCLK */
129 config |= (2 << DP_CONFIGURATION_CTRL_LSCLK_DIV_SHIFT);
130
131 /* Scrambler reset enable */
132 if (drm_dp_alternate_scrambler_reset_cap(dpcd))
133 config |= DP_CONFIGURATION_CTRL_ASSR;
134
135 tbd = dp_link_get_test_bits_depth(ctrl->link,
136 ctrl->panel->dp_mode.bpp);
137
138 if (tbd == DP_TEST_BIT_DEPTH_UNKNOWN) {
139 pr_debug("BIT_DEPTH not set. Configure default\n");
140 tbd = DP_TEST_BIT_DEPTH_8;
141 }
142
143 config |= tbd << DP_CONFIGURATION_CTRL_BPC_SHIFT;
144
145 /* Num of Lanes */
146 config |= ((ctrl->link->link_params.num_lanes - 1)
147 << DP_CONFIGURATION_CTRL_NUM_OF_LANES_SHIFT);
148
149 if (drm_dp_enhanced_frame_cap(dpcd))
150 config |= DP_CONFIGURATION_CTRL_ENHANCED_FRAMING;
151
152 config |= DP_CONFIGURATION_CTRL_P_INTERLACED; /* progressive video */
153
154 /* sync clock & static Mvid */
155 config |= DP_CONFIGURATION_CTRL_STATIC_DYNAMIC_CN;
156 config |= DP_CONFIGURATION_CTRL_SYNC_ASYNC_CLK;
157
158 if (ctrl->panel->psr_cap.version)
159 config |= DP_CONFIGURATION_CTRL_SEND_VSC;
160
161 dp_catalog_ctrl_config_ctrl(ctrl->catalog, config);
162 }
163
164 static void dp_ctrl_configure_source_params(struct dp_ctrl_private *ctrl)
165 {
166 u32 cc, tb;
167
168 dp_catalog_ctrl_lane_mapping(ctrl->catalog);
169 dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, true);
170
171 dp_ctrl_config_ctrl(ctrl);
172
173 tb = dp_link_get_test_bits_depth(ctrl->link,
174 ctrl->panel->dp_mode.bpp);
175 cc = dp_link_get_colorimetry_config(ctrl->link);
176 dp_catalog_ctrl_config_misc(ctrl->catalog, cc, tb);
177 dp_panel_timing_cfg(ctrl->panel);
178 }
179
180 /*
181 * The structure and few functions present below are IP/Hardware
182 * specific implementation. Most of the implementation will not
183 * have coding comments
184 */
185 struct tu_algo_data {
186 s64 lclk_fp;
187 s64 pclk_fp;
188 s64 lwidth;
189 s64 lwidth_fp;
190 s64 hbp_relative_to_pclk;
191 s64 hbp_relative_to_pclk_fp;
192 int nlanes;
193 int bpp;
194 int pixelEnc;
195 int dsc_en;
196 int async_en;
197 int bpc;
198
199 uint delay_start_link_extra_pixclk;
200 int extra_buffer_margin;
201 s64 ratio_fp;
202 s64 original_ratio_fp;
203
204 s64 err_fp;
205 s64 n_err_fp;
206 s64 n_n_err_fp;
207 int tu_size;
208 int tu_size_desired;
209 int tu_size_minus1;
210
211 int valid_boundary_link;
212 s64 resulting_valid_fp;
213 s64 total_valid_fp;
214 s64 effective_valid_fp;
215 s64 effective_valid_recorded_fp;
216 int n_tus;
217 int n_tus_per_lane;
218 int paired_tus;
219 int remainder_tus;
220 int remainder_tus_upper;
221 int remainder_tus_lower;
222 int extra_bytes;
223 int filler_size;
224 int delay_start_link;
225
226 int extra_pclk_cycles;
227 int extra_pclk_cycles_in_link_clk;
228 s64 ratio_by_tu_fp;
229 s64 average_valid2_fp;
230 int new_valid_boundary_link;
231 int remainder_symbols_exist;
232 int n_symbols;
233 s64 n_remainder_symbols_per_lane_fp;
234 s64 last_partial_tu_fp;
235 s64 TU_ratio_err_fp;
236
237 int n_tus_incl_last_incomplete_tu;
238 int extra_pclk_cycles_tmp;
239 int extra_pclk_cycles_in_link_clk_tmp;
240 int extra_required_bytes_new_tmp;
241 int filler_size_tmp;
242 int lower_filler_size_tmp;
243 int delay_start_link_tmp;
244
245 bool boundary_moderation_en;
246 int boundary_mod_lower_err;
247 int upper_boundary_count;
248 int lower_boundary_count;
249 int i_upper_boundary_count;
250 int i_lower_boundary_count;
251 int valid_lower_boundary_link;
252 int even_distribution_BF;
253 int even_distribution_legacy;
254 int even_distribution;
255 int min_hblank_violated;
256 s64 delay_start_time_fp;
257 s64 hbp_time_fp;
258 s64 hactive_time_fp;
259 s64 diff_abs_fp;
260
261 s64 ratio;
262 };
263
264 static int _tu_param_compare(s64 a, s64 b)
265 {
266 u32 a_sign;
267 u32 b_sign;
268 s64 a_temp, b_temp, minus_1;
269
270 if (a == b)
271 return 0;
272
273 minus_1 = drm_fixp_from_fraction(-1, 1);
274
275 a_sign = (a >> 32) & 0x80000000 ? 1 : 0;
276
277 b_sign = (b >> 32) & 0x80000000 ? 1 : 0;
278
279 if (a_sign > b_sign)
280 return 2;
281 else if (b_sign > a_sign)
282 return 1;
283
284 if (!a_sign && !b_sign) { /* positive */
285 if (a > b)
286 return 1;
287 else
288 return 2;
289 } else { /* negative */
290 a_temp = drm_fixp_mul(a, minus_1);
291 b_temp = drm_fixp_mul(b, minus_1);
292
293 if (a_temp > b_temp)
294 return 2;
295 else
296 return 1;
297 }
298 }
299
300 static void dp_panel_update_tu_timings(struct dp_tu_calc_input *in,
301 struct tu_algo_data *tu)
302 {
303 int nlanes = in->nlanes;
304 int dsc_num_slices = in->num_of_dsc_slices;
305 int dsc_num_bytes = 0;
306 int numerator;
307 s64 pclk_dsc_fp;
308 s64 dwidth_dsc_fp;
309 s64 hbp_dsc_fp;
310
311 int tot_num_eoc_symbols = 0;
312 int tot_num_hor_bytes = 0;
313 int tot_num_dummy_bytes = 0;
314 int dwidth_dsc_bytes = 0;
315 int eoc_bytes = 0;
316
317 s64 temp1_fp, temp2_fp, temp3_fp;
318
319 tu->lclk_fp = drm_fixp_from_fraction(in->lclk, 1);
320 tu->pclk_fp = drm_fixp_from_fraction(in->pclk_khz, 1000);
321 tu->lwidth = in->hactive;
322 tu->hbp_relative_to_pclk = in->hporch;
323 tu->nlanes = in->nlanes;
324 tu->bpp = in->bpp;
325 tu->pixelEnc = in->pixel_enc;
326 tu->dsc_en = in->dsc_en;
327 tu->async_en = in->async_en;
328 tu->lwidth_fp = drm_fixp_from_fraction(in->hactive, 1);
329 tu->hbp_relative_to_pclk_fp = drm_fixp_from_fraction(in->hporch, 1);
330
331 if (tu->pixelEnc == 420) {
332 temp1_fp = drm_fixp_from_fraction(2, 1);
333 tu->pclk_fp = drm_fixp_div(tu->pclk_fp, temp1_fp);
334 tu->lwidth_fp = drm_fixp_div(tu->lwidth_fp, temp1_fp);
335 tu->hbp_relative_to_pclk_fp =
336 drm_fixp_div(tu->hbp_relative_to_pclk_fp, 2);
337 }
338
339 if (tu->pixelEnc == 422) {
340 switch (tu->bpp) {
341 case 24:
342 tu->bpp = 16;
343 tu->bpc = 8;
344 break;
345 case 30:
346 tu->bpp = 20;
347 tu->bpc = 10;
348 break;
349 default:
350 tu->bpp = 16;
351 tu->bpc = 8;
352 break;
353 }
354 } else {
355 tu->bpc = tu->bpp/3;
356 }
357
358 if (!in->dsc_en)
359 goto fec_check;
360
361 temp1_fp = drm_fixp_from_fraction(in->compress_ratio, 100);
362 temp2_fp = drm_fixp_from_fraction(in->bpp, 1);
363 temp3_fp = drm_fixp_div(temp2_fp, temp1_fp);
364 temp2_fp = drm_fixp_mul(tu->lwidth_fp, temp3_fp);
365
366 temp1_fp = drm_fixp_from_fraction(8, 1);
367 temp3_fp = drm_fixp_div(temp2_fp, temp1_fp);
368
369 numerator = drm_fixp2int(temp3_fp);
370
371 dsc_num_bytes = numerator / dsc_num_slices;
372 eoc_bytes = dsc_num_bytes % nlanes;
373 tot_num_eoc_symbols = nlanes * dsc_num_slices;
374 tot_num_hor_bytes = dsc_num_bytes * dsc_num_slices;
375 tot_num_dummy_bytes = (nlanes - eoc_bytes) * dsc_num_slices;
376
377 if (dsc_num_bytes == 0)
378 pr_info("incorrect no of bytes per slice=%d\n", dsc_num_bytes);
379
380 dwidth_dsc_bytes = (tot_num_hor_bytes +
381 tot_num_eoc_symbols +
382 (eoc_bytes == 0 ? 0 : tot_num_dummy_bytes));
383
384 dwidth_dsc_fp = drm_fixp_from_fraction(dwidth_dsc_bytes, 3);
385
386 temp2_fp = drm_fixp_mul(tu->pclk_fp, dwidth_dsc_fp);
387 temp1_fp = drm_fixp_div(temp2_fp, tu->lwidth_fp);
388 pclk_dsc_fp = temp1_fp;
389
390 temp1_fp = drm_fixp_div(pclk_dsc_fp, tu->pclk_fp);
391 temp2_fp = drm_fixp_mul(tu->hbp_relative_to_pclk_fp, temp1_fp);
392 hbp_dsc_fp = temp2_fp;
393
394 /* output */
395 tu->pclk_fp = pclk_dsc_fp;
396 tu->lwidth_fp = dwidth_dsc_fp;
397 tu->hbp_relative_to_pclk_fp = hbp_dsc_fp;
398
399 fec_check:
400 if (in->fec_en) {
401 temp1_fp = drm_fixp_from_fraction(976, 1000); /* 0.976 */
402 tu->lclk_fp = drm_fixp_mul(tu->lclk_fp, temp1_fp);
403 }
404 }
405
406 static void _tu_valid_boundary_calc(struct tu_algo_data *tu)
407 {
408 s64 temp1_fp, temp2_fp, temp, temp1, temp2;
409 int compare_result_1, compare_result_2, compare_result_3;
410
411 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1);
412 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp);
413
414 tu->new_valid_boundary_link = drm_fixp2int_ceil(temp2_fp);
415
416 temp = (tu->i_upper_boundary_count *
417 tu->new_valid_boundary_link +
418 tu->i_lower_boundary_count *
419 (tu->new_valid_boundary_link-1));
420 tu->average_valid2_fp = drm_fixp_from_fraction(temp,
421 (tu->i_upper_boundary_count +
422 tu->i_lower_boundary_count));
423
424 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8);
425 temp2_fp = tu->lwidth_fp;
426 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp);
427 temp2_fp = drm_fixp_div(temp1_fp, tu->average_valid2_fp);
428 tu->n_tus = drm_fixp2int(temp2_fp);
429 if ((temp2_fp & 0xFFFFFFFF) > 0xFFFFF000)
430 tu->n_tus += 1;
431
432 temp1_fp = drm_fixp_from_fraction(tu->n_tus, 1);
433 temp2_fp = drm_fixp_mul(temp1_fp, tu->average_valid2_fp);
434 temp1_fp = drm_fixp_from_fraction(tu->n_symbols, 1);
435 temp2_fp = temp1_fp - temp2_fp;
436 temp1_fp = drm_fixp_from_fraction(tu->nlanes, 1);
437 temp2_fp = drm_fixp_div(temp2_fp, temp1_fp);
438 tu->n_remainder_symbols_per_lane_fp = temp2_fp;
439
440 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1);
441 tu->last_partial_tu_fp =
442 drm_fixp_div(tu->n_remainder_symbols_per_lane_fp,
443 temp1_fp);
444
445 if (tu->n_remainder_symbols_per_lane_fp != 0)
446 tu->remainder_symbols_exist = 1;
447 else
448 tu->remainder_symbols_exist = 0;
449
450 temp1_fp = drm_fixp_from_fraction(tu->n_tus, tu->nlanes);
451 tu->n_tus_per_lane = drm_fixp2int(temp1_fp);
452
453 tu->paired_tus = (int)((tu->n_tus_per_lane) /
454 (tu->i_upper_boundary_count +
455 tu->i_lower_boundary_count));
456
457 tu->remainder_tus = tu->n_tus_per_lane - tu->paired_tus *
458 (tu->i_upper_boundary_count +
459 tu->i_lower_boundary_count);
460
461 if ((tu->remainder_tus - tu->i_upper_boundary_count) > 0) {
462 tu->remainder_tus_upper = tu->i_upper_boundary_count;
463 tu->remainder_tus_lower = tu->remainder_tus -
464 tu->i_upper_boundary_count;
465 } else {
466 tu->remainder_tus_upper = tu->remainder_tus;
467 tu->remainder_tus_lower = 0;
468 }
469
470 temp = tu->paired_tus * (tu->i_upper_boundary_count *
471 tu->new_valid_boundary_link +
472 tu->i_lower_boundary_count *
473 (tu->new_valid_boundary_link - 1)) +
474 (tu->remainder_tus_upper *
475 tu->new_valid_boundary_link) +
476 (tu->remainder_tus_lower *
477 (tu->new_valid_boundary_link - 1));
478 tu->total_valid_fp = drm_fixp_from_fraction(temp, 1);
479
480 if (tu->remainder_symbols_exist) {
481 temp1_fp = tu->total_valid_fp +
482 tu->n_remainder_symbols_per_lane_fp;
483 temp2_fp = drm_fixp_from_fraction(tu->n_tus_per_lane, 1);
484 temp2_fp = temp2_fp + tu->last_partial_tu_fp;
485 temp1_fp = drm_fixp_div(temp1_fp, temp2_fp);
486 } else {
487 temp2_fp = drm_fixp_from_fraction(tu->n_tus_per_lane, 1);
488 temp1_fp = drm_fixp_div(tu->total_valid_fp, temp2_fp);
489 }
490 tu->effective_valid_fp = temp1_fp;
491
492 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1);
493 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp);
494 tu->n_n_err_fp = tu->effective_valid_fp - temp2_fp;
495
496 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1);
497 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp);
498 tu->n_err_fp = tu->average_valid2_fp - temp2_fp;
499
500 tu->even_distribution = tu->n_tus % tu->nlanes == 0 ? 1 : 0;
501
502 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8);
503 temp2_fp = tu->lwidth_fp;
504 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp);
505 temp2_fp = drm_fixp_div(temp1_fp, tu->average_valid2_fp);
506
507 if (temp2_fp)
508 tu->n_tus_incl_last_incomplete_tu = drm_fixp2int_ceil(temp2_fp);
509 else
510 tu->n_tus_incl_last_incomplete_tu = 0;
511
512 temp1 = 0;
513 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1);
514 temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp);
515 temp1_fp = tu->average_valid2_fp - temp2_fp;
516 temp2_fp = drm_fixp_from_fraction(tu->n_tus_incl_last_incomplete_tu, 1);
517 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp);
518
519 if (temp1_fp)
520 temp1 = drm_fixp2int_ceil(temp1_fp);
521
522 temp = tu->i_upper_boundary_count * tu->nlanes;
523 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1);
524 temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp);
525 temp1_fp = drm_fixp_from_fraction(tu->new_valid_boundary_link, 1);
526 temp2_fp = temp1_fp - temp2_fp;
527 temp1_fp = drm_fixp_from_fraction(temp, 1);
528 temp2_fp = drm_fixp_mul(temp1_fp, temp2_fp);
529
530 if (temp2_fp)
531 temp2 = drm_fixp2int_ceil(temp2_fp);
532 else
533 temp2 = 0;
534 tu->extra_required_bytes_new_tmp = (int)(temp1 + temp2);
535
536 temp1_fp = drm_fixp_from_fraction(8, tu->bpp);
537 temp2_fp = drm_fixp_from_fraction(
538 tu->extra_required_bytes_new_tmp, 1);
539 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp);
540
541 if (temp1_fp)
542 tu->extra_pclk_cycles_tmp = drm_fixp2int_ceil(temp1_fp);
543 else
544 tu->extra_pclk_cycles_tmp = 0;
545
546 temp1_fp = drm_fixp_from_fraction(tu->extra_pclk_cycles_tmp, 1);
547 temp2_fp = drm_fixp_div(tu->lclk_fp, tu->pclk_fp);
548 temp1_fp = drm_fixp_mul(temp1_fp, temp2_fp);
549
550 if (temp1_fp)
551 tu->extra_pclk_cycles_in_link_clk_tmp =
552 drm_fixp2int_ceil(temp1_fp);
553 else
554 tu->extra_pclk_cycles_in_link_clk_tmp = 0;
555
556 tu->filler_size_tmp = tu->tu_size - tu->new_valid_boundary_link;
557
558 tu->lower_filler_size_tmp = tu->filler_size_tmp + 1;
559
560 tu->delay_start_link_tmp = tu->extra_pclk_cycles_in_link_clk_tmp +
561 tu->lower_filler_size_tmp +
562 tu->extra_buffer_margin;
563
564 temp1_fp = drm_fixp_from_fraction(tu->delay_start_link_tmp, 1);
565 tu->delay_start_time_fp = drm_fixp_div(temp1_fp, tu->lclk_fp);
566
567 compare_result_1 = _tu_param_compare(tu->n_n_err_fp, tu->diff_abs_fp);
568 if (compare_result_1 == 2)
569 compare_result_1 = 1;
570 else
571 compare_result_1 = 0;
572
573 compare_result_2 = _tu_param_compare(tu->n_n_err_fp, tu->err_fp);
574 if (compare_result_2 == 2)
575 compare_result_2 = 1;
576 else
577 compare_result_2 = 0;
578
579 compare_result_3 = _tu_param_compare(tu->hbp_time_fp,
580 tu->delay_start_time_fp);
581 if (compare_result_3 == 2)
582 compare_result_3 = 0;
583 else
584 compare_result_3 = 1;
585
586 if (((tu->even_distribution == 1) ||
587 ((tu->even_distribution_BF == 0) &&
588 (tu->even_distribution_legacy == 0))) &&
589 tu->n_err_fp >= 0 && tu->n_n_err_fp >= 0 &&
590 compare_result_2 &&
591 (compare_result_1 || (tu->min_hblank_violated == 1)) &&
592 (tu->new_valid_boundary_link - 1) > 0 &&
593 compare_result_3 &&
594 (tu->delay_start_link_tmp <= 1023)) {
595 tu->upper_boundary_count = tu->i_upper_boundary_count;
596 tu->lower_boundary_count = tu->i_lower_boundary_count;
597 tu->err_fp = tu->n_n_err_fp;
598 tu->boundary_moderation_en = true;
599 tu->tu_size_desired = tu->tu_size;
600 tu->valid_boundary_link = tu->new_valid_boundary_link;
601 tu->effective_valid_recorded_fp = tu->effective_valid_fp;
602 tu->even_distribution_BF = 1;
603 tu->delay_start_link = tu->delay_start_link_tmp;
604 } else if (tu->boundary_mod_lower_err == 0) {
605 compare_result_1 = _tu_param_compare(tu->n_n_err_fp,
606 tu->diff_abs_fp);
607 if (compare_result_1 == 2)
608 tu->boundary_mod_lower_err = 1;
609 }
610 }
611
612 static void _dp_ctrl_calc_tu(struct dp_ctrl_private *ctrl,
613 struct dp_tu_calc_input *in,
614 struct dp_vc_tu_mapping_table *tu_table)
615 {
616 struct tu_algo_data *tu;
617 int compare_result_1, compare_result_2;
618 u64 temp = 0;
619 s64 temp_fp = 0, temp1_fp = 0, temp2_fp = 0;
620
621 s64 LCLK_FAST_SKEW_fp = drm_fixp_from_fraction(6, 10000); /* 0.0006 */
622 s64 const_p49_fp = drm_fixp_from_fraction(49, 100); /* 0.49 */
623 s64 const_p56_fp = drm_fixp_from_fraction(56, 100); /* 0.56 */
624 s64 RATIO_SCALE_fp = drm_fixp_from_fraction(1001, 1000);
625
626 u8 DP_BRUTE_FORCE = 1;
627 s64 BRUTE_FORCE_THRESHOLD_fp = drm_fixp_from_fraction(1, 10); /* 0.1 */
628 uint EXTRA_PIXCLK_CYCLE_DELAY = 4;
629 uint HBLANK_MARGIN = 4;
630
631 tu = kzalloc(sizeof(*tu), GFP_KERNEL);
632 if (!tu)
633 return;
634
635 dp_panel_update_tu_timings(in, tu);
636
637 tu->err_fp = drm_fixp_from_fraction(1000, 1); /* 1000 */
638
639 temp1_fp = drm_fixp_from_fraction(4, 1);
640 temp2_fp = drm_fixp_mul(temp1_fp, tu->lclk_fp);
641 temp_fp = drm_fixp_div(temp2_fp, tu->pclk_fp);
642 tu->extra_buffer_margin = drm_fixp2int_ceil(temp_fp);
643
644 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8);
645 temp2_fp = drm_fixp_mul(tu->pclk_fp, temp1_fp);
646 temp1_fp = drm_fixp_from_fraction(tu->nlanes, 1);
647 temp2_fp = drm_fixp_div(temp2_fp, temp1_fp);
648 tu->ratio_fp = drm_fixp_div(temp2_fp, tu->lclk_fp);
649
650 tu->original_ratio_fp = tu->ratio_fp;
651 tu->boundary_moderation_en = false;
652 tu->upper_boundary_count = 0;
653 tu->lower_boundary_count = 0;
654 tu->i_upper_boundary_count = 0;
655 tu->i_lower_boundary_count = 0;
656 tu->valid_lower_boundary_link = 0;
657 tu->even_distribution_BF = 0;
658 tu->even_distribution_legacy = 0;
659 tu->even_distribution = 0;
660 tu->delay_start_time_fp = 0;
661
662 tu->err_fp = drm_fixp_from_fraction(1000, 1);
663 tu->n_err_fp = 0;
664 tu->n_n_err_fp = 0;
665
666 tu->ratio = drm_fixp2int(tu->ratio_fp);
667 temp1_fp = drm_fixp_from_fraction(tu->nlanes, 1);
668 div64_u64_rem(tu->lwidth_fp, temp1_fp, &temp2_fp);
669 if (temp2_fp != 0 &&
670 !tu->ratio && tu->dsc_en == 0) {
671 tu->ratio_fp = drm_fixp_mul(tu->ratio_fp, RATIO_SCALE_fp);
672 tu->ratio = drm_fixp2int(tu->ratio_fp);
673 if (tu->ratio)
674 tu->ratio_fp = drm_fixp_from_fraction(1, 1);
675 }
676
677 if (tu->ratio > 1)
678 tu->ratio = 1;
679
680 if (tu->ratio == 1)
681 goto tu_size_calc;
682
683 compare_result_1 = _tu_param_compare(tu->ratio_fp, const_p49_fp);
684 if (!compare_result_1 || compare_result_1 == 1)
685 compare_result_1 = 1;
686 else
687 compare_result_1 = 0;
688
689 compare_result_2 = _tu_param_compare(tu->ratio_fp, const_p56_fp);
690 if (!compare_result_2 || compare_result_2 == 2)
691 compare_result_2 = 1;
692 else
693 compare_result_2 = 0;
694
695 if (tu->dsc_en && compare_result_1 && compare_result_2) {
696 HBLANK_MARGIN += 4;
697 drm_dbg_dp(ctrl->drm_dev,
698 "increase HBLANK_MARGIN to %d\n", HBLANK_MARGIN);
699 }
700
701 tu_size_calc:
702 for (tu->tu_size = 32; tu->tu_size <= 64; tu->tu_size++) {
703 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1);
704 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp);
705 temp = drm_fixp2int_ceil(temp2_fp);
706 temp1_fp = drm_fixp_from_fraction(temp, 1);
707 tu->n_err_fp = temp1_fp - temp2_fp;
708
709 if (tu->n_err_fp < tu->err_fp) {
710 tu->err_fp = tu->n_err_fp;
711 tu->tu_size_desired = tu->tu_size;
712 }
713 }
714
715 tu->tu_size_minus1 = tu->tu_size_desired - 1;
716
717 temp1_fp = drm_fixp_from_fraction(tu->tu_size_desired, 1);
718 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp);
719 tu->valid_boundary_link = drm_fixp2int_ceil(temp2_fp);
720
721 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8);
722 temp2_fp = tu->lwidth_fp;
723 temp2_fp = drm_fixp_mul(temp2_fp, temp1_fp);
724
725 temp1_fp = drm_fixp_from_fraction(tu->valid_boundary_link, 1);
726 temp2_fp = drm_fixp_div(temp2_fp, temp1_fp);
727 tu->n_tus = drm_fixp2int(temp2_fp);
728 if ((temp2_fp & 0xFFFFFFFF) > 0xFFFFF000)
729 tu->n_tus += 1;
730
731 tu->even_distribution_legacy = tu->n_tus % tu->nlanes == 0 ? 1 : 0;
732
733 drm_dbg_dp(ctrl->drm_dev,
734 "n_sym = %d, num_of_tus = %d\n",
735 tu->valid_boundary_link, tu->n_tus);
736
737 temp1_fp = drm_fixp_from_fraction(tu->tu_size_desired, 1);
738 temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp);
739 temp1_fp = drm_fixp_from_fraction(tu->valid_boundary_link, 1);
740 temp2_fp = temp1_fp - temp2_fp;
741 temp1_fp = drm_fixp_from_fraction(tu->n_tus + 1, 1);
742 temp2_fp = drm_fixp_mul(temp1_fp, temp2_fp);
743
744 temp = drm_fixp2int(temp2_fp);
745 if (temp && temp2_fp)
746 tu->extra_bytes = drm_fixp2int_ceil(temp2_fp);
747 else
748 tu->extra_bytes = 0;
749
750 temp1_fp = drm_fixp_from_fraction(tu->extra_bytes, 1);
751 temp2_fp = drm_fixp_from_fraction(8, tu->bpp);
752 temp1_fp = drm_fixp_mul(temp1_fp, temp2_fp);
753
754 if (temp && temp1_fp)
755 tu->extra_pclk_cycles = drm_fixp2int_ceil(temp1_fp);
756 else
757 tu->extra_pclk_cycles = drm_fixp2int(temp1_fp);
758
759 temp1_fp = drm_fixp_div(tu->lclk_fp, tu->pclk_fp);
760 temp2_fp = drm_fixp_from_fraction(tu->extra_pclk_cycles, 1);
761 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp);
762
763 if (temp1_fp)
764 tu->extra_pclk_cycles_in_link_clk = drm_fixp2int_ceil(temp1_fp);
765 else
766 tu->extra_pclk_cycles_in_link_clk = drm_fixp2int(temp1_fp);
767
768 tu->filler_size = tu->tu_size_desired - tu->valid_boundary_link;
769
770 temp1_fp = drm_fixp_from_fraction(tu->tu_size_desired, 1);
771 tu->ratio_by_tu_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp);
772
773 tu->delay_start_link = tu->extra_pclk_cycles_in_link_clk +
774 tu->filler_size + tu->extra_buffer_margin;
775
776 tu->resulting_valid_fp =
777 drm_fixp_from_fraction(tu->valid_boundary_link, 1);
778
779 temp1_fp = drm_fixp_from_fraction(tu->tu_size_desired, 1);
780 temp2_fp = drm_fixp_div(tu->resulting_valid_fp, temp1_fp);
781 tu->TU_ratio_err_fp = temp2_fp - tu->original_ratio_fp;
782
783 temp1_fp = drm_fixp_from_fraction(HBLANK_MARGIN, 1);
784 temp1_fp = tu->hbp_relative_to_pclk_fp - temp1_fp;
785 tu->hbp_time_fp = drm_fixp_div(temp1_fp, tu->pclk_fp);
786
787 temp1_fp = drm_fixp_from_fraction(tu->delay_start_link, 1);
788 tu->delay_start_time_fp = drm_fixp_div(temp1_fp, tu->lclk_fp);
789
790 compare_result_1 = _tu_param_compare(tu->hbp_time_fp,
791 tu->delay_start_time_fp);
792 if (compare_result_1 == 2) /* if (hbp_time_fp < delay_start_time_fp) */
793 tu->min_hblank_violated = 1;
794
795 tu->hactive_time_fp = drm_fixp_div(tu->lwidth_fp, tu->pclk_fp);
796
797 compare_result_2 = _tu_param_compare(tu->hactive_time_fp,
798 tu->delay_start_time_fp);
799 if (compare_result_2 == 2)
800 tu->min_hblank_violated = 1;
801
802 tu->delay_start_time_fp = 0;
803
804 /* brute force */
805
806 tu->delay_start_link_extra_pixclk = EXTRA_PIXCLK_CYCLE_DELAY;
807 tu->diff_abs_fp = tu->resulting_valid_fp - tu->ratio_by_tu_fp;
808
809 temp = drm_fixp2int(tu->diff_abs_fp);
810 if (!temp && tu->diff_abs_fp <= 0xffff)
811 tu->diff_abs_fp = 0;
812
813 /* if(diff_abs < 0) diff_abs *= -1 */
814 if (tu->diff_abs_fp < 0)
815 tu->diff_abs_fp = drm_fixp_mul(tu->diff_abs_fp, -1);
816
817 tu->boundary_mod_lower_err = 0;
818 if ((tu->diff_abs_fp != 0 &&
819 ((tu->diff_abs_fp > BRUTE_FORCE_THRESHOLD_fp) ||
820 (tu->even_distribution_legacy == 0) ||
821 (DP_BRUTE_FORCE == 1))) ||
822 (tu->min_hblank_violated == 1)) {
823 do {
824 tu->err_fp = drm_fixp_from_fraction(1000, 1);
825
826 temp1_fp = drm_fixp_div(tu->lclk_fp, tu->pclk_fp);
827 temp2_fp = drm_fixp_from_fraction(
828 tu->delay_start_link_extra_pixclk, 1);
829 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp);
830
831 if (temp1_fp)
832 tu->extra_buffer_margin =
833 drm_fixp2int_ceil(temp1_fp);
834 else
835 tu->extra_buffer_margin = 0;
836
837 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8);
838 temp1_fp = drm_fixp_mul(tu->lwidth_fp, temp1_fp);
839
840 if (temp1_fp)
841 tu->n_symbols = drm_fixp2int_ceil(temp1_fp);
842 else
843 tu->n_symbols = 0;
844
845 for (tu->tu_size = 32; tu->tu_size <= 64; tu->tu_size++) {
846 for (tu->i_upper_boundary_count = 1;
847 tu->i_upper_boundary_count <= 15;
848 tu->i_upper_boundary_count++) {
849 for (tu->i_lower_boundary_count = 1;
850 tu->i_lower_boundary_count <= 15;
851 tu->i_lower_boundary_count++) {
852 _tu_valid_boundary_calc(tu);
853 }
854 }
855 }
856 tu->delay_start_link_extra_pixclk--;
857 } while (tu->boundary_moderation_en != true &&
858 tu->boundary_mod_lower_err == 1 &&
859 tu->delay_start_link_extra_pixclk != 0);
860
861 if (tu->boundary_moderation_en == true) {
862 temp1_fp = drm_fixp_from_fraction(
863 (tu->upper_boundary_count *
864 tu->valid_boundary_link +
865 tu->lower_boundary_count *
866 (tu->valid_boundary_link - 1)), 1);
867 temp2_fp = drm_fixp_from_fraction(
868 (tu->upper_boundary_count +
869 tu->lower_boundary_count), 1);
870 tu->resulting_valid_fp =
871 drm_fixp_div(temp1_fp, temp2_fp);
872
873 temp1_fp = drm_fixp_from_fraction(
874 tu->tu_size_desired, 1);
875 tu->ratio_by_tu_fp =
876 drm_fixp_mul(tu->original_ratio_fp, temp1_fp);
877
878 tu->valid_lower_boundary_link =
879 tu->valid_boundary_link - 1;
880
881 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8);
882 temp1_fp = drm_fixp_mul(tu->lwidth_fp, temp1_fp);
883 temp2_fp = drm_fixp_div(temp1_fp,
884 tu->resulting_valid_fp);
885 tu->n_tus = drm_fixp2int(temp2_fp);
886
887 tu->tu_size_minus1 = tu->tu_size_desired - 1;
888 tu->even_distribution_BF = 1;
889
890 temp1_fp =
891 drm_fixp_from_fraction(tu->tu_size_desired, 1);
892 temp2_fp =
893 drm_fixp_div(tu->resulting_valid_fp, temp1_fp);
894 tu->TU_ratio_err_fp = temp2_fp - tu->original_ratio_fp;
895 }
896 }
897
898 temp2_fp = drm_fixp_mul(LCLK_FAST_SKEW_fp, tu->lwidth_fp);
899
900 if (temp2_fp)
901 temp = drm_fixp2int_ceil(temp2_fp);
902 else
903 temp = 0;
904
905 temp1_fp = drm_fixp_from_fraction(tu->nlanes, 1);
906 temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp);
907 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8);
908 temp2_fp = drm_fixp_div(temp1_fp, temp2_fp);
909 temp1_fp = drm_fixp_from_fraction(temp, 1);
910 temp2_fp = drm_fixp_mul(temp1_fp, temp2_fp);
911 temp = drm_fixp2int(temp2_fp);
912
913 if (tu->async_en)
914 tu->delay_start_link += (int)temp;
915
916 temp1_fp = drm_fixp_from_fraction(tu->delay_start_link, 1);
917 tu->delay_start_time_fp = drm_fixp_div(temp1_fp, tu->lclk_fp);
918
919 /* OUTPUTS */
920 tu_table->valid_boundary_link = tu->valid_boundary_link;
921 tu_table->delay_start_link = tu->delay_start_link;
922 tu_table->boundary_moderation_en = tu->boundary_moderation_en;
923 tu_table->valid_lower_boundary_link = tu->valid_lower_boundary_link;
924 tu_table->upper_boundary_count = tu->upper_boundary_count;
925 tu_table->lower_boundary_count = tu->lower_boundary_count;
926 tu_table->tu_size_minus1 = tu->tu_size_minus1;
927
928 drm_dbg_dp(ctrl->drm_dev, "TU: valid_boundary_link: %d\n",
929 tu_table->valid_boundary_link);
930 drm_dbg_dp(ctrl->drm_dev, "TU: delay_start_link: %d\n",
931 tu_table->delay_start_link);
932 drm_dbg_dp(ctrl->drm_dev, "TU: boundary_moderation_en: %d\n",
933 tu_table->boundary_moderation_en);
934 drm_dbg_dp(ctrl->drm_dev, "TU: valid_lower_boundary_link: %d\n",
935 tu_table->valid_lower_boundary_link);
936 drm_dbg_dp(ctrl->drm_dev, "TU: upper_boundary_count: %d\n",
937 tu_table->upper_boundary_count);
938 drm_dbg_dp(ctrl->drm_dev, "TU: lower_boundary_count: %d\n",
939 tu_table->lower_boundary_count);
940 drm_dbg_dp(ctrl->drm_dev, "TU: tu_size_minus1: %d\n",
941 tu_table->tu_size_minus1);
942
943 kfree(tu);
944 }
945
946 static void dp_ctrl_calc_tu_parameters(struct dp_ctrl_private *ctrl,
947 struct dp_vc_tu_mapping_table *tu_table)
948 {
949 struct dp_tu_calc_input in;
950 struct drm_display_mode *drm_mode;
951
952 drm_mode = &ctrl->panel->dp_mode.drm_mode;
953
954 in.lclk = ctrl->link->link_params.rate / 1000;
955 in.pclk_khz = drm_mode->clock;
956 in.hactive = drm_mode->hdisplay;
957 in.hporch = drm_mode->htotal - drm_mode->hdisplay;
958 in.nlanes = ctrl->link->link_params.num_lanes;
959 in.bpp = ctrl->panel->dp_mode.bpp;
960 in.pixel_enc = 444;
961 in.dsc_en = 0;
962 in.async_en = 0;
963 in.fec_en = 0;
964 in.num_of_dsc_slices = 0;
965 in.compress_ratio = 100;
966
967 _dp_ctrl_calc_tu(ctrl, &in, tu_table);
968 }
969
970 static void dp_ctrl_setup_tr_unit(struct dp_ctrl_private *ctrl)
971 {
972 u32 dp_tu = 0x0;
973 u32 valid_boundary = 0x0;
974 u32 valid_boundary2 = 0x0;
975 struct dp_vc_tu_mapping_table tu_calc_table;
976
977 dp_ctrl_calc_tu_parameters(ctrl, &tu_calc_table);
978
979 dp_tu |= tu_calc_table.tu_size_minus1;
980 valid_boundary |= tu_calc_table.valid_boundary_link;
981 valid_boundary |= (tu_calc_table.delay_start_link << 16);
982
983 valid_boundary2 |= (tu_calc_table.valid_lower_boundary_link << 1);
984 valid_boundary2 |= (tu_calc_table.upper_boundary_count << 16);
985 valid_boundary2 |= (tu_calc_table.lower_boundary_count << 20);
986
987 if (tu_calc_table.boundary_moderation_en)
988 valid_boundary2 |= BIT(0);
989
990 pr_debug("dp_tu=0x%x, valid_boundary=0x%x, valid_boundary2=0x%x\n",
991 dp_tu, valid_boundary, valid_boundary2);
992
993 dp_catalog_ctrl_update_transfer_unit(ctrl->catalog,
994 dp_tu, valid_boundary, valid_boundary2);
995 }
996
997 static int dp_ctrl_wait4video_ready(struct dp_ctrl_private *ctrl)
998 {
999 int ret = 0;
1000
1001 if (!wait_for_completion_timeout(&ctrl->video_comp,
1002 WAIT_FOR_VIDEO_READY_TIMEOUT_JIFFIES)) {
1003 DRM_ERROR("wait4video timedout\n");
1004 ret = -ETIMEDOUT;
1005 }
1006 return ret;
1007 }
1008
1009 static int dp_ctrl_update_vx_px(struct dp_ctrl_private *ctrl)
1010 {
1011 struct dp_link *link = ctrl->link;
1012 int ret = 0, lane, lane_cnt;
1013 u8 buf[4];
1014 u32 max_level_reached = 0;
1015 u32 voltage_swing_level = link->phy_params.v_level;
1016 u32 pre_emphasis_level = link->phy_params.p_level;
1017
1018 drm_dbg_dp(ctrl->drm_dev,
1019 "voltage level: %d emphasis level: %d\n",
1020 voltage_swing_level, pre_emphasis_level);
1021 ret = dp_catalog_ctrl_update_vx_px(ctrl->catalog,
1022 voltage_swing_level, pre_emphasis_level);
1023
1024 if (ret)
1025 return ret;
1026
1027 if (voltage_swing_level >= DP_TRAIN_VOLTAGE_SWING_MAX) {
1028 drm_dbg_dp(ctrl->drm_dev,
1029 "max. voltage swing level reached %d\n",
1030 voltage_swing_level);
1031 max_level_reached |= DP_TRAIN_MAX_SWING_REACHED;
1032 }
1033
1034 if (pre_emphasis_level >= DP_TRAIN_PRE_EMPHASIS_MAX) {
1035 drm_dbg_dp(ctrl->drm_dev,
1036 "max. pre-emphasis level reached %d\n",
1037 pre_emphasis_level);
1038 max_level_reached |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1039 }
1040
1041 pre_emphasis_level <<= DP_TRAIN_PRE_EMPHASIS_SHIFT;
1042
1043 lane_cnt = ctrl->link->link_params.num_lanes;
1044 for (lane = 0; lane < lane_cnt; lane++)
1045 buf[lane] = voltage_swing_level | pre_emphasis_level
1046 | max_level_reached;
1047
1048 drm_dbg_dp(ctrl->drm_dev, "sink: p|v=0x%x\n",
1049 voltage_swing_level | pre_emphasis_level);
1050 ret = drm_dp_dpcd_write(ctrl->aux, DP_TRAINING_LANE0_SET,
1051 buf, lane_cnt);
1052 if (ret == lane_cnt)
1053 ret = 0;
1054
1055 return ret;
1056 }
1057
1058 static bool dp_ctrl_train_pattern_set(struct dp_ctrl_private *ctrl,
1059 u8 pattern)
1060 {
1061 u8 buf;
1062 int ret = 0;
1063
1064 drm_dbg_dp(ctrl->drm_dev, "sink: pattern=%x\n", pattern);
1065
1066 buf = pattern;
1067
1068 if (pattern && pattern != DP_TRAINING_PATTERN_4)
1069 buf |= DP_LINK_SCRAMBLING_DISABLE;
1070
1071 ret = drm_dp_dpcd_writeb(ctrl->aux, DP_TRAINING_PATTERN_SET, buf);
1072 return ret == 1;
1073 }
1074
1075 static int dp_ctrl_read_link_status(struct dp_ctrl_private *ctrl,
1076 u8 *link_status)
1077 {
1078 int ret = 0, len;
1079
1080 len = drm_dp_dpcd_read_link_status(ctrl->aux, link_status);
1081 if (len != DP_LINK_STATUS_SIZE) {
1082 DRM_ERROR("DP link status read failed, err: %d\n", len);
1083 ret = -EINVAL;
1084 }
1085
1086 return ret;
1087 }
1088
1089 static int dp_ctrl_link_train_1(struct dp_ctrl_private *ctrl,
1090 int *training_step)
1091 {
1092 int tries, old_v_level, ret = 0;
1093 u8 link_status[DP_LINK_STATUS_SIZE];
1094 int const maximum_retries = 4;
1095
1096 dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0);
1097
1098 *training_step = DP_TRAINING_1;
1099
1100 ret = dp_catalog_ctrl_set_pattern_state_bit(ctrl->catalog, 1);
1101 if (ret)
1102 return ret;
1103 dp_ctrl_train_pattern_set(ctrl, DP_TRAINING_PATTERN_1 |
1104 DP_LINK_SCRAMBLING_DISABLE);
1105
1106 ret = dp_ctrl_update_vx_px(ctrl);
1107 if (ret)
1108 return ret;
1109
1110 tries = 0;
1111 old_v_level = ctrl->link->phy_params.v_level;
1112 for (tries = 0; tries < maximum_retries; tries++) {
1113 drm_dp_link_train_clock_recovery_delay(ctrl->aux, ctrl->panel->dpcd);
1114
1115 ret = dp_ctrl_read_link_status(ctrl, link_status);
1116 if (ret)
1117 return ret;
1118
1119 if (drm_dp_clock_recovery_ok(link_status,
1120 ctrl->link->link_params.num_lanes)) {
1121 return 0;
1122 }
1123
1124 if (ctrl->link->phy_params.v_level >=
1125 DP_TRAIN_VOLTAGE_SWING_MAX) {
1126 DRM_ERROR_RATELIMITED("max v_level reached\n");
1127 return -EAGAIN;
1128 }
1129
1130 if (old_v_level != ctrl->link->phy_params.v_level) {
1131 tries = 0;
1132 old_v_level = ctrl->link->phy_params.v_level;
1133 }
1134
1135 dp_link_adjust_levels(ctrl->link, link_status);
1136 ret = dp_ctrl_update_vx_px(ctrl);
1137 if (ret)
1138 return ret;
1139 }
1140
1141 DRM_ERROR("max tries reached\n");
1142 return -ETIMEDOUT;
1143 }
1144
1145 static int dp_ctrl_link_rate_down_shift(struct dp_ctrl_private *ctrl)
1146 {
1147 int ret = 0;
1148
1149 switch (ctrl->link->link_params.rate) {
1150 case 810000:
1151 ctrl->link->link_params.rate = 540000;
1152 break;
1153 case 540000:
1154 ctrl->link->link_params.rate = 270000;
1155 break;
1156 case 270000:
1157 ctrl->link->link_params.rate = 162000;
1158 break;
1159 case 162000:
1160 default:
1161 ret = -EINVAL;
1162 break;
1163 }
1164
1165 if (!ret) {
1166 drm_dbg_dp(ctrl->drm_dev, "new rate=0x%x\n",
1167 ctrl->link->link_params.rate);
1168 }
1169
1170 return ret;
1171 }
1172
1173 static int dp_ctrl_link_lane_down_shift(struct dp_ctrl_private *ctrl)
1174 {
1175
1176 if (ctrl->link->link_params.num_lanes == 1)
1177 return -1;
1178
1179 ctrl->link->link_params.num_lanes /= 2;
1180 ctrl->link->link_params.rate = ctrl->panel->link_info.rate;
1181
1182 ctrl->link->phy_params.p_level = 0;
1183 ctrl->link->phy_params.v_level = 0;
1184
1185 return 0;
1186 }
1187
1188 static void dp_ctrl_clear_training_pattern(struct dp_ctrl_private *ctrl)
1189 {
1190 dp_ctrl_train_pattern_set(ctrl, DP_TRAINING_PATTERN_DISABLE);
1191 drm_dp_link_train_channel_eq_delay(ctrl->aux, ctrl->panel->dpcd);
1192 }
1193
1194 static int dp_ctrl_link_train_2(struct dp_ctrl_private *ctrl,
1195 int *training_step)
1196 {
1197 int tries = 0, ret = 0;
1198 u8 pattern;
1199 u32 state_ctrl_bit;
1200 int const maximum_retries = 5;
1201 u8 link_status[DP_LINK_STATUS_SIZE];
1202
1203 dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0);
1204
1205 *training_step = DP_TRAINING_2;
1206
1207 if (drm_dp_tps4_supported(ctrl->panel->dpcd)) {
1208 pattern = DP_TRAINING_PATTERN_4;
1209 state_ctrl_bit = 4;
1210 } else if (drm_dp_tps3_supported(ctrl->panel->dpcd)) {
1211 pattern = DP_TRAINING_PATTERN_3;
1212 state_ctrl_bit = 3;
1213 } else {
1214 pattern = DP_TRAINING_PATTERN_2;
1215 state_ctrl_bit = 2;
1216 }
1217
1218 ret = dp_catalog_ctrl_set_pattern_state_bit(ctrl->catalog, state_ctrl_bit);
1219 if (ret)
1220 return ret;
1221
1222 dp_ctrl_train_pattern_set(ctrl, pattern);
1223
1224 for (tries = 0; tries <= maximum_retries; tries++) {
1225 drm_dp_link_train_channel_eq_delay(ctrl->aux, ctrl->panel->dpcd);
1226
1227 ret = dp_ctrl_read_link_status(ctrl, link_status);
1228 if (ret)
1229 return ret;
1230
1231 if (drm_dp_channel_eq_ok(link_status,
1232 ctrl->link->link_params.num_lanes)) {
1233 return 0;
1234 }
1235
1236 dp_link_adjust_levels(ctrl->link, link_status);
1237 ret = dp_ctrl_update_vx_px(ctrl);
1238 if (ret)
1239 return ret;
1240
1241 }
1242
1243 return -ETIMEDOUT;
1244 }
1245
1246 static int dp_ctrl_link_train(struct dp_ctrl_private *ctrl,
1247 int *training_step)
1248 {
1249 int ret = 0;
1250 const u8 *dpcd = ctrl->panel->dpcd;
1251 u8 encoding[] = { 0, DP_SET_ANSI_8B10B };
1252 u8 assr;
1253 struct dp_link_info link_info = {0};
1254
1255 dp_ctrl_config_ctrl(ctrl);
1256
1257 link_info.num_lanes = ctrl->link->link_params.num_lanes;
1258 link_info.rate = ctrl->link->link_params.rate;
1259 link_info.capabilities = DP_LINK_CAP_ENHANCED_FRAMING;
1260
1261 dp_aux_link_configure(ctrl->aux, &link_info);
1262
1263 if (drm_dp_max_downspread(dpcd))
1264 encoding[0] |= DP_SPREAD_AMP_0_5;
1265
1266 /* config DOWNSPREAD_CTRL and MAIN_LINK_CHANNEL_CODING_SET */
1267 drm_dp_dpcd_write(ctrl->aux, DP_DOWNSPREAD_CTRL, encoding, 2);
1268
1269 if (drm_dp_alternate_scrambler_reset_cap(dpcd)) {
1270 assr = DP_ALTERNATE_SCRAMBLER_RESET_ENABLE;
1271 drm_dp_dpcd_write(ctrl->aux, DP_EDP_CONFIGURATION_SET,
1272 &assr, 1);
1273 }
1274
1275 ret = dp_ctrl_link_train_1(ctrl, training_step);
1276 if (ret) {
1277 DRM_ERROR("link training #1 failed. ret=%d\n", ret);
1278 goto end;
1279 }
1280
1281 /* print success info as this is a result of user initiated action */
1282 drm_dbg_dp(ctrl->drm_dev, "link training #1 successful\n");
1283
1284 ret = dp_ctrl_link_train_2(ctrl, training_step);
1285 if (ret) {
1286 DRM_ERROR("link training #2 failed. ret=%d\n", ret);
1287 goto end;
1288 }
1289
1290 /* print success info as this is a result of user initiated action */
1291 drm_dbg_dp(ctrl->drm_dev, "link training #2 successful\n");
1292
1293 end:
1294 dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0);
1295
1296 return ret;
1297 }
1298
1299 static int dp_ctrl_setup_main_link(struct dp_ctrl_private *ctrl,
1300 int *training_step)
1301 {
1302 int ret = 0;
1303
1304 dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, true);
1305
1306 if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN)
1307 return ret;
1308
1309 /*
1310 * As part of previous calls, DP controller state might have
1311 * transitioned to PUSH_IDLE. In order to start transmitting
1312 * a link training pattern, we have to first do soft reset.
1313 */
1314
1315 ret = dp_ctrl_link_train(ctrl, training_step);
1316
1317 return ret;
1318 }
1319
1320 static void dp_ctrl_set_clock_rate(struct dp_ctrl_private *ctrl,
1321 enum dp_pm_type module, char *name, unsigned long rate)
1322 {
1323 u32 num = ctrl->parser->mp[module].num_clk;
1324 struct clk_bulk_data *cfg = ctrl->parser->mp[module].clocks;
1325
1326 while (num && strcmp(cfg->id, name)) {
1327 num--;
1328 cfg++;
1329 }
1330
1331 drm_dbg_dp(ctrl->drm_dev, "setting rate=%lu on clk=%s\n",
1332 rate, name);
1333
1334 if (num)
1335 clk_set_rate(cfg->clk, rate);
1336 else
1337 DRM_ERROR("%s clock doesn't exit to set rate %lu\n",
1338 name, rate);
1339 }
1340
1341 static int dp_ctrl_enable_mainlink_clocks(struct dp_ctrl_private *ctrl)
1342 {
1343 int ret = 0;
1344 struct dp_io *dp_io = &ctrl->parser->io;
1345 struct phy *phy = dp_io->phy;
1346 struct phy_configure_opts_dp *opts_dp = &dp_io->phy_opts.dp;
1347 const u8 *dpcd = ctrl->panel->dpcd;
1348
1349 opts_dp->lanes = ctrl->link->link_params.num_lanes;
1350 opts_dp->link_rate = ctrl->link->link_params.rate / 100;
1351 opts_dp->ssc = drm_dp_max_downspread(dpcd);
1352
1353 phy_configure(phy, &dp_io->phy_opts);
1354 phy_power_on(phy);
1355
1356 dev_pm_opp_set_rate(ctrl->dev, ctrl->link->link_params.rate * 1000);
1357 ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, true);
1358 if (ret)
1359 DRM_ERROR("Unable to start link clocks. ret=%d\n", ret);
1360
1361 drm_dbg_dp(ctrl->drm_dev, "link rate=%d\n", ctrl->link->link_params.rate);
1362
1363 return ret;
1364 }
1365
1366 void dp_ctrl_reset_irq_ctrl(struct dp_ctrl *dp_ctrl, bool enable)
1367 {
1368 struct dp_ctrl_private *ctrl;
1369
1370 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1371
1372 dp_catalog_ctrl_reset(ctrl->catalog);
1373
1374 /*
1375 * all dp controller programmable registers will not
1376 * be reset to default value after DP_SW_RESET
1377 * therefore interrupt mask bits have to be updated
1378 * to enable/disable interrupts
1379 */
1380 dp_catalog_ctrl_enable_irq(ctrl->catalog, enable);
1381 }
1382
1383 void dp_ctrl_config_psr(struct dp_ctrl *dp_ctrl)
1384 {
1385 u8 cfg;
1386 struct dp_ctrl_private *ctrl = container_of(dp_ctrl,
1387 struct dp_ctrl_private, dp_ctrl);
1388
1389 if (!ctrl->panel->psr_cap.version)
1390 return;
1391
1392 dp_catalog_ctrl_config_psr(ctrl->catalog);
1393
1394 cfg = DP_PSR_ENABLE;
1395 drm_dp_dpcd_write(ctrl->aux, DP_PSR_EN_CFG, &cfg, 1);
1396 }
1397
1398 void dp_ctrl_set_psr(struct dp_ctrl *dp_ctrl, bool enter)
1399 {
1400 struct dp_ctrl_private *ctrl = container_of(dp_ctrl,
1401 struct dp_ctrl_private, dp_ctrl);
1402
1403 if (!ctrl->panel->psr_cap.version)
1404 return;
1405
1406 /*
1407 * When entering PSR,
1408 * 1. Send PSR enter SDP and wait for the PSR_UPDATE_INT
1409 * 2. Turn off video
1410 * 3. Disable the mainlink
1411 *
1412 * When exiting PSR,
1413 * 1. Enable the mainlink
1414 * 2. Send the PSR exit SDP
1415 */
1416 if (enter) {
1417 reinit_completion(&ctrl->psr_op_comp);
1418 dp_catalog_ctrl_set_psr(ctrl->catalog, true);
1419
1420 if (!wait_for_completion_timeout(&ctrl->psr_op_comp,
1421 PSR_OPERATION_COMPLETION_TIMEOUT_JIFFIES)) {
1422 DRM_ERROR("PSR_ENTRY timedout\n");
1423 dp_catalog_ctrl_set_psr(ctrl->catalog, false);
1424 return;
1425 }
1426
1427 dp_ctrl_push_idle(dp_ctrl);
1428 dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0);
1429
1430 dp_catalog_ctrl_psr_mainlink_enable(ctrl->catalog, false);
1431 } else {
1432 dp_catalog_ctrl_psr_mainlink_enable(ctrl->catalog, true);
1433
1434 dp_catalog_ctrl_set_psr(ctrl->catalog, false);
1435 dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_SEND_VIDEO);
1436 dp_ctrl_wait4video_ready(ctrl);
1437 dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0);
1438 }
1439 }
1440
1441 void dp_ctrl_phy_init(struct dp_ctrl *dp_ctrl)
1442 {
1443 struct dp_ctrl_private *ctrl;
1444 struct dp_io *dp_io;
1445 struct phy *phy;
1446
1447 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1448 dp_io = &ctrl->parser->io;
1449 phy = dp_io->phy;
1450
1451 dp_catalog_ctrl_phy_reset(ctrl->catalog);
1452 phy_init(phy);
1453
1454 drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n",
1455 phy, phy->init_count, phy->power_count);
1456 }
1457
1458 void dp_ctrl_phy_exit(struct dp_ctrl *dp_ctrl)
1459 {
1460 struct dp_ctrl_private *ctrl;
1461 struct dp_io *dp_io;
1462 struct phy *phy;
1463
1464 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1465 dp_io = &ctrl->parser->io;
1466 phy = dp_io->phy;
1467
1468 dp_catalog_ctrl_phy_reset(ctrl->catalog);
1469 phy_exit(phy);
1470 drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n",
1471 phy, phy->init_count, phy->power_count);
1472 }
1473
1474 static bool dp_ctrl_use_fixed_nvid(struct dp_ctrl_private *ctrl)
1475 {
1476 const u8 *dpcd = ctrl->panel->dpcd;
1477
1478 /*
1479 * For better interop experience, used a fixed NVID=0x8000
1480 * whenever connected to a VGA dongle downstream.
1481 */
1482 if (drm_dp_is_branch(dpcd))
1483 return (drm_dp_has_quirk(&ctrl->panel->desc,
1484 DP_DPCD_QUIRK_CONSTANT_N));
1485
1486 return false;
1487 }
1488
1489 static int dp_ctrl_reinitialize_mainlink(struct dp_ctrl_private *ctrl)
1490 {
1491 int ret = 0;
1492 struct dp_io *dp_io = &ctrl->parser->io;
1493 struct phy *phy = dp_io->phy;
1494 struct phy_configure_opts_dp *opts_dp = &dp_io->phy_opts.dp;
1495
1496 dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false);
1497 opts_dp->lanes = ctrl->link->link_params.num_lanes;
1498 phy_configure(phy, &dp_io->phy_opts);
1499 /*
1500 * Disable and re-enable the mainlink clock since the
1501 * link clock might have been adjusted as part of the
1502 * link maintenance.
1503 */
1504 dev_pm_opp_set_rate(ctrl->dev, 0);
1505 ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false);
1506 if (ret) {
1507 DRM_ERROR("Failed to disable clocks. ret=%d\n", ret);
1508 return ret;
1509 }
1510 phy_power_off(phy);
1511 /* hw recommended delay before re-enabling clocks */
1512 msleep(20);
1513
1514 ret = dp_ctrl_enable_mainlink_clocks(ctrl);
1515 if (ret) {
1516 DRM_ERROR("Failed to enable mainlink clks. ret=%d\n", ret);
1517 return ret;
1518 }
1519
1520 return ret;
1521 }
1522
1523 static int dp_ctrl_deinitialize_mainlink(struct dp_ctrl_private *ctrl)
1524 {
1525 struct dp_io *dp_io;
1526 struct phy *phy;
1527 int ret;
1528
1529 dp_io = &ctrl->parser->io;
1530 phy = dp_io->phy;
1531
1532 dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false);
1533
1534 dp_catalog_ctrl_reset(ctrl->catalog);
1535
1536 dev_pm_opp_set_rate(ctrl->dev, 0);
1537 ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false);
1538 if (ret) {
1539 DRM_ERROR("Failed to disable link clocks. ret=%d\n", ret);
1540 }
1541
1542 phy_power_off(phy);
1543
1544 /* aux channel down, reinit phy */
1545 phy_exit(phy);
1546 phy_init(phy);
1547
1548 drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n",
1549 phy, phy->init_count, phy->power_count);
1550 return 0;
1551 }
1552
1553 static int dp_ctrl_link_maintenance(struct dp_ctrl_private *ctrl)
1554 {
1555 int ret = 0;
1556 int training_step = DP_TRAINING_NONE;
1557
1558 dp_ctrl_push_idle(&ctrl->dp_ctrl);
1559
1560 ctrl->link->phy_params.p_level = 0;
1561 ctrl->link->phy_params.v_level = 0;
1562
1563 ret = dp_ctrl_setup_main_link(ctrl, &training_step);
1564 if (ret)
1565 goto end;
1566
1567 dp_ctrl_clear_training_pattern(ctrl);
1568
1569 dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_SEND_VIDEO);
1570
1571 ret = dp_ctrl_wait4video_ready(ctrl);
1572 end:
1573 return ret;
1574 }
1575
1576 static bool dp_ctrl_send_phy_test_pattern(struct dp_ctrl_private *ctrl)
1577 {
1578 bool success = false;
1579 u32 pattern_sent = 0x0;
1580 u32 pattern_requested = ctrl->link->phy_params.phy_test_pattern_sel;
1581
1582 drm_dbg_dp(ctrl->drm_dev, "request: 0x%x\n", pattern_requested);
1583
1584 if (dp_catalog_ctrl_update_vx_px(ctrl->catalog,
1585 ctrl->link->phy_params.v_level,
1586 ctrl->link->phy_params.p_level)) {
1587 DRM_ERROR("Failed to set v/p levels\n");
1588 return false;
1589 }
1590 dp_catalog_ctrl_send_phy_pattern(ctrl->catalog, pattern_requested);
1591 dp_ctrl_update_vx_px(ctrl);
1592 dp_link_send_test_response(ctrl->link);
1593
1594 pattern_sent = dp_catalog_ctrl_read_phy_pattern(ctrl->catalog);
1595
1596 switch (pattern_sent) {
1597 case MR_LINK_TRAINING1:
1598 success = (pattern_requested ==
1599 DP_PHY_TEST_PATTERN_D10_2);
1600 break;
1601 case MR_LINK_SYMBOL_ERM:
1602 success = ((pattern_requested ==
1603 DP_PHY_TEST_PATTERN_ERROR_COUNT) ||
1604 (pattern_requested ==
1605 DP_PHY_TEST_PATTERN_CP2520));
1606 break;
1607 case MR_LINK_PRBS7:
1608 success = (pattern_requested ==
1609 DP_PHY_TEST_PATTERN_PRBS7);
1610 break;
1611 case MR_LINK_CUSTOM80:
1612 success = (pattern_requested ==
1613 DP_PHY_TEST_PATTERN_80BIT_CUSTOM);
1614 break;
1615 case MR_LINK_TRAINING4:
1616 success = (pattern_requested ==
1617 DP_PHY_TEST_PATTERN_SEL_MASK);
1618 break;
1619 default:
1620 success = false;
1621 }
1622
1623 drm_dbg_dp(ctrl->drm_dev, "%s: test->0x%x\n",
1624 success ? "success" : "failed", pattern_requested);
1625 return success;
1626 }
1627
1628 static int dp_ctrl_process_phy_test_request(struct dp_ctrl_private *ctrl)
1629 {
1630 int ret;
1631 unsigned long pixel_rate;
1632
1633 if (!ctrl->link->phy_params.phy_test_pattern_sel) {
1634 drm_dbg_dp(ctrl->drm_dev,
1635 "no test pattern selected by sink\n");
1636 return 0;
1637 }
1638
1639 /*
1640 * The global reset will need DP link related clocks to be
1641 * running. Add the global reset just before disabling the
1642 * link clocks and core clocks.
1643 */
1644 ret = dp_ctrl_off(&ctrl->dp_ctrl);
1645 if (ret) {
1646 DRM_ERROR("failed to disable DP controller\n");
1647 return ret;
1648 }
1649
1650 ret = dp_ctrl_on_link(&ctrl->dp_ctrl);
1651 if (ret) {
1652 DRM_ERROR("failed to enable DP link controller\n");
1653 return ret;
1654 }
1655
1656 pixel_rate = ctrl->panel->dp_mode.drm_mode.clock;
1657 dp_ctrl_set_clock_rate(ctrl, DP_STREAM_PM, "stream_pixel", pixel_rate * 1000);
1658
1659 ret = dp_power_clk_enable(ctrl->power, DP_STREAM_PM, true);
1660 if (ret) {
1661 DRM_ERROR("Failed to start pixel clocks. ret=%d\n", ret);
1662 return ret;
1663 }
1664
1665 dp_ctrl_send_phy_test_pattern(ctrl);
1666
1667 return 0;
1668 }
1669
1670 void dp_ctrl_handle_sink_request(struct dp_ctrl *dp_ctrl)
1671 {
1672 struct dp_ctrl_private *ctrl;
1673 u32 sink_request = 0x0;
1674
1675 if (!dp_ctrl) {
1676 DRM_ERROR("invalid input\n");
1677 return;
1678 }
1679
1680 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1681 sink_request = ctrl->link->sink_request;
1682
1683 if (sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) {
1684 drm_dbg_dp(ctrl->drm_dev, "PHY_TEST_PATTERN request\n");
1685 if (dp_ctrl_process_phy_test_request(ctrl)) {
1686 DRM_ERROR("process phy_test_req failed\n");
1687 return;
1688 }
1689 }
1690
1691 if (sink_request & DP_LINK_STATUS_UPDATED) {
1692 if (dp_ctrl_link_maintenance(ctrl)) {
1693 DRM_ERROR("LM failed: TEST_LINK_TRAINING\n");
1694 return;
1695 }
1696 }
1697
1698 if (sink_request & DP_TEST_LINK_TRAINING) {
1699 dp_link_send_test_response(ctrl->link);
1700 if (dp_ctrl_link_maintenance(ctrl)) {
1701 DRM_ERROR("LM failed: TEST_LINK_TRAINING\n");
1702 return;
1703 }
1704 }
1705 }
1706
1707 static bool dp_ctrl_clock_recovery_any_ok(
1708 const u8 link_status[DP_LINK_STATUS_SIZE],
1709 int lane_count)
1710 {
1711 int reduced_cnt;
1712
1713 if (lane_count <= 1)
1714 return false;
1715
1716 /*
1717 * only interested in the lane number after reduced
1718 * lane_count = 4, then only interested in 2 lanes
1719 * lane_count = 2, then only interested in 1 lane
1720 */
1721 reduced_cnt = lane_count >> 1;
1722
1723 return drm_dp_clock_recovery_ok(link_status, reduced_cnt);
1724 }
1725
1726 static bool dp_ctrl_channel_eq_ok(struct dp_ctrl_private *ctrl)
1727 {
1728 u8 link_status[DP_LINK_STATUS_SIZE];
1729 int num_lanes = ctrl->link->link_params.num_lanes;
1730
1731 dp_ctrl_read_link_status(ctrl, link_status);
1732
1733 return drm_dp_channel_eq_ok(link_status, num_lanes);
1734 }
1735
1736 int dp_ctrl_on_link(struct dp_ctrl *dp_ctrl)
1737 {
1738 int rc = 0;
1739 struct dp_ctrl_private *ctrl;
1740 u32 rate;
1741 int link_train_max_retries = 5;
1742 u32 const phy_cts_pixel_clk_khz = 148500;
1743 u8 link_status[DP_LINK_STATUS_SIZE];
1744 unsigned int training_step;
1745 unsigned long pixel_rate;
1746
1747 if (!dp_ctrl)
1748 return -EINVAL;
1749
1750 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1751
1752 rate = ctrl->panel->link_info.rate;
1753 pixel_rate = ctrl->panel->dp_mode.drm_mode.clock;
1754
1755 dp_power_clk_enable(ctrl->power, DP_CORE_PM, true);
1756
1757 if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) {
1758 drm_dbg_dp(ctrl->drm_dev,
1759 "using phy test link parameters\n");
1760 if (!pixel_rate)
1761 pixel_rate = phy_cts_pixel_clk_khz;
1762 } else {
1763 ctrl->link->link_params.rate = rate;
1764 ctrl->link->link_params.num_lanes =
1765 ctrl->panel->link_info.num_lanes;
1766 }
1767
1768 drm_dbg_dp(ctrl->drm_dev, "rate=%d, num_lanes=%d, pixel_rate=%lu\n",
1769 ctrl->link->link_params.rate, ctrl->link->link_params.num_lanes,
1770 pixel_rate);
1771
1772 rc = dp_ctrl_enable_mainlink_clocks(ctrl);
1773 if (rc)
1774 return rc;
1775
1776 while (--link_train_max_retries) {
1777 training_step = DP_TRAINING_NONE;
1778 rc = dp_ctrl_setup_main_link(ctrl, &training_step);
1779 if (rc == 0) {
1780 /* training completed successfully */
1781 break;
1782 } else if (training_step == DP_TRAINING_1) {
1783 /* link train_1 failed */
1784 if (!dp_catalog_link_is_connected(ctrl->catalog))
1785 break;
1786
1787 dp_ctrl_read_link_status(ctrl, link_status);
1788
1789 rc = dp_ctrl_link_rate_down_shift(ctrl);
1790 if (rc < 0) { /* already in RBR = 1.6G */
1791 if (dp_ctrl_clock_recovery_any_ok(link_status,
1792 ctrl->link->link_params.num_lanes)) {
1793 /*
1794 * some lanes are ready,
1795 * reduce lane number
1796 */
1797 rc = dp_ctrl_link_lane_down_shift(ctrl);
1798 if (rc < 0) { /* lane == 1 already */
1799 /* end with failure */
1800 break;
1801 }
1802 } else {
1803 /* end with failure */
1804 break; /* lane == 1 already */
1805 }
1806 }
1807 } else if (training_step == DP_TRAINING_2) {
1808 /* link train_2 failed */
1809 if (!dp_catalog_link_is_connected(ctrl->catalog))
1810 break;
1811
1812 dp_ctrl_read_link_status(ctrl, link_status);
1813
1814 if (!drm_dp_clock_recovery_ok(link_status,
1815 ctrl->link->link_params.num_lanes))
1816 rc = dp_ctrl_link_rate_down_shift(ctrl);
1817 else
1818 rc = dp_ctrl_link_lane_down_shift(ctrl);
1819
1820 if (rc < 0) {
1821 /* end with failure */
1822 break; /* lane == 1 already */
1823 }
1824
1825 /* stop link training before start re training */
1826 dp_ctrl_clear_training_pattern(ctrl);
1827 }
1828
1829 rc = dp_ctrl_reinitialize_mainlink(ctrl);
1830 if (rc) {
1831 DRM_ERROR("Failed to reinitialize mainlink. rc=%d\n", rc);
1832 break;
1833 }
1834 }
1835
1836 if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN)
1837 return rc;
1838
1839 if (rc == 0) { /* link train successfully */
1840 /*
1841 * do not stop train pattern here
1842 * stop link training at on_stream
1843 * to pass compliance test
1844 */
1845 } else {
1846 /*
1847 * link training failed
1848 * end txing train pattern here
1849 */
1850 dp_ctrl_clear_training_pattern(ctrl);
1851
1852 dp_ctrl_deinitialize_mainlink(ctrl);
1853 rc = -ECONNRESET;
1854 }
1855
1856 return rc;
1857 }
1858
1859 static int dp_ctrl_link_retrain(struct dp_ctrl_private *ctrl)
1860 {
1861 int training_step = DP_TRAINING_NONE;
1862
1863 return dp_ctrl_setup_main_link(ctrl, &training_step);
1864 }
1865
1866 int dp_ctrl_on_stream(struct dp_ctrl *dp_ctrl, bool force_link_train)
1867 {
1868 int ret = 0;
1869 bool mainlink_ready = false;
1870 struct dp_ctrl_private *ctrl;
1871 unsigned long pixel_rate;
1872 unsigned long pixel_rate_orig;
1873
1874 if (!dp_ctrl)
1875 return -EINVAL;
1876
1877 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1878
1879 pixel_rate = pixel_rate_orig = ctrl->panel->dp_mode.drm_mode.clock;
1880
1881 if (dp_ctrl->wide_bus_en)
1882 pixel_rate >>= 1;
1883
1884 drm_dbg_dp(ctrl->drm_dev, "rate=%d, num_lanes=%d, pixel_rate=%lu\n",
1885 ctrl->link->link_params.rate,
1886 ctrl->link->link_params.num_lanes, pixel_rate);
1887
1888 if (!dp_power_clk_status(ctrl->power, DP_CTRL_PM)) { /* link clk is off */
1889 ret = dp_ctrl_enable_mainlink_clocks(ctrl);
1890 if (ret) {
1891 DRM_ERROR("Failed to start link clocks. ret=%d\n", ret);
1892 goto end;
1893 }
1894 }
1895
1896 dp_ctrl_set_clock_rate(ctrl, DP_STREAM_PM, "stream_pixel", pixel_rate * 1000);
1897
1898 ret = dp_power_clk_enable(ctrl->power, DP_STREAM_PM, true);
1899 if (ret) {
1900 DRM_ERROR("Unable to start pixel clocks. ret=%d\n", ret);
1901 goto end;
1902 }
1903
1904 if (force_link_train || !dp_ctrl_channel_eq_ok(ctrl))
1905 dp_ctrl_link_retrain(ctrl);
1906
1907 /* stop txing train pattern to end link training */
1908 dp_ctrl_clear_training_pattern(ctrl);
1909
1910 /*
1911 * Set up transfer unit values and set controller state to send
1912 * video.
1913 */
1914 reinit_completion(&ctrl->video_comp);
1915
1916 dp_ctrl_configure_source_params(ctrl);
1917
1918 dp_catalog_ctrl_config_msa(ctrl->catalog,
1919 ctrl->link->link_params.rate,
1920 pixel_rate_orig, dp_ctrl_use_fixed_nvid(ctrl));
1921
1922 dp_ctrl_setup_tr_unit(ctrl);
1923
1924 dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_SEND_VIDEO);
1925
1926 ret = dp_ctrl_wait4video_ready(ctrl);
1927 if (ret)
1928 return ret;
1929
1930 mainlink_ready = dp_catalog_ctrl_mainlink_ready(ctrl->catalog);
1931 drm_dbg_dp(ctrl->drm_dev,
1932 "mainlink %s\n", mainlink_ready ? "READY" : "NOT READY");
1933
1934 end:
1935 return ret;
1936 }
1937
1938 int dp_ctrl_off_link_stream(struct dp_ctrl *dp_ctrl)
1939 {
1940 struct dp_ctrl_private *ctrl;
1941 struct dp_io *dp_io;
1942 struct phy *phy;
1943 int ret;
1944
1945 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1946 dp_io = &ctrl->parser->io;
1947 phy = dp_io->phy;
1948
1949 /* set dongle to D3 (power off) mode */
1950 dp_link_psm_config(ctrl->link, &ctrl->panel->link_info, true);
1951
1952 dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false);
1953
1954 if (dp_power_clk_status(ctrl->power, DP_STREAM_PM)) {
1955 ret = dp_power_clk_enable(ctrl->power, DP_STREAM_PM, false);
1956 if (ret) {
1957 DRM_ERROR("Failed to disable pclk. ret=%d\n", ret);
1958 return ret;
1959 }
1960 }
1961
1962 dev_pm_opp_set_rate(ctrl->dev, 0);
1963 ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false);
1964 if (ret) {
1965 DRM_ERROR("Failed to disable link clocks. ret=%d\n", ret);
1966 return ret;
1967 }
1968
1969 phy_power_off(phy);
1970
1971 /* aux channel down, reinit phy */
1972 phy_exit(phy);
1973 phy_init(phy);
1974
1975 drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n",
1976 phy, phy->init_count, phy->power_count);
1977 return ret;
1978 }
1979
1980 int dp_ctrl_off_link(struct dp_ctrl *dp_ctrl)
1981 {
1982 struct dp_ctrl_private *ctrl;
1983 struct dp_io *dp_io;
1984 struct phy *phy;
1985 int ret;
1986
1987 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1988 dp_io = &ctrl->parser->io;
1989 phy = dp_io->phy;
1990
1991 dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false);
1992
1993 ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false);
1994 if (ret) {
1995 DRM_ERROR("Failed to disable link clocks. ret=%d\n", ret);
1996 }
1997
1998 DRM_DEBUG_DP("Before, phy=%p init_count=%d power_on=%d\n",
1999 phy, phy->init_count, phy->power_count);
2000
2001 phy_power_off(phy);
2002
2003 DRM_DEBUG_DP("After, phy=%p init_count=%d power_on=%d\n",
2004 phy, phy->init_count, phy->power_count);
2005
2006 return ret;
2007 }
2008
2009 int dp_ctrl_off(struct dp_ctrl *dp_ctrl)
2010 {
2011 struct dp_ctrl_private *ctrl;
2012 struct dp_io *dp_io;
2013 struct phy *phy;
2014 int ret = 0;
2015
2016 if (!dp_ctrl)
2017 return -EINVAL;
2018
2019 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
2020 dp_io = &ctrl->parser->io;
2021 phy = dp_io->phy;
2022
2023 dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false);
2024
2025 dp_catalog_ctrl_reset(ctrl->catalog);
2026
2027 ret = dp_power_clk_enable(ctrl->power, DP_STREAM_PM, false);
2028 if (ret)
2029 DRM_ERROR("Failed to disable pixel clocks. ret=%d\n", ret);
2030
2031 dev_pm_opp_set_rate(ctrl->dev, 0);
2032 ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false);
2033 if (ret) {
2034 DRM_ERROR("Failed to disable link clocks. ret=%d\n", ret);
2035 }
2036
2037 phy_power_off(phy);
2038 drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n",
2039 phy, phy->init_count, phy->power_count);
2040
2041 return ret;
2042 }
2043
2044 irqreturn_t dp_ctrl_isr(struct dp_ctrl *dp_ctrl)
2045 {
2046 struct dp_ctrl_private *ctrl;
2047 u32 isr;
2048 irqreturn_t ret = IRQ_NONE;
2049
2050 if (!dp_ctrl)
2051 return IRQ_NONE;
2052
2053 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
2054
2055 if (ctrl->panel->psr_cap.version) {
2056 isr = dp_catalog_ctrl_read_psr_interrupt_status(ctrl->catalog);
2057
2058 if (isr)
2059 complete(&ctrl->psr_op_comp);
2060
2061 if (isr & PSR_EXIT_INT)
2062 drm_dbg_dp(ctrl->drm_dev, "PSR exit done\n");
2063
2064 if (isr & PSR_UPDATE_INT)
2065 drm_dbg_dp(ctrl->drm_dev, "PSR frame update done\n");
2066
2067 if (isr & PSR_CAPTURE_INT)
2068 drm_dbg_dp(ctrl->drm_dev, "PSR frame capture done\n");
2069 }
2070
2071 isr = dp_catalog_ctrl_get_interrupt(ctrl->catalog);
2072
2073
2074 if (isr & DP_CTRL_INTR_READY_FOR_VIDEO) {
2075 drm_dbg_dp(ctrl->drm_dev, "dp_video_ready\n");
2076 complete(&ctrl->video_comp);
2077 ret = IRQ_HANDLED;
2078 }
2079
2080 if (isr & DP_CTRL_INTR_IDLE_PATTERN_SENT) {
2081 drm_dbg_dp(ctrl->drm_dev, "idle_patterns_sent\n");
2082 complete(&ctrl->idle_comp);
2083 ret = IRQ_HANDLED;
2084 }
2085
2086 return ret;
2087 }
2088
2089 struct dp_ctrl *dp_ctrl_get(struct device *dev, struct dp_link *link,
2090 struct dp_panel *panel, struct drm_dp_aux *aux,
2091 struct dp_power *power, struct dp_catalog *catalog,
2092 struct dp_parser *parser)
2093 {
2094 struct dp_ctrl_private *ctrl;
2095 int ret;
2096
2097 if (!dev || !panel || !aux ||
2098 !link || !catalog) {
2099 DRM_ERROR("invalid input\n");
2100 return ERR_PTR(-EINVAL);
2101 }
2102
2103 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
2104 if (!ctrl) {
2105 DRM_ERROR("Mem allocation failure\n");
2106 return ERR_PTR(-ENOMEM);
2107 }
2108
2109 ret = devm_pm_opp_set_clkname(dev, "ctrl_link");
2110 if (ret) {
2111 dev_err(dev, "invalid DP OPP table in device tree\n");
2112 /* caller do PTR_ERR(opp_table) */
2113 return (struct dp_ctrl *)ERR_PTR(ret);
2114 }
2115
2116 /* OPP table is optional */
2117 ret = devm_pm_opp_of_add_table(dev);
2118 if (ret)
2119 dev_err(dev, "failed to add DP OPP table\n");
2120
2121 init_completion(&ctrl->idle_comp);
2122 init_completion(&ctrl->psr_op_comp);
2123 init_completion(&ctrl->video_comp);
2124
2125 /* in parameters */
2126 ctrl->parser = parser;
2127 ctrl->panel = panel;
2128 ctrl->power = power;
2129 ctrl->aux = aux;
2130 ctrl->link = link;
2131 ctrl->catalog = catalog;
2132 ctrl->dev = dev;
2133
2134 return &ctrl->dp_ctrl;
2135 }
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