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[thirdparty/kernel/stable.git] / drivers / gpu / drm / msm / msm_drv.c
1 /*
2 * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
3 * Copyright (C) 2013 Red Hat
4 * Author: Rob Clark <robdclark@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published by
8 * the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19 #include <linux/kthread.h>
20 #include <uapi/linux/sched/types.h>
21 #include <drm/drm_of.h>
22
23 #include "msm_drv.h"
24 #include "msm_debugfs.h"
25 #include "msm_fence.h"
26 #include "msm_gem.h"
27 #include "msm_gpu.h"
28 #include "msm_kms.h"
29 #include "adreno/adreno_gpu.h"
30
31
32 /*
33 * MSM driver version:
34 * - 1.0.0 - initial interface
35 * - 1.1.0 - adds madvise, and support for submits with > 4 cmd buffers
36 * - 1.2.0 - adds explicit fence support for submit ioctl
37 * - 1.3.0 - adds GMEM_BASE + NR_RINGS params, SUBMITQUEUE_NEW +
38 * SUBMITQUEUE_CLOSE ioctls, and MSM_INFO_IOVA flag for
39 * MSM_GEM_INFO ioctl.
40 * - 1.4.0 - softpin, MSM_RELOC_BO_DUMP, and GEM_INFO support to set/get
41 * GEM object's debug name
42 */
43 #define MSM_VERSION_MAJOR 1
44 #define MSM_VERSION_MINOR 4
45 #define MSM_VERSION_PATCHLEVEL 0
46
47 static const struct drm_mode_config_funcs mode_config_funcs = {
48 .fb_create = msm_framebuffer_create,
49 .output_poll_changed = drm_fb_helper_output_poll_changed,
50 .atomic_check = drm_atomic_helper_check,
51 .atomic_commit = drm_atomic_helper_commit,
52 };
53
54 static const struct drm_mode_config_helper_funcs mode_config_helper_funcs = {
55 .atomic_commit_tail = msm_atomic_commit_tail,
56 };
57
58 #ifdef CONFIG_DRM_MSM_REGISTER_LOGGING
59 static bool reglog = false;
60 MODULE_PARM_DESC(reglog, "Enable register read/write logging");
61 module_param(reglog, bool, 0600);
62 #else
63 #define reglog 0
64 #endif
65
66 #ifdef CONFIG_DRM_FBDEV_EMULATION
67 static bool fbdev = true;
68 MODULE_PARM_DESC(fbdev, "Enable fbdev compat layer");
69 module_param(fbdev, bool, 0600);
70 #endif
71
72 static char *vram = "16m";
73 MODULE_PARM_DESC(vram, "Configure VRAM size (for devices without IOMMU/GPUMMU)");
74 module_param(vram, charp, 0);
75
76 bool dumpstate = false;
77 MODULE_PARM_DESC(dumpstate, "Dump KMS state on errors");
78 module_param(dumpstate, bool, 0600);
79
80 static bool modeset = true;
81 MODULE_PARM_DESC(modeset, "Use kernel modesetting [KMS] (1=on (default), 0=disable)");
82 module_param(modeset, bool, 0600);
83
84 /*
85 * Util/helpers:
86 */
87
88 int msm_clk_bulk_get(struct device *dev, struct clk_bulk_data **bulk)
89 {
90 struct property *prop;
91 const char *name;
92 struct clk_bulk_data *local;
93 int i = 0, ret, count;
94
95 count = of_property_count_strings(dev->of_node, "clock-names");
96 if (count < 1)
97 return 0;
98
99 local = devm_kcalloc(dev, sizeof(struct clk_bulk_data *),
100 count, GFP_KERNEL);
101 if (!local)
102 return -ENOMEM;
103
104 of_property_for_each_string(dev->of_node, "clock-names", prop, name) {
105 local[i].id = devm_kstrdup(dev, name, GFP_KERNEL);
106 if (!local[i].id) {
107 devm_kfree(dev, local);
108 return -ENOMEM;
109 }
110
111 i++;
112 }
113
114 ret = devm_clk_bulk_get(dev, count, local);
115
116 if (ret) {
117 for (i = 0; i < count; i++)
118 devm_kfree(dev, (void *) local[i].id);
119 devm_kfree(dev, local);
120
121 return ret;
122 }
123
124 *bulk = local;
125 return count;
126 }
127
128 struct clk *msm_clk_bulk_get_clock(struct clk_bulk_data *bulk, int count,
129 const char *name)
130 {
131 int i;
132 char n[32];
133
134 snprintf(n, sizeof(n), "%s_clk", name);
135
136 for (i = 0; bulk && i < count; i++) {
137 if (!strcmp(bulk[i].id, name) || !strcmp(bulk[i].id, n))
138 return bulk[i].clk;
139 }
140
141
142 return NULL;
143 }
144
145 struct clk *msm_clk_get(struct platform_device *pdev, const char *name)
146 {
147 struct clk *clk;
148 char name2[32];
149
150 clk = devm_clk_get(&pdev->dev, name);
151 if (!IS_ERR(clk) || PTR_ERR(clk) == -EPROBE_DEFER)
152 return clk;
153
154 snprintf(name2, sizeof(name2), "%s_clk", name);
155
156 clk = devm_clk_get(&pdev->dev, name2);
157 if (!IS_ERR(clk))
158 dev_warn(&pdev->dev, "Using legacy clk name binding. Use "
159 "\"%s\" instead of \"%s\"\n", name, name2);
160
161 return clk;
162 }
163
164 void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
165 const char *dbgname)
166 {
167 struct resource *res;
168 unsigned long size;
169 void __iomem *ptr;
170
171 if (name)
172 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
173 else
174 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
175
176 if (!res) {
177 DRM_DEV_ERROR(&pdev->dev, "failed to get memory resource: %s\n", name);
178 return ERR_PTR(-EINVAL);
179 }
180
181 size = resource_size(res);
182
183 ptr = devm_ioremap_nocache(&pdev->dev, res->start, size);
184 if (!ptr) {
185 DRM_DEV_ERROR(&pdev->dev, "failed to ioremap: %s\n", name);
186 return ERR_PTR(-ENOMEM);
187 }
188
189 if (reglog)
190 printk(KERN_DEBUG "IO:region %s %p %08lx\n", dbgname, ptr, size);
191
192 return ptr;
193 }
194
195 void msm_writel(u32 data, void __iomem *addr)
196 {
197 if (reglog)
198 printk(KERN_DEBUG "IO:W %p %08x\n", addr, data);
199 writel(data, addr);
200 }
201
202 u32 msm_readl(const void __iomem *addr)
203 {
204 u32 val = readl(addr);
205 if (reglog)
206 pr_err("IO:R %p %08x\n", addr, val);
207 return val;
208 }
209
210 struct vblank_event {
211 struct list_head node;
212 int crtc_id;
213 bool enable;
214 };
215
216 static void vblank_ctrl_worker(struct kthread_work *work)
217 {
218 struct msm_vblank_ctrl *vbl_ctrl = container_of(work,
219 struct msm_vblank_ctrl, work);
220 struct msm_drm_private *priv = container_of(vbl_ctrl,
221 struct msm_drm_private, vblank_ctrl);
222 struct msm_kms *kms = priv->kms;
223 struct vblank_event *vbl_ev, *tmp;
224 unsigned long flags;
225
226 spin_lock_irqsave(&vbl_ctrl->lock, flags);
227 list_for_each_entry_safe(vbl_ev, tmp, &vbl_ctrl->event_list, node) {
228 list_del(&vbl_ev->node);
229 spin_unlock_irqrestore(&vbl_ctrl->lock, flags);
230
231 if (vbl_ev->enable)
232 kms->funcs->enable_vblank(kms,
233 priv->crtcs[vbl_ev->crtc_id]);
234 else
235 kms->funcs->disable_vblank(kms,
236 priv->crtcs[vbl_ev->crtc_id]);
237
238 kfree(vbl_ev);
239
240 spin_lock_irqsave(&vbl_ctrl->lock, flags);
241 }
242
243 spin_unlock_irqrestore(&vbl_ctrl->lock, flags);
244 }
245
246 static int vblank_ctrl_queue_work(struct msm_drm_private *priv,
247 int crtc_id, bool enable)
248 {
249 struct msm_vblank_ctrl *vbl_ctrl = &priv->vblank_ctrl;
250 struct vblank_event *vbl_ev;
251 unsigned long flags;
252
253 vbl_ev = kzalloc(sizeof(*vbl_ev), GFP_ATOMIC);
254 if (!vbl_ev)
255 return -ENOMEM;
256
257 vbl_ev->crtc_id = crtc_id;
258 vbl_ev->enable = enable;
259
260 spin_lock_irqsave(&vbl_ctrl->lock, flags);
261 list_add_tail(&vbl_ev->node, &vbl_ctrl->event_list);
262 spin_unlock_irqrestore(&vbl_ctrl->lock, flags);
263
264 kthread_queue_work(&priv->disp_thread[crtc_id].worker,
265 &vbl_ctrl->work);
266
267 return 0;
268 }
269
270 static int msm_drm_uninit(struct device *dev)
271 {
272 struct platform_device *pdev = to_platform_device(dev);
273 struct drm_device *ddev = platform_get_drvdata(pdev);
274 struct msm_drm_private *priv = ddev->dev_private;
275 struct msm_kms *kms = priv->kms;
276 struct msm_mdss *mdss = priv->mdss;
277 struct msm_vblank_ctrl *vbl_ctrl = &priv->vblank_ctrl;
278 struct vblank_event *vbl_ev, *tmp;
279 int i;
280
281 /* We must cancel and cleanup any pending vblank enable/disable
282 * work before drm_irq_uninstall() to avoid work re-enabling an
283 * irq after uninstall has disabled it.
284 */
285 kthread_flush_work(&vbl_ctrl->work);
286 list_for_each_entry_safe(vbl_ev, tmp, &vbl_ctrl->event_list, node) {
287 list_del(&vbl_ev->node);
288 kfree(vbl_ev);
289 }
290
291 /* clean up display commit/event worker threads */
292 for (i = 0; i < priv->num_crtcs; i++) {
293 if (priv->disp_thread[i].thread) {
294 kthread_flush_worker(&priv->disp_thread[i].worker);
295 kthread_stop(priv->disp_thread[i].thread);
296 priv->disp_thread[i].thread = NULL;
297 }
298
299 if (priv->event_thread[i].thread) {
300 kthread_flush_worker(&priv->event_thread[i].worker);
301 kthread_stop(priv->event_thread[i].thread);
302 priv->event_thread[i].thread = NULL;
303 }
304 }
305
306 msm_gem_shrinker_cleanup(ddev);
307
308 drm_kms_helper_poll_fini(ddev);
309
310 drm_dev_unregister(ddev);
311
312 msm_perf_debugfs_cleanup(priv);
313 msm_rd_debugfs_cleanup(priv);
314
315 #ifdef CONFIG_DRM_FBDEV_EMULATION
316 if (fbdev && priv->fbdev)
317 msm_fbdev_free(ddev);
318 #endif
319 drm_atomic_helper_shutdown(ddev);
320 drm_mode_config_cleanup(ddev);
321
322 pm_runtime_get_sync(dev);
323 drm_irq_uninstall(ddev);
324 pm_runtime_put_sync(dev);
325
326 flush_workqueue(priv->wq);
327 destroy_workqueue(priv->wq);
328
329 if (kms && kms->funcs)
330 kms->funcs->destroy(kms);
331
332 if (priv->vram.paddr) {
333 unsigned long attrs = DMA_ATTR_NO_KERNEL_MAPPING;
334 drm_mm_takedown(&priv->vram.mm);
335 dma_free_attrs(dev, priv->vram.size, NULL,
336 priv->vram.paddr, attrs);
337 }
338
339 component_unbind_all(dev, ddev);
340
341 if (mdss && mdss->funcs)
342 mdss->funcs->destroy(ddev);
343
344 ddev->dev_private = NULL;
345 drm_dev_put(ddev);
346
347 kfree(priv);
348
349 return 0;
350 }
351
352 #define KMS_MDP4 4
353 #define KMS_MDP5 5
354 #define KMS_DPU 3
355
356 static int get_mdp_ver(struct platform_device *pdev)
357 {
358 struct device *dev = &pdev->dev;
359
360 return (int) (unsigned long) of_device_get_match_data(dev);
361 }
362
363 #include <linux/of_address.h>
364
365 bool msm_use_mmu(struct drm_device *dev)
366 {
367 struct msm_drm_private *priv = dev->dev_private;
368
369 /* a2xx comes with its own MMU */
370 return priv->is_a2xx || iommu_present(&platform_bus_type);
371 }
372
373 static int msm_init_vram(struct drm_device *dev)
374 {
375 struct msm_drm_private *priv = dev->dev_private;
376 struct device_node *node;
377 unsigned long size = 0;
378 int ret = 0;
379
380 /* In the device-tree world, we could have a 'memory-region'
381 * phandle, which gives us a link to our "vram". Allocating
382 * is all nicely abstracted behind the dma api, but we need
383 * to know the entire size to allocate it all in one go. There
384 * are two cases:
385 * 1) device with no IOMMU, in which case we need exclusive
386 * access to a VRAM carveout big enough for all gpu
387 * buffers
388 * 2) device with IOMMU, but where the bootloader puts up
389 * a splash screen. In this case, the VRAM carveout
390 * need only be large enough for fbdev fb. But we need
391 * exclusive access to the buffer to avoid the kernel
392 * using those pages for other purposes (which appears
393 * as corruption on screen before we have a chance to
394 * load and do initial modeset)
395 */
396
397 node = of_parse_phandle(dev->dev->of_node, "memory-region", 0);
398 if (node) {
399 struct resource r;
400 ret = of_address_to_resource(node, 0, &r);
401 of_node_put(node);
402 if (ret)
403 return ret;
404 size = r.end - r.start;
405 DRM_INFO("using VRAM carveout: %lx@%pa\n", size, &r.start);
406
407 /* if we have no IOMMU, then we need to use carveout allocator.
408 * Grab the entire CMA chunk carved out in early startup in
409 * mach-msm:
410 */
411 } else if (!msm_use_mmu(dev)) {
412 DRM_INFO("using %s VRAM carveout\n", vram);
413 size = memparse(vram, NULL);
414 }
415
416 if (size) {
417 unsigned long attrs = 0;
418 void *p;
419
420 priv->vram.size = size;
421
422 drm_mm_init(&priv->vram.mm, 0, (size >> PAGE_SHIFT) - 1);
423 spin_lock_init(&priv->vram.lock);
424
425 attrs |= DMA_ATTR_NO_KERNEL_MAPPING;
426 attrs |= DMA_ATTR_WRITE_COMBINE;
427
428 /* note that for no-kernel-mapping, the vaddr returned
429 * is bogus, but non-null if allocation succeeded:
430 */
431 p = dma_alloc_attrs(dev->dev, size,
432 &priv->vram.paddr, GFP_KERNEL, attrs);
433 if (!p) {
434 DRM_DEV_ERROR(dev->dev, "failed to allocate VRAM\n");
435 priv->vram.paddr = 0;
436 return -ENOMEM;
437 }
438
439 DRM_DEV_INFO(dev->dev, "VRAM: %08x->%08x\n",
440 (uint32_t)priv->vram.paddr,
441 (uint32_t)(priv->vram.paddr + size));
442 }
443
444 return ret;
445 }
446
447 static int msm_drm_init(struct device *dev, struct drm_driver *drv)
448 {
449 struct platform_device *pdev = to_platform_device(dev);
450 struct drm_device *ddev;
451 struct msm_drm_private *priv;
452 struct msm_kms *kms;
453 struct msm_mdss *mdss;
454 int ret, i;
455 struct sched_param param;
456
457 ddev = drm_dev_alloc(drv, dev);
458 if (IS_ERR(ddev)) {
459 DRM_DEV_ERROR(dev, "failed to allocate drm_device\n");
460 return PTR_ERR(ddev);
461 }
462
463 platform_set_drvdata(pdev, ddev);
464
465 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
466 if (!priv) {
467 ret = -ENOMEM;
468 goto err_put_drm_dev;
469 }
470
471 ddev->dev_private = priv;
472 priv->dev = ddev;
473
474 switch (get_mdp_ver(pdev)) {
475 case KMS_MDP5:
476 ret = mdp5_mdss_init(ddev);
477 break;
478 case KMS_DPU:
479 ret = dpu_mdss_init(ddev);
480 break;
481 default:
482 ret = 0;
483 break;
484 }
485 if (ret)
486 goto err_free_priv;
487
488 mdss = priv->mdss;
489
490 priv->wq = alloc_ordered_workqueue("msm", 0);
491
492 INIT_LIST_HEAD(&priv->inactive_list);
493 INIT_LIST_HEAD(&priv->vblank_ctrl.event_list);
494 kthread_init_work(&priv->vblank_ctrl.work, vblank_ctrl_worker);
495 spin_lock_init(&priv->vblank_ctrl.lock);
496
497 drm_mode_config_init(ddev);
498
499 /* Bind all our sub-components: */
500 ret = component_bind_all(dev, ddev);
501 if (ret)
502 goto err_destroy_mdss;
503
504 ret = msm_init_vram(ddev);
505 if (ret)
506 goto err_msm_uninit;
507
508 msm_gem_shrinker_init(ddev);
509
510 switch (get_mdp_ver(pdev)) {
511 case KMS_MDP4:
512 kms = mdp4_kms_init(ddev);
513 priv->kms = kms;
514 break;
515 case KMS_MDP5:
516 kms = mdp5_kms_init(ddev);
517 break;
518 case KMS_DPU:
519 kms = dpu_kms_init(ddev);
520 priv->kms = kms;
521 break;
522 default:
523 /* valid only for the dummy headless case, where of_node=NULL */
524 WARN_ON(dev->of_node);
525 kms = NULL;
526 break;
527 }
528
529 if (IS_ERR(kms)) {
530 DRM_DEV_ERROR(dev, "failed to load kms\n");
531 ret = PTR_ERR(kms);
532 priv->kms = NULL;
533 goto err_msm_uninit;
534 }
535
536 /* Enable normalization of plane zpos */
537 ddev->mode_config.normalize_zpos = true;
538
539 if (kms) {
540 ret = kms->funcs->hw_init(kms);
541 if (ret) {
542 DRM_DEV_ERROR(dev, "kms hw init failed: %d\n", ret);
543 goto err_msm_uninit;
544 }
545 }
546
547 ddev->mode_config.funcs = &mode_config_funcs;
548 ddev->mode_config.helper_private = &mode_config_helper_funcs;
549
550 /**
551 * this priority was found during empiric testing to have appropriate
552 * realtime scheduling to process display updates and interact with
553 * other real time and normal priority task
554 */
555 param.sched_priority = 16;
556 for (i = 0; i < priv->num_crtcs; i++) {
557
558 /* initialize display thread */
559 priv->disp_thread[i].crtc_id = priv->crtcs[i]->base.id;
560 kthread_init_worker(&priv->disp_thread[i].worker);
561 priv->disp_thread[i].dev = ddev;
562 priv->disp_thread[i].thread =
563 kthread_run(kthread_worker_fn,
564 &priv->disp_thread[i].worker,
565 "crtc_commit:%d", priv->disp_thread[i].crtc_id);
566 if (IS_ERR(priv->disp_thread[i].thread)) {
567 DRM_DEV_ERROR(dev, "failed to create crtc_commit kthread\n");
568 priv->disp_thread[i].thread = NULL;
569 goto err_msm_uninit;
570 }
571
572 ret = sched_setscheduler(priv->disp_thread[i].thread,
573 SCHED_FIFO, &param);
574 if (ret)
575 dev_warn(dev, "disp_thread set priority failed: %d\n",
576 ret);
577
578 /* initialize event thread */
579 priv->event_thread[i].crtc_id = priv->crtcs[i]->base.id;
580 kthread_init_worker(&priv->event_thread[i].worker);
581 priv->event_thread[i].dev = ddev;
582 priv->event_thread[i].thread =
583 kthread_run(kthread_worker_fn,
584 &priv->event_thread[i].worker,
585 "crtc_event:%d", priv->event_thread[i].crtc_id);
586 if (IS_ERR(priv->event_thread[i].thread)) {
587 DRM_DEV_ERROR(dev, "failed to create crtc_event kthread\n");
588 priv->event_thread[i].thread = NULL;
589 goto err_msm_uninit;
590 }
591
592 /**
593 * event thread should also run at same priority as disp_thread
594 * because it is handling frame_done events. A lower priority
595 * event thread and higher priority disp_thread can causes
596 * frame_pending counters beyond 2. This can lead to commit
597 * failure at crtc commit level.
598 */
599 ret = sched_setscheduler(priv->event_thread[i].thread,
600 SCHED_FIFO, &param);
601 if (ret)
602 dev_warn(dev, "event_thread set priority failed:%d\n",
603 ret);
604 }
605
606 ret = drm_vblank_init(ddev, priv->num_crtcs);
607 if (ret < 0) {
608 DRM_DEV_ERROR(dev, "failed to initialize vblank\n");
609 goto err_msm_uninit;
610 }
611
612 if (kms) {
613 pm_runtime_get_sync(dev);
614 ret = drm_irq_install(ddev, kms->irq);
615 pm_runtime_put_sync(dev);
616 if (ret < 0) {
617 DRM_DEV_ERROR(dev, "failed to install IRQ handler\n");
618 goto err_msm_uninit;
619 }
620 }
621
622 ret = drm_dev_register(ddev, 0);
623 if (ret)
624 goto err_msm_uninit;
625
626 drm_mode_config_reset(ddev);
627
628 #ifdef CONFIG_DRM_FBDEV_EMULATION
629 if (kms && fbdev)
630 priv->fbdev = msm_fbdev_init(ddev);
631 #endif
632
633 ret = msm_debugfs_late_init(ddev);
634 if (ret)
635 goto err_msm_uninit;
636
637 drm_kms_helper_poll_init(ddev);
638
639 return 0;
640
641 err_msm_uninit:
642 msm_drm_uninit(dev);
643 return ret;
644 err_destroy_mdss:
645 if (mdss && mdss->funcs)
646 mdss->funcs->destroy(ddev);
647 err_free_priv:
648 kfree(priv);
649 err_put_drm_dev:
650 drm_dev_put(ddev);
651 return ret;
652 }
653
654 /*
655 * DRM operations:
656 */
657
658 static void load_gpu(struct drm_device *dev)
659 {
660 static DEFINE_MUTEX(init_lock);
661 struct msm_drm_private *priv = dev->dev_private;
662
663 mutex_lock(&init_lock);
664
665 if (!priv->gpu)
666 priv->gpu = adreno_load_gpu(dev);
667
668 mutex_unlock(&init_lock);
669 }
670
671 static int context_init(struct drm_device *dev, struct drm_file *file)
672 {
673 struct msm_file_private *ctx;
674
675 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
676 if (!ctx)
677 return -ENOMEM;
678
679 msm_submitqueue_init(dev, ctx);
680
681 file->driver_priv = ctx;
682
683 return 0;
684 }
685
686 static int msm_open(struct drm_device *dev, struct drm_file *file)
687 {
688 /* For now, load gpu on open.. to avoid the requirement of having
689 * firmware in the initrd.
690 */
691 load_gpu(dev);
692
693 return context_init(dev, file);
694 }
695
696 static void context_close(struct msm_file_private *ctx)
697 {
698 msm_submitqueue_close(ctx);
699 kfree(ctx);
700 }
701
702 static void msm_postclose(struct drm_device *dev, struct drm_file *file)
703 {
704 struct msm_drm_private *priv = dev->dev_private;
705 struct msm_file_private *ctx = file->driver_priv;
706
707 mutex_lock(&dev->struct_mutex);
708 if (ctx == priv->lastctx)
709 priv->lastctx = NULL;
710 mutex_unlock(&dev->struct_mutex);
711
712 context_close(ctx);
713 }
714
715 static irqreturn_t msm_irq(int irq, void *arg)
716 {
717 struct drm_device *dev = arg;
718 struct msm_drm_private *priv = dev->dev_private;
719 struct msm_kms *kms = priv->kms;
720 BUG_ON(!kms);
721 return kms->funcs->irq(kms);
722 }
723
724 static void msm_irq_preinstall(struct drm_device *dev)
725 {
726 struct msm_drm_private *priv = dev->dev_private;
727 struct msm_kms *kms = priv->kms;
728 BUG_ON(!kms);
729 kms->funcs->irq_preinstall(kms);
730 }
731
732 static int msm_irq_postinstall(struct drm_device *dev)
733 {
734 struct msm_drm_private *priv = dev->dev_private;
735 struct msm_kms *kms = priv->kms;
736 BUG_ON(!kms);
737
738 if (kms->funcs->irq_postinstall)
739 return kms->funcs->irq_postinstall(kms);
740
741 return 0;
742 }
743
744 static void msm_irq_uninstall(struct drm_device *dev)
745 {
746 struct msm_drm_private *priv = dev->dev_private;
747 struct msm_kms *kms = priv->kms;
748 BUG_ON(!kms);
749 kms->funcs->irq_uninstall(kms);
750 }
751
752 static int msm_enable_vblank(struct drm_device *dev, unsigned int pipe)
753 {
754 struct msm_drm_private *priv = dev->dev_private;
755 struct msm_kms *kms = priv->kms;
756 if (!kms)
757 return -ENXIO;
758 DBG("dev=%p, crtc=%u", dev, pipe);
759 return vblank_ctrl_queue_work(priv, pipe, true);
760 }
761
762 static void msm_disable_vblank(struct drm_device *dev, unsigned int pipe)
763 {
764 struct msm_drm_private *priv = dev->dev_private;
765 struct msm_kms *kms = priv->kms;
766 if (!kms)
767 return;
768 DBG("dev=%p, crtc=%u", dev, pipe);
769 vblank_ctrl_queue_work(priv, pipe, false);
770 }
771
772 /*
773 * DRM ioctls:
774 */
775
776 static int msm_ioctl_get_param(struct drm_device *dev, void *data,
777 struct drm_file *file)
778 {
779 struct msm_drm_private *priv = dev->dev_private;
780 struct drm_msm_param *args = data;
781 struct msm_gpu *gpu;
782
783 /* for now, we just have 3d pipe.. eventually this would need to
784 * be more clever to dispatch to appropriate gpu module:
785 */
786 if (args->pipe != MSM_PIPE_3D0)
787 return -EINVAL;
788
789 gpu = priv->gpu;
790
791 if (!gpu)
792 return -ENXIO;
793
794 return gpu->funcs->get_param(gpu, args->param, &args->value);
795 }
796
797 static int msm_ioctl_gem_new(struct drm_device *dev, void *data,
798 struct drm_file *file)
799 {
800 struct drm_msm_gem_new *args = data;
801
802 if (args->flags & ~MSM_BO_FLAGS) {
803 DRM_ERROR("invalid flags: %08x\n", args->flags);
804 return -EINVAL;
805 }
806
807 return msm_gem_new_handle(dev, file, args->size,
808 args->flags, &args->handle, NULL);
809 }
810
811 static inline ktime_t to_ktime(struct drm_msm_timespec timeout)
812 {
813 return ktime_set(timeout.tv_sec, timeout.tv_nsec);
814 }
815
816 static int msm_ioctl_gem_cpu_prep(struct drm_device *dev, void *data,
817 struct drm_file *file)
818 {
819 struct drm_msm_gem_cpu_prep *args = data;
820 struct drm_gem_object *obj;
821 ktime_t timeout = to_ktime(args->timeout);
822 int ret;
823
824 if (args->op & ~MSM_PREP_FLAGS) {
825 DRM_ERROR("invalid op: %08x\n", args->op);
826 return -EINVAL;
827 }
828
829 obj = drm_gem_object_lookup(file, args->handle);
830 if (!obj)
831 return -ENOENT;
832
833 ret = msm_gem_cpu_prep(obj, args->op, &timeout);
834
835 drm_gem_object_put_unlocked(obj);
836
837 return ret;
838 }
839
840 static int msm_ioctl_gem_cpu_fini(struct drm_device *dev, void *data,
841 struct drm_file *file)
842 {
843 struct drm_msm_gem_cpu_fini *args = data;
844 struct drm_gem_object *obj;
845 int ret;
846
847 obj = drm_gem_object_lookup(file, args->handle);
848 if (!obj)
849 return -ENOENT;
850
851 ret = msm_gem_cpu_fini(obj);
852
853 drm_gem_object_put_unlocked(obj);
854
855 return ret;
856 }
857
858 static int msm_ioctl_gem_info_iova(struct drm_device *dev,
859 struct drm_gem_object *obj, uint64_t *iova)
860 {
861 struct msm_drm_private *priv = dev->dev_private;
862
863 if (!priv->gpu)
864 return -EINVAL;
865
866 /*
867 * Don't pin the memory here - just get an address so that userspace can
868 * be productive
869 */
870 return msm_gem_get_iova(obj, priv->gpu->aspace, iova);
871 }
872
873 static int msm_ioctl_gem_info(struct drm_device *dev, void *data,
874 struct drm_file *file)
875 {
876 struct drm_msm_gem_info *args = data;
877 struct drm_gem_object *obj;
878 struct msm_gem_object *msm_obj;
879 int i, ret = 0;
880
881 if (args->pad)
882 return -EINVAL;
883
884 switch (args->info) {
885 case MSM_INFO_GET_OFFSET:
886 case MSM_INFO_GET_IOVA:
887 /* value returned as immediate, not pointer, so len==0: */
888 if (args->len)
889 return -EINVAL;
890 break;
891 case MSM_INFO_SET_NAME:
892 case MSM_INFO_GET_NAME:
893 break;
894 default:
895 return -EINVAL;
896 }
897
898 obj = drm_gem_object_lookup(file, args->handle);
899 if (!obj)
900 return -ENOENT;
901
902 msm_obj = to_msm_bo(obj);
903
904 switch (args->info) {
905 case MSM_INFO_GET_OFFSET:
906 args->value = msm_gem_mmap_offset(obj);
907 break;
908 case MSM_INFO_GET_IOVA:
909 ret = msm_ioctl_gem_info_iova(dev, obj, &args->value);
910 break;
911 case MSM_INFO_SET_NAME:
912 /* length check should leave room for terminating null: */
913 if (args->len >= sizeof(msm_obj->name)) {
914 ret = -EINVAL;
915 break;
916 }
917 ret = copy_from_user(msm_obj->name,
918 u64_to_user_ptr(args->value), args->len);
919 msm_obj->name[args->len] = '\0';
920 for (i = 0; i < args->len; i++) {
921 if (!isprint(msm_obj->name[i])) {
922 msm_obj->name[i] = '\0';
923 break;
924 }
925 }
926 break;
927 case MSM_INFO_GET_NAME:
928 if (args->value && (args->len < strlen(msm_obj->name))) {
929 ret = -EINVAL;
930 break;
931 }
932 args->len = strlen(msm_obj->name);
933 if (args->value) {
934 ret = copy_to_user(u64_to_user_ptr(args->value),
935 msm_obj->name, args->len);
936 }
937 break;
938 }
939
940 drm_gem_object_put_unlocked(obj);
941
942 return ret;
943 }
944
945 static int msm_ioctl_wait_fence(struct drm_device *dev, void *data,
946 struct drm_file *file)
947 {
948 struct msm_drm_private *priv = dev->dev_private;
949 struct drm_msm_wait_fence *args = data;
950 ktime_t timeout = to_ktime(args->timeout);
951 struct msm_gpu_submitqueue *queue;
952 struct msm_gpu *gpu = priv->gpu;
953 int ret;
954
955 if (args->pad) {
956 DRM_ERROR("invalid pad: %08x\n", args->pad);
957 return -EINVAL;
958 }
959
960 if (!gpu)
961 return 0;
962
963 queue = msm_submitqueue_get(file->driver_priv, args->queueid);
964 if (!queue)
965 return -ENOENT;
966
967 ret = msm_wait_fence(gpu->rb[queue->prio]->fctx, args->fence, &timeout,
968 true);
969
970 msm_submitqueue_put(queue);
971 return ret;
972 }
973
974 static int msm_ioctl_gem_madvise(struct drm_device *dev, void *data,
975 struct drm_file *file)
976 {
977 struct drm_msm_gem_madvise *args = data;
978 struct drm_gem_object *obj;
979 int ret;
980
981 switch (args->madv) {
982 case MSM_MADV_DONTNEED:
983 case MSM_MADV_WILLNEED:
984 break;
985 default:
986 return -EINVAL;
987 }
988
989 ret = mutex_lock_interruptible(&dev->struct_mutex);
990 if (ret)
991 return ret;
992
993 obj = drm_gem_object_lookup(file, args->handle);
994 if (!obj) {
995 ret = -ENOENT;
996 goto unlock;
997 }
998
999 ret = msm_gem_madvise(obj, args->madv);
1000 if (ret >= 0) {
1001 args->retained = ret;
1002 ret = 0;
1003 }
1004
1005 drm_gem_object_put(obj);
1006
1007 unlock:
1008 mutex_unlock(&dev->struct_mutex);
1009 return ret;
1010 }
1011
1012
1013 static int msm_ioctl_submitqueue_new(struct drm_device *dev, void *data,
1014 struct drm_file *file)
1015 {
1016 struct drm_msm_submitqueue *args = data;
1017
1018 if (args->flags & ~MSM_SUBMITQUEUE_FLAGS)
1019 return -EINVAL;
1020
1021 return msm_submitqueue_create(dev, file->driver_priv, args->prio,
1022 args->flags, &args->id);
1023 }
1024
1025
1026 static int msm_ioctl_submitqueue_close(struct drm_device *dev, void *data,
1027 struct drm_file *file)
1028 {
1029 u32 id = *(u32 *) data;
1030
1031 return msm_submitqueue_remove(file->driver_priv, id);
1032 }
1033
1034 static const struct drm_ioctl_desc msm_ioctls[] = {
1035 DRM_IOCTL_DEF_DRV(MSM_GET_PARAM, msm_ioctl_get_param, DRM_AUTH|DRM_RENDER_ALLOW),
1036 DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new, DRM_AUTH|DRM_RENDER_ALLOW),
1037 DRM_IOCTL_DEF_DRV(MSM_GEM_INFO, msm_ioctl_gem_info, DRM_AUTH|DRM_RENDER_ALLOW),
1038 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP, msm_ioctl_gem_cpu_prep, DRM_AUTH|DRM_RENDER_ALLOW),
1039 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_AUTH|DRM_RENDER_ALLOW),
1040 DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT, msm_ioctl_gem_submit, DRM_AUTH|DRM_RENDER_ALLOW),
1041 DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE, msm_ioctl_wait_fence, DRM_AUTH|DRM_RENDER_ALLOW),
1042 DRM_IOCTL_DEF_DRV(MSM_GEM_MADVISE, msm_ioctl_gem_madvise, DRM_AUTH|DRM_RENDER_ALLOW),
1043 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_NEW, msm_ioctl_submitqueue_new, DRM_AUTH|DRM_RENDER_ALLOW),
1044 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_CLOSE, msm_ioctl_submitqueue_close, DRM_AUTH|DRM_RENDER_ALLOW),
1045 };
1046
1047 static const struct vm_operations_struct vm_ops = {
1048 .fault = msm_gem_fault,
1049 .open = drm_gem_vm_open,
1050 .close = drm_gem_vm_close,
1051 };
1052
1053 static const struct file_operations fops = {
1054 .owner = THIS_MODULE,
1055 .open = drm_open,
1056 .release = drm_release,
1057 .unlocked_ioctl = drm_ioctl,
1058 .compat_ioctl = drm_compat_ioctl,
1059 .poll = drm_poll,
1060 .read = drm_read,
1061 .llseek = no_llseek,
1062 .mmap = msm_gem_mmap,
1063 };
1064
1065 static struct drm_driver msm_driver = {
1066 .driver_features = DRIVER_HAVE_IRQ |
1067 DRIVER_GEM |
1068 DRIVER_PRIME |
1069 DRIVER_RENDER |
1070 DRIVER_ATOMIC |
1071 DRIVER_MODESET,
1072 .open = msm_open,
1073 .postclose = msm_postclose,
1074 .lastclose = drm_fb_helper_lastclose,
1075 .irq_handler = msm_irq,
1076 .irq_preinstall = msm_irq_preinstall,
1077 .irq_postinstall = msm_irq_postinstall,
1078 .irq_uninstall = msm_irq_uninstall,
1079 .enable_vblank = msm_enable_vblank,
1080 .disable_vblank = msm_disable_vblank,
1081 .gem_free_object = msm_gem_free_object,
1082 .gem_vm_ops = &vm_ops,
1083 .dumb_create = msm_gem_dumb_create,
1084 .dumb_map_offset = msm_gem_dumb_map_offset,
1085 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1086 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1087 .gem_prime_export = drm_gem_prime_export,
1088 .gem_prime_import = drm_gem_prime_import,
1089 .gem_prime_res_obj = msm_gem_prime_res_obj,
1090 .gem_prime_pin = msm_gem_prime_pin,
1091 .gem_prime_unpin = msm_gem_prime_unpin,
1092 .gem_prime_get_sg_table = msm_gem_prime_get_sg_table,
1093 .gem_prime_import_sg_table = msm_gem_prime_import_sg_table,
1094 .gem_prime_vmap = msm_gem_prime_vmap,
1095 .gem_prime_vunmap = msm_gem_prime_vunmap,
1096 .gem_prime_mmap = msm_gem_prime_mmap,
1097 #ifdef CONFIG_DEBUG_FS
1098 .debugfs_init = msm_debugfs_init,
1099 #endif
1100 .ioctls = msm_ioctls,
1101 .num_ioctls = ARRAY_SIZE(msm_ioctls),
1102 .fops = &fops,
1103 .name = "msm",
1104 .desc = "MSM Snapdragon DRM",
1105 .date = "20130625",
1106 .major = MSM_VERSION_MAJOR,
1107 .minor = MSM_VERSION_MINOR,
1108 .patchlevel = MSM_VERSION_PATCHLEVEL,
1109 };
1110
1111 #ifdef CONFIG_PM_SLEEP
1112 static int msm_pm_suspend(struct device *dev)
1113 {
1114 struct drm_device *ddev = dev_get_drvdata(dev);
1115 struct msm_drm_private *priv = ddev->dev_private;
1116
1117 if (WARN_ON(priv->pm_state))
1118 drm_atomic_state_put(priv->pm_state);
1119
1120 priv->pm_state = drm_atomic_helper_suspend(ddev);
1121 if (IS_ERR(priv->pm_state)) {
1122 int ret = PTR_ERR(priv->pm_state);
1123 DRM_ERROR("Failed to suspend dpu, %d\n", ret);
1124 return ret;
1125 }
1126
1127 return 0;
1128 }
1129
1130 static int msm_pm_resume(struct device *dev)
1131 {
1132 struct drm_device *ddev = dev_get_drvdata(dev);
1133 struct msm_drm_private *priv = ddev->dev_private;
1134 int ret;
1135
1136 if (WARN_ON(!priv->pm_state))
1137 return -ENOENT;
1138
1139 ret = drm_atomic_helper_resume(ddev, priv->pm_state);
1140 if (!ret)
1141 priv->pm_state = NULL;
1142
1143 return ret;
1144 }
1145 #endif
1146
1147 #ifdef CONFIG_PM
1148 static int msm_runtime_suspend(struct device *dev)
1149 {
1150 struct drm_device *ddev = dev_get_drvdata(dev);
1151 struct msm_drm_private *priv = ddev->dev_private;
1152 struct msm_mdss *mdss = priv->mdss;
1153
1154 DBG("");
1155
1156 if (mdss && mdss->funcs)
1157 return mdss->funcs->disable(mdss);
1158
1159 return 0;
1160 }
1161
1162 static int msm_runtime_resume(struct device *dev)
1163 {
1164 struct drm_device *ddev = dev_get_drvdata(dev);
1165 struct msm_drm_private *priv = ddev->dev_private;
1166 struct msm_mdss *mdss = priv->mdss;
1167
1168 DBG("");
1169
1170 if (mdss && mdss->funcs)
1171 return mdss->funcs->enable(mdss);
1172
1173 return 0;
1174 }
1175 #endif
1176
1177 static const struct dev_pm_ops msm_pm_ops = {
1178 SET_SYSTEM_SLEEP_PM_OPS(msm_pm_suspend, msm_pm_resume)
1179 SET_RUNTIME_PM_OPS(msm_runtime_suspend, msm_runtime_resume, NULL)
1180 };
1181
1182 /*
1183 * Componentized driver support:
1184 */
1185
1186 /*
1187 * NOTE: duplication of the same code as exynos or imx (or probably any other).
1188 * so probably some room for some helpers
1189 */
1190 static int compare_of(struct device *dev, void *data)
1191 {
1192 return dev->of_node == data;
1193 }
1194
1195 /*
1196 * Identify what components need to be added by parsing what remote-endpoints
1197 * our MDP output ports are connected to. In the case of LVDS on MDP4, there
1198 * is no external component that we need to add since LVDS is within MDP4
1199 * itself.
1200 */
1201 static int add_components_mdp(struct device *mdp_dev,
1202 struct component_match **matchptr)
1203 {
1204 struct device_node *np = mdp_dev->of_node;
1205 struct device_node *ep_node;
1206 struct device *master_dev;
1207
1208 /*
1209 * on MDP4 based platforms, the MDP platform device is the component
1210 * master that adds other display interface components to itself.
1211 *
1212 * on MDP5 based platforms, the MDSS platform device is the component
1213 * master that adds MDP5 and other display interface components to
1214 * itself.
1215 */
1216 if (of_device_is_compatible(np, "qcom,mdp4"))
1217 master_dev = mdp_dev;
1218 else
1219 master_dev = mdp_dev->parent;
1220
1221 for_each_endpoint_of_node(np, ep_node) {
1222 struct device_node *intf;
1223 struct of_endpoint ep;
1224 int ret;
1225
1226 ret = of_graph_parse_endpoint(ep_node, &ep);
1227 if (ret) {
1228 DRM_DEV_ERROR(mdp_dev, "unable to parse port endpoint\n");
1229 of_node_put(ep_node);
1230 return ret;
1231 }
1232
1233 /*
1234 * The LCDC/LVDS port on MDP4 is a speacial case where the
1235 * remote-endpoint isn't a component that we need to add
1236 */
1237 if (of_device_is_compatible(np, "qcom,mdp4") &&
1238 ep.port == 0)
1239 continue;
1240
1241 /*
1242 * It's okay if some of the ports don't have a remote endpoint
1243 * specified. It just means that the port isn't connected to
1244 * any external interface.
1245 */
1246 intf = of_graph_get_remote_port_parent(ep_node);
1247 if (!intf)
1248 continue;
1249
1250 if (of_device_is_available(intf))
1251 drm_of_component_match_add(master_dev, matchptr,
1252 compare_of, intf);
1253
1254 of_node_put(intf);
1255 }
1256
1257 return 0;
1258 }
1259
1260 static int compare_name_mdp(struct device *dev, void *data)
1261 {
1262 return (strstr(dev_name(dev), "mdp") != NULL);
1263 }
1264
1265 static int add_display_components(struct device *dev,
1266 struct component_match **matchptr)
1267 {
1268 struct device *mdp_dev;
1269 int ret;
1270
1271 /*
1272 * MDP5/DPU based devices don't have a flat hierarchy. There is a top
1273 * level parent: MDSS, and children: MDP5/DPU, DSI, HDMI, eDP etc.
1274 * Populate the children devices, find the MDP5/DPU node, and then add
1275 * the interfaces to our components list.
1276 */
1277 if (of_device_is_compatible(dev->of_node, "qcom,mdss") ||
1278 of_device_is_compatible(dev->of_node, "qcom,sdm845-mdss")) {
1279 ret = of_platform_populate(dev->of_node, NULL, NULL, dev);
1280 if (ret) {
1281 DRM_DEV_ERROR(dev, "failed to populate children devices\n");
1282 return ret;
1283 }
1284
1285 mdp_dev = device_find_child(dev, NULL, compare_name_mdp);
1286 if (!mdp_dev) {
1287 DRM_DEV_ERROR(dev, "failed to find MDSS MDP node\n");
1288 of_platform_depopulate(dev);
1289 return -ENODEV;
1290 }
1291
1292 put_device(mdp_dev);
1293
1294 /* add the MDP component itself */
1295 drm_of_component_match_add(dev, matchptr, compare_of,
1296 mdp_dev->of_node);
1297 } else {
1298 /* MDP4 */
1299 mdp_dev = dev;
1300 }
1301
1302 ret = add_components_mdp(mdp_dev, matchptr);
1303 if (ret)
1304 of_platform_depopulate(dev);
1305
1306 return ret;
1307 }
1308
1309 /*
1310 * We don't know what's the best binding to link the gpu with the drm device.
1311 * Fow now, we just hunt for all the possible gpus that we support, and add them
1312 * as components.
1313 */
1314 static const struct of_device_id msm_gpu_match[] = {
1315 { .compatible = "qcom,adreno" },
1316 { .compatible = "qcom,adreno-3xx" },
1317 { .compatible = "amd,imageon" },
1318 { .compatible = "qcom,kgsl-3d0" },
1319 { },
1320 };
1321
1322 static int add_gpu_components(struct device *dev,
1323 struct component_match **matchptr)
1324 {
1325 struct device_node *np;
1326
1327 np = of_find_matching_node(NULL, msm_gpu_match);
1328 if (!np)
1329 return 0;
1330
1331 drm_of_component_match_add(dev, matchptr, compare_of, np);
1332
1333 of_node_put(np);
1334
1335 return 0;
1336 }
1337
1338 static int msm_drm_bind(struct device *dev)
1339 {
1340 return msm_drm_init(dev, &msm_driver);
1341 }
1342
1343 static void msm_drm_unbind(struct device *dev)
1344 {
1345 msm_drm_uninit(dev);
1346 }
1347
1348 static const struct component_master_ops msm_drm_ops = {
1349 .bind = msm_drm_bind,
1350 .unbind = msm_drm_unbind,
1351 };
1352
1353 /*
1354 * Platform driver:
1355 */
1356
1357 static int msm_pdev_probe(struct platform_device *pdev)
1358 {
1359 struct component_match *match = NULL;
1360 int ret;
1361
1362 if (get_mdp_ver(pdev)) {
1363 ret = add_display_components(&pdev->dev, &match);
1364 if (ret)
1365 return ret;
1366 }
1367
1368 ret = add_gpu_components(&pdev->dev, &match);
1369 if (ret)
1370 return ret;
1371
1372 /* on all devices that I am aware of, iommu's which can map
1373 * any address the cpu can see are used:
1374 */
1375 ret = dma_set_mask_and_coherent(&pdev->dev, ~0);
1376 if (ret)
1377 return ret;
1378
1379 return component_master_add_with_match(&pdev->dev, &msm_drm_ops, match);
1380 }
1381
1382 static int msm_pdev_remove(struct platform_device *pdev)
1383 {
1384 component_master_del(&pdev->dev, &msm_drm_ops);
1385 of_platform_depopulate(&pdev->dev);
1386
1387 return 0;
1388 }
1389
1390 static const struct of_device_id dt_match[] = {
1391 { .compatible = "qcom,mdp4", .data = (void *)KMS_MDP4 },
1392 { .compatible = "qcom,mdss", .data = (void *)KMS_MDP5 },
1393 { .compatible = "qcom,sdm845-mdss", .data = (void *)KMS_DPU },
1394 {}
1395 };
1396 MODULE_DEVICE_TABLE(of, dt_match);
1397
1398 static struct platform_driver msm_platform_driver = {
1399 .probe = msm_pdev_probe,
1400 .remove = msm_pdev_remove,
1401 .driver = {
1402 .name = "msm",
1403 .of_match_table = dt_match,
1404 .pm = &msm_pm_ops,
1405 },
1406 };
1407
1408 static int __init msm_drm_register(void)
1409 {
1410 if (!modeset)
1411 return -EINVAL;
1412
1413 DBG("init");
1414 msm_mdp_register();
1415 msm_dpu_register();
1416 msm_dsi_register();
1417 msm_edp_register();
1418 msm_hdmi_register();
1419 adreno_register();
1420 return platform_driver_register(&msm_platform_driver);
1421 }
1422
1423 static void __exit msm_drm_unregister(void)
1424 {
1425 DBG("fini");
1426 platform_driver_unregister(&msm_platform_driver);
1427 msm_hdmi_unregister();
1428 adreno_unregister();
1429 msm_edp_unregister();
1430 msm_dsi_unregister();
1431 msm_mdp_unregister();
1432 msm_dpu_unregister();
1433 }
1434
1435 module_init(msm_drm_register);
1436 module_exit(msm_drm_unregister);
1437
1438 MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
1439 MODULE_DESCRIPTION("MSM DRM Driver");
1440 MODULE_LICENSE("GPL");
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git