2 * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
3 * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
18 #ifndef __OMAP_DRM_DSS_H
19 #define __OMAP_DRM_DSS_H
21 #include <linux/list.h>
22 #include <linux/kobject.h>
23 #include <linux/device.h>
24 #include <linux/interrupt.h>
25 #include <video/videomode.h>
26 #include <linux/platform_data/omapdss.h>
27 #include <uapi/drm/drm_mode.h>
28 #include <drm/drm_crtc.h>
30 #define DISPC_IRQ_FRAMEDONE (1 << 0)
31 #define DISPC_IRQ_VSYNC (1 << 1)
32 #define DISPC_IRQ_EVSYNC_EVEN (1 << 2)
33 #define DISPC_IRQ_EVSYNC_ODD (1 << 3)
34 #define DISPC_IRQ_ACBIAS_COUNT_STAT (1 << 4)
35 #define DISPC_IRQ_PROG_LINE_NUM (1 << 5)
36 #define DISPC_IRQ_GFX_FIFO_UNDERFLOW (1 << 6)
37 #define DISPC_IRQ_GFX_END_WIN (1 << 7)
38 #define DISPC_IRQ_PAL_GAMMA_MASK (1 << 8)
39 #define DISPC_IRQ_OCP_ERR (1 << 9)
40 #define DISPC_IRQ_VID1_FIFO_UNDERFLOW (1 << 10)
41 #define DISPC_IRQ_VID1_END_WIN (1 << 11)
42 #define DISPC_IRQ_VID2_FIFO_UNDERFLOW (1 << 12)
43 #define DISPC_IRQ_VID2_END_WIN (1 << 13)
44 #define DISPC_IRQ_SYNC_LOST (1 << 14)
45 #define DISPC_IRQ_SYNC_LOST_DIGIT (1 << 15)
46 #define DISPC_IRQ_WAKEUP (1 << 16)
47 #define DISPC_IRQ_SYNC_LOST2 (1 << 17)
48 #define DISPC_IRQ_VSYNC2 (1 << 18)
49 #define DISPC_IRQ_VID3_END_WIN (1 << 19)
50 #define DISPC_IRQ_VID3_FIFO_UNDERFLOW (1 << 20)
51 #define DISPC_IRQ_ACBIAS_COUNT_STAT2 (1 << 21)
52 #define DISPC_IRQ_FRAMEDONE2 (1 << 22)
53 #define DISPC_IRQ_FRAMEDONEWB (1 << 23)
54 #define DISPC_IRQ_FRAMEDONETV (1 << 24)
55 #define DISPC_IRQ_WBBUFFEROVERFLOW (1 << 25)
56 #define DISPC_IRQ_WBUNCOMPLETEERROR (1 << 26)
57 #define DISPC_IRQ_SYNC_LOST3 (1 << 27)
58 #define DISPC_IRQ_VSYNC3 (1 << 28)
59 #define DISPC_IRQ_ACBIAS_COUNT_STAT3 (1 << 29)
60 #define DISPC_IRQ_FRAMEDONE3 (1 << 30)
63 struct omap_drm_private
;
64 struct omap_dss_device
;
67 struct dss_lcd_mgr_config
;
68 struct snd_aes_iec958
;
69 struct snd_cea_861_aud_if
;
70 struct hdmi_avi_infoframe
;
72 enum omap_display_type
{
73 OMAP_DISPLAY_TYPE_NONE
= 0,
74 OMAP_DISPLAY_TYPE_DPI
= 1 << 0,
75 OMAP_DISPLAY_TYPE_DBI
= 1 << 1,
76 OMAP_DISPLAY_TYPE_SDI
= 1 << 2,
77 OMAP_DISPLAY_TYPE_DSI
= 1 << 3,
78 OMAP_DISPLAY_TYPE_VENC
= 1 << 4,
79 OMAP_DISPLAY_TYPE_HDMI
= 1 << 5,
80 OMAP_DISPLAY_TYPE_DVI
= 1 << 6,
92 OMAP_DSS_CHANNEL_LCD
= 0,
93 OMAP_DSS_CHANNEL_DIGIT
= 1,
94 OMAP_DSS_CHANNEL_LCD2
= 2,
95 OMAP_DSS_CHANNEL_LCD3
= 3,
96 OMAP_DSS_CHANNEL_WB
= 4,
99 enum omap_color_mode
{
103 enum omap_dss_load_mode
{
104 OMAP_DSS_LOAD_CLUT_AND_FRAME
= 0,
105 OMAP_DSS_LOAD_CLUT_ONLY
= 1,
106 OMAP_DSS_LOAD_FRAME_ONLY
= 2,
107 OMAP_DSS_LOAD_CLUT_ONCE_FRAME
= 3,
110 enum omap_dss_trans_key_type
{
111 OMAP_DSS_COLOR_KEY_GFX_DST
= 0,
112 OMAP_DSS_COLOR_KEY_VID_SRC
= 1,
115 enum omap_dss_signal_level
{
116 OMAPDSS_SIG_ACTIVE_LOW
,
117 OMAPDSS_SIG_ACTIVE_HIGH
,
120 enum omap_dss_signal_edge
{
121 OMAPDSS_DRIVE_SIG_FALLING_EDGE
,
122 OMAPDSS_DRIVE_SIG_RISING_EDGE
,
125 enum omap_dss_venc_type
{
126 OMAP_DSS_VENC_TYPE_COMPOSITE
,
127 OMAP_DSS_VENC_TYPE_SVIDEO
,
130 enum omap_dss_dsi_pixel_format
{
131 OMAP_DSS_DSI_FMT_RGB888
,
132 OMAP_DSS_DSI_FMT_RGB666
,
133 OMAP_DSS_DSI_FMT_RGB666_PACKED
,
134 OMAP_DSS_DSI_FMT_RGB565
,
137 enum omap_dss_dsi_mode
{
138 OMAP_DSS_DSI_CMD_MODE
= 0,
139 OMAP_DSS_DSI_VIDEO_MODE
,
142 enum omap_display_caps
{
143 OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE
= 1 << 0,
144 OMAP_DSS_DISPLAY_CAP_TEAR_ELIM
= 1 << 1,
147 enum omap_dss_display_state
{
148 OMAP_DSS_DISPLAY_DISABLED
= 0,
149 OMAP_DSS_DISPLAY_ACTIVE
,
152 enum omap_dss_rotation_type
{
153 OMAP_DSS_ROT_NONE
= 0,
154 OMAP_DSS_ROT_TILER
= 1 << 0,
157 enum omap_overlay_caps
{
158 OMAP_DSS_OVL_CAP_SCALE
= 1 << 0,
159 OMAP_DSS_OVL_CAP_GLOBAL_ALPHA
= 1 << 1,
160 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA
= 1 << 2,
161 OMAP_DSS_OVL_CAP_ZORDER
= 1 << 3,
162 OMAP_DSS_OVL_CAP_POS
= 1 << 4,
163 OMAP_DSS_OVL_CAP_REPLICATION
= 1 << 5,
166 enum omap_dss_output_id
{
167 OMAP_DSS_OUTPUT_DPI
= 1 << 0,
168 OMAP_DSS_OUTPUT_DBI
= 1 << 1,
169 OMAP_DSS_OUTPUT_SDI
= 1 << 2,
170 OMAP_DSS_OUTPUT_DSI1
= 1 << 3,
171 OMAP_DSS_OUTPUT_DSI2
= 1 << 4,
172 OMAP_DSS_OUTPUT_VENC
= 1 << 5,
173 OMAP_DSS_OUTPUT_HDMI
= 1 << 6,
178 enum omap_dss_dsi_trans_mode
{
179 /* Sync Pulses: both sync start and end packets sent */
180 OMAP_DSS_DSI_PULSE_MODE
,
181 /* Sync Events: only sync start packets sent */
182 OMAP_DSS_DSI_EVENT_MODE
,
183 /* Burst: only sync start packets sent, pixels are time compressed */
184 OMAP_DSS_DSI_BURST_MODE
,
187 struct omap_dss_dsi_videomode_timings
{
198 /* DSI video mode blanking data */
199 /* Unit: byte clock cycles */
205 /* Unit: line clocks */
210 /* DSI blanking modes */
212 int hsa_blanking_mode
;
213 int hbp_blanking_mode
;
214 int hfp_blanking_mode
;
216 enum omap_dss_dsi_trans_mode trans_mode
;
218 bool ddr_clk_always_on
;
222 struct omap_dss_dsi_config
{
223 enum omap_dss_dsi_mode mode
;
224 enum omap_dss_dsi_pixel_format pixel_format
;
225 const struct videomode
*vm
;
227 unsigned long hs_clk_min
, hs_clk_max
;
228 unsigned long lp_clk_min
, lp_clk_max
;
230 bool ddr_clk_always_on
;
231 enum omap_dss_dsi_trans_mode trans_mode
;
234 struct omap_dss_cpr_coefs
{
240 struct omap_overlay_info
{
242 dma_addr_t p_uv_addr
; /* for NV12 format */
248 enum omap_dss_rotation_type rotation_type
;
252 u16 out_width
; /* if 0, out_width == width */
253 u16 out_height
; /* if 0, out_height == height */
259 struct omap_overlay_manager_info
{
262 enum omap_dss_trans_key_type trans_key_type
;
266 bool partial_alpha_enabled
;
269 struct omap_dss_cpr_coefs cpr_coefs
;
272 /* 22 pins means 1 clk lane and 10 data lanes */
273 #define OMAP_DSS_MAX_DSI_PINS 22
275 struct omap_dsi_pin_config
{
278 * pin numbers in the following order:
284 int pins
[OMAP_DSS_MAX_DSI_PINS
];
287 struct omap_dss_writeback_info
{
295 enum omap_dss_rotation_type rotation_type
;
299 struct omapdss_hdmi_ops
{
300 void (*lost_hotplug
)(struct omap_dss_device
*dssdev
);
301 int (*set_hdmi_mode
)(struct omap_dss_device
*dssdev
, bool hdmi_mode
);
302 int (*set_infoframe
)(struct omap_dss_device
*dssdev
,
303 const struct hdmi_avi_infoframe
*avi
);
306 struct omapdss_dsi_ops
{
307 void (*disable
)(struct omap_dss_device
*dssdev
, bool disconnect_lanes
,
310 /* bus configuration */
311 int (*set_config
)(struct omap_dss_device
*dssdev
,
312 const struct omap_dss_dsi_config
*cfg
);
313 int (*configure_pins
)(struct omap_dss_device
*dssdev
,
314 const struct omap_dsi_pin_config
*pin_cfg
);
316 void (*enable_hs
)(struct omap_dss_device
*dssdev
, int channel
,
318 int (*enable_te
)(struct omap_dss_device
*dssdev
, bool enable
);
320 int (*update
)(struct omap_dss_device
*dssdev
, int channel
,
321 void (*callback
)(int, void *), void *data
);
323 void (*bus_lock
)(struct omap_dss_device
*dssdev
);
324 void (*bus_unlock
)(struct omap_dss_device
*dssdev
);
326 int (*enable_video_output
)(struct omap_dss_device
*dssdev
, int channel
);
327 void (*disable_video_output
)(struct omap_dss_device
*dssdev
,
330 int (*request_vc
)(struct omap_dss_device
*dssdev
, int *channel
);
331 int (*set_vc_id
)(struct omap_dss_device
*dssdev
, int channel
,
333 void (*release_vc
)(struct omap_dss_device
*dssdev
, int channel
);
336 int (*dcs_write
)(struct omap_dss_device
*dssdev
, int channel
,
338 int (*dcs_write_nosync
)(struct omap_dss_device
*dssdev
, int channel
,
340 int (*dcs_read
)(struct omap_dss_device
*dssdev
, int channel
, u8 dcs_cmd
,
343 int (*gen_write
)(struct omap_dss_device
*dssdev
, int channel
,
345 int (*gen_write_nosync
)(struct omap_dss_device
*dssdev
, int channel
,
347 int (*gen_read
)(struct omap_dss_device
*dssdev
, int channel
,
348 u8
*reqdata
, int reqlen
,
351 int (*bta_sync
)(struct omap_dss_device
*dssdev
, int channel
);
353 int (*set_max_rx_packet_size
)(struct omap_dss_device
*dssdev
,
354 int channel
, u16 plen
);
357 struct omap_dss_device_ops
{
358 int (*connect
)(struct omap_dss_device
*dssdev
,
359 struct omap_dss_device
*dst
);
360 void (*disconnect
)(struct omap_dss_device
*dssdev
,
361 struct omap_dss_device
*dst
);
363 int (*enable
)(struct omap_dss_device
*dssdev
);
364 void (*disable
)(struct omap_dss_device
*dssdev
);
366 int (*check_timings
)(struct omap_dss_device
*dssdev
,
367 struct videomode
*vm
);
368 void (*get_timings
)(struct omap_dss_device
*dssdev
,
369 struct videomode
*vm
);
370 void (*set_timings
)(struct omap_dss_device
*dssdev
,
371 const struct videomode
*vm
);
373 bool (*detect
)(struct omap_dss_device
*dssdev
);
375 void (*register_hpd_cb
)(struct omap_dss_device
*dssdev
,
376 void (*cb
)(void *cb_data
,
377 enum drm_connector_status status
),
379 void (*unregister_hpd_cb
)(struct omap_dss_device
*dssdev
);
381 int (*read_edid
)(struct omap_dss_device
*dssdev
, u8
*buf
, int len
);
384 const struct omapdss_hdmi_ops hdmi
;
385 const struct omapdss_dsi_ops dsi
;
390 * enum omap_dss_device_ops_flag - Indicates which device ops are supported
391 * @OMAP_DSS_DEVICE_OP_DETECT: The device supports output connection detection
392 * @OMAP_DSS_DEVICE_OP_HPD: The device supports all hot-plug-related operations
393 * @OMAP_DSS_DEVICE_OP_EDID: The device supports readind EDID
395 enum omap_dss_device_ops_flag
{
396 OMAP_DSS_DEVICE_OP_DETECT
= BIT(0),
397 OMAP_DSS_DEVICE_OP_HPD
= BIT(1),
398 OMAP_DSS_DEVICE_OP_EDID
= BIT(2),
401 enum omap_dss_device_type
{
402 OMAP_DSS_DEVICE_TYPE_OUTPUT
= (1 << 0),
403 OMAP_DSS_DEVICE_TYPE_DISPLAY
= (1 << 1),
406 struct omap_dss_device
{
410 struct module
*owner
;
412 struct dss_device
*dss
;
413 struct omap_dss_device
*src
;
414 struct omap_dss_device
*dst
;
415 struct omap_dss_device
*next
;
417 struct list_head list
;
419 unsigned int alias_id
;
421 enum omap_display_type type
;
423 * DSS output type that this device generates (for DSS internal devices)
424 * or requires (for external encoders). Must be OMAP_DISPLAY_TYPE_NONE
425 * for display devices (connectors and panels) and to non-zero value for
428 enum omap_display_type output_type
;
432 const struct omap_dss_driver
*driver
;
433 const struct omap_dss_device_ops
*ops
;
434 unsigned long ops_flags
;
437 /* helper variable for driver suspend/resume */
438 bool activate_after_resume
;
440 enum omap_display_caps caps
;
442 enum omap_dss_display_state state
;
444 /* OMAP DSS output specific fields */
446 /* DISPC channel for this output */
447 enum omap_channel dispc_channel
;
448 bool dispc_channel_connected
;
450 /* output instance */
451 enum omap_dss_output_id id
;
453 /* bitmask of port numbers in DT */
454 unsigned int of_ports
;
457 struct omap_dss_driver
{
458 int (*update
)(struct omap_dss_device
*dssdev
,
459 u16 x
, u16 y
, u16 w
, u16 h
);
460 int (*sync
)(struct omap_dss_device
*dssdev
);
462 int (*enable_te
)(struct omap_dss_device
*dssdev
, bool enable
);
463 int (*get_te
)(struct omap_dss_device
*dssdev
);
465 int (*memory_read
)(struct omap_dss_device
*dssdev
,
466 void *buf
, size_t size
,
467 u16 x
, u16 y
, u16 w
, u16 h
);
469 void (*get_size
)(struct omap_dss_device
*dssdev
,
470 unsigned int *width
, unsigned int *height
);
473 struct dss_device
*omapdss_get_dss(void);
474 void omapdss_set_dss(struct dss_device
*dss
);
475 static inline bool omapdss_is_initialized(void)
477 return !!omapdss_get_dss();
480 #define for_each_dss_display(d) \
481 while ((d = omapdss_device_get_next(d, OMAP_DSS_DEVICE_TYPE_DISPLAY)) != NULL)
482 void omapdss_display_init(struct omap_dss_device
*dssdev
);
483 struct omap_dss_device
*omapdss_display_get(struct omap_dss_device
*output
);
485 void omapdss_device_register(struct omap_dss_device
*dssdev
);
486 void omapdss_device_unregister(struct omap_dss_device
*dssdev
);
487 struct omap_dss_device
*omapdss_device_get(struct omap_dss_device
*dssdev
);
488 void omapdss_device_put(struct omap_dss_device
*dssdev
);
489 struct omap_dss_device
*omapdss_find_device_by_port(struct device_node
*src
,
491 struct omap_dss_device
*omapdss_device_get_next(struct omap_dss_device
*from
,
492 enum omap_dss_device_type type
);
493 int omapdss_device_connect(struct dss_device
*dss
,
494 struct omap_dss_device
*src
,
495 struct omap_dss_device
*dst
);
496 void omapdss_device_disconnect(struct omap_dss_device
*src
,
497 struct omap_dss_device
*dst
);
499 int omap_dss_get_num_overlay_managers(void);
501 int omap_dss_get_num_overlays(void);
503 #define for_each_dss_output(d) \
504 while ((d = omapdss_device_get_next(d, OMAP_DSS_DEVICE_TYPE_OUTPUT)) != NULL)
505 int omapdss_output_validate(struct omap_dss_device
*out
);
507 typedef void (*omap_dispc_isr_t
) (void *arg
, u32 mask
);
508 int omap_dispc_register_isr(omap_dispc_isr_t isr
, void *arg
, u32 mask
);
509 int omap_dispc_unregister_isr(omap_dispc_isr_t isr
, void *arg
, u32 mask
);
511 int omapdss_compat_init(void);
512 void omapdss_compat_uninit(void);
514 static inline bool omapdss_device_is_connected(struct omap_dss_device
*dssdev
)
519 static inline bool omapdss_device_is_enabled(struct omap_dss_device
*dssdev
)
521 return dssdev
->state
== OMAP_DSS_DISPLAY_ACTIVE
;
524 struct omap_dss_device
*
525 omapdss_of_find_connected_device(struct device_node
*node
, unsigned int port
);
527 enum dss_writeback_channel
{
539 void (*start_update
)(struct omap_drm_private
*priv
,
540 enum omap_channel channel
);
541 int (*enable
)(struct omap_drm_private
*priv
,
542 enum omap_channel channel
);
543 void (*disable
)(struct omap_drm_private
*priv
,
544 enum omap_channel channel
);
545 void (*set_timings
)(struct omap_drm_private
*priv
,
546 enum omap_channel channel
,
547 const struct videomode
*vm
);
548 void (*set_lcd_config
)(struct omap_drm_private
*priv
,
549 enum omap_channel channel
,
550 const struct dss_lcd_mgr_config
*config
);
551 int (*register_framedone_handler
)(struct omap_drm_private
*priv
,
552 enum omap_channel channel
,
553 void (*handler
)(void *), void *data
);
554 void (*unregister_framedone_handler
)(struct omap_drm_private
*priv
,
555 enum omap_channel channel
,
556 void (*handler
)(void *), void *data
);
559 int dss_install_mgr_ops(struct dss_device
*dss
,
560 const struct dss_mgr_ops
*mgr_ops
,
561 struct omap_drm_private
*priv
);
562 void dss_uninstall_mgr_ops(struct dss_device
*dss
);
564 void dss_mgr_set_timings(struct omap_dss_device
*dssdev
,
565 const struct videomode
*vm
);
566 void dss_mgr_set_lcd_config(struct omap_dss_device
*dssdev
,
567 const struct dss_lcd_mgr_config
*config
);
568 int dss_mgr_enable(struct omap_dss_device
*dssdev
);
569 void dss_mgr_disable(struct omap_dss_device
*dssdev
);
570 void dss_mgr_start_update(struct omap_dss_device
*dssdev
);
571 int dss_mgr_register_framedone_handler(struct omap_dss_device
*dssdev
,
572 void (*handler
)(void *), void *data
);
573 void dss_mgr_unregister_framedone_handler(struct omap_dss_device
*dssdev
,
574 void (*handler
)(void *), void *data
);
579 u32 (*read_irqstatus
)(struct dispc_device
*dispc
);
580 void (*clear_irqstatus
)(struct dispc_device
*dispc
, u32 mask
);
581 void (*write_irqenable
)(struct dispc_device
*dispc
, u32 mask
);
583 int (*request_irq
)(struct dispc_device
*dispc
, irq_handler_t handler
,
585 void (*free_irq
)(struct dispc_device
*dispc
, void *dev_id
);
587 int (*runtime_get
)(struct dispc_device
*dispc
);
588 void (*runtime_put
)(struct dispc_device
*dispc
);
590 int (*get_num_ovls
)(struct dispc_device
*dispc
);
591 int (*get_num_mgrs
)(struct dispc_device
*dispc
);
593 u32 (*get_memory_bandwidth_limit
)(struct dispc_device
*dispc
);
595 void (*mgr_enable
)(struct dispc_device
*dispc
,
596 enum omap_channel channel
, bool enable
);
597 bool (*mgr_is_enabled
)(struct dispc_device
*dispc
,
598 enum omap_channel channel
);
599 u32 (*mgr_get_vsync_irq
)(struct dispc_device
*dispc
,
600 enum omap_channel channel
);
601 u32 (*mgr_get_framedone_irq
)(struct dispc_device
*dispc
,
602 enum omap_channel channel
);
603 u32 (*mgr_get_sync_lost_irq
)(struct dispc_device
*dispc
,
604 enum omap_channel channel
);
605 bool (*mgr_go_busy
)(struct dispc_device
*dispc
,
606 enum omap_channel channel
);
607 void (*mgr_go
)(struct dispc_device
*dispc
, enum omap_channel channel
);
608 void (*mgr_set_lcd_config
)(struct dispc_device
*dispc
,
609 enum omap_channel channel
,
610 const struct dss_lcd_mgr_config
*config
);
611 int (*mgr_check_timings
)(struct dispc_device
*dispc
,
612 enum omap_channel channel
,
613 const struct videomode
*vm
);
614 void (*mgr_set_timings
)(struct dispc_device
*dispc
,
615 enum omap_channel channel
,
616 const struct videomode
*vm
);
617 void (*mgr_setup
)(struct dispc_device
*dispc
, enum omap_channel channel
,
618 const struct omap_overlay_manager_info
*info
);
619 u32 (*mgr_gamma_size
)(struct dispc_device
*dispc
,
620 enum omap_channel channel
);
621 void (*mgr_set_gamma
)(struct dispc_device
*dispc
,
622 enum omap_channel channel
,
623 const struct drm_color_lut
*lut
,
624 unsigned int length
);
626 int (*ovl_enable
)(struct dispc_device
*dispc
, enum omap_plane_id plane
,
628 int (*ovl_setup
)(struct dispc_device
*dispc
, enum omap_plane_id plane
,
629 const struct omap_overlay_info
*oi
,
630 const struct videomode
*vm
, bool mem_to_mem
,
631 enum omap_channel channel
);
633 const u32
*(*ovl_get_color_modes
)(struct dispc_device
*dispc
,
634 enum omap_plane_id plane
);
636 u32 (*wb_get_framedone_irq
)(struct dispc_device
*dispc
);
637 int (*wb_setup
)(struct dispc_device
*dispc
,
638 const struct omap_dss_writeback_info
*wi
,
639 bool mem_to_mem
, const struct videomode
*vm
,
640 enum dss_writeback_channel channel_in
);
641 bool (*has_writeback
)(struct dispc_device
*dispc
);
642 bool (*wb_go_busy
)(struct dispc_device
*dispc
);
643 void (*wb_go
)(struct dispc_device
*dispc
);
646 struct dispc_device
*dispc_get_dispc(struct dss_device
*dss
);
647 const struct dispc_ops
*dispc_get_ops(struct dss_device
*dss
);
649 bool omapdss_stack_is_ready(void);
650 void omapdss_gather_components(struct device
*dev
);
652 #endif /* __OMAP_DRM_DSS_H */