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[thirdparty/kernel/stable.git] / drivers / gpu / drm / radeon / evergreen.c
1 /*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24 #include <linux/firmware.h>
25 #include <linux/platform_device.h>
26 #include <linux/slab.h>
27 #include "drmP.h"
28 #include "radeon.h"
29 #include "radeon_asic.h"
30 #include "radeon_drm.h"
31 #include "evergreend.h"
32 #include "atom.h"
33 #include "avivod.h"
34 #include "evergreen_reg.h"
35 #include "evergreen_blit_shaders.h"
36
37 #define EVERGREEN_PFP_UCODE_SIZE 1120
38 #define EVERGREEN_PM4_UCODE_SIZE 1376
39
40 static const u32 crtc_offsets[6] =
41 {
42 EVERGREEN_CRTC0_REGISTER_OFFSET,
43 EVERGREEN_CRTC1_REGISTER_OFFSET,
44 EVERGREEN_CRTC2_REGISTER_OFFSET,
45 EVERGREEN_CRTC3_REGISTER_OFFSET,
46 EVERGREEN_CRTC4_REGISTER_OFFSET,
47 EVERGREEN_CRTC5_REGISTER_OFFSET
48 };
49
50 static void evergreen_gpu_init(struct radeon_device *rdev);
51 void evergreen_fini(struct radeon_device *rdev);
52 void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
53 extern void cayman_cp_int_cntl_setup(struct radeon_device *rdev,
54 int ring, u32 cp_int_cntl);
55
56 void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
57 unsigned *bankh, unsigned *mtaspect,
58 unsigned *tile_split)
59 {
60 *bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
61 *bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
62 *mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
63 *tile_split = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
64 switch (*bankw) {
65 default:
66 case 1: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_1; break;
67 case 2: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_2; break;
68 case 4: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_4; break;
69 case 8: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_8; break;
70 }
71 switch (*bankh) {
72 default:
73 case 1: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_1; break;
74 case 2: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_2; break;
75 case 4: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_4; break;
76 case 8: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_8; break;
77 }
78 switch (*mtaspect) {
79 default:
80 case 1: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_1; break;
81 case 2: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_2; break;
82 case 4: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_4; break;
83 case 8: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_8; break;
84 }
85 }
86
87 void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev)
88 {
89 u16 ctl, v;
90 int cap, err;
91
92 cap = pci_pcie_cap(rdev->pdev);
93 if (!cap)
94 return;
95
96 err = pci_read_config_word(rdev->pdev, cap + PCI_EXP_DEVCTL, &ctl);
97 if (err)
98 return;
99
100 v = (ctl & PCI_EXP_DEVCTL_READRQ) >> 12;
101
102 /* if bios or OS sets MAX_READ_REQUEST_SIZE to an invalid value, fix it
103 * to avoid hangs or perfomance issues
104 */
105 if ((v == 0) || (v == 6) || (v == 7)) {
106 ctl &= ~PCI_EXP_DEVCTL_READRQ;
107 ctl |= (2 << 12);
108 pci_write_config_word(rdev->pdev, cap + PCI_EXP_DEVCTL, ctl);
109 }
110 }
111
112 /**
113 * dce4_wait_for_vblank - vblank wait asic callback.
114 *
115 * @rdev: radeon_device pointer
116 * @crtc: crtc to wait for vblank on
117 *
118 * Wait for vblank on the requested crtc (evergreen+).
119 */
120 void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc)
121 {
122 int i;
123
124 if (crtc >= rdev->num_crtc)
125 return;
126
127 if (RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[crtc]) & EVERGREEN_CRTC_MASTER_EN) {
128 for (i = 0; i < rdev->usec_timeout; i++) {
129 if (!(RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK))
130 break;
131 udelay(1);
132 }
133 for (i = 0; i < rdev->usec_timeout; i++) {
134 if (RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK)
135 break;
136 udelay(1);
137 }
138 }
139 }
140
141 /**
142 * radeon_irq_kms_pflip_irq_get - pre-pageflip callback.
143 *
144 * @rdev: radeon_device pointer
145 * @crtc: crtc to prepare for pageflip on
146 *
147 * Pre-pageflip callback (evergreen+).
148 * Enables the pageflip irq (vblank irq).
149 */
150 void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc)
151 {
152 /* enable the pflip int */
153 radeon_irq_kms_pflip_irq_get(rdev, crtc);
154 }
155
156 /**
157 * evergreen_post_page_flip - pos-pageflip callback.
158 *
159 * @rdev: radeon_device pointer
160 * @crtc: crtc to cleanup pageflip on
161 *
162 * Post-pageflip callback (evergreen+).
163 * Disables the pageflip irq (vblank irq).
164 */
165 void evergreen_post_page_flip(struct radeon_device *rdev, int crtc)
166 {
167 /* disable the pflip int */
168 radeon_irq_kms_pflip_irq_put(rdev, crtc);
169 }
170
171 /**
172 * evergreen_page_flip - pageflip callback.
173 *
174 * @rdev: radeon_device pointer
175 * @crtc_id: crtc to cleanup pageflip on
176 * @crtc_base: new address of the crtc (GPU MC address)
177 *
178 * Does the actual pageflip (evergreen+).
179 * During vblank we take the crtc lock and wait for the update_pending
180 * bit to go high, when it does, we release the lock, and allow the
181 * double buffered update to take place.
182 * Returns the current update pending status.
183 */
184 u32 evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
185 {
186 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
187 u32 tmp = RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset);
188 int i;
189
190 /* Lock the graphics update lock */
191 tmp |= EVERGREEN_GRPH_UPDATE_LOCK;
192 WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
193
194 /* update the scanout addresses */
195 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
196 upper_32_bits(crtc_base));
197 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
198 (u32)crtc_base);
199
200 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
201 upper_32_bits(crtc_base));
202 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
203 (u32)crtc_base);
204
205 /* Wait for update_pending to go high. */
206 for (i = 0; i < rdev->usec_timeout; i++) {
207 if (RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING)
208 break;
209 udelay(1);
210 }
211 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
212
213 /* Unlock the lock, so double-buffering can take place inside vblank */
214 tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK;
215 WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
216
217 /* Return current update_pending status: */
218 return RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING;
219 }
220
221 /* get temperature in millidegrees */
222 int evergreen_get_temp(struct radeon_device *rdev)
223 {
224 u32 temp, toffset;
225 int actual_temp = 0;
226
227 if (rdev->family == CHIP_JUNIPER) {
228 toffset = (RREG32(CG_THERMAL_CTRL) & TOFFSET_MASK) >>
229 TOFFSET_SHIFT;
230 temp = (RREG32(CG_TS0_STATUS) & TS0_ADC_DOUT_MASK) >>
231 TS0_ADC_DOUT_SHIFT;
232
233 if (toffset & 0x100)
234 actual_temp = temp / 2 - (0x200 - toffset);
235 else
236 actual_temp = temp / 2 + toffset;
237
238 actual_temp = actual_temp * 1000;
239
240 } else {
241 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
242 ASIC_T_SHIFT;
243
244 if (temp & 0x400)
245 actual_temp = -256;
246 else if (temp & 0x200)
247 actual_temp = 255;
248 else if (temp & 0x100) {
249 actual_temp = temp & 0x1ff;
250 actual_temp |= ~0x1ff;
251 } else
252 actual_temp = temp & 0xff;
253
254 actual_temp = (actual_temp * 1000) / 2;
255 }
256
257 return actual_temp;
258 }
259
260 int sumo_get_temp(struct radeon_device *rdev)
261 {
262 u32 temp = RREG32(CG_THERMAL_STATUS) & 0xff;
263 int actual_temp = temp - 49;
264
265 return actual_temp * 1000;
266 }
267
268 /**
269 * sumo_pm_init_profile - Initialize power profiles callback.
270 *
271 * @rdev: radeon_device pointer
272 *
273 * Initialize the power states used in profile mode
274 * (sumo, trinity, SI).
275 * Used for profile mode only.
276 */
277 void sumo_pm_init_profile(struct radeon_device *rdev)
278 {
279 int idx;
280
281 /* default */
282 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
283 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
284 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
285 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
286
287 /* low,mid sh/mh */
288 if (rdev->flags & RADEON_IS_MOBILITY)
289 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
290 else
291 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
292
293 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
294 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
295 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
296 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
297
298 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
299 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
300 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
301 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
302
303 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
304 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
305 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
306 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
307
308 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
309 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
310 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
311 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
312
313 /* high sh/mh */
314 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
315 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
316 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
317 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
318 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx =
319 rdev->pm.power_state[idx].num_clock_modes - 1;
320
321 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
322 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
323 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
324 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx =
325 rdev->pm.power_state[idx].num_clock_modes - 1;
326 }
327
328 /**
329 * evergreen_pm_misc - set additional pm hw parameters callback.
330 *
331 * @rdev: radeon_device pointer
332 *
333 * Set non-clock parameters associated with a power state
334 * (voltage, etc.) (evergreen+).
335 */
336 void evergreen_pm_misc(struct radeon_device *rdev)
337 {
338 int req_ps_idx = rdev->pm.requested_power_state_index;
339 int req_cm_idx = rdev->pm.requested_clock_mode_index;
340 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
341 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
342
343 if (voltage->type == VOLTAGE_SW) {
344 /* 0xff01 is a flag rather then an actual voltage */
345 if (voltage->voltage == 0xff01)
346 return;
347 if (voltage->voltage && (voltage->voltage != rdev->pm.current_vddc)) {
348 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
349 rdev->pm.current_vddc = voltage->voltage;
350 DRM_DEBUG("Setting: vddc: %d\n", voltage->voltage);
351 }
352 /* 0xff01 is a flag rather then an actual voltage */
353 if (voltage->vddci == 0xff01)
354 return;
355 if (voltage->vddci && (voltage->vddci != rdev->pm.current_vddci)) {
356 radeon_atom_set_voltage(rdev, voltage->vddci, SET_VOLTAGE_TYPE_ASIC_VDDCI);
357 rdev->pm.current_vddci = voltage->vddci;
358 DRM_DEBUG("Setting: vddci: %d\n", voltage->vddci);
359 }
360 }
361 }
362
363 /**
364 * evergreen_pm_prepare - pre-power state change callback.
365 *
366 * @rdev: radeon_device pointer
367 *
368 * Prepare for a power state change (evergreen+).
369 */
370 void evergreen_pm_prepare(struct radeon_device *rdev)
371 {
372 struct drm_device *ddev = rdev->ddev;
373 struct drm_crtc *crtc;
374 struct radeon_crtc *radeon_crtc;
375 u32 tmp;
376
377 /* disable any active CRTCs */
378 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
379 radeon_crtc = to_radeon_crtc(crtc);
380 if (radeon_crtc->enabled) {
381 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
382 tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
383 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
384 }
385 }
386 }
387
388 /**
389 * evergreen_pm_finish - post-power state change callback.
390 *
391 * @rdev: radeon_device pointer
392 *
393 * Clean up after a power state change (evergreen+).
394 */
395 void evergreen_pm_finish(struct radeon_device *rdev)
396 {
397 struct drm_device *ddev = rdev->ddev;
398 struct drm_crtc *crtc;
399 struct radeon_crtc *radeon_crtc;
400 u32 tmp;
401
402 /* enable any active CRTCs */
403 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
404 radeon_crtc = to_radeon_crtc(crtc);
405 if (radeon_crtc->enabled) {
406 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
407 tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
408 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
409 }
410 }
411 }
412
413 /**
414 * evergreen_hpd_sense - hpd sense callback.
415 *
416 * @rdev: radeon_device pointer
417 * @hpd: hpd (hotplug detect) pin
418 *
419 * Checks if a digital monitor is connected (evergreen+).
420 * Returns true if connected, false if not connected.
421 */
422 bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
423 {
424 bool connected = false;
425
426 switch (hpd) {
427 case RADEON_HPD_1:
428 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
429 connected = true;
430 break;
431 case RADEON_HPD_2:
432 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
433 connected = true;
434 break;
435 case RADEON_HPD_3:
436 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
437 connected = true;
438 break;
439 case RADEON_HPD_4:
440 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
441 connected = true;
442 break;
443 case RADEON_HPD_5:
444 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
445 connected = true;
446 break;
447 case RADEON_HPD_6:
448 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
449 connected = true;
450 break;
451 default:
452 break;
453 }
454
455 return connected;
456 }
457
458 /**
459 * evergreen_hpd_set_polarity - hpd set polarity callback.
460 *
461 * @rdev: radeon_device pointer
462 * @hpd: hpd (hotplug detect) pin
463 *
464 * Set the polarity of the hpd pin (evergreen+).
465 */
466 void evergreen_hpd_set_polarity(struct radeon_device *rdev,
467 enum radeon_hpd_id hpd)
468 {
469 u32 tmp;
470 bool connected = evergreen_hpd_sense(rdev, hpd);
471
472 switch (hpd) {
473 case RADEON_HPD_1:
474 tmp = RREG32(DC_HPD1_INT_CONTROL);
475 if (connected)
476 tmp &= ~DC_HPDx_INT_POLARITY;
477 else
478 tmp |= DC_HPDx_INT_POLARITY;
479 WREG32(DC_HPD1_INT_CONTROL, tmp);
480 break;
481 case RADEON_HPD_2:
482 tmp = RREG32(DC_HPD2_INT_CONTROL);
483 if (connected)
484 tmp &= ~DC_HPDx_INT_POLARITY;
485 else
486 tmp |= DC_HPDx_INT_POLARITY;
487 WREG32(DC_HPD2_INT_CONTROL, tmp);
488 break;
489 case RADEON_HPD_3:
490 tmp = RREG32(DC_HPD3_INT_CONTROL);
491 if (connected)
492 tmp &= ~DC_HPDx_INT_POLARITY;
493 else
494 tmp |= DC_HPDx_INT_POLARITY;
495 WREG32(DC_HPD3_INT_CONTROL, tmp);
496 break;
497 case RADEON_HPD_4:
498 tmp = RREG32(DC_HPD4_INT_CONTROL);
499 if (connected)
500 tmp &= ~DC_HPDx_INT_POLARITY;
501 else
502 tmp |= DC_HPDx_INT_POLARITY;
503 WREG32(DC_HPD4_INT_CONTROL, tmp);
504 break;
505 case RADEON_HPD_5:
506 tmp = RREG32(DC_HPD5_INT_CONTROL);
507 if (connected)
508 tmp &= ~DC_HPDx_INT_POLARITY;
509 else
510 tmp |= DC_HPDx_INT_POLARITY;
511 WREG32(DC_HPD5_INT_CONTROL, tmp);
512 break;
513 case RADEON_HPD_6:
514 tmp = RREG32(DC_HPD6_INT_CONTROL);
515 if (connected)
516 tmp &= ~DC_HPDx_INT_POLARITY;
517 else
518 tmp |= DC_HPDx_INT_POLARITY;
519 WREG32(DC_HPD6_INT_CONTROL, tmp);
520 break;
521 default:
522 break;
523 }
524 }
525
526 /**
527 * evergreen_hpd_init - hpd setup callback.
528 *
529 * @rdev: radeon_device pointer
530 *
531 * Setup the hpd pins used by the card (evergreen+).
532 * Enable the pin, set the polarity, and enable the hpd interrupts.
533 */
534 void evergreen_hpd_init(struct radeon_device *rdev)
535 {
536 struct drm_device *dev = rdev->ddev;
537 struct drm_connector *connector;
538 unsigned enabled = 0;
539 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) |
540 DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN;
541
542 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
543 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
544 switch (radeon_connector->hpd.hpd) {
545 case RADEON_HPD_1:
546 WREG32(DC_HPD1_CONTROL, tmp);
547 break;
548 case RADEON_HPD_2:
549 WREG32(DC_HPD2_CONTROL, tmp);
550 break;
551 case RADEON_HPD_3:
552 WREG32(DC_HPD3_CONTROL, tmp);
553 break;
554 case RADEON_HPD_4:
555 WREG32(DC_HPD4_CONTROL, tmp);
556 break;
557 case RADEON_HPD_5:
558 WREG32(DC_HPD5_CONTROL, tmp);
559 break;
560 case RADEON_HPD_6:
561 WREG32(DC_HPD6_CONTROL, tmp);
562 break;
563 default:
564 break;
565 }
566 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
567 enabled |= 1 << radeon_connector->hpd.hpd;
568 }
569 radeon_irq_kms_enable_hpd(rdev, enabled);
570 }
571
572 /**
573 * evergreen_hpd_fini - hpd tear down callback.
574 *
575 * @rdev: radeon_device pointer
576 *
577 * Tear down the hpd pins used by the card (evergreen+).
578 * Disable the hpd interrupts.
579 */
580 void evergreen_hpd_fini(struct radeon_device *rdev)
581 {
582 struct drm_device *dev = rdev->ddev;
583 struct drm_connector *connector;
584 unsigned disabled = 0;
585
586 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
587 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
588 switch (radeon_connector->hpd.hpd) {
589 case RADEON_HPD_1:
590 WREG32(DC_HPD1_CONTROL, 0);
591 break;
592 case RADEON_HPD_2:
593 WREG32(DC_HPD2_CONTROL, 0);
594 break;
595 case RADEON_HPD_3:
596 WREG32(DC_HPD3_CONTROL, 0);
597 break;
598 case RADEON_HPD_4:
599 WREG32(DC_HPD4_CONTROL, 0);
600 break;
601 case RADEON_HPD_5:
602 WREG32(DC_HPD5_CONTROL, 0);
603 break;
604 case RADEON_HPD_6:
605 WREG32(DC_HPD6_CONTROL, 0);
606 break;
607 default:
608 break;
609 }
610 disabled |= 1 << radeon_connector->hpd.hpd;
611 }
612 radeon_irq_kms_disable_hpd(rdev, disabled);
613 }
614
615 /* watermark setup */
616
617 static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev,
618 struct radeon_crtc *radeon_crtc,
619 struct drm_display_mode *mode,
620 struct drm_display_mode *other_mode)
621 {
622 u32 tmp;
623 /*
624 * Line Buffer Setup
625 * There are 3 line buffers, each one shared by 2 display controllers.
626 * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
627 * the display controllers. The paritioning is done via one of four
628 * preset allocations specified in bits 2:0:
629 * first display controller
630 * 0 - first half of lb (3840 * 2)
631 * 1 - first 3/4 of lb (5760 * 2)
632 * 2 - whole lb (7680 * 2), other crtc must be disabled
633 * 3 - first 1/4 of lb (1920 * 2)
634 * second display controller
635 * 4 - second half of lb (3840 * 2)
636 * 5 - second 3/4 of lb (5760 * 2)
637 * 6 - whole lb (7680 * 2), other crtc must be disabled
638 * 7 - last 1/4 of lb (1920 * 2)
639 */
640 /* this can get tricky if we have two large displays on a paired group
641 * of crtcs. Ideally for multiple large displays we'd assign them to
642 * non-linked crtcs for maximum line buffer allocation.
643 */
644 if (radeon_crtc->base.enabled && mode) {
645 if (other_mode)
646 tmp = 0; /* 1/2 */
647 else
648 tmp = 2; /* whole */
649 } else
650 tmp = 0;
651
652 /* second controller of the pair uses second half of the lb */
653 if (radeon_crtc->crtc_id % 2)
654 tmp += 4;
655 WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp);
656
657 if (radeon_crtc->base.enabled && mode) {
658 switch (tmp) {
659 case 0:
660 case 4:
661 default:
662 if (ASIC_IS_DCE5(rdev))
663 return 4096 * 2;
664 else
665 return 3840 * 2;
666 case 1:
667 case 5:
668 if (ASIC_IS_DCE5(rdev))
669 return 6144 * 2;
670 else
671 return 5760 * 2;
672 case 2:
673 case 6:
674 if (ASIC_IS_DCE5(rdev))
675 return 8192 * 2;
676 else
677 return 7680 * 2;
678 case 3:
679 case 7:
680 if (ASIC_IS_DCE5(rdev))
681 return 2048 * 2;
682 else
683 return 1920 * 2;
684 }
685 }
686
687 /* controller not enabled, so no lb used */
688 return 0;
689 }
690
691 u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev)
692 {
693 u32 tmp = RREG32(MC_SHARED_CHMAP);
694
695 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
696 case 0:
697 default:
698 return 1;
699 case 1:
700 return 2;
701 case 2:
702 return 4;
703 case 3:
704 return 8;
705 }
706 }
707
708 struct evergreen_wm_params {
709 u32 dram_channels; /* number of dram channels */
710 u32 yclk; /* bandwidth per dram data pin in kHz */
711 u32 sclk; /* engine clock in kHz */
712 u32 disp_clk; /* display clock in kHz */
713 u32 src_width; /* viewport width */
714 u32 active_time; /* active display time in ns */
715 u32 blank_time; /* blank time in ns */
716 bool interlaced; /* mode is interlaced */
717 fixed20_12 vsc; /* vertical scale ratio */
718 u32 num_heads; /* number of active crtcs */
719 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
720 u32 lb_size; /* line buffer allocated to pipe */
721 u32 vtaps; /* vertical scaler taps */
722 };
723
724 static u32 evergreen_dram_bandwidth(struct evergreen_wm_params *wm)
725 {
726 /* Calculate DRAM Bandwidth and the part allocated to display. */
727 fixed20_12 dram_efficiency; /* 0.7 */
728 fixed20_12 yclk, dram_channels, bandwidth;
729 fixed20_12 a;
730
731 a.full = dfixed_const(1000);
732 yclk.full = dfixed_const(wm->yclk);
733 yclk.full = dfixed_div(yclk, a);
734 dram_channels.full = dfixed_const(wm->dram_channels * 4);
735 a.full = dfixed_const(10);
736 dram_efficiency.full = dfixed_const(7);
737 dram_efficiency.full = dfixed_div(dram_efficiency, a);
738 bandwidth.full = dfixed_mul(dram_channels, yclk);
739 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
740
741 return dfixed_trunc(bandwidth);
742 }
743
744 static u32 evergreen_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
745 {
746 /* Calculate DRAM Bandwidth and the part allocated to display. */
747 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
748 fixed20_12 yclk, dram_channels, bandwidth;
749 fixed20_12 a;
750
751 a.full = dfixed_const(1000);
752 yclk.full = dfixed_const(wm->yclk);
753 yclk.full = dfixed_div(yclk, a);
754 dram_channels.full = dfixed_const(wm->dram_channels * 4);
755 a.full = dfixed_const(10);
756 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
757 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
758 bandwidth.full = dfixed_mul(dram_channels, yclk);
759 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
760
761 return dfixed_trunc(bandwidth);
762 }
763
764 static u32 evergreen_data_return_bandwidth(struct evergreen_wm_params *wm)
765 {
766 /* Calculate the display Data return Bandwidth */
767 fixed20_12 return_efficiency; /* 0.8 */
768 fixed20_12 sclk, bandwidth;
769 fixed20_12 a;
770
771 a.full = dfixed_const(1000);
772 sclk.full = dfixed_const(wm->sclk);
773 sclk.full = dfixed_div(sclk, a);
774 a.full = dfixed_const(10);
775 return_efficiency.full = dfixed_const(8);
776 return_efficiency.full = dfixed_div(return_efficiency, a);
777 a.full = dfixed_const(32);
778 bandwidth.full = dfixed_mul(a, sclk);
779 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
780
781 return dfixed_trunc(bandwidth);
782 }
783
784 static u32 evergreen_dmif_request_bandwidth(struct evergreen_wm_params *wm)
785 {
786 /* Calculate the DMIF Request Bandwidth */
787 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
788 fixed20_12 disp_clk, bandwidth;
789 fixed20_12 a;
790
791 a.full = dfixed_const(1000);
792 disp_clk.full = dfixed_const(wm->disp_clk);
793 disp_clk.full = dfixed_div(disp_clk, a);
794 a.full = dfixed_const(10);
795 disp_clk_request_efficiency.full = dfixed_const(8);
796 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
797 a.full = dfixed_const(32);
798 bandwidth.full = dfixed_mul(a, disp_clk);
799 bandwidth.full = dfixed_mul(bandwidth, disp_clk_request_efficiency);
800
801 return dfixed_trunc(bandwidth);
802 }
803
804 static u32 evergreen_available_bandwidth(struct evergreen_wm_params *wm)
805 {
806 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
807 u32 dram_bandwidth = evergreen_dram_bandwidth(wm);
808 u32 data_return_bandwidth = evergreen_data_return_bandwidth(wm);
809 u32 dmif_req_bandwidth = evergreen_dmif_request_bandwidth(wm);
810
811 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
812 }
813
814 static u32 evergreen_average_bandwidth(struct evergreen_wm_params *wm)
815 {
816 /* Calculate the display mode Average Bandwidth
817 * DisplayMode should contain the source and destination dimensions,
818 * timing, etc.
819 */
820 fixed20_12 bpp;
821 fixed20_12 line_time;
822 fixed20_12 src_width;
823 fixed20_12 bandwidth;
824 fixed20_12 a;
825
826 a.full = dfixed_const(1000);
827 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
828 line_time.full = dfixed_div(line_time, a);
829 bpp.full = dfixed_const(wm->bytes_per_pixel);
830 src_width.full = dfixed_const(wm->src_width);
831 bandwidth.full = dfixed_mul(src_width, bpp);
832 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
833 bandwidth.full = dfixed_div(bandwidth, line_time);
834
835 return dfixed_trunc(bandwidth);
836 }
837
838 static u32 evergreen_latency_watermark(struct evergreen_wm_params *wm)
839 {
840 /* First calcualte the latency in ns */
841 u32 mc_latency = 2000; /* 2000 ns. */
842 u32 available_bandwidth = evergreen_available_bandwidth(wm);
843 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
844 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
845 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
846 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
847 (wm->num_heads * cursor_line_pair_return_time);
848 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
849 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
850 fixed20_12 a, b, c;
851
852 if (wm->num_heads == 0)
853 return 0;
854
855 a.full = dfixed_const(2);
856 b.full = dfixed_const(1);
857 if ((wm->vsc.full > a.full) ||
858 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
859 (wm->vtaps >= 5) ||
860 ((wm->vsc.full >= a.full) && wm->interlaced))
861 max_src_lines_per_dst_line = 4;
862 else
863 max_src_lines_per_dst_line = 2;
864
865 a.full = dfixed_const(available_bandwidth);
866 b.full = dfixed_const(wm->num_heads);
867 a.full = dfixed_div(a, b);
868
869 b.full = dfixed_const(1000);
870 c.full = dfixed_const(wm->disp_clk);
871 b.full = dfixed_div(c, b);
872 c.full = dfixed_const(wm->bytes_per_pixel);
873 b.full = dfixed_mul(b, c);
874
875 lb_fill_bw = min(dfixed_trunc(a), dfixed_trunc(b));
876
877 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
878 b.full = dfixed_const(1000);
879 c.full = dfixed_const(lb_fill_bw);
880 b.full = dfixed_div(c, b);
881 a.full = dfixed_div(a, b);
882 line_fill_time = dfixed_trunc(a);
883
884 if (line_fill_time < wm->active_time)
885 return latency;
886 else
887 return latency + (line_fill_time - wm->active_time);
888
889 }
890
891 static bool evergreen_average_bandwidth_vs_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
892 {
893 if (evergreen_average_bandwidth(wm) <=
894 (evergreen_dram_bandwidth_for_display(wm) / wm->num_heads))
895 return true;
896 else
897 return false;
898 };
899
900 static bool evergreen_average_bandwidth_vs_available_bandwidth(struct evergreen_wm_params *wm)
901 {
902 if (evergreen_average_bandwidth(wm) <=
903 (evergreen_available_bandwidth(wm) / wm->num_heads))
904 return true;
905 else
906 return false;
907 };
908
909 static bool evergreen_check_latency_hiding(struct evergreen_wm_params *wm)
910 {
911 u32 lb_partitions = wm->lb_size / wm->src_width;
912 u32 line_time = wm->active_time + wm->blank_time;
913 u32 latency_tolerant_lines;
914 u32 latency_hiding;
915 fixed20_12 a;
916
917 a.full = dfixed_const(1);
918 if (wm->vsc.full > a.full)
919 latency_tolerant_lines = 1;
920 else {
921 if (lb_partitions <= (wm->vtaps + 1))
922 latency_tolerant_lines = 1;
923 else
924 latency_tolerant_lines = 2;
925 }
926
927 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
928
929 if (evergreen_latency_watermark(wm) <= latency_hiding)
930 return true;
931 else
932 return false;
933 }
934
935 static void evergreen_program_watermarks(struct radeon_device *rdev,
936 struct radeon_crtc *radeon_crtc,
937 u32 lb_size, u32 num_heads)
938 {
939 struct drm_display_mode *mode = &radeon_crtc->base.mode;
940 struct evergreen_wm_params wm;
941 u32 pixel_period;
942 u32 line_time = 0;
943 u32 latency_watermark_a = 0, latency_watermark_b = 0;
944 u32 priority_a_mark = 0, priority_b_mark = 0;
945 u32 priority_a_cnt = PRIORITY_OFF;
946 u32 priority_b_cnt = PRIORITY_OFF;
947 u32 pipe_offset = radeon_crtc->crtc_id * 16;
948 u32 tmp, arb_control3;
949 fixed20_12 a, b, c;
950
951 if (radeon_crtc->base.enabled && num_heads && mode) {
952 pixel_period = 1000000 / (u32)mode->clock;
953 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
954 priority_a_cnt = 0;
955 priority_b_cnt = 0;
956
957 wm.yclk = rdev->pm.current_mclk * 10;
958 wm.sclk = rdev->pm.current_sclk * 10;
959 wm.disp_clk = mode->clock;
960 wm.src_width = mode->crtc_hdisplay;
961 wm.active_time = mode->crtc_hdisplay * pixel_period;
962 wm.blank_time = line_time - wm.active_time;
963 wm.interlaced = false;
964 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
965 wm.interlaced = true;
966 wm.vsc = radeon_crtc->vsc;
967 wm.vtaps = 1;
968 if (radeon_crtc->rmx_type != RMX_OFF)
969 wm.vtaps = 2;
970 wm.bytes_per_pixel = 4; /* XXX: get this from fb config */
971 wm.lb_size = lb_size;
972 wm.dram_channels = evergreen_get_number_of_dram_channels(rdev);
973 wm.num_heads = num_heads;
974
975 /* set for high clocks */
976 latency_watermark_a = min(evergreen_latency_watermark(&wm), (u32)65535);
977 /* set for low clocks */
978 /* wm.yclk = low clk; wm.sclk = low clk */
979 latency_watermark_b = min(evergreen_latency_watermark(&wm), (u32)65535);
980
981 /* possibly force display priority to high */
982 /* should really do this at mode validation time... */
983 if (!evergreen_average_bandwidth_vs_dram_bandwidth_for_display(&wm) ||
984 !evergreen_average_bandwidth_vs_available_bandwidth(&wm) ||
985 !evergreen_check_latency_hiding(&wm) ||
986 (rdev->disp_priority == 2)) {
987 DRM_DEBUG_KMS("force priority to high\n");
988 priority_a_cnt |= PRIORITY_ALWAYS_ON;
989 priority_b_cnt |= PRIORITY_ALWAYS_ON;
990 }
991
992 a.full = dfixed_const(1000);
993 b.full = dfixed_const(mode->clock);
994 b.full = dfixed_div(b, a);
995 c.full = dfixed_const(latency_watermark_a);
996 c.full = dfixed_mul(c, b);
997 c.full = dfixed_mul(c, radeon_crtc->hsc);
998 c.full = dfixed_div(c, a);
999 a.full = dfixed_const(16);
1000 c.full = dfixed_div(c, a);
1001 priority_a_mark = dfixed_trunc(c);
1002 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
1003
1004 a.full = dfixed_const(1000);
1005 b.full = dfixed_const(mode->clock);
1006 b.full = dfixed_div(b, a);
1007 c.full = dfixed_const(latency_watermark_b);
1008 c.full = dfixed_mul(c, b);
1009 c.full = dfixed_mul(c, radeon_crtc->hsc);
1010 c.full = dfixed_div(c, a);
1011 a.full = dfixed_const(16);
1012 c.full = dfixed_div(c, a);
1013 priority_b_mark = dfixed_trunc(c);
1014 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
1015 }
1016
1017 /* select wm A */
1018 arb_control3 = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
1019 tmp = arb_control3;
1020 tmp &= ~LATENCY_WATERMARK_MASK(3);
1021 tmp |= LATENCY_WATERMARK_MASK(1);
1022 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
1023 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
1024 (LATENCY_LOW_WATERMARK(latency_watermark_a) |
1025 LATENCY_HIGH_WATERMARK(line_time)));
1026 /* select wm B */
1027 tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
1028 tmp &= ~LATENCY_WATERMARK_MASK(3);
1029 tmp |= LATENCY_WATERMARK_MASK(2);
1030 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
1031 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
1032 (LATENCY_LOW_WATERMARK(latency_watermark_b) |
1033 LATENCY_HIGH_WATERMARK(line_time)));
1034 /* restore original selection */
1035 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, arb_control3);
1036
1037 /* write the priority marks */
1038 WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
1039 WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
1040
1041 }
1042
1043 /**
1044 * evergreen_bandwidth_update - update display watermarks callback.
1045 *
1046 * @rdev: radeon_device pointer
1047 *
1048 * Update the display watermarks based on the requested mode(s)
1049 * (evergreen+).
1050 */
1051 void evergreen_bandwidth_update(struct radeon_device *rdev)
1052 {
1053 struct drm_display_mode *mode0 = NULL;
1054 struct drm_display_mode *mode1 = NULL;
1055 u32 num_heads = 0, lb_size;
1056 int i;
1057
1058 radeon_update_display_priority(rdev);
1059
1060 for (i = 0; i < rdev->num_crtc; i++) {
1061 if (rdev->mode_info.crtcs[i]->base.enabled)
1062 num_heads++;
1063 }
1064 for (i = 0; i < rdev->num_crtc; i += 2) {
1065 mode0 = &rdev->mode_info.crtcs[i]->base.mode;
1066 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;
1067 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);
1068 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
1069 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);
1070 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads);
1071 }
1072 }
1073
1074 /**
1075 * evergreen_mc_wait_for_idle - wait for MC idle callback.
1076 *
1077 * @rdev: radeon_device pointer
1078 *
1079 * Wait for the MC (memory controller) to be idle.
1080 * (evergreen+).
1081 * Returns 0 if the MC is idle, -1 if not.
1082 */
1083 int evergreen_mc_wait_for_idle(struct radeon_device *rdev)
1084 {
1085 unsigned i;
1086 u32 tmp;
1087
1088 for (i = 0; i < rdev->usec_timeout; i++) {
1089 /* read MC_STATUS */
1090 tmp = RREG32(SRBM_STATUS) & 0x1F00;
1091 if (!tmp)
1092 return 0;
1093 udelay(1);
1094 }
1095 return -1;
1096 }
1097
1098 /*
1099 * GART
1100 */
1101 void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev)
1102 {
1103 unsigned i;
1104 u32 tmp;
1105
1106 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
1107
1108 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
1109 for (i = 0; i < rdev->usec_timeout; i++) {
1110 /* read MC_STATUS */
1111 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
1112 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
1113 if (tmp == 2) {
1114 printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
1115 return;
1116 }
1117 if (tmp) {
1118 return;
1119 }
1120 udelay(1);
1121 }
1122 }
1123
1124 int evergreen_pcie_gart_enable(struct radeon_device *rdev)
1125 {
1126 u32 tmp;
1127 int r;
1128
1129 if (rdev->gart.robj == NULL) {
1130 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
1131 return -EINVAL;
1132 }
1133 r = radeon_gart_table_vram_pin(rdev);
1134 if (r)
1135 return r;
1136 radeon_gart_restore(rdev);
1137 /* Setup L2 cache */
1138 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1139 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1140 EFFECTIVE_L2_QUEUE_SIZE(7));
1141 WREG32(VM_L2_CNTL2, 0);
1142 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1143 /* Setup TLB control */
1144 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1145 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1146 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
1147 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1148 if (rdev->flags & RADEON_IS_IGP) {
1149 WREG32(FUS_MC_VM_MD_L1_TLB0_CNTL, tmp);
1150 WREG32(FUS_MC_VM_MD_L1_TLB1_CNTL, tmp);
1151 WREG32(FUS_MC_VM_MD_L1_TLB2_CNTL, tmp);
1152 } else {
1153 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1154 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1155 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1156 if ((rdev->family == CHIP_JUNIPER) ||
1157 (rdev->family == CHIP_CYPRESS) ||
1158 (rdev->family == CHIP_HEMLOCK) ||
1159 (rdev->family == CHIP_BARTS))
1160 WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp);
1161 }
1162 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1163 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1164 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1165 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
1166 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1167 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
1168 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
1169 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
1170 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
1171 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
1172 (u32)(rdev->dummy_page.addr >> 12));
1173 WREG32(VM_CONTEXT1_CNTL, 0);
1174
1175 evergreen_pcie_gart_tlb_flush(rdev);
1176 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1177 (unsigned)(rdev->mc.gtt_size >> 20),
1178 (unsigned long long)rdev->gart.table_addr);
1179 rdev->gart.ready = true;
1180 return 0;
1181 }
1182
1183 void evergreen_pcie_gart_disable(struct radeon_device *rdev)
1184 {
1185 u32 tmp;
1186
1187 /* Disable all tables */
1188 WREG32(VM_CONTEXT0_CNTL, 0);
1189 WREG32(VM_CONTEXT1_CNTL, 0);
1190
1191 /* Setup L2 cache */
1192 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
1193 EFFECTIVE_L2_QUEUE_SIZE(7));
1194 WREG32(VM_L2_CNTL2, 0);
1195 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1196 /* Setup TLB control */
1197 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1198 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1199 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1200 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1201 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1202 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1203 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1204 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
1205 radeon_gart_table_vram_unpin(rdev);
1206 }
1207
1208 void evergreen_pcie_gart_fini(struct radeon_device *rdev)
1209 {
1210 evergreen_pcie_gart_disable(rdev);
1211 radeon_gart_table_vram_free(rdev);
1212 radeon_gart_fini(rdev);
1213 }
1214
1215
1216 void evergreen_agp_enable(struct radeon_device *rdev)
1217 {
1218 u32 tmp;
1219
1220 /* Setup L2 cache */
1221 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1222 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1223 EFFECTIVE_L2_QUEUE_SIZE(7));
1224 WREG32(VM_L2_CNTL2, 0);
1225 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1226 /* Setup TLB control */
1227 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1228 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1229 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
1230 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1231 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1232 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1233 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1234 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1235 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1236 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1237 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
1238 WREG32(VM_CONTEXT0_CNTL, 0);
1239 WREG32(VM_CONTEXT1_CNTL, 0);
1240 }
1241
1242 void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)
1243 {
1244 save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
1245 save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
1246
1247 /* Stop all video */
1248 WREG32(VGA_RENDER_CONTROL, 0);
1249 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
1250 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
1251 if (rdev->num_crtc >= 4) {
1252 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
1253 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
1254 }
1255 if (rdev->num_crtc >= 6) {
1256 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
1257 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
1258 }
1259 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1260 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1261 if (rdev->num_crtc >= 4) {
1262 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1263 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1264 }
1265 if (rdev->num_crtc >= 6) {
1266 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1267 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1268 }
1269 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1270 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1271 if (rdev->num_crtc >= 4) {
1272 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1273 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1274 }
1275 if (rdev->num_crtc >= 6) {
1276 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1277 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1278 }
1279
1280 WREG32(D1VGA_CONTROL, 0);
1281 WREG32(D2VGA_CONTROL, 0);
1282 if (rdev->num_crtc >= 4) {
1283 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
1284 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
1285 }
1286 if (rdev->num_crtc >= 6) {
1287 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
1288 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1289 }
1290 }
1291
1292 void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
1293 {
1294 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
1295 upper_32_bits(rdev->mc.vram_start));
1296 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
1297 upper_32_bits(rdev->mc.vram_start));
1298 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
1299 (u32)rdev->mc.vram_start);
1300 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
1301 (u32)rdev->mc.vram_start);
1302
1303 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
1304 upper_32_bits(rdev->mc.vram_start));
1305 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
1306 upper_32_bits(rdev->mc.vram_start));
1307 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
1308 (u32)rdev->mc.vram_start);
1309 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
1310 (u32)rdev->mc.vram_start);
1311
1312 if (rdev->num_crtc >= 4) {
1313 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
1314 upper_32_bits(rdev->mc.vram_start));
1315 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
1316 upper_32_bits(rdev->mc.vram_start));
1317 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
1318 (u32)rdev->mc.vram_start);
1319 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
1320 (u32)rdev->mc.vram_start);
1321
1322 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
1323 upper_32_bits(rdev->mc.vram_start));
1324 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
1325 upper_32_bits(rdev->mc.vram_start));
1326 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
1327 (u32)rdev->mc.vram_start);
1328 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
1329 (u32)rdev->mc.vram_start);
1330 }
1331 if (rdev->num_crtc >= 6) {
1332 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
1333 upper_32_bits(rdev->mc.vram_start));
1334 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
1335 upper_32_bits(rdev->mc.vram_start));
1336 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
1337 (u32)rdev->mc.vram_start);
1338 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
1339 (u32)rdev->mc.vram_start);
1340
1341 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
1342 upper_32_bits(rdev->mc.vram_start));
1343 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
1344 upper_32_bits(rdev->mc.vram_start));
1345 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
1346 (u32)rdev->mc.vram_start);
1347 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
1348 (u32)rdev->mc.vram_start);
1349 }
1350
1351 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
1352 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
1353 /* Unlock host access */
1354 WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
1355 mdelay(1);
1356 WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
1357 }
1358
1359 void evergreen_mc_program(struct radeon_device *rdev)
1360 {
1361 struct evergreen_mc_save save;
1362 u32 tmp;
1363 int i, j;
1364
1365 /* Initialize HDP */
1366 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1367 WREG32((0x2c14 + j), 0x00000000);
1368 WREG32((0x2c18 + j), 0x00000000);
1369 WREG32((0x2c1c + j), 0x00000000);
1370 WREG32((0x2c20 + j), 0x00000000);
1371 WREG32((0x2c24 + j), 0x00000000);
1372 }
1373 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1374
1375 evergreen_mc_stop(rdev, &save);
1376 if (evergreen_mc_wait_for_idle(rdev)) {
1377 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1378 }
1379 /* Lockout access through VGA aperture*/
1380 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1381 /* Update configuration */
1382 if (rdev->flags & RADEON_IS_AGP) {
1383 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1384 /* VRAM before AGP */
1385 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1386 rdev->mc.vram_start >> 12);
1387 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1388 rdev->mc.gtt_end >> 12);
1389 } else {
1390 /* VRAM after AGP */
1391 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1392 rdev->mc.gtt_start >> 12);
1393 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1394 rdev->mc.vram_end >> 12);
1395 }
1396 } else {
1397 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1398 rdev->mc.vram_start >> 12);
1399 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1400 rdev->mc.vram_end >> 12);
1401 }
1402 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
1403 /* llano/ontario only */
1404 if ((rdev->family == CHIP_PALM) ||
1405 (rdev->family == CHIP_SUMO) ||
1406 (rdev->family == CHIP_SUMO2)) {
1407 tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF;
1408 tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24;
1409 tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20;
1410 WREG32(MC_FUS_VM_FB_OFFSET, tmp);
1411 }
1412 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1413 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1414 WREG32(MC_VM_FB_LOCATION, tmp);
1415 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1416 WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
1417 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1418 if (rdev->flags & RADEON_IS_AGP) {
1419 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
1420 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
1421 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1422 } else {
1423 WREG32(MC_VM_AGP_BASE, 0);
1424 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1425 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1426 }
1427 if (evergreen_mc_wait_for_idle(rdev)) {
1428 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1429 }
1430 evergreen_mc_resume(rdev, &save);
1431 /* we need to own VRAM, so turn off the VGA renderer here
1432 * to stop it overwriting our objects */
1433 rv515_vga_render_disable(rdev);
1434 }
1435
1436 /*
1437 * CP.
1438 */
1439 void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1440 {
1441 struct radeon_ring *ring = &rdev->ring[ib->ring];
1442 u32 next_rptr;
1443
1444 /* set to DX10/11 mode */
1445 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));
1446 radeon_ring_write(ring, 1);
1447
1448 if (ring->rptr_save_reg) {
1449 next_rptr = ring->wptr + 3 + 4;
1450 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1451 radeon_ring_write(ring, ((ring->rptr_save_reg -
1452 PACKET3_SET_CONFIG_REG_START) >> 2));
1453 radeon_ring_write(ring, next_rptr);
1454 } else if (rdev->wb.enabled) {
1455 next_rptr = ring->wptr + 5 + 4;
1456 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3));
1457 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
1458 radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18));
1459 radeon_ring_write(ring, next_rptr);
1460 radeon_ring_write(ring, 0);
1461 }
1462
1463 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
1464 radeon_ring_write(ring,
1465 #ifdef __BIG_ENDIAN
1466 (2 << 0) |
1467 #endif
1468 (ib->gpu_addr & 0xFFFFFFFC));
1469 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
1470 radeon_ring_write(ring, ib->length_dw);
1471 }
1472
1473
1474 static int evergreen_cp_load_microcode(struct radeon_device *rdev)
1475 {
1476 const __be32 *fw_data;
1477 int i;
1478
1479 if (!rdev->me_fw || !rdev->pfp_fw)
1480 return -EINVAL;
1481
1482 r700_cp_stop(rdev);
1483 WREG32(CP_RB_CNTL,
1484 #ifdef __BIG_ENDIAN
1485 BUF_SWAP_32BIT |
1486 #endif
1487 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
1488
1489 fw_data = (const __be32 *)rdev->pfp_fw->data;
1490 WREG32(CP_PFP_UCODE_ADDR, 0);
1491 for (i = 0; i < EVERGREEN_PFP_UCODE_SIZE; i++)
1492 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1493 WREG32(CP_PFP_UCODE_ADDR, 0);
1494
1495 fw_data = (const __be32 *)rdev->me_fw->data;
1496 WREG32(CP_ME_RAM_WADDR, 0);
1497 for (i = 0; i < EVERGREEN_PM4_UCODE_SIZE; i++)
1498 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1499
1500 WREG32(CP_PFP_UCODE_ADDR, 0);
1501 WREG32(CP_ME_RAM_WADDR, 0);
1502 WREG32(CP_ME_RAM_RADDR, 0);
1503 return 0;
1504 }
1505
1506 static int evergreen_cp_start(struct radeon_device *rdev)
1507 {
1508 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1509 int r, i;
1510 uint32_t cp_me;
1511
1512 r = radeon_ring_lock(rdev, ring, 7);
1513 if (r) {
1514 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1515 return r;
1516 }
1517 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
1518 radeon_ring_write(ring, 0x1);
1519 radeon_ring_write(ring, 0x0);
1520 radeon_ring_write(ring, rdev->config.evergreen.max_hw_contexts - 1);
1521 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1522 radeon_ring_write(ring, 0);
1523 radeon_ring_write(ring, 0);
1524 radeon_ring_unlock_commit(rdev, ring);
1525
1526 cp_me = 0xff;
1527 WREG32(CP_ME_CNTL, cp_me);
1528
1529 r = radeon_ring_lock(rdev, ring, evergreen_default_size + 19);
1530 if (r) {
1531 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1532 return r;
1533 }
1534
1535 /* setup clear context state */
1536 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1537 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1538
1539 for (i = 0; i < evergreen_default_size; i++)
1540 radeon_ring_write(ring, evergreen_default_state[i]);
1541
1542 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1543 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
1544
1545 /* set clear context state */
1546 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
1547 radeon_ring_write(ring, 0);
1548
1549 /* SQ_VTX_BASE_VTX_LOC */
1550 radeon_ring_write(ring, 0xc0026f00);
1551 radeon_ring_write(ring, 0x00000000);
1552 radeon_ring_write(ring, 0x00000000);
1553 radeon_ring_write(ring, 0x00000000);
1554
1555 /* Clear consts */
1556 radeon_ring_write(ring, 0xc0036f00);
1557 radeon_ring_write(ring, 0x00000bc4);
1558 radeon_ring_write(ring, 0xffffffff);
1559 radeon_ring_write(ring, 0xffffffff);
1560 radeon_ring_write(ring, 0xffffffff);
1561
1562 radeon_ring_write(ring, 0xc0026900);
1563 radeon_ring_write(ring, 0x00000316);
1564 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1565 radeon_ring_write(ring, 0x00000010); /* */
1566
1567 radeon_ring_unlock_commit(rdev, ring);
1568
1569 return 0;
1570 }
1571
1572 int evergreen_cp_resume(struct radeon_device *rdev)
1573 {
1574 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1575 u32 tmp;
1576 u32 rb_bufsz;
1577 int r;
1578
1579 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1580 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1581 SOFT_RESET_PA |
1582 SOFT_RESET_SH |
1583 SOFT_RESET_VGT |
1584 SOFT_RESET_SPI |
1585 SOFT_RESET_SX));
1586 RREG32(GRBM_SOFT_RESET);
1587 mdelay(15);
1588 WREG32(GRBM_SOFT_RESET, 0);
1589 RREG32(GRBM_SOFT_RESET);
1590
1591 /* Set ring buffer size */
1592 rb_bufsz = drm_order(ring->ring_size / 8);
1593 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1594 #ifdef __BIG_ENDIAN
1595 tmp |= BUF_SWAP_32BIT;
1596 #endif
1597 WREG32(CP_RB_CNTL, tmp);
1598 WREG32(CP_SEM_WAIT_TIMER, 0x0);
1599 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
1600
1601 /* Set the write pointer delay */
1602 WREG32(CP_RB_WPTR_DELAY, 0);
1603
1604 /* Initialize the ring buffer's read and write pointers */
1605 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1606 WREG32(CP_RB_RPTR_WR, 0);
1607 ring->wptr = 0;
1608 WREG32(CP_RB_WPTR, ring->wptr);
1609
1610 /* set the wb address wether it's enabled or not */
1611 WREG32(CP_RB_RPTR_ADDR,
1612 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
1613 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
1614 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1615
1616 if (rdev->wb.enabled)
1617 WREG32(SCRATCH_UMSK, 0xff);
1618 else {
1619 tmp |= RB_NO_UPDATE;
1620 WREG32(SCRATCH_UMSK, 0);
1621 }
1622
1623 mdelay(1);
1624 WREG32(CP_RB_CNTL, tmp);
1625
1626 WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
1627 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1628
1629 ring->rptr = RREG32(CP_RB_RPTR);
1630
1631 evergreen_cp_start(rdev);
1632 ring->ready = true;
1633 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
1634 if (r) {
1635 ring->ready = false;
1636 return r;
1637 }
1638 return 0;
1639 }
1640
1641 /*
1642 * Core functions
1643 */
1644 static void evergreen_gpu_init(struct radeon_device *rdev)
1645 {
1646 u32 gb_addr_config;
1647 u32 mc_shared_chmap, mc_arb_ramcfg;
1648 u32 sx_debug_1;
1649 u32 smx_dc_ctl0;
1650 u32 sq_config;
1651 u32 sq_lds_resource_mgmt;
1652 u32 sq_gpr_resource_mgmt_1;
1653 u32 sq_gpr_resource_mgmt_2;
1654 u32 sq_gpr_resource_mgmt_3;
1655 u32 sq_thread_resource_mgmt;
1656 u32 sq_thread_resource_mgmt_2;
1657 u32 sq_stack_resource_mgmt_1;
1658 u32 sq_stack_resource_mgmt_2;
1659 u32 sq_stack_resource_mgmt_3;
1660 u32 vgt_cache_invalidation;
1661 u32 hdp_host_path_cntl, tmp;
1662 u32 disabled_rb_mask;
1663 int i, j, num_shader_engines, ps_thread_count;
1664
1665 switch (rdev->family) {
1666 case CHIP_CYPRESS:
1667 case CHIP_HEMLOCK:
1668 rdev->config.evergreen.num_ses = 2;
1669 rdev->config.evergreen.max_pipes = 4;
1670 rdev->config.evergreen.max_tile_pipes = 8;
1671 rdev->config.evergreen.max_simds = 10;
1672 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1673 rdev->config.evergreen.max_gprs = 256;
1674 rdev->config.evergreen.max_threads = 248;
1675 rdev->config.evergreen.max_gs_threads = 32;
1676 rdev->config.evergreen.max_stack_entries = 512;
1677 rdev->config.evergreen.sx_num_of_sets = 4;
1678 rdev->config.evergreen.sx_max_export_size = 256;
1679 rdev->config.evergreen.sx_max_export_pos_size = 64;
1680 rdev->config.evergreen.sx_max_export_smx_size = 192;
1681 rdev->config.evergreen.max_hw_contexts = 8;
1682 rdev->config.evergreen.sq_num_cf_insts = 2;
1683
1684 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1685 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1686 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1687 gb_addr_config = CYPRESS_GB_ADDR_CONFIG_GOLDEN;
1688 break;
1689 case CHIP_JUNIPER:
1690 rdev->config.evergreen.num_ses = 1;
1691 rdev->config.evergreen.max_pipes = 4;
1692 rdev->config.evergreen.max_tile_pipes = 4;
1693 rdev->config.evergreen.max_simds = 10;
1694 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1695 rdev->config.evergreen.max_gprs = 256;
1696 rdev->config.evergreen.max_threads = 248;
1697 rdev->config.evergreen.max_gs_threads = 32;
1698 rdev->config.evergreen.max_stack_entries = 512;
1699 rdev->config.evergreen.sx_num_of_sets = 4;
1700 rdev->config.evergreen.sx_max_export_size = 256;
1701 rdev->config.evergreen.sx_max_export_pos_size = 64;
1702 rdev->config.evergreen.sx_max_export_smx_size = 192;
1703 rdev->config.evergreen.max_hw_contexts = 8;
1704 rdev->config.evergreen.sq_num_cf_insts = 2;
1705
1706 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1707 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1708 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1709 gb_addr_config = JUNIPER_GB_ADDR_CONFIG_GOLDEN;
1710 break;
1711 case CHIP_REDWOOD:
1712 rdev->config.evergreen.num_ses = 1;
1713 rdev->config.evergreen.max_pipes = 4;
1714 rdev->config.evergreen.max_tile_pipes = 4;
1715 rdev->config.evergreen.max_simds = 5;
1716 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1717 rdev->config.evergreen.max_gprs = 256;
1718 rdev->config.evergreen.max_threads = 248;
1719 rdev->config.evergreen.max_gs_threads = 32;
1720 rdev->config.evergreen.max_stack_entries = 256;
1721 rdev->config.evergreen.sx_num_of_sets = 4;
1722 rdev->config.evergreen.sx_max_export_size = 256;
1723 rdev->config.evergreen.sx_max_export_pos_size = 64;
1724 rdev->config.evergreen.sx_max_export_smx_size = 192;
1725 rdev->config.evergreen.max_hw_contexts = 8;
1726 rdev->config.evergreen.sq_num_cf_insts = 2;
1727
1728 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1729 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1730 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1731 gb_addr_config = REDWOOD_GB_ADDR_CONFIG_GOLDEN;
1732 break;
1733 case CHIP_CEDAR:
1734 default:
1735 rdev->config.evergreen.num_ses = 1;
1736 rdev->config.evergreen.max_pipes = 2;
1737 rdev->config.evergreen.max_tile_pipes = 2;
1738 rdev->config.evergreen.max_simds = 2;
1739 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1740 rdev->config.evergreen.max_gprs = 256;
1741 rdev->config.evergreen.max_threads = 192;
1742 rdev->config.evergreen.max_gs_threads = 16;
1743 rdev->config.evergreen.max_stack_entries = 256;
1744 rdev->config.evergreen.sx_num_of_sets = 4;
1745 rdev->config.evergreen.sx_max_export_size = 128;
1746 rdev->config.evergreen.sx_max_export_pos_size = 32;
1747 rdev->config.evergreen.sx_max_export_smx_size = 96;
1748 rdev->config.evergreen.max_hw_contexts = 4;
1749 rdev->config.evergreen.sq_num_cf_insts = 1;
1750
1751 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1752 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1753 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1754 gb_addr_config = CEDAR_GB_ADDR_CONFIG_GOLDEN;
1755 break;
1756 case CHIP_PALM:
1757 rdev->config.evergreen.num_ses = 1;
1758 rdev->config.evergreen.max_pipes = 2;
1759 rdev->config.evergreen.max_tile_pipes = 2;
1760 rdev->config.evergreen.max_simds = 2;
1761 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1762 rdev->config.evergreen.max_gprs = 256;
1763 rdev->config.evergreen.max_threads = 192;
1764 rdev->config.evergreen.max_gs_threads = 16;
1765 rdev->config.evergreen.max_stack_entries = 256;
1766 rdev->config.evergreen.sx_num_of_sets = 4;
1767 rdev->config.evergreen.sx_max_export_size = 128;
1768 rdev->config.evergreen.sx_max_export_pos_size = 32;
1769 rdev->config.evergreen.sx_max_export_smx_size = 96;
1770 rdev->config.evergreen.max_hw_contexts = 4;
1771 rdev->config.evergreen.sq_num_cf_insts = 1;
1772
1773 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1774 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1775 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1776 gb_addr_config = CEDAR_GB_ADDR_CONFIG_GOLDEN;
1777 break;
1778 case CHIP_SUMO:
1779 rdev->config.evergreen.num_ses = 1;
1780 rdev->config.evergreen.max_pipes = 4;
1781 rdev->config.evergreen.max_tile_pipes = 2;
1782 if (rdev->pdev->device == 0x9648)
1783 rdev->config.evergreen.max_simds = 3;
1784 else if ((rdev->pdev->device == 0x9647) ||
1785 (rdev->pdev->device == 0x964a))
1786 rdev->config.evergreen.max_simds = 4;
1787 else
1788 rdev->config.evergreen.max_simds = 5;
1789 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1790 rdev->config.evergreen.max_gprs = 256;
1791 rdev->config.evergreen.max_threads = 248;
1792 rdev->config.evergreen.max_gs_threads = 32;
1793 rdev->config.evergreen.max_stack_entries = 256;
1794 rdev->config.evergreen.sx_num_of_sets = 4;
1795 rdev->config.evergreen.sx_max_export_size = 256;
1796 rdev->config.evergreen.sx_max_export_pos_size = 64;
1797 rdev->config.evergreen.sx_max_export_smx_size = 192;
1798 rdev->config.evergreen.max_hw_contexts = 8;
1799 rdev->config.evergreen.sq_num_cf_insts = 2;
1800
1801 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1802 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1803 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1804 gb_addr_config = REDWOOD_GB_ADDR_CONFIG_GOLDEN;
1805 break;
1806 case CHIP_SUMO2:
1807 rdev->config.evergreen.num_ses = 1;
1808 rdev->config.evergreen.max_pipes = 4;
1809 rdev->config.evergreen.max_tile_pipes = 4;
1810 rdev->config.evergreen.max_simds = 2;
1811 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1812 rdev->config.evergreen.max_gprs = 256;
1813 rdev->config.evergreen.max_threads = 248;
1814 rdev->config.evergreen.max_gs_threads = 32;
1815 rdev->config.evergreen.max_stack_entries = 512;
1816 rdev->config.evergreen.sx_num_of_sets = 4;
1817 rdev->config.evergreen.sx_max_export_size = 256;
1818 rdev->config.evergreen.sx_max_export_pos_size = 64;
1819 rdev->config.evergreen.sx_max_export_smx_size = 192;
1820 rdev->config.evergreen.max_hw_contexts = 8;
1821 rdev->config.evergreen.sq_num_cf_insts = 2;
1822
1823 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1824 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1825 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1826 gb_addr_config = REDWOOD_GB_ADDR_CONFIG_GOLDEN;
1827 break;
1828 case CHIP_BARTS:
1829 rdev->config.evergreen.num_ses = 2;
1830 rdev->config.evergreen.max_pipes = 4;
1831 rdev->config.evergreen.max_tile_pipes = 8;
1832 rdev->config.evergreen.max_simds = 7;
1833 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1834 rdev->config.evergreen.max_gprs = 256;
1835 rdev->config.evergreen.max_threads = 248;
1836 rdev->config.evergreen.max_gs_threads = 32;
1837 rdev->config.evergreen.max_stack_entries = 512;
1838 rdev->config.evergreen.sx_num_of_sets = 4;
1839 rdev->config.evergreen.sx_max_export_size = 256;
1840 rdev->config.evergreen.sx_max_export_pos_size = 64;
1841 rdev->config.evergreen.sx_max_export_smx_size = 192;
1842 rdev->config.evergreen.max_hw_contexts = 8;
1843 rdev->config.evergreen.sq_num_cf_insts = 2;
1844
1845 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1846 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1847 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1848 gb_addr_config = BARTS_GB_ADDR_CONFIG_GOLDEN;
1849 break;
1850 case CHIP_TURKS:
1851 rdev->config.evergreen.num_ses = 1;
1852 rdev->config.evergreen.max_pipes = 4;
1853 rdev->config.evergreen.max_tile_pipes = 4;
1854 rdev->config.evergreen.max_simds = 6;
1855 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1856 rdev->config.evergreen.max_gprs = 256;
1857 rdev->config.evergreen.max_threads = 248;
1858 rdev->config.evergreen.max_gs_threads = 32;
1859 rdev->config.evergreen.max_stack_entries = 256;
1860 rdev->config.evergreen.sx_num_of_sets = 4;
1861 rdev->config.evergreen.sx_max_export_size = 256;
1862 rdev->config.evergreen.sx_max_export_pos_size = 64;
1863 rdev->config.evergreen.sx_max_export_smx_size = 192;
1864 rdev->config.evergreen.max_hw_contexts = 8;
1865 rdev->config.evergreen.sq_num_cf_insts = 2;
1866
1867 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1868 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1869 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1870 gb_addr_config = TURKS_GB_ADDR_CONFIG_GOLDEN;
1871 break;
1872 case CHIP_CAICOS:
1873 rdev->config.evergreen.num_ses = 1;
1874 rdev->config.evergreen.max_pipes = 4;
1875 rdev->config.evergreen.max_tile_pipes = 2;
1876 rdev->config.evergreen.max_simds = 2;
1877 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1878 rdev->config.evergreen.max_gprs = 256;
1879 rdev->config.evergreen.max_threads = 192;
1880 rdev->config.evergreen.max_gs_threads = 16;
1881 rdev->config.evergreen.max_stack_entries = 256;
1882 rdev->config.evergreen.sx_num_of_sets = 4;
1883 rdev->config.evergreen.sx_max_export_size = 128;
1884 rdev->config.evergreen.sx_max_export_pos_size = 32;
1885 rdev->config.evergreen.sx_max_export_smx_size = 96;
1886 rdev->config.evergreen.max_hw_contexts = 4;
1887 rdev->config.evergreen.sq_num_cf_insts = 1;
1888
1889 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1890 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1891 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1892 gb_addr_config = CAICOS_GB_ADDR_CONFIG_GOLDEN;
1893 break;
1894 }
1895
1896 /* Initialize HDP */
1897 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1898 WREG32((0x2c14 + j), 0x00000000);
1899 WREG32((0x2c18 + j), 0x00000000);
1900 WREG32((0x2c1c + j), 0x00000000);
1901 WREG32((0x2c20 + j), 0x00000000);
1902 WREG32((0x2c24 + j), 0x00000000);
1903 }
1904
1905 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1906
1907 evergreen_fix_pci_max_read_req_size(rdev);
1908
1909 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
1910 if ((rdev->family == CHIP_PALM) ||
1911 (rdev->family == CHIP_SUMO) ||
1912 (rdev->family == CHIP_SUMO2))
1913 mc_arb_ramcfg = RREG32(FUS_MC_ARB_RAMCFG);
1914 else
1915 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
1916
1917 /* setup tiling info dword. gb_addr_config is not adequate since it does
1918 * not have bank info, so create a custom tiling dword.
1919 * bits 3:0 num_pipes
1920 * bits 7:4 num_banks
1921 * bits 11:8 group_size
1922 * bits 15:12 row_size
1923 */
1924 rdev->config.evergreen.tile_config = 0;
1925 switch (rdev->config.evergreen.max_tile_pipes) {
1926 case 1:
1927 default:
1928 rdev->config.evergreen.tile_config |= (0 << 0);
1929 break;
1930 case 2:
1931 rdev->config.evergreen.tile_config |= (1 << 0);
1932 break;
1933 case 4:
1934 rdev->config.evergreen.tile_config |= (2 << 0);
1935 break;
1936 case 8:
1937 rdev->config.evergreen.tile_config |= (3 << 0);
1938 break;
1939 }
1940 /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
1941 if (rdev->flags & RADEON_IS_IGP)
1942 rdev->config.evergreen.tile_config |= 1 << 4;
1943 else {
1944 switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
1945 case 0: /* four banks */
1946 rdev->config.evergreen.tile_config |= 0 << 4;
1947 break;
1948 case 1: /* eight banks */
1949 rdev->config.evergreen.tile_config |= 1 << 4;
1950 break;
1951 case 2: /* sixteen banks */
1952 default:
1953 rdev->config.evergreen.tile_config |= 2 << 4;
1954 break;
1955 }
1956 }
1957 rdev->config.evergreen.tile_config |= 0 << 8;
1958 rdev->config.evergreen.tile_config |=
1959 ((gb_addr_config & 0x30000000) >> 28) << 12;
1960
1961 num_shader_engines = (gb_addr_config & NUM_SHADER_ENGINES(3) >> 12) + 1;
1962
1963 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK)) {
1964 u32 efuse_straps_4;
1965 u32 efuse_straps_3;
1966
1967 WREG32(RCU_IND_INDEX, 0x204);
1968 efuse_straps_4 = RREG32(RCU_IND_DATA);
1969 WREG32(RCU_IND_INDEX, 0x203);
1970 efuse_straps_3 = RREG32(RCU_IND_DATA);
1971 tmp = (((efuse_straps_4 & 0xf) << 4) |
1972 ((efuse_straps_3 & 0xf0000000) >> 28));
1973 } else {
1974 tmp = 0;
1975 for (i = (rdev->config.evergreen.num_ses - 1); i >= 0; i--) {
1976 u32 rb_disable_bitmap;
1977
1978 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
1979 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
1980 rb_disable_bitmap = (RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000) >> 16;
1981 tmp <<= 4;
1982 tmp |= rb_disable_bitmap;
1983 }
1984 }
1985 /* enabled rb are just the one not disabled :) */
1986 disabled_rb_mask = tmp;
1987
1988 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
1989 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
1990
1991 WREG32(GB_ADDR_CONFIG, gb_addr_config);
1992 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
1993 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
1994
1995 tmp = gb_addr_config & NUM_PIPES_MASK;
1996 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.evergreen.max_backends,
1997 EVERGREEN_MAX_BACKENDS, disabled_rb_mask);
1998 WREG32(GB_BACKEND_MAP, tmp);
1999
2000 WREG32(CGTS_SYS_TCC_DISABLE, 0);
2001 WREG32(CGTS_TCC_DISABLE, 0);
2002 WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
2003 WREG32(CGTS_USER_TCC_DISABLE, 0);
2004
2005 /* set HW defaults for 3D engine */
2006 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
2007 ROQ_IB2_START(0x2b)));
2008
2009 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
2010
2011 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO |
2012 SYNC_GRADIENT |
2013 SYNC_WALKER |
2014 SYNC_ALIGNER));
2015
2016 sx_debug_1 = RREG32(SX_DEBUG_1);
2017 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
2018 WREG32(SX_DEBUG_1, sx_debug_1);
2019
2020
2021 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
2022 smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
2023 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);
2024 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
2025
2026 if (rdev->family <= CHIP_SUMO2)
2027 WREG32(SMX_SAR_CTL0, 0x00010000);
2028
2029 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |
2030 POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |
2031 SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));
2032
2033 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) |
2034 SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) |
2035 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size)));
2036
2037 WREG32(VGT_NUM_INSTANCES, 1);
2038 WREG32(SPI_CONFIG_CNTL, 0);
2039 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
2040 WREG32(CP_PERFMON_CNTL, 0);
2041
2042 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) |
2043 FETCH_FIFO_HIWATER(0x4) |
2044 DONE_FIFO_HIWATER(0xe0) |
2045 ALU_UPDATE_FIFO_HIWATER(0x8)));
2046
2047 sq_config = RREG32(SQ_CONFIG);
2048 sq_config &= ~(PS_PRIO(3) |
2049 VS_PRIO(3) |
2050 GS_PRIO(3) |
2051 ES_PRIO(3));
2052 sq_config |= (VC_ENABLE |
2053 EXPORT_SRC_C |
2054 PS_PRIO(0) |
2055 VS_PRIO(1) |
2056 GS_PRIO(2) |
2057 ES_PRIO(3));
2058
2059 switch (rdev->family) {
2060 case CHIP_CEDAR:
2061 case CHIP_PALM:
2062 case CHIP_SUMO:
2063 case CHIP_SUMO2:
2064 case CHIP_CAICOS:
2065 /* no vertex cache */
2066 sq_config &= ~VC_ENABLE;
2067 break;
2068 default:
2069 break;
2070 }
2071
2072 sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT);
2073
2074 sq_gpr_resource_mgmt_1 = NUM_PS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2))* 12 / 32);
2075 sq_gpr_resource_mgmt_1 |= NUM_VS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 6 / 32);
2076 sq_gpr_resource_mgmt_1 |= NUM_CLAUSE_TEMP_GPRS(4);
2077 sq_gpr_resource_mgmt_2 = NUM_GS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
2078 sq_gpr_resource_mgmt_2 |= NUM_ES_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
2079 sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
2080 sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
2081
2082 switch (rdev->family) {
2083 case CHIP_CEDAR:
2084 case CHIP_PALM:
2085 case CHIP_SUMO:
2086 case CHIP_SUMO2:
2087 ps_thread_count = 96;
2088 break;
2089 default:
2090 ps_thread_count = 128;
2091 break;
2092 }
2093
2094 sq_thread_resource_mgmt = NUM_PS_THREADS(ps_thread_count);
2095 sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2096 sq_thread_resource_mgmt |= NUM_GS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2097 sq_thread_resource_mgmt |= NUM_ES_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2098 sq_thread_resource_mgmt_2 = NUM_HS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2099 sq_thread_resource_mgmt_2 |= NUM_LS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2100
2101 sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2102 sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2103 sq_stack_resource_mgmt_2 = NUM_GS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2104 sq_stack_resource_mgmt_2 |= NUM_ES_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2105 sq_stack_resource_mgmt_3 = NUM_HS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2106 sq_stack_resource_mgmt_3 |= NUM_LS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2107
2108 WREG32(SQ_CONFIG, sq_config);
2109 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
2110 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
2111 WREG32(SQ_GPR_RESOURCE_MGMT_3, sq_gpr_resource_mgmt_3);
2112 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
2113 WREG32(SQ_THREAD_RESOURCE_MGMT_2, sq_thread_resource_mgmt_2);
2114 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
2115 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
2116 WREG32(SQ_STACK_RESOURCE_MGMT_3, sq_stack_resource_mgmt_3);
2117 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2118 WREG32(SQ_LDS_RESOURCE_MGMT, sq_lds_resource_mgmt);
2119
2120 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
2121 FORCE_EOV_MAX_REZ_CNT(255)));
2122
2123 switch (rdev->family) {
2124 case CHIP_CEDAR:
2125 case CHIP_PALM:
2126 case CHIP_SUMO:
2127 case CHIP_SUMO2:
2128 case CHIP_CAICOS:
2129 vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY);
2130 break;
2131 default:
2132 vgt_cache_invalidation = CACHE_INVALIDATION(VC_AND_TC);
2133 break;
2134 }
2135 vgt_cache_invalidation |= AUTO_INVLD_EN(ES_AND_GS_AUTO);
2136 WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation);
2137
2138 WREG32(VGT_GS_VERTEX_REUSE, 16);
2139 WREG32(PA_SU_LINE_STIPPLE_VALUE, 0);
2140 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
2141
2142 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
2143 WREG32(VGT_OUT_DEALLOC_CNTL, 16);
2144
2145 WREG32(CB_PERF_CTR0_SEL_0, 0);
2146 WREG32(CB_PERF_CTR0_SEL_1, 0);
2147 WREG32(CB_PERF_CTR1_SEL_0, 0);
2148 WREG32(CB_PERF_CTR1_SEL_1, 0);
2149 WREG32(CB_PERF_CTR2_SEL_0, 0);
2150 WREG32(CB_PERF_CTR2_SEL_1, 0);
2151 WREG32(CB_PERF_CTR3_SEL_0, 0);
2152 WREG32(CB_PERF_CTR3_SEL_1, 0);
2153
2154 /* clear render buffer base addresses */
2155 WREG32(CB_COLOR0_BASE, 0);
2156 WREG32(CB_COLOR1_BASE, 0);
2157 WREG32(CB_COLOR2_BASE, 0);
2158 WREG32(CB_COLOR3_BASE, 0);
2159 WREG32(CB_COLOR4_BASE, 0);
2160 WREG32(CB_COLOR5_BASE, 0);
2161 WREG32(CB_COLOR6_BASE, 0);
2162 WREG32(CB_COLOR7_BASE, 0);
2163 WREG32(CB_COLOR8_BASE, 0);
2164 WREG32(CB_COLOR9_BASE, 0);
2165 WREG32(CB_COLOR10_BASE, 0);
2166 WREG32(CB_COLOR11_BASE, 0);
2167
2168 /* set the shader const cache sizes to 0 */
2169 for (i = SQ_ALU_CONST_BUFFER_SIZE_PS_0; i < 0x28200; i += 4)
2170 WREG32(i, 0);
2171 for (i = SQ_ALU_CONST_BUFFER_SIZE_HS_0; i < 0x29000; i += 4)
2172 WREG32(i, 0);
2173
2174 tmp = RREG32(HDP_MISC_CNTL);
2175 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
2176 WREG32(HDP_MISC_CNTL, tmp);
2177
2178 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
2179 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
2180
2181 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
2182
2183 udelay(50);
2184
2185 }
2186
2187 int evergreen_mc_init(struct radeon_device *rdev)
2188 {
2189 u32 tmp;
2190 int chansize, numchan;
2191
2192 /* Get VRAM informations */
2193 rdev->mc.vram_is_ddr = true;
2194 if ((rdev->family == CHIP_PALM) ||
2195 (rdev->family == CHIP_SUMO) ||
2196 (rdev->family == CHIP_SUMO2))
2197 tmp = RREG32(FUS_MC_ARB_RAMCFG);
2198 else
2199 tmp = RREG32(MC_ARB_RAMCFG);
2200 if (tmp & CHANSIZE_OVERRIDE) {
2201 chansize = 16;
2202 } else if (tmp & CHANSIZE_MASK) {
2203 chansize = 64;
2204 } else {
2205 chansize = 32;
2206 }
2207 tmp = RREG32(MC_SHARED_CHMAP);
2208 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
2209 case 0:
2210 default:
2211 numchan = 1;
2212 break;
2213 case 1:
2214 numchan = 2;
2215 break;
2216 case 2:
2217 numchan = 4;
2218 break;
2219 case 3:
2220 numchan = 8;
2221 break;
2222 }
2223 rdev->mc.vram_width = numchan * chansize;
2224 /* Could aper size report 0 ? */
2225 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2226 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2227 /* Setup GPU memory space */
2228 if ((rdev->family == CHIP_PALM) ||
2229 (rdev->family == CHIP_SUMO) ||
2230 (rdev->family == CHIP_SUMO2)) {
2231 /* size in bytes on fusion */
2232 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
2233 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
2234 } else {
2235 /* size in MB on evergreen/cayman/tn */
2236 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2237 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2238 }
2239 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2240 r700_vram_gtt_location(rdev, &rdev->mc);
2241 radeon_update_bandwidth_info(rdev);
2242
2243 return 0;
2244 }
2245
2246 bool evergreen_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2247 {
2248 u32 srbm_status;
2249 u32 grbm_status;
2250 u32 grbm_status_se0, grbm_status_se1;
2251
2252 srbm_status = RREG32(SRBM_STATUS);
2253 grbm_status = RREG32(GRBM_STATUS);
2254 grbm_status_se0 = RREG32(GRBM_STATUS_SE0);
2255 grbm_status_se1 = RREG32(GRBM_STATUS_SE1);
2256 if (!(grbm_status & GUI_ACTIVE)) {
2257 radeon_ring_lockup_update(ring);
2258 return false;
2259 }
2260 /* force CP activities */
2261 radeon_ring_force_activity(rdev, ring);
2262 return radeon_ring_test_lockup(rdev, ring);
2263 }
2264
2265 static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
2266 {
2267 struct evergreen_mc_save save;
2268 u32 grbm_reset = 0;
2269
2270 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
2271 return 0;
2272
2273 dev_info(rdev->dev, "GPU softreset \n");
2274 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
2275 RREG32(GRBM_STATUS));
2276 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
2277 RREG32(GRBM_STATUS_SE0));
2278 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
2279 RREG32(GRBM_STATUS_SE1));
2280 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
2281 RREG32(SRBM_STATUS));
2282 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
2283 RREG32(CP_STALLED_STAT1));
2284 dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n",
2285 RREG32(CP_STALLED_STAT2));
2286 dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n",
2287 RREG32(CP_BUSY_STAT));
2288 dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
2289 RREG32(CP_STAT));
2290 evergreen_mc_stop(rdev, &save);
2291 if (evergreen_mc_wait_for_idle(rdev)) {
2292 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2293 }
2294 /* Disable CP parsing/prefetching */
2295 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
2296
2297 /* reset all the gfx blocks */
2298 grbm_reset = (SOFT_RESET_CP |
2299 SOFT_RESET_CB |
2300 SOFT_RESET_DB |
2301 SOFT_RESET_PA |
2302 SOFT_RESET_SC |
2303 SOFT_RESET_SPI |
2304 SOFT_RESET_SH |
2305 SOFT_RESET_SX |
2306 SOFT_RESET_TC |
2307 SOFT_RESET_TA |
2308 SOFT_RESET_VC |
2309 SOFT_RESET_VGT);
2310
2311 dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
2312 WREG32(GRBM_SOFT_RESET, grbm_reset);
2313 (void)RREG32(GRBM_SOFT_RESET);
2314 udelay(50);
2315 WREG32(GRBM_SOFT_RESET, 0);
2316 (void)RREG32(GRBM_SOFT_RESET);
2317 /* Wait a little for things to settle down */
2318 udelay(50);
2319 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
2320 RREG32(GRBM_STATUS));
2321 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
2322 RREG32(GRBM_STATUS_SE0));
2323 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
2324 RREG32(GRBM_STATUS_SE1));
2325 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
2326 RREG32(SRBM_STATUS));
2327 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
2328 RREG32(CP_STALLED_STAT1));
2329 dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n",
2330 RREG32(CP_STALLED_STAT2));
2331 dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n",
2332 RREG32(CP_BUSY_STAT));
2333 dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
2334 RREG32(CP_STAT));
2335 evergreen_mc_resume(rdev, &save);
2336 return 0;
2337 }
2338
2339 int evergreen_asic_reset(struct radeon_device *rdev)
2340 {
2341 return evergreen_gpu_soft_reset(rdev);
2342 }
2343
2344 /* Interrupts */
2345
2346 u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc)
2347 {
2348 switch (crtc) {
2349 case 0:
2350 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC0_REGISTER_OFFSET);
2351 case 1:
2352 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC1_REGISTER_OFFSET);
2353 case 2:
2354 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC2_REGISTER_OFFSET);
2355 case 3:
2356 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC3_REGISTER_OFFSET);
2357 case 4:
2358 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC4_REGISTER_OFFSET);
2359 case 5:
2360 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC5_REGISTER_OFFSET);
2361 default:
2362 return 0;
2363 }
2364 }
2365
2366 void evergreen_disable_interrupt_state(struct radeon_device *rdev)
2367 {
2368 u32 tmp;
2369
2370 if (rdev->family >= CHIP_CAYMAN) {
2371 cayman_cp_int_cntl_setup(rdev, 0,
2372 CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
2373 cayman_cp_int_cntl_setup(rdev, 1, 0);
2374 cayman_cp_int_cntl_setup(rdev, 2, 0);
2375 } else
2376 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
2377 WREG32(GRBM_INT_CNTL, 0);
2378 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2379 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2380 if (rdev->num_crtc >= 4) {
2381 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2382 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2383 }
2384 if (rdev->num_crtc >= 6) {
2385 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2386 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2387 }
2388
2389 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2390 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2391 if (rdev->num_crtc >= 4) {
2392 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2393 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2394 }
2395 if (rdev->num_crtc >= 6) {
2396 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2397 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2398 }
2399
2400 /* only one DAC on DCE6 */
2401 if (!ASIC_IS_DCE6(rdev))
2402 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2403 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2404
2405 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2406 WREG32(DC_HPD1_INT_CONTROL, tmp);
2407 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2408 WREG32(DC_HPD2_INT_CONTROL, tmp);
2409 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2410 WREG32(DC_HPD3_INT_CONTROL, tmp);
2411 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2412 WREG32(DC_HPD4_INT_CONTROL, tmp);
2413 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2414 WREG32(DC_HPD5_INT_CONTROL, tmp);
2415 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2416 WREG32(DC_HPD6_INT_CONTROL, tmp);
2417
2418 }
2419
2420 int evergreen_irq_set(struct radeon_device *rdev)
2421 {
2422 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
2423 u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0;
2424 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
2425 u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
2426 u32 grbm_int_cntl = 0;
2427 u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
2428 u32 afmt1 = 0, afmt2 = 0, afmt3 = 0, afmt4 = 0, afmt5 = 0, afmt6 = 0;
2429
2430 if (!rdev->irq.installed) {
2431 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
2432 return -EINVAL;
2433 }
2434 /* don't enable anything if the ih is disabled */
2435 if (!rdev->ih.enabled) {
2436 r600_disable_interrupts(rdev);
2437 /* force the active interrupt state to all disabled */
2438 evergreen_disable_interrupt_state(rdev);
2439 return 0;
2440 }
2441
2442 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2443 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2444 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2445 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
2446 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
2447 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
2448
2449 afmt1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2450 afmt2 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2451 afmt3 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2452 afmt4 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2453 afmt5 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2454 afmt6 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2455
2456 if (rdev->family >= CHIP_CAYMAN) {
2457 /* enable CP interrupts on all rings */
2458 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
2459 DRM_DEBUG("evergreen_irq_set: sw int gfx\n");
2460 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
2461 }
2462 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP1_INDEX])) {
2463 DRM_DEBUG("evergreen_irq_set: sw int cp1\n");
2464 cp_int_cntl1 |= TIME_STAMP_INT_ENABLE;
2465 }
2466 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP2_INDEX])) {
2467 DRM_DEBUG("evergreen_irq_set: sw int cp2\n");
2468 cp_int_cntl2 |= TIME_STAMP_INT_ENABLE;
2469 }
2470 } else {
2471 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
2472 DRM_DEBUG("evergreen_irq_set: sw int gfx\n");
2473 cp_int_cntl |= RB_INT_ENABLE;
2474 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
2475 }
2476 }
2477
2478 if (rdev->irq.crtc_vblank_int[0] ||
2479 atomic_read(&rdev->irq.pflip[0])) {
2480 DRM_DEBUG("evergreen_irq_set: vblank 0\n");
2481 crtc1 |= VBLANK_INT_MASK;
2482 }
2483 if (rdev->irq.crtc_vblank_int[1] ||
2484 atomic_read(&rdev->irq.pflip[1])) {
2485 DRM_DEBUG("evergreen_irq_set: vblank 1\n");
2486 crtc2 |= VBLANK_INT_MASK;
2487 }
2488 if (rdev->irq.crtc_vblank_int[2] ||
2489 atomic_read(&rdev->irq.pflip[2])) {
2490 DRM_DEBUG("evergreen_irq_set: vblank 2\n");
2491 crtc3 |= VBLANK_INT_MASK;
2492 }
2493 if (rdev->irq.crtc_vblank_int[3] ||
2494 atomic_read(&rdev->irq.pflip[3])) {
2495 DRM_DEBUG("evergreen_irq_set: vblank 3\n");
2496 crtc4 |= VBLANK_INT_MASK;
2497 }
2498 if (rdev->irq.crtc_vblank_int[4] ||
2499 atomic_read(&rdev->irq.pflip[4])) {
2500 DRM_DEBUG("evergreen_irq_set: vblank 4\n");
2501 crtc5 |= VBLANK_INT_MASK;
2502 }
2503 if (rdev->irq.crtc_vblank_int[5] ||
2504 atomic_read(&rdev->irq.pflip[5])) {
2505 DRM_DEBUG("evergreen_irq_set: vblank 5\n");
2506 crtc6 |= VBLANK_INT_MASK;
2507 }
2508 if (rdev->irq.hpd[0]) {
2509 DRM_DEBUG("evergreen_irq_set: hpd 1\n");
2510 hpd1 |= DC_HPDx_INT_EN;
2511 }
2512 if (rdev->irq.hpd[1]) {
2513 DRM_DEBUG("evergreen_irq_set: hpd 2\n");
2514 hpd2 |= DC_HPDx_INT_EN;
2515 }
2516 if (rdev->irq.hpd[2]) {
2517 DRM_DEBUG("evergreen_irq_set: hpd 3\n");
2518 hpd3 |= DC_HPDx_INT_EN;
2519 }
2520 if (rdev->irq.hpd[3]) {
2521 DRM_DEBUG("evergreen_irq_set: hpd 4\n");
2522 hpd4 |= DC_HPDx_INT_EN;
2523 }
2524 if (rdev->irq.hpd[4]) {
2525 DRM_DEBUG("evergreen_irq_set: hpd 5\n");
2526 hpd5 |= DC_HPDx_INT_EN;
2527 }
2528 if (rdev->irq.hpd[5]) {
2529 DRM_DEBUG("evergreen_irq_set: hpd 6\n");
2530 hpd6 |= DC_HPDx_INT_EN;
2531 }
2532 if (rdev->irq.afmt[0]) {
2533 DRM_DEBUG("evergreen_irq_set: hdmi 0\n");
2534 afmt1 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2535 }
2536 if (rdev->irq.afmt[1]) {
2537 DRM_DEBUG("evergreen_irq_set: hdmi 1\n");
2538 afmt2 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2539 }
2540 if (rdev->irq.afmt[2]) {
2541 DRM_DEBUG("evergreen_irq_set: hdmi 2\n");
2542 afmt3 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2543 }
2544 if (rdev->irq.afmt[3]) {
2545 DRM_DEBUG("evergreen_irq_set: hdmi 3\n");
2546 afmt4 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2547 }
2548 if (rdev->irq.afmt[4]) {
2549 DRM_DEBUG("evergreen_irq_set: hdmi 4\n");
2550 afmt5 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2551 }
2552 if (rdev->irq.afmt[5]) {
2553 DRM_DEBUG("evergreen_irq_set: hdmi 5\n");
2554 afmt6 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2555 }
2556 if (rdev->irq.gui_idle) {
2557 DRM_DEBUG("gui idle\n");
2558 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
2559 }
2560
2561 if (rdev->family >= CHIP_CAYMAN) {
2562 cayman_cp_int_cntl_setup(rdev, 0, cp_int_cntl);
2563 cayman_cp_int_cntl_setup(rdev, 1, cp_int_cntl1);
2564 cayman_cp_int_cntl_setup(rdev, 2, cp_int_cntl2);
2565 } else
2566 WREG32(CP_INT_CNTL, cp_int_cntl);
2567 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
2568
2569 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
2570 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
2571 if (rdev->num_crtc >= 4) {
2572 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
2573 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
2574 }
2575 if (rdev->num_crtc >= 6) {
2576 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
2577 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
2578 }
2579
2580 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
2581 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
2582 if (rdev->num_crtc >= 4) {
2583 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
2584 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
2585 }
2586 if (rdev->num_crtc >= 6) {
2587 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
2588 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
2589 }
2590
2591 WREG32(DC_HPD1_INT_CONTROL, hpd1);
2592 WREG32(DC_HPD2_INT_CONTROL, hpd2);
2593 WREG32(DC_HPD3_INT_CONTROL, hpd3);
2594 WREG32(DC_HPD4_INT_CONTROL, hpd4);
2595 WREG32(DC_HPD5_INT_CONTROL, hpd5);
2596 WREG32(DC_HPD6_INT_CONTROL, hpd6);
2597
2598 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, afmt1);
2599 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, afmt2);
2600 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, afmt3);
2601 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, afmt4);
2602 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, afmt5);
2603 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, afmt6);
2604
2605 return 0;
2606 }
2607
2608 static void evergreen_irq_ack(struct radeon_device *rdev)
2609 {
2610 u32 tmp;
2611
2612 rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS);
2613 rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
2614 rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
2615 rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
2616 rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
2617 rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
2618 rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
2619 rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
2620 if (rdev->num_crtc >= 4) {
2621 rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
2622 rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
2623 }
2624 if (rdev->num_crtc >= 6) {
2625 rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
2626 rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
2627 }
2628
2629 rdev->irq.stat_regs.evergreen.afmt_status1 = RREG32(AFMT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
2630 rdev->irq.stat_regs.evergreen.afmt_status2 = RREG32(AFMT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
2631 rdev->irq.stat_regs.evergreen.afmt_status3 = RREG32(AFMT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
2632 rdev->irq.stat_regs.evergreen.afmt_status4 = RREG32(AFMT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
2633 rdev->irq.stat_regs.evergreen.afmt_status5 = RREG32(AFMT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
2634 rdev->irq.stat_regs.evergreen.afmt_status6 = RREG32(AFMT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
2635
2636 if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
2637 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2638 if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
2639 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2640 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)
2641 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
2642 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)
2643 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
2644 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)
2645 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
2646 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)
2647 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
2648
2649 if (rdev->num_crtc >= 4) {
2650 if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
2651 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2652 if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
2653 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2654 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
2655 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
2656 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
2657 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
2658 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
2659 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
2660 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
2661 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
2662 }
2663
2664 if (rdev->num_crtc >= 6) {
2665 if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
2666 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2667 if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
2668 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2669 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
2670 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
2671 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
2672 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
2673 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
2674 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
2675 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
2676 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
2677 }
2678
2679 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
2680 tmp = RREG32(DC_HPD1_INT_CONTROL);
2681 tmp |= DC_HPDx_INT_ACK;
2682 WREG32(DC_HPD1_INT_CONTROL, tmp);
2683 }
2684 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
2685 tmp = RREG32(DC_HPD2_INT_CONTROL);
2686 tmp |= DC_HPDx_INT_ACK;
2687 WREG32(DC_HPD2_INT_CONTROL, tmp);
2688 }
2689 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
2690 tmp = RREG32(DC_HPD3_INT_CONTROL);
2691 tmp |= DC_HPDx_INT_ACK;
2692 WREG32(DC_HPD3_INT_CONTROL, tmp);
2693 }
2694 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
2695 tmp = RREG32(DC_HPD4_INT_CONTROL);
2696 tmp |= DC_HPDx_INT_ACK;
2697 WREG32(DC_HPD4_INT_CONTROL, tmp);
2698 }
2699 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
2700 tmp = RREG32(DC_HPD5_INT_CONTROL);
2701 tmp |= DC_HPDx_INT_ACK;
2702 WREG32(DC_HPD5_INT_CONTROL, tmp);
2703 }
2704 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
2705 tmp = RREG32(DC_HPD5_INT_CONTROL);
2706 tmp |= DC_HPDx_INT_ACK;
2707 WREG32(DC_HPD6_INT_CONTROL, tmp);
2708 }
2709 if (rdev->irq.stat_regs.evergreen.afmt_status1 & AFMT_AZ_FORMAT_WTRIG) {
2710 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
2711 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2712 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, tmp);
2713 }
2714 if (rdev->irq.stat_regs.evergreen.afmt_status2 & AFMT_AZ_FORMAT_WTRIG) {
2715 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
2716 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2717 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, tmp);
2718 }
2719 if (rdev->irq.stat_regs.evergreen.afmt_status3 & AFMT_AZ_FORMAT_WTRIG) {
2720 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
2721 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2722 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, tmp);
2723 }
2724 if (rdev->irq.stat_regs.evergreen.afmt_status4 & AFMT_AZ_FORMAT_WTRIG) {
2725 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
2726 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2727 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, tmp);
2728 }
2729 if (rdev->irq.stat_regs.evergreen.afmt_status5 & AFMT_AZ_FORMAT_WTRIG) {
2730 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
2731 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2732 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, tmp);
2733 }
2734 if (rdev->irq.stat_regs.evergreen.afmt_status6 & AFMT_AZ_FORMAT_WTRIG) {
2735 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
2736 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2737 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, tmp);
2738 }
2739 }
2740
2741 void evergreen_irq_disable(struct radeon_device *rdev)
2742 {
2743 r600_disable_interrupts(rdev);
2744 /* Wait and acknowledge irq */
2745 mdelay(1);
2746 evergreen_irq_ack(rdev);
2747 evergreen_disable_interrupt_state(rdev);
2748 }
2749
2750 void evergreen_irq_suspend(struct radeon_device *rdev)
2751 {
2752 evergreen_irq_disable(rdev);
2753 r600_rlc_stop(rdev);
2754 }
2755
2756 static u32 evergreen_get_ih_wptr(struct radeon_device *rdev)
2757 {
2758 u32 wptr, tmp;
2759
2760 if (rdev->wb.enabled)
2761 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
2762 else
2763 wptr = RREG32(IH_RB_WPTR);
2764
2765 if (wptr & RB_OVERFLOW) {
2766 /* When a ring buffer overflow happen start parsing interrupt
2767 * from the last not overwritten vector (wptr + 16). Hopefully
2768 * this should allow us to catchup.
2769 */
2770 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
2771 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
2772 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
2773 tmp = RREG32(IH_RB_CNTL);
2774 tmp |= IH_WPTR_OVERFLOW_CLEAR;
2775 WREG32(IH_RB_CNTL, tmp);
2776 }
2777 return (wptr & rdev->ih.ptr_mask);
2778 }
2779
2780 int evergreen_irq_process(struct radeon_device *rdev)
2781 {
2782 u32 wptr;
2783 u32 rptr;
2784 u32 src_id, src_data;
2785 u32 ring_index;
2786 bool queue_hotplug = false;
2787 bool queue_hdmi = false;
2788
2789 if (!rdev->ih.enabled || rdev->shutdown)
2790 return IRQ_NONE;
2791
2792 wptr = evergreen_get_ih_wptr(rdev);
2793
2794 restart_ih:
2795 /* is somebody else already processing irqs? */
2796 if (atomic_xchg(&rdev->ih.lock, 1))
2797 return IRQ_NONE;
2798
2799 rptr = rdev->ih.rptr;
2800 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
2801
2802 /* Order reading of wptr vs. reading of IH ring data */
2803 rmb();
2804
2805 /* display interrupts */
2806 evergreen_irq_ack(rdev);
2807
2808 while (rptr != wptr) {
2809 /* wptr/rptr are in bytes! */
2810 ring_index = rptr / 4;
2811 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
2812 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
2813
2814 switch (src_id) {
2815 case 1: /* D1 vblank/vline */
2816 switch (src_data) {
2817 case 0: /* D1 vblank */
2818 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) {
2819 if (rdev->irq.crtc_vblank_int[0]) {
2820 drm_handle_vblank(rdev->ddev, 0);
2821 rdev->pm.vblank_sync = true;
2822 wake_up(&rdev->irq.vblank_queue);
2823 }
2824 if (atomic_read(&rdev->irq.pflip[0]))
2825 radeon_crtc_handle_flip(rdev, 0);
2826 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
2827 DRM_DEBUG("IH: D1 vblank\n");
2828 }
2829 break;
2830 case 1: /* D1 vline */
2831 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) {
2832 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT;
2833 DRM_DEBUG("IH: D1 vline\n");
2834 }
2835 break;
2836 default:
2837 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2838 break;
2839 }
2840 break;
2841 case 2: /* D2 vblank/vline */
2842 switch (src_data) {
2843 case 0: /* D2 vblank */
2844 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
2845 if (rdev->irq.crtc_vblank_int[1]) {
2846 drm_handle_vblank(rdev->ddev, 1);
2847 rdev->pm.vblank_sync = true;
2848 wake_up(&rdev->irq.vblank_queue);
2849 }
2850 if (atomic_read(&rdev->irq.pflip[1]))
2851 radeon_crtc_handle_flip(rdev, 1);
2852 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
2853 DRM_DEBUG("IH: D2 vblank\n");
2854 }
2855 break;
2856 case 1: /* D2 vline */
2857 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) {
2858 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
2859 DRM_DEBUG("IH: D2 vline\n");
2860 }
2861 break;
2862 default:
2863 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2864 break;
2865 }
2866 break;
2867 case 3: /* D3 vblank/vline */
2868 switch (src_data) {
2869 case 0: /* D3 vblank */
2870 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {
2871 if (rdev->irq.crtc_vblank_int[2]) {
2872 drm_handle_vblank(rdev->ddev, 2);
2873 rdev->pm.vblank_sync = true;
2874 wake_up(&rdev->irq.vblank_queue);
2875 }
2876 if (atomic_read(&rdev->irq.pflip[2]))
2877 radeon_crtc_handle_flip(rdev, 2);
2878 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
2879 DRM_DEBUG("IH: D3 vblank\n");
2880 }
2881 break;
2882 case 1: /* D3 vline */
2883 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) {
2884 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
2885 DRM_DEBUG("IH: D3 vline\n");
2886 }
2887 break;
2888 default:
2889 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2890 break;
2891 }
2892 break;
2893 case 4: /* D4 vblank/vline */
2894 switch (src_data) {
2895 case 0: /* D4 vblank */
2896 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {
2897 if (rdev->irq.crtc_vblank_int[3]) {
2898 drm_handle_vblank(rdev->ddev, 3);
2899 rdev->pm.vblank_sync = true;
2900 wake_up(&rdev->irq.vblank_queue);
2901 }
2902 if (atomic_read(&rdev->irq.pflip[3]))
2903 radeon_crtc_handle_flip(rdev, 3);
2904 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
2905 DRM_DEBUG("IH: D4 vblank\n");
2906 }
2907 break;
2908 case 1: /* D4 vline */
2909 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) {
2910 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
2911 DRM_DEBUG("IH: D4 vline\n");
2912 }
2913 break;
2914 default:
2915 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2916 break;
2917 }
2918 break;
2919 case 5: /* D5 vblank/vline */
2920 switch (src_data) {
2921 case 0: /* D5 vblank */
2922 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {
2923 if (rdev->irq.crtc_vblank_int[4]) {
2924 drm_handle_vblank(rdev->ddev, 4);
2925 rdev->pm.vblank_sync = true;
2926 wake_up(&rdev->irq.vblank_queue);
2927 }
2928 if (atomic_read(&rdev->irq.pflip[4]))
2929 radeon_crtc_handle_flip(rdev, 4);
2930 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
2931 DRM_DEBUG("IH: D5 vblank\n");
2932 }
2933 break;
2934 case 1: /* D5 vline */
2935 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) {
2936 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
2937 DRM_DEBUG("IH: D5 vline\n");
2938 }
2939 break;
2940 default:
2941 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2942 break;
2943 }
2944 break;
2945 case 6: /* D6 vblank/vline */
2946 switch (src_data) {
2947 case 0: /* D6 vblank */
2948 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {
2949 if (rdev->irq.crtc_vblank_int[5]) {
2950 drm_handle_vblank(rdev->ddev, 5);
2951 rdev->pm.vblank_sync = true;
2952 wake_up(&rdev->irq.vblank_queue);
2953 }
2954 if (atomic_read(&rdev->irq.pflip[5]))
2955 radeon_crtc_handle_flip(rdev, 5);
2956 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
2957 DRM_DEBUG("IH: D6 vblank\n");
2958 }
2959 break;
2960 case 1: /* D6 vline */
2961 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) {
2962 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
2963 DRM_DEBUG("IH: D6 vline\n");
2964 }
2965 break;
2966 default:
2967 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2968 break;
2969 }
2970 break;
2971 case 42: /* HPD hotplug */
2972 switch (src_data) {
2973 case 0:
2974 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
2975 rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT;
2976 queue_hotplug = true;
2977 DRM_DEBUG("IH: HPD1\n");
2978 }
2979 break;
2980 case 1:
2981 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
2982 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT;
2983 queue_hotplug = true;
2984 DRM_DEBUG("IH: HPD2\n");
2985 }
2986 break;
2987 case 2:
2988 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
2989 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
2990 queue_hotplug = true;
2991 DRM_DEBUG("IH: HPD3\n");
2992 }
2993 break;
2994 case 3:
2995 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
2996 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
2997 queue_hotplug = true;
2998 DRM_DEBUG("IH: HPD4\n");
2999 }
3000 break;
3001 case 4:
3002 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
3003 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
3004 queue_hotplug = true;
3005 DRM_DEBUG("IH: HPD5\n");
3006 }
3007 break;
3008 case 5:
3009 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
3010 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
3011 queue_hotplug = true;
3012 DRM_DEBUG("IH: HPD6\n");
3013 }
3014 break;
3015 default:
3016 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3017 break;
3018 }
3019 break;
3020 case 44: /* hdmi */
3021 switch (src_data) {
3022 case 0:
3023 if (rdev->irq.stat_regs.evergreen.afmt_status1 & AFMT_AZ_FORMAT_WTRIG) {
3024 rdev->irq.stat_regs.evergreen.afmt_status1 &= ~AFMT_AZ_FORMAT_WTRIG;
3025 queue_hdmi = true;
3026 DRM_DEBUG("IH: HDMI0\n");
3027 }
3028 break;
3029 case 1:
3030 if (rdev->irq.stat_regs.evergreen.afmt_status2 & AFMT_AZ_FORMAT_WTRIG) {
3031 rdev->irq.stat_regs.evergreen.afmt_status2 &= ~AFMT_AZ_FORMAT_WTRIG;
3032 queue_hdmi = true;
3033 DRM_DEBUG("IH: HDMI1\n");
3034 }
3035 break;
3036 case 2:
3037 if (rdev->irq.stat_regs.evergreen.afmt_status3 & AFMT_AZ_FORMAT_WTRIG) {
3038 rdev->irq.stat_regs.evergreen.afmt_status3 &= ~AFMT_AZ_FORMAT_WTRIG;
3039 queue_hdmi = true;
3040 DRM_DEBUG("IH: HDMI2\n");
3041 }
3042 break;
3043 case 3:
3044 if (rdev->irq.stat_regs.evergreen.afmt_status4 & AFMT_AZ_FORMAT_WTRIG) {
3045 rdev->irq.stat_regs.evergreen.afmt_status4 &= ~AFMT_AZ_FORMAT_WTRIG;
3046 queue_hdmi = true;
3047 DRM_DEBUG("IH: HDMI3\n");
3048 }
3049 break;
3050 case 4:
3051 if (rdev->irq.stat_regs.evergreen.afmt_status5 & AFMT_AZ_FORMAT_WTRIG) {
3052 rdev->irq.stat_regs.evergreen.afmt_status5 &= ~AFMT_AZ_FORMAT_WTRIG;
3053 queue_hdmi = true;
3054 DRM_DEBUG("IH: HDMI4\n");
3055 }
3056 break;
3057 case 5:
3058 if (rdev->irq.stat_regs.evergreen.afmt_status6 & AFMT_AZ_FORMAT_WTRIG) {
3059 rdev->irq.stat_regs.evergreen.afmt_status6 &= ~AFMT_AZ_FORMAT_WTRIG;
3060 queue_hdmi = true;
3061 DRM_DEBUG("IH: HDMI5\n");
3062 }
3063 break;
3064 default:
3065 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
3066 break;
3067 }
3068 break;
3069 case 176: /* CP_INT in ring buffer */
3070 case 177: /* CP_INT in IB1 */
3071 case 178: /* CP_INT in IB2 */
3072 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
3073 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
3074 break;
3075 case 181: /* CP EOP event */
3076 DRM_DEBUG("IH: CP EOP\n");
3077 if (rdev->family >= CHIP_CAYMAN) {
3078 switch (src_data) {
3079 case 0:
3080 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
3081 break;
3082 case 1:
3083 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
3084 break;
3085 case 2:
3086 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
3087 break;
3088 }
3089 } else
3090 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
3091 break;
3092 case 233: /* GUI IDLE */
3093 DRM_DEBUG("IH: GUI idle\n");
3094 wake_up(&rdev->irq.idle_queue);
3095 break;
3096 default:
3097 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3098 break;
3099 }
3100
3101 /* wptr/rptr are in bytes! */
3102 rptr += 16;
3103 rptr &= rdev->ih.ptr_mask;
3104 }
3105 if (queue_hotplug)
3106 schedule_work(&rdev->hotplug_work);
3107 if (queue_hdmi)
3108 schedule_work(&rdev->audio_work);
3109 rdev->ih.rptr = rptr;
3110 WREG32(IH_RB_RPTR, rdev->ih.rptr);
3111 atomic_set(&rdev->ih.lock, 0);
3112
3113 /* make sure wptr hasn't changed while processing */
3114 wptr = evergreen_get_ih_wptr(rdev);
3115 if (wptr != rptr)
3116 goto restart_ih;
3117
3118 return IRQ_HANDLED;
3119 }
3120
3121 static int evergreen_startup(struct radeon_device *rdev)
3122 {
3123 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3124 int r;
3125
3126 /* enable pcie gen2 link */
3127 evergreen_pcie_gen2_enable(rdev);
3128
3129 if (ASIC_IS_DCE5(rdev)) {
3130 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
3131 r = ni_init_microcode(rdev);
3132 if (r) {
3133 DRM_ERROR("Failed to load firmware!\n");
3134 return r;
3135 }
3136 }
3137 r = ni_mc_load_microcode(rdev);
3138 if (r) {
3139 DRM_ERROR("Failed to load MC firmware!\n");
3140 return r;
3141 }
3142 } else {
3143 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
3144 r = r600_init_microcode(rdev);
3145 if (r) {
3146 DRM_ERROR("Failed to load firmware!\n");
3147 return r;
3148 }
3149 }
3150 }
3151
3152 r = r600_vram_scratch_init(rdev);
3153 if (r)
3154 return r;
3155
3156 evergreen_mc_program(rdev);
3157 if (rdev->flags & RADEON_IS_AGP) {
3158 evergreen_agp_enable(rdev);
3159 } else {
3160 r = evergreen_pcie_gart_enable(rdev);
3161 if (r)
3162 return r;
3163 }
3164 evergreen_gpu_init(rdev);
3165
3166 r = evergreen_blit_init(rdev);
3167 if (r) {
3168 r600_blit_fini(rdev);
3169 rdev->asic->copy.copy = NULL;
3170 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
3171 }
3172
3173 /* allocate wb buffer */
3174 r = radeon_wb_init(rdev);
3175 if (r)
3176 return r;
3177
3178 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
3179 if (r) {
3180 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3181 return r;
3182 }
3183
3184 /* Enable IRQ */
3185 r = r600_irq_init(rdev);
3186 if (r) {
3187 DRM_ERROR("radeon: IH init failed (%d).\n", r);
3188 radeon_irq_kms_fini(rdev);
3189 return r;
3190 }
3191 evergreen_irq_set(rdev);
3192
3193 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
3194 R600_CP_RB_RPTR, R600_CP_RB_WPTR,
3195 0, 0xfffff, RADEON_CP_PACKET2);
3196 if (r)
3197 return r;
3198 r = evergreen_cp_load_microcode(rdev);
3199 if (r)
3200 return r;
3201 r = evergreen_cp_resume(rdev);
3202 if (r)
3203 return r;
3204
3205 r = radeon_ib_pool_init(rdev);
3206 if (r) {
3207 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
3208 return r;
3209 }
3210
3211 r = r600_audio_init(rdev);
3212 if (r) {
3213 DRM_ERROR("radeon: audio init failed\n");
3214 return r;
3215 }
3216
3217 return 0;
3218 }
3219
3220 int evergreen_resume(struct radeon_device *rdev)
3221 {
3222 int r;
3223
3224 /* reset the asic, the gfx blocks are often in a bad state
3225 * after the driver is unloaded or after a resume
3226 */
3227 if (radeon_asic_reset(rdev))
3228 dev_warn(rdev->dev, "GPU reset failed !\n");
3229 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
3230 * posting will perform necessary task to bring back GPU into good
3231 * shape.
3232 */
3233 /* post card */
3234 atom_asic_init(rdev->mode_info.atom_context);
3235
3236 rdev->accel_working = true;
3237 r = evergreen_startup(rdev);
3238 if (r) {
3239 DRM_ERROR("evergreen startup failed on resume\n");
3240 rdev->accel_working = false;
3241 return r;
3242 }
3243
3244 return r;
3245
3246 }
3247
3248 int evergreen_suspend(struct radeon_device *rdev)
3249 {
3250 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3251
3252 r600_audio_fini(rdev);
3253 r700_cp_stop(rdev);
3254 ring->ready = false;
3255 evergreen_irq_suspend(rdev);
3256 radeon_wb_disable(rdev);
3257 evergreen_pcie_gart_disable(rdev);
3258
3259 return 0;
3260 }
3261
3262 /* Plan is to move initialization in that function and use
3263 * helper function so that radeon_device_init pretty much
3264 * do nothing more than calling asic specific function. This
3265 * should also allow to remove a bunch of callback function
3266 * like vram_info.
3267 */
3268 int evergreen_init(struct radeon_device *rdev)
3269 {
3270 int r;
3271
3272 /* Read BIOS */
3273 if (!radeon_get_bios(rdev)) {
3274 if (ASIC_IS_AVIVO(rdev))
3275 return -EINVAL;
3276 }
3277 /* Must be an ATOMBIOS */
3278 if (!rdev->is_atom_bios) {
3279 dev_err(rdev->dev, "Expecting atombios for evergreen GPU\n");
3280 return -EINVAL;
3281 }
3282 r = radeon_atombios_init(rdev);
3283 if (r)
3284 return r;
3285 /* reset the asic, the gfx blocks are often in a bad state
3286 * after the driver is unloaded or after a resume
3287 */
3288 if (radeon_asic_reset(rdev))
3289 dev_warn(rdev->dev, "GPU reset failed !\n");
3290 /* Post card if necessary */
3291 if (!radeon_card_posted(rdev)) {
3292 if (!rdev->bios) {
3293 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
3294 return -EINVAL;
3295 }
3296 DRM_INFO("GPU not posted. posting now...\n");
3297 atom_asic_init(rdev->mode_info.atom_context);
3298 }
3299 /* Initialize scratch registers */
3300 r600_scratch_init(rdev);
3301 /* Initialize surface registers */
3302 radeon_surface_init(rdev);
3303 /* Initialize clocks */
3304 radeon_get_clock_info(rdev->ddev);
3305 /* Fence driver */
3306 r = radeon_fence_driver_init(rdev);
3307 if (r)
3308 return r;
3309 /* initialize AGP */
3310 if (rdev->flags & RADEON_IS_AGP) {
3311 r = radeon_agp_init(rdev);
3312 if (r)
3313 radeon_agp_disable(rdev);
3314 }
3315 /* initialize memory controller */
3316 r = evergreen_mc_init(rdev);
3317 if (r)
3318 return r;
3319 /* Memory manager */
3320 r = radeon_bo_init(rdev);
3321 if (r)
3322 return r;
3323
3324 r = radeon_irq_kms_init(rdev);
3325 if (r)
3326 return r;
3327
3328 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
3329 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
3330
3331 rdev->ih.ring_obj = NULL;
3332 r600_ih_ring_init(rdev, 64 * 1024);
3333
3334 r = r600_pcie_gart_init(rdev);
3335 if (r)
3336 return r;
3337
3338 rdev->accel_working = true;
3339 r = evergreen_startup(rdev);
3340 if (r) {
3341 dev_err(rdev->dev, "disabling GPU acceleration\n");
3342 r700_cp_fini(rdev);
3343 r600_irq_fini(rdev);
3344 radeon_wb_fini(rdev);
3345 radeon_ib_pool_fini(rdev);
3346 radeon_irq_kms_fini(rdev);
3347 evergreen_pcie_gart_fini(rdev);
3348 rdev->accel_working = false;
3349 }
3350
3351 /* Don't start up if the MC ucode is missing on BTC parts.
3352 * The default clocks and voltages before the MC ucode
3353 * is loaded are not suffient for advanced operations.
3354 */
3355 if (ASIC_IS_DCE5(rdev)) {
3356 if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) {
3357 DRM_ERROR("radeon: MC ucode required for NI+.\n");
3358 return -EINVAL;
3359 }
3360 }
3361
3362 return 0;
3363 }
3364
3365 void evergreen_fini(struct radeon_device *rdev)
3366 {
3367 r600_audio_fini(rdev);
3368 r600_blit_fini(rdev);
3369 r700_cp_fini(rdev);
3370 r600_irq_fini(rdev);
3371 radeon_wb_fini(rdev);
3372 radeon_ib_pool_fini(rdev);
3373 radeon_irq_kms_fini(rdev);
3374 evergreen_pcie_gart_fini(rdev);
3375 r600_vram_scratch_fini(rdev);
3376 radeon_gem_fini(rdev);
3377 radeon_fence_driver_fini(rdev);
3378 radeon_agp_fini(rdev);
3379 radeon_bo_fini(rdev);
3380 radeon_atombios_fini(rdev);
3381 kfree(rdev->bios);
3382 rdev->bios = NULL;
3383 }
3384
3385 void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
3386 {
3387 u32 link_width_cntl, speed_cntl, mask;
3388 int ret;
3389
3390 if (radeon_pcie_gen2 == 0)
3391 return;
3392
3393 if (rdev->flags & RADEON_IS_IGP)
3394 return;
3395
3396 if (!(rdev->flags & RADEON_IS_PCIE))
3397 return;
3398
3399 /* x2 cards have a special sequence */
3400 if (ASIC_IS_X2(rdev))
3401 return;
3402
3403 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
3404 if (ret != 0)
3405 return;
3406
3407 if (!(mask & DRM_PCIE_SPEED_50))
3408 return;
3409
3410 DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
3411
3412 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3413 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) ||
3414 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
3415
3416 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3417 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3418 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3419
3420 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3421 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
3422 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3423
3424 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3425 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
3426 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3427
3428 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3429 speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
3430 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3431
3432 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3433 speed_cntl |= LC_GEN2_EN_STRAP;
3434 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3435
3436 } else {
3437 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3438 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
3439 if (1)
3440 link_width_cntl |= LC_UPCONFIGURE_DIS;
3441 else
3442 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3443 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3444 }
3445 }
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git