drivers/gpu/drm/rockchip/rockchip_drm_vop.h

   1 /*
   2  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
   3  * Author:Mark Yao <mark.yao@rock-chips.com>
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #ifndef _ROCKCHIP_DRM_VOP_H
  16 #define _ROCKCHIP_DRM_VOP_H
  17
  18 /*
  19  * major: IP major version, used for IP structure
  20  * minor: big feature change under same structure
  21  */
  22 #define VOP_VERSION(major, minor)       ((major) << 8 | (minor))
  23 #define VOP_MAJOR(version)              ((version) >> 8)
  24 #define VOP_MINOR(version)              ((version) & 0xff)
  25
  26 enum vop_data_format {
  27         VOP_FMT_ARGB8888 = 0,
  28         VOP_FMT_RGB888,
  29         VOP_FMT_RGB565,
  30         VOP_FMT_YUV420SP = 4,
  31         VOP_FMT_YUV422SP,
  32         VOP_FMT_YUV444SP,
  33 };
  34
  35 struct vop_reg {
  36         uint32_t mask;
  37         uint16_t offset;
  38         uint8_t shift;
  39         bool write_mask;
  40         bool relaxed;
  41 };
  42
  43 struct vop_modeset {
  44         struct vop_reg htotal_pw;
  45         struct vop_reg hact_st_end;
  46         struct vop_reg hpost_st_end;
  47         struct vop_reg vtotal_pw;
  48         struct vop_reg vact_st_end;
  49         struct vop_reg vpost_st_end;
  50 };
  51
  52 struct vop_output {
  53         struct vop_reg pin_pol;
  54         struct vop_reg dp_pin_pol;
  55         struct vop_reg edp_pin_pol;
  56         struct vop_reg hdmi_pin_pol;
  57         struct vop_reg mipi_pin_pol;
  58         struct vop_reg rgb_pin_pol;
  59         struct vop_reg dp_en;
  60         struct vop_reg edp_en;
  61         struct vop_reg hdmi_en;
  62         struct vop_reg mipi_en;
  63         struct vop_reg mipi_dual_channel_en;
  64         struct vop_reg rgb_en;
  65 };
  66
  67 struct vop_common {
  68         struct vop_reg cfg_done;
  69         struct vop_reg dsp_blank;
  70         struct vop_reg data_blank;
  71         struct vop_reg pre_dither_down;
  72         struct vop_reg dither_down;
  73         struct vop_reg dither_up;
  74         struct vop_reg gate_en;
  75         struct vop_reg mmu_en;
  76         struct vop_reg out_mode;
  77         struct vop_reg standby;
  78 };
  79
  80 struct vop_misc {
  81         struct vop_reg global_regdone_en;
  82 };
  83
  84 struct vop_intr {
  85         const int *intrs;
  86         uint32_t nintrs;
  87
  88         struct vop_reg line_flag_num[2];
  89         struct vop_reg enable;
  90         struct vop_reg clear;
  91         struct vop_reg status;
  92 };
  93
  94 struct vop_scl_extension {
  95         struct vop_reg cbcr_vsd_mode;
  96         struct vop_reg cbcr_vsu_mode;
  97         struct vop_reg cbcr_hsd_mode;
  98         struct vop_reg cbcr_ver_scl_mode;
  99         struct vop_reg cbcr_hor_scl_mode;
 100         struct vop_reg yrgb_vsd_mode;
 101         struct vop_reg yrgb_vsu_mode;
 102         struct vop_reg yrgb_hsd_mode;
 103         struct vop_reg yrgb_ver_scl_mode;
 104         struct vop_reg yrgb_hor_scl_mode;
 105         struct vop_reg line_load_mode;
 106         struct vop_reg cbcr_axi_gather_num;
 107         struct vop_reg yrgb_axi_gather_num;
 108         struct vop_reg vsd_cbcr_gt2;
 109         struct vop_reg vsd_cbcr_gt4;
 110         struct vop_reg vsd_yrgb_gt2;
 111         struct vop_reg vsd_yrgb_gt4;
 112         struct vop_reg bic_coe_sel;
 113         struct vop_reg cbcr_axi_gather_en;
 114         struct vop_reg yrgb_axi_gather_en;
 115         struct vop_reg lb_mode;
 116 };
 117
 118 struct vop_scl_regs {
 119         const struct vop_scl_extension *ext;
 120
 121         struct vop_reg scale_yrgb_x;
 122         struct vop_reg scale_yrgb_y;
 123         struct vop_reg scale_cbcr_x;
 124         struct vop_reg scale_cbcr_y;
 125 };
 126
 127 struct vop_win_phy {
 128         const struct vop_scl_regs *scl;
 129         const uint32_t *data_formats;
 130         uint32_t nformats;
 131
 132         struct vop_reg enable;
 133         struct vop_reg gate;
 134         struct vop_reg format;
 135         struct vop_reg rb_swap;
 136         struct vop_reg act_info;
 137         struct vop_reg dsp_info;
 138         struct vop_reg dsp_st;
 139         struct vop_reg yrgb_mst;
 140         struct vop_reg uv_mst;
 141         struct vop_reg yrgb_vir;
 142         struct vop_reg uv_vir;
 143
 144         struct vop_reg dst_alpha_ctl;
 145         struct vop_reg src_alpha_ctl;
 146         struct vop_reg channel;
 147 };
 148
 149 struct vop_win_data {
 150         uint32_t base;
 151         const struct vop_win_phy *phy;
 152         enum drm_plane_type type;
 153 };
 154
 155 struct vop_data {
 156         uint32_t version;
 157         const struct vop_intr *intr;
 158         const struct vop_common *common;
 159         const struct vop_misc *misc;
 160         const struct vop_modeset *modeset;
 161         const struct vop_output *output;
 162         const struct vop_win_data *win;
 163         unsigned int win_size;
 164
 165 #define VOP_FEATURE_OUTPUT_RGB10        BIT(0)
 166 #define VOP_FEATURE_INTERNAL_RGB        BIT(1)
 167         u64 feature;
 168 };
 169
 170 /* interrupt define */
 171 #define DSP_HOLD_VALID_INTR             (1 << 0)
 172 #define FS_INTR                         (1 << 1)
 173 #define LINE_FLAG_INTR                  (1 << 2)
 174 #define BUS_ERROR_INTR                  (1 << 3)
 175
 176 #define INTR_MASK                       (DSP_HOLD_VALID_INTR | FS_INTR | \
 177                                          LINE_FLAG_INTR | BUS_ERROR_INTR)
 178
 179 #define DSP_HOLD_VALID_INTR_EN(x)       ((x) << 4)
 180 #define FS_INTR_EN(x)                   ((x) << 5)
 181 #define LINE_FLAG_INTR_EN(x)            ((x) << 6)
 182 #define BUS_ERROR_INTR_EN(x)            ((x) << 7)
 183 #define DSP_HOLD_VALID_INTR_MASK        (1 << 4)
 184 #define FS_INTR_MASK                    (1 << 5)
 185 #define LINE_FLAG_INTR_MASK             (1 << 6)
 186 #define BUS_ERROR_INTR_MASK             (1 << 7)
 187
 188 #define INTR_CLR_SHIFT                  8
 189 #define DSP_HOLD_VALID_INTR_CLR         (1 << (INTR_CLR_SHIFT + 0))
 190 #define FS_INTR_CLR                     (1 << (INTR_CLR_SHIFT + 1))
 191 #define LINE_FLAG_INTR_CLR              (1 << (INTR_CLR_SHIFT + 2))
 192 #define BUS_ERROR_INTR_CLR              (1 << (INTR_CLR_SHIFT + 3))
 193
 194 #define DSP_LINE_NUM(x)                 (((x) & 0x1fff) << 12)
 195 #define DSP_LINE_NUM_MASK               (0x1fff << 12)
 196
 197 /* src alpha ctrl define */
 198 #define SRC_FADING_VALUE(x)             (((x) & 0xff) << 24)
 199 #define SRC_GLOBAL_ALPHA(x)             (((x) & 0xff) << 16)
 200 #define SRC_FACTOR_M0(x)                (((x) & 0x7) << 6)
 201 #define SRC_ALPHA_CAL_M0(x)             (((x) & 0x1) << 5)
 202 #define SRC_BLEND_M0(x)                 (((x) & 0x3) << 3)
 203 #define SRC_ALPHA_M0(x)                 (((x) & 0x1) << 2)
 204 #define SRC_COLOR_M0(x)                 (((x) & 0x1) << 1)
 205 #define SRC_ALPHA_EN(x)                 (((x) & 0x1) << 0)
 206 /* dst alpha ctrl define */
 207 #define DST_FACTOR_M0(x)                (((x) & 0x7) << 6)
 208
 209 /*
 210  * display output interface supported by rockchip lcdc
 211  */
 212 #define ROCKCHIP_OUT_MODE_P888  0
 213 #define ROCKCHIP_OUT_MODE_P666  1
 214 #define ROCKCHIP_OUT_MODE_P565  2
 215 /* for use special outface */
 216 #define ROCKCHIP_OUT_MODE_AAAA  15
 217
 218 /* output flags */
 219 #define ROCKCHIP_OUTPUT_DSI_DUAL        BIT(0)
 220
 221 enum alpha_mode {
 222         ALPHA_STRAIGHT,
 223         ALPHA_INVERSE,
 224 };
 225
 226 enum global_blend_mode {
 227         ALPHA_GLOBAL,
 228         ALPHA_PER_PIX,
 229         ALPHA_PER_PIX_GLOBAL,
 230 };
 231
 232 enum alpha_cal_mode {
 233         ALPHA_SATURATION,
 234         ALPHA_NO_SATURATION,
 235 };
 236
 237 enum color_mode {
 238         ALPHA_SRC_PRE_MUL,
 239         ALPHA_SRC_NO_PRE_MUL,
 240 };
 241
 242 enum factor_mode {
 243         ALPHA_ZERO,
 244         ALPHA_ONE,
 245         ALPHA_SRC,
 246         ALPHA_SRC_INVERSE,
 247         ALPHA_SRC_GLOBAL,
 248 };
 249
 250 enum scale_mode {
 251         SCALE_NONE = 0x0,
 252         SCALE_UP   = 0x1,
 253         SCALE_DOWN = 0x2
 254 };
 255
 256 enum lb_mode {
 257         LB_YUV_3840X5 = 0x0,
 258         LB_YUV_2560X8 = 0x1,
 259         LB_RGB_3840X2 = 0x2,
 260         LB_RGB_2560X4 = 0x3,
 261         LB_RGB_1920X5 = 0x4,
 262         LB_RGB_1280X8 = 0x5
 263 };
 264
 265 enum sacle_up_mode {
 266         SCALE_UP_BIL = 0x0,
 267         SCALE_UP_BIC = 0x1
 268 };
 269
 270 enum scale_down_mode {
 271         SCALE_DOWN_BIL = 0x0,
 272         SCALE_DOWN_AVG = 0x1
 273 };
 274
 275 enum vop_pol {
 276         HSYNC_POSITIVE = 0,
 277         VSYNC_POSITIVE = 1,
 278         DEN_NEGATIVE   = 2,
 279         DCLK_INVERT    = 3
 280 };
 281
 282 #define FRAC_16_16(mult, div)    (((mult) << 16) / (div))
 283 #define SCL_FT_DEFAULT_FIXPOINT_SHIFT   12
 284 #define SCL_MAX_VSKIPLINES              4
 285 #define MIN_SCL_FT_AFTER_VSKIP          1
 286
 287 static inline uint16_t scl_cal_scale(int src, int dst, int shift)
 288 {
 289         return ((src * 2 - 3) << (shift - 1)) / (dst - 1);
 290 }
 291
 292 static inline uint16_t scl_cal_scale2(int src, int dst)
 293 {
 294         return ((src - 1) << 12) / (dst - 1);
 295 }
 296
 297 #define GET_SCL_FT_BILI_DN(src, dst)    scl_cal_scale(src, dst, 12)
 298 #define GET_SCL_FT_BILI_UP(src, dst)    scl_cal_scale(src, dst, 16)
 299 #define GET_SCL_FT_BIC(src, dst)        scl_cal_scale(src, dst, 16)
 300
 301 static inline uint16_t scl_get_bili_dn_vskip(int src_h, int dst_h,
 302                                              int vskiplines)
 303 {
 304         int act_height;
 305
 306         act_height = (src_h + vskiplines - 1) / vskiplines;
 307
 308         if (act_height == dst_h)
 309                 return GET_SCL_FT_BILI_DN(src_h, dst_h) / vskiplines;
 310
 311         return GET_SCL_FT_BILI_DN(act_height, dst_h);
 312 }
 313
 314 static inline enum scale_mode scl_get_scl_mode(int src, int dst)
 315 {
 316         if (src < dst)
 317                 return SCALE_UP;
 318         else if (src > dst)
 319                 return SCALE_DOWN;
 320
 321         return SCALE_NONE;
 322 }
 323
 324 static inline int scl_get_vskiplines(uint32_t srch, uint32_t dsth)
 325 {
 326         uint32_t vskiplines;
 327
 328         for (vskiplines = SCL_MAX_VSKIPLINES; vskiplines > 1; vskiplines /= 2)
 329                 if (srch >= vskiplines * dsth * MIN_SCL_FT_AFTER_VSKIP)
 330                         break;
 331
 332         return vskiplines;
 333 }
 334
 335 static inline int scl_vop_cal_lb_mode(int width, bool is_yuv)
 336 {
 337         int lb_mode;
 338
 339         if (is_yuv) {
 340                 if (width > 1280)
 341                         lb_mode = LB_YUV_3840X5;
 342                 else
 343                         lb_mode = LB_YUV_2560X8;
 344         } else {
 345                 if (width > 2560)
 346                         lb_mode = LB_RGB_3840X2;
 347                 else if (width > 1920)
 348                         lb_mode = LB_RGB_2560X4;
 349                 else
 350                         lb_mode = LB_RGB_1920X5;
 351         }
 352
 353         return lb_mode;
 354 }
 355
 356 extern const struct component_ops vop_component_ops;
 357 #endif /* _ROCKCHIP_DRM_VOP_H */