1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2016 Allwinnertech Co., Ltd.
4 * Copyright (C) 2017-2018 Bootlin
6 * Maxime Ripard <maxime.ripard@bootlin.com>
10 #include <linux/component.h>
11 #include <linux/crc-ccitt.h>
12 #include <linux/module.h>
13 #include <linux/of_address.h>
14 #include <linux/phy/phy-mipi-dphy.h>
15 #include <linux/phy/phy.h>
16 #include <linux/platform_device.h>
17 #include <linux/regmap.h>
18 #include <linux/regulator/consumer.h>
19 #include <linux/reset.h>
20 #include <linux/slab.h>
22 #include <drm/drm_atomic_helper.h>
23 #include <drm/drm_mipi_dsi.h>
24 #include <drm/drm_panel.h>
25 #include <drm/drm_print.h>
26 #include <drm/drm_probe_helper.h>
28 #include "sun4i_crtc.h"
29 #include "sun4i_tcon.h"
30 #include "sun6i_mipi_dsi.h"
32 #include <video/mipi_display.h>
34 #define SUN6I_DSI_CTL_REG 0x000
35 #define SUN6I_DSI_CTL_EN BIT(0)
37 #define SUN6I_DSI_BASIC_CTL_REG 0x00c
38 #define SUN6I_DSI_BASIC_CTL_TRAIL_INV(n) (((n) & 0xf) << 4)
39 #define SUN6I_DSI_BASIC_CTL_TRAIL_FILL BIT(3)
40 #define SUN6I_DSI_BASIC_CTL_HBP_DIS BIT(2)
41 #define SUN6I_DSI_BASIC_CTL_HSA_HSE_DIS BIT(1)
42 #define SUN6I_DSI_BASIC_CTL_VIDEO_BURST BIT(0)
44 #define SUN6I_DSI_BASIC_CTL0_REG 0x010
45 #define SUN6I_DSI_BASIC_CTL0_HS_EOTP_EN BIT(18)
46 #define SUN6I_DSI_BASIC_CTL0_CRC_EN BIT(17)
47 #define SUN6I_DSI_BASIC_CTL0_ECC_EN BIT(16)
48 #define SUN6I_DSI_BASIC_CTL0_INST_ST BIT(0)
50 #define SUN6I_DSI_BASIC_CTL1_REG 0x014
51 #define SUN6I_DSI_BASIC_CTL1_VIDEO_ST_DELAY(n) (((n) & 0x1fff) << 4)
52 #define SUN6I_DSI_BASIC_CTL1_VIDEO_FILL BIT(2)
53 #define SUN6I_DSI_BASIC_CTL1_VIDEO_PRECISION BIT(1)
54 #define SUN6I_DSI_BASIC_CTL1_VIDEO_MODE BIT(0)
56 #define SUN6I_DSI_BASIC_SIZE0_REG 0x018
57 #define SUN6I_DSI_BASIC_SIZE0_VBP(n) (((n) & 0xfff) << 16)
58 #define SUN6I_DSI_BASIC_SIZE0_VSA(n) ((n) & 0xfff)
60 #define SUN6I_DSI_BASIC_SIZE1_REG 0x01c
61 #define SUN6I_DSI_BASIC_SIZE1_VT(n) (((n) & 0xfff) << 16)
62 #define SUN6I_DSI_BASIC_SIZE1_VACT(n) ((n) & 0xfff)
64 #define SUN6I_DSI_INST_FUNC_REG(n) (0x020 + (n) * 0x04)
65 #define SUN6I_DSI_INST_FUNC_INST_MODE(n) (((n) & 0xf) << 28)
66 #define SUN6I_DSI_INST_FUNC_ESCAPE_ENTRY(n) (((n) & 0xf) << 24)
67 #define SUN6I_DSI_INST_FUNC_TRANS_PACKET(n) (((n) & 0xf) << 20)
68 #define SUN6I_DSI_INST_FUNC_LANE_CEN BIT(4)
69 #define SUN6I_DSI_INST_FUNC_LANE_DEN(n) ((n) & 0xf)
71 #define SUN6I_DSI_INST_LOOP_SEL_REG 0x040
73 #define SUN6I_DSI_INST_LOOP_NUM_REG(n) (0x044 + (n) * 0x10)
74 #define SUN6I_DSI_INST_LOOP_NUM_N1(n) (((n) & 0xfff) << 16)
75 #define SUN6I_DSI_INST_LOOP_NUM_N0(n) ((n) & 0xfff)
77 #define SUN6I_DSI_INST_JUMP_SEL_REG 0x048
79 #define SUN6I_DSI_INST_JUMP_CFG_REG(n) (0x04c + (n) * 0x04)
80 #define SUN6I_DSI_INST_JUMP_CFG_TO(n) (((n) & 0xf) << 20)
81 #define SUN6I_DSI_INST_JUMP_CFG_POINT(n) (((n) & 0xf) << 16)
82 #define SUN6I_DSI_INST_JUMP_CFG_NUM(n) ((n) & 0xffff)
84 #define SUN6I_DSI_TRANS_START_REG 0x060
86 #define SUN6I_DSI_TRANS_ZERO_REG 0x078
88 #define SUN6I_DSI_TCON_DRQ_REG 0x07c
89 #define SUN6I_DSI_TCON_DRQ_ENABLE_MODE BIT(28)
90 #define SUN6I_DSI_TCON_DRQ_SET(n) ((n) & 0x3ff)
92 #define SUN6I_DSI_PIXEL_CTL0_REG 0x080
93 #define SUN6I_DSI_PIXEL_CTL0_PD_PLUG_DISABLE BIT(16)
94 #define SUN6I_DSI_PIXEL_CTL0_FORMAT(n) ((n) & 0xf)
96 #define SUN6I_DSI_PIXEL_CTL1_REG 0x084
98 #define SUN6I_DSI_PIXEL_PH_REG 0x090
99 #define SUN6I_DSI_PIXEL_PH_ECC(n) (((n) & 0xff) << 24)
100 #define SUN6I_DSI_PIXEL_PH_WC(n) (((n) & 0xffff) << 8)
101 #define SUN6I_DSI_PIXEL_PH_VC(n) (((n) & 3) << 6)
102 #define SUN6I_DSI_PIXEL_PH_DT(n) ((n) & 0x3f)
104 #define SUN6I_DSI_PIXEL_PF0_REG 0x098
105 #define SUN6I_DSI_PIXEL_PF0_CRC_FORCE(n) ((n) & 0xffff)
107 #define SUN6I_DSI_PIXEL_PF1_REG 0x09c
108 #define SUN6I_DSI_PIXEL_PF1_CRC_INIT_LINEN(n) (((n) & 0xffff) << 16)
109 #define SUN6I_DSI_PIXEL_PF1_CRC_INIT_LINE0(n) ((n) & 0xffff)
111 #define SUN6I_DSI_SYNC_HSS_REG 0x0b0
113 #define SUN6I_DSI_SYNC_HSE_REG 0x0b4
115 #define SUN6I_DSI_SYNC_VSS_REG 0x0b8
117 #define SUN6I_DSI_SYNC_VSE_REG 0x0bc
119 #define SUN6I_DSI_BLK_HSA0_REG 0x0c0
121 #define SUN6I_DSI_BLK_HSA1_REG 0x0c4
122 #define SUN6I_DSI_BLK_PF(n) (((n) & 0xffff) << 16)
123 #define SUN6I_DSI_BLK_PD(n) ((n) & 0xff)
125 #define SUN6I_DSI_BLK_HBP0_REG 0x0c8
127 #define SUN6I_DSI_BLK_HBP1_REG 0x0cc
129 #define SUN6I_DSI_BLK_HFP0_REG 0x0d0
131 #define SUN6I_DSI_BLK_HFP1_REG 0x0d4
133 #define SUN6I_DSI_BLK_HBLK0_REG 0x0e0
135 #define SUN6I_DSI_BLK_HBLK1_REG 0x0e4
137 #define SUN6I_DSI_BLK_VBLK0_REG 0x0e8
139 #define SUN6I_DSI_BLK_VBLK1_REG 0x0ec
141 #define SUN6I_DSI_BURST_LINE_REG 0x0f0
142 #define SUN6I_DSI_BURST_LINE_SYNC_POINT(n) (((n) & 0xffff) << 16)
143 #define SUN6I_DSI_BURST_LINE_NUM(n) ((n) & 0xffff)
145 #define SUN6I_DSI_BURST_DRQ_REG 0x0f4
146 #define SUN6I_DSI_BURST_DRQ_EDGE1(n) (((n) & 0xffff) << 16)
147 #define SUN6I_DSI_BURST_DRQ_EDGE0(n) ((n) & 0xffff)
149 #define SUN6I_DSI_CMD_CTL_REG 0x200
150 #define SUN6I_DSI_CMD_CTL_RX_OVERFLOW BIT(26)
151 #define SUN6I_DSI_CMD_CTL_RX_FLAG BIT(25)
152 #define SUN6I_DSI_CMD_CTL_TX_FLAG BIT(9)
154 #define SUN6I_DSI_CMD_RX_REG(n) (0x240 + (n) * 0x04)
156 #define SUN6I_DSI_DEBUG_DATA_REG 0x2f8
158 #define SUN6I_DSI_CMD_TX_REG(n) (0x300 + (n) * 0x04)
160 #define SUN6I_DSI_SYNC_POINT 40
162 enum sun6i_dsi_start_inst
{
169 enum sun6i_dsi_inst_id
{
170 DSI_INST_ID_LP11
= 0,
178 DSI_INST_ID_END
= 15,
181 enum sun6i_dsi_inst_mode
{
182 DSI_INST_MODE_STOP
= 0,
185 DSI_INST_MODE_ESCAPE
,
186 DSI_INST_MODE_HSCEXIT
,
190 enum sun6i_dsi_inst_escape
{
191 DSI_INST_ESCA_LPDT
= 0,
201 enum sun6i_dsi_inst_packet
{
202 DSI_INST_PACK_PIXEL
= 0,
203 DSI_INST_PACK_COMMAND
,
206 static const u32 sun6i_dsi_ecc_array
[] = {
207 [0] = (BIT(0) | BIT(1) | BIT(2) | BIT(4) | BIT(5) | BIT(7) | BIT(10) |
208 BIT(11) | BIT(13) | BIT(16) | BIT(20) | BIT(21) | BIT(22) |
210 [1] = (BIT(0) | BIT(1) | BIT(3) | BIT(4) | BIT(6) | BIT(8) | BIT(10) |
211 BIT(12) | BIT(14) | BIT(17) | BIT(20) | BIT(21) | BIT(22) |
213 [2] = (BIT(0) | BIT(2) | BIT(3) | BIT(5) | BIT(6) | BIT(9) | BIT(11) |
214 BIT(12) | BIT(15) | BIT(18) | BIT(20) | BIT(21) | BIT(22)),
215 [3] = (BIT(1) | BIT(2) | BIT(3) | BIT(7) | BIT(8) | BIT(9) | BIT(13) |
216 BIT(14) | BIT(15) | BIT(19) | BIT(20) | BIT(21) | BIT(23)),
217 [4] = (BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(16) |
218 BIT(17) | BIT(18) | BIT(19) | BIT(20) | BIT(22) | BIT(23)),
219 [5] = (BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) |
220 BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(21) | BIT(22) |
224 static u32
sun6i_dsi_ecc_compute(unsigned int data
)
229 for (i
= 0; i
< ARRAY_SIZE(sun6i_dsi_ecc_array
); i
++) {
230 u32 field
= sun6i_dsi_ecc_array
[i
];
235 for (j
= 0; j
< 24; j
++) {
236 if (!(BIT(j
) & field
))
240 val
= (BIT(j
) & data
) ? 1 : 0;
243 val
^= (BIT(j
) & data
) ? 1 : 0;
253 static u16
sun6i_dsi_crc_compute(u8
const *buffer
, size_t len
)
255 return crc_ccitt(0xffff, buffer
, len
);
258 static u16
sun6i_dsi_crc_repeat(u8 pd
, u8
*buffer
, size_t len
)
260 memset(buffer
, pd
, len
);
262 return sun6i_dsi_crc_compute(buffer
, len
);
265 static u32
sun6i_dsi_build_sync_pkt(u8 dt
, u8 vc
, u8 d0
, u8 d1
)
269 val
|= (vc
& 3) << 6;
270 val
|= (d0
& 0xff) << 8;
271 val
|= (d1
& 0xff) << 16;
272 val
|= sun6i_dsi_ecc_compute(val
) << 24;
277 static u32
sun6i_dsi_build_blk0_pkt(u8 vc
, u16 wc
)
279 return sun6i_dsi_build_sync_pkt(MIPI_DSI_BLANKING_PACKET
, vc
,
283 static u32
sun6i_dsi_build_blk1_pkt(u16 pd
, u8
*buffer
, size_t len
)
285 u32 val
= SUN6I_DSI_BLK_PD(pd
);
287 return val
| SUN6I_DSI_BLK_PF(sun6i_dsi_crc_repeat(pd
, buffer
, len
));
290 static void sun6i_dsi_inst_abort(struct sun6i_dsi
*dsi
)
292 regmap_update_bits(dsi
->regs
, SUN6I_DSI_BASIC_CTL0_REG
,
293 SUN6I_DSI_BASIC_CTL0_INST_ST
, 0);
296 static void sun6i_dsi_inst_commit(struct sun6i_dsi
*dsi
)
298 regmap_update_bits(dsi
->regs
, SUN6I_DSI_BASIC_CTL0_REG
,
299 SUN6I_DSI_BASIC_CTL0_INST_ST
,
300 SUN6I_DSI_BASIC_CTL0_INST_ST
);
303 static int sun6i_dsi_inst_wait_for_completion(struct sun6i_dsi
*dsi
)
307 return regmap_read_poll_timeout(dsi
->regs
, SUN6I_DSI_BASIC_CTL0_REG
,
309 !(val
& SUN6I_DSI_BASIC_CTL0_INST_ST
),
313 static void sun6i_dsi_inst_setup(struct sun6i_dsi
*dsi
,
314 enum sun6i_dsi_inst_id id
,
315 enum sun6i_dsi_inst_mode mode
,
317 enum sun6i_dsi_inst_packet packet
,
318 enum sun6i_dsi_inst_escape escape
)
320 regmap_write(dsi
->regs
, SUN6I_DSI_INST_FUNC_REG(id
),
321 SUN6I_DSI_INST_FUNC_INST_MODE(mode
) |
322 SUN6I_DSI_INST_FUNC_ESCAPE_ENTRY(escape
) |
323 SUN6I_DSI_INST_FUNC_TRANS_PACKET(packet
) |
324 (clock
? SUN6I_DSI_INST_FUNC_LANE_CEN
: 0) |
325 SUN6I_DSI_INST_FUNC_LANE_DEN(data
));
328 static void sun6i_dsi_inst_init(struct sun6i_dsi
*dsi
,
329 struct mipi_dsi_device
*device
)
331 u8 lanes_mask
= GENMASK(device
->lanes
- 1, 0);
333 sun6i_dsi_inst_setup(dsi
, DSI_INST_ID_LP11
, DSI_INST_MODE_STOP
,
334 true, lanes_mask
, 0, 0);
336 sun6i_dsi_inst_setup(dsi
, DSI_INST_ID_TBA
, DSI_INST_MODE_TBA
,
339 sun6i_dsi_inst_setup(dsi
, DSI_INST_ID_HSC
, DSI_INST_MODE_HS
,
340 true, 0, DSI_INST_PACK_PIXEL
, 0);
342 sun6i_dsi_inst_setup(dsi
, DSI_INST_ID_HSD
, DSI_INST_MODE_HS
,
343 false, lanes_mask
, DSI_INST_PACK_PIXEL
, 0);
345 sun6i_dsi_inst_setup(dsi
, DSI_INST_ID_LPDT
, DSI_INST_MODE_ESCAPE
,
346 false, 1, DSI_INST_PACK_COMMAND
,
349 sun6i_dsi_inst_setup(dsi
, DSI_INST_ID_HSCEXIT
, DSI_INST_MODE_HSCEXIT
,
352 sun6i_dsi_inst_setup(dsi
, DSI_INST_ID_NOP
, DSI_INST_MODE_STOP
,
353 false, lanes_mask
, 0, 0);
355 sun6i_dsi_inst_setup(dsi
, DSI_INST_ID_DLY
, DSI_INST_MODE_NOP
,
356 true, lanes_mask
, 0, 0);
358 regmap_write(dsi
->regs
, SUN6I_DSI_INST_JUMP_CFG_REG(0),
359 SUN6I_DSI_INST_JUMP_CFG_POINT(DSI_INST_ID_NOP
) |
360 SUN6I_DSI_INST_JUMP_CFG_TO(DSI_INST_ID_HSCEXIT
) |
361 SUN6I_DSI_INST_JUMP_CFG_NUM(1));
364 static u16
sun6i_dsi_get_video_start_delay(struct sun6i_dsi
*dsi
,
365 struct drm_display_mode
*mode
)
367 u16 delay
= mode
->vtotal
- (mode
->vsync_start
- mode
->vdisplay
) + 1;
369 if (delay
> mode
->vtotal
)
370 delay
= delay
% mode
->vtotal
;
372 return max_t(u16
, delay
, 1);
375 static u16
sun6i_dsi_get_line_num(struct sun6i_dsi
*dsi
,
376 struct drm_display_mode
*mode
)
378 struct mipi_dsi_device
*device
= dsi
->device
;
379 unsigned int Bpp
= mipi_dsi_pixel_format_to_bpp(device
->format
) / 8;
381 return mode
->htotal
* Bpp
/ device
->lanes
;
384 static u16
sun6i_dsi_get_drq_edge0(struct sun6i_dsi
*dsi
,
385 struct drm_display_mode
*mode
,
386 u16 line_num
, u16 edge1
)
390 edge0
+= (mode
->hdisplay
+ 40) * SUN6I_DSI_TCON_DIV
/ 8;
392 if (edge0
> line_num
)
393 return edge0
- line_num
;
398 static u16
sun6i_dsi_get_drq_edge1(struct sun6i_dsi
*dsi
,
399 struct drm_display_mode
*mode
,
402 struct mipi_dsi_device
*device
= dsi
->device
;
403 unsigned int Bpp
= mipi_dsi_pixel_format_to_bpp(device
->format
) / 8;
404 unsigned int hbp
= mode
->htotal
- mode
->hsync_end
;
407 edge1
= SUN6I_DSI_SYNC_POINT
;
408 edge1
+= (mode
->hdisplay
+ hbp
+ 20) * Bpp
/ device
->lanes
;
410 if (edge1
> line_num
)
416 static void sun6i_dsi_setup_burst(struct sun6i_dsi
*dsi
,
417 struct drm_display_mode
*mode
)
419 struct mipi_dsi_device
*device
= dsi
->device
;
422 if (device
->mode_flags
& MIPI_DSI_MODE_VIDEO_BURST
) {
423 u16 line_num
= sun6i_dsi_get_line_num(dsi
, mode
);
426 edge1
= sun6i_dsi_get_drq_edge1(dsi
, mode
, line_num
);
427 edge0
= sun6i_dsi_get_drq_edge0(dsi
, mode
, line_num
, edge1
);
429 regmap_write(dsi
->regs
, SUN6I_DSI_BURST_DRQ_REG
,
430 SUN6I_DSI_BURST_DRQ_EDGE0(edge0
) |
431 SUN6I_DSI_BURST_DRQ_EDGE1(edge1
));
433 regmap_write(dsi
->regs
, SUN6I_DSI_BURST_LINE_REG
,
434 SUN6I_DSI_BURST_LINE_NUM(line_num
) |
435 SUN6I_DSI_BURST_LINE_SYNC_POINT(SUN6I_DSI_SYNC_POINT
));
437 val
= SUN6I_DSI_TCON_DRQ_ENABLE_MODE
;
438 } else if ((mode
->hsync_start
- mode
->hdisplay
) > 20) {
440 u16 drq
= (mode
->hsync_start
- mode
->hdisplay
) - 20;
442 drq
*= mipi_dsi_pixel_format_to_bpp(device
->format
);
445 val
= (SUN6I_DSI_TCON_DRQ_ENABLE_MODE
|
446 SUN6I_DSI_TCON_DRQ_SET(drq
));
449 regmap_write(dsi
->regs
, SUN6I_DSI_TCON_DRQ_REG
, val
);
452 static void sun6i_dsi_setup_inst_loop(struct sun6i_dsi
*dsi
,
453 struct drm_display_mode
*mode
)
455 struct mipi_dsi_device
*device
= dsi
->device
;
458 if (device
->mode_flags
& MIPI_DSI_MODE_VIDEO_BURST
) {
459 u32 hsync_porch
= (mode
->htotal
- mode
->hdisplay
) * 150;
461 delay
= (hsync_porch
/ ((mode
->clock
/ 1000) * 8));
465 regmap_write(dsi
->regs
, SUN6I_DSI_INST_LOOP_SEL_REG
,
466 2 << (4 * DSI_INST_ID_LP11
) |
467 3 << (4 * DSI_INST_ID_DLY
));
469 regmap_write(dsi
->regs
, SUN6I_DSI_INST_LOOP_NUM_REG(0),
470 SUN6I_DSI_INST_LOOP_NUM_N0(50 - 1) |
471 SUN6I_DSI_INST_LOOP_NUM_N1(delay
));
472 regmap_write(dsi
->regs
, SUN6I_DSI_INST_LOOP_NUM_REG(1),
473 SUN6I_DSI_INST_LOOP_NUM_N0(50 - 1) |
474 SUN6I_DSI_INST_LOOP_NUM_N1(delay
));
477 static void sun6i_dsi_setup_format(struct sun6i_dsi
*dsi
,
478 struct drm_display_mode
*mode
)
480 struct mipi_dsi_device
*device
= dsi
->device
;
481 u32 val
= SUN6I_DSI_PIXEL_PH_VC(device
->channel
);
486 * TODO: The format defines are only valid in video mode and
487 * change in command mode.
489 switch (device
->format
) {
490 case MIPI_DSI_FMT_RGB888
:
491 dt
= MIPI_DSI_PACKED_PIXEL_STREAM_24
;
494 case MIPI_DSI_FMT_RGB666
:
495 dt
= MIPI_DSI_PIXEL_STREAM_3BYTE_18
;
498 case MIPI_DSI_FMT_RGB666_PACKED
:
499 dt
= MIPI_DSI_PACKED_PIXEL_STREAM_18
;
502 case MIPI_DSI_FMT_RGB565
:
503 dt
= MIPI_DSI_PACKED_PIXEL_STREAM_16
;
509 val
|= SUN6I_DSI_PIXEL_PH_DT(dt
);
511 wc
= mode
->hdisplay
* mipi_dsi_pixel_format_to_bpp(device
->format
) / 8;
512 val
|= SUN6I_DSI_PIXEL_PH_WC(wc
);
513 val
|= SUN6I_DSI_PIXEL_PH_ECC(sun6i_dsi_ecc_compute(val
));
515 regmap_write(dsi
->regs
, SUN6I_DSI_PIXEL_PH_REG
, val
);
517 regmap_write(dsi
->regs
, SUN6I_DSI_PIXEL_PF0_REG
,
518 SUN6I_DSI_PIXEL_PF0_CRC_FORCE(0xffff));
520 regmap_write(dsi
->regs
, SUN6I_DSI_PIXEL_PF1_REG
,
521 SUN6I_DSI_PIXEL_PF1_CRC_INIT_LINE0(0xffff) |
522 SUN6I_DSI_PIXEL_PF1_CRC_INIT_LINEN(0xffff));
524 regmap_write(dsi
->regs
, SUN6I_DSI_PIXEL_CTL0_REG
,
525 SUN6I_DSI_PIXEL_CTL0_PD_PLUG_DISABLE
|
526 SUN6I_DSI_PIXEL_CTL0_FORMAT(fmt
));
529 static void sun6i_dsi_setup_timings(struct sun6i_dsi
*dsi
,
530 struct drm_display_mode
*mode
)
532 struct mipi_dsi_device
*device
= dsi
->device
;
533 unsigned int Bpp
= mipi_dsi_pixel_format_to_bpp(device
->format
) / 8;
534 u16 hbp
= 0, hfp
= 0, hsa
= 0, hblk
= 0, vblk
= 0;
539 /* Do all timing calculations up front to allocate buffer space */
541 if (device
->mode_flags
& MIPI_DSI_MODE_VIDEO_BURST
) {
542 hblk
= mode
->hdisplay
* Bpp
;
543 basic_ctl
= SUN6I_DSI_BASIC_CTL_VIDEO_BURST
|
544 SUN6I_DSI_BASIC_CTL_HSA_HSE_DIS
|
545 SUN6I_DSI_BASIC_CTL_HBP_DIS
;
547 if (device
->lanes
== 4)
548 basic_ctl
|= SUN6I_DSI_BASIC_CTL_TRAIL_FILL
|
549 SUN6I_DSI_BASIC_CTL_TRAIL_INV(0xc);
552 * A sync period is composed of a blanking packet (4
553 * bytes + payload + 2 bytes) and a sync event packet
554 * (4 bytes). Its minimal size is therefore 10 bytes
556 #define HSA_PACKET_OVERHEAD 10
557 hsa
= max((unsigned int)HSA_PACKET_OVERHEAD
,
558 (mode
->hsync_end
- mode
->hsync_start
) * Bpp
- HSA_PACKET_OVERHEAD
);
561 * The backporch is set using a blanking packet (4
562 * bytes + payload + 2 bytes). Its minimal size is
565 #define HBP_PACKET_OVERHEAD 6
566 hbp
= max((unsigned int)HBP_PACKET_OVERHEAD
,
567 (mode
->htotal
- mode
->hsync_end
) * Bpp
- HBP_PACKET_OVERHEAD
);
570 * The frontporch is set using a sync event (4 bytes)
571 * and two blanking packets (each one is 4 bytes +
572 * payload + 2 bytes). Its minimal size is therefore
575 #define HFP_PACKET_OVERHEAD 16
576 hfp
= max((unsigned int)HFP_PACKET_OVERHEAD
,
577 (mode
->hsync_start
- mode
->hdisplay
) * Bpp
- HFP_PACKET_OVERHEAD
);
580 * The blanking is set using a sync event (4 bytes)
581 * and a blanking packet (4 bytes + payload + 2
582 * bytes). Its minimal size is therefore 10 bytes.
584 #define HBLK_PACKET_OVERHEAD 10
585 hblk
= max((unsigned int)HBLK_PACKET_OVERHEAD
,
586 (mode
->htotal
- (mode
->hsync_end
- mode
->hsync_start
)) * Bpp
-
587 HBLK_PACKET_OVERHEAD
);
590 * And I'm not entirely sure what vblk is about. The driver in
591 * Allwinner BSP is using a rather convoluted calculation
592 * there only for 4 lanes. However, using 0 (the !4 lanes
593 * case) even with a 4 lanes screen seems to work...
598 /* How many bytes do we need to send all payloads? */
599 bytes
= max_t(size_t, max(max(hfp
, hblk
), max(hsa
, hbp
)), vblk
);
600 buffer
= kmalloc(bytes
, GFP_KERNEL
);
601 if (WARN_ON(!buffer
))
604 regmap_write(dsi
->regs
, SUN6I_DSI_BASIC_CTL_REG
, basic_ctl
);
606 regmap_write(dsi
->regs
, SUN6I_DSI_SYNC_HSS_REG
,
607 sun6i_dsi_build_sync_pkt(MIPI_DSI_H_SYNC_START
,
611 regmap_write(dsi
->regs
, SUN6I_DSI_SYNC_HSE_REG
,
612 sun6i_dsi_build_sync_pkt(MIPI_DSI_H_SYNC_END
,
616 regmap_write(dsi
->regs
, SUN6I_DSI_SYNC_VSS_REG
,
617 sun6i_dsi_build_sync_pkt(MIPI_DSI_V_SYNC_START
,
621 regmap_write(dsi
->regs
, SUN6I_DSI_SYNC_VSE_REG
,
622 sun6i_dsi_build_sync_pkt(MIPI_DSI_V_SYNC_END
,
626 regmap_write(dsi
->regs
, SUN6I_DSI_BASIC_SIZE0_REG
,
627 SUN6I_DSI_BASIC_SIZE0_VSA(mode
->vsync_end
-
629 SUN6I_DSI_BASIC_SIZE0_VBP(mode
->vtotal
-
632 regmap_write(dsi
->regs
, SUN6I_DSI_BASIC_SIZE1_REG
,
633 SUN6I_DSI_BASIC_SIZE1_VACT(mode
->vdisplay
) |
634 SUN6I_DSI_BASIC_SIZE1_VT(mode
->vtotal
));
637 regmap_write(dsi
->regs
, SUN6I_DSI_BLK_HSA0_REG
,
638 sun6i_dsi_build_blk0_pkt(device
->channel
, hsa
));
639 regmap_write(dsi
->regs
, SUN6I_DSI_BLK_HSA1_REG
,
640 sun6i_dsi_build_blk1_pkt(0, buffer
, hsa
));
643 regmap_write(dsi
->regs
, SUN6I_DSI_BLK_HBP0_REG
,
644 sun6i_dsi_build_blk0_pkt(device
->channel
, hbp
));
645 regmap_write(dsi
->regs
, SUN6I_DSI_BLK_HBP1_REG
,
646 sun6i_dsi_build_blk1_pkt(0, buffer
, hbp
));
649 regmap_write(dsi
->regs
, SUN6I_DSI_BLK_HFP0_REG
,
650 sun6i_dsi_build_blk0_pkt(device
->channel
, hfp
));
651 regmap_write(dsi
->regs
, SUN6I_DSI_BLK_HFP1_REG
,
652 sun6i_dsi_build_blk1_pkt(0, buffer
, hfp
));
655 regmap_write(dsi
->regs
, SUN6I_DSI_BLK_HBLK0_REG
,
656 sun6i_dsi_build_blk0_pkt(device
->channel
, hblk
));
657 regmap_write(dsi
->regs
, SUN6I_DSI_BLK_HBLK1_REG
,
658 sun6i_dsi_build_blk1_pkt(0, buffer
, hblk
));
661 regmap_write(dsi
->regs
, SUN6I_DSI_BLK_VBLK0_REG
,
662 sun6i_dsi_build_blk0_pkt(device
->channel
, vblk
));
663 regmap_write(dsi
->regs
, SUN6I_DSI_BLK_VBLK1_REG
,
664 sun6i_dsi_build_blk1_pkt(0, buffer
, vblk
));
669 static int sun6i_dsi_start(struct sun6i_dsi
*dsi
,
670 enum sun6i_dsi_start_inst func
)
674 regmap_write(dsi
->regs
, SUN6I_DSI_INST_JUMP_SEL_REG
,
675 DSI_INST_ID_LPDT
<< (4 * DSI_INST_ID_LP11
) |
676 DSI_INST_ID_END
<< (4 * DSI_INST_ID_LPDT
));
679 regmap_write(dsi
->regs
, SUN6I_DSI_INST_JUMP_SEL_REG
,
680 DSI_INST_ID_LPDT
<< (4 * DSI_INST_ID_LP11
) |
681 DSI_INST_ID_DLY
<< (4 * DSI_INST_ID_LPDT
) |
682 DSI_INST_ID_TBA
<< (4 * DSI_INST_ID_DLY
) |
683 DSI_INST_ID_END
<< (4 * DSI_INST_ID_TBA
));
686 regmap_write(dsi
->regs
, SUN6I_DSI_INST_JUMP_SEL_REG
,
687 DSI_INST_ID_HSC
<< (4 * DSI_INST_ID_LP11
) |
688 DSI_INST_ID_END
<< (4 * DSI_INST_ID_HSC
));
691 regmap_write(dsi
->regs
, SUN6I_DSI_INST_JUMP_SEL_REG
,
692 DSI_INST_ID_NOP
<< (4 * DSI_INST_ID_LP11
) |
693 DSI_INST_ID_HSD
<< (4 * DSI_INST_ID_NOP
) |
694 DSI_INST_ID_DLY
<< (4 * DSI_INST_ID_HSD
) |
695 DSI_INST_ID_NOP
<< (4 * DSI_INST_ID_DLY
) |
696 DSI_INST_ID_END
<< (4 * DSI_INST_ID_HSCEXIT
));
699 regmap_write(dsi
->regs
, SUN6I_DSI_INST_JUMP_SEL_REG
,
700 DSI_INST_ID_END
<< (4 * DSI_INST_ID_LP11
));
704 sun6i_dsi_inst_abort(dsi
);
705 sun6i_dsi_inst_commit(dsi
);
707 if (func
== DSI_START_HSC
)
708 regmap_write_bits(dsi
->regs
,
709 SUN6I_DSI_INST_FUNC_REG(DSI_INST_ID_LP11
),
710 SUN6I_DSI_INST_FUNC_LANE_CEN
, 0);
715 static void sun6i_dsi_encoder_enable(struct drm_encoder
*encoder
)
717 struct drm_display_mode
*mode
= &encoder
->crtc
->state
->adjusted_mode
;
718 struct sun6i_dsi
*dsi
= encoder_to_sun6i_dsi(encoder
);
719 struct mipi_dsi_device
*device
= dsi
->device
;
720 union phy_configure_opts opts
= { 0 };
721 struct phy_configure_opts_mipi_dphy
*cfg
= &opts
.mipi_dphy
;
725 DRM_DEBUG_DRIVER("Enabling DSI output\n");
727 err
= regulator_enable(dsi
->regulator
);
729 dev_warn(dsi
->dev
, "failed to enable VCC-DSI supply: %d\n", err
);
731 reset_control_deassert(dsi
->reset
);
732 clk_prepare_enable(dsi
->mod_clk
);
735 * Enable the DSI block.
737 regmap_write(dsi
->regs
, SUN6I_DSI_CTL_REG
, SUN6I_DSI_CTL_EN
);
739 regmap_write(dsi
->regs
, SUN6I_DSI_BASIC_CTL0_REG
,
740 SUN6I_DSI_BASIC_CTL0_ECC_EN
| SUN6I_DSI_BASIC_CTL0_CRC_EN
);
742 regmap_write(dsi
->regs
, SUN6I_DSI_TRANS_START_REG
, 10);
743 regmap_write(dsi
->regs
, SUN6I_DSI_TRANS_ZERO_REG
, 0);
745 sun6i_dsi_inst_init(dsi
, dsi
->device
);
747 regmap_write(dsi
->regs
, SUN6I_DSI_DEBUG_DATA_REG
, 0xff);
749 delay
= sun6i_dsi_get_video_start_delay(dsi
, mode
);
750 regmap_write(dsi
->regs
, SUN6I_DSI_BASIC_CTL1_REG
,
751 SUN6I_DSI_BASIC_CTL1_VIDEO_ST_DELAY(delay
) |
752 SUN6I_DSI_BASIC_CTL1_VIDEO_FILL
|
753 SUN6I_DSI_BASIC_CTL1_VIDEO_PRECISION
|
754 SUN6I_DSI_BASIC_CTL1_VIDEO_MODE
);
756 sun6i_dsi_setup_burst(dsi
, mode
);
757 sun6i_dsi_setup_inst_loop(dsi
, mode
);
758 sun6i_dsi_setup_format(dsi
, mode
);
759 sun6i_dsi_setup_timings(dsi
, mode
);
763 phy_mipi_dphy_get_default_config(mode
->clock
* 1000,
764 mipi_dsi_pixel_format_to_bpp(device
->format
),
767 phy_set_mode(dsi
->dphy
, PHY_MODE_MIPI_DPHY
);
768 phy_configure(dsi
->dphy
, &opts
);
769 phy_power_on(dsi
->dphy
);
772 drm_panel_prepare(dsi
->panel
);
775 * FIXME: This should be moved after the switch to HS mode.
777 * Unfortunately, once in HS mode, it seems like we're not
778 * able to send DCS commands anymore, which would prevent any
779 * panel to send any DCS command as part as their enable
780 * method, which is quite common.
782 * I haven't seen any artifact due to that sub-optimal
783 * ordering on the panels I've tested it with, so I guess this
784 * will do for now, until that IP is better understood.
787 drm_panel_enable(dsi
->panel
);
789 sun6i_dsi_start(dsi
, DSI_START_HSC
);
793 sun6i_dsi_start(dsi
, DSI_START_HSD
);
796 static void sun6i_dsi_encoder_disable(struct drm_encoder
*encoder
)
798 struct sun6i_dsi
*dsi
= encoder_to_sun6i_dsi(encoder
);
800 DRM_DEBUG_DRIVER("Disabling DSI output\n");
803 drm_panel_disable(dsi
->panel
);
804 drm_panel_unprepare(dsi
->panel
);
807 phy_power_off(dsi
->dphy
);
810 clk_disable_unprepare(dsi
->mod_clk
);
811 reset_control_assert(dsi
->reset
);
812 regulator_disable(dsi
->regulator
);
815 static int sun6i_dsi_get_modes(struct drm_connector
*connector
)
817 struct sun6i_dsi
*dsi
= connector_to_sun6i_dsi(connector
);
819 return drm_panel_get_modes(dsi
->panel
, connector
);
822 static struct drm_connector_helper_funcs sun6i_dsi_connector_helper_funcs
= {
823 .get_modes
= sun6i_dsi_get_modes
,
826 static enum drm_connector_status
827 sun6i_dsi_connector_detect(struct drm_connector
*connector
, bool force
)
829 struct sun6i_dsi
*dsi
= connector_to_sun6i_dsi(connector
);
831 return dsi
->panel
? connector_status_connected
:
832 connector_status_disconnected
;
835 static const struct drm_connector_funcs sun6i_dsi_connector_funcs
= {
836 .detect
= sun6i_dsi_connector_detect
,
837 .fill_modes
= drm_helper_probe_single_connector_modes
,
838 .destroy
= drm_connector_cleanup
,
839 .reset
= drm_atomic_helper_connector_reset
,
840 .atomic_duplicate_state
= drm_atomic_helper_connector_duplicate_state
,
841 .atomic_destroy_state
= drm_atomic_helper_connector_destroy_state
,
844 static const struct drm_encoder_helper_funcs sun6i_dsi_enc_helper_funcs
= {
845 .disable
= sun6i_dsi_encoder_disable
,
846 .enable
= sun6i_dsi_encoder_enable
,
849 static const struct drm_encoder_funcs sun6i_dsi_enc_funcs
= {
850 .destroy
= drm_encoder_cleanup
,
853 static u32
sun6i_dsi_dcs_build_pkt_hdr(struct sun6i_dsi
*dsi
,
854 const struct mipi_dsi_msg
*msg
)
858 if (msg
->type
== MIPI_DSI_DCS_LONG_WRITE
) {
859 pkt
|= ((msg
->tx_len
) & 0xffff) << 8;
860 pkt
|= (((msg
->tx_len
) >> 8) & 0xffff) << 16;
862 pkt
|= (((u8
*)msg
->tx_buf
)[0] << 8);
864 pkt
|= (((u8
*)msg
->tx_buf
)[1] << 16);
867 pkt
|= sun6i_dsi_ecc_compute(pkt
) << 24;
872 static int sun6i_dsi_dcs_write_short(struct sun6i_dsi
*dsi
,
873 const struct mipi_dsi_msg
*msg
)
875 regmap_write(dsi
->regs
, SUN6I_DSI_CMD_TX_REG(0),
876 sun6i_dsi_dcs_build_pkt_hdr(dsi
, msg
));
877 regmap_write_bits(dsi
->regs
, SUN6I_DSI_CMD_CTL_REG
,
880 sun6i_dsi_start(dsi
, DSI_START_LPTX
);
885 static int sun6i_dsi_dcs_write_long(struct sun6i_dsi
*dsi
,
886 const struct mipi_dsi_msg
*msg
)
892 regmap_write(dsi
->regs
, SUN6I_DSI_CMD_TX_REG(0),
893 sun6i_dsi_dcs_build_pkt_hdr(dsi
, msg
));
895 bounce
= kzalloc(msg
->tx_len
+ sizeof(crc
), GFP_KERNEL
);
899 memcpy(bounce
, msg
->tx_buf
, msg
->tx_len
);
902 crc
= sun6i_dsi_crc_compute(bounce
, msg
->tx_len
);
903 memcpy((u8
*)bounce
+ msg
->tx_len
, &crc
, sizeof(crc
));
906 regmap_bulk_write(dsi
->regs
, SUN6I_DSI_CMD_TX_REG(1), bounce
, len
);
907 regmap_write(dsi
->regs
, SUN6I_DSI_CMD_CTL_REG
, len
+ 4 - 1);
910 sun6i_dsi_start(dsi
, DSI_START_LPTX
);
912 ret
= sun6i_dsi_inst_wait_for_completion(dsi
);
914 sun6i_dsi_inst_abort(dsi
);
919 * TODO: There's some bits (reg 0x200, bits 8/9) that
920 * apparently can be used to check whether the data have been
921 * sent, but I couldn't get it to work reliably.
926 static int sun6i_dsi_dcs_read(struct sun6i_dsi
*dsi
,
927 const struct mipi_dsi_msg
*msg
)
933 regmap_write(dsi
->regs
, SUN6I_DSI_CMD_TX_REG(0),
934 sun6i_dsi_dcs_build_pkt_hdr(dsi
, msg
));
935 regmap_write(dsi
->regs
, SUN6I_DSI_CMD_CTL_REG
,
938 sun6i_dsi_start(dsi
, DSI_START_LPRX
);
940 ret
= sun6i_dsi_inst_wait_for_completion(dsi
);
942 sun6i_dsi_inst_abort(dsi
);
947 * TODO: There's some bits (reg 0x200, bits 24/25) that
948 * apparently can be used to check whether the data have been
949 * received, but I couldn't get it to work reliably.
951 regmap_read(dsi
->regs
, SUN6I_DSI_CMD_CTL_REG
, &val
);
952 if (val
& SUN6I_DSI_CMD_CTL_RX_OVERFLOW
)
955 regmap_read(dsi
->regs
, SUN6I_DSI_CMD_RX_REG(0), &val
);
957 if (byte0
== MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT
)
960 ((u8
*)msg
->rx_buf
)[0] = (val
>> 8);
965 static int sun6i_dsi_attach(struct mipi_dsi_host
*host
,
966 struct mipi_dsi_device
*device
)
968 struct sun6i_dsi
*dsi
= host_to_sun6i_dsi(host
);
969 struct drm_panel
*panel
= of_drm_find_panel(device
->dev
.of_node
);
972 return PTR_ERR(panel
);
973 if (!dsi
->drm
|| !dsi
->drm
->registered
)
974 return -EPROBE_DEFER
;
977 dsi
->device
= device
;
979 drm_panel_attach(dsi
->panel
, &dsi
->connector
);
980 drm_kms_helper_hotplug_event(dsi
->drm
);
982 dev_info(host
->dev
, "Attached device %s\n", device
->name
);
987 static int sun6i_dsi_detach(struct mipi_dsi_host
*host
,
988 struct mipi_dsi_device
*device
)
990 struct sun6i_dsi
*dsi
= host_to_sun6i_dsi(host
);
991 struct drm_panel
*panel
= dsi
->panel
;
996 drm_panel_detach(panel
);
997 drm_kms_helper_hotplug_event(dsi
->drm
);
1002 static ssize_t
sun6i_dsi_transfer(struct mipi_dsi_host
*host
,
1003 const struct mipi_dsi_msg
*msg
)
1005 struct sun6i_dsi
*dsi
= host_to_sun6i_dsi(host
);
1008 ret
= sun6i_dsi_inst_wait_for_completion(dsi
);
1010 sun6i_dsi_inst_abort(dsi
);
1012 regmap_write(dsi
->regs
, SUN6I_DSI_CMD_CTL_REG
,
1013 SUN6I_DSI_CMD_CTL_RX_OVERFLOW
|
1014 SUN6I_DSI_CMD_CTL_RX_FLAG
|
1015 SUN6I_DSI_CMD_CTL_TX_FLAG
);
1017 switch (msg
->type
) {
1018 case MIPI_DSI_DCS_SHORT_WRITE
:
1019 case MIPI_DSI_DCS_SHORT_WRITE_PARAM
:
1020 case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM
:
1021 ret
= sun6i_dsi_dcs_write_short(dsi
, msg
);
1024 case MIPI_DSI_DCS_LONG_WRITE
:
1025 ret
= sun6i_dsi_dcs_write_long(dsi
, msg
);
1028 case MIPI_DSI_DCS_READ
:
1029 if (msg
->rx_len
== 1) {
1030 ret
= sun6i_dsi_dcs_read(dsi
, msg
);
1033 /* Else, fall through */
1042 static const struct mipi_dsi_host_ops sun6i_dsi_host_ops
= {
1043 .attach
= sun6i_dsi_attach
,
1044 .detach
= sun6i_dsi_detach
,
1045 .transfer
= sun6i_dsi_transfer
,
1048 static const struct regmap_config sun6i_dsi_regmap_config
= {
1052 .max_register
= SUN6I_DSI_CMD_TX_REG(255),
1056 static int sun6i_dsi_bind(struct device
*dev
, struct device
*master
,
1059 struct drm_device
*drm
= data
;
1060 struct sun6i_dsi
*dsi
= dev_get_drvdata(dev
);
1063 drm_encoder_helper_add(&dsi
->encoder
,
1064 &sun6i_dsi_enc_helper_funcs
);
1065 ret
= drm_encoder_init(drm
,
1067 &sun6i_dsi_enc_funcs
,
1068 DRM_MODE_ENCODER_DSI
,
1071 dev_err(dsi
->dev
, "Couldn't initialise the DSI encoder\n");
1074 dsi
->encoder
.possible_crtcs
= BIT(0);
1076 drm_connector_helper_add(&dsi
->connector
,
1077 &sun6i_dsi_connector_helper_funcs
);
1078 ret
= drm_connector_init(drm
, &dsi
->connector
,
1079 &sun6i_dsi_connector_funcs
,
1080 DRM_MODE_CONNECTOR_DSI
);
1083 "Couldn't initialise the DSI connector\n");
1084 goto err_cleanup_connector
;
1087 drm_connector_attach_encoder(&dsi
->connector
, &dsi
->encoder
);
1093 err_cleanup_connector
:
1094 drm_encoder_cleanup(&dsi
->encoder
);
1098 static void sun6i_dsi_unbind(struct device
*dev
, struct device
*master
,
1101 struct sun6i_dsi
*dsi
= dev_get_drvdata(dev
);
1106 static const struct component_ops sun6i_dsi_ops
= {
1107 .bind
= sun6i_dsi_bind
,
1108 .unbind
= sun6i_dsi_unbind
,
1111 static int sun6i_dsi_probe(struct platform_device
*pdev
)
1113 struct device
*dev
= &pdev
->dev
;
1114 const char *bus_clk_name
= NULL
;
1115 struct sun6i_dsi
*dsi
;
1116 struct resource
*res
;
1120 dsi
= devm_kzalloc(dev
, sizeof(*dsi
), GFP_KERNEL
);
1123 dev_set_drvdata(dev
, dsi
);
1125 dsi
->host
.ops
= &sun6i_dsi_host_ops
;
1126 dsi
->host
.dev
= dev
;
1128 if (of_device_is_compatible(dev
->of_node
,
1129 "allwinner,sun6i-a31-mipi-dsi"))
1130 bus_clk_name
= "bus";
1132 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1133 base
= devm_ioremap_resource(dev
, res
);
1135 dev_err(dev
, "Couldn't map the DSI encoder registers\n");
1136 return PTR_ERR(base
);
1139 dsi
->regulator
= devm_regulator_get(dev
, "vcc-dsi");
1140 if (IS_ERR(dsi
->regulator
)) {
1141 dev_err(dev
, "Couldn't get VCC-DSI supply\n");
1142 return PTR_ERR(dsi
->regulator
);
1145 dsi
->reset
= devm_reset_control_get_shared(dev
, NULL
);
1146 if (IS_ERR(dsi
->reset
)) {
1147 dev_err(dev
, "Couldn't get our reset line\n");
1148 return PTR_ERR(dsi
->reset
);
1151 dsi
->regs
= devm_regmap_init_mmio(dev
, base
, &sun6i_dsi_regmap_config
);
1152 if (IS_ERR(dsi
->regs
)) {
1153 dev_err(dev
, "Couldn't init regmap\n");
1154 return PTR_ERR(dsi
->regs
);
1157 dsi
->bus_clk
= devm_clk_get(dev
, bus_clk_name
);
1158 if (IS_ERR(dsi
->bus_clk
)) {
1159 dev_err(dev
, "Couldn't get the DSI bus clock\n");
1160 return PTR_ERR(dsi
->bus_clk
);
1163 ret
= regmap_mmio_attach_clk(dsi
->regs
, dsi
->bus_clk
);
1167 if (of_device_is_compatible(dev
->of_node
,
1168 "allwinner,sun6i-a31-mipi-dsi")) {
1169 dsi
->mod_clk
= devm_clk_get(dev
, "mod");
1170 if (IS_ERR(dsi
->mod_clk
)) {
1171 dev_err(dev
, "Couldn't get the DSI mod clock\n");
1172 ret
= PTR_ERR(dsi
->mod_clk
);
1173 goto err_attach_clk
;
1178 * In order to operate properly, that clock seems to be always
1181 clk_set_rate_exclusive(dsi
->mod_clk
, 297000000);
1183 dsi
->dphy
= devm_phy_get(dev
, "dphy");
1184 if (IS_ERR(dsi
->dphy
)) {
1185 dev_err(dev
, "Couldn't get the MIPI D-PHY\n");
1186 ret
= PTR_ERR(dsi
->dphy
);
1187 goto err_unprotect_clk
;
1190 ret
= mipi_dsi_host_register(&dsi
->host
);
1192 dev_err(dev
, "Couldn't register MIPI-DSI host\n");
1193 goto err_unprotect_clk
;
1196 ret
= component_add(&pdev
->dev
, &sun6i_dsi_ops
);
1198 dev_err(dev
, "Couldn't register our component\n");
1199 goto err_remove_dsi_host
;
1204 err_remove_dsi_host
:
1205 mipi_dsi_host_unregister(&dsi
->host
);
1207 clk_rate_exclusive_put(dsi
->mod_clk
);
1209 if (!IS_ERR(dsi
->bus_clk
))
1210 regmap_mmio_detach_clk(dsi
->regs
);
1214 static int sun6i_dsi_remove(struct platform_device
*pdev
)
1216 struct device
*dev
= &pdev
->dev
;
1217 struct sun6i_dsi
*dsi
= dev_get_drvdata(dev
);
1219 component_del(&pdev
->dev
, &sun6i_dsi_ops
);
1220 mipi_dsi_host_unregister(&dsi
->host
);
1221 clk_rate_exclusive_put(dsi
->mod_clk
);
1223 if (!IS_ERR(dsi
->bus_clk
))
1224 regmap_mmio_detach_clk(dsi
->regs
);
1229 static const struct of_device_id sun6i_dsi_of_table
[] = {
1230 { .compatible
= "allwinner,sun6i-a31-mipi-dsi" },
1231 { .compatible
= "allwinner,sun50i-a64-mipi-dsi" },
1234 MODULE_DEVICE_TABLE(of
, sun6i_dsi_of_table
);
1236 static struct platform_driver sun6i_dsi_platform_driver
= {
1237 .probe
= sun6i_dsi_probe
,
1238 .remove
= sun6i_dsi_remove
,
1240 .name
= "sun6i-mipi-dsi",
1241 .of_match_table
= sun6i_dsi_of_table
,
1244 module_platform_driver(sun6i_dsi_platform_driver
);
1246 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
1247 MODULE_DESCRIPTION("Allwinner A31 DSI Driver");
1248 MODULE_LICENSE("GPL");